2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "brw_vec4_gs_visitor.h"
48 #include "brw_dead_control_flow.h"
49 #include "main/uniforms.h"
50 #include "brw_fs_live_variables.h"
51 #include "glsl/nir/glsl_types.h"
52 #include "program/sampler.h"
57 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
58 const fs_reg
*src
, unsigned sources
)
60 memset(this, 0, sizeof(*this));
62 this->src
= new fs_reg
[MAX2(sources
, 3)];
63 for (unsigned i
= 0; i
< sources
; i
++)
64 this->src
[i
] = src
[i
];
66 this->opcode
= opcode
;
68 this->sources
= sources
;
69 this->exec_size
= exec_size
;
71 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
73 assert(this->exec_size
!= 0);
75 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
77 /* This will be the case for almost all instructions. */
84 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
88 this->regs_written
= 0;
92 unreachable("Invalid destination register file");
95 this->writes_accumulator
= false;
100 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
103 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
105 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
108 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
110 init(opcode
, exec_size
, dst
, NULL
, 0);
113 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
116 const fs_reg src
[1] = { src0
};
117 init(opcode
, exec_size
, dst
, src
, 1);
120 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
121 const fs_reg
&src0
, const fs_reg
&src1
)
123 const fs_reg src
[2] = { src0
, src1
};
124 init(opcode
, exec_size
, dst
, src
, 2);
127 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
128 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
130 const fs_reg src
[3] = { src0
, src1
, src2
};
131 init(opcode
, exec_size
, dst
, src
, 3);
134 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
135 const fs_reg src
[], unsigned sources
)
137 init(opcode
, exec_width
, dst
, src
, sources
);
140 fs_inst::fs_inst(const fs_inst
&that
)
142 memcpy(this, &that
, sizeof(that
));
144 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
146 for (unsigned i
= 0; i
< that
.sources
; i
++)
147 this->src
[i
] = that
.src
[i
];
156 fs_inst::resize_sources(uint8_t num_sources
)
158 if (this->sources
!= num_sources
) {
159 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
161 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
162 src
[i
] = this->src
[i
];
166 this->sources
= num_sources
;
171 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
173 const fs_reg
&surf_index
,
174 const fs_reg
&varying_offset
,
175 uint32_t const_offset
)
177 /* We have our constant surface use a pitch of 4 bytes, so our index can
178 * be any component of a vector, and then we load 4 contiguous
179 * components starting from that.
181 * We break down the const_offset to a portion added to the variable
182 * offset and a portion done using reg_offset, which means that if you
183 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
184 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
185 * CSE can later notice that those loads are all the same and eliminate
186 * the redundant ones.
188 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
189 bld
.ADD(vec4_offset
, varying_offset
, fs_reg(const_offset
& ~3));
192 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
193 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
194 * u, v, r) as parameters, or we can just use the SIMD16 message
195 * consisting of (header, u). We choose the second, at the cost of a
196 * longer return length.
202 if (devinfo
->gen
>= 7)
203 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
205 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
207 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
208 fs_reg vec4_result
= fs_reg(VGRF
, alloc
.allocate(regs_written
), dst
.type
);
209 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
210 inst
->regs_written
= regs_written
;
212 if (devinfo
->gen
< 7) {
213 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
);
214 inst
->header_size
= 1;
215 if (devinfo
->gen
== 4)
218 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
221 bld
.MOV(dst
, offset(vec4_result
, bld
, (const_offset
& 3) * scale
));
225 * A helper for MOV generation for fixing up broken hardware SEND dependency
229 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
231 /* The caller always wants uncompressed to emit the minimal extra
232 * dependencies, and to avoid having to deal with aligning its regs to 2.
234 const fs_builder ubld
= bld
.annotate("send dependency resolve")
237 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
241 fs_inst::equals(fs_inst
*inst
) const
243 return (opcode
== inst
->opcode
&&
244 dst
.equals(inst
->dst
) &&
245 src
[0].equals(inst
->src
[0]) &&
246 src
[1].equals(inst
->src
[1]) &&
247 src
[2].equals(inst
->src
[2]) &&
248 saturate
== inst
->saturate
&&
249 predicate
== inst
->predicate
&&
250 conditional_mod
== inst
->conditional_mod
&&
251 mlen
== inst
->mlen
&&
252 base_mrf
== inst
->base_mrf
&&
253 target
== inst
->target
&&
255 header_size
== inst
->header_size
&&
256 shadow_compare
== inst
->shadow_compare
&&
257 exec_size
== inst
->exec_size
&&
258 offset
== inst
->offset
);
262 fs_inst::overwrites_reg(const fs_reg
®
) const
264 return reg
.in_range(dst
, regs_written
);
268 fs_inst::is_send_from_grf() const
271 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
272 case SHADER_OPCODE_SHADER_TIME_ADD
:
273 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
274 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
275 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
276 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
277 case SHADER_OPCODE_UNTYPED_ATOMIC
:
278 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
279 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
280 case SHADER_OPCODE_TYPED_ATOMIC
:
281 case SHADER_OPCODE_TYPED_SURFACE_READ
:
282 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
283 case SHADER_OPCODE_URB_WRITE_SIMD8
:
284 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
285 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
286 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
287 case SHADER_OPCODE_URB_READ_SIMD8
:
289 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
290 return src
[1].file
== VGRF
;
291 case FS_OPCODE_FB_WRITE
:
292 return src
[0].file
== VGRF
;
295 return src
[0].file
== VGRF
;
302 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
304 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
307 fs_reg reg
= this->src
[0];
308 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
311 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
314 for (int i
= 0; i
< this->sources
; i
++) {
315 reg
.type
= this->src
[i
].type
;
316 if (!this->src
[i
].equals(reg
))
319 if (i
< this->header_size
) {
322 reg
.reg_offset
+= this->exec_size
/ 8;
330 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
332 if (devinfo
->gen
== 6 && is_math())
335 if (is_send_from_grf())
338 if (!backend_instruction::can_do_source_mods())
345 fs_inst::can_change_types() const
347 return dst
.type
== src
[0].type
&&
348 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
349 (opcode
== BRW_OPCODE_MOV
||
350 (opcode
== BRW_OPCODE_SEL
&&
351 dst
.type
== src
[1].type
&&
352 predicate
!= BRW_PREDICATE_NONE
&&
353 !src
[1].abs
&& !src
[1].negate
));
357 fs_inst::has_side_effects() const
359 return this->eot
|| backend_instruction::has_side_effects();
365 memset(this, 0, sizeof(*this));
369 /** Generic unset register constructor. */
373 this->file
= BAD_FILE
;
376 /** Immediate value constructor. */
377 fs_reg::fs_reg(float f
)
381 this->type
= BRW_REGISTER_TYPE_F
;
386 /** Immediate value constructor. */
387 fs_reg::fs_reg(int32_t i
)
391 this->type
= BRW_REGISTER_TYPE_D
;
396 /** Immediate value constructor. */
397 fs_reg::fs_reg(uint32_t u
)
401 this->type
= BRW_REGISTER_TYPE_UD
;
406 /** Vector float immediate value constructor. */
407 fs_reg::fs_reg(uint8_t vf
[4])
411 this->type
= BRW_REGISTER_TYPE_VF
;
412 memcpy(&this->ud
, vf
, sizeof(unsigned));
415 /** Vector float immediate value constructor. */
416 fs_reg::fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
420 this->type
= BRW_REGISTER_TYPE_VF
;
421 this->ud
= (vf0
<< 0) | (vf1
<< 8) | (vf2
<< 16) | (vf3
<< 24);
424 fs_reg::fs_reg(struct brw_reg reg
) :
427 this->reg_offset
= 0;
428 this->subreg_offset
= 0;
429 this->reladdr
= NULL
;
431 if (this->file
== IMM
&&
432 (this->type
!= BRW_REGISTER_TYPE_V
&&
433 this->type
!= BRW_REGISTER_TYPE_UV
&&
434 this->type
!= BRW_REGISTER_TYPE_VF
)) {
440 fs_reg::equals(const fs_reg
&r
) const
442 return (memcmp((brw_reg
*)this, (brw_reg
*)&r
, sizeof(brw_reg
)) == 0 &&
443 reg_offset
== r
.reg_offset
&&
444 subreg_offset
== r
.subreg_offset
&&
445 !reladdr
&& !r
.reladdr
&&
450 fs_reg::set_smear(unsigned subreg
)
452 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
453 subreg_offset
= subreg
* type_sz(type
);
459 fs_reg::is_contiguous() const
465 fs_reg::component_size(unsigned width
) const
467 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
470 return MAX2(width
* stride
, 1) * type_sz(type
);
474 type_size_scalar(const struct glsl_type
*type
)
476 unsigned int size
, i
;
478 switch (type
->base_type
) {
481 case GLSL_TYPE_FLOAT
:
483 return type
->components();
484 case GLSL_TYPE_ARRAY
:
485 return type_size_scalar(type
->fields
.array
) * type
->length
;
486 case GLSL_TYPE_STRUCT
:
488 for (i
= 0; i
< type
->length
; i
++) {
489 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
492 case GLSL_TYPE_SAMPLER
:
493 /* Samplers take up no register space, since they're baked in at
497 case GLSL_TYPE_ATOMIC_UINT
:
499 case GLSL_TYPE_SUBROUTINE
:
501 case GLSL_TYPE_IMAGE
:
502 return BRW_IMAGE_PARAM_SIZE
;
504 case GLSL_TYPE_ERROR
:
505 case GLSL_TYPE_INTERFACE
:
506 case GLSL_TYPE_DOUBLE
:
507 unreachable("not reached");
514 * Returns the number of scalar components needed to store type, assuming
515 * that vectors are padded out to vec4.
517 * This has the packing rules of type_size_vec4(), but counts components
518 * similar to type_size_scalar().
521 type_size_vec4_times_4(const struct glsl_type
*type
)
523 return 4 * type_size_vec4(type
);
527 * Create a MOV to read the timestamp register.
529 * The caller is responsible for emitting the MOV. The return value is
530 * the destination of the MOV, with extra parameters set.
533 fs_visitor::get_timestamp(const fs_builder
&bld
)
535 assert(devinfo
->gen
>= 7);
537 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
540 BRW_REGISTER_TYPE_UD
));
542 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
544 /* We want to read the 3 fields we care about even if it's not enabled in
547 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
553 fs_visitor::emit_shader_time_begin()
555 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
557 /* We want only the low 32 bits of the timestamp. Since it's running
558 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
559 * which is plenty of time for our purposes. It is identical across the
560 * EUs, but since it's tracking GPU core speed it will increment at a
561 * varying rate as render P-states change.
563 shader_start_time
.set_smear(0);
567 fs_visitor::emit_shader_time_end()
569 /* Insert our code just before the final SEND with EOT. */
570 exec_node
*end
= this->instructions
.get_tail();
571 assert(end
&& ((fs_inst
*) end
)->eot
);
572 const fs_builder ibld
= bld
.annotate("shader time end")
573 .exec_all().at(NULL
, end
);
575 fs_reg shader_end_time
= get_timestamp(ibld
);
577 /* We only use the low 32 bits of the timestamp - see
578 * emit_shader_time_begin()).
580 * We could also check if render P-states have changed (or anything
581 * else that might disrupt timing) by setting smear to 2 and checking if
582 * that field is != 0.
584 shader_end_time
.set_smear(0);
586 /* Check that there weren't any timestamp reset events (assuming these
587 * were the only two timestamp reads that happened).
589 fs_reg reset
= shader_end_time
;
591 set_condmod(BRW_CONDITIONAL_Z
,
592 ibld
.AND(ibld
.null_reg_ud(), reset
, fs_reg(1u)));
593 ibld
.IF(BRW_PREDICATE_NORMAL
);
595 fs_reg start
= shader_start_time
;
597 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
600 const fs_builder cbld
= ibld
.group(1, 0);
601 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
603 /* If there were no instructions between the two timestamp gets, the diff
604 * is 2 cycles. Remove that overhead, so I can forget about that when
605 * trying to determine the time taken for single instructions.
607 cbld
.ADD(diff
, diff
, fs_reg(-2u));
608 SHADER_TIME_ADD(cbld
, 0, diff
);
609 SHADER_TIME_ADD(cbld
, 1, fs_reg(1u));
610 ibld
.emit(BRW_OPCODE_ELSE
);
611 SHADER_TIME_ADD(cbld
, 2, fs_reg(1u));
612 ibld
.emit(BRW_OPCODE_ENDIF
);
616 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
617 int shader_time_subindex
,
620 int index
= shader_time_index
* 3 + shader_time_subindex
;
621 fs_reg offset
= fs_reg(index
* SHADER_TIME_STRIDE
);
624 if (dispatch_width
== 8)
625 payload
= vgrf(glsl_type::uvec2_type
);
627 payload
= vgrf(glsl_type::uint_type
);
629 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
633 fs_visitor::vfail(const char *format
, va_list va
)
642 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
643 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
645 this->fail_msg
= msg
;
648 fprintf(stderr
, "%s", msg
);
653 fs_visitor::fail(const char *format
, ...)
657 va_start(va
, format
);
663 * Mark this program as impossible to compile in SIMD16 mode.
665 * During the SIMD8 compile (which happens first), we can detect and flag
666 * things that are unsupported in SIMD16 mode, so the compiler can skip
667 * the SIMD16 compile altogether.
669 * During a SIMD16 compile (if one happens anyway), this just calls fail().
672 fs_visitor::no16(const char *msg
)
674 if (dispatch_width
== 16) {
677 simd16_unsupported
= true;
679 compiler
->shader_perf_log(log_data
,
680 "SIMD16 shader failed to compile: %s", msg
);
685 * Returns true if the instruction has a flag that means it won't
686 * update an entire destination register.
688 * For example, dead code elimination and live variable analysis want to know
689 * when a write to a variable screens off any preceding values that were in
693 fs_inst::is_partial_write() const
695 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
696 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
697 !this->dst
.is_contiguous());
701 fs_inst::components_read(unsigned i
) const
704 case FS_OPCODE_LINTERP
:
710 case FS_OPCODE_PIXEL_X
:
711 case FS_OPCODE_PIXEL_Y
:
715 case FS_OPCODE_FB_WRITE_LOGICAL
:
716 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
717 /* First/second FB write color. */
719 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
723 case SHADER_OPCODE_TEX_LOGICAL
:
724 case SHADER_OPCODE_TXD_LOGICAL
:
725 case SHADER_OPCODE_TXF_LOGICAL
:
726 case SHADER_OPCODE_TXL_LOGICAL
:
727 case SHADER_OPCODE_TXS_LOGICAL
:
728 case FS_OPCODE_TXB_LOGICAL
:
729 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
730 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
731 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
732 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
733 case SHADER_OPCODE_LOD_LOGICAL
:
734 case SHADER_OPCODE_TG4_LOGICAL
:
735 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
736 assert(src
[8].file
== IMM
&& src
[9].file
== IMM
);
737 /* Texture coordinates. */
740 /* Texture derivatives. */
741 else if ((i
== 2 || i
== 3) && opcode
== SHADER_OPCODE_TXD_LOGICAL
)
743 /* Texture offset. */
747 else if (i
== 5 && opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
752 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
753 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
754 assert(src
[3].file
== IMM
);
755 /* Surface coordinates. */
758 /* Surface operation source (ignored for reads). */
764 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
765 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
766 assert(src
[3].file
== IMM
&&
768 /* Surface coordinates. */
771 /* Surface operation source. */
777 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
778 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
779 assert(src
[3].file
== IMM
&&
781 const unsigned op
= src
[4].ud
;
782 /* Surface coordinates. */
785 /* Surface operation source. */
786 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
788 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
789 op
== BRW_AOP_PREDEC
))
801 fs_inst::regs_read(int arg
) const
804 case FS_OPCODE_FB_WRITE
:
805 case SHADER_OPCODE_URB_WRITE_SIMD8
:
806 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
807 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
808 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
809 case SHADER_OPCODE_URB_READ_SIMD8
:
810 case SHADER_OPCODE_UNTYPED_ATOMIC
:
811 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
812 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
813 case SHADER_OPCODE_TYPED_ATOMIC
:
814 case SHADER_OPCODE_TYPED_SURFACE_READ
:
815 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
816 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
821 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
822 /* The payload is actually stored in src1 */
827 case FS_OPCODE_LINTERP
:
832 case SHADER_OPCODE_LOAD_PAYLOAD
:
833 if (arg
< this->header_size
)
837 case CS_OPCODE_CS_TERMINATE
:
838 case SHADER_OPCODE_BARRIER
:
842 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
847 switch (src
[arg
].file
) {
857 return DIV_ROUND_UP(components_read(arg
) *
858 src
[arg
].component_size(exec_size
),
861 unreachable("MRF registers are not allowed as sources");
867 fs_inst::reads_flag() const
873 fs_inst::writes_flag() const
875 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
876 opcode
!= BRW_OPCODE_IF
&&
877 opcode
!= BRW_OPCODE_WHILE
)) ||
878 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
882 * Returns how many MRFs an FS opcode will write over.
884 * Note that this is not the 0 or 1 implied writes in an actual gen
885 * instruction -- the FS opcodes often generate MOVs in addition.
888 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
893 if (inst
->base_mrf
== -1)
896 switch (inst
->opcode
) {
897 case SHADER_OPCODE_RCP
:
898 case SHADER_OPCODE_RSQ
:
899 case SHADER_OPCODE_SQRT
:
900 case SHADER_OPCODE_EXP2
:
901 case SHADER_OPCODE_LOG2
:
902 case SHADER_OPCODE_SIN
:
903 case SHADER_OPCODE_COS
:
904 return 1 * dispatch_width
/ 8;
905 case SHADER_OPCODE_POW
:
906 case SHADER_OPCODE_INT_QUOTIENT
:
907 case SHADER_OPCODE_INT_REMAINDER
:
908 return 2 * dispatch_width
/ 8;
909 case SHADER_OPCODE_TEX
:
911 case SHADER_OPCODE_TXD
:
912 case SHADER_OPCODE_TXF
:
913 case SHADER_OPCODE_TXF_CMS
:
914 case SHADER_OPCODE_TXF_CMS_W
:
915 case SHADER_OPCODE_TXF_MCS
:
916 case SHADER_OPCODE_TG4
:
917 case SHADER_OPCODE_TG4_OFFSET
:
918 case SHADER_OPCODE_TXL
:
919 case SHADER_OPCODE_TXS
:
920 case SHADER_OPCODE_LOD
:
921 case SHADER_OPCODE_SAMPLEINFO
:
923 case FS_OPCODE_FB_WRITE
:
925 case FS_OPCODE_GET_BUFFER_SIZE
:
926 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
927 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
929 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
931 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
933 case SHADER_OPCODE_UNTYPED_ATOMIC
:
934 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
935 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
936 case SHADER_OPCODE_TYPED_ATOMIC
:
937 case SHADER_OPCODE_TYPED_SURFACE_READ
:
938 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
939 case SHADER_OPCODE_URB_WRITE_SIMD8
:
940 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
941 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
942 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
943 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
944 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
945 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
946 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
949 unreachable("not reached");
954 fs_visitor::vgrf(const glsl_type
*const type
)
956 int reg_width
= dispatch_width
/ 8;
957 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
958 brw_type_for_base_type(type
));
961 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
966 this->type
= BRW_REGISTER_TYPE_F
;
967 this->stride
= (file
== UNIFORM
? 0 : 1);
970 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
976 this->stride
= (file
== UNIFORM
? 0 : 1);
979 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
980 * This brings in those uniform definitions
983 fs_visitor::import_uniforms(fs_visitor
*v
)
985 this->push_constant_loc
= v
->push_constant_loc
;
986 this->pull_constant_loc
= v
->pull_constant_loc
;
987 this->uniforms
= v
->uniforms
;
988 this->param_size
= v
->param_size
;
992 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
993 bool origin_upper_left
)
995 assert(stage
== MESA_SHADER_FRAGMENT
);
996 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
997 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
999 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
1001 /* gl_FragCoord.x */
1002 if (pixel_center_integer
) {
1003 bld
.MOV(wpos
, this->pixel_x
);
1005 bld
.ADD(wpos
, this->pixel_x
, fs_reg(0.5f
));
1007 wpos
= offset(wpos
, bld
, 1);
1009 /* gl_FragCoord.y */
1010 if (!flip
&& pixel_center_integer
) {
1011 bld
.MOV(wpos
, this->pixel_y
);
1013 fs_reg pixel_y
= this->pixel_y
;
1014 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
1017 pixel_y
.negate
= true;
1018 offset
+= key
->drawable_height
- 1.0f
;
1021 bld
.ADD(wpos
, pixel_y
, fs_reg(offset
));
1023 wpos
= offset(wpos
, bld
, 1);
1025 /* gl_FragCoord.z */
1026 if (devinfo
->gen
>= 6) {
1027 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1029 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1030 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1031 interp_reg(VARYING_SLOT_POS
, 2));
1033 wpos
= offset(wpos
, bld
, 1);
1035 /* gl_FragCoord.w: Already set up in emit_interpolation */
1036 bld
.MOV(wpos
, this->wpos_w
);
1042 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1043 glsl_interp_qualifier interpolation_mode
,
1044 bool is_centroid
, bool is_sample
)
1046 brw_wm_barycentric_interp_mode barycoord_mode
;
1047 if (devinfo
->gen
>= 6) {
1049 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1050 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1052 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1053 } else if (is_sample
) {
1054 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1055 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1057 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1059 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1060 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1062 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1065 /* On Ironlake and below, there is only one interpolation mode.
1066 * Centroid interpolation doesn't mean anything on this hardware --
1067 * there is no multisampling.
1069 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1071 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1072 this->delta_xy
[barycoord_mode
], interp
);
1076 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
1077 const glsl_type
*type
,
1078 glsl_interp_qualifier interpolation_mode
,
1079 int location
, bool mod_centroid
,
1082 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
1084 assert(stage
== MESA_SHADER_FRAGMENT
);
1085 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1086 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1088 unsigned int array_elements
;
1090 if (type
->is_array()) {
1091 array_elements
= type
->arrays_of_arrays_size();
1092 if (array_elements
== 0) {
1093 fail("dereferenced array '%s' has length 0\n", name
);
1095 type
= type
->without_array();
1100 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1102 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1103 if (key
->flat_shade
&& is_gl_Color
) {
1104 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1106 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1110 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1111 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1112 if (prog_data
->urb_setup
[location
] == -1) {
1113 /* If there's no incoming setup data for this slot, don't
1114 * emit interpolation for it.
1116 attr
= offset(attr
, bld
, type
->vector_elements
);
1121 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1122 /* Constant interpolation (flat shading) case. The SF has
1123 * handed us defined values in only the constant offset
1124 * field of the setup reg.
1126 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1127 struct brw_reg interp
= interp_reg(location
, k
);
1128 interp
= suboffset(interp
, 3);
1129 interp
.type
= attr
.type
;
1130 bld
.emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1131 attr
= offset(attr
, bld
, 1);
1134 /* Smooth/noperspective interpolation case. */
1135 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1136 struct brw_reg interp
= interp_reg(location
, k
);
1137 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1138 /* Get the pixel/sample mask into f0 so that we know
1139 * which pixels are lit. Then, for each channel that is
1140 * unlit, replace the centroid data with non-centroid
1143 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1146 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1148 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1149 inst
->predicate_inverse
= true;
1150 if (devinfo
->has_pln
)
1151 inst
->no_dd_clear
= true;
1153 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1154 mod_centroid
&& !key
->persample_shading
,
1155 mod_sample
|| key
->persample_shading
);
1156 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1157 inst
->predicate_inverse
= false;
1158 if (devinfo
->has_pln
)
1159 inst
->no_dd_check
= true;
1162 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1163 mod_centroid
&& !key
->persample_shading
,
1164 mod_sample
|| key
->persample_shading
);
1166 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1167 bld
.MUL(attr
, attr
, this->pixel_w
);
1169 attr
= offset(attr
, bld
, 1);
1179 fs_visitor::emit_frontfacing_interpolation()
1181 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1183 if (devinfo
->gen
>= 6) {
1184 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1185 * a boolean result from this (~0/true or 0/false).
1187 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1188 * this task in only one instruction:
1189 * - a negation source modifier will flip the bit; and
1190 * - a W -> D type conversion will sign extend the bit into the high
1191 * word of the destination.
1193 * An ASR 15 fills the low word of the destination.
1195 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1198 bld
.ASR(*reg
, g0
, fs_reg(15));
1200 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1201 * a boolean result from this (1/true or 0/false).
1203 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1204 * the negation source modifier to flip it. Unfortunately the SHR
1205 * instruction only operates on UD (or D with an abs source modifier)
1206 * sources without negation.
1208 * Instead, use ASR (which will give ~0/true or 0/false).
1210 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1213 bld
.ASR(*reg
, g1_6
, fs_reg(31));
1220 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1222 assert(stage
== MESA_SHADER_FRAGMENT
);
1223 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1224 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1226 if (key
->compute_pos_offset
) {
1227 /* Convert int_sample_pos to floating point */
1228 bld
.MOV(dst
, int_sample_pos
);
1229 /* Scale to the range [0, 1] */
1230 bld
.MUL(dst
, dst
, fs_reg(1 / 16.0f
));
1233 /* From ARB_sample_shading specification:
1234 * "When rendering to a non-multisample buffer, or if multisample
1235 * rasterization is disabled, gl_SamplePosition will always be
1238 bld
.MOV(dst
, fs_reg(0.5f
));
1243 fs_visitor::emit_samplepos_setup()
1245 assert(devinfo
->gen
>= 6);
1247 const fs_builder abld
= bld
.annotate("compute sample position");
1248 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1250 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1251 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1253 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1254 * mode will be enabled.
1256 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1257 * R31.1:0 Position Offset X/Y for Slot[3:0]
1258 * R31.3:2 Position Offset X/Y for Slot[7:4]
1261 * The X, Y sample positions come in as bytes in thread payload. So, read
1262 * the positions using vstride=16, width=8, hstride=2.
1264 struct brw_reg sample_pos_reg
=
1265 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1266 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1268 if (dispatch_width
== 8) {
1269 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1271 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1272 abld
.half(1).MOV(half(int_sample_x
, 1),
1273 fs_reg(suboffset(sample_pos_reg
, 16)));
1275 /* Compute gl_SamplePosition.x */
1276 compute_sample_position(pos
, int_sample_x
);
1277 pos
= offset(pos
, abld
, 1);
1278 if (dispatch_width
== 8) {
1279 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1281 abld
.half(0).MOV(half(int_sample_y
, 0),
1282 fs_reg(suboffset(sample_pos_reg
, 1)));
1283 abld
.half(1).MOV(half(int_sample_y
, 1),
1284 fs_reg(suboffset(sample_pos_reg
, 17)));
1286 /* Compute gl_SamplePosition.y */
1287 compute_sample_position(pos
, int_sample_y
);
1292 fs_visitor::emit_sampleid_setup()
1294 assert(stage
== MESA_SHADER_FRAGMENT
);
1295 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1296 assert(devinfo
->gen
>= 6);
1298 const fs_builder abld
= bld
.annotate("compute sample id");
1299 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1301 if (key
->compute_sample_id
) {
1302 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1304 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1306 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1307 * 8x multisampling, subspan 0 will represent sample N (where N
1308 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1309 * 7. We can find the value of N by looking at R0.0 bits 7:6
1310 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1311 * (since samples are always delivered in pairs). That is, we
1312 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1313 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1314 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1315 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1316 * populating a temporary variable with the sequence (0, 1, 2, 3),
1317 * and then reading from it using vstride=1, width=4, hstride=0.
1318 * These computations hold good for 4x multisampling as well.
1320 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1321 * the first four slots are sample 0 of subspan 0; the next four
1322 * are sample 1 of subspan 0; the third group is sample 0 of
1323 * subspan 1, and finally sample 1 of subspan 1.
1326 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1327 * accomodate 16x MSAA.
1329 unsigned sspi_mask
= devinfo
->gen
>= 9 ? 0x1c0 : 0xc0;
1331 abld
.exec_all().group(1, 0)
1332 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1334 abld
.exec_all().group(1, 0).SHR(t1
, t1
, fs_reg(5));
1336 /* This works for both SIMD8 and SIMD16 */
1337 abld
.exec_all().group(4, 0)
1338 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1340 /* This special instruction takes care of setting vstride=1,
1341 * width=4, hstride=0 of t2 during an ADD instruction.
1343 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1345 /* As per GL_ARB_sample_shading specification:
1346 * "When rendering to a non-multisample buffer, or if multisample
1347 * rasterization is disabled, gl_SampleID will always be zero."
1349 abld
.MOV(*reg
, fs_reg(0));
1356 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1358 if (!src
.abs
&& !src
.negate
)
1361 fs_reg temp
= bld
.vgrf(src
.type
);
1368 fs_visitor::emit_discard_jump()
1370 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1372 /* For performance, after a discard, jump to the end of the
1373 * shader if all relevant channels have been discarded.
1375 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1376 discard_jump
->flag_subreg
= 1;
1378 discard_jump
->predicate
= (dispatch_width
== 8)
1379 ? BRW_PREDICATE_ALIGN1_ANY8H
1380 : BRW_PREDICATE_ALIGN1_ANY16H
;
1381 discard_jump
->predicate_inverse
= true;
1385 fs_visitor::emit_gs_thread_end()
1387 assert(stage
== MESA_SHADER_GEOMETRY
);
1389 struct brw_gs_prog_data
*gs_prog_data
=
1390 (struct brw_gs_prog_data
*) prog_data
;
1392 if (gs_compile
->control_data_header_size_bits
> 0) {
1393 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1396 const fs_builder abld
= bld
.annotate("thread end");
1399 if (gs_prog_data
->static_vertex_count
!= -1) {
1400 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1401 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1402 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1403 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1404 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1407 /* Delete now dead instructions. */
1408 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1414 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1418 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1419 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1420 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1423 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1424 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1425 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1426 sources
[1] = this->final_gs_vertex_count
;
1427 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1428 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1436 fs_visitor::assign_curb_setup()
1438 if (dispatch_width
== 8) {
1439 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1441 if (stage
== MESA_SHADER_FRAGMENT
) {
1442 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1443 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1444 } else if (stage
== MESA_SHADER_COMPUTE
) {
1445 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1446 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1448 unreachable("Unsupported shader type!");
1452 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1454 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1455 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1456 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1457 if (inst
->src
[i
].file
== UNIFORM
) {
1458 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1460 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1461 constant_nr
= push_constant_loc
[uniform_nr
];
1463 /* Section 5.11 of the OpenGL 4.1 spec says:
1464 * "Out-of-bounds reads return undefined values, which include
1465 * values from other variables of the active program or zero."
1466 * Just return the first push constant.
1471 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1474 brw_reg
.abs
= inst
->src
[i
].abs
;
1475 brw_reg
.negate
= inst
->src
[i
].negate
;
1477 assert(inst
->src
[i
].stride
== 0);
1478 inst
->src
[i
] = byte_offset(
1479 retype(brw_reg
, inst
->src
[i
].type
),
1480 inst
->src
[i
].subreg_offset
);
1485 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1486 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1490 fs_visitor::calculate_urb_setup()
1492 assert(stage
== MESA_SHADER_FRAGMENT
);
1493 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1494 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1496 memset(prog_data
->urb_setup
, -1,
1497 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1500 /* Figure out where each of the incoming setup attributes lands. */
1501 if (devinfo
->gen
>= 6) {
1502 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1503 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1504 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1505 * first 16 varying inputs, so we can put them wherever we want.
1506 * Just put them in order.
1508 * This is useful because it means that (a) inputs not used by the
1509 * fragment shader won't take up valuable register space, and (b) we
1510 * won't have to recompile the fragment shader if it gets paired with
1511 * a different vertex (or geometry) shader.
1513 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1514 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1515 BITFIELD64_BIT(i
)) {
1516 prog_data
->urb_setup
[i
] = urb_next
++;
1520 bool include_vue_header
=
1521 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1523 /* We have enough input varyings that the SF/SBE pipeline stage can't
1524 * arbitrarily rearrange them to suit our whim; we have to put them
1525 * in an order that matches the output of the previous pipeline stage
1526 * (geometry or vertex shader).
1528 struct brw_vue_map prev_stage_vue_map
;
1529 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1530 key
->input_slots_valid
,
1531 nir
->info
.separate_shader
);
1533 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1535 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1536 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1538 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1539 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1540 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1541 BITFIELD64_BIT(varying
))) {
1542 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1545 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1548 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1549 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1550 /* Point size is packed into the header, not as a general attribute */
1551 if (i
== VARYING_SLOT_PSIZ
)
1554 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1555 /* The back color slot is skipped when the front color is
1556 * also written to. In addition, some slots can be
1557 * written in the vertex shader and not read in the
1558 * fragment shader. So the register number must always be
1559 * incremented, mapped or not.
1561 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1562 prog_data
->urb_setup
[i
] = urb_next
;
1568 * It's a FS only attribute, and we did interpolation for this attribute
1569 * in SF thread. So, count it here, too.
1571 * See compile_sf_prog() for more info.
1573 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1574 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1577 prog_data
->num_varying_inputs
= urb_next
;
1581 fs_visitor::assign_urb_setup()
1583 assert(stage
== MESA_SHADER_FRAGMENT
);
1584 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1586 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1588 /* Offset all the urb_setup[] index by the actual position of the
1589 * setup regs, now that the location of the constants has been chosen.
1591 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1592 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1593 assert(inst
->src
[1].file
== FIXED_GRF
);
1594 inst
->src
[1].nr
+= urb_start
;
1597 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1598 assert(inst
->src
[0].file
== FIXED_GRF
);
1599 inst
->src
[0].nr
+= urb_start
;
1603 /* Each attribute is 4 setup channels, each of which is half a reg. */
1604 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1608 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1610 for (int i
= 0; i
< inst
->sources
; i
++) {
1611 if (inst
->src
[i
].file
== ATTR
) {
1612 int grf
= payload
.num_regs
+
1613 prog_data
->curb_read_length
+
1615 inst
->src
[i
].reg_offset
;
1617 struct brw_reg reg
=
1618 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1619 inst
->src
[i
].subreg_offset
),
1620 inst
->exec_size
* inst
->src
[i
].stride
,
1621 inst
->exec_size
, inst
->src
[i
].stride
);
1622 reg
.abs
= inst
->src
[i
].abs
;
1623 reg
.negate
= inst
->src
[i
].negate
;
1631 fs_visitor::assign_vs_urb_setup()
1633 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1635 assert(stage
== MESA_SHADER_VERTEX
);
1636 int count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1637 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1640 /* Each attribute is 4 regs. */
1641 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attributes
;
1643 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1645 /* Rewrite all ATTR file references to the hw grf that they land in. */
1646 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1647 convert_attr_sources_to_hw_regs(inst
);
1652 fs_visitor::assign_gs_urb_setup()
1654 assert(stage
== MESA_SHADER_GEOMETRY
);
1656 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1658 first_non_payload_grf
+=
1659 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1661 const unsigned first_icp_handle
= payload
.num_regs
-
1662 (vue_prog_data
->include_vue_handles
? nir
->info
.gs
.vertices_in
: 0);
1664 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1665 /* Lower URB_READ_SIMD8 opcodes into real messages. */
1666 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8
) {
1667 assert(inst
->src
[0].file
== IMM
);
1668 inst
->src
[0] = retype(brw_vec8_grf(first_icp_handle
+
1670 0), BRW_REGISTER_TYPE_UD
);
1671 /* for now, assume constant - we can do per-slot offsets later */
1672 assert(inst
->src
[1].file
== IMM
);
1673 inst
->offset
= inst
->src
[1].ud
;
1674 inst
->src
[1] = fs_reg();
1676 inst
->base_mrf
= -1;
1679 /* Rewrite all ATTR file references to GRFs. */
1680 convert_attr_sources_to_hw_regs(inst
);
1686 * Split large virtual GRFs into separate components if we can.
1688 * This is mostly duplicated with what brw_fs_vector_splitting does,
1689 * but that's really conservative because it's afraid of doing
1690 * splitting that doesn't result in real progress after the rest of
1691 * the optimization phases, which would cause infinite looping in
1692 * optimization. We can do it once here, safely. This also has the
1693 * opportunity to split interpolated values, or maybe even uniforms,
1694 * which we don't have at the IR level.
1696 * We want to split, because virtual GRFs are what we register
1697 * allocate and spill (due to contiguousness requirements for some
1698 * instructions), and they're what we naturally generate in the
1699 * codegen process, but most virtual GRFs don't actually need to be
1700 * contiguous sets of GRFs. If we split, we'll end up with reduced
1701 * live intervals and better dead code elimination and coalescing.
1704 fs_visitor::split_virtual_grfs()
1706 int num_vars
= this->alloc
.count
;
1708 /* Count the total number of registers */
1710 int vgrf_to_reg
[num_vars
];
1711 for (int i
= 0; i
< num_vars
; i
++) {
1712 vgrf_to_reg
[i
] = reg_count
;
1713 reg_count
+= alloc
.sizes
[i
];
1716 /* An array of "split points". For each register slot, this indicates
1717 * if this slot can be separated from the previous slot. Every time an
1718 * instruction uses multiple elements of a register (as a source or
1719 * destination), we mark the used slots as inseparable. Then we go
1720 * through and split the registers into the smallest pieces we can.
1722 bool split_points
[reg_count
];
1723 memset(split_points
, 0, sizeof(split_points
));
1725 /* Mark all used registers as fully splittable */
1726 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1727 if (inst
->dst
.file
== VGRF
) {
1728 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1729 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1730 split_points
[reg
+ j
] = true;
1733 for (int i
= 0; i
< inst
->sources
; i
++) {
1734 if (inst
->src
[i
].file
== VGRF
) {
1735 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1736 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1737 split_points
[reg
+ j
] = true;
1742 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1743 if (inst
->dst
.file
== VGRF
) {
1744 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1745 for (int j
= 1; j
< inst
->regs_written
; j
++)
1746 split_points
[reg
+ j
] = false;
1748 for (int i
= 0; i
< inst
->sources
; i
++) {
1749 if (inst
->src
[i
].file
== VGRF
) {
1750 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1751 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1752 split_points
[reg
+ j
] = false;
1757 int new_virtual_grf
[reg_count
];
1758 int new_reg_offset
[reg_count
];
1761 for (int i
= 0; i
< num_vars
; i
++) {
1762 /* The first one should always be 0 as a quick sanity check. */
1763 assert(split_points
[reg
] == false);
1766 new_reg_offset
[reg
] = 0;
1771 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1772 /* If this is a split point, reset the offset to 0 and allocate a
1773 * new virtual GRF for the previous offset many registers
1775 if (split_points
[reg
]) {
1776 assert(offset
<= MAX_VGRF_SIZE
);
1777 int grf
= alloc
.allocate(offset
);
1778 for (int k
= reg
- offset
; k
< reg
; k
++)
1779 new_virtual_grf
[k
] = grf
;
1782 new_reg_offset
[reg
] = offset
;
1787 /* The last one gets the original register number */
1788 assert(offset
<= MAX_VGRF_SIZE
);
1789 alloc
.sizes
[i
] = offset
;
1790 for (int k
= reg
- offset
; k
< reg
; k
++)
1791 new_virtual_grf
[k
] = i
;
1793 assert(reg
== reg_count
);
1795 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1796 if (inst
->dst
.file
== VGRF
) {
1797 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1798 inst
->dst
.nr
= new_virtual_grf
[reg
];
1799 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1800 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1802 for (int i
= 0; i
< inst
->sources
; i
++) {
1803 if (inst
->src
[i
].file
== VGRF
) {
1804 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1805 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1806 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1807 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1811 invalidate_live_intervals();
1815 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1817 * During code generation, we create tons of temporary variables, many of
1818 * which get immediately killed and are never used again. Yet, in later
1819 * optimization and analysis passes, such as compute_live_intervals, we need
1820 * to loop over all the virtual GRFs. Compacting them can save a lot of
1824 fs_visitor::compact_virtual_grfs()
1826 bool progress
= false;
1827 int remap_table
[this->alloc
.count
];
1828 memset(remap_table
, -1, sizeof(remap_table
));
1830 /* Mark which virtual GRFs are used. */
1831 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1832 if (inst
->dst
.file
== VGRF
)
1833 remap_table
[inst
->dst
.nr
] = 0;
1835 for (int i
= 0; i
< inst
->sources
; i
++) {
1836 if (inst
->src
[i
].file
== VGRF
)
1837 remap_table
[inst
->src
[i
].nr
] = 0;
1841 /* Compact the GRF arrays. */
1843 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1844 if (remap_table
[i
] == -1) {
1845 /* We just found an unused register. This means that we are
1846 * actually going to compact something.
1850 remap_table
[i
] = new_index
;
1851 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1852 invalidate_live_intervals();
1857 this->alloc
.count
= new_index
;
1859 /* Patch all the instructions to use the newly renumbered registers */
1860 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1861 if (inst
->dst
.file
== VGRF
)
1862 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1864 for (int i
= 0; i
< inst
->sources
; i
++) {
1865 if (inst
->src
[i
].file
== VGRF
)
1866 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1870 /* Patch all the references to delta_xy, since they're used in register
1871 * allocation. If they're unused, switch them to BAD_FILE so we don't
1872 * think some random VGRF is delta_xy.
1874 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1875 if (delta_xy
[i
].file
== VGRF
) {
1876 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1877 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1879 delta_xy
[i
].file
= BAD_FILE
;
1888 * Assign UNIFORM file registers to either push constants or pull constants.
1890 * We allow a fragment shader to have more than the specified minimum
1891 * maximum number of fragment shader uniform components (64). If
1892 * there are too many of these, they'd fill up all of register space.
1893 * So, this will push some of them out to the pull constant buffer and
1894 * update the program to load them. We also use pull constants for all
1895 * indirect constant loads because we don't support indirect accesses in
1899 fs_visitor::assign_constant_locations()
1901 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1902 if (dispatch_width
!= 8)
1905 unsigned int num_pull_constants
= 0;
1907 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1908 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1910 bool is_live
[uniforms
];
1911 memset(is_live
, 0, sizeof(is_live
));
1913 /* First, we walk through the instructions and do two things:
1915 * 1) Figure out which uniforms are live.
1917 * 2) Find all indirect access of uniform arrays and flag them as needing
1918 * to go into the pull constant buffer.
1920 * Note that we don't move constant-indexed accesses to arrays. No
1921 * testing has been done of the performance impact of this choice.
1923 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1924 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1925 if (inst
->src
[i
].file
!= UNIFORM
)
1928 if (inst
->src
[i
].reladdr
) {
1929 int uniform
= inst
->src
[i
].nr
;
1931 /* If this array isn't already present in the pull constant buffer,
1934 if (pull_constant_loc
[uniform
] == -1) {
1935 assert(param_size
[uniform
]);
1936 for (int j
= 0; j
< param_size
[uniform
]; j
++)
1937 pull_constant_loc
[uniform
+ j
] = num_pull_constants
++;
1940 /* Mark the the one accessed uniform as live */
1941 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1942 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1943 is_live
[constant_nr
] = true;
1948 /* Only allow 16 registers (128 uniform components) as push constants.
1950 * Just demote the end of the list. We could probably do better
1951 * here, demoting things that are rarely used in the program first.
1953 * If changing this value, note the limitation about total_regs in
1956 unsigned int max_push_components
= 16 * 8;
1957 unsigned int num_push_constants
= 0;
1959 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1961 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1962 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1963 /* This UNIFORM register is either dead, or has already been demoted
1964 * to a pull const. Mark it as no longer living in the param[] array.
1966 push_constant_loc
[i
] = -1;
1970 if (num_push_constants
< max_push_components
) {
1971 /* Retain as a push constant. Record the location in the params[]
1974 push_constant_loc
[i
] = num_push_constants
++;
1976 /* Demote to a pull constant. */
1977 push_constant_loc
[i
] = -1;
1978 pull_constant_loc
[i
] = num_pull_constants
++;
1982 stage_prog_data
->nr_params
= num_push_constants
;
1983 stage_prog_data
->nr_pull_params
= num_pull_constants
;
1985 /* Up until now, the param[] array has been indexed by reg + reg_offset
1986 * of UNIFORM registers. Move pull constants into pull_param[] and
1987 * condense param[] to only contain the uniforms we chose to push.
1989 * NOTE: Because we are condensing the params[] array, we know that
1990 * push_constant_loc[i] <= i and we can do it in one smooth loop without
1991 * having to make a copy.
1993 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1994 const gl_constant_value
*value
= stage_prog_data
->param
[i
];
1996 if (pull_constant_loc
[i
] != -1) {
1997 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
1998 } else if (push_constant_loc
[i
] != -1) {
1999 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2005 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2006 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2009 fs_visitor::demote_pull_constants()
2011 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2012 for (int i
= 0; i
< inst
->sources
; i
++) {
2013 if (inst
->src
[i
].file
!= UNIFORM
)
2017 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2018 if (location
>= uniforms
) /* Out of bounds access */
2021 pull_index
= pull_constant_loc
[location
];
2023 if (pull_index
== -1)
2026 /* Set up the annotation tracking for new generated instructions. */
2027 const fs_builder
ibld(this, block
, inst
);
2028 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2029 fs_reg dst
= vgrf(glsl_type::float_type
);
2031 assert(inst
->src
[i
].stride
== 0);
2033 /* Generate a pull load into dst. */
2034 if (inst
->src
[i
].reladdr
) {
2035 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
2037 *inst
->src
[i
].reladdr
,
2039 inst
->src
[i
].reladdr
= NULL
;
2040 inst
->src
[i
].stride
= 1;
2042 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2043 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
2044 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2045 dst
, fs_reg(index
), offset
);
2046 inst
->src
[i
].set_smear(pull_index
& 3);
2048 brw_mark_surface_used(prog_data
, index
);
2050 /* Rewrite the instruction to use the temporary VGRF. */
2051 inst
->src
[i
].file
= VGRF
;
2052 inst
->src
[i
].nr
= dst
.nr
;
2053 inst
->src
[i
].reg_offset
= 0;
2056 invalidate_live_intervals();
2060 fs_visitor::opt_algebraic()
2062 bool progress
= false;
2064 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2065 switch (inst
->opcode
) {
2066 case BRW_OPCODE_MOV
:
2067 if (inst
->src
[0].file
!= IMM
)
2070 if (inst
->saturate
) {
2071 if (inst
->dst
.type
!= inst
->src
[0].type
)
2072 assert(!"unimplemented: saturate mixed types");
2074 if (brw_saturate_immediate(inst
->dst
.type
, &inst
->src
[0])) {
2075 inst
->saturate
= false;
2081 case BRW_OPCODE_MUL
:
2082 if (inst
->src
[1].file
!= IMM
)
2086 if (inst
->src
[1].is_one()) {
2087 inst
->opcode
= BRW_OPCODE_MOV
;
2088 inst
->src
[1] = reg_undef
;
2094 if (inst
->src
[1].is_negative_one()) {
2095 inst
->opcode
= BRW_OPCODE_MOV
;
2096 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2097 inst
->src
[1] = reg_undef
;
2103 if (inst
->src
[1].is_zero()) {
2104 inst
->opcode
= BRW_OPCODE_MOV
;
2105 inst
->src
[0] = inst
->src
[1];
2106 inst
->src
[1] = reg_undef
;
2111 if (inst
->src
[0].file
== IMM
) {
2112 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2113 inst
->opcode
= BRW_OPCODE_MOV
;
2114 inst
->src
[0].f
*= inst
->src
[1].f
;
2115 inst
->src
[1] = reg_undef
;
2120 case BRW_OPCODE_ADD
:
2121 if (inst
->src
[1].file
!= IMM
)
2125 if (inst
->src
[1].is_zero()) {
2126 inst
->opcode
= BRW_OPCODE_MOV
;
2127 inst
->src
[1] = reg_undef
;
2132 if (inst
->src
[0].file
== IMM
) {
2133 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2134 inst
->opcode
= BRW_OPCODE_MOV
;
2135 inst
->src
[0].f
+= inst
->src
[1].f
;
2136 inst
->src
[1] = reg_undef
;
2142 if (inst
->src
[0].equals(inst
->src
[1])) {
2143 inst
->opcode
= BRW_OPCODE_MOV
;
2144 inst
->src
[1] = reg_undef
;
2149 case BRW_OPCODE_LRP
:
2150 if (inst
->src
[1].equals(inst
->src
[2])) {
2151 inst
->opcode
= BRW_OPCODE_MOV
;
2152 inst
->src
[0] = inst
->src
[1];
2153 inst
->src
[1] = reg_undef
;
2154 inst
->src
[2] = reg_undef
;
2159 case BRW_OPCODE_CMP
:
2160 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2162 inst
->src
[0].negate
&&
2163 inst
->src
[1].is_zero()) {
2164 inst
->src
[0].abs
= false;
2165 inst
->src
[0].negate
= false;
2166 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2171 case BRW_OPCODE_SEL
:
2172 if (inst
->src
[0].equals(inst
->src
[1])) {
2173 inst
->opcode
= BRW_OPCODE_MOV
;
2174 inst
->src
[1] = reg_undef
;
2175 inst
->predicate
= BRW_PREDICATE_NONE
;
2176 inst
->predicate_inverse
= false;
2178 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2179 switch (inst
->conditional_mod
) {
2180 case BRW_CONDITIONAL_LE
:
2181 case BRW_CONDITIONAL_L
:
2182 switch (inst
->src
[1].type
) {
2183 case BRW_REGISTER_TYPE_F
:
2184 if (inst
->src
[1].f
>= 1.0f
) {
2185 inst
->opcode
= BRW_OPCODE_MOV
;
2186 inst
->src
[1] = reg_undef
;
2187 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2195 case BRW_CONDITIONAL_GE
:
2196 case BRW_CONDITIONAL_G
:
2197 switch (inst
->src
[1].type
) {
2198 case BRW_REGISTER_TYPE_F
:
2199 if (inst
->src
[1].f
<= 0.0f
) {
2200 inst
->opcode
= BRW_OPCODE_MOV
;
2201 inst
->src
[1] = reg_undef
;
2202 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2214 case BRW_OPCODE_MAD
:
2215 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2216 inst
->opcode
= BRW_OPCODE_MOV
;
2217 inst
->src
[1] = reg_undef
;
2218 inst
->src
[2] = reg_undef
;
2220 } else if (inst
->src
[0].is_zero()) {
2221 inst
->opcode
= BRW_OPCODE_MUL
;
2222 inst
->src
[0] = inst
->src
[2];
2223 inst
->src
[2] = reg_undef
;
2225 } else if (inst
->src
[1].is_one()) {
2226 inst
->opcode
= BRW_OPCODE_ADD
;
2227 inst
->src
[1] = inst
->src
[2];
2228 inst
->src
[2] = reg_undef
;
2230 } else if (inst
->src
[2].is_one()) {
2231 inst
->opcode
= BRW_OPCODE_ADD
;
2232 inst
->src
[2] = reg_undef
;
2234 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2235 inst
->opcode
= BRW_OPCODE_ADD
;
2236 inst
->src
[1].f
*= inst
->src
[2].f
;
2237 inst
->src
[2] = reg_undef
;
2241 case SHADER_OPCODE_RCP
: {
2242 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2243 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2244 if (inst
->src
[0].equals(prev
->dst
)) {
2245 inst
->opcode
= SHADER_OPCODE_RSQ
;
2246 inst
->src
[0] = prev
->src
[0];
2252 case SHADER_OPCODE_BROADCAST
:
2253 if (is_uniform(inst
->src
[0])) {
2254 inst
->opcode
= BRW_OPCODE_MOV
;
2256 inst
->force_writemask_all
= true;
2258 } else if (inst
->src
[1].file
== IMM
) {
2259 inst
->opcode
= BRW_OPCODE_MOV
;
2260 inst
->src
[0] = component(inst
->src
[0],
2263 inst
->force_writemask_all
= true;
2272 /* Swap if src[0] is immediate. */
2273 if (progress
&& inst
->is_commutative()) {
2274 if (inst
->src
[0].file
== IMM
) {
2275 fs_reg tmp
= inst
->src
[1];
2276 inst
->src
[1] = inst
->src
[0];
2285 * Optimize sample messages that have constant zero values for the trailing
2286 * texture coordinates. We can just reduce the message length for these
2287 * instructions instead of reserving a register for it. Trailing parameters
2288 * that aren't sent default to zero anyway. This will cause the dead code
2289 * eliminator to remove the MOV instruction that would otherwise be emitted to
2290 * set up the zero value.
2293 fs_visitor::opt_zero_samples()
2295 /* Gen4 infers the texturing opcode based on the message length so we can't
2298 if (devinfo
->gen
< 5)
2301 bool progress
= false;
2303 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2304 if (!inst
->is_tex())
2307 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2309 if (load_payload
->is_head_sentinel() ||
2310 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2313 /* We don't want to remove the message header or the first parameter.
2314 * Removing the first parameter is not allowed, see the Haswell PRM
2315 * volume 7, page 149:
2317 * "Parameter 0 is required except for the sampleinfo message, which
2318 * has no parameter 0"
2320 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2321 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2322 (inst
->exec_size
/ 8) +
2323 inst
->header_size
- 1].is_zero()) {
2324 inst
->mlen
-= inst
->exec_size
/ 8;
2330 invalidate_live_intervals();
2336 * Optimize sample messages which are followed by the final RT write.
2338 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2339 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2340 * final texturing results copied to the framebuffer write payload and modify
2341 * them to write to the framebuffer directly.
2344 fs_visitor::opt_sampler_eot()
2346 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2348 if (stage
!= MESA_SHADER_FRAGMENT
)
2351 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2354 /* FINISHME: It should be possible to implement this optimization when there
2355 * are multiple drawbuffers.
2357 if (key
->nr_color_regions
!= 1)
2360 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2361 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2362 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2363 assert(fb_write
->eot
);
2364 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2366 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2368 /* There wasn't one; nothing to do. */
2369 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2372 /* 3D Sampler » Messages » Message Format
2374 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2375 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2377 if (tex_inst
->opcode
== SHADER_OPCODE_TXS
||
2378 tex_inst
->opcode
== SHADER_OPCODE_SAMPLEINFO
||
2379 tex_inst
->opcode
== SHADER_OPCODE_LOD
||
2380 tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2381 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2384 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2385 * It's very likely to be the previous instruction.
2387 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2388 if (load_payload
->is_head_sentinel() ||
2389 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2392 assert(!tex_inst
->eot
); /* We can't get here twice */
2393 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2395 const fs_builder
ibld(this, block
, tex_inst
);
2397 tex_inst
->offset
|= fb_write
->target
<< 24;
2398 tex_inst
->eot
= true;
2399 tex_inst
->dst
= ibld
.null_reg_ud();
2400 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2402 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2403 * to create a new LOAD_PAYLOAD command with the same sources and a space
2404 * saved for the header. Using a new destination register not only makes sure
2405 * we have enough space, but it will make sure the dead code eliminator kills
2406 * the instruction that this will replace.
2408 if (tex_inst
->header_size
!= 0)
2411 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2412 load_payload
->sources
+ 1);
2413 fs_reg
*new_sources
=
2414 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2416 new_sources
[0] = fs_reg();
2417 for (int i
= 0; i
< load_payload
->sources
; i
++)
2418 new_sources
[i
+1] = load_payload
->src
[i
];
2420 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2421 * requires a lot of information about the sources to appropriately figure
2422 * out the number of registers needed to be used. Given this stage in our
2423 * optimization, we may not have the appropriate GRFs required by
2424 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2425 * manually emit the instruction.
2427 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2428 load_payload
->exec_size
,
2431 load_payload
->sources
+ 1);
2433 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2434 new_load_payload
->header_size
= 1;
2436 tex_inst
->header_size
= 1;
2437 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2438 tex_inst
->src
[0] = send_header
;
2444 fs_visitor::opt_register_renaming()
2446 bool progress
= false;
2449 int remap
[alloc
.count
];
2450 memset(remap
, -1, sizeof(int) * alloc
.count
);
2452 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2453 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2455 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2456 inst
->opcode
== BRW_OPCODE_WHILE
) {
2460 /* Rewrite instruction sources. */
2461 for (int i
= 0; i
< inst
->sources
; i
++) {
2462 if (inst
->src
[i
].file
== VGRF
&&
2463 remap
[inst
->src
[i
].nr
] != -1 &&
2464 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2465 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2470 const int dst
= inst
->dst
.nr
;
2473 inst
->dst
.file
== VGRF
&&
2474 alloc
.sizes
[inst
->dst
.nr
] == inst
->exec_size
/ 8 &&
2475 !inst
->is_partial_write()) {
2476 if (remap
[dst
] == -1) {
2479 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2480 inst
->dst
.nr
= remap
[dst
];
2483 } else if (inst
->dst
.file
== VGRF
&&
2485 remap
[dst
] != dst
) {
2486 inst
->dst
.nr
= remap
[dst
];
2492 invalidate_live_intervals();
2494 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2495 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2496 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2505 * Remove redundant or useless discard jumps.
2507 * For example, we can eliminate jumps in the following sequence:
2509 * discard-jump (redundant with the next jump)
2510 * discard-jump (useless; jumps to the next instruction)
2514 fs_visitor::opt_redundant_discard_jumps()
2516 bool progress
= false;
2518 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2520 fs_inst
*placeholder_halt
= NULL
;
2521 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2522 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2523 placeholder_halt
= inst
;
2528 if (!placeholder_halt
)
2531 /* Delete any HALTs immediately before the placeholder halt. */
2532 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2533 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2534 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2535 prev
->remove(last_bblock
);
2540 invalidate_live_intervals();
2546 fs_visitor::compute_to_mrf()
2548 bool progress
= false;
2551 /* No MRFs on Gen >= 7. */
2552 if (devinfo
->gen
>= 7)
2555 calculate_live_intervals();
2557 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2561 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2562 inst
->is_partial_write() ||
2563 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2564 inst
->dst
.type
!= inst
->src
[0].type
||
2565 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2566 !inst
->src
[0].is_contiguous() ||
2567 inst
->src
[0].subreg_offset
)
2570 /* Work out which hardware MRF registers are written by this
2573 int mrf_low
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2575 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2576 mrf_high
= mrf_low
+ 4;
2577 } else if (inst
->exec_size
== 16) {
2578 mrf_high
= mrf_low
+ 1;
2583 /* Can't compute-to-MRF this GRF if someone else was going to
2586 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2589 /* Found a move of a GRF to a MRF. Let's see if we can go
2590 * rewrite the thing that made this GRF to write into the MRF.
2592 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2593 if (scan_inst
->dst
.file
== VGRF
&&
2594 scan_inst
->dst
.nr
== inst
->src
[0].nr
) {
2595 /* Found the last thing to write our reg we want to turn
2596 * into a compute-to-MRF.
2599 /* If this one instruction didn't populate all the
2600 * channels, bail. We might be able to rewrite everything
2601 * that writes that reg, but it would require smarter
2602 * tracking to delay the rewriting until complete success.
2604 if (scan_inst
->is_partial_write())
2607 /* Things returning more than one register would need us to
2608 * understand coalescing out more than one MOV at a time.
2610 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2613 /* SEND instructions can't have MRF as a destination. */
2614 if (scan_inst
->mlen
)
2617 if (devinfo
->gen
== 6) {
2618 /* gen6 math instructions must have the destination be
2619 * GRF, so no compute-to-MRF for them.
2621 if (scan_inst
->is_math()) {
2626 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2627 /* Found the creator of our MRF's source value. */
2628 scan_inst
->dst
.file
= MRF
;
2629 scan_inst
->dst
.nr
= inst
->dst
.nr
;
2630 scan_inst
->saturate
|= inst
->saturate
;
2631 inst
->remove(block
);
2637 /* We don't handle control flow here. Most computation of
2638 * values that end up in MRFs are shortly before the MRF
2641 if (block
->start() == scan_inst
)
2644 /* You can't read from an MRF, so if someone else reads our
2645 * MRF's source GRF that we wanted to rewrite, that stops us.
2647 bool interfered
= false;
2648 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2649 if (scan_inst
->src
[i
].file
== VGRF
&&
2650 scan_inst
->src
[i
].nr
== inst
->src
[0].nr
&&
2651 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2658 if (scan_inst
->dst
.file
== MRF
) {
2659 /* If somebody else writes our MRF here, we can't
2660 * compute-to-MRF before that.
2662 int scan_mrf_low
= scan_inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2665 if (scan_inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2666 scan_mrf_high
= scan_mrf_low
+ 4;
2667 } else if (scan_inst
->exec_size
== 16) {
2668 scan_mrf_high
= scan_mrf_low
+ 1;
2670 scan_mrf_high
= scan_mrf_low
;
2673 if (mrf_low
== scan_mrf_low
||
2674 mrf_low
== scan_mrf_high
||
2675 mrf_high
== scan_mrf_low
||
2676 mrf_high
== scan_mrf_high
) {
2681 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2682 /* Found a SEND instruction, which means that there are
2683 * live values in MRFs from base_mrf to base_mrf +
2684 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2687 if (mrf_low
>= scan_inst
->base_mrf
&&
2688 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2691 if (mrf_high
>= scan_inst
->base_mrf
&&
2692 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2700 invalidate_live_intervals();
2706 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2707 * flow. We could probably do better here with some form of divergence
2711 fs_visitor::eliminate_find_live_channel()
2713 bool progress
= false;
2716 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2717 switch (inst
->opcode
) {
2723 case BRW_OPCODE_ENDIF
:
2724 case BRW_OPCODE_WHILE
:
2728 case FS_OPCODE_DISCARD_JUMP
:
2729 /* This can potentially make control flow non-uniform until the end
2734 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2736 inst
->opcode
= BRW_OPCODE_MOV
;
2737 inst
->src
[0] = fs_reg(0u);
2739 inst
->force_writemask_all
= true;
2753 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2754 * instructions to FS_OPCODE_REP_FB_WRITE.
2757 fs_visitor::emit_repclear_shader()
2759 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2761 int color_mrf
= base_mrf
+ 2;
2763 fs_inst
*mov
= bld
.exec_all().group(4, 0)
2764 .MOV(brw_message_reg(color_mrf
),
2765 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2768 if (key
->nr_color_regions
== 1) {
2769 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2770 write
->saturate
= key
->clamp_fragment_color
;
2771 write
->base_mrf
= color_mrf
;
2773 write
->header_size
= 0;
2776 assume(key
->nr_color_regions
> 0);
2777 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2778 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2779 write
->saturate
= key
->clamp_fragment_color
;
2780 write
->base_mrf
= base_mrf
;
2782 write
->header_size
= 2;
2790 assign_constant_locations();
2791 assign_curb_setup();
2793 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2794 assert(mov
->src
[0].file
== FIXED_GRF
);
2795 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2799 * Walks through basic blocks, looking for repeated MRF writes and
2800 * removing the later ones.
2803 fs_visitor::remove_duplicate_mrf_writes()
2805 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2806 bool progress
= false;
2808 /* Need to update the MRF tracking for compressed instructions. */
2809 if (dispatch_width
== 16)
2812 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2814 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2815 if (inst
->is_control_flow()) {
2816 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2819 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2820 inst
->dst
.file
== MRF
) {
2821 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
2822 if (prev_inst
&& inst
->equals(prev_inst
)) {
2823 inst
->remove(block
);
2829 /* Clear out the last-write records for MRFs that were overwritten. */
2830 if (inst
->dst
.file
== MRF
) {
2831 last_mrf_move
[inst
->dst
.nr
] = NULL
;
2834 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2835 /* Found a SEND instruction, which will include two or fewer
2836 * implied MRF writes. We could do better here.
2838 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2839 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2843 /* Clear out any MRF move records whose sources got overwritten. */
2844 if (inst
->dst
.file
== VGRF
) {
2845 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2846 if (last_mrf_move
[i
] &&
2847 last_mrf_move
[i
]->src
[0].nr
== inst
->dst
.nr
) {
2848 last_mrf_move
[i
] = NULL
;
2853 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2854 inst
->dst
.file
== MRF
&&
2855 inst
->src
[0].file
== VGRF
&&
2856 !inst
->is_partial_write()) {
2857 last_mrf_move
[inst
->dst
.nr
] = inst
;
2862 invalidate_live_intervals();
2868 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2870 /* Clear the flag for registers that actually got read (as expected). */
2871 for (int i
= 0; i
< inst
->sources
; i
++) {
2873 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
2874 grf
= inst
->src
[i
].nr
;
2879 if (grf
>= first_grf
&&
2880 grf
< first_grf
+ grf_len
) {
2881 deps
[grf
- first_grf
] = false;
2882 if (inst
->exec_size
== 16)
2883 deps
[grf
- first_grf
+ 1] = false;
2889 * Implements this workaround for the original 965:
2891 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2892 * check for post destination dependencies on this instruction, software
2893 * must ensure that there is no destination hazard for the case of ‘write
2894 * followed by a posted write’ shown in the following example.
2897 * 2. send r3.xy <rest of send instruction>
2900 * Due to no post-destination dependency check on the ‘send’, the above
2901 * code sequence could have two instructions (1 and 2) in flight at the
2902 * same time that both consider ‘r3’ as the target of their final writes.
2905 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2908 int write_len
= inst
->regs_written
;
2909 int first_write_grf
= inst
->dst
.nr
;
2910 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2911 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2913 memset(needs_dep
, false, sizeof(needs_dep
));
2914 memset(needs_dep
, true, write_len
);
2916 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2918 /* Walk backwards looking for writes to registers we're writing which
2919 * aren't read since being written. If we hit the start of the program,
2920 * we assume that there are no outstanding dependencies on entry to the
2923 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2924 /* If we hit control flow, assume that there *are* outstanding
2925 * dependencies, and force their cleanup before our instruction.
2927 if (block
->start() == scan_inst
) {
2928 for (int i
= 0; i
< write_len
; i
++) {
2930 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
2931 first_write_grf
+ i
);
2936 /* We insert our reads as late as possible on the assumption that any
2937 * instruction but a MOV that might have left us an outstanding
2938 * dependency has more latency than a MOV.
2940 if (scan_inst
->dst
.file
== VGRF
) {
2941 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2942 int reg
= scan_inst
->dst
.nr
+ i
;
2944 if (reg
>= first_write_grf
&&
2945 reg
< first_write_grf
+ write_len
&&
2946 needs_dep
[reg
- first_write_grf
]) {
2947 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
2948 needs_dep
[reg
- first_write_grf
] = false;
2949 if (scan_inst
->exec_size
== 16)
2950 needs_dep
[reg
- first_write_grf
+ 1] = false;
2955 /* Clear the flag for registers that actually got read (as expected). */
2956 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2958 /* Continue the loop only if we haven't resolved all the dependencies */
2960 for (i
= 0; i
< write_len
; i
++) {
2970 * Implements this workaround for the original 965:
2972 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2973 * used as a destination register until after it has been sourced by an
2974 * instruction with a different destination register.
2977 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
2979 int write_len
= inst
->regs_written
;
2980 int first_write_grf
= inst
->dst
.nr
;
2981 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2982 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2984 memset(needs_dep
, false, sizeof(needs_dep
));
2985 memset(needs_dep
, true, write_len
);
2986 /* Walk forwards looking for writes to registers we're writing which aren't
2987 * read before being written.
2989 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
2990 /* If we hit control flow, force resolve all remaining dependencies. */
2991 if (block
->end() == scan_inst
) {
2992 for (int i
= 0; i
< write_len
; i
++) {
2994 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
2995 first_write_grf
+ i
);
3000 /* Clear the flag for registers that actually got read (as expected). */
3001 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3003 /* We insert our reads as late as possible since they're reading the
3004 * result of a SEND, which has massive latency.
3006 if (scan_inst
->dst
.file
== VGRF
&&
3007 scan_inst
->dst
.nr
>= first_write_grf
&&
3008 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3009 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3010 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3012 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3015 /* Continue the loop only if we haven't resolved all the dependencies */
3017 for (i
= 0; i
< write_len
; i
++) {
3027 fs_visitor::insert_gen4_send_dependency_workarounds()
3029 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3032 bool progress
= false;
3034 /* Note that we're done with register allocation, so GRF fs_regs always
3035 * have a .reg_offset of 0.
3038 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3039 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3040 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3041 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3047 invalidate_live_intervals();
3051 * Turns the generic expression-style uniform pull constant load instruction
3052 * into a hardware-specific series of instructions for loading a pull
3055 * The expression style allows the CSE pass before this to optimize out
3056 * repeated loads from the same offset, and gives the pre-register-allocation
3057 * scheduling full flexibility, while the conversion to native instructions
3058 * allows the post-register-allocation scheduler the best information
3061 * Note that execution masking for setting up pull constant loads is special:
3062 * the channels that need to be written are unrelated to the current execution
3063 * mask, since a later instruction will use one of the result channels as a
3064 * source operand for all 8 or 16 of its channels.
3067 fs_visitor::lower_uniform_pull_constant_loads()
3069 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3070 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3073 if (devinfo
->gen
>= 7) {
3074 /* The offset arg before was a vec4-aligned byte offset. We need to
3075 * turn it into a dword offset.
3077 fs_reg const_offset_reg
= inst
->src
[1];
3078 assert(const_offset_reg
.file
== IMM
&&
3079 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3080 const_offset_reg
.ud
/= 4;
3082 fs_reg payload
, offset
;
3083 if (devinfo
->gen
>= 9) {
3084 /* We have to use a message header on Skylake to get SIMD4x2
3085 * mode. Reserve space for the register.
3087 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3088 offset
.reg_offset
++;
3091 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3095 /* This is actually going to be a MOV, but since only the first dword
3096 * is accessed, we have a special opcode to do just that one. Note
3097 * that this needs to be an operation that will be considered a def
3098 * by live variable analysis, or register allocation will explode.
3100 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3101 8, offset
, const_offset_reg
);
3102 setup
->force_writemask_all
= true;
3104 setup
->ir
= inst
->ir
;
3105 setup
->annotation
= inst
->annotation
;
3106 inst
->insert_before(block
, setup
);
3108 /* Similarly, this will only populate the first 4 channels of the
3109 * result register (since we only use smear values from 0-3), but we
3110 * don't tell the optimizer.
3112 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3113 inst
->src
[1] = payload
;
3114 inst
->base_mrf
= -1;
3116 invalidate_live_intervals();
3118 /* Before register allocation, we didn't tell the scheduler about the
3119 * MRF we use. We know it's safe to use this MRF because nothing
3120 * else does except for register spill/unspill, which generates and
3121 * uses its MRF within a single IR instruction.
3123 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3130 fs_visitor::lower_load_payload()
3132 bool progress
= false;
3134 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3135 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3138 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3139 assert(inst
->saturate
== false);
3140 fs_reg dst
= inst
->dst
;
3142 /* Get rid of COMPR4. We'll add it back in if we need it */
3143 if (dst
.file
== MRF
)
3144 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3146 const fs_builder
ibld(this, block
, inst
);
3147 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3149 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3150 if (inst
->src
[i
].file
!= BAD_FILE
) {
3151 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3152 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3153 hbld
.MOV(mov_dst
, mov_src
);
3155 dst
= offset(dst
, hbld
, 1);
3158 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3159 inst
->exec_size
> 8) {
3160 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3161 * a straightforward copy. Instead, the result of the
3162 * LOAD_PAYLOAD is treated as interleaved and the first four
3163 * non-header sources are unpacked as:
3174 * This is used for gen <= 5 fb writes.
3176 assert(inst
->exec_size
== 16);
3177 assert(inst
->header_size
+ 4 <= inst
->sources
);
3178 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3179 if (inst
->src
[i
].file
!= BAD_FILE
) {
3180 if (devinfo
->has_compr4
) {
3181 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3182 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3183 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3185 /* Platform doesn't have COMPR4. We have to fake it */
3186 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3187 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3189 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3196 /* The loop above only ever incremented us through the first set
3197 * of 4 registers. However, thanks to the magic of COMPR4, we
3198 * actually wrote to the first 8 registers, so we need to take
3199 * that into account now.
3203 /* The COMPR4 code took care of the first 4 sources. We'll let
3204 * the regular path handle any remaining sources. Yes, we are
3205 * modifying the instruction but we're about to delete it so
3206 * this really doesn't hurt anything.
3208 inst
->header_size
+= 4;
3211 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3212 if (inst
->src
[i
].file
!= BAD_FILE
)
3213 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3214 dst
= offset(dst
, ibld
, 1);
3217 inst
->remove(block
);
3222 invalidate_live_intervals();
3228 fs_visitor::lower_integer_multiplication()
3230 bool progress
= false;
3232 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3233 const fs_builder
ibld(this, block
, inst
);
3235 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3236 if (inst
->dst
.is_accumulator() ||
3237 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3238 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3241 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3242 * operation directly, but CHV/BXT cannot.
3244 if (devinfo
->gen
>= 8 &&
3245 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3248 if (inst
->src
[1].file
== IMM
&&
3249 inst
->src
[1].ud
< (1 << 16)) {
3250 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3251 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3254 * If multiplying by an immediate value that fits in 16-bits, do a
3255 * single MUL instruction with that value in the proper location.
3257 if (devinfo
->gen
< 7) {
3258 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3260 ibld
.MOV(imm
, inst
->src
[1]);
3261 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3263 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3266 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3267 * do 32-bit integer multiplication in one instruction, but instead
3268 * must do a sequence (which actually calculates a 64-bit result):
3270 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3271 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3272 * mov(8) g2<1>D acc0<8,8,1>D
3274 * But on Gen > 6, the ability to use second accumulator register
3275 * (acc1) for non-float data types was removed, preventing a simple
3276 * implementation in SIMD16. A 16-channel result can be calculated by
3277 * executing the three instructions twice in SIMD8, once with quarter
3278 * control of 1Q for the first eight channels and again with 2Q for
3279 * the second eight channels.
3281 * Which accumulator register is implicitly accessed (by AccWrEnable
3282 * for instance) is determined by the quarter control. Unfortunately
3283 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3284 * implicit accumulator access by an instruction with 2Q will access
3285 * acc1 regardless of whether the data type is usable in acc1.
3287 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3288 * integer data types.
3290 * Since we only want the low 32-bits of the result, we can do two
3291 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3292 * adjust the high result and add them (like the mach is doing):
3294 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3295 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3296 * shl(8) g9<1>D g8<8,8,1>D 16D
3297 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3299 * We avoid the shl instruction by realizing that we only want to add
3300 * the low 16-bits of the "high" result to the high 16-bits of the
3301 * "low" result and using proper regioning on the add:
3303 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3304 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3305 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3307 * Since it does not use the (single) accumulator register, we can
3308 * schedule multi-component multiplications much better.
3311 fs_reg orig_dst
= inst
->dst
;
3312 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3313 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3316 fs_reg low
= inst
->dst
;
3317 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3320 if (devinfo
->gen
>= 7) {
3321 fs_reg src1_0_w
= inst
->src
[1];
3322 fs_reg src1_1_w
= inst
->src
[1];
3324 if (inst
->src
[1].file
== IMM
) {
3325 src1_0_w
.ud
&= 0xffff;
3328 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3329 if (src1_0_w
.stride
!= 0) {
3330 assert(src1_0_w
.stride
== 1);
3331 src1_0_w
.stride
= 2;
3334 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3335 if (src1_1_w
.stride
!= 0) {
3336 assert(src1_1_w
.stride
== 1);
3337 src1_1_w
.stride
= 2;
3339 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3341 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3342 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3344 fs_reg src0_0_w
= inst
->src
[0];
3345 fs_reg src0_1_w
= inst
->src
[0];
3347 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3348 if (src0_0_w
.stride
!= 0) {
3349 assert(src0_0_w
.stride
== 1);
3350 src0_0_w
.stride
= 2;
3353 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3354 if (src0_1_w
.stride
!= 0) {
3355 assert(src0_1_w
.stride
== 1);
3356 src0_1_w
.stride
= 2;
3358 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3360 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3361 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3364 fs_reg dst
= inst
->dst
;
3365 dst
.type
= BRW_REGISTER_TYPE_UW
;
3366 dst
.subreg_offset
= 2;
3369 high
.type
= BRW_REGISTER_TYPE_UW
;
3372 low
.type
= BRW_REGISTER_TYPE_UW
;
3373 low
.subreg_offset
= 2;
3376 ibld
.ADD(dst
, low
, high
);
3378 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3379 set_condmod(inst
->conditional_mod
,
3380 ibld
.MOV(orig_dst
, inst
->dst
));
3384 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3385 /* Should have been lowered to 8-wide. */
3386 assert(inst
->exec_size
<= 8);
3387 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3389 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3390 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3392 if (devinfo
->gen
>= 8) {
3393 /* Until Gen8, integer multiplies read 32-bits from one source,
3394 * and 16-bits from the other, and relying on the MACH instruction
3395 * to generate the high bits of the result.
3397 * On Gen8, the multiply instruction does a full 32x32-bit
3398 * multiply, but in order to do a 64-bit multiply we can simulate
3399 * the previous behavior and then use a MACH instruction.
3401 * FINISHME: Don't use source modifiers on src1.
3403 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3404 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3405 mul
->src
[1].type
= (type_is_signed(mul
->src
[1].type
) ?
3406 BRW_REGISTER_TYPE_W
: BRW_REGISTER_TYPE_UW
);
3407 mul
->src
[1].stride
*= 2;
3409 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3410 inst
->force_sechalf
) {
3411 /* Among other things the quarter control bits influence which
3412 * accumulator register is used by the hardware for instructions
3413 * that access the accumulator implicitly (e.g. MACH). A
3414 * second-half instruction would normally map to acc1, which
3415 * doesn't exist on Gen7 and up (the hardware does emulate it for
3416 * floating-point instructions *only* by taking advantage of the
3417 * extra precision of acc0 not normally used for floating point
3420 * HSW and up are careful enough not to try to access an
3421 * accumulator register that doesn't exist, but on earlier Gen7
3422 * hardware we need to make sure that the quarter control bits are
3423 * zero to avoid non-deterministic behaviour and emit an extra MOV
3424 * to get the result masked correctly according to the current
3427 mach
->force_sechalf
= false;
3428 mach
->force_writemask_all
= true;
3429 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3430 ibld
.MOV(inst
->dst
, mach
->dst
);
3436 inst
->remove(block
);
3441 invalidate_live_intervals();
3447 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3448 fs_reg
*dst
, fs_reg color
, unsigned components
)
3450 if (key
->clamp_fragment_color
) {
3451 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3452 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3454 for (unsigned i
= 0; i
< components
; i
++)
3456 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3461 for (unsigned i
= 0; i
< components
; i
++)
3462 dst
[i
] = offset(color
, bld
, i
);
3466 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3467 const brw_wm_prog_data
*prog_data
,
3468 const brw_wm_prog_key
*key
,
3469 const fs_visitor::thread_payload
&payload
)
3471 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3472 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3473 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3474 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3475 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3476 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3477 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3478 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3479 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3480 const unsigned components
=
3481 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3483 /* We can potentially have a message length of up to 15, so we have to set
3484 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3487 int header_size
= 2, payload_header_size
;
3488 unsigned length
= 0;
3490 /* From the Sandy Bridge PRM, volume 4, page 198:
3492 * "Dispatched Pixel Enables. One bit per pixel indicating
3493 * which pixels were originally enabled when the thread was
3494 * dispatched. This field is only required for the end-of-
3495 * thread message and on all dual-source messages."
3497 if (devinfo
->gen
>= 6 &&
3498 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3499 color1
.file
== BAD_FILE
&&
3500 key
->nr_color_regions
== 1) {
3504 if (header_size
!= 0) {
3505 assert(header_size
== 2);
3506 /* Allocate 2 registers for a header */
3510 if (payload
.aa_dest_stencil_reg
) {
3511 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3512 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3513 .MOV(sources
[length
],
3514 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3518 if (prog_data
->uses_omask
) {
3519 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3520 BRW_REGISTER_TYPE_UD
);
3522 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3523 * relevant. Since it's unsigned single words one vgrf is always
3524 * 16-wide, but only the lower or higher 8 channels will be used by the
3525 * hardware when doing a SIMD8 write depending on whether we have
3526 * selected the subspans for the first or second half respectively.
3528 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3529 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3530 sample_mask
.stride
*= 2;
3532 bld
.exec_all().annotate("FB write oMask")
3533 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3534 inst
->force_sechalf
),
3539 payload_header_size
= length
;
3541 if (src0_alpha
.file
!= BAD_FILE
) {
3542 /* FIXME: This is being passed at the wrong location in the payload and
3543 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3544 * It's supposed to be immediately before oMask but there seems to be no
3545 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3546 * requires header sources to form a contiguous segment at the beginning
3547 * of the message and src0_alpha has per-channel semantics.
3549 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3553 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3556 if (color1
.file
!= BAD_FILE
) {
3557 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3561 if (src_depth
.file
!= BAD_FILE
) {
3562 sources
[length
] = src_depth
;
3566 if (dst_depth
.file
!= BAD_FILE
) {
3567 sources
[length
] = dst_depth
;
3571 if (src_stencil
.file
!= BAD_FILE
) {
3572 assert(devinfo
->gen
>= 9);
3573 assert(bld
.dispatch_width() != 16);
3575 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3576 bld
.exec_all().annotate("FB write OS")
3577 .emit(FS_OPCODE_PACK_STENCIL_REF
, sources
[length
],
3578 retype(src_stencil
, BRW_REGISTER_TYPE_UB
));
3583 if (devinfo
->gen
>= 7) {
3584 /* Send from the GRF */
3585 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3586 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3587 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3588 load
->dst
= payload
;
3590 inst
->src
[0] = payload
;
3591 inst
->resize_sources(1);
3592 inst
->base_mrf
= -1;
3594 /* Send from the MRF */
3595 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3596 sources
, length
, payload_header_size
);
3598 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3599 * will do this for us if we just give it a COMPR4 destination.
3601 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3602 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3604 inst
->resize_sources(0);
3608 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3609 inst
->mlen
= load
->regs_written
;
3610 inst
->header_size
= header_size
;
3614 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3615 const fs_reg
&coordinate
,
3616 const fs_reg
&shadow_c
,
3617 const fs_reg
&lod
, const fs_reg
&lod2
,
3618 const fs_reg
&sampler
,
3619 unsigned coord_components
,
3620 unsigned grad_components
)
3622 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3623 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3624 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3625 fs_reg msg_end
= msg_begin
;
3628 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3630 for (unsigned i
= 0; i
< coord_components
; i
++)
3631 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3632 offset(coordinate
, bld
, i
));
3634 msg_end
= offset(msg_end
, bld
, coord_components
);
3636 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3637 * require all three components to be present and zero if they are unused.
3639 if (coord_components
> 0 &&
3640 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3641 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3642 for (unsigned i
= coord_components
; i
< 3; i
++)
3643 bld
.MOV(offset(msg_end
, bld
, i
), fs_reg(0.0f
));
3645 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3648 if (op
== SHADER_OPCODE_TXD
) {
3649 /* TXD unsupported in SIMD16 mode. */
3650 assert(bld
.dispatch_width() == 8);
3652 /* the slots for u and v are always present, but r is optional */
3653 if (coord_components
< 2)
3654 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3657 * dPdx = dudx, dvdx, drdx
3658 * dPdy = dudy, dvdy, drdy
3660 * 1-arg: Does not exist.
3662 * 2-arg: dudx dvdx dudy dvdy
3663 * dPdx.x dPdx.y dPdy.x dPdy.y
3666 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3667 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3668 * m5 m6 m7 m8 m9 m10
3670 for (unsigned i
= 0; i
< grad_components
; i
++)
3671 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3673 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3675 for (unsigned i
= 0; i
< grad_components
; i
++)
3676 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3678 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3682 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3683 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3685 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3686 bld
.dispatch_width() == 16);
3688 const brw_reg_type type
=
3689 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3690 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3691 bld
.MOV(retype(msg_end
, type
), lod
);
3692 msg_end
= offset(msg_end
, bld
, 1);
3695 if (shadow_c
.file
!= BAD_FILE
) {
3696 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3697 /* There's no plain shadow compare message, so we use shadow
3698 * compare with a bias of 0.0.
3700 bld
.MOV(msg_end
, fs_reg(0.0f
));
3701 msg_end
= offset(msg_end
, bld
, 1);
3704 bld
.MOV(msg_end
, shadow_c
);
3705 msg_end
= offset(msg_end
, bld
, 1);
3709 inst
->src
[0] = reg_undef
;
3710 inst
->src
[1] = sampler
;
3711 inst
->resize_sources(2);
3712 inst
->base_mrf
= msg_begin
.nr
;
3713 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3714 inst
->header_size
= 1;
3718 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3720 const fs_reg
&shadow_c
,
3721 fs_reg lod
, fs_reg lod2
,
3722 const fs_reg
&sample_index
,
3723 const fs_reg
&sampler
,
3724 const fs_reg
&offset_value
,
3725 unsigned coord_components
,
3726 unsigned grad_components
)
3728 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3729 fs_reg msg_coords
= message
;
3730 unsigned header_size
= 0;
3732 if (offset_value
.file
!= BAD_FILE
) {
3733 /* The offsets set up by the visitor are in the m1 header, so we can't
3740 for (unsigned i
= 0; i
< coord_components
; i
++) {
3741 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3742 coordinate
= offset(coordinate
, bld
, 1);
3744 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3745 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3747 if (shadow_c
.file
!= BAD_FILE
) {
3748 fs_reg msg_shadow
= msg_lod
;
3749 bld
.MOV(msg_shadow
, shadow_c
);
3750 msg_lod
= offset(msg_shadow
, bld
, 1);
3755 case SHADER_OPCODE_TXL
:
3757 bld
.MOV(msg_lod
, lod
);
3758 msg_end
= offset(msg_lod
, bld
, 1);
3760 case SHADER_OPCODE_TXD
:
3763 * dPdx = dudx, dvdx, drdx
3764 * dPdy = dudy, dvdy, drdy
3766 * Load up these values:
3767 * - dudx dudy dvdx dvdy drdx drdy
3768 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3771 for (unsigned i
= 0; i
< grad_components
; i
++) {
3772 bld
.MOV(msg_end
, lod
);
3773 lod
= offset(lod
, bld
, 1);
3774 msg_end
= offset(msg_end
, bld
, 1);
3776 bld
.MOV(msg_end
, lod2
);
3777 lod2
= offset(lod2
, bld
, 1);
3778 msg_end
= offset(msg_end
, bld
, 1);
3781 case SHADER_OPCODE_TXS
:
3782 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3783 bld
.MOV(msg_lod
, lod
);
3784 msg_end
= offset(msg_lod
, bld
, 1);
3786 case SHADER_OPCODE_TXF
:
3787 msg_lod
= offset(msg_coords
, bld
, 3);
3788 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3789 msg_end
= offset(msg_lod
, bld
, 1);
3791 case SHADER_OPCODE_TXF_CMS
:
3792 msg_lod
= offset(msg_coords
, bld
, 3);
3794 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u));
3796 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3797 msg_end
= offset(msg_lod
, bld
, 2);
3804 inst
->src
[0] = reg_undef
;
3805 inst
->src
[1] = sampler
;
3806 inst
->resize_sources(2);
3807 inst
->base_mrf
= message
.nr
;
3808 inst
->mlen
= msg_end
.nr
- message
.nr
;
3809 inst
->header_size
= header_size
;
3811 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3812 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3816 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3818 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3821 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
3825 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3827 const fs_reg
&shadow_c
,
3828 fs_reg lod
, fs_reg lod2
,
3829 const fs_reg
&sample_index
,
3830 const fs_reg
&mcs
, const fs_reg
&sampler
,
3831 fs_reg offset_value
,
3832 unsigned coord_components
,
3833 unsigned grad_components
)
3835 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3836 int reg_width
= bld
.dispatch_width() / 8;
3837 unsigned header_size
= 0, length
= 0;
3838 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3839 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3840 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3842 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3843 offset_value
.file
!= BAD_FILE
||
3844 is_high_sampler(devinfo
, sampler
)) {
3845 /* For general texture offsets (no txf workaround), we need a header to
3846 * put them in. Note that we're only reserving space for it in the
3847 * message payload as it will be initialized implicitly by the
3850 * TG4 needs to place its channel select in the header, for interaction
3851 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3852 * larger sampler numbers we need to offset the Sampler State Pointer in
3856 sources
[0] = fs_reg();
3860 if (shadow_c
.file
!= BAD_FILE
) {
3861 bld
.MOV(sources
[length
], shadow_c
);
3865 bool coordinate_done
= false;
3867 /* The sampler can only meaningfully compute LOD for fragment shader
3868 * messages. For all other stages, we change the opcode to TXL and
3869 * hardcode the LOD to 0.
3871 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3872 op
== SHADER_OPCODE_TEX
) {
3873 op
= SHADER_OPCODE_TXL
;
3877 /* Set up the LOD info */
3880 case SHADER_OPCODE_TXL
:
3881 bld
.MOV(sources
[length
], lod
);
3884 case SHADER_OPCODE_TXD
:
3885 /* TXD should have been lowered in SIMD16 mode. */
3886 assert(bld
.dispatch_width() == 8);
3888 /* Load dPdx and the coordinate together:
3889 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3891 for (unsigned i
= 0; i
< coord_components
; i
++) {
3892 bld
.MOV(sources
[length
], coordinate
);
3893 coordinate
= offset(coordinate
, bld
, 1);
3896 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3897 * only derivatives for (u, v, r).
3899 if (i
< grad_components
) {
3900 bld
.MOV(sources
[length
], lod
);
3901 lod
= offset(lod
, bld
, 1);
3904 bld
.MOV(sources
[length
], lod2
);
3905 lod2
= offset(lod2
, bld
, 1);
3910 coordinate_done
= true;
3912 case SHADER_OPCODE_TXS
:
3913 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
3916 case SHADER_OPCODE_TXF
:
3917 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
3918 * On Gen9 they are u, v, lod, r
3920 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3921 coordinate
= offset(coordinate
, bld
, 1);
3924 if (devinfo
->gen
>= 9) {
3925 if (coord_components
>= 2) {
3926 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3927 coordinate
= offset(coordinate
, bld
, 1);
3932 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
3935 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
3936 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3937 coordinate
= offset(coordinate
, bld
, 1);
3941 coordinate_done
= true;
3943 case SHADER_OPCODE_TXF_CMS
:
3944 case SHADER_OPCODE_TXF_CMS_W
:
3945 case SHADER_OPCODE_TXF_UMS
:
3946 case SHADER_OPCODE_TXF_MCS
:
3947 if (op
== SHADER_OPCODE_TXF_UMS
||
3948 op
== SHADER_OPCODE_TXF_CMS
||
3949 op
== SHADER_OPCODE_TXF_CMS_W
) {
3950 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
3954 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
3955 /* Data from the multisample control surface. */
3956 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
3959 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
3962 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
3963 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
3966 offset(mcs
, bld
, 1));
3971 /* There is no offsetting for this message; just copy in the integer
3972 * texture coordinates.
3974 for (unsigned i
= 0; i
< coord_components
; i
++) {
3975 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3976 coordinate
= offset(coordinate
, bld
, 1);
3980 coordinate_done
= true;
3982 case SHADER_OPCODE_TG4_OFFSET
:
3983 /* gather4_po_c should have been lowered in SIMD16 mode. */
3984 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
3986 /* More crazy intermixing */
3987 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
3988 bld
.MOV(sources
[length
], coordinate
);
3989 coordinate
= offset(coordinate
, bld
, 1);
3993 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
3994 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
3995 offset_value
= offset(offset_value
, bld
, 1);
3999 if (coord_components
== 3) { /* r if present */
4000 bld
.MOV(sources
[length
], coordinate
);
4001 coordinate
= offset(coordinate
, bld
, 1);
4005 coordinate_done
= true;
4011 /* Set up the coordinate (except for cases where it was done above) */
4012 if (!coordinate_done
) {
4013 for (unsigned i
= 0; i
< coord_components
; i
++) {
4014 bld
.MOV(sources
[length
], coordinate
);
4015 coordinate
= offset(coordinate
, bld
, 1);
4022 mlen
= length
* reg_width
- header_size
;
4024 mlen
= length
* reg_width
;
4026 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4027 BRW_REGISTER_TYPE_F
);
4028 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4030 /* Generate the SEND. */
4032 inst
->src
[0] = src_payload
;
4033 inst
->src
[1] = sampler
;
4034 inst
->resize_sources(2);
4035 inst
->base_mrf
= -1;
4037 inst
->header_size
= header_size
;
4039 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4040 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4044 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4046 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4047 const fs_reg
&coordinate
= inst
->src
[0];
4048 const fs_reg
&shadow_c
= inst
->src
[1];
4049 const fs_reg
&lod
= inst
->src
[2];
4050 const fs_reg
&lod2
= inst
->src
[3];
4051 const fs_reg
&sample_index
= inst
->src
[4];
4052 const fs_reg
&mcs
= inst
->src
[5];
4053 const fs_reg
&sampler
= inst
->src
[6];
4054 const fs_reg
&offset_value
= inst
->src
[7];
4055 assert(inst
->src
[8].file
== IMM
&& inst
->src
[9].file
== IMM
);
4056 const unsigned coord_components
= inst
->src
[8].ud
;
4057 const unsigned grad_components
= inst
->src
[9].ud
;
4059 if (devinfo
->gen
>= 7) {
4060 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4061 shadow_c
, lod
, lod2
, sample_index
,
4062 mcs
, sampler
, offset_value
,
4063 coord_components
, grad_components
);
4064 } else if (devinfo
->gen
>= 5) {
4065 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4066 shadow_c
, lod
, lod2
, sample_index
,
4067 sampler
, offset_value
,
4068 coord_components
, grad_components
);
4070 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4071 shadow_c
, lod
, lod2
, sampler
,
4072 coord_components
, grad_components
);
4077 * Initialize the header present in some typed and untyped surface
4081 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4083 fs_builder ubld
= bld
.exec_all().group(8, 0);
4084 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4085 ubld
.MOV(dst
, fs_reg(0));
4086 ubld
.MOV(component(dst
, 7), sample_mask
);
4091 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4092 const fs_reg
&sample_mask
)
4094 /* Get the logical send arguments. */
4095 const fs_reg
&addr
= inst
->src
[0];
4096 const fs_reg
&src
= inst
->src
[1];
4097 const fs_reg
&surface
= inst
->src
[2];
4098 const UNUSED fs_reg
&dims
= inst
->src
[3];
4099 const fs_reg
&arg
= inst
->src
[4];
4101 /* Calculate the total number of components of the payload. */
4102 const unsigned addr_sz
= inst
->components_read(0);
4103 const unsigned src_sz
= inst
->components_read(1);
4104 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4105 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4107 /* Allocate space for the payload. */
4108 fs_reg
*const components
= new fs_reg
[sz
];
4109 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4112 /* Construct the payload. */
4114 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4116 for (unsigned i
= 0; i
< addr_sz
; i
++)
4117 components
[n
++] = offset(addr
, bld
, i
);
4119 for (unsigned i
= 0; i
< src_sz
; i
++)
4120 components
[n
++] = offset(src
, bld
, i
);
4122 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4124 /* Update the original instruction. */
4126 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4127 inst
->header_size
= header_sz
;
4129 inst
->src
[0] = payload
;
4130 inst
->src
[1] = surface
;
4132 inst
->resize_sources(3);
4134 delete[] components
;
4138 fs_visitor::lower_logical_sends()
4140 bool progress
= false;
4142 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4143 const fs_builder
ibld(this, block
, inst
);
4145 switch (inst
->opcode
) {
4146 case FS_OPCODE_FB_WRITE_LOGICAL
:
4147 assert(stage
== MESA_SHADER_FRAGMENT
);
4148 lower_fb_write_logical_send(ibld
, inst
,
4149 (const brw_wm_prog_data
*)prog_data
,
4150 (const brw_wm_prog_key
*)key
,
4154 case SHADER_OPCODE_TEX_LOGICAL
:
4155 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4158 case SHADER_OPCODE_TXD_LOGICAL
:
4159 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4162 case SHADER_OPCODE_TXF_LOGICAL
:
4163 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4166 case SHADER_OPCODE_TXL_LOGICAL
:
4167 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4170 case SHADER_OPCODE_TXS_LOGICAL
:
4171 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4174 case FS_OPCODE_TXB_LOGICAL
:
4175 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4178 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4179 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4182 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4183 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4186 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4187 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4190 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4191 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4194 case SHADER_OPCODE_LOD_LOGICAL
:
4195 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4198 case SHADER_OPCODE_TG4_LOGICAL
:
4199 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4202 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4203 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4206 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4207 lower_surface_logical_send(ibld
, inst
,
4208 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4212 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4213 lower_surface_logical_send(ibld
, inst
,
4214 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4215 ibld
.sample_mask_reg());
4218 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4219 lower_surface_logical_send(ibld
, inst
,
4220 SHADER_OPCODE_UNTYPED_ATOMIC
,
4221 ibld
.sample_mask_reg());
4224 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4225 lower_surface_logical_send(ibld
, inst
,
4226 SHADER_OPCODE_TYPED_SURFACE_READ
,
4230 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4231 lower_surface_logical_send(ibld
, inst
,
4232 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4233 ibld
.sample_mask_reg());
4236 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4237 lower_surface_logical_send(ibld
, inst
,
4238 SHADER_OPCODE_TYPED_ATOMIC
,
4239 ibld
.sample_mask_reg());
4250 invalidate_live_intervals();
4256 * Get the closest native SIMD width supported by the hardware for instruction
4257 * \p inst. The instruction will be left untouched by
4258 * fs_visitor::lower_simd_width() if the returned value is equal to the
4259 * original execution size.
4262 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4263 const fs_inst
*inst
)
4265 switch (inst
->opcode
) {
4266 case BRW_OPCODE_MOV
:
4267 case BRW_OPCODE_SEL
:
4268 case BRW_OPCODE_NOT
:
4269 case BRW_OPCODE_AND
:
4271 case BRW_OPCODE_XOR
:
4272 case BRW_OPCODE_SHR
:
4273 case BRW_OPCODE_SHL
:
4274 case BRW_OPCODE_ASR
:
4275 case BRW_OPCODE_CMP
:
4276 case BRW_OPCODE_CMPN
:
4277 case BRW_OPCODE_CSEL
:
4278 case BRW_OPCODE_F32TO16
:
4279 case BRW_OPCODE_F16TO32
:
4280 case BRW_OPCODE_BFREV
:
4281 case BRW_OPCODE_BFE
:
4282 case BRW_OPCODE_BFI1
:
4283 case BRW_OPCODE_BFI2
:
4284 case BRW_OPCODE_ADD
:
4285 case BRW_OPCODE_MUL
:
4286 case BRW_OPCODE_AVG
:
4287 case BRW_OPCODE_FRC
:
4288 case BRW_OPCODE_RNDU
:
4289 case BRW_OPCODE_RNDD
:
4290 case BRW_OPCODE_RNDE
:
4291 case BRW_OPCODE_RNDZ
:
4292 case BRW_OPCODE_LZD
:
4293 case BRW_OPCODE_FBH
:
4294 case BRW_OPCODE_FBL
:
4295 case BRW_OPCODE_CBIT
:
4296 case BRW_OPCODE_SAD2
:
4297 case BRW_OPCODE_MAD
:
4298 case BRW_OPCODE_LRP
:
4299 case SHADER_OPCODE_RCP
:
4300 case SHADER_OPCODE_RSQ
:
4301 case SHADER_OPCODE_SQRT
:
4302 case SHADER_OPCODE_EXP2
:
4303 case SHADER_OPCODE_LOG2
:
4304 case SHADER_OPCODE_POW
:
4305 case SHADER_OPCODE_INT_QUOTIENT
:
4306 case SHADER_OPCODE_INT_REMAINDER
:
4307 case SHADER_OPCODE_SIN
:
4308 case SHADER_OPCODE_COS
: {
4309 /* According to the PRMs:
4310 * "A. In Direct Addressing mode, a source cannot span more than 2
4311 * adjacent GRF registers.
4312 * B. A destination cannot span more than 2 adjacent GRF registers."
4314 * Look for the source or destination with the largest register region
4315 * which is the one that is going to limit the overal execution size of
4316 * the instruction due to this rule.
4318 unsigned reg_count
= inst
->regs_written
;
4320 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4321 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4323 /* Calculate the maximum execution size of the instruction based on the
4324 * factor by which it goes over the hardware limit of 2 GRFs.
4326 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4328 case SHADER_OPCODE_MULH
:
4329 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4330 * is 8-wide on Gen7+.
4332 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4334 case FS_OPCODE_FB_WRITE_LOGICAL
:
4335 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4338 assert(devinfo
->gen
!= 6 ||
4339 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4340 inst
->exec_size
== 8);
4341 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4342 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4343 8 : inst
->exec_size
);
4345 case SHADER_OPCODE_TXD_LOGICAL
:
4346 /* TXD is unsupported in SIMD16 mode. */
4349 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4350 /* gather4_po_c is unsupported in SIMD16 mode. */
4351 const fs_reg
&shadow_c
= inst
->src
[1];
4352 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4354 case SHADER_OPCODE_TXL_LOGICAL
:
4355 case FS_OPCODE_TXB_LOGICAL
: {
4356 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4357 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4358 * mode because the message exceeds the maximum length of 11.
4360 const fs_reg
&shadow_c
= inst
->src
[1];
4361 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4363 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4366 return inst
->exec_size
;
4368 case SHADER_OPCODE_TXF_LOGICAL
:
4369 case SHADER_OPCODE_TXS_LOGICAL
:
4370 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4371 * messages. Use SIMD16 instead.
4373 if (devinfo
->gen
== 4)
4376 return inst
->exec_size
;
4378 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4379 /* This opcode can take up to 6 arguments which means that in some
4380 * circumstances it can end up with a message that is too long in SIMD16
4383 const unsigned coord_components
= inst
->src
[8].ud
;
4384 /* First three arguments are the sample index and the two arguments for
4387 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
4390 return inst
->exec_size
;
4393 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4394 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4395 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4399 return inst
->exec_size
;
4404 * The \p rows array of registers represents a \p num_rows by \p num_columns
4405 * matrix in row-major order, write it in column-major order into the register
4406 * passed as destination. \p stride gives the separation between matrix
4407 * elements in the input in fs_builder::dispatch_width() units.
4410 emit_transpose(const fs_builder
&bld
,
4411 const fs_reg
&dst
, const fs_reg
*rows
,
4412 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4414 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4416 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4417 for (unsigned j
= 0; j
< num_rows
; ++j
)
4418 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4421 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4423 delete[] components
;
4427 fs_visitor::lower_simd_width()
4429 bool progress
= false;
4431 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4432 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4434 if (lower_width
!= inst
->exec_size
) {
4435 /* Builder matching the original instruction. We may also need to
4436 * emit an instruction of width larger than the original, set the
4437 * execution size of the builder to the highest of both for now so
4438 * we're sure that both cases can be handled.
4440 const fs_builder ibld
= bld
.at(block
, inst
)
4441 .exec_all(inst
->force_writemask_all
)
4442 .group(MAX2(inst
->exec_size
, lower_width
),
4443 inst
->force_sechalf
);
4445 /* Split the copies in chunks of the execution width of either the
4446 * original or the lowered instruction, whichever is lower.
4448 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4449 const unsigned n
= inst
->exec_size
/ copy_width
;
4450 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4451 inst
->dst
.component_size(inst
->exec_size
);
4454 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4455 !inst
->writes_accumulator
&& !inst
->mlen
);
4457 for (unsigned i
= 0; i
< n
; i
++) {
4458 /* Emit a copy of the original instruction with the lowered width.
4459 * If the EOT flag was set throw it away except for the last
4460 * instruction to avoid killing the thread prematurely.
4462 fs_inst split_inst
= *inst
;
4463 split_inst
.exec_size
= lower_width
;
4464 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4466 /* Select the correct channel enables for the i-th group, then
4467 * transform the sources and destination and emit the lowered
4470 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4472 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4473 if (inst
->src
[j
].file
!= BAD_FILE
&&
4474 !is_uniform(inst
->src
[j
])) {
4475 /* Get the i-th copy_width-wide chunk of the source. */
4476 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4477 const unsigned src_size
= inst
->components_read(j
);
4479 /* Use a trivial transposition to copy one every n
4480 * copy_width-wide components of the register into a
4481 * temporary passed as source to the lowered instruction.
4483 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4484 emit_transpose(lbld
.group(copy_width
, 0),
4485 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4489 if (inst
->regs_written
) {
4490 /* Allocate enough space to hold the result of the lowered
4491 * instruction and fix up the number of registers written.
4493 split_inst
.dst
= dsts
[i
] =
4494 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4495 split_inst
.regs_written
=
4496 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4500 lbld
.emit(split_inst
);
4503 if (inst
->regs_written
) {
4504 /* Distance between useful channels in the temporaries, skipping
4505 * garbage if the lowered instruction is wider than the original.
4507 const unsigned m
= lower_width
/ copy_width
;
4509 /* Interleave the components of the result from the lowered
4510 * instructions. We need to set exec_all() when copying more than
4511 * one half per component, because LOAD_PAYLOAD (in terms of which
4512 * emit_transpose is implemented) can only use the same channel
4513 * enable signals for all of its non-header sources.
4515 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4516 .group(copy_width
, 0),
4517 inst
->dst
, dsts
, n
, dst_size
, m
);
4520 inst
->remove(block
);
4526 invalidate_live_intervals();
4532 fs_visitor::dump_instructions()
4534 dump_instructions(NULL
);
4538 fs_visitor::dump_instructions(const char *name
)
4540 FILE *file
= stderr
;
4541 if (name
&& geteuid() != 0) {
4542 file
= fopen(name
, "w");
4548 calculate_register_pressure();
4549 int ip
= 0, max_pressure
= 0;
4550 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4551 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4552 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4553 dump_instruction(inst
, file
);
4556 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4559 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4560 fprintf(file
, "%4d: ", ip
++);
4561 dump_instruction(inst
, file
);
4565 if (file
!= stderr
) {
4571 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4573 dump_instruction(be_inst
, stderr
);
4577 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4579 fs_inst
*inst
= (fs_inst
*)be_inst
;
4581 if (inst
->predicate
) {
4582 fprintf(file
, "(%cf0.%d) ",
4583 inst
->predicate_inverse
? '-' : '+',
4587 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4589 fprintf(file
, ".sat");
4590 if (inst
->conditional_mod
) {
4591 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4592 if (!inst
->predicate
&&
4593 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4594 inst
->opcode
!= BRW_OPCODE_IF
&&
4595 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4596 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4599 fprintf(file
, "(%d) ", inst
->exec_size
);
4602 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4605 switch (inst
->dst
.file
) {
4607 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
4608 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
4609 inst
->dst
.subreg_offset
)
4610 fprintf(file
, "+%d.%d",
4611 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4614 fprintf(file
, "g%d", inst
->dst
.nr
);
4617 fprintf(file
, "m%d", inst
->dst
.nr
);
4620 fprintf(file
, "(null)");
4623 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4626 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4629 switch (inst
->dst
.nr
) {
4631 fprintf(file
, "null");
4633 case BRW_ARF_ADDRESS
:
4634 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
4636 case BRW_ARF_ACCUMULATOR
:
4637 fprintf(file
, "acc%d", inst
->dst
.subnr
);
4640 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4643 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4646 if (inst
->dst
.subnr
)
4647 fprintf(file
, "+%d", inst
->dst
.subnr
);
4650 unreachable("not reached");
4652 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4654 for (int i
= 0; i
< inst
->sources
; i
++) {
4655 if (inst
->src
[i
].negate
)
4657 if (inst
->src
[i
].abs
)
4659 switch (inst
->src
[i
].file
) {
4661 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
4662 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
4663 inst
->src
[i
].subreg_offset
)
4664 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4665 inst
->src
[i
].subreg_offset
);
4668 fprintf(file
, "g%d", inst
->src
[i
].nr
);
4671 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
4674 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
4677 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
4678 if (inst
->src
[i
].reladdr
) {
4679 fprintf(file
, "+reladdr");
4680 } else if (inst
->src
[i
].subreg_offset
) {
4681 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4682 inst
->src
[i
].subreg_offset
);
4686 fprintf(file
, "(null)");
4689 switch (inst
->src
[i
].type
) {
4690 case BRW_REGISTER_TYPE_F
:
4691 fprintf(file
, "%ff", inst
->src
[i
].f
);
4693 case BRW_REGISTER_TYPE_W
:
4694 case BRW_REGISTER_TYPE_D
:
4695 fprintf(file
, "%dd", inst
->src
[i
].d
);
4697 case BRW_REGISTER_TYPE_UW
:
4698 case BRW_REGISTER_TYPE_UD
:
4699 fprintf(file
, "%uu", inst
->src
[i
].ud
);
4701 case BRW_REGISTER_TYPE_VF
:
4702 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4703 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
4704 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
4705 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
4706 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
4709 fprintf(file
, "???");
4714 switch (inst
->src
[i
].nr
) {
4716 fprintf(file
, "null");
4718 case BRW_ARF_ADDRESS
:
4719 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
4721 case BRW_ARF_ACCUMULATOR
:
4722 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
4725 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4728 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4731 if (inst
->src
[i
].subnr
)
4732 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
4735 if (inst
->src
[i
].abs
)
4738 if (inst
->src
[i
].file
!= IMM
) {
4739 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4742 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4743 fprintf(file
, ", ");
4748 if (inst
->force_writemask_all
)
4749 fprintf(file
, "NoMask ");
4751 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4752 if (inst
->force_sechalf
)
4753 fprintf(file
, "2ndhalf ");
4755 fprintf(file
, "1sthalf ");
4758 fprintf(file
, "\n");
4762 * Possibly returns an instruction that set up @param reg.
4764 * Sometimes we want to take the result of some expression/variable
4765 * dereference tree and rewrite the instruction generating the result
4766 * of the tree. When processing the tree, we know that the
4767 * instructions generated are all writing temporaries that are dead
4768 * outside of this tree. So, if we have some instructions that write
4769 * a temporary, we're free to point that temp write somewhere else.
4771 * Note that this doesn't guarantee that the instruction generated
4772 * only reg -- it might be the size=4 destination of a texture instruction.
4775 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4780 end
->is_partial_write() ||
4782 !reg
.equals(end
->dst
)) {
4790 fs_visitor::setup_payload_gen6()
4793 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
4794 unsigned barycentric_interp_modes
=
4795 (stage
== MESA_SHADER_FRAGMENT
) ?
4796 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4798 assert(devinfo
->gen
>= 6);
4800 /* R0-1: masks, pixel X/Y coordinates. */
4801 payload
.num_regs
= 2;
4802 /* R2: only for 32-pixel dispatch.*/
4804 /* R3-26: barycentric interpolation coordinates. These appear in the
4805 * same order that they appear in the brw_wm_barycentric_interp_mode
4806 * enum. Each set of coordinates occupies 2 registers if dispatch width
4807 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4808 * appear if they were enabled using the "Barycentric Interpolation
4809 * Mode" bits in WM_STATE.
4811 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4812 if (barycentric_interp_modes
& (1 << i
)) {
4813 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4814 payload
.num_regs
+= 2;
4815 if (dispatch_width
== 16) {
4816 payload
.num_regs
+= 2;
4821 /* R27: interpolated depth if uses source depth */
4823 payload
.source_depth_reg
= payload
.num_regs
;
4825 if (dispatch_width
== 16) {
4826 /* R28: interpolated depth if not SIMD8. */
4830 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4832 payload
.source_w_reg
= payload
.num_regs
;
4834 if (dispatch_width
== 16) {
4835 /* R30: interpolated W if not SIMD8. */
4840 if (stage
== MESA_SHADER_FRAGMENT
) {
4841 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4842 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4843 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4844 /* R31: MSAA position offsets. */
4845 if (prog_data
->uses_pos_offset
) {
4846 payload
.sample_pos_reg
= payload
.num_regs
;
4851 /* R32: MSAA input coverage mask */
4852 if (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
4853 assert(devinfo
->gen
>= 7);
4854 payload
.sample_mask_in_reg
= payload
.num_regs
;
4856 if (dispatch_width
== 16) {
4857 /* R33: input coverage mask if not SIMD8. */
4862 /* R34-: bary for 32-pixel. */
4863 /* R58-59: interp W for 32-pixel. */
4865 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4866 source_depth_to_render_target
= true;
4871 fs_visitor::setup_vs_payload()
4873 /* R0: thread header, R1: urb handles */
4874 payload
.num_regs
= 2;
4878 * We are building the local ID push constant data using the simplest possible
4879 * method. We simply push the local IDs directly as they should appear in the
4880 * registers for the uvec3 gl_LocalInvocationID variable.
4882 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
4883 * registers worth of push constant space.
4885 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
4886 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
4889 * FINISHME: There are a few easy optimizations to consider.
4891 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
4892 * no need for using push constant space for that dimension.
4894 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
4895 * easily use 16-bit words rather than 32-bit dwords in the push constant
4898 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
4899 * conveying the data, and thereby reduce push constant usage.
4903 fs_visitor::setup_gs_payload()
4905 assert(stage
== MESA_SHADER_GEOMETRY
);
4907 struct brw_gs_prog_data
*gs_prog_data
=
4908 (struct brw_gs_prog_data
*) prog_data
;
4909 struct brw_vue_prog_data
*vue_prog_data
=
4910 (struct brw_vue_prog_data
*) prog_data
;
4912 /* R0: thread header, R1: output URB handles */
4913 payload
.num_regs
= 2;
4915 if (gs_prog_data
->include_primitive_id
) {
4916 /* R2: Primitive ID 0..7 */
4920 /* Use a maximum of 32 registers for push-model inputs. */
4921 const unsigned max_push_components
= 32;
4923 /* If pushing our inputs would take too many registers, reduce the URB read
4924 * length (which is in HWords, or 8 registers), and resort to pulling.
4926 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
4927 * have to multiply by VerticesIn to obtain the total storage requirement.
4929 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
4930 max_push_components
) {
4931 gs_prog_data
->base
.include_vue_handles
= true;
4933 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
4934 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
4936 vue_prog_data
->urb_read_length
=
4937 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
4942 fs_visitor::setup_cs_payload()
4944 assert(devinfo
->gen
>= 7);
4945 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
4947 payload
.num_regs
= 1;
4949 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
4950 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
4951 payload
.local_invocation_id_reg
= payload
.num_regs
;
4952 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
4957 fs_visitor::calculate_register_pressure()
4959 invalidate_live_intervals();
4960 calculate_live_intervals();
4962 unsigned num_instructions
= 0;
4963 foreach_block(block
, cfg
)
4964 num_instructions
+= block
->instructions
.length();
4966 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
4968 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
4969 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
4970 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
4975 fs_visitor::optimize()
4977 /* Start by validating the shader we currently have. */
4980 /* bld is the common builder object pointing at the end of the program we
4981 * used to translate it into i965 IR. For the optimization and lowering
4982 * passes coming next, any code added after the end of the program without
4983 * having explicitly called fs_builder::at() clearly points at a mistake.
4984 * Ideally optimization passes wouldn't be part of the visitor so they
4985 * wouldn't have access to bld at all, but they do, so just in case some
4986 * pass forgets to ask for a location explicitly set it to NULL here to
4987 * make it trip. The dispatch width is initialized to a bogus value to
4988 * make sure that optimizations set the execution controls explicitly to
4989 * match the code they are manipulating instead of relying on the defaults.
4991 bld
= fs_builder(this, 64);
4993 assign_constant_locations();
4994 demote_pull_constants();
4998 split_virtual_grfs();
5001 #define OPT(pass, args...) ({ \
5003 bool this_progress = pass(args); \
5005 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5006 char filename[64]; \
5007 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5008 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5010 backend_shader::dump_instructions(filename); \
5015 progress = progress || this_progress; \
5019 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5021 snprintf(filename
, 64, "%s%d-%s-00-start",
5022 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5024 backend_shader::dump_instructions(filename
);
5027 bool progress
= false;
5031 OPT(lower_simd_width
);
5032 OPT(lower_logical_sends
);
5039 OPT(remove_duplicate_mrf_writes
);
5043 OPT(opt_copy_propagate
);
5044 OPT(opt_predicated_break
, this);
5045 OPT(opt_cmod_propagation
);
5046 OPT(dead_code_eliminate
);
5047 OPT(opt_peephole_sel
);
5048 OPT(dead_control_flow_eliminate
, this);
5049 OPT(opt_register_renaming
);
5050 OPT(opt_redundant_discard_jumps
);
5051 OPT(opt_saturate_propagation
);
5052 OPT(opt_zero_samples
);
5053 OPT(register_coalesce
);
5054 OPT(compute_to_mrf
);
5055 OPT(eliminate_find_live_channel
);
5057 OPT(compact_virtual_grfs
);
5062 OPT(opt_sampler_eot
);
5064 if (OPT(lower_load_payload
)) {
5065 split_virtual_grfs();
5066 OPT(register_coalesce
);
5067 OPT(compute_to_mrf
);
5068 OPT(dead_code_eliminate
);
5071 OPT(opt_combine_constants
);
5072 OPT(lower_integer_multiplication
);
5074 lower_uniform_pull_constant_loads();
5080 * Three source instruction must have a GRF/MRF destination register.
5081 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5084 fs_visitor::fixup_3src_null_dest()
5086 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5087 if (inst
->is_3src() && inst
->dst
.is_null()) {
5088 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5095 fs_visitor::allocate_registers()
5097 bool allocated_without_spills
;
5099 static const enum instruction_scheduler_mode pre_modes
[] = {
5101 SCHEDULE_PRE_NON_LIFO
,
5105 /* Try each scheduling heuristic to see if it can successfully register
5106 * allocate without spilling. They should be ordered by decreasing
5107 * performance but increasing likelihood of allocating.
5109 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5110 schedule_instructions(pre_modes
[i
]);
5113 assign_regs_trivial();
5114 allocated_without_spills
= true;
5116 allocated_without_spills
= assign_regs(false);
5118 if (allocated_without_spills
)
5122 if (!allocated_without_spills
) {
5123 /* We assume that any spilling is worse than just dropping back to
5124 * SIMD8. There's probably actually some intermediate point where
5125 * SIMD16 with a couple of spills is still better.
5127 if (dispatch_width
== 16) {
5128 fail("Failure to register allocate. Reduce number of "
5129 "live scalar values to avoid this.");
5131 compiler
->shader_perf_log(log_data
,
5132 "%s shader triggered register spilling. "
5133 "Try reducing the number of live scalar "
5134 "values to improve performance.\n",
5138 /* Since we're out of heuristics, just go spill registers until we
5139 * get an allocation.
5141 while (!assign_regs(true)) {
5147 /* This must come after all optimization and register allocation, since
5148 * it inserts dead code that happens to have side effects, and it does
5149 * so based on the actual physical registers in use.
5151 insert_gen4_send_dependency_workarounds();
5156 schedule_instructions(SCHEDULE_POST
);
5158 if (last_scratch
> 0)
5159 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5163 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5165 assert(stage
== MESA_SHADER_VERTEX
);
5169 if (shader_time_index
>= 0)
5170 emit_shader_time_begin();
5177 compute_clip_distance(clip_planes
);
5181 if (shader_time_index
>= 0)
5182 emit_shader_time_end();
5188 assign_curb_setup();
5189 assign_vs_urb_setup();
5191 fixup_3src_null_dest();
5192 allocate_registers();
5198 fs_visitor::run_gs()
5200 assert(stage
== MESA_SHADER_GEOMETRY
);
5204 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
5206 if (gs_compile
->control_data_header_size_bits
> 0) {
5207 /* Create a VGRF to store accumulated control data bits. */
5208 this->control_data_bits
= vgrf(glsl_type::uint_type
);
5210 /* If we're outputting more than 32 control data bits, then EmitVertex()
5211 * will set control_data_bits to 0 after emitting the first vertex.
5212 * Otherwise, we need to initialize it to 0 here.
5214 if (gs_compile
->control_data_header_size_bits
<= 32) {
5215 const fs_builder abld
= bld
.annotate("initialize control data bits");
5216 abld
.MOV(this->control_data_bits
, fs_reg(0u));
5220 if (shader_time_index
>= 0)
5221 emit_shader_time_begin();
5225 emit_gs_thread_end();
5227 if (shader_time_index
>= 0)
5228 emit_shader_time_end();
5237 assign_curb_setup();
5238 assign_gs_urb_setup();
5240 fixup_3src_null_dest();
5241 allocate_registers();
5247 fs_visitor::run_fs(bool do_rep_send
)
5249 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5250 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
5252 assert(stage
== MESA_SHADER_FRAGMENT
);
5254 if (devinfo
->gen
>= 6)
5255 setup_payload_gen6();
5257 setup_payload_gen4();
5261 } else if (do_rep_send
) {
5262 assert(dispatch_width
== 16);
5263 emit_repclear_shader();
5265 if (shader_time_index
>= 0)
5266 emit_shader_time_begin();
5268 calculate_urb_setup();
5269 if (nir
->info
.inputs_read
> 0) {
5270 if (devinfo
->gen
< 6)
5271 emit_interpolation_setup_gen4();
5273 emit_interpolation_setup_gen6();
5276 /* We handle discards by keeping track of the still-live pixels in f0.1.
5277 * Initialize it with the dispatched pixels.
5279 if (wm_prog_data
->uses_kill
) {
5280 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5281 discard_init
->flag_subreg
= 1;
5284 /* Generate FS IR for main(). (the visitor only descends into
5285 * functions called "main").
5292 if (wm_prog_data
->uses_kill
)
5293 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5295 if (wm_key
->alpha_test_func
)
5300 if (shader_time_index
>= 0)
5301 emit_shader_time_end();
5307 assign_curb_setup();
5310 fixup_3src_null_dest();
5311 allocate_registers();
5317 if (dispatch_width
== 8)
5318 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5320 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5326 fs_visitor::run_cs()
5328 assert(stage
== MESA_SHADER_COMPUTE
);
5332 if (shader_time_index
>= 0)
5333 emit_shader_time_begin();
5340 emit_cs_terminate();
5342 if (shader_time_index
>= 0)
5343 emit_shader_time_end();
5349 assign_curb_setup();
5351 fixup_3src_null_dest();
5352 allocate_registers();
5361 * Return a bitfield where bit n is set if barycentric interpolation mode n
5362 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
5365 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
5366 bool shade_model_flat
,
5367 bool persample_shading
,
5368 const nir_shader
*shader
)
5370 unsigned barycentric_interp_modes
= 0;
5372 nir_foreach_variable(var
, &shader
->inputs
) {
5373 enum glsl_interp_qualifier interp_qualifier
=
5374 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5375 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
5376 bool is_sample
= var
->data
.sample
|| persample_shading
;
5377 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5378 (var
->data
.location
== VARYING_SLOT_COL1
);
5380 /* Ignore WPOS and FACE, because they don't require interpolation. */
5381 if (var
->data
.location
== VARYING_SLOT_POS
||
5382 var
->data
.location
== VARYING_SLOT_FACE
)
5385 /* Determine the set (or sets) of barycentric coordinates needed to
5386 * interpolate this variable. Note that when
5387 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
5388 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
5389 * for lit pixels, so we need both sets of barycentric coordinates.
5391 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
5393 barycentric_interp_modes
|=
5394 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
5395 } else if (is_sample
) {
5396 barycentric_interp_modes
|=
5397 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
5399 if ((!is_centroid
&& !is_sample
) ||
5400 devinfo
->needs_unlit_centroid_workaround
) {
5401 barycentric_interp_modes
|=
5402 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
5404 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
5405 (!(shade_model_flat
&& is_gl_Color
) &&
5406 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
5408 barycentric_interp_modes
|=
5409 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
5410 } else if (is_sample
) {
5411 barycentric_interp_modes
|=
5412 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
5414 if ((!is_centroid
&& !is_sample
) ||
5415 devinfo
->needs_unlit_centroid_workaround
) {
5416 barycentric_interp_modes
|=
5417 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
5422 return barycentric_interp_modes
;
5426 computed_depth_mode(const nir_shader
*shader
)
5428 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5429 switch (shader
->info
.fs
.depth_layout
) {
5430 case FRAG_DEPTH_LAYOUT_NONE
:
5431 case FRAG_DEPTH_LAYOUT_ANY
:
5432 return BRW_PSCDEPTH_ON
;
5433 case FRAG_DEPTH_LAYOUT_GREATER
:
5434 return BRW_PSCDEPTH_ON_GE
;
5435 case FRAG_DEPTH_LAYOUT_LESS
:
5436 return BRW_PSCDEPTH_ON_LE
;
5437 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
5438 return BRW_PSCDEPTH_OFF
;
5441 return BRW_PSCDEPTH_OFF
;
5445 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
5447 const struct brw_wm_prog_key
*key
,
5448 struct brw_wm_prog_data
*prog_data
,
5449 const nir_shader
*shader
,
5450 struct gl_program
*prog
,
5451 int shader_time_index8
, int shader_time_index16
,
5453 unsigned *final_assembly_size
,
5456 /* key->alpha_test_func means simulating alpha testing via discards,
5457 * so the shader definitely kills pixels.
5459 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
5460 prog_data
->uses_omask
=
5461 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
5462 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
5463 prog_data
->computed_stencil
=
5464 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
5466 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
5468 prog_data
->barycentric_interp_modes
=
5469 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
5471 key
->persample_shading
,
5474 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
,
5475 &prog_data
->base
, prog
, shader
, 8,
5476 shader_time_index8
);
5477 if (!v
.run_fs(false /* do_rep_send */)) {
5479 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
5484 cfg_t
*simd16_cfg
= NULL
;
5485 fs_visitor
v2(compiler
, log_data
, mem_ctx
, key
,
5486 &prog_data
->base
, prog
, shader
, 16,
5487 shader_time_index16
);
5488 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
5489 if (!v
.simd16_unsupported
) {
5490 /* Try a SIMD16 compile */
5491 v2
.import_uniforms(&v
);
5492 if (!v2
.run_fs(use_rep_send
)) {
5493 compiler
->shader_perf_log(log_data
,
5494 "SIMD16 shader failed to compile: %s",
5497 simd16_cfg
= v2
.cfg
;
5503 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || use_rep_send
;
5504 if ((no_simd8
|| compiler
->devinfo
->gen
< 5) && simd16_cfg
) {
5506 prog_data
->no_8
= true;
5509 prog_data
->no_8
= false;
5512 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
5513 v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
5515 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5516 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
5517 shader
->info
.label
? shader
->info
.label
:
5519 shader
->info
.name
));
5523 g
.generate_code(simd8_cfg
, 8);
5525 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5527 return g
.get_assembly(final_assembly_size
);
5531 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*prog_data
,
5532 void *buffer
, uint32_t threads
, uint32_t stride
)
5534 if (prog_data
->local_invocation_id_regs
== 0)
5537 /* 'stride' should be an integer number of registers, that is, a multiple
5540 assert(stride
% 32 == 0);
5542 unsigned x
= 0, y
= 0, z
= 0;
5543 for (unsigned t
= 0; t
< threads
; t
++) {
5544 uint32_t *param
= (uint32_t *) buffer
+ stride
* t
/ 4;
5546 for (unsigned i
= 0; i
< prog_data
->simd_size
; i
++) {
5547 param
[0 * prog_data
->simd_size
+ i
] = x
;
5548 param
[1 * prog_data
->simd_size
+ i
] = y
;
5549 param
[2 * prog_data
->simd_size
+ i
] = z
;
5552 if (x
== prog_data
->local_size
[0]) {
5555 if (y
== prog_data
->local_size
[1]) {
5558 if (z
== prog_data
->local_size
[2])
5567 fs_visitor::emit_cs_local_invocation_id_setup()
5569 assert(stage
== MESA_SHADER_COMPUTE
);
5571 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5573 struct brw_reg src
=
5574 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
5575 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
5577 src
.nr
+= dispatch_width
/ 8;
5578 bld
.MOV(offset(*reg
, bld
, 1), src
);
5579 src
.nr
+= dispatch_width
/ 8;
5580 bld
.MOV(offset(*reg
, bld
, 2), src
);
5586 fs_visitor::emit_cs_work_group_id_setup()
5588 assert(stage
== MESA_SHADER_COMPUTE
);
5590 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5592 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
5593 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
5594 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
5596 bld
.MOV(*reg
, r0_1
);
5597 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
5598 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
5604 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
5606 const struct brw_cs_prog_key
*key
,
5607 struct brw_cs_prog_data
*prog_data
,
5608 const nir_shader
*shader
,
5609 int shader_time_index
,
5610 unsigned *final_assembly_size
,
5613 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
5614 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
5615 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
5616 unsigned local_workgroup_size
=
5617 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
5618 shader
->info
.cs
.local_size
[2];
5620 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
5623 const char *fail_msg
= NULL
;
5625 /* Now the main event: Visit the shader IR and generate our CS IR for it.
5627 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5628 NULL
, /* Never used in core profile */
5629 shader
, 8, shader_time_index
);
5631 fail_msg
= v8
.fail_msg
;
5632 } else if (local_workgroup_size
<= 8 * max_cs_threads
) {
5634 prog_data
->simd_size
= 8;
5637 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5638 NULL
, /* Never used in core profile */
5639 shader
, 16, shader_time_index
);
5640 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
5641 !fail_msg
&& !v8
.simd16_unsupported
&&
5642 local_workgroup_size
<= 16 * max_cs_threads
) {
5643 /* Try a SIMD16 compile */
5644 v16
.import_uniforms(&v8
);
5645 if (!v16
.run_cs()) {
5646 compiler
->shader_perf_log(log_data
,
5647 "SIMD16 shader failed to compile: %s",
5651 "Couldn't generate SIMD16 program and not "
5652 "enough threads for SIMD8";
5656 prog_data
->simd_size
= 16;
5660 if (unlikely(cfg
== NULL
)) {
5663 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
5668 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
5669 v8
.promoted_constants
, v8
.runtime_check_aads_emit
, "CS");
5670 if (INTEL_DEBUG
& DEBUG_CS
) {
5671 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
5672 shader
->info
.label
? shader
->info
.label
:
5675 g
.enable_debug(name
);
5678 g
.generate_code(cfg
, prog_data
->simd_size
);
5680 return g
.get_assembly(final_assembly_size
);