2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
47 #include "../glsl/glsl_types.h"
48 #include "../glsl/ir_optimization.h"
49 #include "../glsl/ir_print_visitor.h"
51 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
54 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
56 struct brw_shader
*shader
;
58 shader
= talloc_zero(NULL
, struct brw_shader
);
60 shader
->base
.Type
= type
;
61 shader
->base
.Name
= name
;
62 _mesa_init_shader(ctx
, &shader
->base
);
68 struct gl_shader_program
*
69 brw_new_shader_program(struct gl_context
*ctx
, GLuint name
)
71 struct brw_shader_program
*prog
;
72 prog
= talloc_zero(NULL
, struct brw_shader_program
);
74 prog
->base
.Name
= name
;
75 _mesa_init_shader_program(ctx
, &prog
->base
);
81 brw_compile_shader(struct gl_context
*ctx
, struct gl_shader
*shader
)
83 if (!_mesa_ir_compile_shader(ctx
, shader
))
90 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
92 struct brw_context
*brw
= brw_context(ctx
);
93 struct intel_context
*intel
= &brw
->intel
;
95 struct brw_shader
*shader
=
96 (struct brw_shader
*)prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
98 void *mem_ctx
= talloc_new(NULL
);
102 talloc_free(shader
->ir
);
103 shader
->ir
= new(shader
) exec_list
;
104 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
106 do_mat_op_to_vec(shader
->ir
);
107 lower_instructions(shader
->ir
,
114 /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this,
115 * if-statements need to be flattened.
118 lower_if_to_cond_assign(shader
->ir
, 16);
120 do_lower_texture_projection(shader
->ir
);
121 do_vec_index_to_cond_assign(shader
->ir
);
122 brw_do_cubemap_normalize(shader
->ir
);
127 brw_do_channel_expressions(shader
->ir
);
128 brw_do_vector_splitting(shader
->ir
);
130 progress
= do_lower_jumps(shader
->ir
, true, true,
131 true, /* main return */
132 false, /* continue */
136 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
138 progress
= lower_noise(shader
->ir
) || progress
;
140 lower_variable_index_to_cond_assign(shader
->ir
,
142 GL_TRUE
, /* output */
144 GL_TRUE
/* uniform */
146 progress
= lower_quadop_vector(shader
->ir
, false) || progress
;
149 validate_ir_tree(shader
->ir
);
151 reparent_ir(shader
->ir
, shader
->ir
);
152 talloc_free(mem_ctx
);
155 if (!_mesa_ir_link_shader(ctx
, prog
))
162 type_size(const struct glsl_type
*type
)
164 unsigned int size
, i
;
166 switch (type
->base_type
) {
169 case GLSL_TYPE_FLOAT
:
171 return type
->components();
172 case GLSL_TYPE_ARRAY
:
173 return type_size(type
->fields
.array
) * type
->length
;
174 case GLSL_TYPE_STRUCT
:
176 for (i
= 0; i
< type
->length
; i
++) {
177 size
+= type_size(type
->fields
.structure
[i
].type
);
180 case GLSL_TYPE_SAMPLER
:
181 /* Samplers take up no register space, since they're baked in at
186 assert(!"not reached");
192 * Returns how many MRFs an FS opcode will write over.
194 * Note that this is not the 0 or 1 implied writes in an actual gen
195 * instruction -- the FS opcodes often generate MOVs in addition.
198 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
203 switch (inst
->opcode
) {
218 case FS_OPCODE_FB_WRITE
:
220 case FS_OPCODE_PULL_CONSTANT_LOAD
:
221 case FS_OPCODE_UNSPILL
:
223 case FS_OPCODE_SPILL
:
226 assert(!"not reached");
232 fs_visitor::virtual_grf_alloc(int size
)
234 if (virtual_grf_array_size
<= virtual_grf_next
) {
235 if (virtual_grf_array_size
== 0)
236 virtual_grf_array_size
= 16;
238 virtual_grf_array_size
*= 2;
239 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
240 int, virtual_grf_array_size
);
242 /* This slot is always unused. */
243 virtual_grf_sizes
[0] = 0;
245 virtual_grf_sizes
[virtual_grf_next
] = size
;
246 return virtual_grf_next
++;
249 /** Fixed HW reg constructor. */
250 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
254 this->hw_reg
= hw_reg
;
255 this->type
= BRW_REGISTER_TYPE_F
;
258 /** Fixed HW reg constructor. */
259 fs_reg::fs_reg(enum register_file file
, int hw_reg
, uint32_t type
)
263 this->hw_reg
= hw_reg
;
268 brw_type_for_base_type(const struct glsl_type
*type
)
270 switch (type
->base_type
) {
271 case GLSL_TYPE_FLOAT
:
272 return BRW_REGISTER_TYPE_F
;
275 return BRW_REGISTER_TYPE_D
;
277 return BRW_REGISTER_TYPE_UD
;
278 case GLSL_TYPE_ARRAY
:
279 case GLSL_TYPE_STRUCT
:
280 case GLSL_TYPE_SAMPLER
:
281 /* These should be overridden with the type of the member when
282 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
283 * way to trip up if we don't.
285 return BRW_REGISTER_TYPE_UD
;
287 assert(!"not reached");
288 return BRW_REGISTER_TYPE_F
;
292 /** Automatic reg constructor. */
293 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
298 this->reg
= v
->virtual_grf_alloc(type_size(type
));
299 this->reg_offset
= 0;
300 this->type
= brw_type_for_base_type(type
);
304 fs_visitor::variable_storage(ir_variable
*var
)
306 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
309 /* Our support for uniforms is piggy-backed on the struct
310 * gl_fragment_program, because that's where the values actually
311 * get stored, rather than in some global gl_shader_program uniform
315 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
317 unsigned int offset
= 0;
320 if (type
->is_matrix()) {
321 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
322 type
->vector_elements
,
325 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
326 offset
+= setup_uniform_values(loc
+ offset
, column
);
332 switch (type
->base_type
) {
333 case GLSL_TYPE_FLOAT
:
337 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
338 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
339 unsigned int param
= c
->prog_data
.nr_params
++;
341 assert(param
< ARRAY_SIZE(c
->prog_data
.param
));
343 switch (type
->base_type
) {
344 case GLSL_TYPE_FLOAT
:
345 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
348 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2U
;
351 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2I
;
354 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2B
;
357 assert(!"not reached");
358 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
362 c
->prog_data
.param
[param
] = &vec_values
[i
];
366 case GLSL_TYPE_STRUCT
:
367 for (unsigned int i
= 0; i
< type
->length
; i
++) {
368 offset
+= setup_uniform_values(loc
+ offset
,
369 type
->fields
.structure
[i
].type
);
373 case GLSL_TYPE_ARRAY
:
374 for (unsigned int i
= 0; i
< type
->length
; i
++) {
375 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
379 case GLSL_TYPE_SAMPLER
:
380 /* The sampler takes up a slot, but we don't use any values from it. */
384 assert(!"not reached");
390 /* Our support for builtin uniforms is even scarier than non-builtin.
391 * It sits on top of the PROG_STATE_VAR parameters that are
392 * automatically updated from GL context state.
395 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
397 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
399 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
400 statevar
= &_mesa_builtin_uniform_desc
[i
];
401 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
405 if (!statevar
->name
) {
407 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
412 if (ir
->type
->is_array()) {
413 array_count
= ir
->type
->length
;
418 for (int a
= 0; a
< array_count
; a
++) {
419 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
420 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
421 int tokens
[STATE_LENGTH
];
423 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
424 if (ir
->type
->is_array()) {
428 /* This state reference has already been setup by ir_to_mesa,
429 * but we'll get the same index back here.
431 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
432 (gl_state_index
*)tokens
);
433 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
435 /* Add each of the unique swizzles of the element as a
436 * parameter. This'll end up matching the expected layout of
437 * the array/matrix/structure we're trying to fill in.
440 for (unsigned int i
= 0; i
< 4; i
++) {
441 int swiz
= GET_SWZ(element
->swizzle
, i
);
442 if (swiz
== last_swiz
)
446 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
448 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
455 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
457 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
459 fs_reg neg_y
= this->pixel_y
;
461 bool flip
= !ir
->origin_upper_left
^ c
->key
.render_to_fbo
;
464 if (ir
->pixel_center_integer
) {
465 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
467 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
472 if (!flip
&& ir
->pixel_center_integer
) {
473 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
475 fs_reg pixel_y
= this->pixel_y
;
476 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
479 pixel_y
.negate
= true;
480 offset
+= c
->key
.drawable_height
- 1.0;
483 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
488 if (intel
->gen
>= 6) {
489 emit(fs_inst(BRW_OPCODE_MOV
, wpos
,
490 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
492 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
493 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
497 /* gl_FragCoord.w: Already set up in emit_interpolation */
498 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
504 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
506 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
507 /* Interpolation is always in floating point regs. */
508 reg
->type
= BRW_REGISTER_TYPE_F
;
511 unsigned int array_elements
;
512 const glsl_type
*type
;
514 if (ir
->type
->is_array()) {
515 array_elements
= ir
->type
->length
;
516 if (array_elements
== 0) {
519 type
= ir
->type
->fields
.array
;
525 int location
= ir
->location
;
526 for (unsigned int i
= 0; i
< array_elements
; i
++) {
527 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
528 if (urb_setup
[location
] == -1) {
529 /* If there's no incoming setup data for this slot, don't
530 * emit interpolation for it.
532 attr
.reg_offset
+= type
->vector_elements
;
537 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
538 struct brw_reg interp
= interp_reg(location
, c
);
539 emit(fs_inst(FS_OPCODE_LINTERP
,
547 if (intel
->gen
< 6) {
548 attr
.reg_offset
-= type
->vector_elements
;
549 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
550 emit(fs_inst(BRW_OPCODE_MUL
,
565 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
567 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
569 /* The frontfacing comes in as a bit in the thread payload. */
570 if (intel
->gen
>= 6) {
571 emit(fs_inst(BRW_OPCODE_ASR
,
573 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
575 emit(fs_inst(BRW_OPCODE_NOT
,
578 emit(fs_inst(BRW_OPCODE_AND
,
583 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
584 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
587 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
591 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
592 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
599 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src
)
611 assert(!"not reached: bad math opcode");
615 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
616 * might be able to do better by doing execsize = 1 math and then
617 * expanding that result out, but we would need to be careful with
620 * The hardware ignores source modifiers (negate and abs) on math
621 * instructions, so we also move to a temp to set those up.
623 if (intel
->gen
>= 6 && (src
.file
== UNIFORM
||
626 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
627 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src
));
631 fs_inst
*inst
= emit(fs_inst(opcode
, dst
, src
));
633 if (intel
->gen
< 6) {
642 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
647 assert(opcode
== FS_OPCODE_POW
);
649 if (intel
->gen
>= 6) {
650 /* Can't do hstride == 0 args to gen6 math, so expand it out. */
651 if (src0
.file
== UNIFORM
) {
652 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
653 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src0
));
657 if (src1
.file
== UNIFORM
) {
658 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
659 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src1
));
663 inst
= emit(fs_inst(opcode
, dst
, src0
, src1
));
665 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1), src1
));
666 inst
= emit(fs_inst(opcode
, dst
, src0
, reg_null_f
));
668 inst
->base_mrf
= base_mrf
;
675 fs_visitor::visit(ir_variable
*ir
)
679 if (variable_storage(ir
))
682 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
683 this->frag_color
= ir
;
684 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
685 this->frag_data
= ir
;
686 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
687 this->frag_depth
= ir
;
690 if (ir
->mode
== ir_var_in
) {
691 if (!strcmp(ir
->name
, "gl_FragCoord")) {
692 reg
= emit_fragcoord_interpolation(ir
);
693 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
694 reg
= emit_frontfacing_interpolation(ir
);
696 reg
= emit_general_interpolation(ir
);
699 hash_table_insert(this->variable_ht
, reg
, ir
);
703 if (ir
->mode
== ir_var_uniform
) {
704 int param_index
= c
->prog_data
.nr_params
;
706 if (!strncmp(ir
->name
, "gl_", 3)) {
707 setup_builtin_uniform_values(ir
);
709 setup_uniform_values(ir
->location
, ir
->type
);
712 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
713 reg
->type
= brw_type_for_base_type(ir
->type
);
717 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
719 hash_table_insert(this->variable_ht
, reg
, ir
);
723 fs_visitor::visit(ir_dereference_variable
*ir
)
725 fs_reg
*reg
= variable_storage(ir
->var
);
730 fs_visitor::visit(ir_dereference_record
*ir
)
732 const glsl_type
*struct_type
= ir
->record
->type
;
734 ir
->record
->accept(this);
736 unsigned int offset
= 0;
737 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
738 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
740 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
742 this->result
.reg_offset
+= offset
;
743 this->result
.type
= brw_type_for_base_type(ir
->type
);
747 fs_visitor::visit(ir_dereference_array
*ir
)
752 ir
->array
->accept(this);
753 index
= ir
->array_index
->as_constant();
755 element_size
= type_size(ir
->type
);
756 this->result
.type
= brw_type_for_base_type(ir
->type
);
759 assert(this->result
.file
== UNIFORM
||
760 (this->result
.file
== GRF
&&
761 this->result
.reg
!= 0));
762 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
764 assert(!"FINISHME: non-constant array element");
768 /* Instruction selection: Produce a MOV.sat instead of
769 * MIN(MAX(val, 0), 1) when possible.
772 fs_visitor::try_emit_saturate(ir_expression
*ir
)
774 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
779 sat_val
->accept(this);
780 fs_reg src
= this->result
;
782 this->result
= fs_reg(this, ir
->type
);
783 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, src
));
784 inst
->saturate
= true;
790 brw_conditional_for_comparison(unsigned int op
)
794 return BRW_CONDITIONAL_L
;
795 case ir_binop_greater
:
796 return BRW_CONDITIONAL_G
;
797 case ir_binop_lequal
:
798 return BRW_CONDITIONAL_LE
;
799 case ir_binop_gequal
:
800 return BRW_CONDITIONAL_GE
;
802 case ir_binop_all_equal
: /* same as equal for scalars */
803 return BRW_CONDITIONAL_Z
;
804 case ir_binop_nequal
:
805 case ir_binop_any_nequal
: /* same as nequal for scalars */
806 return BRW_CONDITIONAL_NZ
;
808 assert(!"not reached: bad operation for comparison");
809 return BRW_CONDITIONAL_NZ
;
814 fs_visitor::visit(ir_expression
*ir
)
816 unsigned int operand
;
820 assert(ir
->get_num_operands() <= 2);
822 if (try_emit_saturate(ir
))
825 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
826 ir
->operands
[operand
]->accept(this);
827 if (this->result
.file
== BAD_FILE
) {
829 printf("Failed to get tree for expression operand:\n");
830 ir
->operands
[operand
]->accept(&v
);
833 op
[operand
] = this->result
;
835 /* Matrix expression operands should have been broken down to vector
836 * operations already.
838 assert(!ir
->operands
[operand
]->type
->is_matrix());
839 /* And then those vector operands should have been broken down to scalar.
841 assert(!ir
->operands
[operand
]->type
->is_vector());
844 /* Storage for our result. If our result goes into an assignment, it will
845 * just get copy-propagated out, so no worries.
847 this->result
= fs_reg(this, ir
->type
);
849 switch (ir
->operation
) {
850 case ir_unop_logic_not
:
851 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
852 * ones complement of the whole register, not just bit 0.
854 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1)));
857 op
[0].negate
= !op
[0].negate
;
858 this->result
= op
[0];
862 this->result
= op
[0];
865 temp
= fs_reg(this, ir
->type
);
867 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
869 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
870 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
871 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
872 inst
->predicated
= true;
874 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
875 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
876 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
877 inst
->predicated
= true;
881 emit_math(FS_OPCODE_RCP
, this->result
, op
[0]);
885 emit_math(FS_OPCODE_EXP2
, this->result
, op
[0]);
888 emit_math(FS_OPCODE_LOG2
, this->result
, op
[0]);
892 assert(!"not reached: should be handled by ir_explog_to_explog2");
895 case ir_unop_sin_reduced
:
896 emit_math(FS_OPCODE_SIN
, this->result
, op
[0]);
899 case ir_unop_cos_reduced
:
900 emit_math(FS_OPCODE_COS
, this->result
, op
[0]);
904 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
907 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
911 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
914 assert(!"not reached: should be handled by ir_sub_to_add_neg");
918 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
921 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
924 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
928 case ir_binop_greater
:
929 case ir_binop_lequal
:
930 case ir_binop_gequal
:
932 case ir_binop_all_equal
:
933 case ir_binop_nequal
:
934 case ir_binop_any_nequal
:
936 /* original gen4 does implicit conversion before comparison. */
938 temp
.type
= op
[0].type
;
940 inst
= emit(fs_inst(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]));
941 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->operation
);
942 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
945 case ir_binop_logic_xor
:
946 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
949 case ir_binop_logic_or
:
950 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
953 case ir_binop_logic_and
:
954 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
959 assert(!"not reached: should be handled by brw_fs_channel_expressions");
963 assert(!"not reached: should be handled by lower_noise");
966 case ir_quadop_vector
:
967 assert(!"not reached: should be handled by lower_quadop_vector");
971 emit_math(FS_OPCODE_SQRT
, this->result
, op
[0]);
975 emit_math(FS_OPCODE_RSQ
, this->result
, op
[0]);
982 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
987 /* original gen4 does implicit conversion before comparison. */
989 temp
.type
= op
[0].type
;
991 inst
= emit(fs_inst(BRW_OPCODE_CMP
, temp
, op
[0], fs_reg(0.0f
)));
992 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
993 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
,
994 this->result
, fs_reg(1)));
998 emit(fs_inst(BRW_OPCODE_RNDZ
, this->result
, op
[0]));
1001 op
[0].negate
= !op
[0].negate
;
1002 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1003 this->result
.negate
= true;
1006 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1009 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
1011 case ir_unop_round_even
:
1012 emit(fs_inst(BRW_OPCODE_RNDE
, this->result
, op
[0]));
1016 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1017 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1019 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1020 inst
->predicated
= true;
1023 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1024 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1026 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1027 inst
->predicated
= true;
1031 emit_math(FS_OPCODE_POW
, this->result
, op
[0], op
[1]);
1034 case ir_unop_bit_not
:
1035 inst
= emit(fs_inst(BRW_OPCODE_NOT
, this->result
, op
[0]));
1037 case ir_binop_bit_and
:
1038 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
1040 case ir_binop_bit_xor
:
1041 inst
= emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
1043 case ir_binop_bit_or
:
1044 inst
= emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
1048 case ir_binop_lshift
:
1049 case ir_binop_rshift
:
1050 assert(!"GLSL 1.30 features unsupported");
1056 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1057 const glsl_type
*type
, bool predicated
)
1059 switch (type
->base_type
) {
1060 case GLSL_TYPE_FLOAT
:
1061 case GLSL_TYPE_UINT
:
1063 case GLSL_TYPE_BOOL
:
1064 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1065 l
.type
= brw_type_for_base_type(type
);
1066 r
.type
= brw_type_for_base_type(type
);
1068 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1069 inst
->predicated
= predicated
;
1075 case GLSL_TYPE_ARRAY
:
1076 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1077 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1081 case GLSL_TYPE_STRUCT
:
1082 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1083 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1088 case GLSL_TYPE_SAMPLER
:
1092 assert(!"not reached");
1098 fs_visitor::visit(ir_assignment
*ir
)
1103 /* FINISHME: arrays on the lhs */
1104 ir
->lhs
->accept(this);
1107 ir
->rhs
->accept(this);
1110 assert(l
.file
!= BAD_FILE
);
1111 assert(r
.file
!= BAD_FILE
);
1113 if (ir
->condition
) {
1114 emit_bool_to_cond_code(ir
->condition
);
1117 if (ir
->lhs
->type
->is_scalar() ||
1118 ir
->lhs
->type
->is_vector()) {
1119 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1120 if (ir
->write_mask
& (1 << i
)) {
1121 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1123 inst
->predicated
= true;
1129 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1134 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1138 bool simd16
= false;
1144 if (ir
->shadow_comparitor
) {
1145 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1146 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1148 coordinate
.reg_offset
++;
1150 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1153 if (ir
->op
== ir_tex
) {
1154 /* There's no plain shadow compare message, so we use shadow
1155 * compare with a bias of 0.0.
1157 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1160 } else if (ir
->op
== ir_txb
) {
1161 ir
->lod_info
.bias
->accept(this);
1162 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1166 assert(ir
->op
== ir_txl
);
1167 ir
->lod_info
.lod
->accept(this);
1168 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1173 ir
->shadow_comparitor
->accept(this);
1174 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1176 } else if (ir
->op
== ir_tex
) {
1177 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1178 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1180 coordinate
.reg_offset
++;
1182 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1185 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1186 * instructions. We'll need to do SIMD16 here.
1188 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1190 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1191 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2),
1193 coordinate
.reg_offset
++;
1196 /* lod/bias appears after u/v/r. */
1199 if (ir
->op
== ir_txb
) {
1200 ir
->lod_info
.bias
->accept(this);
1201 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1205 ir
->lod_info
.lod
->accept(this);
1206 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1211 /* The unused upper half. */
1214 /* Now, since we're doing simd16, the return is 2 interleaved
1215 * vec4s where the odd-indexed ones are junk. We'll need to move
1216 * this weirdness around to the expected layout.
1220 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1222 dst
.type
= BRW_REGISTER_TYPE_F
;
1225 fs_inst
*inst
= NULL
;
1228 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1231 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1234 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1238 assert(!"GLSL 1.30 features unsupported");
1241 inst
->base_mrf
= base_mrf
;
1245 for (int i
= 0; i
< 4; i
++) {
1246 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1247 orig_dst
.reg_offset
++;
1248 dst
.reg_offset
+= 2;
1256 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1258 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1259 * optional parameters like shadow comparitor or LOD bias. If
1260 * optional parameters aren't present, those base slots are
1261 * optional and don't need to be included in the message.
1263 * We don't fill in the unnecessary slots regardless, which may
1264 * look surprising in the disassembly.
1266 int mlen
= 1; /* g0 header always present. */
1269 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1270 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1272 coordinate
.reg_offset
++;
1274 mlen
+= ir
->coordinate
->type
->vector_elements
;
1276 if (ir
->shadow_comparitor
) {
1277 mlen
= MAX2(mlen
, 5);
1279 ir
->shadow_comparitor
->accept(this);
1280 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1284 fs_inst
*inst
= NULL
;
1287 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1290 ir
->lod_info
.bias
->accept(this);
1291 mlen
= MAX2(mlen
, 5);
1292 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1295 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1298 ir
->lod_info
.lod
->accept(this);
1299 mlen
= MAX2(mlen
, 5);
1300 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1303 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1307 assert(!"GLSL 1.30 features unsupported");
1310 inst
->base_mrf
= base_mrf
;
1317 fs_visitor::visit(ir_texture
*ir
)
1320 fs_inst
*inst
= NULL
;
1322 ir
->coordinate
->accept(this);
1323 fs_reg coordinate
= this->result
;
1325 /* Should be lowered by do_lower_texture_projection */
1326 assert(!ir
->projector
);
1328 sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
1329 ctx
->Shader
.CurrentFragmentProgram
,
1330 &brw
->fragment_program
->Base
);
1331 sampler
= c
->fp
->program
.Base
.SamplerUnits
[sampler
];
1333 /* The 965 requires the EU to do the normalization of GL rectangle
1334 * texture coordinates. We use the program parameter state
1335 * tracking to get the scaling factor.
1337 if (ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1338 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1339 int tokens
[STATE_LENGTH
] = {
1341 STATE_TEXRECT_SCALE
,
1347 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
1349 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
+ 1] =
1352 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1353 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1354 GLuint index
= _mesa_add_state_reference(params
,
1355 (gl_state_index
*)tokens
);
1356 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
1358 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[0];
1359 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[1];
1361 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1362 fs_reg src
= coordinate
;
1365 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_x
));
1368 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_y
));
1371 /* Writemasking doesn't eliminate channels on SIMD8 texture
1372 * samples, so don't worry about them.
1374 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1376 if (intel
->gen
< 5) {
1377 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1379 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1382 inst
->sampler
= sampler
;
1386 if (ir
->shadow_comparitor
)
1387 inst
->shadow_compare
= true;
1389 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1390 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1392 for (int i
= 0; i
< 4; i
++) {
1393 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1394 fs_reg l
= swizzle_dst
;
1397 if (swiz
== SWIZZLE_ZERO
) {
1398 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1399 } else if (swiz
== SWIZZLE_ONE
) {
1400 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1403 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1404 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1407 this->result
= swizzle_dst
;
1412 fs_visitor::visit(ir_swizzle
*ir
)
1414 ir
->val
->accept(this);
1415 fs_reg val
= this->result
;
1417 if (ir
->type
->vector_elements
== 1) {
1418 this->result
.reg_offset
+= ir
->mask
.x
;
1422 fs_reg result
= fs_reg(this, ir
->type
);
1423 this->result
= result
;
1425 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1426 fs_reg channel
= val
;
1444 channel
.reg_offset
+= swiz
;
1445 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1446 result
.reg_offset
++;
1451 fs_visitor::visit(ir_discard
*ir
)
1453 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1455 assert(ir
->condition
== NULL
); /* FINISHME */
1457 emit(fs_inst(FS_OPCODE_DISCARD_NOT
, temp
, reg_null_d
));
1458 emit(fs_inst(FS_OPCODE_DISCARD_AND
, reg_null_d
, temp
));
1459 kill_emitted
= true;
1463 fs_visitor::visit(ir_constant
*ir
)
1465 /* Set this->result to reg at the bottom of the function because some code
1466 * paths will cause this visitor to be applied to other fields. This will
1467 * cause the value stored in this->result to be modified.
1469 * Make reg constant so that it doesn't get accidentally modified along the
1470 * way. Yes, I actually had this problem. :(
1472 const fs_reg
reg(this, ir
->type
);
1473 fs_reg dst_reg
= reg
;
1475 if (ir
->type
->is_array()) {
1476 const unsigned size
= type_size(ir
->type
->fields
.array
);
1478 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1479 ir
->array_elements
[i
]->accept(this);
1480 fs_reg src_reg
= this->result
;
1482 dst_reg
.type
= src_reg
.type
;
1483 for (unsigned j
= 0; j
< size
; j
++) {
1484 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, src_reg
));
1485 src_reg
.reg_offset
++;
1486 dst_reg
.reg_offset
++;
1489 } else if (ir
->type
->is_record()) {
1490 foreach_list(node
, &ir
->components
) {
1491 ir_instruction
*const field
= (ir_instruction
*) node
;
1492 const unsigned size
= type_size(field
->type
);
1494 field
->accept(this);
1495 fs_reg src_reg
= this->result
;
1497 dst_reg
.type
= src_reg
.type
;
1498 for (unsigned j
= 0; j
< size
; j
++) {
1499 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, src_reg
));
1500 src_reg
.reg_offset
++;
1501 dst_reg
.reg_offset
++;
1505 const unsigned size
= type_size(ir
->type
);
1507 for (unsigned i
= 0; i
< size
; i
++) {
1508 switch (ir
->type
->base_type
) {
1509 case GLSL_TYPE_FLOAT
:
1510 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.f
[i
])));
1512 case GLSL_TYPE_UINT
:
1513 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.u
[i
])));
1516 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.i
[i
])));
1518 case GLSL_TYPE_BOOL
:
1519 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg((int)ir
->value
.b
[i
])));
1522 assert(!"Non-float/uint/int/bool constant");
1524 dst_reg
.reg_offset
++;
1532 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1534 ir_expression
*expr
= ir
->as_expression();
1540 assert(expr
->get_num_operands() <= 2);
1541 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1542 assert(expr
->operands
[i
]->type
->is_scalar());
1544 expr
->operands
[i
]->accept(this);
1545 op
[i
] = this->result
;
1548 switch (expr
->operation
) {
1549 case ir_unop_logic_not
:
1550 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1)));
1551 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1554 case ir_binop_logic_xor
:
1555 inst
= emit(fs_inst(BRW_OPCODE_XOR
, reg_null_d
, op
[0], op
[1]));
1556 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1559 case ir_binop_logic_or
:
1560 inst
= emit(fs_inst(BRW_OPCODE_OR
, reg_null_d
, op
[0], op
[1]));
1561 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1564 case ir_binop_logic_and
:
1565 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], op
[1]));
1566 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1570 if (intel
->gen
>= 6) {
1571 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
,
1572 op
[0], fs_reg(0.0f
)));
1574 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_f
, op
[0]));
1576 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1580 if (intel
->gen
>= 6) {
1581 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0)));
1583 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, op
[0]));
1585 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1588 case ir_binop_greater
:
1589 case ir_binop_gequal
:
1591 case ir_binop_lequal
:
1592 case ir_binop_equal
:
1593 case ir_binop_all_equal
:
1594 case ir_binop_nequal
:
1595 case ir_binop_any_nequal
:
1596 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_cmp
, op
[0], op
[1]));
1597 inst
->conditional_mod
=
1598 brw_conditional_for_comparison(expr
->operation
);
1602 assert(!"not reached");
1611 if (intel
->gen
>= 6) {
1612 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
,
1613 this->result
, fs_reg(1)));
1614 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1616 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, this->result
));
1617 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1622 * Emit a gen6 IF statement with the comparison folded into the IF
1626 fs_visitor::emit_if_gen6(ir_if
*ir
)
1628 ir_expression
*expr
= ir
->condition
->as_expression();
1635 assert(expr
->get_num_operands() <= 2);
1636 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1637 assert(expr
->operands
[i
]->type
->is_scalar());
1639 expr
->operands
[i
]->accept(this);
1640 op
[i
] = this->result
;
1643 switch (expr
->operation
) {
1644 case ir_unop_logic_not
:
1645 inst
= emit(fs_inst(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(0)));
1646 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1649 case ir_binop_logic_xor
:
1650 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1651 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1654 case ir_binop_logic_or
:
1655 temp
= fs_reg(this, glsl_type::bool_type
);
1656 emit(fs_inst(BRW_OPCODE_OR
, temp
, op
[0], op
[1]));
1657 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1658 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1661 case ir_binop_logic_and
:
1662 temp
= fs_reg(this, glsl_type::bool_type
);
1663 emit(fs_inst(BRW_OPCODE_AND
, temp
, op
[0], op
[1]));
1664 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1665 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1669 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0)));
1670 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1674 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1675 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1678 case ir_binop_greater
:
1679 case ir_binop_gequal
:
1681 case ir_binop_lequal
:
1682 case ir_binop_equal
:
1683 case ir_binop_all_equal
:
1684 case ir_binop_nequal
:
1685 case ir_binop_any_nequal
:
1686 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1687 inst
->conditional_mod
=
1688 brw_conditional_for_comparison(expr
->operation
);
1691 assert(!"not reached");
1692 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1693 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1700 ir
->condition
->accept(this);
1702 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0)));
1703 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1707 fs_visitor::visit(ir_if
*ir
)
1711 /* Don't point the annotation at the if statement, because then it plus
1712 * the then and else blocks get printed.
1714 this->base_ir
= ir
->condition
;
1716 if (intel
->gen
>= 6) {
1719 emit_bool_to_cond_code(ir
->condition
);
1721 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1722 inst
->predicated
= true;
1725 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1726 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1732 if (!ir
->else_instructions
.is_empty()) {
1733 emit(fs_inst(BRW_OPCODE_ELSE
));
1735 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1736 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1743 emit(fs_inst(BRW_OPCODE_ENDIF
));
1747 fs_visitor::visit(ir_loop
*ir
)
1749 fs_reg counter
= reg_undef
;
1752 this->base_ir
= ir
->counter
;
1753 ir
->counter
->accept(this);
1754 counter
= *(variable_storage(ir
->counter
));
1757 this->base_ir
= ir
->from
;
1758 ir
->from
->accept(this);
1760 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1764 emit(fs_inst(BRW_OPCODE_DO
));
1767 this->base_ir
= ir
->to
;
1768 ir
->to
->accept(this);
1770 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_cmp
,
1771 counter
, this->result
));
1772 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->cmp
);
1774 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1775 inst
->predicated
= true;
1778 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1779 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1785 if (ir
->increment
) {
1786 this->base_ir
= ir
->increment
;
1787 ir
->increment
->accept(this);
1788 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1791 emit(fs_inst(BRW_OPCODE_WHILE
));
1795 fs_visitor::visit(ir_loop_jump
*ir
)
1798 case ir_loop_jump::jump_break
:
1799 emit(fs_inst(BRW_OPCODE_BREAK
));
1801 case ir_loop_jump::jump_continue
:
1802 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1808 fs_visitor::visit(ir_call
*ir
)
1810 assert(!"FINISHME");
1814 fs_visitor::visit(ir_return
*ir
)
1816 assert(!"FINISHME");
1820 fs_visitor::visit(ir_function
*ir
)
1822 /* Ignore function bodies other than main() -- we shouldn't see calls to
1823 * them since they should all be inlined before we get to ir_to_mesa.
1825 if (strcmp(ir
->name
, "main") == 0) {
1826 const ir_function_signature
*sig
;
1829 sig
= ir
->matching_signature(&empty
);
1833 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1834 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1843 fs_visitor::visit(ir_function_signature
*ir
)
1845 assert(!"not reached");
1850 fs_visitor::emit(fs_inst inst
)
1852 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1855 list_inst
->annotation
= this->current_annotation
;
1856 list_inst
->ir
= this->base_ir
;
1858 this->instructions
.push_tail(list_inst
);
1863 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1865 fs_visitor::emit_dummy_fs()
1867 /* Everyone's favorite color. */
1868 emit(fs_inst(BRW_OPCODE_MOV
,
1871 emit(fs_inst(BRW_OPCODE_MOV
,
1874 emit(fs_inst(BRW_OPCODE_MOV
,
1877 emit(fs_inst(BRW_OPCODE_MOV
,
1882 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1885 write
->base_mrf
= 0;
1888 /* The register location here is relative to the start of the URB
1889 * data. It will get adjusted to be a real location before
1890 * generate_code() time.
1893 fs_visitor::interp_reg(int location
, int channel
)
1895 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1896 int stride
= (channel
& 1) * 4;
1898 assert(urb_setup
[location
] != -1);
1900 return brw_vec1_grf(regnr
, stride
);
1903 /** Emits the interpolation for the varying inputs. */
1905 fs_visitor::emit_interpolation_setup_gen4()
1907 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1909 this->current_annotation
= "compute pixel centers";
1910 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1911 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1912 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1913 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1914 emit(fs_inst(BRW_OPCODE_ADD
,
1916 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1917 fs_reg(brw_imm_v(0x10101010))));
1918 emit(fs_inst(BRW_OPCODE_ADD
,
1920 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1921 fs_reg(brw_imm_v(0x11001100))));
1923 this->current_annotation
= "compute pixel deltas from v0";
1925 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1926 this->delta_y
= this->delta_x
;
1927 this->delta_y
.reg_offset
++;
1929 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1930 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1932 emit(fs_inst(BRW_OPCODE_ADD
,
1935 fs_reg(negate(brw_vec1_grf(1, 0)))));
1936 emit(fs_inst(BRW_OPCODE_ADD
,
1939 fs_reg(negate(brw_vec1_grf(1, 1)))));
1941 this->current_annotation
= "compute pos.w and 1/pos.w";
1942 /* Compute wpos.w. It's always in our setup, since it's needed to
1943 * interpolate the other attributes.
1945 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1946 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1947 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1948 /* Compute the pixel 1/W value from wpos.w. */
1949 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1950 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1951 this->current_annotation
= NULL
;
1954 /** Emits the interpolation for the varying inputs. */
1956 fs_visitor::emit_interpolation_setup_gen6()
1958 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1960 /* If the pixel centers end up used, the setup is the same as for gen4. */
1961 this->current_annotation
= "compute pixel centers";
1962 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1963 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1964 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1965 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1966 emit(fs_inst(BRW_OPCODE_ADD
,
1968 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1969 fs_reg(brw_imm_v(0x10101010))));
1970 emit(fs_inst(BRW_OPCODE_ADD
,
1972 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1973 fs_reg(brw_imm_v(0x11001100))));
1975 /* As of gen6, we can no longer mix float and int sources. We have
1976 * to turn the integer pixel centers into floats for their actual
1979 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1980 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1981 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
));
1982 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
));
1984 this->current_annotation
= "compute 1/pos.w";
1985 this->wpos_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
1986 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1987 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1989 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1990 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1992 this->current_annotation
= NULL
;
1996 fs_visitor::emit_fb_writes()
1998 this->current_annotation
= "FB write header";
1999 GLboolean header_present
= GL_TRUE
;
2002 if (intel
->gen
>= 6 &&
2003 !this->kill_emitted
&&
2004 c
->key
.nr_color_regions
== 1) {
2005 header_present
= false;
2008 if (header_present
) {
2013 if (c
->aa_dest_stencil_reg
) {
2014 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2015 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0))));
2018 /* Reserve space for color. It'll be filled in per MRT below. */
2022 if (c
->source_depth_to_render_target
) {
2023 if (c
->computes_depth
) {
2024 /* Hand over gl_FragDepth. */
2025 assert(this->frag_depth
);
2026 fs_reg depth
= *(variable_storage(this->frag_depth
));
2028 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
2030 /* Pass through the payload depth. */
2031 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2032 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
2036 if (c
->dest_depth_reg
) {
2037 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2038 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0))));
2041 fs_reg color
= reg_undef
;
2042 if (this->frag_color
)
2043 color
= *(variable_storage(this->frag_color
));
2044 else if (this->frag_data
) {
2045 color
= *(variable_storage(this->frag_data
));
2046 color
.type
= BRW_REGISTER_TYPE_F
;
2049 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2050 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
2051 "FB write target %d",
2053 if (this->frag_color
|| this->frag_data
) {
2054 for (int i
= 0; i
< 4; i
++) {
2055 emit(fs_inst(BRW_OPCODE_MOV
,
2056 fs_reg(MRF
, color_mrf
+ i
),
2062 if (this->frag_color
)
2063 color
.reg_offset
-= 4;
2065 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
2066 reg_undef
, reg_undef
));
2067 inst
->target
= target
;
2070 if (target
== c
->key
.nr_color_regions
- 1)
2072 inst
->header_present
= header_present
;
2075 if (c
->key
.nr_color_regions
== 0) {
2076 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
2077 reg_undef
, reg_undef
));
2081 inst
->header_present
= header_present
;
2084 this->current_annotation
= NULL
;
2088 fs_visitor::generate_fb_write(fs_inst
*inst
)
2090 GLboolean eot
= inst
->eot
;
2091 struct brw_reg implied_header
;
2093 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
2096 brw_push_insn_state(p
);
2097 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2098 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
2100 if (inst
->header_present
) {
2101 if (intel
->gen
>= 6) {
2103 brw_message_reg(inst
->base_mrf
),
2104 brw_vec8_grf(0, 0));
2106 if (inst
->target
> 0) {
2107 /* Set the render target index for choosing BLEND_STATE. */
2108 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 2),
2109 BRW_REGISTER_TYPE_UD
),
2110 brw_imm_ud(inst
->target
));
2113 /* Clear viewport index, render target array index. */
2114 brw_AND(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 0),
2115 BRW_REGISTER_TYPE_UD
),
2116 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2117 brw_imm_ud(0xf7ff));
2119 implied_header
= brw_null_reg();
2121 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2125 brw_message_reg(inst
->base_mrf
+ 1),
2126 brw_vec8_grf(1, 0));
2128 implied_header
= brw_null_reg();
2131 brw_pop_insn_state(p
);
2134 8, /* dispatch_width */
2135 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
2142 inst
->header_present
);
2146 fs_visitor::generate_linterp(fs_inst
*inst
,
2147 struct brw_reg dst
, struct brw_reg
*src
)
2149 struct brw_reg delta_x
= src
[0];
2150 struct brw_reg delta_y
= src
[1];
2151 struct brw_reg interp
= src
[2];
2154 delta_y
.nr
== delta_x
.nr
+ 1 &&
2155 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
2156 brw_PLN(p
, dst
, interp
, delta_x
);
2158 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
2159 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
2164 fs_visitor::generate_math(fs_inst
*inst
,
2165 struct brw_reg dst
, struct brw_reg
*src
)
2169 switch (inst
->opcode
) {
2171 op
= BRW_MATH_FUNCTION_INV
;
2174 op
= BRW_MATH_FUNCTION_RSQ
;
2176 case FS_OPCODE_SQRT
:
2177 op
= BRW_MATH_FUNCTION_SQRT
;
2179 case FS_OPCODE_EXP2
:
2180 op
= BRW_MATH_FUNCTION_EXP
;
2182 case FS_OPCODE_LOG2
:
2183 op
= BRW_MATH_FUNCTION_LOG
;
2186 op
= BRW_MATH_FUNCTION_POW
;
2189 op
= BRW_MATH_FUNCTION_SIN
;
2192 op
= BRW_MATH_FUNCTION_COS
;
2195 assert(!"not reached: unknown math function");
2200 if (intel
->gen
>= 6) {
2201 assert(inst
->mlen
== 0);
2203 if (inst
->opcode
== FS_OPCODE_POW
) {
2204 brw_math2(p
, dst
, op
, src
[0], src
[1]);
2208 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2209 BRW_MATH_SATURATE_NONE
,
2211 BRW_MATH_DATA_VECTOR
,
2212 BRW_MATH_PRECISION_FULL
);
2215 assert(inst
->mlen
>= 1);
2219 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2220 BRW_MATH_SATURATE_NONE
,
2221 inst
->base_mrf
, src
[0],
2222 BRW_MATH_DATA_VECTOR
,
2223 BRW_MATH_PRECISION_FULL
);
2228 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
)
2232 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2234 if (intel
->gen
>= 5) {
2235 switch (inst
->opcode
) {
2237 if (inst
->shadow_compare
) {
2238 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
2240 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
2244 if (inst
->shadow_compare
) {
2245 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
2247 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
2252 switch (inst
->opcode
) {
2254 /* Note that G45 and older determines shadow compare and dispatch width
2255 * from message length for most messages.
2257 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2258 if (inst
->shadow_compare
) {
2259 assert(inst
->mlen
== 6);
2261 assert(inst
->mlen
<= 4);
2265 if (inst
->shadow_compare
) {
2266 assert(inst
->mlen
== 6);
2267 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2269 assert(inst
->mlen
== 9);
2270 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2271 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2276 assert(msg_type
!= -1);
2278 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2284 retype(dst
, BRW_REGISTER_TYPE_UW
),
2286 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2287 SURF_INDEX_TEXTURE(inst
->sampler
),
2299 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2302 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2304 * and we're trying to produce:
2307 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2308 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2309 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2310 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2311 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2312 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2313 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2314 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2316 * and add another set of two more subspans if in 16-pixel dispatch mode.
2318 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2319 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2320 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2321 * between each other. We could probably do it like ddx and swizzle the right
2322 * order later, but bail for now and just produce
2323 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2326 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2328 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2329 BRW_REGISTER_TYPE_F
,
2330 BRW_VERTICAL_STRIDE_2
,
2332 BRW_HORIZONTAL_STRIDE_0
,
2333 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2334 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2335 BRW_REGISTER_TYPE_F
,
2336 BRW_VERTICAL_STRIDE_2
,
2338 BRW_HORIZONTAL_STRIDE_0
,
2339 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2340 brw_ADD(p
, dst
, src0
, negate(src1
));
2344 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2346 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2347 BRW_REGISTER_TYPE_F
,
2348 BRW_VERTICAL_STRIDE_4
,
2350 BRW_HORIZONTAL_STRIDE_0
,
2351 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2352 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2353 BRW_REGISTER_TYPE_F
,
2354 BRW_VERTICAL_STRIDE_4
,
2356 BRW_HORIZONTAL_STRIDE_0
,
2357 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2358 brw_ADD(p
, dst
, src0
, negate(src1
));
2362 fs_visitor::generate_discard_not(fs_inst
*inst
, struct brw_reg mask
)
2364 if (intel
->gen
>= 6) {
2365 /* Gen6 no longer has the mask reg for us to just read the
2366 * active channels from. However, cmp updates just the channels
2367 * of the flag reg that are enabled, so we can get at the
2368 * channel enables that way. In this step, make a reg of ones
2371 brw_MOV(p
, mask
, brw_imm_ud(1));
2373 brw_push_insn_state(p
);
2374 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2375 brw_NOT(p
, mask
, brw_mask_reg(1)); /* IMASK */
2376 brw_pop_insn_state(p
);
2381 fs_visitor::generate_discard_and(fs_inst
*inst
, struct brw_reg mask
)
2383 if (intel
->gen
>= 6) {
2384 struct brw_reg f0
= brw_flag_reg();
2385 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
2387 brw_push_insn_state(p
);
2388 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2389 brw_MOV(p
, f0
, brw_imm_uw(0xffff)); /* inactive channels undiscarded */
2390 brw_pop_insn_state(p
);
2392 brw_CMP(p
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
),
2393 BRW_CONDITIONAL_Z
, mask
, brw_imm_ud(0)); /* active channels fail test */
2394 /* Undo CMP's whacking of predication*/
2395 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2397 brw_push_insn_state(p
);
2398 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2399 brw_AND(p
, g1
, f0
, g1
);
2400 brw_pop_insn_state(p
);
2402 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2404 mask
= brw_uw1_reg(mask
.file
, mask
.nr
, 0);
2406 brw_push_insn_state(p
);
2407 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2408 brw_AND(p
, g0
, mask
, g0
);
2409 brw_pop_insn_state(p
);
2414 fs_visitor::generate_spill(fs_inst
*inst
, struct brw_reg src
)
2416 assert(inst
->mlen
!= 0);
2419 retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_UD
),
2420 retype(src
, BRW_REGISTER_TYPE_UD
));
2421 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
), 1,
2426 fs_visitor::generate_unspill(fs_inst
*inst
, struct brw_reg dst
)
2428 assert(inst
->mlen
!= 0);
2430 /* Clear any post destination dependencies that would be ignored by
2431 * the block read. See the B-Spec for pre-gen5 send instruction.
2433 * This could use a better solution, since texture sampling and
2434 * math reads could potentially run into it as well -- anywhere
2435 * that we have a SEND with a destination that is a register that
2436 * was written but not read within the last N instructions (what's
2437 * N? unsure). This is rare because of dead code elimination, but
2440 if (intel
->gen
== 4 && !intel
->is_g4x
)
2441 brw_MOV(p
, brw_null_reg(), dst
);
2443 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
), 1,
2446 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2447 /* gen4 errata: destination from a send can't be used as a
2448 * destination until it's been read. Just read it so we don't
2451 brw_MOV(p
, brw_null_reg(), dst
);
2457 fs_visitor::generate_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
)
2459 assert(inst
->mlen
!= 0);
2461 /* Clear any post destination dependencies that would be ignored by
2462 * the block read. See the B-Spec for pre-gen5 send instruction.
2464 * This could use a better solution, since texture sampling and
2465 * math reads could potentially run into it as well -- anywhere
2466 * that we have a SEND with a destination that is a register that
2467 * was written but not read within the last N instructions (what's
2468 * N? unsure). This is rare because of dead code elimination, but
2471 if (intel
->gen
== 4 && !intel
->is_g4x
)
2472 brw_MOV(p
, brw_null_reg(), dst
);
2474 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
2475 inst
->offset
, SURF_INDEX_FRAG_CONST_BUFFER
);
2477 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2478 /* gen4 errata: destination from a send can't be used as a
2479 * destination until it's been read. Just read it so we don't
2482 brw_MOV(p
, brw_null_reg(), dst
);
2487 fs_visitor::assign_curb_setup()
2489 c
->prog_data
.first_curbe_grf
= c
->nr_payload_regs
;
2490 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2492 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2493 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2494 fs_inst
*inst
= (fs_inst
*)iter
.get();
2496 for (unsigned int i
= 0; i
< 3; i
++) {
2497 if (inst
->src
[i
].file
== UNIFORM
) {
2498 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2499 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2503 inst
->src
[i
].file
= FIXED_HW_REG
;
2504 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
2511 fs_visitor::calculate_urb_setup()
2513 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2518 /* Figure out where each of the incoming setup attributes lands. */
2519 if (intel
->gen
>= 6) {
2520 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2521 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
2522 urb_setup
[i
] = urb_next
++;
2526 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2527 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2528 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2531 if (i
>= VERT_RESULT_VAR0
)
2532 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2533 else if (i
<= VERT_RESULT_TEX7
)
2539 urb_setup
[fp_index
] = urb_next
++;
2544 /* Each attribute is 4 setup channels, each of which is half a reg. */
2545 c
->prog_data
.urb_read_length
= urb_next
* 2;
2549 fs_visitor::assign_urb_setup()
2551 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2553 /* Offset all the urb_setup[] index by the actual position of the
2554 * setup regs, now that the location of the constants has been chosen.
2556 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2557 fs_inst
*inst
= (fs_inst
*)iter
.get();
2559 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
2562 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2564 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2567 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2571 * Split large virtual GRFs into separate components if we can.
2573 * This is mostly duplicated with what brw_fs_vector_splitting does,
2574 * but that's really conservative because it's afraid of doing
2575 * splitting that doesn't result in real progress after the rest of
2576 * the optimization phases, which would cause infinite looping in
2577 * optimization. We can do it once here, safely. This also has the
2578 * opportunity to split interpolated values, or maybe even uniforms,
2579 * which we don't have at the IR level.
2581 * We want to split, because virtual GRFs are what we register
2582 * allocate and spill (due to contiguousness requirements for some
2583 * instructions), and they're what we naturally generate in the
2584 * codegen process, but most virtual GRFs don't actually need to be
2585 * contiguous sets of GRFs. If we split, we'll end up with reduced
2586 * live intervals and better dead code elimination and coalescing.
2589 fs_visitor::split_virtual_grfs()
2591 int num_vars
= this->virtual_grf_next
;
2592 bool split_grf
[num_vars
];
2593 int new_virtual_grf
[num_vars
];
2595 /* Try to split anything > 0 sized. */
2596 for (int i
= 0; i
< num_vars
; i
++) {
2597 if (this->virtual_grf_sizes
[i
] != 1)
2598 split_grf
[i
] = true;
2600 split_grf
[i
] = false;
2604 /* PLN opcodes rely on the delta_xy being contiguous. */
2605 split_grf
[this->delta_x
.reg
] = false;
2608 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2609 fs_inst
*inst
= (fs_inst
*)iter
.get();
2611 /* Texturing produces 4 contiguous registers, so no splitting. */
2612 if ((inst
->opcode
== FS_OPCODE_TEX
||
2613 inst
->opcode
== FS_OPCODE_TXB
||
2614 inst
->opcode
== FS_OPCODE_TXL
) &&
2615 inst
->dst
.file
== GRF
) {
2616 split_grf
[inst
->dst
.reg
] = false;
2620 /* Allocate new space for split regs. Note that the virtual
2621 * numbers will be contiguous.
2623 for (int i
= 0; i
< num_vars
; i
++) {
2625 new_virtual_grf
[i
] = virtual_grf_alloc(1);
2626 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
2627 int reg
= virtual_grf_alloc(1);
2628 assert(reg
== new_virtual_grf
[i
] + j
- 1);
2631 this->virtual_grf_sizes
[i
] = 1;
2635 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2636 fs_inst
*inst
= (fs_inst
*)iter
.get();
2638 if (inst
->dst
.file
== GRF
&&
2639 split_grf
[inst
->dst
.reg
] &&
2640 inst
->dst
.reg_offset
!= 0) {
2641 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
2642 inst
->dst
.reg_offset
- 1);
2643 inst
->dst
.reg_offset
= 0;
2645 for (int i
= 0; i
< 3; i
++) {
2646 if (inst
->src
[i
].file
== GRF
&&
2647 split_grf
[inst
->src
[i
].reg
] &&
2648 inst
->src
[i
].reg_offset
!= 0) {
2649 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
2650 inst
->src
[i
].reg_offset
- 1);
2651 inst
->src
[i
].reg_offset
= 0;
2658 * Choose accesses from the UNIFORM file to demote to using the pull
2661 * We allow a fragment shader to have more than the specified minimum
2662 * maximum number of fragment shader uniform components (64). If
2663 * there are too many of these, they'd fill up all of register space.
2664 * So, this will push some of them out to the pull constant buffer and
2665 * update the program to load them.
2668 fs_visitor::setup_pull_constants()
2670 /* Only allow 16 registers (128 uniform components) as push constants. */
2671 unsigned int max_uniform_components
= 16 * 8;
2672 if (c
->prog_data
.nr_params
<= max_uniform_components
)
2675 /* Just demote the end of the list. We could probably do better
2676 * here, demoting things that are rarely used in the program first.
2678 int pull_uniform_base
= max_uniform_components
;
2679 int pull_uniform_count
= c
->prog_data
.nr_params
- pull_uniform_base
;
2681 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2682 fs_inst
*inst
= (fs_inst
*)iter
.get();
2684 for (int i
= 0; i
< 3; i
++) {
2685 if (inst
->src
[i
].file
!= UNIFORM
)
2688 int uniform_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2689 if (uniform_nr
< pull_uniform_base
)
2692 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
2693 fs_inst
*pull
= new(mem_ctx
) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD
,
2695 pull
->offset
= ((uniform_nr
- pull_uniform_base
) * 4) & ~15;
2696 pull
->ir
= inst
->ir
;
2697 pull
->annotation
= inst
->annotation
;
2698 pull
->base_mrf
= 14;
2701 inst
->insert_before(pull
);
2703 inst
->src
[i
].file
= GRF
;
2704 inst
->src
[i
].reg
= dst
.reg
;
2705 inst
->src
[i
].reg_offset
= 0;
2706 inst
->src
[i
].smear
= (uniform_nr
- pull_uniform_base
) & 3;
2710 for (int i
= 0; i
< pull_uniform_count
; i
++) {
2711 c
->prog_data
.pull_param
[i
] = c
->prog_data
.param
[pull_uniform_base
+ i
];
2712 c
->prog_data
.pull_param_convert
[i
] =
2713 c
->prog_data
.param_convert
[pull_uniform_base
+ i
];
2715 c
->prog_data
.nr_params
-= pull_uniform_count
;
2716 c
->prog_data
.nr_pull_params
= pull_uniform_count
;
2720 fs_visitor::calculate_live_intervals()
2722 int num_vars
= this->virtual_grf_next
;
2723 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2724 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2727 int bb_header_ip
= 0;
2729 for (int i
= 0; i
< num_vars
; i
++) {
2735 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2736 fs_inst
*inst
= (fs_inst
*)iter
.get();
2738 if (inst
->opcode
== BRW_OPCODE_DO
) {
2739 if (loop_depth
++ == 0)
2741 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2744 if (loop_depth
== 0) {
2745 /* Patches up the use of vars marked for being live across
2748 for (int i
= 0; i
< num_vars
; i
++) {
2749 if (use
[i
] == loop_start
) {
2755 for (unsigned int i
= 0; i
< 3; i
++) {
2756 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2757 int reg
= inst
->src
[i
].reg
;
2759 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2760 def
[reg
] >= bb_header_ip
)) {
2763 def
[reg
] = MIN2(loop_start
, def
[reg
]);
2764 use
[reg
] = loop_start
;
2766 /* Nobody else is going to go smash our start to
2767 * later in the loop now, because def[reg] now
2768 * points before the bb header.
2773 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2774 int reg
= inst
->dst
.reg
;
2776 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2777 !inst
->predicated
)) {
2778 def
[reg
] = MIN2(def
[reg
], ip
);
2780 def
[reg
] = MIN2(def
[reg
], loop_start
);
2787 /* Set the basic block header IP. This is used for determining
2788 * if a complete def of single-register virtual GRF in a loop
2789 * dominates a use in the same basic block. It's a quick way to
2790 * reduce the live interval range of most register used in a
2793 if (inst
->opcode
== BRW_OPCODE_IF
||
2794 inst
->opcode
== BRW_OPCODE_ELSE
||
2795 inst
->opcode
== BRW_OPCODE_ENDIF
||
2796 inst
->opcode
== BRW_OPCODE_DO
||
2797 inst
->opcode
== BRW_OPCODE_WHILE
||
2798 inst
->opcode
== BRW_OPCODE_BREAK
||
2799 inst
->opcode
== BRW_OPCODE_CONTINUE
) {
2804 talloc_free(this->virtual_grf_def
);
2805 talloc_free(this->virtual_grf_use
);
2806 this->virtual_grf_def
= def
;
2807 this->virtual_grf_use
= use
;
2811 * Attempts to move immediate constants into the immediate
2812 * constant slot of following instructions.
2814 * Immediate constants are a bit tricky -- they have to be in the last
2815 * operand slot, you can't do abs/negate on them,
2819 fs_visitor::propagate_constants()
2821 bool progress
= false;
2823 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2824 fs_inst
*inst
= (fs_inst
*)iter
.get();
2826 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2828 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2829 inst
->dst
.type
!= inst
->src
[0].type
)
2832 /* Don't bother with cases where we should have had the
2833 * operation on the constant folded in GLSL already.
2838 /* Found a move of a constant to a GRF. Find anything else using the GRF
2839 * before it's written, and replace it with the constant if we can.
2841 exec_list_iterator scan_iter
= iter
;
2843 for (; scan_iter
.has_next(); scan_iter
.next()) {
2844 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2846 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2847 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2848 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2849 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2853 for (int i
= 2; i
>= 0; i
--) {
2854 if (scan_inst
->src
[i
].file
!= GRF
||
2855 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2856 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2859 /* Don't bother with cases where we should have had the
2860 * operation on the constant folded in GLSL already.
2862 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2865 switch (scan_inst
->opcode
) {
2866 case BRW_OPCODE_MOV
:
2867 scan_inst
->src
[i
] = inst
->src
[0];
2871 case BRW_OPCODE_MUL
:
2872 case BRW_OPCODE_ADD
:
2874 scan_inst
->src
[i
] = inst
->src
[0];
2876 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2877 /* Fit this constant in by commuting the operands */
2878 scan_inst
->src
[0] = scan_inst
->src
[1];
2879 scan_inst
->src
[1] = inst
->src
[0];
2882 case BRW_OPCODE_CMP
:
2883 case BRW_OPCODE_SEL
:
2885 scan_inst
->src
[i
] = inst
->src
[0];
2891 if (scan_inst
->dst
.file
== GRF
&&
2892 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2893 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2894 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2903 * Must be called after calculate_live_intervales() to remove unused
2904 * writes to registers -- register allocation will fail otherwise
2905 * because something deffed but not used won't be considered to
2906 * interfere with other regs.
2909 fs_visitor::dead_code_eliminate()
2911 bool progress
= false;
2914 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2915 fs_inst
*inst
= (fs_inst
*)iter
.get();
2917 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
2929 fs_visitor::register_coalesce()
2931 bool progress
= false;
2935 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2936 fs_inst
*inst
= (fs_inst
*)iter
.get();
2938 /* Make sure that we dominate the instructions we're going to
2939 * scan for interfering with our coalescing, or we won't have
2940 * scanned enough to see if anything interferes with our
2941 * coalescing. We don't dominate the following instructions if
2942 * we're in a loop or an if block.
2944 switch (inst
->opcode
) {
2948 case BRW_OPCODE_WHILE
:
2954 case BRW_OPCODE_ENDIF
:
2958 if (loop_depth
|| if_depth
)
2961 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2964 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= GRF
||
2965 inst
->dst
.type
!= inst
->src
[0].type
)
2968 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
2969 * them: check for no writes to either one until the exit of the
2972 bool interfered
= false;
2973 exec_list_iterator scan_iter
= iter
;
2975 for (; scan_iter
.has_next(); scan_iter
.next()) {
2976 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2978 if (scan_inst
->dst
.file
== GRF
) {
2979 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2980 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2981 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2985 if (scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
2986 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
2987 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2997 /* Rewrite the later usage to point at the source of the move to
3000 for (exec_list_iterator scan_iter
= iter
; scan_iter
.has_next();
3002 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
3004 for (int i
= 0; i
< 3; i
++) {
3005 if (scan_inst
->src
[i
].file
== GRF
&&
3006 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
3007 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
3008 scan_inst
->src
[i
].reg
= inst
->src
[0].reg
;
3009 scan_inst
->src
[i
].reg_offset
= inst
->src
[0].reg_offset
;
3010 scan_inst
->src
[i
].abs
|= inst
->src
[0].abs
;
3011 scan_inst
->src
[i
].negate
^= inst
->src
[0].negate
;
3012 scan_inst
->src
[i
].smear
= inst
->src
[0].smear
;
3026 fs_visitor::compute_to_mrf()
3028 bool progress
= false;
3031 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3032 fs_inst
*inst
= (fs_inst
*)iter
.get();
3037 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3039 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
3040 inst
->dst
.type
!= inst
->src
[0].type
||
3041 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
3044 /* Can't compute-to-MRF this GRF if someone else was going to
3047 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
3050 /* Found a move of a GRF to a MRF. Let's see if we can go
3051 * rewrite the thing that made this GRF to write into the MRF.
3054 for (scan_inst
= (fs_inst
*)inst
->prev
;
3055 scan_inst
->prev
!= NULL
;
3056 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
3057 if (scan_inst
->dst
.file
== GRF
&&
3058 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
3059 /* Found the last thing to write our reg we want to turn
3060 * into a compute-to-MRF.
3063 if (scan_inst
->opcode
== FS_OPCODE_TEX
) {
3064 /* texturing writes several continuous regs, so we can't
3065 * compute-to-mrf that.
3070 /* If it's predicated, it (probably) didn't populate all
3073 if (scan_inst
->predicated
)
3076 /* SEND instructions can't have MRF as a destination. */
3077 if (scan_inst
->mlen
)
3080 if (intel
->gen
>= 6) {
3081 /* gen6 math instructions must have the destination be
3082 * GRF, so no compute-to-MRF for them.
3084 if (scan_inst
->opcode
== FS_OPCODE_RCP
||
3085 scan_inst
->opcode
== FS_OPCODE_RSQ
||
3086 scan_inst
->opcode
== FS_OPCODE_SQRT
||
3087 scan_inst
->opcode
== FS_OPCODE_EXP2
||
3088 scan_inst
->opcode
== FS_OPCODE_LOG2
||
3089 scan_inst
->opcode
== FS_OPCODE_SIN
||
3090 scan_inst
->opcode
== FS_OPCODE_COS
||
3091 scan_inst
->opcode
== FS_OPCODE_POW
) {
3096 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
3097 /* Found the creator of our MRF's source value. */
3098 scan_inst
->dst
.file
= MRF
;
3099 scan_inst
->dst
.hw_reg
= inst
->dst
.hw_reg
;
3100 scan_inst
->saturate
|= inst
->saturate
;
3107 /* We don't handle flow control here. Most computation of
3108 * values that end up in MRFs are shortly before the MRF
3111 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
3112 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
3113 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
3117 /* You can't read from an MRF, so if someone else reads our
3118 * MRF's source GRF that we wanted to rewrite, that stops us.
3120 bool interfered
= false;
3121 for (int i
= 0; i
< 3; i
++) {
3122 if (scan_inst
->src
[i
].file
== GRF
&&
3123 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
3124 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
3131 if (scan_inst
->dst
.file
== MRF
&&
3132 scan_inst
->dst
.hw_reg
== inst
->dst
.hw_reg
) {
3133 /* Somebody else wrote our MRF here, so we can't can't
3134 * compute-to-MRF before that.
3139 if (scan_inst
->mlen
> 0) {
3140 /* Found a SEND instruction, which means that there are
3141 * live values in MRFs from base_mrf to base_mrf +
3142 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3145 if (inst
->dst
.hw_reg
>= scan_inst
->base_mrf
&&
3146 inst
->dst
.hw_reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
3157 * Walks through basic blocks, locking for repeated MRF writes and
3158 * removing the later ones.
3161 fs_visitor::remove_duplicate_mrf_writes()
3163 fs_inst
*last_mrf_move
[16];
3164 bool progress
= false;
3166 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3168 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3169 fs_inst
*inst
= (fs_inst
*)iter
.get();
3171 switch (inst
->opcode
) {
3173 case BRW_OPCODE_WHILE
:
3175 case BRW_OPCODE_ELSE
:
3176 case BRW_OPCODE_ENDIF
:
3177 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3183 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3184 inst
->dst
.file
== MRF
) {
3185 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.hw_reg
];
3186 if (prev_inst
&& inst
->equals(prev_inst
)) {
3193 /* Clear out the last-write records for MRFs that were overwritten. */
3194 if (inst
->dst
.file
== MRF
) {
3195 last_mrf_move
[inst
->dst
.hw_reg
] = NULL
;
3198 if (inst
->mlen
> 0) {
3199 /* Found a SEND instruction, which will include two of fewer
3200 * implied MRF writes. We could do better here.
3202 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3203 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3207 /* Clear out any MRF move records whose sources got overwritten. */
3208 if (inst
->dst
.file
== GRF
) {
3209 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
3210 if (last_mrf_move
[i
] &&
3211 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
3212 last_mrf_move
[i
] = NULL
;
3217 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3218 inst
->dst
.file
== MRF
&&
3219 inst
->src
[0].file
== GRF
&&
3220 !inst
->predicated
) {
3221 last_mrf_move
[inst
->dst
.hw_reg
] = inst
;
3229 fs_visitor::virtual_grf_interferes(int a
, int b
)
3231 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
3232 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
3234 /* For dead code, just check if the def interferes with the other range. */
3235 if (this->virtual_grf_use
[a
] == -1) {
3236 return (this->virtual_grf_def
[a
] >= this->virtual_grf_def
[b
] &&
3237 this->virtual_grf_def
[a
] < this->virtual_grf_use
[b
]);
3239 if (this->virtual_grf_use
[b
] == -1) {
3240 return (this->virtual_grf_def
[b
] >= this->virtual_grf_def
[a
] &&
3241 this->virtual_grf_def
[b
] < this->virtual_grf_use
[a
]);
3247 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
3249 struct brw_reg brw_reg
;
3251 switch (reg
->file
) {
3255 if (reg
->smear
== -1) {
3256 brw_reg
= brw_vec8_reg(reg
->file
,
3259 brw_reg
= brw_vec1_reg(reg
->file
,
3260 reg
->hw_reg
, reg
->smear
);
3262 brw_reg
= retype(brw_reg
, reg
->type
);
3265 switch (reg
->type
) {
3266 case BRW_REGISTER_TYPE_F
:
3267 brw_reg
= brw_imm_f(reg
->imm
.f
);
3269 case BRW_REGISTER_TYPE_D
:
3270 brw_reg
= brw_imm_d(reg
->imm
.i
);
3272 case BRW_REGISTER_TYPE_UD
:
3273 brw_reg
= brw_imm_ud(reg
->imm
.u
);
3276 assert(!"not reached");
3277 brw_reg
= brw_null_reg();
3282 brw_reg
= reg
->fixed_hw_reg
;
3285 /* Probably unused. */
3286 brw_reg
= brw_null_reg();
3289 assert(!"not reached");
3290 brw_reg
= brw_null_reg();
3293 assert(!"not reached");
3294 brw_reg
= brw_null_reg();
3298 brw_reg
= brw_abs(brw_reg
);
3300 brw_reg
= negate(brw_reg
);
3306 fs_visitor::generate_code()
3308 int last_native_inst
= 0;
3309 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
3310 int if_stack_depth
= 0, loop_stack_depth
= 0;
3311 int if_depth_in_loop
[16];
3312 const char *last_annotation_string
= NULL
;
3313 ir_instruction
*last_annotation_ir
= NULL
;
3315 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3316 printf("Native code for fragment shader %d:\n",
3317 ctx
->Shader
.CurrentFragmentProgram
->Name
);
3320 if_depth_in_loop
[loop_stack_depth
] = 0;
3322 memset(&if_stack
, 0, sizeof(if_stack
));
3323 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3324 fs_inst
*inst
= (fs_inst
*)iter
.get();
3325 struct brw_reg src
[3], dst
;
3327 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3328 if (last_annotation_ir
!= inst
->ir
) {
3329 last_annotation_ir
= inst
->ir
;
3330 if (last_annotation_ir
) {
3332 last_annotation_ir
->print();
3336 if (last_annotation_string
!= inst
->annotation
) {
3337 last_annotation_string
= inst
->annotation
;
3338 if (last_annotation_string
)
3339 printf(" %s\n", last_annotation_string
);
3343 for (unsigned int i
= 0; i
< 3; i
++) {
3344 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
3346 dst
= brw_reg_from_fs_reg(&inst
->dst
);
3348 brw_set_conditionalmod(p
, inst
->conditional_mod
);
3349 brw_set_predicate_control(p
, inst
->predicated
);
3350 brw_set_saturate(p
, inst
->saturate
);
3352 switch (inst
->opcode
) {
3353 case BRW_OPCODE_MOV
:
3354 brw_MOV(p
, dst
, src
[0]);
3356 case BRW_OPCODE_ADD
:
3357 brw_ADD(p
, dst
, src
[0], src
[1]);
3359 case BRW_OPCODE_MUL
:
3360 brw_MUL(p
, dst
, src
[0], src
[1]);
3363 case BRW_OPCODE_FRC
:
3364 brw_FRC(p
, dst
, src
[0]);
3366 case BRW_OPCODE_RNDD
:
3367 brw_RNDD(p
, dst
, src
[0]);
3369 case BRW_OPCODE_RNDE
:
3370 brw_RNDE(p
, dst
, src
[0]);
3372 case BRW_OPCODE_RNDZ
:
3373 brw_RNDZ(p
, dst
, src
[0]);
3376 case BRW_OPCODE_AND
:
3377 brw_AND(p
, dst
, src
[0], src
[1]);
3380 brw_OR(p
, dst
, src
[0], src
[1]);
3382 case BRW_OPCODE_XOR
:
3383 brw_XOR(p
, dst
, src
[0], src
[1]);
3385 case BRW_OPCODE_NOT
:
3386 brw_NOT(p
, dst
, src
[0]);
3388 case BRW_OPCODE_ASR
:
3389 brw_ASR(p
, dst
, src
[0], src
[1]);
3391 case BRW_OPCODE_SHR
:
3392 brw_SHR(p
, dst
, src
[0], src
[1]);
3394 case BRW_OPCODE_SHL
:
3395 brw_SHL(p
, dst
, src
[0], src
[1]);
3398 case BRW_OPCODE_CMP
:
3399 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
3401 case BRW_OPCODE_SEL
:
3402 brw_SEL(p
, dst
, src
[0], src
[1]);
3406 assert(if_stack_depth
< 16);
3407 if (inst
->src
[0].file
!= BAD_FILE
) {
3408 assert(intel
->gen
>= 6);
3409 if_stack
[if_stack_depth
] = brw_IF_gen6(p
, inst
->conditional_mod
, src
[0], src
[1]);
3411 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
3413 if_depth_in_loop
[loop_stack_depth
]++;
3417 case BRW_OPCODE_ELSE
:
3418 if_stack
[if_stack_depth
- 1] =
3419 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
3421 case BRW_OPCODE_ENDIF
:
3423 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
3424 if_depth_in_loop
[loop_stack_depth
]--;
3428 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
3429 if_depth_in_loop
[loop_stack_depth
] = 0;
3432 case BRW_OPCODE_BREAK
:
3433 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
3434 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3436 case BRW_OPCODE_CONTINUE
:
3437 /* FINISHME: We need to write the loop instruction support still. */
3438 if (intel
->gen
>= 6)
3439 brw_CONT_gen6(p
, loop_stack
[loop_stack_depth
- 1]);
3441 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
3442 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3445 case BRW_OPCODE_WHILE
: {
3446 struct brw_instruction
*inst0
, *inst1
;
3449 if (intel
->gen
>= 5)
3452 assert(loop_stack_depth
> 0);
3454 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
3455 if (intel
->gen
< 6) {
3456 /* patch all the BREAK/CONT instructions from last BGNLOOP */
3457 while (inst0
> loop_stack
[loop_stack_depth
]) {
3459 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
3460 inst0
->bits3
.if_else
.jump_count
== 0) {
3461 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
3463 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
3464 inst0
->bits3
.if_else
.jump_count
== 0) {
3465 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
3474 case FS_OPCODE_SQRT
:
3475 case FS_OPCODE_EXP2
:
3476 case FS_OPCODE_LOG2
:
3480 generate_math(inst
, dst
, src
);
3482 case FS_OPCODE_LINTERP
:
3483 generate_linterp(inst
, dst
, src
);
3488 generate_tex(inst
, dst
);
3490 case FS_OPCODE_DISCARD_NOT
:
3491 generate_discard_not(inst
, dst
);
3493 case FS_OPCODE_DISCARD_AND
:
3494 generate_discard_and(inst
, src
[0]);
3497 generate_ddx(inst
, dst
, src
[0]);
3500 generate_ddy(inst
, dst
, src
[0]);
3503 case FS_OPCODE_SPILL
:
3504 generate_spill(inst
, src
[0]);
3507 case FS_OPCODE_UNSPILL
:
3508 generate_unspill(inst
, dst
);
3511 case FS_OPCODE_PULL_CONSTANT_LOAD
:
3512 generate_pull_constant_load(inst
, dst
);
3515 case FS_OPCODE_FB_WRITE
:
3516 generate_fb_write(inst
);
3519 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
3520 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
3521 brw_opcodes
[inst
->opcode
].name
);
3523 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
3528 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3529 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
3531 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3532 ((uint32_t *)&p
->store
[i
])[3],
3533 ((uint32_t *)&p
->store
[i
])[2],
3534 ((uint32_t *)&p
->store
[i
])[1],
3535 ((uint32_t *)&p
->store
[i
])[0]);
3537 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3541 last_native_inst
= p
->nr_insn
;
3546 /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
3547 * emit issues, it doesn't get the jump distances into the output,
3548 * which is often something we want to debug. So this is here in
3549 * case you're doing that.
3552 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3553 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
3554 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3555 ((uint32_t *)&p
->store
[i
])[3],
3556 ((uint32_t *)&p
->store
[i
])[2],
3557 ((uint32_t *)&p
->store
[i
])[1],
3558 ((uint32_t *)&p
->store
[i
])[0]);
3559 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3566 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
3568 struct intel_context
*intel
= &brw
->intel
;
3569 struct gl_context
*ctx
= &intel
->ctx
;
3570 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentFragmentProgram
;
3575 struct brw_shader
*shader
=
3576 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3580 /* We always use 8-wide mode, at least for now. For one, flow
3581 * control only works in 8-wide. Also, when we're fragment shader
3582 * bound, we're almost always under register pressure as well, so
3583 * 8-wide would save us from the performance cliff of spilling
3586 c
->dispatch_width
= 8;
3588 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3589 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3590 _mesa_print_ir(shader
->ir
, NULL
);
3594 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3596 fs_visitor
v(c
, shader
);
3601 v
.calculate_urb_setup();
3603 v
.emit_interpolation_setup_gen4();
3605 v
.emit_interpolation_setup_gen6();
3607 /* Generate FS IR for main(). (the visitor only descends into
3608 * functions called "main").
3610 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
3611 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
3618 v
.split_virtual_grfs();
3619 v
.setup_pull_constants();
3621 v
.assign_curb_setup();
3622 v
.assign_urb_setup();
3628 progress
= v
.remove_duplicate_mrf_writes() || progress
;
3630 v
.calculate_live_intervals();
3631 progress
= v
.propagate_constants() || progress
;
3632 progress
= v
.register_coalesce() || progress
;
3633 v
.calculate_live_intervals();
3634 progress
= v
.compute_to_mrf() || progress
;
3635 progress
= v
.dead_code_eliminate() || progress
;
3639 /* Debug of register spilling: Go spill everything. */
3640 int virtual_grf_count
= v
.virtual_grf_next
;
3641 for (int i
= 1; i
< virtual_grf_count
; i
++) {
3644 v
.calculate_live_intervals();
3648 v
.assign_regs_trivial();
3650 while (!v
.assign_regs()) {
3654 v
.calculate_live_intervals();
3662 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3667 c
->prog_data
.total_grf
= v
.grf_used
;