2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "program/prog_parameter.h"
35 #include "program/prog_print.h"
36 #include "program/prog_optimize.h"
37 #include "program/hash_table.h"
38 #include "brw_context.h"
43 #include "../glsl/glsl_types.h"
44 #include "../glsl/ir_optimization.h"
45 #include "../glsl/ir_print_visitor.h"
48 ARF
= BRW_ARCHITECTURE_REGISTER_FILE
,
49 GRF
= BRW_GENERAL_REGISTER_FILE
,
50 MRF
= BRW_MESSAGE_REGISTER_FILE
,
51 IMM
= BRW_IMMEDIATE_VALUE
,
52 FIXED_HW_REG
, /* a struct brw_reg */
53 UNIFORM
, /* prog_data->params[hw_reg] */
58 FS_OPCODE_FB_WRITE
= 256,
75 static int using_new_fs
= -1;
78 brw_new_shader(GLcontext
*ctx
, GLuint name
, GLuint type
)
80 struct brw_shader
*shader
;
82 shader
= talloc_zero(NULL
, struct brw_shader
);
84 shader
->base
.Type
= type
;
85 shader
->base
.Name
= name
;
86 _mesa_init_shader(ctx
, &shader
->base
);
92 struct gl_shader_program
*
93 brw_new_shader_program(GLcontext
*ctx
, GLuint name
)
95 struct brw_shader_program
*prog
;
96 prog
= talloc_zero(NULL
, struct brw_shader_program
);
98 prog
->base
.Name
= name
;
99 _mesa_init_shader_program(ctx
, &prog
->base
);
105 brw_compile_shader(GLcontext
*ctx
, struct gl_shader
*shader
)
107 if (!_mesa_ir_compile_shader(ctx
, shader
))
114 brw_link_shader(GLcontext
*ctx
, struct gl_shader_program
*prog
)
116 if (using_new_fs
== -1)
117 using_new_fs
= getenv("INTEL_NEW_FS") != NULL
;
119 for (unsigned i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
120 struct brw_shader
*shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
122 if (using_new_fs
&& shader
->base
.Type
== GL_FRAGMENT_SHADER
) {
123 void *mem_ctx
= talloc_new(NULL
);
127 talloc_free(shader
->ir
);
128 shader
->ir
= new(shader
) exec_list
;
129 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
131 do_mat_op_to_vec(shader
->ir
);
132 do_mod_to_fract(shader
->ir
);
133 do_div_to_mul_rcp(shader
->ir
);
134 do_sub_to_add_neg(shader
->ir
);
135 do_explog_to_explog2(shader
->ir
);
137 brw_do_channel_expressions(shader
->ir
);
138 brw_do_vector_splitting(shader
->ir
);
143 progress
= do_common_optimization(shader
->ir
, true) || progress
;
146 validate_ir_tree(shader
->ir
);
148 reparent_ir(shader
->ir
, shader
->ir
);
149 talloc_free(mem_ctx
);
153 if (!_mesa_ir_link_shader(ctx
, prog
))
160 type_size(const struct glsl_type
*type
)
162 unsigned int size
, i
;
164 switch (type
->base_type
) {
167 case GLSL_TYPE_FLOAT
:
169 return type
->components();
170 case GLSL_TYPE_ARRAY
:
171 /* FINISHME: uniform/varying arrays. */
172 return type_size(type
->fields
.array
) * type
->length
;
173 case GLSL_TYPE_STRUCT
:
175 for (i
= 0; i
< type
->length
; i
++) {
176 size
+= type_size(type
->fields
.structure
[i
].type
);
179 case GLSL_TYPE_SAMPLER
:
180 /* Samplers take up no register space, since they're baked in at
185 assert(!"not reached");
192 /* Callers of this talloc-based new need not call delete. It's
193 * easier to just talloc_free 'ctx' (or any of its ancestors). */
194 static void* operator new(size_t size
, void *ctx
)
198 node
= talloc_size(ctx
, size
);
199 assert(node
!= NULL
);
204 /** Generic unset register constructor. */
207 this->file
= BAD_FILE
;
209 this->reg_offset
= 0;
215 /** Immediate value constructor. */
221 this->type
= BRW_REGISTER_TYPE_F
;
227 /** Immediate value constructor. */
233 this->type
= BRW_REGISTER_TYPE_D
;
239 /** Immediate value constructor. */
245 this->type
= BRW_REGISTER_TYPE_UD
;
251 /** Fixed brw_reg Immediate value constructor. */
252 fs_reg(struct brw_reg fixed_hw_reg
)
254 this->file
= FIXED_HW_REG
;
255 this->fixed_hw_reg
= fixed_hw_reg
;
258 this->type
= fixed_hw_reg
.type
;
263 fs_reg(enum register_file file
, int hw_reg
);
264 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
266 /** Register file: ARF, GRF, MRF, IMM. */
267 enum register_file file
;
268 /** Abstract register number. 0 = fixed hw reg */
270 /** Offset within the abstract register. */
272 /** HW register number. Generally unset until register allocation. */
274 /** Register type. BRW_REGISTER_TYPE_* */
278 struct brw_reg fixed_hw_reg
;
280 /** Value for file == BRW_IMMMEDIATE_FILE */
288 static const fs_reg reg_undef
;
289 static const fs_reg
reg_null(ARF
, BRW_ARF_NULL
);
291 class fs_inst
: public exec_node
{
293 /* Callers of this talloc-based new need not call delete. It's
294 * easier to just talloc_free 'ctx' (or any of its ancestors). */
295 static void* operator new(size_t size
, void *ctx
)
299 node
= talloc_zero_size(ctx
, size
);
300 assert(node
!= NULL
);
307 this->opcode
= BRW_OPCODE_NOP
;
308 this->saturate
= false;
309 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
310 this->predicated
= false;
312 this->shadow_compare
= false;
323 this->opcode
= opcode
;
326 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
)
329 this->opcode
= opcode
;
334 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
337 this->opcode
= opcode
;
343 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg src2
)
346 this->opcode
= opcode
;
353 int opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
358 int conditional_mod
; /**< BRW_CONDITIONAL_* */
360 int mlen
; /** SEND message length */
365 * Annotation for the generated IR. One of the two can be set.
368 const char *annotation
;
372 class fs_visitor
: public ir_visitor
376 fs_visitor(struct brw_wm_compile
*c
, struct brw_shader
*shader
)
381 this->intel
= &brw
->intel
;
382 this->ctx
= &intel
->ctx
;
383 this->mem_ctx
= talloc_new(NULL
);
384 this->shader
= shader
;
386 this->next_abstract_grf
= 1;
387 this->variable_ht
= hash_table_ctor(0,
388 hash_table_pointer_hash
,
389 hash_table_pointer_compare
);
391 this->frag_color
= NULL
;
392 this->frag_data
= NULL
;
393 this->frag_depth
= NULL
;
394 this->first_non_payload_grf
= 0;
396 this->current_annotation
= NULL
;
397 this->annotation_string
= NULL
;
398 this->annotation_ir
= NULL
;
402 talloc_free(this->mem_ctx
);
403 hash_table_dtor(this->variable_ht
);
406 fs_reg
*variable_storage(ir_variable
*var
);
408 void visit(ir_variable
*ir
);
409 void visit(ir_assignment
*ir
);
410 void visit(ir_dereference_variable
*ir
);
411 void visit(ir_dereference_record
*ir
);
412 void visit(ir_dereference_array
*ir
);
413 void visit(ir_expression
*ir
);
414 void visit(ir_texture
*ir
);
415 void visit(ir_if
*ir
);
416 void visit(ir_constant
*ir
);
417 void visit(ir_swizzle
*ir
);
418 void visit(ir_return
*ir
);
419 void visit(ir_loop
*ir
);
420 void visit(ir_loop_jump
*ir
);
421 void visit(ir_discard
*ir
);
422 void visit(ir_call
*ir
);
423 void visit(ir_function
*ir
);
424 void visit(ir_function_signature
*ir
);
426 fs_inst
*emit(fs_inst inst
);
427 void assign_curb_setup();
428 void assign_urb_setup();
430 void generate_code();
431 void generate_fb_write(fs_inst
*inst
);
432 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
433 struct brw_reg
*src
);
434 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
435 void generate_math(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg
*src
);
437 void emit_dummy_fs();
438 void emit_interpolation();
439 void emit_pinterp(int location
);
440 void emit_fb_writes();
442 struct brw_reg
interp_reg(int location
, int channel
);
444 struct brw_context
*brw
;
445 struct intel_context
*intel
;
447 struct brw_wm_compile
*c
;
448 struct brw_compile
*p
;
449 struct brw_shader
*shader
;
451 exec_list instructions
;
452 int next_abstract_grf
;
453 struct hash_table
*variable_ht
;
454 ir_variable
*frag_color
, *frag_data
, *frag_depth
;
455 int first_non_payload_grf
;
457 /** @{ debug annotation info */
458 const char *current_annotation
;
459 ir_instruction
*base_ir
;
460 const char **annotation_string
;
461 ir_instruction
**annotation_ir
;
466 /* Result of last visit() method. */
474 fs_reg interp_attrs
[64];
480 /** Fixed HW reg constructor. */
481 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
485 this->reg_offset
= 0;
486 this->hw_reg
= hw_reg
;
487 this->type
= BRW_REGISTER_TYPE_F
;
492 /** Automatic reg constructor. */
493 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
496 this->reg
= v
->next_abstract_grf
;
497 this->reg_offset
= 0;
498 v
->next_abstract_grf
+= type_size(type
);
503 switch (type
->base_type
) {
504 case GLSL_TYPE_FLOAT
:
505 this->type
= BRW_REGISTER_TYPE_F
;
509 this->type
= BRW_REGISTER_TYPE_D
;
512 this->type
= BRW_REGISTER_TYPE_UD
;
515 assert(!"not reached");
516 this->type
= BRW_REGISTER_TYPE_F
;
522 fs_visitor::variable_storage(ir_variable
*var
)
524 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
528 fs_visitor::visit(ir_variable
*ir
)
532 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
533 this->frag_color
= ir
;
534 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
535 this->frag_data
= ir
;
536 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
537 this->frag_depth
= ir
;
538 assert(!"FINISHME: this hangs currently.");
541 if (ir
->mode
== ir_var_in
) {
542 reg
= &this->interp_attrs
[ir
->location
];
545 if (ir
->mode
== ir_var_uniform
) {
546 const float *vec_values
;
547 int param_index
= c
->prog_data
.nr_params
;
549 /* FINISHME: This is wildly incomplete. */
550 assert(ir
->type
->is_scalar() || ir
->type
->is_vector() ||
551 ir
->type
->is_sampler());
553 const struct gl_program
*fp
= &this->brw
->fragment_program
->Base
;
554 /* Our support for uniforms is piggy-backed on the struct
555 * gl_fragment_program, because that's where the values actually
556 * get stored, rather than in some global gl_shader_program uniform
559 vec_values
= fp
->Parameters
->ParameterValues
[ir
->location
];
560 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
561 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
564 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
568 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
570 hash_table_insert(this->variable_ht
, reg
, ir
);
574 fs_visitor::visit(ir_dereference_variable
*ir
)
576 fs_reg
*reg
= variable_storage(ir
->var
);
581 fs_visitor::visit(ir_dereference_record
*ir
)
587 fs_visitor::visit(ir_dereference_array
*ir
)
592 ir
->array
->accept(this);
593 index
= ir
->array_index
->as_constant();
595 if (ir
->type
->is_matrix()) {
596 element_size
= ir
->type
->vector_elements
;
598 element_size
= type_size(ir
->type
);
602 assert(this->result
.file
== UNIFORM
||
603 (this->result
.file
== GRF
&&
604 this->result
.reg
!= 0));
605 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
607 assert(!"FINISHME: non-constant matrix column");
612 fs_visitor::visit(ir_expression
*ir
)
614 unsigned int operand
;
619 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
620 ir
->operands
[operand
]->accept(this);
621 if (this->result
.file
== BAD_FILE
) {
623 printf("Failed to get tree for expression operand:\n");
624 ir
->operands
[operand
]->accept(&v
);
627 op
[operand
] = this->result
;
629 /* Matrix expression operands should have been broken down to vector
630 * operations already.
632 assert(!ir
->operands
[operand
]->type
->is_matrix());
633 /* And then those vector operands should have been broken down to scalar.
635 assert(!ir
->operands
[operand
]->type
->is_vector());
638 /* Storage for our result. If our result goes into an assignment, it will
639 * just get copy-propagated out, so no worries.
641 this->result
= fs_reg(this, ir
->type
);
643 switch (ir
->operation
) {
644 case ir_unop_logic_not
:
645 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], fs_reg(-1)));
648 op
[0].negate
= ~op
[0].negate
;
649 this->result
= op
[0];
653 this->result
= op
[0];
656 temp
= fs_reg(this, ir
->type
);
658 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
660 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
661 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
662 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
663 inst
->predicated
= true;
665 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
666 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
667 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
668 inst
->predicated
= true;
672 emit(fs_inst(FS_OPCODE_RCP
, this->result
, op
[0]));
676 emit(fs_inst(FS_OPCODE_EXP2
, this->result
, op
[0]));
679 emit(fs_inst(FS_OPCODE_LOG2
, this->result
, op
[0]));
683 assert(!"not reached: should be handled by ir_explog_to_explog2");
686 emit(fs_inst(FS_OPCODE_SIN
, this->result
, op
[0]));
689 emit(fs_inst(FS_OPCODE_COS
, this->result
, op
[0]));
693 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
696 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
700 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
703 assert(!"not reached: should be handled by ir_sub_to_add_neg");
707 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
710 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
713 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
717 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
718 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
719 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
721 case ir_binop_greater
:
722 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
723 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
724 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
726 case ir_binop_lequal
:
727 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
728 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
729 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
731 case ir_binop_gequal
:
732 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
733 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
734 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
737 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
738 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
739 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
741 case ir_binop_nequal
:
742 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
743 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
744 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
747 case ir_binop_logic_xor
:
748 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
751 case ir_binop_logic_or
:
752 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
755 case ir_binop_logic_and
:
756 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
762 assert(!"not reached: should be handled by brw_channel_expressions");
766 emit(fs_inst(FS_OPCODE_SQRT
, this->result
, op
[0]));
770 emit(fs_inst(FS_OPCODE_RSQ
, this->result
, op
[0]));
776 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
779 emit(fs_inst(BRW_OPCODE_RNDZ
, this->result
, op
[0]));
783 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
784 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
787 emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
790 op
[0].negate
= ~op
[0].negate
;
791 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
792 this->result
.negate
= true;
795 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
798 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
802 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
803 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
805 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
806 inst
->predicated
= true;
809 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
810 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
812 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
813 inst
->predicated
= true;
817 inst
= emit(fs_inst(FS_OPCODE_POW
, this->result
, op
[0], op
[1]));
820 case ir_unop_bit_not
:
822 case ir_binop_lshift
:
823 case ir_binop_rshift
:
824 case ir_binop_bit_and
:
825 case ir_binop_bit_xor
:
826 case ir_binop_bit_or
:
827 assert(!"GLSL 1.30 features unsupported");
833 fs_visitor::visit(ir_assignment
*ir
)
840 /* FINISHME: arrays on the lhs */
841 ir
->lhs
->accept(this);
844 ir
->rhs
->accept(this);
847 /* FINISHME: This should really set to the correct maximal writemask for each
848 * FINISHME: component written (in the loops below). This case can only
849 * FINISHME: occur for matrices, arrays, and structures.
851 if (ir
->write_mask
== 0) {
852 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
853 write_mask
= WRITEMASK_XYZW
;
855 assert(ir
->lhs
->type
->is_vector() || ir
->lhs
->type
->is_scalar());
856 write_mask
= ir
->write_mask
;
859 assert(l
.file
!= BAD_FILE
);
860 assert(r
.file
!= BAD_FILE
);
863 /* Get the condition bool into the predicate. */
864 ir
->condition
->accept(this);
865 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, fs_reg(0)));
866 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
869 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
870 if (i
>= 4 || (write_mask
& (1 << i
))) {
871 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
873 inst
->predicated
= true;
881 fs_visitor::visit(ir_texture
*ir
)
884 fs_inst
*inst
= NULL
;
885 unsigned int mlen
= 0;
887 ir
->coordinate
->accept(this);
888 fs_reg coordinate
= this->result
;
891 fs_reg inv_proj
= fs_reg(this, glsl_type::float_type
);
893 ir
->projector
->accept(this);
894 emit(fs_inst(FS_OPCODE_RCP
, inv_proj
, this->result
));
896 fs_reg proj_coordinate
= fs_reg(this, ir
->coordinate
->type
);
897 for (unsigned int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
898 emit(fs_inst(BRW_OPCODE_MUL
, proj_coordinate
, coordinate
, inv_proj
));
899 coordinate
.reg_offset
++;
900 proj_coordinate
.reg_offset
++;
902 proj_coordinate
.reg_offset
= 0;
904 coordinate
= proj_coordinate
;
907 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
908 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
909 coordinate
.reg_offset
++;
912 /* Pre-Ironlake, the 8-wide sampler always took u,v,r. */
916 if (ir
->shadow_comparitor
) {
917 /* For shadow comparisons, we have to supply u,v,r. */
920 ir
->shadow_comparitor
->accept(this);
921 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
925 /* Do we ever want to handle writemasking on texture samples? Is it
926 * performance relevant?
928 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
932 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
935 ir
->lod_info
.bias
->accept(this);
936 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
939 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
, fs_reg(MRF
, base_mrf
)));
942 ir
->lod_info
.lod
->accept(this);
943 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
946 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
, fs_reg(MRF
, base_mrf
)));
950 assert(!"GLSL 1.30 features unsupported");
956 if (ir
->shadow_comparitor
)
957 inst
->shadow_compare
= true;
962 fs_visitor::visit(ir_swizzle
*ir
)
964 ir
->val
->accept(this);
965 fs_reg val
= this->result
;
967 fs_reg result
= fs_reg(this, ir
->type
);
968 this->result
= result
;
970 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
971 fs_reg channel
= val
;
989 channel
.reg_offset
+= swiz
;
990 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
996 fs_visitor::visit(ir_discard
*ir
)
1002 fs_visitor::visit(ir_constant
*ir
)
1004 fs_reg
reg(this, ir
->type
);
1007 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1008 switch (ir
->type
->base_type
) {
1009 case GLSL_TYPE_FLOAT
:
1010 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
1012 case GLSL_TYPE_UINT
:
1013 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1016 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1018 case GLSL_TYPE_BOOL
:
1019 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1022 assert(!"Non-float/uint/int/bool constant");
1029 fs_visitor::visit(ir_if
*ir
)
1033 /* Don't point the annotation at the if statement, because then it plus
1034 * the then and else blocks get printed.
1036 this->base_ir
= ir
->condition
;
1038 /* Generate the condition into the condition code. */
1039 ir
->condition
->accept(this);
1040 inst
= emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(brw_null_reg()), this->result
));
1041 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1043 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1044 inst
->predicated
= true;
1046 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1047 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1053 if (!ir
->else_instructions
.is_empty()) {
1054 emit(fs_inst(BRW_OPCODE_ELSE
));
1056 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1057 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1064 emit(fs_inst(BRW_OPCODE_ENDIF
));
1068 fs_visitor::visit(ir_loop
*ir
)
1070 assert(!"FINISHME");
1074 fs_visitor::visit(ir_loop_jump
*ir
)
1076 assert(!"FINISHME");
1080 fs_visitor::visit(ir_call
*ir
)
1082 assert(!"FINISHME");
1086 fs_visitor::visit(ir_return
*ir
)
1088 assert(!"FINISHME");
1092 fs_visitor::visit(ir_function
*ir
)
1094 /* Ignore function bodies other than main() -- we shouldn't see calls to
1095 * them since they should all be inlined before we get to ir_to_mesa.
1097 if (strcmp(ir
->name
, "main") == 0) {
1098 const ir_function_signature
*sig
;
1101 sig
= ir
->matching_signature(&empty
);
1105 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1106 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1115 fs_visitor::visit(ir_function_signature
*ir
)
1117 assert(!"not reached");
1122 fs_visitor::emit(fs_inst inst
)
1124 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1127 list_inst
->annotation
= this->current_annotation
;
1128 list_inst
->ir
= this->base_ir
;
1130 this->instructions
.push_tail(list_inst
);
1135 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1137 fs_visitor::emit_dummy_fs()
1139 /* Everyone's favorite color. */
1140 emit(fs_inst(BRW_OPCODE_MOV
,
1143 emit(fs_inst(BRW_OPCODE_MOV
,
1146 emit(fs_inst(BRW_OPCODE_MOV
,
1149 emit(fs_inst(BRW_OPCODE_MOV
,
1154 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1159 /* The register location here is relative to the start of the URB
1160 * data. It will get adjusted to be a real location before
1161 * generate_code() time.
1164 fs_visitor::interp_reg(int location
, int channel
)
1166 int regnr
= location
* 2 + channel
/ 2;
1167 int stride
= (channel
& 1) * 4;
1169 return brw_vec1_grf(regnr
, stride
);
1172 /** Emits the interpolation for the varying inputs. */
1174 fs_visitor::emit_interpolation()
1176 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1177 /* For now, the source regs for the setup URB data will be unset,
1178 * since we don't know until codegen how many push constants we'll
1179 * use, and therefore what the setup URB offset is.
1181 fs_reg src_reg
= reg_undef
;
1183 this->current_annotation
= "compute pixel centers";
1184 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1185 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1186 emit(fs_inst(BRW_OPCODE_ADD
,
1188 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1189 fs_reg(brw_imm_v(0x10101010))));
1190 emit(fs_inst(BRW_OPCODE_ADD
,
1192 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1193 fs_reg(brw_imm_v(0x11001100))));
1195 this->current_annotation
= "compute pixel deltas from v0";
1196 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1197 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1198 emit(fs_inst(BRW_OPCODE_ADD
,
1201 fs_reg(negate(brw_vec1_grf(1, 0)))));
1202 emit(fs_inst(BRW_OPCODE_ADD
,
1205 fs_reg(brw_vec1_grf(1, 1))));
1207 this->current_annotation
= "compute pos.w and 1/pos.w";
1208 /* Compute wpos. Unlike many other varying inputs, we usually need it
1209 * to produce 1/w, and the varying variable wouldn't show up.
1211 fs_reg wpos
= fs_reg(this, glsl_type::vec4_type
);
1212 this->interp_attrs
[FRAG_ATTRIB_WPOS
] = wpos
;
1213 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
)); /* FINISHME: ARB_fcc */
1215 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
)); /* FINISHME: ARB_fcc */
1217 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
1218 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
1220 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
1221 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1222 /* Compute the pixel W value from wpos.w. */
1223 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1224 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos
));
1226 /* FINISHME: gl_FrontFacing */
1228 foreach_iter(exec_list_iterator
, iter
, *this->shader
->ir
) {
1229 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1230 ir_variable
*var
= ir
->as_variable();
1235 if (var
->mode
!= ir_var_in
)
1238 /* If it's already set up (WPOS), skip. */
1239 if (var
->location
== 0)
1242 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1244 "(FRAG_ATTRIB[%d])",
1247 emit_pinterp(var
->location
);
1249 this->current_annotation
= NULL
;
1253 fs_visitor::emit_pinterp(int location
)
1255 fs_reg interp_attr
= fs_reg(this, glsl_type::vec4_type
);
1256 this->interp_attrs
[location
] = interp_attr
;
1258 for (unsigned int i
= 0; i
< 4; i
++) {
1259 struct brw_reg interp
= interp_reg(location
, i
);
1260 emit(fs_inst(FS_OPCODE_LINTERP
,
1265 interp_attr
.reg_offset
++;
1267 interp_attr
.reg_offset
-= 4;
1269 for (unsigned int i
= 0; i
< 4; i
++) {
1270 emit(fs_inst(BRW_OPCODE_MUL
,
1274 interp_attr
.reg_offset
++;
1279 fs_visitor::emit_fb_writes()
1281 this->current_annotation
= "FB write";
1283 assert(this->frag_color
|| !"FINISHME: MRT");
1284 fs_reg color
= *(variable_storage(this->frag_color
));
1286 for (int i
= 0; i
< 4; i
++) {
1287 emit(fs_inst(BRW_OPCODE_MOV
,
1293 emit(fs_inst(FS_OPCODE_FB_WRITE
,
1297 this->current_annotation
= NULL
;
1301 fs_visitor::generate_fb_write(fs_inst
*inst
)
1303 GLboolean eot
= 1; /* FINISHME: MRT */
1304 /* FINISHME: AADS */
1306 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1309 brw_push_insn_state(p
);
1310 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1311 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1314 brw_vec8_grf(1, 0));
1315 brw_pop_insn_state(p
);
1320 8, /* dispatch_width */
1321 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
1323 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
1324 0, /* FINISHME: MRT target */
1331 fs_visitor::generate_linterp(fs_inst
*inst
,
1332 struct brw_reg dst
, struct brw_reg
*src
)
1334 struct brw_reg delta_x
= src
[0];
1335 struct brw_reg delta_y
= src
[1];
1336 struct brw_reg interp
= src
[2];
1339 delta_y
.nr
== delta_x
.nr
+ 1 &&
1340 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
1341 brw_PLN(p
, dst
, interp
, delta_x
);
1343 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
1344 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
1349 fs_visitor::generate_math(fs_inst
*inst
,
1350 struct brw_reg dst
, struct brw_reg
*src
)
1354 switch (inst
->opcode
) {
1356 op
= BRW_MATH_FUNCTION_INV
;
1359 op
= BRW_MATH_FUNCTION_RSQ
;
1361 case FS_OPCODE_SQRT
:
1362 op
= BRW_MATH_FUNCTION_SQRT
;
1364 case FS_OPCODE_EXP2
:
1365 op
= BRW_MATH_FUNCTION_EXP
;
1367 case FS_OPCODE_LOG2
:
1368 op
= BRW_MATH_FUNCTION_LOG
;
1371 op
= BRW_MATH_FUNCTION_POW
;
1374 op
= BRW_MATH_FUNCTION_SIN
;
1377 op
= BRW_MATH_FUNCTION_COS
;
1380 assert(!"not reached: unknown math function");
1385 if (inst
->opcode
== FS_OPCODE_POW
) {
1386 brw_MOV(p
, brw_message_reg(3), src
[1]);
1391 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
1392 BRW_MATH_SATURATE_NONE
,
1394 BRW_MATH_DATA_VECTOR
,
1395 BRW_MATH_PRECISION_FULL
);
1399 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
1404 if (intel
->gen
== 5) {
1405 switch (inst
->opcode
) {
1407 if (inst
->shadow_compare
) {
1408 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
1410 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
1414 if (inst
->shadow_compare
) {
1415 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
1417 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
1422 switch (inst
->opcode
) {
1424 /* Note that G45 and older determines shadow compare and dispatch width
1425 * from message length for most messages.
1427 if (inst
->shadow_compare
) {
1428 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
1430 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
1433 if (inst
->shadow_compare
) {
1434 assert(!"FINISHME: shadow compare with bias.");
1435 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1437 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1443 assert(msg_type
!= -1);
1449 retype(dst
, BRW_REGISTER_TYPE_UW
),
1451 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
1452 SURF_INDEX_TEXTURE(inst
->sampler
),
1460 BRW_SAMPLER_SIMD_MODE_SIMD8
);
1464 trivial_assign_reg(int header_size
, fs_reg
*reg
)
1466 if (reg
->file
== GRF
&& reg
->reg
!= 0) {
1467 reg
->hw_reg
= header_size
+ reg
->reg
- 1 + reg
->reg_offset
;
1473 fs_visitor::assign_curb_setup()
1475 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
1476 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
1478 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1479 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1480 fs_inst
*inst
= (fs_inst
*)iter
.get();
1482 for (unsigned int i
= 0; i
< 3; i
++) {
1483 if (inst
->src
[i
].file
== UNIFORM
) {
1484 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
1485 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
1489 inst
->src
[i
].file
= FIXED_HW_REG
;
1490 inst
->src
[i
].fixed_hw_reg
= brw_reg
;
1497 fs_visitor::assign_urb_setup()
1499 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
1500 int interp_reg_nr
[FRAG_ATTRIB_MAX
];
1502 c
->prog_data
.urb_read_length
= 0;
1504 /* Figure out where each of the incoming setup attributes lands. */
1505 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
1506 interp_reg_nr
[i
] = -1;
1508 if (i
!= FRAG_ATTRIB_WPOS
&&
1509 !(brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)))
1512 /* Each attribute is 4 setup channels, each of which is half a reg. */
1513 interp_reg_nr
[i
] = urb_start
+ c
->prog_data
.urb_read_length
;
1514 c
->prog_data
.urb_read_length
+= 2;
1517 /* Map the register numbers for FS_OPCODE_LINTERP so that it uses
1518 * the correct setup input.
1520 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1521 fs_inst
*inst
= (fs_inst
*)iter
.get();
1523 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
1526 assert(inst
->src
[2].file
== FIXED_HW_REG
);
1528 int location
= inst
->src
[2].fixed_hw_reg
.nr
/ 2;
1529 assert(interp_reg_nr
[location
] != -1);
1530 inst
->src
[2].fixed_hw_reg
.nr
= (interp_reg_nr
[location
] +
1531 (inst
->src
[2].fixed_hw_reg
.nr
& 1));
1534 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
1538 fs_visitor::assign_regs()
1540 int header_size
= this->first_non_payload_grf
;
1543 /* FINISHME: trivial assignment of register numbers */
1544 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1545 fs_inst
*inst
= (fs_inst
*)iter
.get();
1547 trivial_assign_reg(header_size
, &inst
->dst
);
1548 trivial_assign_reg(header_size
, &inst
->src
[0]);
1549 trivial_assign_reg(header_size
, &inst
->src
[1]);
1551 last_grf
= MAX2(last_grf
, inst
->dst
.hw_reg
);
1552 last_grf
= MAX2(last_grf
, inst
->src
[0].hw_reg
);
1553 last_grf
= MAX2(last_grf
, inst
->src
[1].hw_reg
);
1556 this->grf_used
= last_grf
+ 1;
1559 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
1561 struct brw_reg brw_reg
;
1563 switch (reg
->file
) {
1567 brw_reg
= brw_vec8_reg(reg
->file
,
1569 brw_reg
= retype(brw_reg
, reg
->type
);
1572 switch (reg
->type
) {
1573 case BRW_REGISTER_TYPE_F
:
1574 brw_reg
= brw_imm_f(reg
->imm
.f
);
1576 case BRW_REGISTER_TYPE_D
:
1577 brw_reg
= brw_imm_d(reg
->imm
.i
);
1579 case BRW_REGISTER_TYPE_UD
:
1580 brw_reg
= brw_imm_ud(reg
->imm
.u
);
1583 assert(!"not reached");
1588 brw_reg
= reg
->fixed_hw_reg
;
1591 /* Probably unused. */
1592 brw_reg
= brw_null_reg();
1595 assert(!"not reached");
1596 brw_reg
= brw_null_reg();
1600 brw_reg
= brw_abs(brw_reg
);
1602 brw_reg
= negate(brw_reg
);
1608 fs_visitor::generate_code()
1610 unsigned int annotation_len
= 0;
1611 int last_native_inst
= 0;
1612 struct brw_instruction
*if_stack
[16];
1613 int if_stack_depth
= 0;
1615 memset(&if_stack
, 0, sizeof(if_stack
));
1616 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1617 fs_inst
*inst
= (fs_inst
*)iter
.get();
1618 struct brw_reg src
[3], dst
;
1620 for (unsigned int i
= 0; i
< 3; i
++) {
1621 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
1623 dst
= brw_reg_from_fs_reg(&inst
->dst
);
1625 brw_set_conditionalmod(p
, inst
->conditional_mod
);
1626 brw_set_predicate_control(p
, inst
->predicated
);
1628 switch (inst
->opcode
) {
1629 case BRW_OPCODE_MOV
:
1630 brw_MOV(p
, dst
, src
[0]);
1632 case BRW_OPCODE_ADD
:
1633 brw_ADD(p
, dst
, src
[0], src
[1]);
1635 case BRW_OPCODE_MUL
:
1636 brw_MUL(p
, dst
, src
[0], src
[1]);
1639 case BRW_OPCODE_FRC
:
1640 brw_FRC(p
, dst
, src
[0]);
1642 case BRW_OPCODE_RNDD
:
1643 brw_RNDD(p
, dst
, src
[0]);
1645 case BRW_OPCODE_RNDZ
:
1646 brw_RNDZ(p
, dst
, src
[0]);
1649 case BRW_OPCODE_AND
:
1650 brw_AND(p
, dst
, src
[0], src
[1]);
1653 brw_OR(p
, dst
, src
[0], src
[1]);
1655 case BRW_OPCODE_XOR
:
1656 brw_XOR(p
, dst
, src
[0], src
[1]);
1659 case BRW_OPCODE_CMP
:
1660 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1662 case BRW_OPCODE_SEL
:
1663 brw_SEL(p
, dst
, src
[0], src
[1]);
1667 assert(if_stack_depth
< 16);
1668 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
1671 case BRW_OPCODE_ELSE
:
1672 if_stack
[if_stack_depth
- 1] =
1673 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
1675 case BRW_OPCODE_ENDIF
:
1677 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
1681 case FS_OPCODE_SQRT
:
1682 case FS_OPCODE_EXP2
:
1683 case FS_OPCODE_LOG2
:
1687 generate_math(inst
, dst
, src
);
1689 case FS_OPCODE_LINTERP
:
1690 generate_linterp(inst
, dst
, src
);
1695 generate_tex(inst
, dst
, src
[0]);
1697 case FS_OPCODE_FB_WRITE
:
1698 generate_fb_write(inst
);
1701 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
1702 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
1703 brw_opcodes
[inst
->opcode
].name
);
1705 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
1710 if (annotation_len
< p
->nr_insn
) {
1711 annotation_len
*= 2;
1712 if (annotation_len
< 16)
1713 annotation_len
= 16;
1715 this->annotation_string
= talloc_realloc(this->mem_ctx
,
1719 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
1725 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
1726 this->annotation_string
[i
] = inst
->annotation
;
1727 this->annotation_ir
[i
] = inst
->ir
;
1729 last_native_inst
= p
->nr_insn
;
1734 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
1736 struct brw_compile
*p
= &c
->func
;
1737 struct intel_context
*intel
= &brw
->intel
;
1738 GLcontext
*ctx
= &intel
->ctx
;
1739 struct brw_shader
*shader
= NULL
;
1740 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
1748 for (unsigned int i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
1749 if (prog
->_LinkedShaders
[i
]->Type
== GL_FRAGMENT_SHADER
) {
1750 shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
1757 /* We always use 8-wide mode, at least for now. For one, flow
1758 * control only works in 8-wide. Also, when we're fragment shader
1759 * bound, we're almost always under register pressure as well, so
1760 * 8-wide would save us from the performance cliff of spilling
1763 c
->dispatch_width
= 8;
1765 if (INTEL_DEBUG
& DEBUG_WM
) {
1766 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
1767 _mesa_print_ir(shader
->ir
, NULL
);
1771 /* Now the main event: Visit the shader IR and generate our FS IR for it.
1773 fs_visitor
v(c
, shader
);
1778 v
.emit_interpolation();
1780 /* Generate FS IR for main(). (the visitor only descends into
1781 * functions called "main").
1783 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
1784 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1793 v
.assign_curb_setup();
1794 v
.assign_urb_setup();
1800 if (INTEL_DEBUG
& DEBUG_WM
) {
1801 const char *last_annotation_string
= NULL
;
1802 ir_instruction
*last_annotation_ir
= NULL
;
1804 printf("Native code for fragment shader %d:\n", prog
->Name
);
1805 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
1806 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
1807 last_annotation_ir
= v
.annotation_ir
[i
];
1808 if (last_annotation_ir
) {
1810 last_annotation_ir
->print();
1814 if (last_annotation_string
!= v
.annotation_string
[i
]) {
1815 last_annotation_string
= v
.annotation_string
[i
];
1816 if (last_annotation_string
)
1817 printf(" %s\n", last_annotation_string
);
1819 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
1824 c
->prog_data
.total_grf
= v
.grf_used
;
1825 c
->prog_data
.total_scratch
= 0;