2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "brw_vec4_gs_visitor.h"
48 #include "brw_dead_control_flow.h"
49 #include "main/uniforms.h"
50 #include "brw_fs_live_variables.h"
51 #include "glsl/nir/glsl_types.h"
52 #include "program/sampler.h"
57 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
58 const fs_reg
*src
, unsigned sources
)
60 memset(this, 0, sizeof(*this));
62 this->src
= new fs_reg
[MAX2(sources
, 3)];
63 for (unsigned i
= 0; i
< sources
; i
++)
64 this->src
[i
] = src
[i
];
66 this->opcode
= opcode
;
68 this->sources
= sources
;
69 this->exec_size
= exec_size
;
71 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
73 assert(this->exec_size
!= 0);
75 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
77 /* This will be the case for almost all instructions. */
84 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
88 this->regs_written
= 0;
92 unreachable("Invalid destination register file");
95 this->writes_accumulator
= false;
100 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
103 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
105 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
108 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
110 init(opcode
, exec_size
, dst
, NULL
, 0);
113 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
116 const fs_reg src
[1] = { src0
};
117 init(opcode
, exec_size
, dst
, src
, 1);
120 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
121 const fs_reg
&src0
, const fs_reg
&src1
)
123 const fs_reg src
[2] = { src0
, src1
};
124 init(opcode
, exec_size
, dst
, src
, 2);
127 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
128 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
130 const fs_reg src
[3] = { src0
, src1
, src2
};
131 init(opcode
, exec_size
, dst
, src
, 3);
134 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
135 const fs_reg src
[], unsigned sources
)
137 init(opcode
, exec_width
, dst
, src
, sources
);
140 fs_inst::fs_inst(const fs_inst
&that
)
142 memcpy(this, &that
, sizeof(that
));
144 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
146 for (unsigned i
= 0; i
< that
.sources
; i
++)
147 this->src
[i
] = that
.src
[i
];
156 fs_inst::resize_sources(uint8_t num_sources
)
158 if (this->sources
!= num_sources
) {
159 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
161 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
162 src
[i
] = this->src
[i
];
166 this->sources
= num_sources
;
171 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
173 const fs_reg
&surf_index
,
174 const fs_reg
&varying_offset
,
175 uint32_t const_offset
)
177 /* We have our constant surface use a pitch of 4 bytes, so our index can
178 * be any component of a vector, and then we load 4 contiguous
179 * components starting from that.
181 * We break down the const_offset to a portion added to the variable
182 * offset and a portion done using reg_offset, which means that if you
183 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
184 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
185 * CSE can later notice that those loads are all the same and eliminate
186 * the redundant ones.
188 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
189 bld
.ADD(vec4_offset
, varying_offset
, fs_reg(const_offset
& ~3));
192 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
193 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
194 * u, v, r) as parameters, or we can just use the SIMD16 message
195 * consisting of (header, u). We choose the second, at the cost of a
196 * longer return length.
202 if (devinfo
->gen
>= 7)
203 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
205 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
207 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
208 fs_reg vec4_result
= fs_reg(VGRF
, alloc
.allocate(regs_written
), dst
.type
);
209 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
210 inst
->regs_written
= regs_written
;
212 if (devinfo
->gen
< 7) {
213 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
);
214 inst
->header_size
= 1;
215 if (devinfo
->gen
== 4)
218 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
221 bld
.MOV(dst
, offset(vec4_result
, bld
, (const_offset
& 3) * scale
));
225 * A helper for MOV generation for fixing up broken hardware SEND dependency
229 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
231 /* The caller always wants uncompressed to emit the minimal extra
232 * dependencies, and to avoid having to deal with aligning its regs to 2.
234 const fs_builder ubld
= bld
.annotate("send dependency resolve")
237 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
241 fs_inst::equals(fs_inst
*inst
) const
243 return (opcode
== inst
->opcode
&&
244 dst
.equals(inst
->dst
) &&
245 src
[0].equals(inst
->src
[0]) &&
246 src
[1].equals(inst
->src
[1]) &&
247 src
[2].equals(inst
->src
[2]) &&
248 saturate
== inst
->saturate
&&
249 predicate
== inst
->predicate
&&
250 conditional_mod
== inst
->conditional_mod
&&
251 mlen
== inst
->mlen
&&
252 base_mrf
== inst
->base_mrf
&&
253 target
== inst
->target
&&
255 header_size
== inst
->header_size
&&
256 shadow_compare
== inst
->shadow_compare
&&
257 exec_size
== inst
->exec_size
&&
258 offset
== inst
->offset
);
262 fs_inst::overwrites_reg(const fs_reg
®
) const
264 return reg
.in_range(dst
, regs_written
);
268 fs_inst::is_send_from_grf() const
271 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
272 case SHADER_OPCODE_SHADER_TIME_ADD
:
273 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
274 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
275 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
276 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
277 case SHADER_OPCODE_UNTYPED_ATOMIC
:
278 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
279 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
280 case SHADER_OPCODE_TYPED_ATOMIC
:
281 case SHADER_OPCODE_TYPED_SURFACE_READ
:
282 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
283 case SHADER_OPCODE_URB_WRITE_SIMD8
:
284 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
285 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
286 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
287 case SHADER_OPCODE_URB_READ_SIMD8
:
288 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
290 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
291 return src
[1].file
== VGRF
;
292 case FS_OPCODE_FB_WRITE
:
293 return src
[0].file
== VGRF
;
296 return src
[0].file
== VGRF
;
303 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
305 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
308 fs_reg reg
= this->src
[0];
309 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
312 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
315 for (int i
= 0; i
< this->sources
; i
++) {
316 reg
.type
= this->src
[i
].type
;
317 if (!this->src
[i
].equals(reg
))
320 if (i
< this->header_size
) {
323 reg
.reg_offset
+= this->exec_size
/ 8;
331 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
333 if (devinfo
->gen
== 6 && is_math())
336 if (is_send_from_grf())
339 if (!backend_instruction::can_do_source_mods())
346 fs_inst::can_change_types() const
348 return dst
.type
== src
[0].type
&&
349 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
350 (opcode
== BRW_OPCODE_MOV
||
351 (opcode
== BRW_OPCODE_SEL
&&
352 dst
.type
== src
[1].type
&&
353 predicate
!= BRW_PREDICATE_NONE
&&
354 !src
[1].abs
&& !src
[1].negate
));
358 fs_inst::has_side_effects() const
360 return this->eot
|| backend_instruction::has_side_effects();
366 memset(this, 0, sizeof(*this));
370 /** Generic unset register constructor. */
374 this->file
= BAD_FILE
;
377 /** Immediate value constructor. */
378 fs_reg::fs_reg(float f
)
382 this->type
= BRW_REGISTER_TYPE_F
;
387 /** Immediate value constructor. */
388 fs_reg::fs_reg(int32_t i
)
392 this->type
= BRW_REGISTER_TYPE_D
;
397 /** Immediate value constructor. */
398 fs_reg::fs_reg(uint32_t u
)
402 this->type
= BRW_REGISTER_TYPE_UD
;
407 /** Vector float immediate value constructor. */
408 fs_reg::fs_reg(uint8_t vf
[4])
412 this->type
= BRW_REGISTER_TYPE_VF
;
413 memcpy(&this->ud
, vf
, sizeof(unsigned));
416 /** Vector float immediate value constructor. */
417 fs_reg::fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
421 this->type
= BRW_REGISTER_TYPE_VF
;
422 this->ud
= (vf0
<< 0) | (vf1
<< 8) | (vf2
<< 16) | (vf3
<< 24);
425 fs_reg::fs_reg(struct brw_reg reg
) :
428 this->reg_offset
= 0;
429 this->subreg_offset
= 0;
430 this->reladdr
= NULL
;
432 if (this->file
== IMM
&&
433 (this->type
!= BRW_REGISTER_TYPE_V
&&
434 this->type
!= BRW_REGISTER_TYPE_UV
&&
435 this->type
!= BRW_REGISTER_TYPE_VF
)) {
441 fs_reg::equals(const fs_reg
&r
) const
443 return (memcmp((brw_reg
*)this, (brw_reg
*)&r
, sizeof(brw_reg
)) == 0 &&
444 reg_offset
== r
.reg_offset
&&
445 subreg_offset
== r
.subreg_offset
&&
446 !reladdr
&& !r
.reladdr
&&
451 fs_reg::set_smear(unsigned subreg
)
453 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
454 subreg_offset
= subreg
* type_sz(type
);
460 fs_reg::is_contiguous() const
466 fs_reg::component_size(unsigned width
) const
468 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
471 return MAX2(width
* stride
, 1) * type_sz(type
);
475 type_size_scalar(const struct glsl_type
*type
)
477 unsigned int size
, i
;
479 switch (type
->base_type
) {
482 case GLSL_TYPE_FLOAT
:
484 return type
->components();
485 case GLSL_TYPE_ARRAY
:
486 return type_size_scalar(type
->fields
.array
) * type
->length
;
487 case GLSL_TYPE_STRUCT
:
489 for (i
= 0; i
< type
->length
; i
++) {
490 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
493 case GLSL_TYPE_SAMPLER
:
494 /* Samplers take up no register space, since they're baked in at
498 case GLSL_TYPE_ATOMIC_UINT
:
500 case GLSL_TYPE_SUBROUTINE
:
502 case GLSL_TYPE_IMAGE
:
503 return BRW_IMAGE_PARAM_SIZE
;
505 case GLSL_TYPE_ERROR
:
506 case GLSL_TYPE_INTERFACE
:
507 case GLSL_TYPE_DOUBLE
:
508 unreachable("not reached");
515 * Returns the number of scalar components needed to store type, assuming
516 * that vectors are padded out to vec4.
518 * This has the packing rules of type_size_vec4(), but counts components
519 * similar to type_size_scalar().
522 type_size_vec4_times_4(const struct glsl_type
*type
)
524 return 4 * type_size_vec4(type
);
528 * Create a MOV to read the timestamp register.
530 * The caller is responsible for emitting the MOV. The return value is
531 * the destination of the MOV, with extra parameters set.
534 fs_visitor::get_timestamp(const fs_builder
&bld
)
536 assert(devinfo
->gen
>= 7);
538 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
541 BRW_REGISTER_TYPE_UD
));
543 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
545 /* We want to read the 3 fields we care about even if it's not enabled in
548 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
554 fs_visitor::emit_shader_time_begin()
556 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
558 /* We want only the low 32 bits of the timestamp. Since it's running
559 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
560 * which is plenty of time for our purposes. It is identical across the
561 * EUs, but since it's tracking GPU core speed it will increment at a
562 * varying rate as render P-states change.
564 shader_start_time
.set_smear(0);
568 fs_visitor::emit_shader_time_end()
570 /* Insert our code just before the final SEND with EOT. */
571 exec_node
*end
= this->instructions
.get_tail();
572 assert(end
&& ((fs_inst
*) end
)->eot
);
573 const fs_builder ibld
= bld
.annotate("shader time end")
574 .exec_all().at(NULL
, end
);
576 fs_reg shader_end_time
= get_timestamp(ibld
);
578 /* We only use the low 32 bits of the timestamp - see
579 * emit_shader_time_begin()).
581 * We could also check if render P-states have changed (or anything
582 * else that might disrupt timing) by setting smear to 2 and checking if
583 * that field is != 0.
585 shader_end_time
.set_smear(0);
587 /* Check that there weren't any timestamp reset events (assuming these
588 * were the only two timestamp reads that happened).
590 fs_reg reset
= shader_end_time
;
592 set_condmod(BRW_CONDITIONAL_Z
,
593 ibld
.AND(ibld
.null_reg_ud(), reset
, fs_reg(1u)));
594 ibld
.IF(BRW_PREDICATE_NORMAL
);
596 fs_reg start
= shader_start_time
;
598 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
601 const fs_builder cbld
= ibld
.group(1, 0);
602 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
604 /* If there were no instructions between the two timestamp gets, the diff
605 * is 2 cycles. Remove that overhead, so I can forget about that when
606 * trying to determine the time taken for single instructions.
608 cbld
.ADD(diff
, diff
, fs_reg(-2u));
609 SHADER_TIME_ADD(cbld
, 0, diff
);
610 SHADER_TIME_ADD(cbld
, 1, fs_reg(1u));
611 ibld
.emit(BRW_OPCODE_ELSE
);
612 SHADER_TIME_ADD(cbld
, 2, fs_reg(1u));
613 ibld
.emit(BRW_OPCODE_ENDIF
);
617 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
618 int shader_time_subindex
,
621 int index
= shader_time_index
* 3 + shader_time_subindex
;
622 fs_reg offset
= fs_reg(index
* SHADER_TIME_STRIDE
);
625 if (dispatch_width
== 8)
626 payload
= vgrf(glsl_type::uvec2_type
);
628 payload
= vgrf(glsl_type::uint_type
);
630 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
634 fs_visitor::vfail(const char *format
, va_list va
)
643 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
644 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
646 this->fail_msg
= msg
;
649 fprintf(stderr
, "%s", msg
);
654 fs_visitor::fail(const char *format
, ...)
658 va_start(va
, format
);
664 * Mark this program as impossible to compile in SIMD16 mode.
666 * During the SIMD8 compile (which happens first), we can detect and flag
667 * things that are unsupported in SIMD16 mode, so the compiler can skip
668 * the SIMD16 compile altogether.
670 * During a SIMD16 compile (if one happens anyway), this just calls fail().
673 fs_visitor::no16(const char *msg
)
675 if (dispatch_width
== 16) {
678 simd16_unsupported
= true;
680 compiler
->shader_perf_log(log_data
,
681 "SIMD16 shader failed to compile: %s", msg
);
686 * Returns true if the instruction has a flag that means it won't
687 * update an entire destination register.
689 * For example, dead code elimination and live variable analysis want to know
690 * when a write to a variable screens off any preceding values that were in
694 fs_inst::is_partial_write() const
696 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
697 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
698 !this->dst
.is_contiguous());
702 fs_inst::components_read(unsigned i
) const
705 case FS_OPCODE_LINTERP
:
711 case FS_OPCODE_PIXEL_X
:
712 case FS_OPCODE_PIXEL_Y
:
716 case FS_OPCODE_FB_WRITE_LOGICAL
:
717 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
718 /* First/second FB write color. */
720 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
724 case SHADER_OPCODE_TEX_LOGICAL
:
725 case SHADER_OPCODE_TXD_LOGICAL
:
726 case SHADER_OPCODE_TXF_LOGICAL
:
727 case SHADER_OPCODE_TXL_LOGICAL
:
728 case SHADER_OPCODE_TXS_LOGICAL
:
729 case FS_OPCODE_TXB_LOGICAL
:
730 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
731 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
732 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
733 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
734 case SHADER_OPCODE_LOD_LOGICAL
:
735 case SHADER_OPCODE_TG4_LOGICAL
:
736 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
737 assert(src
[8].file
== IMM
&& src
[9].file
== IMM
);
738 /* Texture coordinates. */
741 /* Texture derivatives. */
742 else if ((i
== 2 || i
== 3) && opcode
== SHADER_OPCODE_TXD_LOGICAL
)
744 /* Texture offset. */
748 else if (i
== 5 && opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
753 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
754 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
755 assert(src
[3].file
== IMM
);
756 /* Surface coordinates. */
759 /* Surface operation source (ignored for reads). */
765 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
766 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
767 assert(src
[3].file
== IMM
&&
769 /* Surface coordinates. */
772 /* Surface operation source. */
778 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
779 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
780 assert(src
[3].file
== IMM
&&
782 const unsigned op
= src
[4].ud
;
783 /* Surface coordinates. */
786 /* Surface operation source. */
787 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
789 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
790 op
== BRW_AOP_PREDEC
))
802 fs_inst::regs_read(int arg
) const
805 case FS_OPCODE_FB_WRITE
:
806 case SHADER_OPCODE_URB_WRITE_SIMD8
:
807 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
808 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
809 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
810 case SHADER_OPCODE_URB_READ_SIMD8
:
811 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
812 case SHADER_OPCODE_UNTYPED_ATOMIC
:
813 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
814 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
815 case SHADER_OPCODE_TYPED_ATOMIC
:
816 case SHADER_OPCODE_TYPED_SURFACE_READ
:
817 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
818 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
823 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
824 /* The payload is actually stored in src1 */
829 case FS_OPCODE_LINTERP
:
834 case SHADER_OPCODE_LOAD_PAYLOAD
:
835 if (arg
< this->header_size
)
839 case CS_OPCODE_CS_TERMINATE
:
840 case SHADER_OPCODE_BARRIER
:
844 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
849 switch (src
[arg
].file
) {
859 return DIV_ROUND_UP(components_read(arg
) *
860 src
[arg
].component_size(exec_size
),
863 unreachable("MRF registers are not allowed as sources");
869 fs_inst::reads_flag() const
875 fs_inst::writes_flag() const
877 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
878 opcode
!= BRW_OPCODE_IF
&&
879 opcode
!= BRW_OPCODE_WHILE
)) ||
880 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
884 * Returns how many MRFs an FS opcode will write over.
886 * Note that this is not the 0 or 1 implied writes in an actual gen
887 * instruction -- the FS opcodes often generate MOVs in addition.
890 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
895 if (inst
->base_mrf
== -1)
898 switch (inst
->opcode
) {
899 case SHADER_OPCODE_RCP
:
900 case SHADER_OPCODE_RSQ
:
901 case SHADER_OPCODE_SQRT
:
902 case SHADER_OPCODE_EXP2
:
903 case SHADER_OPCODE_LOG2
:
904 case SHADER_OPCODE_SIN
:
905 case SHADER_OPCODE_COS
:
906 return 1 * dispatch_width
/ 8;
907 case SHADER_OPCODE_POW
:
908 case SHADER_OPCODE_INT_QUOTIENT
:
909 case SHADER_OPCODE_INT_REMAINDER
:
910 return 2 * dispatch_width
/ 8;
911 case SHADER_OPCODE_TEX
:
913 case SHADER_OPCODE_TXD
:
914 case SHADER_OPCODE_TXF
:
915 case SHADER_OPCODE_TXF_CMS
:
916 case SHADER_OPCODE_TXF_CMS_W
:
917 case SHADER_OPCODE_TXF_MCS
:
918 case SHADER_OPCODE_TG4
:
919 case SHADER_OPCODE_TG4_OFFSET
:
920 case SHADER_OPCODE_TXL
:
921 case SHADER_OPCODE_TXS
:
922 case SHADER_OPCODE_LOD
:
923 case SHADER_OPCODE_SAMPLEINFO
:
925 case FS_OPCODE_FB_WRITE
:
927 case FS_OPCODE_GET_BUFFER_SIZE
:
928 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
929 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
931 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
933 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
935 case SHADER_OPCODE_UNTYPED_ATOMIC
:
936 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
937 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
938 case SHADER_OPCODE_TYPED_ATOMIC
:
939 case SHADER_OPCODE_TYPED_SURFACE_READ
:
940 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
941 case SHADER_OPCODE_URB_WRITE_SIMD8
:
942 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
943 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
944 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
945 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
946 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
947 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
948 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
951 unreachable("not reached");
956 fs_visitor::vgrf(const glsl_type
*const type
)
958 int reg_width
= dispatch_width
/ 8;
959 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
960 brw_type_for_base_type(type
));
963 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
968 this->type
= BRW_REGISTER_TYPE_F
;
969 this->stride
= (file
== UNIFORM
? 0 : 1);
972 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
978 this->stride
= (file
== UNIFORM
? 0 : 1);
981 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
982 * This brings in those uniform definitions
985 fs_visitor::import_uniforms(fs_visitor
*v
)
987 this->push_constant_loc
= v
->push_constant_loc
;
988 this->pull_constant_loc
= v
->pull_constant_loc
;
989 this->uniforms
= v
->uniforms
;
990 this->param_size
= v
->param_size
;
994 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
995 bool origin_upper_left
)
997 assert(stage
== MESA_SHADER_FRAGMENT
);
998 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
999 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
1001 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
1003 /* gl_FragCoord.x */
1004 if (pixel_center_integer
) {
1005 bld
.MOV(wpos
, this->pixel_x
);
1007 bld
.ADD(wpos
, this->pixel_x
, fs_reg(0.5f
));
1009 wpos
= offset(wpos
, bld
, 1);
1011 /* gl_FragCoord.y */
1012 if (!flip
&& pixel_center_integer
) {
1013 bld
.MOV(wpos
, this->pixel_y
);
1015 fs_reg pixel_y
= this->pixel_y
;
1016 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
1019 pixel_y
.negate
= true;
1020 offset
+= key
->drawable_height
- 1.0f
;
1023 bld
.ADD(wpos
, pixel_y
, fs_reg(offset
));
1025 wpos
= offset(wpos
, bld
, 1);
1027 /* gl_FragCoord.z */
1028 if (devinfo
->gen
>= 6) {
1029 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1031 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1032 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1033 interp_reg(VARYING_SLOT_POS
, 2));
1035 wpos
= offset(wpos
, bld
, 1);
1037 /* gl_FragCoord.w: Already set up in emit_interpolation */
1038 bld
.MOV(wpos
, this->wpos_w
);
1044 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1045 glsl_interp_qualifier interpolation_mode
,
1046 bool is_centroid
, bool is_sample
)
1048 brw_wm_barycentric_interp_mode barycoord_mode
;
1049 if (devinfo
->gen
>= 6) {
1051 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1052 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1054 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1055 } else if (is_sample
) {
1056 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1057 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1059 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1061 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1062 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1064 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1067 /* On Ironlake and below, there is only one interpolation mode.
1068 * Centroid interpolation doesn't mean anything on this hardware --
1069 * there is no multisampling.
1071 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1073 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1074 this->delta_xy
[barycoord_mode
], interp
);
1078 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
1079 const glsl_type
*type
,
1080 glsl_interp_qualifier interpolation_mode
,
1081 int location
, bool mod_centroid
,
1084 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
1086 assert(stage
== MESA_SHADER_FRAGMENT
);
1087 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1088 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1090 unsigned int array_elements
;
1092 if (type
->is_array()) {
1093 array_elements
= type
->arrays_of_arrays_size();
1094 if (array_elements
== 0) {
1095 fail("dereferenced array '%s' has length 0\n", name
);
1097 type
= type
->without_array();
1102 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1104 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1105 if (key
->flat_shade
&& is_gl_Color
) {
1106 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1108 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1112 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1113 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1114 if (prog_data
->urb_setup
[location
] == -1) {
1115 /* If there's no incoming setup data for this slot, don't
1116 * emit interpolation for it.
1118 attr
= offset(attr
, bld
, type
->vector_elements
);
1123 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1124 /* Constant interpolation (flat shading) case. The SF has
1125 * handed us defined values in only the constant offset
1126 * field of the setup reg.
1128 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1129 struct brw_reg interp
= interp_reg(location
, k
);
1130 interp
= suboffset(interp
, 3);
1131 interp
.type
= attr
.type
;
1132 bld
.emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1133 attr
= offset(attr
, bld
, 1);
1136 /* Smooth/noperspective interpolation case. */
1137 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1138 struct brw_reg interp
= interp_reg(location
, k
);
1139 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1140 /* Get the pixel/sample mask into f0 so that we know
1141 * which pixels are lit. Then, for each channel that is
1142 * unlit, replace the centroid data with non-centroid
1145 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1148 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1150 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1151 inst
->predicate_inverse
= true;
1152 if (devinfo
->has_pln
)
1153 inst
->no_dd_clear
= true;
1155 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1156 mod_centroid
&& !key
->persample_shading
,
1157 mod_sample
|| key
->persample_shading
);
1158 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1159 inst
->predicate_inverse
= false;
1160 if (devinfo
->has_pln
)
1161 inst
->no_dd_check
= true;
1164 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1165 mod_centroid
&& !key
->persample_shading
,
1166 mod_sample
|| key
->persample_shading
);
1168 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1169 bld
.MUL(attr
, attr
, this->pixel_w
);
1171 attr
= offset(attr
, bld
, 1);
1181 fs_visitor::emit_frontfacing_interpolation()
1183 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1185 if (devinfo
->gen
>= 6) {
1186 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1187 * a boolean result from this (~0/true or 0/false).
1189 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1190 * this task in only one instruction:
1191 * - a negation source modifier will flip the bit; and
1192 * - a W -> D type conversion will sign extend the bit into the high
1193 * word of the destination.
1195 * An ASR 15 fills the low word of the destination.
1197 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1200 bld
.ASR(*reg
, g0
, fs_reg(15));
1202 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1203 * a boolean result from this (1/true or 0/false).
1205 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1206 * the negation source modifier to flip it. Unfortunately the SHR
1207 * instruction only operates on UD (or D with an abs source modifier)
1208 * sources without negation.
1210 * Instead, use ASR (which will give ~0/true or 0/false).
1212 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1215 bld
.ASR(*reg
, g1_6
, fs_reg(31));
1222 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1224 assert(stage
== MESA_SHADER_FRAGMENT
);
1225 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1226 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1228 if (key
->compute_pos_offset
) {
1229 /* Convert int_sample_pos to floating point */
1230 bld
.MOV(dst
, int_sample_pos
);
1231 /* Scale to the range [0, 1] */
1232 bld
.MUL(dst
, dst
, fs_reg(1 / 16.0f
));
1235 /* From ARB_sample_shading specification:
1236 * "When rendering to a non-multisample buffer, or if multisample
1237 * rasterization is disabled, gl_SamplePosition will always be
1240 bld
.MOV(dst
, fs_reg(0.5f
));
1245 fs_visitor::emit_samplepos_setup()
1247 assert(devinfo
->gen
>= 6);
1249 const fs_builder abld
= bld
.annotate("compute sample position");
1250 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1252 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1253 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1255 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1256 * mode will be enabled.
1258 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1259 * R31.1:0 Position Offset X/Y for Slot[3:0]
1260 * R31.3:2 Position Offset X/Y for Slot[7:4]
1263 * The X, Y sample positions come in as bytes in thread payload. So, read
1264 * the positions using vstride=16, width=8, hstride=2.
1266 struct brw_reg sample_pos_reg
=
1267 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1268 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1270 if (dispatch_width
== 8) {
1271 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1273 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1274 abld
.half(1).MOV(half(int_sample_x
, 1),
1275 fs_reg(suboffset(sample_pos_reg
, 16)));
1277 /* Compute gl_SamplePosition.x */
1278 compute_sample_position(pos
, int_sample_x
);
1279 pos
= offset(pos
, abld
, 1);
1280 if (dispatch_width
== 8) {
1281 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1283 abld
.half(0).MOV(half(int_sample_y
, 0),
1284 fs_reg(suboffset(sample_pos_reg
, 1)));
1285 abld
.half(1).MOV(half(int_sample_y
, 1),
1286 fs_reg(suboffset(sample_pos_reg
, 17)));
1288 /* Compute gl_SamplePosition.y */
1289 compute_sample_position(pos
, int_sample_y
);
1294 fs_visitor::emit_sampleid_setup()
1296 assert(stage
== MESA_SHADER_FRAGMENT
);
1297 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1298 assert(devinfo
->gen
>= 6);
1300 const fs_builder abld
= bld
.annotate("compute sample id");
1301 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1303 if (key
->compute_sample_id
) {
1304 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1306 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1308 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1309 * 8x multisampling, subspan 0 will represent sample N (where N
1310 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1311 * 7. We can find the value of N by looking at R0.0 bits 7:6
1312 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1313 * (since samples are always delivered in pairs). That is, we
1314 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1315 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1316 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1317 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1318 * populating a temporary variable with the sequence (0, 1, 2, 3),
1319 * and then reading from it using vstride=1, width=4, hstride=0.
1320 * These computations hold good for 4x multisampling as well.
1322 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1323 * the first four slots are sample 0 of subspan 0; the next four
1324 * are sample 1 of subspan 0; the third group is sample 0 of
1325 * subspan 1, and finally sample 1 of subspan 1.
1328 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1329 * accomodate 16x MSAA.
1331 unsigned sspi_mask
= devinfo
->gen
>= 9 ? 0x1c0 : 0xc0;
1333 abld
.exec_all().group(1, 0)
1334 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1336 abld
.exec_all().group(1, 0).SHR(t1
, t1
, fs_reg(5));
1338 /* This works for both SIMD8 and SIMD16 */
1339 abld
.exec_all().group(4, 0)
1340 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1342 /* This special instruction takes care of setting vstride=1,
1343 * width=4, hstride=0 of t2 during an ADD instruction.
1345 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1347 /* As per GL_ARB_sample_shading specification:
1348 * "When rendering to a non-multisample buffer, or if multisample
1349 * rasterization is disabled, gl_SampleID will always be zero."
1351 abld
.MOV(*reg
, fs_reg(0));
1358 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1360 if (!src
.abs
&& !src
.negate
)
1363 fs_reg temp
= bld
.vgrf(src
.type
);
1370 fs_visitor::emit_discard_jump()
1372 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1374 /* For performance, after a discard, jump to the end of the
1375 * shader if all relevant channels have been discarded.
1377 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1378 discard_jump
->flag_subreg
= 1;
1380 discard_jump
->predicate
= (dispatch_width
== 8)
1381 ? BRW_PREDICATE_ALIGN1_ANY8H
1382 : BRW_PREDICATE_ALIGN1_ANY16H
;
1383 discard_jump
->predicate_inverse
= true;
1387 fs_visitor::emit_gs_thread_end()
1389 assert(stage
== MESA_SHADER_GEOMETRY
);
1391 struct brw_gs_prog_data
*gs_prog_data
=
1392 (struct brw_gs_prog_data
*) prog_data
;
1394 if (gs_compile
->control_data_header_size_bits
> 0) {
1395 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1398 const fs_builder abld
= bld
.annotate("thread end");
1401 if (gs_prog_data
->static_vertex_count
!= -1) {
1402 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1403 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1404 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1405 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1406 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1409 /* Delete now dead instructions. */
1410 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1416 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1420 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1421 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1422 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1425 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1426 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1427 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1428 sources
[1] = this->final_gs_vertex_count
;
1429 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1430 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1438 fs_visitor::assign_curb_setup()
1440 if (dispatch_width
== 8) {
1441 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1443 if (stage
== MESA_SHADER_FRAGMENT
) {
1444 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1445 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1446 } else if (stage
== MESA_SHADER_COMPUTE
) {
1447 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1448 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1450 unreachable("Unsupported shader type!");
1454 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1456 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1457 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1458 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1459 if (inst
->src
[i
].file
== UNIFORM
) {
1460 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1462 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1463 constant_nr
= push_constant_loc
[uniform_nr
];
1465 /* Section 5.11 of the OpenGL 4.1 spec says:
1466 * "Out-of-bounds reads return undefined values, which include
1467 * values from other variables of the active program or zero."
1468 * Just return the first push constant.
1473 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1476 brw_reg
.abs
= inst
->src
[i
].abs
;
1477 brw_reg
.negate
= inst
->src
[i
].negate
;
1479 assert(inst
->src
[i
].stride
== 0);
1480 inst
->src
[i
] = byte_offset(
1481 retype(brw_reg
, inst
->src
[i
].type
),
1482 inst
->src
[i
].subreg_offset
);
1487 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1488 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1492 fs_visitor::calculate_urb_setup()
1494 assert(stage
== MESA_SHADER_FRAGMENT
);
1495 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1496 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1498 memset(prog_data
->urb_setup
, -1,
1499 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1502 /* Figure out where each of the incoming setup attributes lands. */
1503 if (devinfo
->gen
>= 6) {
1504 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1505 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1506 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1507 * first 16 varying inputs, so we can put them wherever we want.
1508 * Just put them in order.
1510 * This is useful because it means that (a) inputs not used by the
1511 * fragment shader won't take up valuable register space, and (b) we
1512 * won't have to recompile the fragment shader if it gets paired with
1513 * a different vertex (or geometry) shader.
1515 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1516 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1517 BITFIELD64_BIT(i
)) {
1518 prog_data
->urb_setup
[i
] = urb_next
++;
1522 bool include_vue_header
=
1523 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1525 /* We have enough input varyings that the SF/SBE pipeline stage can't
1526 * arbitrarily rearrange them to suit our whim; we have to put them
1527 * in an order that matches the output of the previous pipeline stage
1528 * (geometry or vertex shader).
1530 struct brw_vue_map prev_stage_vue_map
;
1531 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1532 key
->input_slots_valid
,
1533 nir
->info
.separate_shader
);
1535 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1537 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1538 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1540 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1541 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1542 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1543 BITFIELD64_BIT(varying
))) {
1544 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1547 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1550 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1551 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1552 /* Point size is packed into the header, not as a general attribute */
1553 if (i
== VARYING_SLOT_PSIZ
)
1556 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1557 /* The back color slot is skipped when the front color is
1558 * also written to. In addition, some slots can be
1559 * written in the vertex shader and not read in the
1560 * fragment shader. So the register number must always be
1561 * incremented, mapped or not.
1563 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1564 prog_data
->urb_setup
[i
] = urb_next
;
1570 * It's a FS only attribute, and we did interpolation for this attribute
1571 * in SF thread. So, count it here, too.
1573 * See compile_sf_prog() for more info.
1575 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1576 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1579 prog_data
->num_varying_inputs
= urb_next
;
1583 fs_visitor::assign_urb_setup()
1585 assert(stage
== MESA_SHADER_FRAGMENT
);
1586 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1588 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1590 /* Offset all the urb_setup[] index by the actual position of the
1591 * setup regs, now that the location of the constants has been chosen.
1593 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1594 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1595 assert(inst
->src
[1].file
== FIXED_GRF
);
1596 inst
->src
[1].nr
+= urb_start
;
1599 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1600 assert(inst
->src
[0].file
== FIXED_GRF
);
1601 inst
->src
[0].nr
+= urb_start
;
1605 /* Each attribute is 4 setup channels, each of which is half a reg. */
1606 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1610 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1612 for (int i
= 0; i
< inst
->sources
; i
++) {
1613 if (inst
->src
[i
].file
== ATTR
) {
1614 int grf
= payload
.num_regs
+
1615 prog_data
->curb_read_length
+
1617 inst
->src
[i
].reg_offset
;
1619 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : inst
->exec_size
;
1620 struct brw_reg reg
=
1621 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1622 inst
->src
[i
].subreg_offset
),
1623 inst
->exec_size
* inst
->src
[i
].stride
,
1624 width
, inst
->src
[i
].stride
);
1625 reg
.abs
= inst
->src
[i
].abs
;
1626 reg
.negate
= inst
->src
[i
].negate
;
1634 fs_visitor::assign_vs_urb_setup()
1636 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1638 assert(stage
== MESA_SHADER_VERTEX
);
1639 int count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1640 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1643 /* Each attribute is 4 regs. */
1644 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attributes
;
1646 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1648 /* Rewrite all ATTR file references to the hw grf that they land in. */
1649 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1650 convert_attr_sources_to_hw_regs(inst
);
1655 fs_visitor::assign_gs_urb_setup()
1657 assert(stage
== MESA_SHADER_GEOMETRY
);
1659 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1661 first_non_payload_grf
+=
1662 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1664 const unsigned first_icp_handle
= payload
.num_regs
-
1665 (vue_prog_data
->include_vue_handles
? nir
->info
.gs
.vertices_in
: 0);
1667 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1668 /* Lower URB_READ_SIMD8 opcodes into real messages. */
1669 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8
) {
1670 assert(inst
->src
[0].file
== IMM
);
1671 inst
->src
[0] = retype(brw_vec8_grf(first_icp_handle
+
1673 0), BRW_REGISTER_TYPE_UD
);
1674 /* for now, assume constant - we can do per-slot offsets later */
1675 assert(inst
->src
[1].file
== IMM
);
1676 inst
->offset
= inst
->src
[1].ud
;
1677 inst
->src
[1] = fs_reg();
1679 inst
->base_mrf
= -1;
1682 /* Rewrite all ATTR file references to GRFs. */
1683 convert_attr_sources_to_hw_regs(inst
);
1689 * Split large virtual GRFs into separate components if we can.
1691 * This is mostly duplicated with what brw_fs_vector_splitting does,
1692 * but that's really conservative because it's afraid of doing
1693 * splitting that doesn't result in real progress after the rest of
1694 * the optimization phases, which would cause infinite looping in
1695 * optimization. We can do it once here, safely. This also has the
1696 * opportunity to split interpolated values, or maybe even uniforms,
1697 * which we don't have at the IR level.
1699 * We want to split, because virtual GRFs are what we register
1700 * allocate and spill (due to contiguousness requirements for some
1701 * instructions), and they're what we naturally generate in the
1702 * codegen process, but most virtual GRFs don't actually need to be
1703 * contiguous sets of GRFs. If we split, we'll end up with reduced
1704 * live intervals and better dead code elimination and coalescing.
1707 fs_visitor::split_virtual_grfs()
1709 int num_vars
= this->alloc
.count
;
1711 /* Count the total number of registers */
1713 int vgrf_to_reg
[num_vars
];
1714 for (int i
= 0; i
< num_vars
; i
++) {
1715 vgrf_to_reg
[i
] = reg_count
;
1716 reg_count
+= alloc
.sizes
[i
];
1719 /* An array of "split points". For each register slot, this indicates
1720 * if this slot can be separated from the previous slot. Every time an
1721 * instruction uses multiple elements of a register (as a source or
1722 * destination), we mark the used slots as inseparable. Then we go
1723 * through and split the registers into the smallest pieces we can.
1725 bool split_points
[reg_count
];
1726 memset(split_points
, 0, sizeof(split_points
));
1728 /* Mark all used registers as fully splittable */
1729 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1730 if (inst
->dst
.file
== VGRF
) {
1731 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1732 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1733 split_points
[reg
+ j
] = true;
1736 for (int i
= 0; i
< inst
->sources
; i
++) {
1737 if (inst
->src
[i
].file
== VGRF
) {
1738 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1739 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1740 split_points
[reg
+ j
] = true;
1745 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1746 if (inst
->dst
.file
== VGRF
) {
1747 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1748 for (int j
= 1; j
< inst
->regs_written
; j
++)
1749 split_points
[reg
+ j
] = false;
1751 for (int i
= 0; i
< inst
->sources
; i
++) {
1752 if (inst
->src
[i
].file
== VGRF
) {
1753 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1754 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1755 split_points
[reg
+ j
] = false;
1760 int new_virtual_grf
[reg_count
];
1761 int new_reg_offset
[reg_count
];
1764 for (int i
= 0; i
< num_vars
; i
++) {
1765 /* The first one should always be 0 as a quick sanity check. */
1766 assert(split_points
[reg
] == false);
1769 new_reg_offset
[reg
] = 0;
1774 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1775 /* If this is a split point, reset the offset to 0 and allocate a
1776 * new virtual GRF for the previous offset many registers
1778 if (split_points
[reg
]) {
1779 assert(offset
<= MAX_VGRF_SIZE
);
1780 int grf
= alloc
.allocate(offset
);
1781 for (int k
= reg
- offset
; k
< reg
; k
++)
1782 new_virtual_grf
[k
] = grf
;
1785 new_reg_offset
[reg
] = offset
;
1790 /* The last one gets the original register number */
1791 assert(offset
<= MAX_VGRF_SIZE
);
1792 alloc
.sizes
[i
] = offset
;
1793 for (int k
= reg
- offset
; k
< reg
; k
++)
1794 new_virtual_grf
[k
] = i
;
1796 assert(reg
== reg_count
);
1798 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1799 if (inst
->dst
.file
== VGRF
) {
1800 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1801 inst
->dst
.nr
= new_virtual_grf
[reg
];
1802 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1803 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1805 for (int i
= 0; i
< inst
->sources
; i
++) {
1806 if (inst
->src
[i
].file
== VGRF
) {
1807 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1808 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1809 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1810 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1814 invalidate_live_intervals();
1818 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1820 * During code generation, we create tons of temporary variables, many of
1821 * which get immediately killed and are never used again. Yet, in later
1822 * optimization and analysis passes, such as compute_live_intervals, we need
1823 * to loop over all the virtual GRFs. Compacting them can save a lot of
1827 fs_visitor::compact_virtual_grfs()
1829 bool progress
= false;
1830 int remap_table
[this->alloc
.count
];
1831 memset(remap_table
, -1, sizeof(remap_table
));
1833 /* Mark which virtual GRFs are used. */
1834 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1835 if (inst
->dst
.file
== VGRF
)
1836 remap_table
[inst
->dst
.nr
] = 0;
1838 for (int i
= 0; i
< inst
->sources
; i
++) {
1839 if (inst
->src
[i
].file
== VGRF
)
1840 remap_table
[inst
->src
[i
].nr
] = 0;
1844 /* Compact the GRF arrays. */
1846 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1847 if (remap_table
[i
] == -1) {
1848 /* We just found an unused register. This means that we are
1849 * actually going to compact something.
1853 remap_table
[i
] = new_index
;
1854 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1855 invalidate_live_intervals();
1860 this->alloc
.count
= new_index
;
1862 /* Patch all the instructions to use the newly renumbered registers */
1863 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1864 if (inst
->dst
.file
== VGRF
)
1865 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1867 for (int i
= 0; i
< inst
->sources
; i
++) {
1868 if (inst
->src
[i
].file
== VGRF
)
1869 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1873 /* Patch all the references to delta_xy, since they're used in register
1874 * allocation. If they're unused, switch them to BAD_FILE so we don't
1875 * think some random VGRF is delta_xy.
1877 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1878 if (delta_xy
[i
].file
== VGRF
) {
1879 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1880 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1882 delta_xy
[i
].file
= BAD_FILE
;
1891 * Assign UNIFORM file registers to either push constants or pull constants.
1893 * We allow a fragment shader to have more than the specified minimum
1894 * maximum number of fragment shader uniform components (64). If
1895 * there are too many of these, they'd fill up all of register space.
1896 * So, this will push some of them out to the pull constant buffer and
1897 * update the program to load them. We also use pull constants for all
1898 * indirect constant loads because we don't support indirect accesses in
1902 fs_visitor::assign_constant_locations()
1904 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1905 if (dispatch_width
!= 8)
1908 unsigned int num_pull_constants
= 0;
1910 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1911 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1913 bool is_live
[uniforms
];
1914 memset(is_live
, 0, sizeof(is_live
));
1916 /* First, we walk through the instructions and do two things:
1918 * 1) Figure out which uniforms are live.
1920 * 2) Find all indirect access of uniform arrays and flag them as needing
1921 * to go into the pull constant buffer.
1923 * Note that we don't move constant-indexed accesses to arrays. No
1924 * testing has been done of the performance impact of this choice.
1926 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1927 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1928 if (inst
->src
[i
].file
!= UNIFORM
)
1931 if (inst
->src
[i
].reladdr
) {
1932 int uniform
= inst
->src
[i
].nr
;
1934 /* If this array isn't already present in the pull constant buffer,
1937 if (pull_constant_loc
[uniform
] == -1) {
1938 assert(param_size
[uniform
]);
1939 for (int j
= 0; j
< param_size
[uniform
]; j
++)
1940 pull_constant_loc
[uniform
+ j
] = num_pull_constants
++;
1943 /* Mark the the one accessed uniform as live */
1944 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1945 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1946 is_live
[constant_nr
] = true;
1951 /* Only allow 16 registers (128 uniform components) as push constants.
1953 * Just demote the end of the list. We could probably do better
1954 * here, demoting things that are rarely used in the program first.
1956 * If changing this value, note the limitation about total_regs in
1959 unsigned int max_push_components
= 16 * 8;
1960 unsigned int num_push_constants
= 0;
1962 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1964 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1965 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1966 /* This UNIFORM register is either dead, or has already been demoted
1967 * to a pull const. Mark it as no longer living in the param[] array.
1969 push_constant_loc
[i
] = -1;
1973 if (num_push_constants
< max_push_components
) {
1974 /* Retain as a push constant. Record the location in the params[]
1977 push_constant_loc
[i
] = num_push_constants
++;
1979 /* Demote to a pull constant. */
1980 push_constant_loc
[i
] = -1;
1981 pull_constant_loc
[i
] = num_pull_constants
++;
1985 stage_prog_data
->nr_params
= num_push_constants
;
1986 stage_prog_data
->nr_pull_params
= num_pull_constants
;
1988 /* Up until now, the param[] array has been indexed by reg + reg_offset
1989 * of UNIFORM registers. Move pull constants into pull_param[] and
1990 * condense param[] to only contain the uniforms we chose to push.
1992 * NOTE: Because we are condensing the params[] array, we know that
1993 * push_constant_loc[i] <= i and we can do it in one smooth loop without
1994 * having to make a copy.
1996 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1997 const gl_constant_value
*value
= stage_prog_data
->param
[i
];
1999 if (pull_constant_loc
[i
] != -1) {
2000 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2001 } else if (push_constant_loc
[i
] != -1) {
2002 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2008 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2009 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2012 fs_visitor::demote_pull_constants()
2014 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2015 for (int i
= 0; i
< inst
->sources
; i
++) {
2016 if (inst
->src
[i
].file
!= UNIFORM
)
2020 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2021 if (location
>= uniforms
) /* Out of bounds access */
2024 pull_index
= pull_constant_loc
[location
];
2026 if (pull_index
== -1)
2029 /* Set up the annotation tracking for new generated instructions. */
2030 const fs_builder
ibld(this, block
, inst
);
2031 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2032 fs_reg dst
= vgrf(glsl_type::float_type
);
2034 assert(inst
->src
[i
].stride
== 0);
2036 /* Generate a pull load into dst. */
2037 if (inst
->src
[i
].reladdr
) {
2038 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
2040 *inst
->src
[i
].reladdr
,
2042 inst
->src
[i
].reladdr
= NULL
;
2043 inst
->src
[i
].stride
= 1;
2045 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2046 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
2047 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2048 dst
, fs_reg(index
), offset
);
2049 inst
->src
[i
].set_smear(pull_index
& 3);
2051 brw_mark_surface_used(prog_data
, index
);
2053 /* Rewrite the instruction to use the temporary VGRF. */
2054 inst
->src
[i
].file
= VGRF
;
2055 inst
->src
[i
].nr
= dst
.nr
;
2056 inst
->src
[i
].reg_offset
= 0;
2059 invalidate_live_intervals();
2063 fs_visitor::opt_algebraic()
2065 bool progress
= false;
2067 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2068 switch (inst
->opcode
) {
2069 case BRW_OPCODE_MOV
:
2070 if (inst
->src
[0].file
!= IMM
)
2073 if (inst
->saturate
) {
2074 if (inst
->dst
.type
!= inst
->src
[0].type
)
2075 assert(!"unimplemented: saturate mixed types");
2077 if (brw_saturate_immediate(inst
->dst
.type
, &inst
->src
[0])) {
2078 inst
->saturate
= false;
2084 case BRW_OPCODE_MUL
:
2085 if (inst
->src
[1].file
!= IMM
)
2089 if (inst
->src
[1].is_one()) {
2090 inst
->opcode
= BRW_OPCODE_MOV
;
2091 inst
->src
[1] = reg_undef
;
2097 if (inst
->src
[1].is_negative_one()) {
2098 inst
->opcode
= BRW_OPCODE_MOV
;
2099 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2100 inst
->src
[1] = reg_undef
;
2106 if (inst
->src
[1].is_zero()) {
2107 inst
->opcode
= BRW_OPCODE_MOV
;
2108 inst
->src
[0] = inst
->src
[1];
2109 inst
->src
[1] = reg_undef
;
2114 if (inst
->src
[0].file
== IMM
) {
2115 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2116 inst
->opcode
= BRW_OPCODE_MOV
;
2117 inst
->src
[0].f
*= inst
->src
[1].f
;
2118 inst
->src
[1] = reg_undef
;
2123 case BRW_OPCODE_ADD
:
2124 if (inst
->src
[1].file
!= IMM
)
2128 if (inst
->src
[1].is_zero()) {
2129 inst
->opcode
= BRW_OPCODE_MOV
;
2130 inst
->src
[1] = reg_undef
;
2135 if (inst
->src
[0].file
== IMM
) {
2136 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2137 inst
->opcode
= BRW_OPCODE_MOV
;
2138 inst
->src
[0].f
+= inst
->src
[1].f
;
2139 inst
->src
[1] = reg_undef
;
2145 if (inst
->src
[0].equals(inst
->src
[1])) {
2146 inst
->opcode
= BRW_OPCODE_MOV
;
2147 inst
->src
[1] = reg_undef
;
2152 case BRW_OPCODE_LRP
:
2153 if (inst
->src
[1].equals(inst
->src
[2])) {
2154 inst
->opcode
= BRW_OPCODE_MOV
;
2155 inst
->src
[0] = inst
->src
[1];
2156 inst
->src
[1] = reg_undef
;
2157 inst
->src
[2] = reg_undef
;
2162 case BRW_OPCODE_CMP
:
2163 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2165 inst
->src
[0].negate
&&
2166 inst
->src
[1].is_zero()) {
2167 inst
->src
[0].abs
= false;
2168 inst
->src
[0].negate
= false;
2169 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2174 case BRW_OPCODE_SEL
:
2175 if (inst
->src
[0].equals(inst
->src
[1])) {
2176 inst
->opcode
= BRW_OPCODE_MOV
;
2177 inst
->src
[1] = reg_undef
;
2178 inst
->predicate
= BRW_PREDICATE_NONE
;
2179 inst
->predicate_inverse
= false;
2181 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2182 switch (inst
->conditional_mod
) {
2183 case BRW_CONDITIONAL_LE
:
2184 case BRW_CONDITIONAL_L
:
2185 switch (inst
->src
[1].type
) {
2186 case BRW_REGISTER_TYPE_F
:
2187 if (inst
->src
[1].f
>= 1.0f
) {
2188 inst
->opcode
= BRW_OPCODE_MOV
;
2189 inst
->src
[1] = reg_undef
;
2190 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2198 case BRW_CONDITIONAL_GE
:
2199 case BRW_CONDITIONAL_G
:
2200 switch (inst
->src
[1].type
) {
2201 case BRW_REGISTER_TYPE_F
:
2202 if (inst
->src
[1].f
<= 0.0f
) {
2203 inst
->opcode
= BRW_OPCODE_MOV
;
2204 inst
->src
[1] = reg_undef
;
2205 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2217 case BRW_OPCODE_MAD
:
2218 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2219 inst
->opcode
= BRW_OPCODE_MOV
;
2220 inst
->src
[1] = reg_undef
;
2221 inst
->src
[2] = reg_undef
;
2223 } else if (inst
->src
[0].is_zero()) {
2224 inst
->opcode
= BRW_OPCODE_MUL
;
2225 inst
->src
[0] = inst
->src
[2];
2226 inst
->src
[2] = reg_undef
;
2228 } else if (inst
->src
[1].is_one()) {
2229 inst
->opcode
= BRW_OPCODE_ADD
;
2230 inst
->src
[1] = inst
->src
[2];
2231 inst
->src
[2] = reg_undef
;
2233 } else if (inst
->src
[2].is_one()) {
2234 inst
->opcode
= BRW_OPCODE_ADD
;
2235 inst
->src
[2] = reg_undef
;
2237 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2238 inst
->opcode
= BRW_OPCODE_ADD
;
2239 inst
->src
[1].f
*= inst
->src
[2].f
;
2240 inst
->src
[2] = reg_undef
;
2244 case SHADER_OPCODE_RCP
: {
2245 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2246 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2247 if (inst
->src
[0].equals(prev
->dst
)) {
2248 inst
->opcode
= SHADER_OPCODE_RSQ
;
2249 inst
->src
[0] = prev
->src
[0];
2255 case SHADER_OPCODE_BROADCAST
:
2256 if (is_uniform(inst
->src
[0])) {
2257 inst
->opcode
= BRW_OPCODE_MOV
;
2259 inst
->force_writemask_all
= true;
2261 } else if (inst
->src
[1].file
== IMM
) {
2262 inst
->opcode
= BRW_OPCODE_MOV
;
2263 inst
->src
[0] = component(inst
->src
[0],
2266 inst
->force_writemask_all
= true;
2275 /* Swap if src[0] is immediate. */
2276 if (progress
&& inst
->is_commutative()) {
2277 if (inst
->src
[0].file
== IMM
) {
2278 fs_reg tmp
= inst
->src
[1];
2279 inst
->src
[1] = inst
->src
[0];
2288 * Optimize sample messages that have constant zero values for the trailing
2289 * texture coordinates. We can just reduce the message length for these
2290 * instructions instead of reserving a register for it. Trailing parameters
2291 * that aren't sent default to zero anyway. This will cause the dead code
2292 * eliminator to remove the MOV instruction that would otherwise be emitted to
2293 * set up the zero value.
2296 fs_visitor::opt_zero_samples()
2298 /* Gen4 infers the texturing opcode based on the message length so we can't
2301 if (devinfo
->gen
< 5)
2304 bool progress
= false;
2306 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2307 if (!inst
->is_tex())
2310 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2312 if (load_payload
->is_head_sentinel() ||
2313 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2316 /* We don't want to remove the message header or the first parameter.
2317 * Removing the first parameter is not allowed, see the Haswell PRM
2318 * volume 7, page 149:
2320 * "Parameter 0 is required except for the sampleinfo message, which
2321 * has no parameter 0"
2323 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2324 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2325 (inst
->exec_size
/ 8) +
2326 inst
->header_size
- 1].is_zero()) {
2327 inst
->mlen
-= inst
->exec_size
/ 8;
2333 invalidate_live_intervals();
2339 * Optimize sample messages which are followed by the final RT write.
2341 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2342 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2343 * final texturing results copied to the framebuffer write payload and modify
2344 * them to write to the framebuffer directly.
2347 fs_visitor::opt_sampler_eot()
2349 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2351 if (stage
!= MESA_SHADER_FRAGMENT
)
2354 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2357 /* FINISHME: It should be possible to implement this optimization when there
2358 * are multiple drawbuffers.
2360 if (key
->nr_color_regions
!= 1)
2363 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2364 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2365 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2366 assert(fb_write
->eot
);
2367 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2369 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2371 /* There wasn't one; nothing to do. */
2372 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2375 /* 3D Sampler » Messages » Message Format
2377 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2378 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2380 if (tex_inst
->opcode
== SHADER_OPCODE_TXS
||
2381 tex_inst
->opcode
== SHADER_OPCODE_SAMPLEINFO
||
2382 tex_inst
->opcode
== SHADER_OPCODE_LOD
||
2383 tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2384 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2387 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2388 * It's very likely to be the previous instruction.
2390 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2391 if (load_payload
->is_head_sentinel() ||
2392 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2395 assert(!tex_inst
->eot
); /* We can't get here twice */
2396 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2398 const fs_builder
ibld(this, block
, tex_inst
);
2400 tex_inst
->offset
|= fb_write
->target
<< 24;
2401 tex_inst
->eot
= true;
2402 tex_inst
->dst
= ibld
.null_reg_ud();
2403 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2405 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2406 * to create a new LOAD_PAYLOAD command with the same sources and a space
2407 * saved for the header. Using a new destination register not only makes sure
2408 * we have enough space, but it will make sure the dead code eliminator kills
2409 * the instruction that this will replace.
2411 if (tex_inst
->header_size
!= 0)
2414 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2415 load_payload
->sources
+ 1);
2416 fs_reg
*new_sources
=
2417 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2419 new_sources
[0] = fs_reg();
2420 for (int i
= 0; i
< load_payload
->sources
; i
++)
2421 new_sources
[i
+1] = load_payload
->src
[i
];
2423 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2424 * requires a lot of information about the sources to appropriately figure
2425 * out the number of registers needed to be used. Given this stage in our
2426 * optimization, we may not have the appropriate GRFs required by
2427 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2428 * manually emit the instruction.
2430 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2431 load_payload
->exec_size
,
2434 load_payload
->sources
+ 1);
2436 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2437 new_load_payload
->header_size
= 1;
2439 tex_inst
->header_size
= 1;
2440 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2441 tex_inst
->src
[0] = send_header
;
2447 fs_visitor::opt_register_renaming()
2449 bool progress
= false;
2452 int remap
[alloc
.count
];
2453 memset(remap
, -1, sizeof(int) * alloc
.count
);
2455 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2456 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2458 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2459 inst
->opcode
== BRW_OPCODE_WHILE
) {
2463 /* Rewrite instruction sources. */
2464 for (int i
= 0; i
< inst
->sources
; i
++) {
2465 if (inst
->src
[i
].file
== VGRF
&&
2466 remap
[inst
->src
[i
].nr
] != -1 &&
2467 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2468 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2473 const int dst
= inst
->dst
.nr
;
2476 inst
->dst
.file
== VGRF
&&
2477 alloc
.sizes
[inst
->dst
.nr
] == inst
->exec_size
/ 8 &&
2478 !inst
->is_partial_write()) {
2479 if (remap
[dst
] == -1) {
2482 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2483 inst
->dst
.nr
= remap
[dst
];
2486 } else if (inst
->dst
.file
== VGRF
&&
2488 remap
[dst
] != dst
) {
2489 inst
->dst
.nr
= remap
[dst
];
2495 invalidate_live_intervals();
2497 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2498 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2499 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2508 * Remove redundant or useless discard jumps.
2510 * For example, we can eliminate jumps in the following sequence:
2512 * discard-jump (redundant with the next jump)
2513 * discard-jump (useless; jumps to the next instruction)
2517 fs_visitor::opt_redundant_discard_jumps()
2519 bool progress
= false;
2521 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2523 fs_inst
*placeholder_halt
= NULL
;
2524 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2525 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2526 placeholder_halt
= inst
;
2531 if (!placeholder_halt
)
2534 /* Delete any HALTs immediately before the placeholder halt. */
2535 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2536 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2537 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2538 prev
->remove(last_bblock
);
2543 invalidate_live_intervals();
2549 fs_visitor::compute_to_mrf()
2551 bool progress
= false;
2554 /* No MRFs on Gen >= 7. */
2555 if (devinfo
->gen
>= 7)
2558 calculate_live_intervals();
2560 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2564 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2565 inst
->is_partial_write() ||
2566 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2567 inst
->dst
.type
!= inst
->src
[0].type
||
2568 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2569 !inst
->src
[0].is_contiguous() ||
2570 inst
->src
[0].subreg_offset
)
2573 /* Work out which hardware MRF registers are written by this
2576 int mrf_low
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2578 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2579 mrf_high
= mrf_low
+ 4;
2580 } else if (inst
->exec_size
== 16) {
2581 mrf_high
= mrf_low
+ 1;
2586 /* Can't compute-to-MRF this GRF if someone else was going to
2589 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2592 /* Found a move of a GRF to a MRF. Let's see if we can go
2593 * rewrite the thing that made this GRF to write into the MRF.
2595 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2596 if (scan_inst
->dst
.file
== VGRF
&&
2597 scan_inst
->dst
.nr
== inst
->src
[0].nr
) {
2598 /* Found the last thing to write our reg we want to turn
2599 * into a compute-to-MRF.
2602 /* If this one instruction didn't populate all the
2603 * channels, bail. We might be able to rewrite everything
2604 * that writes that reg, but it would require smarter
2605 * tracking to delay the rewriting until complete success.
2607 if (scan_inst
->is_partial_write())
2610 /* Things returning more than one register would need us to
2611 * understand coalescing out more than one MOV at a time.
2613 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2616 /* SEND instructions can't have MRF as a destination. */
2617 if (scan_inst
->mlen
)
2620 if (devinfo
->gen
== 6) {
2621 /* gen6 math instructions must have the destination be
2622 * GRF, so no compute-to-MRF for them.
2624 if (scan_inst
->is_math()) {
2629 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2630 /* Found the creator of our MRF's source value. */
2631 scan_inst
->dst
.file
= MRF
;
2632 scan_inst
->dst
.nr
= inst
->dst
.nr
;
2633 scan_inst
->saturate
|= inst
->saturate
;
2634 inst
->remove(block
);
2640 /* We don't handle control flow here. Most computation of
2641 * values that end up in MRFs are shortly before the MRF
2644 if (block
->start() == scan_inst
)
2647 /* You can't read from an MRF, so if someone else reads our
2648 * MRF's source GRF that we wanted to rewrite, that stops us.
2650 bool interfered
= false;
2651 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2652 if (scan_inst
->src
[i
].file
== VGRF
&&
2653 scan_inst
->src
[i
].nr
== inst
->src
[0].nr
&&
2654 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2661 if (scan_inst
->dst
.file
== MRF
) {
2662 /* If somebody else writes our MRF here, we can't
2663 * compute-to-MRF before that.
2665 int scan_mrf_low
= scan_inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2668 if (scan_inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2669 scan_mrf_high
= scan_mrf_low
+ 4;
2670 } else if (scan_inst
->exec_size
== 16) {
2671 scan_mrf_high
= scan_mrf_low
+ 1;
2673 scan_mrf_high
= scan_mrf_low
;
2676 if (mrf_low
== scan_mrf_low
||
2677 mrf_low
== scan_mrf_high
||
2678 mrf_high
== scan_mrf_low
||
2679 mrf_high
== scan_mrf_high
) {
2684 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2685 /* Found a SEND instruction, which means that there are
2686 * live values in MRFs from base_mrf to base_mrf +
2687 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2690 if (mrf_low
>= scan_inst
->base_mrf
&&
2691 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2694 if (mrf_high
>= scan_inst
->base_mrf
&&
2695 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2703 invalidate_live_intervals();
2709 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2710 * flow. We could probably do better here with some form of divergence
2714 fs_visitor::eliminate_find_live_channel()
2716 bool progress
= false;
2719 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2720 switch (inst
->opcode
) {
2726 case BRW_OPCODE_ENDIF
:
2727 case BRW_OPCODE_WHILE
:
2731 case FS_OPCODE_DISCARD_JUMP
:
2732 /* This can potentially make control flow non-uniform until the end
2737 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2739 inst
->opcode
= BRW_OPCODE_MOV
;
2740 inst
->src
[0] = fs_reg(0u);
2742 inst
->force_writemask_all
= true;
2756 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2757 * instructions to FS_OPCODE_REP_FB_WRITE.
2760 fs_visitor::emit_repclear_shader()
2762 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2764 int color_mrf
= base_mrf
+ 2;
2766 fs_inst
*mov
= bld
.exec_all().group(4, 0)
2767 .MOV(brw_message_reg(color_mrf
),
2768 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2771 if (key
->nr_color_regions
== 1) {
2772 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2773 write
->saturate
= key
->clamp_fragment_color
;
2774 write
->base_mrf
= color_mrf
;
2776 write
->header_size
= 0;
2779 assume(key
->nr_color_regions
> 0);
2780 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2781 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2782 write
->saturate
= key
->clamp_fragment_color
;
2783 write
->base_mrf
= base_mrf
;
2785 write
->header_size
= 2;
2793 assign_constant_locations();
2794 assign_curb_setup();
2796 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2797 assert(mov
->src
[0].file
== FIXED_GRF
);
2798 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2802 * Walks through basic blocks, looking for repeated MRF writes and
2803 * removing the later ones.
2806 fs_visitor::remove_duplicate_mrf_writes()
2808 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2809 bool progress
= false;
2811 /* Need to update the MRF tracking for compressed instructions. */
2812 if (dispatch_width
== 16)
2815 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2817 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2818 if (inst
->is_control_flow()) {
2819 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2822 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2823 inst
->dst
.file
== MRF
) {
2824 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
2825 if (prev_inst
&& inst
->equals(prev_inst
)) {
2826 inst
->remove(block
);
2832 /* Clear out the last-write records for MRFs that were overwritten. */
2833 if (inst
->dst
.file
== MRF
) {
2834 last_mrf_move
[inst
->dst
.nr
] = NULL
;
2837 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2838 /* Found a SEND instruction, which will include two or fewer
2839 * implied MRF writes. We could do better here.
2841 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2842 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2846 /* Clear out any MRF move records whose sources got overwritten. */
2847 if (inst
->dst
.file
== VGRF
) {
2848 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2849 if (last_mrf_move
[i
] &&
2850 last_mrf_move
[i
]->src
[0].nr
== inst
->dst
.nr
) {
2851 last_mrf_move
[i
] = NULL
;
2856 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2857 inst
->dst
.file
== MRF
&&
2858 inst
->src
[0].file
== VGRF
&&
2859 !inst
->is_partial_write()) {
2860 last_mrf_move
[inst
->dst
.nr
] = inst
;
2865 invalidate_live_intervals();
2871 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2873 /* Clear the flag for registers that actually got read (as expected). */
2874 for (int i
= 0; i
< inst
->sources
; i
++) {
2876 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
2877 grf
= inst
->src
[i
].nr
;
2882 if (grf
>= first_grf
&&
2883 grf
< first_grf
+ grf_len
) {
2884 deps
[grf
- first_grf
] = false;
2885 if (inst
->exec_size
== 16)
2886 deps
[grf
- first_grf
+ 1] = false;
2892 * Implements this workaround for the original 965:
2894 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2895 * check for post destination dependencies on this instruction, software
2896 * must ensure that there is no destination hazard for the case of ‘write
2897 * followed by a posted write’ shown in the following example.
2900 * 2. send r3.xy <rest of send instruction>
2903 * Due to no post-destination dependency check on the ‘send’, the above
2904 * code sequence could have two instructions (1 and 2) in flight at the
2905 * same time that both consider ‘r3’ as the target of their final writes.
2908 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2911 int write_len
= inst
->regs_written
;
2912 int first_write_grf
= inst
->dst
.nr
;
2913 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2914 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2916 memset(needs_dep
, false, sizeof(needs_dep
));
2917 memset(needs_dep
, true, write_len
);
2919 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2921 /* Walk backwards looking for writes to registers we're writing which
2922 * aren't read since being written. If we hit the start of the program,
2923 * we assume that there are no outstanding dependencies on entry to the
2926 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2927 /* If we hit control flow, assume that there *are* outstanding
2928 * dependencies, and force their cleanup before our instruction.
2930 if (block
->start() == scan_inst
) {
2931 for (int i
= 0; i
< write_len
; i
++) {
2933 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
2934 first_write_grf
+ i
);
2939 /* We insert our reads as late as possible on the assumption that any
2940 * instruction but a MOV that might have left us an outstanding
2941 * dependency has more latency than a MOV.
2943 if (scan_inst
->dst
.file
== VGRF
) {
2944 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2945 int reg
= scan_inst
->dst
.nr
+ i
;
2947 if (reg
>= first_write_grf
&&
2948 reg
< first_write_grf
+ write_len
&&
2949 needs_dep
[reg
- first_write_grf
]) {
2950 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
2951 needs_dep
[reg
- first_write_grf
] = false;
2952 if (scan_inst
->exec_size
== 16)
2953 needs_dep
[reg
- first_write_grf
+ 1] = false;
2958 /* Clear the flag for registers that actually got read (as expected). */
2959 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2961 /* Continue the loop only if we haven't resolved all the dependencies */
2963 for (i
= 0; i
< write_len
; i
++) {
2973 * Implements this workaround for the original 965:
2975 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2976 * used as a destination register until after it has been sourced by an
2977 * instruction with a different destination register.
2980 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
2982 int write_len
= inst
->regs_written
;
2983 int first_write_grf
= inst
->dst
.nr
;
2984 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2985 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2987 memset(needs_dep
, false, sizeof(needs_dep
));
2988 memset(needs_dep
, true, write_len
);
2989 /* Walk forwards looking for writes to registers we're writing which aren't
2990 * read before being written.
2992 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
2993 /* If we hit control flow, force resolve all remaining dependencies. */
2994 if (block
->end() == scan_inst
) {
2995 for (int i
= 0; i
< write_len
; i
++) {
2997 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
2998 first_write_grf
+ i
);
3003 /* Clear the flag for registers that actually got read (as expected). */
3004 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3006 /* We insert our reads as late as possible since they're reading the
3007 * result of a SEND, which has massive latency.
3009 if (scan_inst
->dst
.file
== VGRF
&&
3010 scan_inst
->dst
.nr
>= first_write_grf
&&
3011 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3012 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3013 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3015 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3018 /* Continue the loop only if we haven't resolved all the dependencies */
3020 for (i
= 0; i
< write_len
; i
++) {
3030 fs_visitor::insert_gen4_send_dependency_workarounds()
3032 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3035 bool progress
= false;
3037 /* Note that we're done with register allocation, so GRF fs_regs always
3038 * have a .reg_offset of 0.
3041 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3042 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3043 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3044 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3050 invalidate_live_intervals();
3054 * Turns the generic expression-style uniform pull constant load instruction
3055 * into a hardware-specific series of instructions for loading a pull
3058 * The expression style allows the CSE pass before this to optimize out
3059 * repeated loads from the same offset, and gives the pre-register-allocation
3060 * scheduling full flexibility, while the conversion to native instructions
3061 * allows the post-register-allocation scheduler the best information
3064 * Note that execution masking for setting up pull constant loads is special:
3065 * the channels that need to be written are unrelated to the current execution
3066 * mask, since a later instruction will use one of the result channels as a
3067 * source operand for all 8 or 16 of its channels.
3070 fs_visitor::lower_uniform_pull_constant_loads()
3072 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3073 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3076 if (devinfo
->gen
>= 7) {
3077 /* The offset arg before was a vec4-aligned byte offset. We need to
3078 * turn it into a dword offset.
3080 fs_reg const_offset_reg
= inst
->src
[1];
3081 assert(const_offset_reg
.file
== IMM
&&
3082 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3083 const_offset_reg
.ud
/= 4;
3085 fs_reg payload
, offset
;
3086 if (devinfo
->gen
>= 9) {
3087 /* We have to use a message header on Skylake to get SIMD4x2
3088 * mode. Reserve space for the register.
3090 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3091 offset
.reg_offset
++;
3094 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3098 /* This is actually going to be a MOV, but since only the first dword
3099 * is accessed, we have a special opcode to do just that one. Note
3100 * that this needs to be an operation that will be considered a def
3101 * by live variable analysis, or register allocation will explode.
3103 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3104 8, offset
, const_offset_reg
);
3105 setup
->force_writemask_all
= true;
3107 setup
->ir
= inst
->ir
;
3108 setup
->annotation
= inst
->annotation
;
3109 inst
->insert_before(block
, setup
);
3111 /* Similarly, this will only populate the first 4 channels of the
3112 * result register (since we only use smear values from 0-3), but we
3113 * don't tell the optimizer.
3115 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3116 inst
->src
[1] = payload
;
3117 inst
->base_mrf
= -1;
3119 invalidate_live_intervals();
3121 /* Before register allocation, we didn't tell the scheduler about the
3122 * MRF we use. We know it's safe to use this MRF because nothing
3123 * else does except for register spill/unspill, which generates and
3124 * uses its MRF within a single IR instruction.
3126 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3133 fs_visitor::lower_load_payload()
3135 bool progress
= false;
3137 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3138 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3141 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3142 assert(inst
->saturate
== false);
3143 fs_reg dst
= inst
->dst
;
3145 /* Get rid of COMPR4. We'll add it back in if we need it */
3146 if (dst
.file
== MRF
)
3147 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3149 const fs_builder
ibld(this, block
, inst
);
3150 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3152 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3153 if (inst
->src
[i
].file
!= BAD_FILE
) {
3154 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3155 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3156 hbld
.MOV(mov_dst
, mov_src
);
3158 dst
= offset(dst
, hbld
, 1);
3161 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3162 inst
->exec_size
> 8) {
3163 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3164 * a straightforward copy. Instead, the result of the
3165 * LOAD_PAYLOAD is treated as interleaved and the first four
3166 * non-header sources are unpacked as:
3177 * This is used for gen <= 5 fb writes.
3179 assert(inst
->exec_size
== 16);
3180 assert(inst
->header_size
+ 4 <= inst
->sources
);
3181 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3182 if (inst
->src
[i
].file
!= BAD_FILE
) {
3183 if (devinfo
->has_compr4
) {
3184 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3185 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3186 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3188 /* Platform doesn't have COMPR4. We have to fake it */
3189 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3190 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3192 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3199 /* The loop above only ever incremented us through the first set
3200 * of 4 registers. However, thanks to the magic of COMPR4, we
3201 * actually wrote to the first 8 registers, so we need to take
3202 * that into account now.
3206 /* The COMPR4 code took care of the first 4 sources. We'll let
3207 * the regular path handle any remaining sources. Yes, we are
3208 * modifying the instruction but we're about to delete it so
3209 * this really doesn't hurt anything.
3211 inst
->header_size
+= 4;
3214 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3215 if (inst
->src
[i
].file
!= BAD_FILE
)
3216 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3217 dst
= offset(dst
, ibld
, 1);
3220 inst
->remove(block
);
3225 invalidate_live_intervals();
3231 fs_visitor::lower_integer_multiplication()
3233 bool progress
= false;
3235 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3236 const fs_builder
ibld(this, block
, inst
);
3238 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3239 if (inst
->dst
.is_accumulator() ||
3240 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3241 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3244 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3245 * operation directly, but CHV/BXT cannot.
3247 if (devinfo
->gen
>= 8 &&
3248 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3251 if (inst
->src
[1].file
== IMM
&&
3252 inst
->src
[1].ud
< (1 << 16)) {
3253 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3254 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3257 * If multiplying by an immediate value that fits in 16-bits, do a
3258 * single MUL instruction with that value in the proper location.
3260 if (devinfo
->gen
< 7) {
3261 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3263 ibld
.MOV(imm
, inst
->src
[1]);
3264 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3266 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3269 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3270 * do 32-bit integer multiplication in one instruction, but instead
3271 * must do a sequence (which actually calculates a 64-bit result):
3273 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3274 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3275 * mov(8) g2<1>D acc0<8,8,1>D
3277 * But on Gen > 6, the ability to use second accumulator register
3278 * (acc1) for non-float data types was removed, preventing a simple
3279 * implementation in SIMD16. A 16-channel result can be calculated by
3280 * executing the three instructions twice in SIMD8, once with quarter
3281 * control of 1Q for the first eight channels and again with 2Q for
3282 * the second eight channels.
3284 * Which accumulator register is implicitly accessed (by AccWrEnable
3285 * for instance) is determined by the quarter control. Unfortunately
3286 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3287 * implicit accumulator access by an instruction with 2Q will access
3288 * acc1 regardless of whether the data type is usable in acc1.
3290 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3291 * integer data types.
3293 * Since we only want the low 32-bits of the result, we can do two
3294 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3295 * adjust the high result and add them (like the mach is doing):
3297 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3298 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3299 * shl(8) g9<1>D g8<8,8,1>D 16D
3300 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3302 * We avoid the shl instruction by realizing that we only want to add
3303 * the low 16-bits of the "high" result to the high 16-bits of the
3304 * "low" result and using proper regioning on the add:
3306 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3307 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3308 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3310 * Since it does not use the (single) accumulator register, we can
3311 * schedule multi-component multiplications much better.
3314 fs_reg orig_dst
= inst
->dst
;
3315 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3316 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3319 fs_reg low
= inst
->dst
;
3320 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3323 if (devinfo
->gen
>= 7) {
3324 fs_reg src1_0_w
= inst
->src
[1];
3325 fs_reg src1_1_w
= inst
->src
[1];
3327 if (inst
->src
[1].file
== IMM
) {
3328 src1_0_w
.ud
&= 0xffff;
3331 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3332 if (src1_0_w
.stride
!= 0) {
3333 assert(src1_0_w
.stride
== 1);
3334 src1_0_w
.stride
= 2;
3337 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3338 if (src1_1_w
.stride
!= 0) {
3339 assert(src1_1_w
.stride
== 1);
3340 src1_1_w
.stride
= 2;
3342 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3344 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3345 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3347 fs_reg src0_0_w
= inst
->src
[0];
3348 fs_reg src0_1_w
= inst
->src
[0];
3350 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3351 if (src0_0_w
.stride
!= 0) {
3352 assert(src0_0_w
.stride
== 1);
3353 src0_0_w
.stride
= 2;
3356 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3357 if (src0_1_w
.stride
!= 0) {
3358 assert(src0_1_w
.stride
== 1);
3359 src0_1_w
.stride
= 2;
3361 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3363 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3364 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3367 fs_reg dst
= inst
->dst
;
3368 dst
.type
= BRW_REGISTER_TYPE_UW
;
3369 dst
.subreg_offset
= 2;
3372 high
.type
= BRW_REGISTER_TYPE_UW
;
3375 low
.type
= BRW_REGISTER_TYPE_UW
;
3376 low
.subreg_offset
= 2;
3379 ibld
.ADD(dst
, low
, high
);
3381 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3382 set_condmod(inst
->conditional_mod
,
3383 ibld
.MOV(orig_dst
, inst
->dst
));
3387 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3388 /* Should have been lowered to 8-wide. */
3389 assert(inst
->exec_size
<= 8);
3390 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3392 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3393 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3395 if (devinfo
->gen
>= 8) {
3396 /* Until Gen8, integer multiplies read 32-bits from one source,
3397 * and 16-bits from the other, and relying on the MACH instruction
3398 * to generate the high bits of the result.
3400 * On Gen8, the multiply instruction does a full 32x32-bit
3401 * multiply, but in order to do a 64-bit multiply we can simulate
3402 * the previous behavior and then use a MACH instruction.
3404 * FINISHME: Don't use source modifiers on src1.
3406 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3407 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3408 mul
->src
[1].type
= (type_is_signed(mul
->src
[1].type
) ?
3409 BRW_REGISTER_TYPE_W
: BRW_REGISTER_TYPE_UW
);
3410 mul
->src
[1].stride
*= 2;
3412 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3413 inst
->force_sechalf
) {
3414 /* Among other things the quarter control bits influence which
3415 * accumulator register is used by the hardware for instructions
3416 * that access the accumulator implicitly (e.g. MACH). A
3417 * second-half instruction would normally map to acc1, which
3418 * doesn't exist on Gen7 and up (the hardware does emulate it for
3419 * floating-point instructions *only* by taking advantage of the
3420 * extra precision of acc0 not normally used for floating point
3423 * HSW and up are careful enough not to try to access an
3424 * accumulator register that doesn't exist, but on earlier Gen7
3425 * hardware we need to make sure that the quarter control bits are
3426 * zero to avoid non-deterministic behaviour and emit an extra MOV
3427 * to get the result masked correctly according to the current
3430 mach
->force_sechalf
= false;
3431 mach
->force_writemask_all
= true;
3432 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3433 ibld
.MOV(inst
->dst
, mach
->dst
);
3439 inst
->remove(block
);
3444 invalidate_live_intervals();
3450 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3451 fs_reg
*dst
, fs_reg color
, unsigned components
)
3453 if (key
->clamp_fragment_color
) {
3454 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3455 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3457 for (unsigned i
= 0; i
< components
; i
++)
3459 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3464 for (unsigned i
= 0; i
< components
; i
++)
3465 dst
[i
] = offset(color
, bld
, i
);
3469 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3470 const brw_wm_prog_data
*prog_data
,
3471 const brw_wm_prog_key
*key
,
3472 const fs_visitor::thread_payload
&payload
)
3474 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3475 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3476 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3477 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3478 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3479 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3480 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3481 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3482 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3483 const unsigned components
=
3484 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3486 /* We can potentially have a message length of up to 15, so we have to set
3487 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3490 int header_size
= 2, payload_header_size
;
3491 unsigned length
= 0;
3493 /* From the Sandy Bridge PRM, volume 4, page 198:
3495 * "Dispatched Pixel Enables. One bit per pixel indicating
3496 * which pixels were originally enabled when the thread was
3497 * dispatched. This field is only required for the end-of-
3498 * thread message and on all dual-source messages."
3500 if (devinfo
->gen
>= 6 &&
3501 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3502 color1
.file
== BAD_FILE
&&
3503 key
->nr_color_regions
== 1) {
3507 if (header_size
!= 0) {
3508 assert(header_size
== 2);
3509 /* Allocate 2 registers for a header */
3513 if (payload
.aa_dest_stencil_reg
) {
3514 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3515 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3516 .MOV(sources
[length
],
3517 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3521 if (prog_data
->uses_omask
) {
3522 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3523 BRW_REGISTER_TYPE_UD
);
3525 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3526 * relevant. Since it's unsigned single words one vgrf is always
3527 * 16-wide, but only the lower or higher 8 channels will be used by the
3528 * hardware when doing a SIMD8 write depending on whether we have
3529 * selected the subspans for the first or second half respectively.
3531 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3532 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3533 sample_mask
.stride
*= 2;
3535 bld
.exec_all().annotate("FB write oMask")
3536 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3537 inst
->force_sechalf
),
3542 payload_header_size
= length
;
3544 if (src0_alpha
.file
!= BAD_FILE
) {
3545 /* FIXME: This is being passed at the wrong location in the payload and
3546 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3547 * It's supposed to be immediately before oMask but there seems to be no
3548 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3549 * requires header sources to form a contiguous segment at the beginning
3550 * of the message and src0_alpha has per-channel semantics.
3552 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3556 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3559 if (color1
.file
!= BAD_FILE
) {
3560 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3564 if (src_depth
.file
!= BAD_FILE
) {
3565 sources
[length
] = src_depth
;
3569 if (dst_depth
.file
!= BAD_FILE
) {
3570 sources
[length
] = dst_depth
;
3574 if (src_stencil
.file
!= BAD_FILE
) {
3575 assert(devinfo
->gen
>= 9);
3576 assert(bld
.dispatch_width() != 16);
3578 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3579 bld
.exec_all().annotate("FB write OS")
3580 .emit(FS_OPCODE_PACK_STENCIL_REF
, sources
[length
],
3581 retype(src_stencil
, BRW_REGISTER_TYPE_UB
));
3586 if (devinfo
->gen
>= 7) {
3587 /* Send from the GRF */
3588 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3589 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3590 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3591 load
->dst
= payload
;
3593 inst
->src
[0] = payload
;
3594 inst
->resize_sources(1);
3595 inst
->base_mrf
= -1;
3597 /* Send from the MRF */
3598 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3599 sources
, length
, payload_header_size
);
3601 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3602 * will do this for us if we just give it a COMPR4 destination.
3604 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3605 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3607 inst
->resize_sources(0);
3611 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3612 inst
->mlen
= load
->regs_written
;
3613 inst
->header_size
= header_size
;
3617 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3618 const fs_reg
&coordinate
,
3619 const fs_reg
&shadow_c
,
3620 const fs_reg
&lod
, const fs_reg
&lod2
,
3621 const fs_reg
&sampler
,
3622 unsigned coord_components
,
3623 unsigned grad_components
)
3625 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3626 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3627 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3628 fs_reg msg_end
= msg_begin
;
3631 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3633 for (unsigned i
= 0; i
< coord_components
; i
++)
3634 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3635 offset(coordinate
, bld
, i
));
3637 msg_end
= offset(msg_end
, bld
, coord_components
);
3639 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3640 * require all three components to be present and zero if they are unused.
3642 if (coord_components
> 0 &&
3643 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3644 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3645 for (unsigned i
= coord_components
; i
< 3; i
++)
3646 bld
.MOV(offset(msg_end
, bld
, i
), fs_reg(0.0f
));
3648 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3651 if (op
== SHADER_OPCODE_TXD
) {
3652 /* TXD unsupported in SIMD16 mode. */
3653 assert(bld
.dispatch_width() == 8);
3655 /* the slots for u and v are always present, but r is optional */
3656 if (coord_components
< 2)
3657 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3660 * dPdx = dudx, dvdx, drdx
3661 * dPdy = dudy, dvdy, drdy
3663 * 1-arg: Does not exist.
3665 * 2-arg: dudx dvdx dudy dvdy
3666 * dPdx.x dPdx.y dPdy.x dPdy.y
3669 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3670 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3671 * m5 m6 m7 m8 m9 m10
3673 for (unsigned i
= 0; i
< grad_components
; i
++)
3674 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3676 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3678 for (unsigned i
= 0; i
< grad_components
; i
++)
3679 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3681 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3685 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3686 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3688 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3689 bld
.dispatch_width() == 16);
3691 const brw_reg_type type
=
3692 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3693 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3694 bld
.MOV(retype(msg_end
, type
), lod
);
3695 msg_end
= offset(msg_end
, bld
, 1);
3698 if (shadow_c
.file
!= BAD_FILE
) {
3699 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3700 /* There's no plain shadow compare message, so we use shadow
3701 * compare with a bias of 0.0.
3703 bld
.MOV(msg_end
, fs_reg(0.0f
));
3704 msg_end
= offset(msg_end
, bld
, 1);
3707 bld
.MOV(msg_end
, shadow_c
);
3708 msg_end
= offset(msg_end
, bld
, 1);
3712 inst
->src
[0] = reg_undef
;
3713 inst
->src
[1] = sampler
;
3714 inst
->resize_sources(2);
3715 inst
->base_mrf
= msg_begin
.nr
;
3716 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3717 inst
->header_size
= 1;
3721 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3723 const fs_reg
&shadow_c
,
3724 fs_reg lod
, fs_reg lod2
,
3725 const fs_reg
&sample_index
,
3726 const fs_reg
&sampler
,
3727 const fs_reg
&offset_value
,
3728 unsigned coord_components
,
3729 unsigned grad_components
)
3731 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3732 fs_reg msg_coords
= message
;
3733 unsigned header_size
= 0;
3735 if (offset_value
.file
!= BAD_FILE
) {
3736 /* The offsets set up by the visitor are in the m1 header, so we can't
3743 for (unsigned i
= 0; i
< coord_components
; i
++) {
3744 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3745 coordinate
= offset(coordinate
, bld
, 1);
3747 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3748 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3750 if (shadow_c
.file
!= BAD_FILE
) {
3751 fs_reg msg_shadow
= msg_lod
;
3752 bld
.MOV(msg_shadow
, shadow_c
);
3753 msg_lod
= offset(msg_shadow
, bld
, 1);
3758 case SHADER_OPCODE_TXL
:
3760 bld
.MOV(msg_lod
, lod
);
3761 msg_end
= offset(msg_lod
, bld
, 1);
3763 case SHADER_OPCODE_TXD
:
3766 * dPdx = dudx, dvdx, drdx
3767 * dPdy = dudy, dvdy, drdy
3769 * Load up these values:
3770 * - dudx dudy dvdx dvdy drdx drdy
3771 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3774 for (unsigned i
= 0; i
< grad_components
; i
++) {
3775 bld
.MOV(msg_end
, lod
);
3776 lod
= offset(lod
, bld
, 1);
3777 msg_end
= offset(msg_end
, bld
, 1);
3779 bld
.MOV(msg_end
, lod2
);
3780 lod2
= offset(lod2
, bld
, 1);
3781 msg_end
= offset(msg_end
, bld
, 1);
3784 case SHADER_OPCODE_TXS
:
3785 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3786 bld
.MOV(msg_lod
, lod
);
3787 msg_end
= offset(msg_lod
, bld
, 1);
3789 case SHADER_OPCODE_TXF
:
3790 msg_lod
= offset(msg_coords
, bld
, 3);
3791 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3792 msg_end
= offset(msg_lod
, bld
, 1);
3794 case SHADER_OPCODE_TXF_CMS
:
3795 msg_lod
= offset(msg_coords
, bld
, 3);
3797 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u));
3799 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3800 msg_end
= offset(msg_lod
, bld
, 2);
3807 inst
->src
[0] = reg_undef
;
3808 inst
->src
[1] = sampler
;
3809 inst
->resize_sources(2);
3810 inst
->base_mrf
= message
.nr
;
3811 inst
->mlen
= msg_end
.nr
- message
.nr
;
3812 inst
->header_size
= header_size
;
3814 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3815 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3819 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3821 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3824 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
3828 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3830 const fs_reg
&shadow_c
,
3831 fs_reg lod
, fs_reg lod2
,
3832 const fs_reg
&sample_index
,
3833 const fs_reg
&mcs
, const fs_reg
&sampler
,
3834 fs_reg offset_value
,
3835 unsigned coord_components
,
3836 unsigned grad_components
)
3838 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3839 int reg_width
= bld
.dispatch_width() / 8;
3840 unsigned header_size
= 0, length
= 0;
3841 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3842 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3843 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3845 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3846 offset_value
.file
!= BAD_FILE
||
3847 is_high_sampler(devinfo
, sampler
)) {
3848 /* For general texture offsets (no txf workaround), we need a header to
3849 * put them in. Note that we're only reserving space for it in the
3850 * message payload as it will be initialized implicitly by the
3853 * TG4 needs to place its channel select in the header, for interaction
3854 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3855 * larger sampler numbers we need to offset the Sampler State Pointer in
3859 sources
[0] = fs_reg();
3863 if (shadow_c
.file
!= BAD_FILE
) {
3864 bld
.MOV(sources
[length
], shadow_c
);
3868 bool coordinate_done
= false;
3870 /* The sampler can only meaningfully compute LOD for fragment shader
3871 * messages. For all other stages, we change the opcode to TXL and
3872 * hardcode the LOD to 0.
3874 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3875 op
== SHADER_OPCODE_TEX
) {
3876 op
= SHADER_OPCODE_TXL
;
3880 /* Set up the LOD info */
3883 case SHADER_OPCODE_TXL
:
3884 bld
.MOV(sources
[length
], lod
);
3887 case SHADER_OPCODE_TXD
:
3888 /* TXD should have been lowered in SIMD16 mode. */
3889 assert(bld
.dispatch_width() == 8);
3891 /* Load dPdx and the coordinate together:
3892 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3894 for (unsigned i
= 0; i
< coord_components
; i
++) {
3895 bld
.MOV(sources
[length
], coordinate
);
3896 coordinate
= offset(coordinate
, bld
, 1);
3899 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3900 * only derivatives for (u, v, r).
3902 if (i
< grad_components
) {
3903 bld
.MOV(sources
[length
], lod
);
3904 lod
= offset(lod
, bld
, 1);
3907 bld
.MOV(sources
[length
], lod2
);
3908 lod2
= offset(lod2
, bld
, 1);
3913 coordinate_done
= true;
3915 case SHADER_OPCODE_TXS
:
3916 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
3919 case SHADER_OPCODE_TXF
:
3920 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
3921 * On Gen9 they are u, v, lod, r
3923 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3924 coordinate
= offset(coordinate
, bld
, 1);
3927 if (devinfo
->gen
>= 9) {
3928 if (coord_components
>= 2) {
3929 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3930 coordinate
= offset(coordinate
, bld
, 1);
3935 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
3938 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
3939 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3940 coordinate
= offset(coordinate
, bld
, 1);
3944 coordinate_done
= true;
3946 case SHADER_OPCODE_TXF_CMS
:
3947 case SHADER_OPCODE_TXF_CMS_W
:
3948 case SHADER_OPCODE_TXF_UMS
:
3949 case SHADER_OPCODE_TXF_MCS
:
3950 if (op
== SHADER_OPCODE_TXF_UMS
||
3951 op
== SHADER_OPCODE_TXF_CMS
||
3952 op
== SHADER_OPCODE_TXF_CMS_W
) {
3953 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
3957 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
3958 /* Data from the multisample control surface. */
3959 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
3962 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
3965 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
3966 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
3969 offset(mcs
, bld
, 1));
3974 /* There is no offsetting for this message; just copy in the integer
3975 * texture coordinates.
3977 for (unsigned i
= 0; i
< coord_components
; i
++) {
3978 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3979 coordinate
= offset(coordinate
, bld
, 1);
3983 coordinate_done
= true;
3985 case SHADER_OPCODE_TG4_OFFSET
:
3986 /* gather4_po_c should have been lowered in SIMD16 mode. */
3987 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
3989 /* More crazy intermixing */
3990 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
3991 bld
.MOV(sources
[length
], coordinate
);
3992 coordinate
= offset(coordinate
, bld
, 1);
3996 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
3997 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
3998 offset_value
= offset(offset_value
, bld
, 1);
4002 if (coord_components
== 3) { /* r if present */
4003 bld
.MOV(sources
[length
], coordinate
);
4004 coordinate
= offset(coordinate
, bld
, 1);
4008 coordinate_done
= true;
4014 /* Set up the coordinate (except for cases where it was done above) */
4015 if (!coordinate_done
) {
4016 for (unsigned i
= 0; i
< coord_components
; i
++) {
4017 bld
.MOV(sources
[length
], coordinate
);
4018 coordinate
= offset(coordinate
, bld
, 1);
4025 mlen
= length
* reg_width
- header_size
;
4027 mlen
= length
* reg_width
;
4029 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4030 BRW_REGISTER_TYPE_F
);
4031 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4033 /* Generate the SEND. */
4035 inst
->src
[0] = src_payload
;
4036 inst
->src
[1] = sampler
;
4037 inst
->resize_sources(2);
4038 inst
->base_mrf
= -1;
4040 inst
->header_size
= header_size
;
4042 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4043 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4047 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4049 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4050 const fs_reg
&coordinate
= inst
->src
[0];
4051 const fs_reg
&shadow_c
= inst
->src
[1];
4052 const fs_reg
&lod
= inst
->src
[2];
4053 const fs_reg
&lod2
= inst
->src
[3];
4054 const fs_reg
&sample_index
= inst
->src
[4];
4055 const fs_reg
&mcs
= inst
->src
[5];
4056 const fs_reg
&sampler
= inst
->src
[6];
4057 const fs_reg
&offset_value
= inst
->src
[7];
4058 assert(inst
->src
[8].file
== IMM
&& inst
->src
[9].file
== IMM
);
4059 const unsigned coord_components
= inst
->src
[8].ud
;
4060 const unsigned grad_components
= inst
->src
[9].ud
;
4062 if (devinfo
->gen
>= 7) {
4063 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4064 shadow_c
, lod
, lod2
, sample_index
,
4065 mcs
, sampler
, offset_value
,
4066 coord_components
, grad_components
);
4067 } else if (devinfo
->gen
>= 5) {
4068 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4069 shadow_c
, lod
, lod2
, sample_index
,
4070 sampler
, offset_value
,
4071 coord_components
, grad_components
);
4073 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4074 shadow_c
, lod
, lod2
, sampler
,
4075 coord_components
, grad_components
);
4080 * Initialize the header present in some typed and untyped surface
4084 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4086 fs_builder ubld
= bld
.exec_all().group(8, 0);
4087 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4088 ubld
.MOV(dst
, fs_reg(0));
4089 ubld
.MOV(component(dst
, 7), sample_mask
);
4094 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4095 const fs_reg
&sample_mask
)
4097 /* Get the logical send arguments. */
4098 const fs_reg
&addr
= inst
->src
[0];
4099 const fs_reg
&src
= inst
->src
[1];
4100 const fs_reg
&surface
= inst
->src
[2];
4101 const UNUSED fs_reg
&dims
= inst
->src
[3];
4102 const fs_reg
&arg
= inst
->src
[4];
4104 /* Calculate the total number of components of the payload. */
4105 const unsigned addr_sz
= inst
->components_read(0);
4106 const unsigned src_sz
= inst
->components_read(1);
4107 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4108 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4110 /* Allocate space for the payload. */
4111 fs_reg
*const components
= new fs_reg
[sz
];
4112 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4115 /* Construct the payload. */
4117 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4119 for (unsigned i
= 0; i
< addr_sz
; i
++)
4120 components
[n
++] = offset(addr
, bld
, i
);
4122 for (unsigned i
= 0; i
< src_sz
; i
++)
4123 components
[n
++] = offset(src
, bld
, i
);
4125 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4127 /* Update the original instruction. */
4129 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4130 inst
->header_size
= header_sz
;
4132 inst
->src
[0] = payload
;
4133 inst
->src
[1] = surface
;
4135 inst
->resize_sources(3);
4137 delete[] components
;
4141 fs_visitor::lower_logical_sends()
4143 bool progress
= false;
4145 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4146 const fs_builder
ibld(this, block
, inst
);
4148 switch (inst
->opcode
) {
4149 case FS_OPCODE_FB_WRITE_LOGICAL
:
4150 assert(stage
== MESA_SHADER_FRAGMENT
);
4151 lower_fb_write_logical_send(ibld
, inst
,
4152 (const brw_wm_prog_data
*)prog_data
,
4153 (const brw_wm_prog_key
*)key
,
4157 case SHADER_OPCODE_TEX_LOGICAL
:
4158 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4161 case SHADER_OPCODE_TXD_LOGICAL
:
4162 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4165 case SHADER_OPCODE_TXF_LOGICAL
:
4166 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4169 case SHADER_OPCODE_TXL_LOGICAL
:
4170 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4173 case SHADER_OPCODE_TXS_LOGICAL
:
4174 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4177 case FS_OPCODE_TXB_LOGICAL
:
4178 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4181 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4182 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4185 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4186 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4189 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4190 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4193 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4194 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4197 case SHADER_OPCODE_LOD_LOGICAL
:
4198 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4201 case SHADER_OPCODE_TG4_LOGICAL
:
4202 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4205 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4206 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4209 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4210 lower_surface_logical_send(ibld
, inst
,
4211 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4215 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4216 lower_surface_logical_send(ibld
, inst
,
4217 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4218 ibld
.sample_mask_reg());
4221 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4222 lower_surface_logical_send(ibld
, inst
,
4223 SHADER_OPCODE_UNTYPED_ATOMIC
,
4224 ibld
.sample_mask_reg());
4227 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4228 lower_surface_logical_send(ibld
, inst
,
4229 SHADER_OPCODE_TYPED_SURFACE_READ
,
4233 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4234 lower_surface_logical_send(ibld
, inst
,
4235 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4236 ibld
.sample_mask_reg());
4239 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4240 lower_surface_logical_send(ibld
, inst
,
4241 SHADER_OPCODE_TYPED_ATOMIC
,
4242 ibld
.sample_mask_reg());
4253 invalidate_live_intervals();
4259 * Get the closest native SIMD width supported by the hardware for instruction
4260 * \p inst. The instruction will be left untouched by
4261 * fs_visitor::lower_simd_width() if the returned value is equal to the
4262 * original execution size.
4265 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4266 const fs_inst
*inst
)
4268 switch (inst
->opcode
) {
4269 case BRW_OPCODE_MOV
:
4270 case BRW_OPCODE_SEL
:
4271 case BRW_OPCODE_NOT
:
4272 case BRW_OPCODE_AND
:
4274 case BRW_OPCODE_XOR
:
4275 case BRW_OPCODE_SHR
:
4276 case BRW_OPCODE_SHL
:
4277 case BRW_OPCODE_ASR
:
4278 case BRW_OPCODE_CMP
:
4279 case BRW_OPCODE_CMPN
:
4280 case BRW_OPCODE_CSEL
:
4281 case BRW_OPCODE_F32TO16
:
4282 case BRW_OPCODE_F16TO32
:
4283 case BRW_OPCODE_BFREV
:
4284 case BRW_OPCODE_BFE
:
4285 case BRW_OPCODE_BFI1
:
4286 case BRW_OPCODE_BFI2
:
4287 case BRW_OPCODE_ADD
:
4288 case BRW_OPCODE_MUL
:
4289 case BRW_OPCODE_AVG
:
4290 case BRW_OPCODE_FRC
:
4291 case BRW_OPCODE_RNDU
:
4292 case BRW_OPCODE_RNDD
:
4293 case BRW_OPCODE_RNDE
:
4294 case BRW_OPCODE_RNDZ
:
4295 case BRW_OPCODE_LZD
:
4296 case BRW_OPCODE_FBH
:
4297 case BRW_OPCODE_FBL
:
4298 case BRW_OPCODE_CBIT
:
4299 case BRW_OPCODE_SAD2
:
4300 case BRW_OPCODE_MAD
:
4301 case BRW_OPCODE_LRP
:
4302 case SHADER_OPCODE_RCP
:
4303 case SHADER_OPCODE_RSQ
:
4304 case SHADER_OPCODE_SQRT
:
4305 case SHADER_OPCODE_EXP2
:
4306 case SHADER_OPCODE_LOG2
:
4307 case SHADER_OPCODE_POW
:
4308 case SHADER_OPCODE_INT_QUOTIENT
:
4309 case SHADER_OPCODE_INT_REMAINDER
:
4310 case SHADER_OPCODE_SIN
:
4311 case SHADER_OPCODE_COS
: {
4312 /* According to the PRMs:
4313 * "A. In Direct Addressing mode, a source cannot span more than 2
4314 * adjacent GRF registers.
4315 * B. A destination cannot span more than 2 adjacent GRF registers."
4317 * Look for the source or destination with the largest register region
4318 * which is the one that is going to limit the overal execution size of
4319 * the instruction due to this rule.
4321 unsigned reg_count
= inst
->regs_written
;
4323 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4324 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4326 /* Calculate the maximum execution size of the instruction based on the
4327 * factor by which it goes over the hardware limit of 2 GRFs.
4329 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4331 case SHADER_OPCODE_MULH
:
4332 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4333 * is 8-wide on Gen7+.
4335 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4337 case FS_OPCODE_FB_WRITE_LOGICAL
:
4338 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4341 assert(devinfo
->gen
!= 6 ||
4342 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4343 inst
->exec_size
== 8);
4344 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4345 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4346 8 : inst
->exec_size
);
4348 case SHADER_OPCODE_TXD_LOGICAL
:
4349 /* TXD is unsupported in SIMD16 mode. */
4352 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4353 /* gather4_po_c is unsupported in SIMD16 mode. */
4354 const fs_reg
&shadow_c
= inst
->src
[1];
4355 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4357 case SHADER_OPCODE_TXL_LOGICAL
:
4358 case FS_OPCODE_TXB_LOGICAL
: {
4359 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4360 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4361 * mode because the message exceeds the maximum length of 11.
4363 const fs_reg
&shadow_c
= inst
->src
[1];
4364 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4366 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4369 return inst
->exec_size
;
4371 case SHADER_OPCODE_TXF_LOGICAL
:
4372 case SHADER_OPCODE_TXS_LOGICAL
:
4373 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4374 * messages. Use SIMD16 instead.
4376 if (devinfo
->gen
== 4)
4379 return inst
->exec_size
;
4381 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4382 /* This opcode can take up to 6 arguments which means that in some
4383 * circumstances it can end up with a message that is too long in SIMD16
4386 const unsigned coord_components
= inst
->src
[8].ud
;
4387 /* First three arguments are the sample index and the two arguments for
4390 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
4393 return inst
->exec_size
;
4396 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4397 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4398 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4402 return inst
->exec_size
;
4407 * The \p rows array of registers represents a \p num_rows by \p num_columns
4408 * matrix in row-major order, write it in column-major order into the register
4409 * passed as destination. \p stride gives the separation between matrix
4410 * elements in the input in fs_builder::dispatch_width() units.
4413 emit_transpose(const fs_builder
&bld
,
4414 const fs_reg
&dst
, const fs_reg
*rows
,
4415 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4417 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4419 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4420 for (unsigned j
= 0; j
< num_rows
; ++j
)
4421 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4424 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4426 delete[] components
;
4430 fs_visitor::lower_simd_width()
4432 bool progress
= false;
4434 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4435 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4437 if (lower_width
!= inst
->exec_size
) {
4438 /* Builder matching the original instruction. We may also need to
4439 * emit an instruction of width larger than the original, set the
4440 * execution size of the builder to the highest of both for now so
4441 * we're sure that both cases can be handled.
4443 const fs_builder ibld
= bld
.at(block
, inst
)
4444 .exec_all(inst
->force_writemask_all
)
4445 .group(MAX2(inst
->exec_size
, lower_width
),
4446 inst
->force_sechalf
);
4448 /* Split the copies in chunks of the execution width of either the
4449 * original or the lowered instruction, whichever is lower.
4451 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4452 const unsigned n
= inst
->exec_size
/ copy_width
;
4453 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4454 inst
->dst
.component_size(inst
->exec_size
);
4457 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4458 !inst
->writes_accumulator
&& !inst
->mlen
);
4460 for (unsigned i
= 0; i
< n
; i
++) {
4461 /* Emit a copy of the original instruction with the lowered width.
4462 * If the EOT flag was set throw it away except for the last
4463 * instruction to avoid killing the thread prematurely.
4465 fs_inst split_inst
= *inst
;
4466 split_inst
.exec_size
= lower_width
;
4467 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4469 /* Select the correct channel enables for the i-th group, then
4470 * transform the sources and destination and emit the lowered
4473 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4475 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4476 if (inst
->src
[j
].file
!= BAD_FILE
&&
4477 !is_uniform(inst
->src
[j
])) {
4478 /* Get the i-th copy_width-wide chunk of the source. */
4479 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4480 const unsigned src_size
= inst
->components_read(j
);
4482 /* Use a trivial transposition to copy one every n
4483 * copy_width-wide components of the register into a
4484 * temporary passed as source to the lowered instruction.
4486 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4487 emit_transpose(lbld
.group(copy_width
, 0),
4488 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4492 if (inst
->regs_written
) {
4493 /* Allocate enough space to hold the result of the lowered
4494 * instruction and fix up the number of registers written.
4496 split_inst
.dst
= dsts
[i
] =
4497 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4498 split_inst
.regs_written
=
4499 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4503 lbld
.emit(split_inst
);
4506 if (inst
->regs_written
) {
4507 /* Distance between useful channels in the temporaries, skipping
4508 * garbage if the lowered instruction is wider than the original.
4510 const unsigned m
= lower_width
/ copy_width
;
4512 /* Interleave the components of the result from the lowered
4513 * instructions. We need to set exec_all() when copying more than
4514 * one half per component, because LOAD_PAYLOAD (in terms of which
4515 * emit_transpose is implemented) can only use the same channel
4516 * enable signals for all of its non-header sources.
4518 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4519 .group(copy_width
, 0),
4520 inst
->dst
, dsts
, n
, dst_size
, m
);
4523 inst
->remove(block
);
4529 invalidate_live_intervals();
4535 fs_visitor::dump_instructions()
4537 dump_instructions(NULL
);
4541 fs_visitor::dump_instructions(const char *name
)
4543 FILE *file
= stderr
;
4544 if (name
&& geteuid() != 0) {
4545 file
= fopen(name
, "w");
4551 calculate_register_pressure();
4552 int ip
= 0, max_pressure
= 0;
4553 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4554 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4555 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4556 dump_instruction(inst
, file
);
4559 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4562 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4563 fprintf(file
, "%4d: ", ip
++);
4564 dump_instruction(inst
, file
);
4568 if (file
!= stderr
) {
4574 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4576 dump_instruction(be_inst
, stderr
);
4580 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4582 fs_inst
*inst
= (fs_inst
*)be_inst
;
4584 if (inst
->predicate
) {
4585 fprintf(file
, "(%cf0.%d) ",
4586 inst
->predicate_inverse
? '-' : '+',
4590 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4592 fprintf(file
, ".sat");
4593 if (inst
->conditional_mod
) {
4594 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4595 if (!inst
->predicate
&&
4596 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4597 inst
->opcode
!= BRW_OPCODE_IF
&&
4598 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4599 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4602 fprintf(file
, "(%d) ", inst
->exec_size
);
4605 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4608 switch (inst
->dst
.file
) {
4610 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
4611 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
4612 inst
->dst
.subreg_offset
)
4613 fprintf(file
, "+%d.%d",
4614 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4617 fprintf(file
, "g%d", inst
->dst
.nr
);
4620 fprintf(file
, "m%d", inst
->dst
.nr
);
4623 fprintf(file
, "(null)");
4626 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4629 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4632 switch (inst
->dst
.nr
) {
4634 fprintf(file
, "null");
4636 case BRW_ARF_ADDRESS
:
4637 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
4639 case BRW_ARF_ACCUMULATOR
:
4640 fprintf(file
, "acc%d", inst
->dst
.subnr
);
4643 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4646 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4649 if (inst
->dst
.subnr
)
4650 fprintf(file
, "+%d", inst
->dst
.subnr
);
4653 unreachable("not reached");
4655 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4657 for (int i
= 0; i
< inst
->sources
; i
++) {
4658 if (inst
->src
[i
].negate
)
4660 if (inst
->src
[i
].abs
)
4662 switch (inst
->src
[i
].file
) {
4664 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
4665 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
4666 inst
->src
[i
].subreg_offset
)
4667 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4668 inst
->src
[i
].subreg_offset
);
4671 fprintf(file
, "g%d", inst
->src
[i
].nr
);
4674 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
4677 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
4680 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
4681 if (inst
->src
[i
].reladdr
) {
4682 fprintf(file
, "+reladdr");
4683 } else if (inst
->src
[i
].subreg_offset
) {
4684 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4685 inst
->src
[i
].subreg_offset
);
4689 fprintf(file
, "(null)");
4692 switch (inst
->src
[i
].type
) {
4693 case BRW_REGISTER_TYPE_F
:
4694 fprintf(file
, "%ff", inst
->src
[i
].f
);
4696 case BRW_REGISTER_TYPE_W
:
4697 case BRW_REGISTER_TYPE_D
:
4698 fprintf(file
, "%dd", inst
->src
[i
].d
);
4700 case BRW_REGISTER_TYPE_UW
:
4701 case BRW_REGISTER_TYPE_UD
:
4702 fprintf(file
, "%uu", inst
->src
[i
].ud
);
4704 case BRW_REGISTER_TYPE_VF
:
4705 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4706 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
4707 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
4708 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
4709 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
4712 fprintf(file
, "???");
4717 switch (inst
->src
[i
].nr
) {
4719 fprintf(file
, "null");
4721 case BRW_ARF_ADDRESS
:
4722 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
4724 case BRW_ARF_ACCUMULATOR
:
4725 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
4728 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4731 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4734 if (inst
->src
[i
].subnr
)
4735 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
4738 if (inst
->src
[i
].abs
)
4741 if (inst
->src
[i
].file
!= IMM
) {
4742 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4745 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4746 fprintf(file
, ", ");
4751 if (inst
->force_writemask_all
)
4752 fprintf(file
, "NoMask ");
4754 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4755 if (inst
->force_sechalf
)
4756 fprintf(file
, "2ndhalf ");
4758 fprintf(file
, "1sthalf ");
4761 fprintf(file
, "\n");
4765 * Possibly returns an instruction that set up @param reg.
4767 * Sometimes we want to take the result of some expression/variable
4768 * dereference tree and rewrite the instruction generating the result
4769 * of the tree. When processing the tree, we know that the
4770 * instructions generated are all writing temporaries that are dead
4771 * outside of this tree. So, if we have some instructions that write
4772 * a temporary, we're free to point that temp write somewhere else.
4774 * Note that this doesn't guarantee that the instruction generated
4775 * only reg -- it might be the size=4 destination of a texture instruction.
4778 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4783 end
->is_partial_write() ||
4785 !reg
.equals(end
->dst
)) {
4793 fs_visitor::setup_payload_gen6()
4796 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
4797 unsigned barycentric_interp_modes
=
4798 (stage
== MESA_SHADER_FRAGMENT
) ?
4799 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4801 assert(devinfo
->gen
>= 6);
4803 /* R0-1: masks, pixel X/Y coordinates. */
4804 payload
.num_regs
= 2;
4805 /* R2: only for 32-pixel dispatch.*/
4807 /* R3-26: barycentric interpolation coordinates. These appear in the
4808 * same order that they appear in the brw_wm_barycentric_interp_mode
4809 * enum. Each set of coordinates occupies 2 registers if dispatch width
4810 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4811 * appear if they were enabled using the "Barycentric Interpolation
4812 * Mode" bits in WM_STATE.
4814 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4815 if (barycentric_interp_modes
& (1 << i
)) {
4816 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4817 payload
.num_regs
+= 2;
4818 if (dispatch_width
== 16) {
4819 payload
.num_regs
+= 2;
4824 /* R27: interpolated depth if uses source depth */
4826 payload
.source_depth_reg
= payload
.num_regs
;
4828 if (dispatch_width
== 16) {
4829 /* R28: interpolated depth if not SIMD8. */
4833 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4835 payload
.source_w_reg
= payload
.num_regs
;
4837 if (dispatch_width
== 16) {
4838 /* R30: interpolated W if not SIMD8. */
4843 if (stage
== MESA_SHADER_FRAGMENT
) {
4844 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4845 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4846 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4847 /* R31: MSAA position offsets. */
4848 if (prog_data
->uses_pos_offset
) {
4849 payload
.sample_pos_reg
= payload
.num_regs
;
4854 /* R32: MSAA input coverage mask */
4855 if (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
4856 assert(devinfo
->gen
>= 7);
4857 payload
.sample_mask_in_reg
= payload
.num_regs
;
4859 if (dispatch_width
== 16) {
4860 /* R33: input coverage mask if not SIMD8. */
4865 /* R34-: bary for 32-pixel. */
4866 /* R58-59: interp W for 32-pixel. */
4868 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4869 source_depth_to_render_target
= true;
4874 fs_visitor::setup_vs_payload()
4876 /* R0: thread header, R1: urb handles */
4877 payload
.num_regs
= 2;
4881 * We are building the local ID push constant data using the simplest possible
4882 * method. We simply push the local IDs directly as they should appear in the
4883 * registers for the uvec3 gl_LocalInvocationID variable.
4885 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
4886 * registers worth of push constant space.
4888 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
4889 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
4892 * FINISHME: There are a few easy optimizations to consider.
4894 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
4895 * no need for using push constant space for that dimension.
4897 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
4898 * easily use 16-bit words rather than 32-bit dwords in the push constant
4901 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
4902 * conveying the data, and thereby reduce push constant usage.
4906 fs_visitor::setup_gs_payload()
4908 assert(stage
== MESA_SHADER_GEOMETRY
);
4910 struct brw_gs_prog_data
*gs_prog_data
=
4911 (struct brw_gs_prog_data
*) prog_data
;
4912 struct brw_vue_prog_data
*vue_prog_data
=
4913 (struct brw_vue_prog_data
*) prog_data
;
4915 /* R0: thread header, R1: output URB handles */
4916 payload
.num_regs
= 2;
4918 if (gs_prog_data
->include_primitive_id
) {
4919 /* R2: Primitive ID 0..7 */
4923 /* Use a maximum of 32 registers for push-model inputs. */
4924 const unsigned max_push_components
= 32;
4926 /* If pushing our inputs would take too many registers, reduce the URB read
4927 * length (which is in HWords, or 8 registers), and resort to pulling.
4929 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
4930 * have to multiply by VerticesIn to obtain the total storage requirement.
4932 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
4933 max_push_components
) {
4934 gs_prog_data
->base
.include_vue_handles
= true;
4936 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
4937 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
4939 vue_prog_data
->urb_read_length
=
4940 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
4945 fs_visitor::setup_cs_payload()
4947 assert(devinfo
->gen
>= 7);
4948 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
4950 payload
.num_regs
= 1;
4952 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
4953 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
4954 payload
.local_invocation_id_reg
= payload
.num_regs
;
4955 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
4960 fs_visitor::calculate_register_pressure()
4962 invalidate_live_intervals();
4963 calculate_live_intervals();
4965 unsigned num_instructions
= 0;
4966 foreach_block(block
, cfg
)
4967 num_instructions
+= block
->instructions
.length();
4969 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
4971 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
4972 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
4973 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
4978 fs_visitor::optimize()
4980 /* Start by validating the shader we currently have. */
4983 /* bld is the common builder object pointing at the end of the program we
4984 * used to translate it into i965 IR. For the optimization and lowering
4985 * passes coming next, any code added after the end of the program without
4986 * having explicitly called fs_builder::at() clearly points at a mistake.
4987 * Ideally optimization passes wouldn't be part of the visitor so they
4988 * wouldn't have access to bld at all, but they do, so just in case some
4989 * pass forgets to ask for a location explicitly set it to NULL here to
4990 * make it trip. The dispatch width is initialized to a bogus value to
4991 * make sure that optimizations set the execution controls explicitly to
4992 * match the code they are manipulating instead of relying on the defaults.
4994 bld
= fs_builder(this, 64);
4996 assign_constant_locations();
4997 demote_pull_constants();
5001 split_virtual_grfs();
5004 #define OPT(pass, args...) ({ \
5006 bool this_progress = pass(args); \
5008 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5009 char filename[64]; \
5010 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5011 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5013 backend_shader::dump_instructions(filename); \
5018 progress = progress || this_progress; \
5022 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5024 snprintf(filename
, 64, "%s%d-%s-00-start",
5025 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5027 backend_shader::dump_instructions(filename
);
5030 bool progress
= false;
5034 OPT(lower_simd_width
);
5035 OPT(lower_logical_sends
);
5042 OPT(remove_duplicate_mrf_writes
);
5046 OPT(opt_copy_propagate
);
5047 OPT(opt_predicated_break
, this);
5048 OPT(opt_cmod_propagation
);
5049 OPT(dead_code_eliminate
);
5050 OPT(opt_peephole_sel
);
5051 OPT(dead_control_flow_eliminate
, this);
5052 OPT(opt_register_renaming
);
5053 OPT(opt_redundant_discard_jumps
);
5054 OPT(opt_saturate_propagation
);
5055 OPT(opt_zero_samples
);
5056 OPT(register_coalesce
);
5057 OPT(compute_to_mrf
);
5058 OPT(eliminate_find_live_channel
);
5060 OPT(compact_virtual_grfs
);
5065 OPT(opt_sampler_eot
);
5067 if (OPT(lower_load_payload
)) {
5068 split_virtual_grfs();
5069 OPT(register_coalesce
);
5070 OPT(compute_to_mrf
);
5071 OPT(dead_code_eliminate
);
5074 OPT(opt_combine_constants
);
5075 OPT(lower_integer_multiplication
);
5077 lower_uniform_pull_constant_loads();
5083 * Three source instruction must have a GRF/MRF destination register.
5084 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5087 fs_visitor::fixup_3src_null_dest()
5089 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5090 if (inst
->is_3src() && inst
->dst
.is_null()) {
5091 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5098 fs_visitor::allocate_registers()
5100 bool allocated_without_spills
;
5102 static const enum instruction_scheduler_mode pre_modes
[] = {
5104 SCHEDULE_PRE_NON_LIFO
,
5108 /* Try each scheduling heuristic to see if it can successfully register
5109 * allocate without spilling. They should be ordered by decreasing
5110 * performance but increasing likelihood of allocating.
5112 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5113 schedule_instructions(pre_modes
[i
]);
5116 assign_regs_trivial();
5117 allocated_without_spills
= true;
5119 allocated_without_spills
= assign_regs(false);
5121 if (allocated_without_spills
)
5125 if (!allocated_without_spills
) {
5126 /* We assume that any spilling is worse than just dropping back to
5127 * SIMD8. There's probably actually some intermediate point where
5128 * SIMD16 with a couple of spills is still better.
5130 if (dispatch_width
== 16) {
5131 fail("Failure to register allocate. Reduce number of "
5132 "live scalar values to avoid this.");
5134 compiler
->shader_perf_log(log_data
,
5135 "%s shader triggered register spilling. "
5136 "Try reducing the number of live scalar "
5137 "values to improve performance.\n",
5141 /* Since we're out of heuristics, just go spill registers until we
5142 * get an allocation.
5144 while (!assign_regs(true)) {
5150 /* This must come after all optimization and register allocation, since
5151 * it inserts dead code that happens to have side effects, and it does
5152 * so based on the actual physical registers in use.
5154 insert_gen4_send_dependency_workarounds();
5159 schedule_instructions(SCHEDULE_POST
);
5161 if (last_scratch
> 0)
5162 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5166 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5168 assert(stage
== MESA_SHADER_VERTEX
);
5172 if (shader_time_index
>= 0)
5173 emit_shader_time_begin();
5180 compute_clip_distance(clip_planes
);
5184 if (shader_time_index
>= 0)
5185 emit_shader_time_end();
5191 assign_curb_setup();
5192 assign_vs_urb_setup();
5194 fixup_3src_null_dest();
5195 allocate_registers();
5201 fs_visitor::run_gs()
5203 assert(stage
== MESA_SHADER_GEOMETRY
);
5207 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
5209 if (gs_compile
->control_data_header_size_bits
> 0) {
5210 /* Create a VGRF to store accumulated control data bits. */
5211 this->control_data_bits
= vgrf(glsl_type::uint_type
);
5213 /* If we're outputting more than 32 control data bits, then EmitVertex()
5214 * will set control_data_bits to 0 after emitting the first vertex.
5215 * Otherwise, we need to initialize it to 0 here.
5217 if (gs_compile
->control_data_header_size_bits
<= 32) {
5218 const fs_builder abld
= bld
.annotate("initialize control data bits");
5219 abld
.MOV(this->control_data_bits
, fs_reg(0u));
5223 if (shader_time_index
>= 0)
5224 emit_shader_time_begin();
5228 emit_gs_thread_end();
5230 if (shader_time_index
>= 0)
5231 emit_shader_time_end();
5240 assign_curb_setup();
5241 assign_gs_urb_setup();
5243 fixup_3src_null_dest();
5244 allocate_registers();
5250 fs_visitor::run_fs(bool do_rep_send
)
5252 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5253 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
5255 assert(stage
== MESA_SHADER_FRAGMENT
);
5257 if (devinfo
->gen
>= 6)
5258 setup_payload_gen6();
5260 setup_payload_gen4();
5264 } else if (do_rep_send
) {
5265 assert(dispatch_width
== 16);
5266 emit_repclear_shader();
5268 if (shader_time_index
>= 0)
5269 emit_shader_time_begin();
5271 calculate_urb_setup();
5272 if (nir
->info
.inputs_read
> 0) {
5273 if (devinfo
->gen
< 6)
5274 emit_interpolation_setup_gen4();
5276 emit_interpolation_setup_gen6();
5279 /* We handle discards by keeping track of the still-live pixels in f0.1.
5280 * Initialize it with the dispatched pixels.
5282 if (wm_prog_data
->uses_kill
) {
5283 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5284 discard_init
->flag_subreg
= 1;
5287 /* Generate FS IR for main(). (the visitor only descends into
5288 * functions called "main").
5295 if (wm_prog_data
->uses_kill
)
5296 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5298 if (wm_key
->alpha_test_func
)
5303 if (shader_time_index
>= 0)
5304 emit_shader_time_end();
5310 assign_curb_setup();
5313 fixup_3src_null_dest();
5314 allocate_registers();
5320 if (dispatch_width
== 8)
5321 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5323 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5329 fs_visitor::run_cs()
5331 assert(stage
== MESA_SHADER_COMPUTE
);
5335 if (shader_time_index
>= 0)
5336 emit_shader_time_begin();
5343 emit_cs_terminate();
5345 if (shader_time_index
>= 0)
5346 emit_shader_time_end();
5352 assign_curb_setup();
5354 fixup_3src_null_dest();
5355 allocate_registers();
5364 * Return a bitfield where bit n is set if barycentric interpolation mode n
5365 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
5368 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
5369 bool shade_model_flat
,
5370 bool persample_shading
,
5371 const nir_shader
*shader
)
5373 unsigned barycentric_interp_modes
= 0;
5375 nir_foreach_variable(var
, &shader
->inputs
) {
5376 enum glsl_interp_qualifier interp_qualifier
=
5377 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5378 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
5379 bool is_sample
= var
->data
.sample
|| persample_shading
;
5380 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5381 (var
->data
.location
== VARYING_SLOT_COL1
);
5383 /* Ignore WPOS and FACE, because they don't require interpolation. */
5384 if (var
->data
.location
== VARYING_SLOT_POS
||
5385 var
->data
.location
== VARYING_SLOT_FACE
)
5388 /* Determine the set (or sets) of barycentric coordinates needed to
5389 * interpolate this variable. Note that when
5390 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
5391 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
5392 * for lit pixels, so we need both sets of barycentric coordinates.
5394 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
5396 barycentric_interp_modes
|=
5397 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
5398 } else if (is_sample
) {
5399 barycentric_interp_modes
|=
5400 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
5402 if ((!is_centroid
&& !is_sample
) ||
5403 devinfo
->needs_unlit_centroid_workaround
) {
5404 barycentric_interp_modes
|=
5405 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
5407 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
5408 (!(shade_model_flat
&& is_gl_Color
) &&
5409 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
5411 barycentric_interp_modes
|=
5412 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
5413 } else if (is_sample
) {
5414 barycentric_interp_modes
|=
5415 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
5417 if ((!is_centroid
&& !is_sample
) ||
5418 devinfo
->needs_unlit_centroid_workaround
) {
5419 barycentric_interp_modes
|=
5420 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
5425 return barycentric_interp_modes
;
5429 computed_depth_mode(const nir_shader
*shader
)
5431 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5432 switch (shader
->info
.fs
.depth_layout
) {
5433 case FRAG_DEPTH_LAYOUT_NONE
:
5434 case FRAG_DEPTH_LAYOUT_ANY
:
5435 return BRW_PSCDEPTH_ON
;
5436 case FRAG_DEPTH_LAYOUT_GREATER
:
5437 return BRW_PSCDEPTH_ON_GE
;
5438 case FRAG_DEPTH_LAYOUT_LESS
:
5439 return BRW_PSCDEPTH_ON_LE
;
5440 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
5441 return BRW_PSCDEPTH_OFF
;
5444 return BRW_PSCDEPTH_OFF
;
5448 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
5450 const struct brw_wm_prog_key
*key
,
5451 struct brw_wm_prog_data
*prog_data
,
5452 const nir_shader
*shader
,
5453 struct gl_program
*prog
,
5454 int shader_time_index8
, int shader_time_index16
,
5456 unsigned *final_assembly_size
,
5459 /* key->alpha_test_func means simulating alpha testing via discards,
5460 * so the shader definitely kills pixels.
5462 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
5463 prog_data
->uses_omask
=
5464 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
5465 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
5466 prog_data
->computed_stencil
=
5467 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
5469 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
5471 prog_data
->barycentric_interp_modes
=
5472 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
5474 key
->persample_shading
,
5477 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
,
5478 &prog_data
->base
, prog
, shader
, 8,
5479 shader_time_index8
);
5480 if (!v
.run_fs(false /* do_rep_send */)) {
5482 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
5487 cfg_t
*simd16_cfg
= NULL
;
5488 fs_visitor
v2(compiler
, log_data
, mem_ctx
, key
,
5489 &prog_data
->base
, prog
, shader
, 16,
5490 shader_time_index16
);
5491 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
5492 if (!v
.simd16_unsupported
) {
5493 /* Try a SIMD16 compile */
5494 v2
.import_uniforms(&v
);
5495 if (!v2
.run_fs(use_rep_send
)) {
5496 compiler
->shader_perf_log(log_data
,
5497 "SIMD16 shader failed to compile: %s",
5500 simd16_cfg
= v2
.cfg
;
5506 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || use_rep_send
;
5507 if ((no_simd8
|| compiler
->devinfo
->gen
< 5) && simd16_cfg
) {
5509 prog_data
->no_8
= true;
5512 prog_data
->no_8
= false;
5515 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
5516 v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
5518 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5519 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
5520 shader
->info
.label
? shader
->info
.label
:
5522 shader
->info
.name
));
5526 g
.generate_code(simd8_cfg
, 8);
5528 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5530 return g
.get_assembly(final_assembly_size
);
5534 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*prog_data
,
5535 void *buffer
, uint32_t threads
, uint32_t stride
)
5537 if (prog_data
->local_invocation_id_regs
== 0)
5540 /* 'stride' should be an integer number of registers, that is, a multiple
5543 assert(stride
% 32 == 0);
5545 unsigned x
= 0, y
= 0, z
= 0;
5546 for (unsigned t
= 0; t
< threads
; t
++) {
5547 uint32_t *param
= (uint32_t *) buffer
+ stride
* t
/ 4;
5549 for (unsigned i
= 0; i
< prog_data
->simd_size
; i
++) {
5550 param
[0 * prog_data
->simd_size
+ i
] = x
;
5551 param
[1 * prog_data
->simd_size
+ i
] = y
;
5552 param
[2 * prog_data
->simd_size
+ i
] = z
;
5555 if (x
== prog_data
->local_size
[0]) {
5558 if (y
== prog_data
->local_size
[1]) {
5561 if (z
== prog_data
->local_size
[2])
5570 fs_visitor::emit_cs_local_invocation_id_setup()
5572 assert(stage
== MESA_SHADER_COMPUTE
);
5574 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5576 struct brw_reg src
=
5577 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
5578 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
5580 src
.nr
+= dispatch_width
/ 8;
5581 bld
.MOV(offset(*reg
, bld
, 1), src
);
5582 src
.nr
+= dispatch_width
/ 8;
5583 bld
.MOV(offset(*reg
, bld
, 2), src
);
5589 fs_visitor::emit_cs_work_group_id_setup()
5591 assert(stage
== MESA_SHADER_COMPUTE
);
5593 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5595 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
5596 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
5597 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
5599 bld
.MOV(*reg
, r0_1
);
5600 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
5601 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
5607 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
5609 const struct brw_cs_prog_key
*key
,
5610 struct brw_cs_prog_data
*prog_data
,
5611 const nir_shader
*shader
,
5612 int shader_time_index
,
5613 unsigned *final_assembly_size
,
5616 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
5617 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
5618 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
5619 unsigned local_workgroup_size
=
5620 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
5621 shader
->info
.cs
.local_size
[2];
5623 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
5626 const char *fail_msg
= NULL
;
5628 /* Now the main event: Visit the shader IR and generate our CS IR for it.
5630 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5631 NULL
, /* Never used in core profile */
5632 shader
, 8, shader_time_index
);
5634 fail_msg
= v8
.fail_msg
;
5635 } else if (local_workgroup_size
<= 8 * max_cs_threads
) {
5637 prog_data
->simd_size
= 8;
5640 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5641 NULL
, /* Never used in core profile */
5642 shader
, 16, shader_time_index
);
5643 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
5644 !fail_msg
&& !v8
.simd16_unsupported
&&
5645 local_workgroup_size
<= 16 * max_cs_threads
) {
5646 /* Try a SIMD16 compile */
5647 v16
.import_uniforms(&v8
);
5648 if (!v16
.run_cs()) {
5649 compiler
->shader_perf_log(log_data
,
5650 "SIMD16 shader failed to compile: %s",
5654 "Couldn't generate SIMD16 program and not "
5655 "enough threads for SIMD8";
5659 prog_data
->simd_size
= 16;
5663 if (unlikely(cfg
== NULL
)) {
5666 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
5671 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
5672 v8
.promoted_constants
, v8
.runtime_check_aads_emit
, "CS");
5673 if (INTEL_DEBUG
& DEBUG_CS
) {
5674 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
5675 shader
->info
.label
? shader
->info
.label
:
5678 g
.enable_debug(name
);
5681 g
.generate_code(cfg
, prog_data
->simd_size
);
5683 return g
.get_assembly(final_assembly_size
);