2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "../glsl/glsl_types.h"
47 #include "../glsl/ir_optimization.h"
48 #include "../glsl/ir_print_visitor.h"
51 ARF
= BRW_ARCHITECTURE_REGISTER_FILE
,
52 GRF
= BRW_GENERAL_REGISTER_FILE
,
53 MRF
= BRW_MESSAGE_REGISTER_FILE
,
54 IMM
= BRW_IMMEDIATE_VALUE
,
55 FIXED_HW_REG
, /* a struct brw_reg */
56 UNIFORM
, /* prog_data->params[hw_reg] */
61 FS_OPCODE_FB_WRITE
= 256,
79 static int using_new_fs
= -1;
80 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
83 brw_new_shader(GLcontext
*ctx
, GLuint name
, GLuint type
)
85 struct brw_shader
*shader
;
87 shader
= talloc_zero(NULL
, struct brw_shader
);
89 shader
->base
.Type
= type
;
90 shader
->base
.Name
= name
;
91 _mesa_init_shader(ctx
, &shader
->base
);
97 struct gl_shader_program
*
98 brw_new_shader_program(GLcontext
*ctx
, GLuint name
)
100 struct brw_shader_program
*prog
;
101 prog
= talloc_zero(NULL
, struct brw_shader_program
);
103 prog
->base
.Name
= name
;
104 _mesa_init_shader_program(ctx
, &prog
->base
);
110 brw_compile_shader(GLcontext
*ctx
, struct gl_shader
*shader
)
112 if (!_mesa_ir_compile_shader(ctx
, shader
))
119 brw_link_shader(GLcontext
*ctx
, struct gl_shader_program
*prog
)
121 if (using_new_fs
== -1)
122 using_new_fs
= getenv("INTEL_NEW_FS") != NULL
;
124 for (unsigned i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
125 struct brw_shader
*shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
127 if (using_new_fs
&& shader
->base
.Type
== GL_FRAGMENT_SHADER
) {
128 void *mem_ctx
= talloc_new(NULL
);
132 talloc_free(shader
->ir
);
133 shader
->ir
= new(shader
) exec_list
;
134 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
136 do_mat_op_to_vec(shader
->ir
);
137 do_mod_to_fract(shader
->ir
);
138 do_div_to_mul_rcp(shader
->ir
);
139 do_sub_to_add_neg(shader
->ir
);
140 do_explog_to_explog2(shader
->ir
);
141 do_lower_texture_projection(shader
->ir
);
146 brw_do_channel_expressions(shader
->ir
);
147 brw_do_vector_splitting(shader
->ir
);
149 progress
= do_lower_jumps(shader
->ir
, true, true,
150 true, /* main return */
151 false, /* continue */
155 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
157 progress
= lower_noise(shader
->ir
) || progress
;
159 lower_variable_index_to_cond_assign(shader
->ir
,
161 GL_TRUE
, /* output */
163 GL_TRUE
/* uniform */
167 validate_ir_tree(shader
->ir
);
169 reparent_ir(shader
->ir
, shader
->ir
);
170 talloc_free(mem_ctx
);
174 if (!_mesa_ir_link_shader(ctx
, prog
))
181 type_size(const struct glsl_type
*type
)
183 unsigned int size
, i
;
185 switch (type
->base_type
) {
188 case GLSL_TYPE_FLOAT
:
190 return type
->components();
191 case GLSL_TYPE_ARRAY
:
192 return type_size(type
->fields
.array
) * type
->length
;
193 case GLSL_TYPE_STRUCT
:
195 for (i
= 0; i
< type
->length
; i
++) {
196 size
+= type_size(type
->fields
.structure
[i
].type
);
199 case GLSL_TYPE_SAMPLER
:
200 /* Samplers take up no register space, since they're baked in at
205 assert(!"not reached");
212 /* Callers of this talloc-based new need not call delete. It's
213 * easier to just talloc_free 'ctx' (or any of its ancestors). */
214 static void* operator new(size_t size
, void *ctx
)
218 node
= talloc_size(ctx
, size
);
219 assert(node
!= NULL
);
227 this->reg_offset
= 0;
233 /** Generic unset register constructor. */
237 this->file
= BAD_FILE
;
240 /** Immediate value constructor. */
245 this->type
= BRW_REGISTER_TYPE_F
;
249 /** Immediate value constructor. */
254 this->type
= BRW_REGISTER_TYPE_D
;
258 /** Immediate value constructor. */
263 this->type
= BRW_REGISTER_TYPE_UD
;
267 /** Fixed brw_reg Immediate value constructor. */
268 fs_reg(struct brw_reg fixed_hw_reg
)
271 this->file
= FIXED_HW_REG
;
272 this->fixed_hw_reg
= fixed_hw_reg
;
273 this->type
= fixed_hw_reg
.type
;
276 fs_reg(enum register_file file
, int hw_reg
);
277 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
279 /** Register file: ARF, GRF, MRF, IMM. */
280 enum register_file file
;
281 /** virtual register number. 0 = fixed hw reg */
283 /** Offset within the virtual register. */
285 /** HW register number. Generally unset until register allocation. */
287 /** Register type. BRW_REGISTER_TYPE_* */
291 struct brw_reg fixed_hw_reg
;
293 /** Value for file == BRW_IMMMEDIATE_FILE */
301 static const fs_reg reg_undef
;
302 static const fs_reg
reg_null(ARF
, BRW_ARF_NULL
);
304 class fs_inst
: public exec_node
{
306 /* Callers of this talloc-based new need not call delete. It's
307 * easier to just talloc_free 'ctx' (or any of its ancestors). */
308 static void* operator new(size_t size
, void *ctx
)
312 node
= talloc_zero_size(ctx
, size
);
313 assert(node
!= NULL
);
320 this->opcode
= BRW_OPCODE_NOP
;
321 this->saturate
= false;
322 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
323 this->predicated
= false;
327 this->header_present
= false;
328 this->shadow_compare
= false;
339 this->opcode
= opcode
;
342 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
)
345 this->opcode
= opcode
;
350 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
353 this->opcode
= opcode
;
359 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg src2
)
362 this->opcode
= opcode
;
369 int opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
374 int conditional_mod
; /**< BRW_CONDITIONAL_* */
376 int mlen
; /**< SEND message length */
378 int target
; /**< MRT target. */
384 * Annotation for the generated IR. One of the two can be set.
387 const char *annotation
;
391 class fs_visitor
: public ir_visitor
395 fs_visitor(struct brw_wm_compile
*c
, struct brw_shader
*shader
)
400 this->fp
= brw
->fragment_program
;
401 this->intel
= &brw
->intel
;
402 this->ctx
= &intel
->ctx
;
403 this->mem_ctx
= talloc_new(NULL
);
404 this->shader
= shader
;
406 this->variable_ht
= hash_table_ctor(0,
407 hash_table_pointer_hash
,
408 hash_table_pointer_compare
);
410 this->frag_color
= NULL
;
411 this->frag_data
= NULL
;
412 this->frag_depth
= NULL
;
413 this->first_non_payload_grf
= 0;
415 this->current_annotation
= NULL
;
416 this->annotation_string
= NULL
;
417 this->annotation_ir
= NULL
;
418 this->base_ir
= NULL
;
420 this->virtual_grf_sizes
= NULL
;
421 this->virtual_grf_next
= 1;
422 this->virtual_grf_array_size
= 0;
423 this->virtual_grf_def
= NULL
;
424 this->virtual_grf_use
= NULL
;
426 this->kill_emitted
= false;
431 talloc_free(this->mem_ctx
);
432 hash_table_dtor(this->variable_ht
);
435 fs_reg
*variable_storage(ir_variable
*var
);
436 int virtual_grf_alloc(int size
);
438 void visit(ir_variable
*ir
);
439 void visit(ir_assignment
*ir
);
440 void visit(ir_dereference_variable
*ir
);
441 void visit(ir_dereference_record
*ir
);
442 void visit(ir_dereference_array
*ir
);
443 void visit(ir_expression
*ir
);
444 void visit(ir_texture
*ir
);
445 void visit(ir_if
*ir
);
446 void visit(ir_constant
*ir
);
447 void visit(ir_swizzle
*ir
);
448 void visit(ir_return
*ir
);
449 void visit(ir_loop
*ir
);
450 void visit(ir_loop_jump
*ir
);
451 void visit(ir_discard
*ir
);
452 void visit(ir_call
*ir
);
453 void visit(ir_function
*ir
);
454 void visit(ir_function_signature
*ir
);
456 fs_inst
*emit(fs_inst inst
);
457 void assign_curb_setup();
458 void calculate_urb_setup();
459 void assign_urb_setup();
461 void assign_regs_trivial();
462 void calculate_live_intervals();
463 bool propagate_constants();
464 bool dead_code_eliminate();
465 bool virtual_grf_interferes(int a
, int b
);
466 void generate_code();
467 void generate_fb_write(fs_inst
*inst
);
468 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
469 struct brw_reg
*src
);
470 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
471 void generate_math(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg
*src
);
472 void generate_discard(fs_inst
*inst
, struct brw_reg temp
);
473 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
474 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
476 void emit_dummy_fs();
477 void emit_fragcoord_interpolation(ir_variable
*ir
);
478 void emit_general_interpolation(ir_variable
*ir
);
479 void emit_interpolation_setup_gen4();
480 void emit_interpolation_setup_gen6();
481 fs_inst
*emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
);
482 fs_inst
*emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
);
483 void emit_fb_writes();
484 void emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
485 const glsl_type
*type
, bool predicated
);
487 struct brw_reg
interp_reg(int location
, int channel
);
488 int setup_uniform_values(int loc
, const glsl_type
*type
);
489 void setup_builtin_uniform_values(ir_variable
*ir
);
491 struct brw_context
*brw
;
492 const struct gl_fragment_program
*fp
;
493 struct intel_context
*intel
;
495 struct brw_wm_compile
*c
;
496 struct brw_compile
*p
;
497 struct brw_shader
*shader
;
499 exec_list instructions
;
501 int *virtual_grf_sizes
;
502 int virtual_grf_next
;
503 int virtual_grf_array_size
;
504 int *virtual_grf_def
;
505 int *virtual_grf_use
;
507 struct hash_table
*variable_ht
;
508 ir_variable
*frag_color
, *frag_data
, *frag_depth
;
509 int first_non_payload_grf
;
510 int urb_setup
[FRAG_ATTRIB_MAX
];
513 /** @{ debug annotation info */
514 const char *current_annotation
;
515 ir_instruction
*base_ir
;
516 const char **annotation_string
;
517 ir_instruction
**annotation_ir
;
522 /* Result of last visit() method. */
537 fs_visitor::virtual_grf_alloc(int size
)
539 if (virtual_grf_array_size
<= virtual_grf_next
) {
540 if (virtual_grf_array_size
== 0)
541 virtual_grf_array_size
= 16;
543 virtual_grf_array_size
*= 2;
544 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
545 int, virtual_grf_array_size
);
547 /* This slot is always unused. */
548 virtual_grf_sizes
[0] = 0;
550 virtual_grf_sizes
[virtual_grf_next
] = size
;
551 return virtual_grf_next
++;
554 /** Fixed HW reg constructor. */
555 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
559 this->hw_reg
= hw_reg
;
560 this->type
= BRW_REGISTER_TYPE_F
;
564 brw_type_for_base_type(const struct glsl_type
*type
)
566 switch (type
->base_type
) {
567 case GLSL_TYPE_FLOAT
:
568 return BRW_REGISTER_TYPE_F
;
571 return BRW_REGISTER_TYPE_D
;
573 return BRW_REGISTER_TYPE_UD
;
574 case GLSL_TYPE_ARRAY
:
575 case GLSL_TYPE_STRUCT
:
576 /* These should be overridden with the type of the member when
577 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
578 * way to trip up if we don't.
580 return BRW_REGISTER_TYPE_UD
;
582 assert(!"not reached");
583 return BRW_REGISTER_TYPE_F
;
587 /** Automatic reg constructor. */
588 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
593 this->reg
= v
->virtual_grf_alloc(type_size(type
));
594 this->reg_offset
= 0;
595 this->type
= brw_type_for_base_type(type
);
599 fs_visitor::variable_storage(ir_variable
*var
)
601 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
604 /* Our support for uniforms is piggy-backed on the struct
605 * gl_fragment_program, because that's where the values actually
606 * get stored, rather than in some global gl_shader_program uniform
610 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
612 unsigned int offset
= 0;
615 if (type
->is_matrix()) {
616 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
617 type
->vector_elements
,
620 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
621 offset
+= setup_uniform_values(loc
+ offset
, column
);
627 switch (type
->base_type
) {
628 case GLSL_TYPE_FLOAT
:
632 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
633 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
634 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
638 case GLSL_TYPE_STRUCT
:
639 for (unsigned int i
= 0; i
< type
->length
; i
++) {
640 offset
+= setup_uniform_values(loc
+ offset
,
641 type
->fields
.structure
[i
].type
);
645 case GLSL_TYPE_ARRAY
:
646 for (unsigned int i
= 0; i
< type
->length
; i
++) {
647 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
651 case GLSL_TYPE_SAMPLER
:
652 /* The sampler takes up a slot, but we don't use any values from it. */
656 assert(!"not reached");
662 /* Our support for builtin uniforms is even scarier than non-builtin.
663 * It sits on top of the PROG_STATE_VAR parameters that are
664 * automatically updated from GL context state.
667 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
669 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
671 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
672 statevar
= &_mesa_builtin_uniform_desc
[i
];
673 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
677 if (!statevar
->name
) {
679 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
684 if (ir
->type
->is_array()) {
685 array_count
= ir
->type
->length
;
690 for (int a
= 0; a
< array_count
; a
++) {
691 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
692 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
693 int tokens
[STATE_LENGTH
];
695 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
696 if (ir
->type
->is_array()) {
700 /* This state reference has already been setup by ir_to_mesa,
701 * but we'll get the same index back here.
703 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
704 (gl_state_index
*)tokens
);
705 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
707 /* Add each of the unique swizzles of the element as a
708 * parameter. This'll end up matching the expected layout of
709 * the array/matrix/structure we're trying to fill in.
712 for (unsigned int i
= 0; i
< 4; i
++) {
713 int swiz
= GET_SWZ(element
->swizzle
, i
);
714 if (swiz
== last_swiz
)
718 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
725 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
727 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
729 fs_reg neg_y
= this->pixel_y
;
733 if (ir
->pixel_center_integer
) {
734 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
736 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
741 if (ir
->origin_upper_left
&& ir
->pixel_center_integer
) {
742 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
744 fs_reg pixel_y
= this->pixel_y
;
745 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
747 if (!ir
->origin_upper_left
) {
748 pixel_y
.negate
= true;
749 offset
+= c
->key
.drawable_height
- 1.0;
752 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
757 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
758 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
761 /* gl_FragCoord.w: Already set up in emit_interpolation */
762 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
764 hash_table_insert(this->variable_ht
, reg
, ir
);
769 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
771 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
772 /* Interpolation is always in floating point regs. */
773 reg
->type
= BRW_REGISTER_TYPE_F
;
776 unsigned int array_elements
;
777 const glsl_type
*type
;
779 if (ir
->type
->is_array()) {
780 array_elements
= ir
->type
->length
;
781 if (array_elements
== 0) {
784 type
= ir
->type
->fields
.array
;
790 int location
= ir
->location
;
791 for (unsigned int i
= 0; i
< array_elements
; i
++) {
792 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
793 if (urb_setup
[location
] == -1) {
794 /* If there's no incoming setup data for this slot, don't
795 * emit interpolation for it.
797 attr
.reg_offset
+= type
->vector_elements
;
802 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
803 struct brw_reg interp
= interp_reg(location
, c
);
804 emit(fs_inst(FS_OPCODE_LINTERP
,
811 attr
.reg_offset
-= type
->vector_elements
;
813 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
814 emit(fs_inst(BRW_OPCODE_MUL
,
824 hash_table_insert(this->variable_ht
, reg
, ir
);
828 fs_visitor::visit(ir_variable
*ir
)
832 if (variable_storage(ir
))
835 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
836 this->frag_color
= ir
;
837 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
838 this->frag_data
= ir
;
839 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
840 this->frag_depth
= ir
;
843 if (ir
->mode
== ir_var_in
) {
844 if (!strcmp(ir
->name
, "gl_FragCoord")) {
845 emit_fragcoord_interpolation(ir
);
847 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
848 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
849 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
850 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
853 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
857 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
858 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
860 emit_general_interpolation(ir
);
865 if (ir
->mode
== ir_var_uniform
) {
866 int param_index
= c
->prog_data
.nr_params
;
868 if (!strncmp(ir
->name
, "gl_", 3)) {
869 setup_builtin_uniform_values(ir
);
871 setup_uniform_values(ir
->location
, ir
->type
);
874 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
878 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
880 hash_table_insert(this->variable_ht
, reg
, ir
);
884 fs_visitor::visit(ir_dereference_variable
*ir
)
886 fs_reg
*reg
= variable_storage(ir
->var
);
891 fs_visitor::visit(ir_dereference_record
*ir
)
893 const glsl_type
*struct_type
= ir
->record
->type
;
895 ir
->record
->accept(this);
897 unsigned int offset
= 0;
898 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
899 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
901 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
903 this->result
.reg_offset
+= offset
;
904 this->result
.type
= brw_type_for_base_type(ir
->type
);
908 fs_visitor::visit(ir_dereference_array
*ir
)
913 ir
->array
->accept(this);
914 index
= ir
->array_index
->as_constant();
916 element_size
= type_size(ir
->type
);
917 this->result
.type
= brw_type_for_base_type(ir
->type
);
920 assert(this->result
.file
== UNIFORM
||
921 (this->result
.file
== GRF
&&
922 this->result
.reg
!= 0));
923 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
925 assert(!"FINISHME: non-constant array element");
930 fs_visitor::visit(ir_expression
*ir
)
932 unsigned int operand
;
937 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
938 ir
->operands
[operand
]->accept(this);
939 if (this->result
.file
== BAD_FILE
) {
941 printf("Failed to get tree for expression operand:\n");
942 ir
->operands
[operand
]->accept(&v
);
945 op
[operand
] = this->result
;
947 /* Matrix expression operands should have been broken down to vector
948 * operations already.
950 assert(!ir
->operands
[operand
]->type
->is_matrix());
951 /* And then those vector operands should have been broken down to scalar.
953 assert(!ir
->operands
[operand
]->type
->is_vector());
956 /* Storage for our result. If our result goes into an assignment, it will
957 * just get copy-propagated out, so no worries.
959 this->result
= fs_reg(this, ir
->type
);
961 switch (ir
->operation
) {
962 case ir_unop_logic_not
:
963 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], fs_reg(-1)));
966 op
[0].negate
= !op
[0].negate
;
967 this->result
= op
[0];
971 this->result
= op
[0];
974 temp
= fs_reg(this, ir
->type
);
976 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
978 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
979 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
980 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
981 inst
->predicated
= true;
983 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
984 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
985 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
986 inst
->predicated
= true;
990 emit(fs_inst(FS_OPCODE_RCP
, this->result
, op
[0]));
994 emit(fs_inst(FS_OPCODE_EXP2
, this->result
, op
[0]));
997 emit(fs_inst(FS_OPCODE_LOG2
, this->result
, op
[0]));
1001 assert(!"not reached: should be handled by ir_explog_to_explog2");
1004 emit(fs_inst(FS_OPCODE_SIN
, this->result
, op
[0]));
1007 emit(fs_inst(FS_OPCODE_COS
, this->result
, op
[0]));
1011 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
1014 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
1018 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
1021 assert(!"not reached: should be handled by ir_sub_to_add_neg");
1025 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
1028 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1031 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1035 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1036 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1037 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1039 case ir_binop_greater
:
1040 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1041 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1042 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1044 case ir_binop_lequal
:
1045 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1046 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1047 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1049 case ir_binop_gequal
:
1050 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1051 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1052 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1054 case ir_binop_equal
:
1055 case ir_binop_all_equal
: /* same as nequal for scalars */
1056 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1057 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1058 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1060 case ir_binop_nequal
:
1061 case ir_binop_any_nequal
: /* same as nequal for scalars */
1062 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1063 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1064 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1067 case ir_binop_logic_xor
:
1068 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
1071 case ir_binop_logic_or
:
1072 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
1075 case ir_binop_logic_and
:
1076 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
1080 case ir_binop_cross
:
1082 assert(!"not reached: should be handled by brw_fs_channel_expressions");
1086 assert(!"not reached: should be handled by lower_noise");
1090 emit(fs_inst(FS_OPCODE_SQRT
, this->result
, op
[0]));
1094 emit(fs_inst(FS_OPCODE_RSQ
, this->result
, op
[0]));
1100 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1103 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1107 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
1108 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1111 emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1114 op
[0].negate
= ~op
[0].negate
;
1115 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1116 this->result
.negate
= true;
1119 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1122 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
1126 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1127 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1129 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1130 inst
->predicated
= true;
1133 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1134 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1136 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1137 inst
->predicated
= true;
1141 inst
= emit(fs_inst(FS_OPCODE_POW
, this->result
, op
[0], op
[1]));
1144 case ir_unop_bit_not
:
1146 case ir_binop_lshift
:
1147 case ir_binop_rshift
:
1148 case ir_binop_bit_and
:
1149 case ir_binop_bit_xor
:
1150 case ir_binop_bit_or
:
1151 assert(!"GLSL 1.30 features unsupported");
1157 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1158 const glsl_type
*type
, bool predicated
)
1160 switch (type
->base_type
) {
1161 case GLSL_TYPE_FLOAT
:
1162 case GLSL_TYPE_UINT
:
1164 case GLSL_TYPE_BOOL
:
1165 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1166 l
.type
= brw_type_for_base_type(type
);
1167 r
.type
= brw_type_for_base_type(type
);
1169 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1170 inst
->predicated
= predicated
;
1176 case GLSL_TYPE_ARRAY
:
1177 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1178 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1181 case GLSL_TYPE_STRUCT
:
1182 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1183 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1188 case GLSL_TYPE_SAMPLER
:
1192 assert(!"not reached");
1198 fs_visitor::visit(ir_assignment
*ir
)
1203 /* FINISHME: arrays on the lhs */
1204 ir
->lhs
->accept(this);
1207 ir
->rhs
->accept(this);
1210 assert(l
.file
!= BAD_FILE
);
1211 assert(r
.file
!= BAD_FILE
);
1213 if (ir
->condition
) {
1214 /* Get the condition bool into the predicate. */
1215 ir
->condition
->accept(this);
1216 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, this->result
, fs_reg(0)));
1217 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1220 if (ir
->lhs
->type
->is_scalar() ||
1221 ir
->lhs
->type
->is_vector()) {
1222 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1223 if (ir
->write_mask
& (1 << i
)) {
1224 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1226 inst
->predicated
= true;
1232 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1237 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1241 bool simd16
= false;
1244 if (ir
->shadow_comparitor
) {
1245 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1246 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1248 coordinate
.reg_offset
++;
1250 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1253 if (ir
->op
== ir_tex
) {
1254 /* There's no plain shadow compare message, so we use shadow
1255 * compare with a bias of 0.0.
1257 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1260 } else if (ir
->op
== ir_txb
) {
1261 ir
->lod_info
.bias
->accept(this);
1262 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1266 assert(ir
->op
== ir_txl
);
1267 ir
->lod_info
.lod
->accept(this);
1268 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1273 ir
->shadow_comparitor
->accept(this);
1274 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1276 } else if (ir
->op
== ir_tex
) {
1277 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1278 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1280 coordinate
.reg_offset
++;
1282 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1285 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1286 * instructions. We'll need to do SIMD16 here.
1288 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1290 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
* 2;) {
1291 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1293 coordinate
.reg_offset
++;
1296 /* The unused upper half. */
1300 /* lod/bias appears after u/v/r. */
1303 if (ir
->op
== ir_txb
) {
1304 ir
->lod_info
.bias
->accept(this);
1305 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1309 ir
->lod_info
.lod
->accept(this);
1310 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1315 /* The unused upper half. */
1318 /* Now, since we're doing simd16, the return is 2 interleaved
1319 * vec4s where the odd-indexed ones are junk. We'll need to move
1320 * this weirdness around to the expected layout.
1324 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1326 dst
.type
= BRW_REGISTER_TYPE_F
;
1329 fs_inst
*inst
= NULL
;
1332 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
1335 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
, fs_reg(MRF
, base_mrf
)));
1338 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
, fs_reg(MRF
, base_mrf
)));
1342 assert(!"GLSL 1.30 features unsupported");
1348 for (int i
= 0; i
< 4; i
++) {
1349 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1350 orig_dst
.reg_offset
++;
1351 dst
.reg_offset
+= 2;
1359 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1361 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1362 * optional parameters like shadow comparitor or LOD bias. If
1363 * optional parameters aren't present, those base slots are
1364 * optional and don't need to be included in the message.
1366 * We don't fill in the unnecessary slots regardless, which may
1367 * look surprising in the disassembly.
1372 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1373 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1374 coordinate
.reg_offset
++;
1377 if (ir
->shadow_comparitor
) {
1378 mlen
= MAX2(mlen
, 4);
1380 ir
->shadow_comparitor
->accept(this);
1381 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1385 fs_inst
*inst
= NULL
;
1388 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
1391 ir
->lod_info
.bias
->accept(this);
1392 mlen
= MAX2(mlen
, 4);
1393 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1396 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
, fs_reg(MRF
, base_mrf
)));
1399 ir
->lod_info
.lod
->accept(this);
1400 mlen
= MAX2(mlen
, 4);
1401 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1404 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
, fs_reg(MRF
, base_mrf
)));
1408 assert(!"GLSL 1.30 features unsupported");
1417 fs_visitor::visit(ir_texture
*ir
)
1419 fs_inst
*inst
= NULL
;
1421 ir
->coordinate
->accept(this);
1422 fs_reg coordinate
= this->result
;
1424 /* Should be lowered by do_lower_texture_projection */
1425 assert(!ir
->projector
);
1427 /* Writemasking doesn't eliminate channels on SIMD8 texture
1428 * samples, so don't worry about them.
1430 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1432 if (intel
->gen
< 5) {
1433 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1435 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1439 _mesa_get_sampler_uniform_value(ir
->sampler
,
1440 ctx
->Shader
.CurrentProgram
,
1441 &brw
->fragment_program
->Base
);
1442 inst
->sampler
= c
->fp
->program
.Base
.SamplerUnits
[inst
->sampler
];
1446 if (ir
->shadow_comparitor
)
1447 inst
->shadow_compare
= true;
1449 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1450 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1452 for (int i
= 0; i
< 4; i
++) {
1453 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1454 fs_reg l
= swizzle_dst
;
1457 if (swiz
== SWIZZLE_ZERO
) {
1458 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1459 } else if (swiz
== SWIZZLE_ONE
) {
1460 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1463 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1464 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1467 this->result
= swizzle_dst
;
1472 fs_visitor::visit(ir_swizzle
*ir
)
1474 ir
->val
->accept(this);
1475 fs_reg val
= this->result
;
1477 if (ir
->type
->vector_elements
== 1) {
1478 this->result
.reg_offset
+= ir
->mask
.x
;
1482 fs_reg result
= fs_reg(this, ir
->type
);
1483 this->result
= result
;
1485 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1486 fs_reg channel
= val
;
1504 channel
.reg_offset
+= swiz
;
1505 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1506 result
.reg_offset
++;
1511 fs_visitor::visit(ir_discard
*ir
)
1513 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1515 assert(ir
->condition
== NULL
); /* FINISHME */
1517 emit(fs_inst(FS_OPCODE_DISCARD
, temp
, temp
));
1518 kill_emitted
= true;
1522 fs_visitor::visit(ir_constant
*ir
)
1524 fs_reg
reg(this, ir
->type
);
1527 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1528 switch (ir
->type
->base_type
) {
1529 case GLSL_TYPE_FLOAT
:
1530 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
1532 case GLSL_TYPE_UINT
:
1533 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1536 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1538 case GLSL_TYPE_BOOL
:
1539 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1542 assert(!"Non-float/uint/int/bool constant");
1549 fs_visitor::visit(ir_if
*ir
)
1553 /* Don't point the annotation at the if statement, because then it plus
1554 * the then and else blocks get printed.
1556 this->base_ir
= ir
->condition
;
1558 /* Generate the condition into the condition code. */
1559 ir
->condition
->accept(this);
1560 inst
= emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(brw_null_reg()), this->result
));
1561 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1563 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1564 inst
->predicated
= true;
1566 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1567 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1573 if (!ir
->else_instructions
.is_empty()) {
1574 emit(fs_inst(BRW_OPCODE_ELSE
));
1576 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1577 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1584 emit(fs_inst(BRW_OPCODE_ENDIF
));
1588 fs_visitor::visit(ir_loop
*ir
)
1590 fs_reg counter
= reg_undef
;
1593 this->base_ir
= ir
->counter
;
1594 ir
->counter
->accept(this);
1595 counter
= *(variable_storage(ir
->counter
));
1598 this->base_ir
= ir
->from
;
1599 ir
->from
->accept(this);
1601 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1605 emit(fs_inst(BRW_OPCODE_DO
));
1608 this->base_ir
= ir
->to
;
1609 ir
->to
->accept(this);
1611 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
,
1612 counter
, this->result
));
1614 case ir_binop_equal
:
1615 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1617 case ir_binop_nequal
:
1618 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1620 case ir_binop_gequal
:
1621 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1623 case ir_binop_lequal
:
1624 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1626 case ir_binop_greater
:
1627 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1630 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1633 assert(!"not reached: unknown loop condition");
1638 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1639 inst
->predicated
= true;
1642 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1643 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1649 if (ir
->increment
) {
1650 this->base_ir
= ir
->increment
;
1651 ir
->increment
->accept(this);
1652 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1655 emit(fs_inst(BRW_OPCODE_WHILE
));
1659 fs_visitor::visit(ir_loop_jump
*ir
)
1662 case ir_loop_jump::jump_break
:
1663 emit(fs_inst(BRW_OPCODE_BREAK
));
1665 case ir_loop_jump::jump_continue
:
1666 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1672 fs_visitor::visit(ir_call
*ir
)
1674 assert(!"FINISHME");
1678 fs_visitor::visit(ir_return
*ir
)
1680 assert(!"FINISHME");
1684 fs_visitor::visit(ir_function
*ir
)
1686 /* Ignore function bodies other than main() -- we shouldn't see calls to
1687 * them since they should all be inlined before we get to ir_to_mesa.
1689 if (strcmp(ir
->name
, "main") == 0) {
1690 const ir_function_signature
*sig
;
1693 sig
= ir
->matching_signature(&empty
);
1697 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1698 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1707 fs_visitor::visit(ir_function_signature
*ir
)
1709 assert(!"not reached");
1714 fs_visitor::emit(fs_inst inst
)
1716 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1719 list_inst
->annotation
= this->current_annotation
;
1720 list_inst
->ir
= this->base_ir
;
1722 this->instructions
.push_tail(list_inst
);
1727 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1729 fs_visitor::emit_dummy_fs()
1731 /* Everyone's favorite color. */
1732 emit(fs_inst(BRW_OPCODE_MOV
,
1735 emit(fs_inst(BRW_OPCODE_MOV
,
1738 emit(fs_inst(BRW_OPCODE_MOV
,
1741 emit(fs_inst(BRW_OPCODE_MOV
,
1746 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1751 /* The register location here is relative to the start of the URB
1752 * data. It will get adjusted to be a real location before
1753 * generate_code() time.
1756 fs_visitor::interp_reg(int location
, int channel
)
1758 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1759 int stride
= (channel
& 1) * 4;
1761 assert(urb_setup
[location
] != -1);
1763 return brw_vec1_grf(regnr
, stride
);
1766 /** Emits the interpolation for the varying inputs. */
1768 fs_visitor::emit_interpolation_setup_gen4()
1770 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1772 this->current_annotation
= "compute pixel centers";
1773 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1774 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1775 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1776 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1777 emit(fs_inst(BRW_OPCODE_ADD
,
1779 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1780 fs_reg(brw_imm_v(0x10101010))));
1781 emit(fs_inst(BRW_OPCODE_ADD
,
1783 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1784 fs_reg(brw_imm_v(0x11001100))));
1786 this->current_annotation
= "compute pixel deltas from v0";
1788 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1789 this->delta_y
= this->delta_x
;
1790 this->delta_y
.reg_offset
++;
1792 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1793 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1795 emit(fs_inst(BRW_OPCODE_ADD
,
1798 fs_reg(negate(brw_vec1_grf(1, 0)))));
1799 emit(fs_inst(BRW_OPCODE_ADD
,
1802 fs_reg(negate(brw_vec1_grf(1, 1)))));
1804 this->current_annotation
= "compute pos.w and 1/pos.w";
1805 /* Compute wpos.w. It's always in our setup, since it's needed to
1806 * interpolate the other attributes.
1808 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1809 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1810 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1811 /* Compute the pixel 1/W value from wpos.w. */
1812 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1813 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
));
1814 this->current_annotation
= NULL
;
1817 /** Emits the interpolation for the varying inputs. */
1819 fs_visitor::emit_interpolation_setup_gen6()
1821 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1823 /* If the pixel centers end up used, the setup is the same as for gen4. */
1824 this->current_annotation
= "compute pixel centers";
1825 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1826 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1827 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1828 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1829 emit(fs_inst(BRW_OPCODE_ADD
,
1831 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1832 fs_reg(brw_imm_v(0x10101010))));
1833 emit(fs_inst(BRW_OPCODE_ADD
,
1835 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1836 fs_reg(brw_imm_v(0x11001100))));
1838 this->current_annotation
= "compute 1/pos.w";
1839 this->wpos_w
= fs_reg(brw_vec8_grf(c
->key
.source_w_reg
, 0));
1840 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1841 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
));
1843 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1844 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1846 this->current_annotation
= NULL
;
1850 fs_visitor::emit_fb_writes()
1852 this->current_annotation
= "FB write header";
1853 GLboolean header_present
= GL_TRUE
;
1856 if (intel
->gen
>= 6 &&
1857 !this->kill_emitted
&&
1858 c
->key
.nr_color_regions
== 1) {
1859 header_present
= false;
1862 if (header_present
) {
1867 if (c
->key
.aa_dest_stencil_reg
) {
1868 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1869 fs_reg(brw_vec8_grf(c
->key
.aa_dest_stencil_reg
, 0))));
1872 /* Reserve space for color. It'll be filled in per MRT below. */
1876 if (c
->key
.source_depth_to_render_target
) {
1877 if (c
->key
.computes_depth
) {
1878 /* Hand over gl_FragDepth. */
1879 assert(this->frag_depth
);
1880 fs_reg depth
= *(variable_storage(this->frag_depth
));
1882 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
1884 /* Pass through the payload depth. */
1885 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1886 fs_reg(brw_vec8_grf(c
->key
.source_depth_reg
, 0))));
1890 if (c
->key
.dest_depth_reg
) {
1891 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1892 fs_reg(brw_vec8_grf(c
->key
.dest_depth_reg
, 0))));
1895 fs_reg color
= reg_undef
;
1896 if (this->frag_color
)
1897 color
= *(variable_storage(this->frag_color
));
1898 else if (this->frag_data
)
1899 color
= *(variable_storage(this->frag_data
));
1901 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1902 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1903 "FB write target %d",
1905 if (this->frag_color
|| this->frag_data
) {
1906 for (int i
= 0; i
< 4; i
++) {
1907 emit(fs_inst(BRW_OPCODE_MOV
,
1908 fs_reg(MRF
, color_mrf
+ i
),
1914 if (this->frag_color
)
1915 color
.reg_offset
-= 4;
1917 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1918 reg_undef
, reg_undef
));
1919 inst
->target
= target
;
1921 if (target
== c
->key
.nr_color_regions
- 1)
1923 inst
->header_present
= header_present
;
1926 if (c
->key
.nr_color_regions
== 0) {
1927 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1928 reg_undef
, reg_undef
));
1931 inst
->header_present
= header_present
;
1934 this->current_annotation
= NULL
;
1938 fs_visitor::generate_fb_write(fs_inst
*inst
)
1940 GLboolean eot
= inst
->eot
;
1941 struct brw_reg implied_header
;
1943 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1946 brw_push_insn_state(p
);
1947 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1948 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1950 if (inst
->header_present
) {
1951 if (intel
->gen
>= 6) {
1954 brw_vec8_grf(0, 0));
1955 implied_header
= brw_null_reg();
1957 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1962 brw_vec8_grf(1, 0));
1964 implied_header
= brw_null_reg();
1967 brw_pop_insn_state(p
);
1970 8, /* dispatch_width */
1971 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
1981 fs_visitor::generate_linterp(fs_inst
*inst
,
1982 struct brw_reg dst
, struct brw_reg
*src
)
1984 struct brw_reg delta_x
= src
[0];
1985 struct brw_reg delta_y
= src
[1];
1986 struct brw_reg interp
= src
[2];
1989 delta_y
.nr
== delta_x
.nr
+ 1 &&
1990 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
1991 brw_PLN(p
, dst
, interp
, delta_x
);
1993 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
1994 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
1999 fs_visitor::generate_math(fs_inst
*inst
,
2000 struct brw_reg dst
, struct brw_reg
*src
)
2004 switch (inst
->opcode
) {
2006 op
= BRW_MATH_FUNCTION_INV
;
2009 op
= BRW_MATH_FUNCTION_RSQ
;
2011 case FS_OPCODE_SQRT
:
2012 op
= BRW_MATH_FUNCTION_SQRT
;
2014 case FS_OPCODE_EXP2
:
2015 op
= BRW_MATH_FUNCTION_EXP
;
2017 case FS_OPCODE_LOG2
:
2018 op
= BRW_MATH_FUNCTION_LOG
;
2021 op
= BRW_MATH_FUNCTION_POW
;
2024 op
= BRW_MATH_FUNCTION_SIN
;
2027 op
= BRW_MATH_FUNCTION_COS
;
2030 assert(!"not reached: unknown math function");
2035 if (inst
->opcode
== FS_OPCODE_POW
) {
2036 brw_MOV(p
, brw_message_reg(3), src
[1]);
2041 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2042 BRW_MATH_SATURATE_NONE
,
2044 BRW_MATH_DATA_VECTOR
,
2045 BRW_MATH_PRECISION_FULL
);
2049 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2053 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2055 if (intel
->gen
== 5) {
2056 switch (inst
->opcode
) {
2058 if (inst
->shadow_compare
) {
2059 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
2061 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
2065 if (inst
->shadow_compare
) {
2066 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
2068 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
2073 switch (inst
->opcode
) {
2075 /* Note that G45 and older determines shadow compare and dispatch width
2076 * from message length for most messages.
2078 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2079 if (inst
->shadow_compare
) {
2080 assert(inst
->mlen
== 5);
2082 assert(inst
->mlen
<= 6);
2086 if (inst
->shadow_compare
) {
2087 assert(inst
->mlen
== 5);
2088 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2090 assert(inst
->mlen
== 8);
2091 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2092 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2097 assert(msg_type
!= -1);
2099 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2108 retype(dst
, BRW_REGISTER_TYPE_UW
),
2110 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2111 SURF_INDEX_TEXTURE(inst
->sampler
),
2123 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2126 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2128 * and we're trying to produce:
2131 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2132 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2133 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2134 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2135 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2136 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2137 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2138 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2140 * and add another set of two more subspans if in 16-pixel dispatch mode.
2142 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2143 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2144 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2145 * between each other. We could probably do it like ddx and swizzle the right
2146 * order later, but bail for now and just produce
2147 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2150 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2152 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2153 BRW_REGISTER_TYPE_F
,
2154 BRW_VERTICAL_STRIDE_2
,
2156 BRW_HORIZONTAL_STRIDE_0
,
2157 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2158 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2159 BRW_REGISTER_TYPE_F
,
2160 BRW_VERTICAL_STRIDE_2
,
2162 BRW_HORIZONTAL_STRIDE_0
,
2163 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2164 brw_ADD(p
, dst
, src0
, negate(src1
));
2168 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2170 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2171 BRW_REGISTER_TYPE_F
,
2172 BRW_VERTICAL_STRIDE_4
,
2174 BRW_HORIZONTAL_STRIDE_0
,
2175 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2176 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2177 BRW_REGISTER_TYPE_F
,
2178 BRW_VERTICAL_STRIDE_4
,
2180 BRW_HORIZONTAL_STRIDE_0
,
2181 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2182 brw_ADD(p
, dst
, src0
, negate(src1
));
2186 fs_visitor::generate_discard(fs_inst
*inst
, struct brw_reg temp
)
2188 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2189 temp
= brw_uw1_reg(temp
.file
, temp
.nr
, 0);
2191 brw_push_insn_state(p
);
2192 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2193 brw_NOT(p
, temp
, brw_mask_reg(1)); /* IMASK */
2194 brw_AND(p
, g0
, temp
, g0
);
2195 brw_pop_insn_state(p
);
2199 fs_visitor::assign_curb_setup()
2201 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
2202 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2204 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2205 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2206 fs_inst
*inst
= (fs_inst
*)iter
.get();
2208 for (unsigned int i
= 0; i
< 3; i
++) {
2209 if (inst
->src
[i
].file
== UNIFORM
) {
2210 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2211 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2215 inst
->src
[i
].file
= FIXED_HW_REG
;
2216 inst
->src
[i
].fixed_hw_reg
= brw_reg
;
2223 fs_visitor::calculate_urb_setup()
2225 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2230 /* Figure out where each of the incoming setup attributes lands. */
2231 if (intel
->gen
>= 6) {
2232 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2233 if (i
== FRAG_ATTRIB_WPOS
||
2234 (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
))) {
2235 urb_setup
[i
] = urb_next
++;
2239 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2240 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2241 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2244 if (i
>= VERT_RESULT_VAR0
)
2245 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2246 else if (i
<= VERT_RESULT_TEX7
)
2252 urb_setup
[fp_index
] = urb_next
++;
2257 /* Each attribute is 4 setup channels, each of which is half a reg. */
2258 c
->prog_data
.urb_read_length
= urb_next
* 2;
2262 fs_visitor::assign_urb_setup()
2264 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2266 /* Offset all the urb_setup[] index by the actual position of the
2267 * setup regs, now that the location of the constants has been chosen.
2269 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2270 fs_inst
*inst
= (fs_inst
*)iter
.get();
2272 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
2275 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2277 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2280 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2284 assign_reg(int *reg_hw_locations
, fs_reg
*reg
)
2286 if (reg
->file
== GRF
&& reg
->reg
!= 0) {
2287 reg
->hw_reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
;
2293 fs_visitor::assign_regs_trivial()
2296 int hw_reg_mapping
[this->virtual_grf_next
];
2299 hw_reg_mapping
[0] = 0;
2300 hw_reg_mapping
[1] = this->first_non_payload_grf
;
2301 for (i
= 2; i
< this->virtual_grf_next
; i
++) {
2302 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
2303 this->virtual_grf_sizes
[i
- 1]);
2305 last_grf
= hw_reg_mapping
[i
- 1] + this->virtual_grf_sizes
[i
- 1];
2307 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2308 fs_inst
*inst
= (fs_inst
*)iter
.get();
2310 assign_reg(hw_reg_mapping
, &inst
->dst
);
2311 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2312 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2315 this->grf_used
= last_grf
+ 1;
2319 fs_visitor::assign_regs()
2322 int hw_reg_mapping
[this->virtual_grf_next
+ 1];
2323 int base_reg_count
= BRW_MAX_GRF
- this->first_non_payload_grf
;
2324 int class_sizes
[base_reg_count
];
2325 int class_count
= 0;
2326 int aligned_pair_class
= -1;
2328 /* Set up the register classes.
2330 * The base registers store a scalar value. For texture samples,
2331 * we get virtual GRFs composed of 4 contiguous hw register. For
2332 * structures and arrays, we store them as contiguous larger things
2333 * than that, though we should be able to do better most of the
2336 class_sizes
[class_count
++] = 1;
2337 if (brw
->has_pln
&& intel
->gen
< 6) {
2338 /* Always set up the (unaligned) pairs for gen5, so we can find
2339 * them for making the aligned pair class.
2341 class_sizes
[class_count
++] = 2;
2343 for (int r
= 1; r
< this->virtual_grf_next
; r
++) {
2346 for (i
= 0; i
< class_count
; i
++) {
2347 if (class_sizes
[i
] == this->virtual_grf_sizes
[r
])
2350 if (i
== class_count
) {
2351 if (this->virtual_grf_sizes
[r
] >= base_reg_count
) {
2352 fprintf(stderr
, "Object too large to register allocate.\n");
2356 class_sizes
[class_count
++] = this->virtual_grf_sizes
[r
];
2360 int ra_reg_count
= 0;
2361 int class_base_reg
[class_count
];
2362 int class_reg_count
[class_count
];
2363 int classes
[class_count
+ 1];
2365 for (int i
= 0; i
< class_count
; i
++) {
2366 class_base_reg
[i
] = ra_reg_count
;
2367 class_reg_count
[i
] = base_reg_count
- (class_sizes
[i
] - 1);
2368 ra_reg_count
+= class_reg_count
[i
];
2371 struct ra_regs
*regs
= ra_alloc_reg_set(ra_reg_count
);
2372 for (int i
= 0; i
< class_count
; i
++) {
2373 classes
[i
] = ra_alloc_reg_class(regs
);
2375 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2376 ra_class_add_reg(regs
, classes
[i
], class_base_reg
[i
] + i_r
);
2379 /* Add conflicts between our contiguous registers aliasing
2380 * base regs and other register classes' contiguous registers
2381 * that alias base regs, or the base regs themselves for classes[0].
2383 for (int c
= 0; c
<= i
; c
++) {
2384 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2385 for (int c_r
= MAX2(0, i_r
- (class_sizes
[c
] - 1));
2386 c_r
< MIN2(class_reg_count
[c
], i_r
+ class_sizes
[i
]);
2390 printf("%d/%d conflicts %d/%d\n",
2391 class_sizes
[i
], this->first_non_payload_grf
+ i_r
,
2392 class_sizes
[c
], this->first_non_payload_grf
+ c_r
);
2395 ra_add_reg_conflict(regs
,
2396 class_base_reg
[i
] + i_r
,
2397 class_base_reg
[c
] + c_r
);
2403 /* Add a special class for aligned pairs, which we'll put delta_x/y
2404 * in on gen5 so that we can do PLN.
2406 if (brw
->has_pln
&& intel
->gen
< 6) {
2407 int reg_count
= (base_reg_count
- 1) / 2;
2408 int unaligned_pair_class
= 1;
2409 assert(class_sizes
[unaligned_pair_class
] == 2);
2411 aligned_pair_class
= class_count
;
2412 classes
[aligned_pair_class
] = ra_alloc_reg_class(regs
);
2413 class_base_reg
[aligned_pair_class
] = 0;
2414 class_reg_count
[aligned_pair_class
] = 0;
2415 int start
= (this->first_non_payload_grf
& 1) ? 1 : 0;
2417 for (int i
= 0; i
< reg_count
; i
++) {
2418 ra_class_add_reg(regs
, classes
[aligned_pair_class
],
2419 class_base_reg
[unaligned_pair_class
] + i
* 2 + start
);
2424 ra_set_finalize(regs
);
2426 struct ra_graph
*g
= ra_alloc_interference_graph(regs
,
2427 this->virtual_grf_next
);
2428 /* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1
2431 ra_set_node_class(g
, 0, classes
[0]);
2433 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2434 for (int c
= 0; c
< class_count
; c
++) {
2435 if (class_sizes
[c
] == this->virtual_grf_sizes
[i
]) {
2436 if (aligned_pair_class
>= 0 &&
2437 this->delta_x
.reg
== i
) {
2438 ra_set_node_class(g
, i
, classes
[aligned_pair_class
]);
2440 ra_set_node_class(g
, i
, classes
[c
]);
2446 for (int j
= 1; j
< i
; j
++) {
2447 if (virtual_grf_interferes(i
, j
)) {
2448 ra_add_node_interference(g
, i
, j
);
2453 /* FINISHME: Handle spilling */
2454 if (!ra_allocate_no_spills(g
)) {
2455 fprintf(stderr
, "Failed to allocate registers.\n");
2460 /* Get the chosen virtual registers for each node, and map virtual
2461 * regs in the register classes back down to real hardware reg
2464 hw_reg_mapping
[0] = 0; /* unused */
2465 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2466 int reg
= ra_get_node_reg(g
, i
);
2469 for (int c
= 0; c
< class_count
; c
++) {
2470 if (reg
>= class_base_reg
[c
] &&
2471 reg
< class_base_reg
[c
] + class_reg_count
[c
]) {
2472 hw_reg
= reg
- class_base_reg
[c
];
2477 assert(hw_reg
!= -1);
2478 hw_reg_mapping
[i
] = this->first_non_payload_grf
+ hw_reg
;
2479 last_grf
= MAX2(last_grf
,
2480 hw_reg_mapping
[i
] + this->virtual_grf_sizes
[i
] - 1);
2483 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2484 fs_inst
*inst
= (fs_inst
*)iter
.get();
2486 assign_reg(hw_reg_mapping
, &inst
->dst
);
2487 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2488 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2491 this->grf_used
= last_grf
+ 1;
2498 fs_visitor::calculate_live_intervals()
2500 int num_vars
= this->virtual_grf_next
;
2501 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2502 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2506 for (int i
= 0; i
< num_vars
; i
++) {
2512 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2513 fs_inst
*inst
= (fs_inst
*)iter
.get();
2515 if (inst
->opcode
== BRW_OPCODE_DO
) {
2516 if (loop_depth
++ == 0)
2518 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2521 if (loop_depth
== 0) {
2524 * Patches up any vars marked for use within the loop as
2525 * live until the end. This is conservative, as there
2526 * will often be variables defined and used inside the
2527 * loop but dead at the end of the loop body.
2529 for (int i
= 0; i
< num_vars
; i
++) {
2530 if (use
[i
] == loop_start
) {
2541 for (unsigned int i
= 0; i
< 3; i
++) {
2542 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2543 use
[inst
->src
[i
].reg
] = MAX2(use
[inst
->src
[i
].reg
], eip
);
2546 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2547 def
[inst
->dst
.reg
] = MIN2(def
[inst
->dst
.reg
], eip
);
2554 talloc_free(this->virtual_grf_def
);
2555 talloc_free(this->virtual_grf_use
);
2556 this->virtual_grf_def
= def
;
2557 this->virtual_grf_use
= use
;
2561 * Attempts to move immediate constants into the immediate
2562 * constant slot of following instructions.
2564 * Immediate constants are a bit tricky -- they have to be in the last
2565 * operand slot, you can't do abs/negate on them,
2569 fs_visitor::propagate_constants()
2571 bool progress
= false;
2573 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2574 fs_inst
*inst
= (fs_inst
*)iter
.get();
2576 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2578 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2579 inst
->dst
.type
!= inst
->src
[0].type
)
2582 /* Don't bother with cases where we should have had the
2583 * operation on the constant folded in GLSL already.
2588 /* Found a move of a constant to a GRF. Find anything else using the GRF
2589 * before it's written, and replace it with the constant if we can.
2591 exec_list_iterator scan_iter
= iter
;
2593 for (; scan_iter
.has_next(); scan_iter
.next()) {
2594 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2596 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2597 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2598 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2599 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2603 for (int i
= 2; i
>= 0; i
--) {
2604 if (scan_inst
->src
[i
].file
!= GRF
||
2605 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2606 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2609 /* Don't bother with cases where we should have had the
2610 * operation on the constant folded in GLSL already.
2612 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2615 switch (scan_inst
->opcode
) {
2616 case BRW_OPCODE_MOV
:
2617 scan_inst
->src
[i
] = inst
->src
[0];
2621 case BRW_OPCODE_MUL
:
2622 case BRW_OPCODE_ADD
:
2624 scan_inst
->src
[i
] = inst
->src
[0];
2626 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2627 /* Fit this constant in by commuting the operands */
2628 scan_inst
->src
[0] = scan_inst
->src
[1];
2629 scan_inst
->src
[1] = inst
->src
[0];
2632 case BRW_OPCODE_CMP
:
2634 scan_inst
->src
[i
] = inst
->src
[0];
2640 if (scan_inst
->dst
.file
== GRF
&&
2641 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2642 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2643 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2652 * Must be called after calculate_live_intervales() to remove unused
2653 * writes to registers -- register allocation will fail otherwise
2654 * because something deffed but not used won't be considered to
2655 * interfere with other regs.
2658 fs_visitor::dead_code_eliminate()
2660 bool progress
= false;
2661 int num_vars
= this->virtual_grf_next
;
2662 bool dead
[num_vars
];
2664 for (int i
= 0; i
< num_vars
; i
++) {
2665 /* This would be ">=", but FS_OPCODE_DISCARD has a src == dst where
2666 * it writes dst then reads it as src.
2668 dead
[i
] = this->virtual_grf_def
[i
] > this->virtual_grf_use
[i
];
2671 /* Mark off its interval so it won't interfere with anything. */
2672 this->virtual_grf_def
[i
] = -1;
2673 this->virtual_grf_use
[i
] = -1;
2677 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2678 fs_inst
*inst
= (fs_inst
*)iter
.get();
2680 if (inst
->dst
.file
== GRF
&& dead
[inst
->dst
.reg
]) {
2690 fs_visitor::virtual_grf_interferes(int a
, int b
)
2692 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
2693 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
2695 /* For dead code, just check if the def interferes with the other range. */
2696 if (this->virtual_grf_use
[a
] == -1) {
2697 return (this->virtual_grf_def
[a
] >= this->virtual_grf_def
[b
] &&
2698 this->virtual_grf_def
[a
] < this->virtual_grf_use
[b
]);
2700 if (this->virtual_grf_use
[b
] == -1) {
2701 return (this->virtual_grf_def
[b
] >= this->virtual_grf_def
[a
] &&
2702 this->virtual_grf_def
[b
] < this->virtual_grf_use
[a
]);
2705 return start
<= end
;
2708 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
2710 struct brw_reg brw_reg
;
2712 switch (reg
->file
) {
2716 brw_reg
= brw_vec8_reg(reg
->file
,
2718 brw_reg
= retype(brw_reg
, reg
->type
);
2721 switch (reg
->type
) {
2722 case BRW_REGISTER_TYPE_F
:
2723 brw_reg
= brw_imm_f(reg
->imm
.f
);
2725 case BRW_REGISTER_TYPE_D
:
2726 brw_reg
= brw_imm_d(reg
->imm
.i
);
2728 case BRW_REGISTER_TYPE_UD
:
2729 brw_reg
= brw_imm_ud(reg
->imm
.u
);
2732 assert(!"not reached");
2737 brw_reg
= reg
->fixed_hw_reg
;
2740 /* Probably unused. */
2741 brw_reg
= brw_null_reg();
2744 assert(!"not reached");
2745 brw_reg
= brw_null_reg();
2749 brw_reg
= brw_abs(brw_reg
);
2751 brw_reg
= negate(brw_reg
);
2757 fs_visitor::generate_code()
2759 unsigned int annotation_len
= 0;
2760 int last_native_inst
= 0;
2761 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
2762 int if_stack_depth
= 0, loop_stack_depth
= 0;
2763 int if_depth_in_loop
[16];
2765 if_depth_in_loop
[loop_stack_depth
] = 0;
2767 memset(&if_stack
, 0, sizeof(if_stack
));
2768 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2769 fs_inst
*inst
= (fs_inst
*)iter
.get();
2770 struct brw_reg src
[3], dst
;
2772 for (unsigned int i
= 0; i
< 3; i
++) {
2773 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
2775 dst
= brw_reg_from_fs_reg(&inst
->dst
);
2777 brw_set_conditionalmod(p
, inst
->conditional_mod
);
2778 brw_set_predicate_control(p
, inst
->predicated
);
2780 switch (inst
->opcode
) {
2781 case BRW_OPCODE_MOV
:
2782 brw_MOV(p
, dst
, src
[0]);
2784 case BRW_OPCODE_ADD
:
2785 brw_ADD(p
, dst
, src
[0], src
[1]);
2787 case BRW_OPCODE_MUL
:
2788 brw_MUL(p
, dst
, src
[0], src
[1]);
2791 case BRW_OPCODE_FRC
:
2792 brw_FRC(p
, dst
, src
[0]);
2794 case BRW_OPCODE_RNDD
:
2795 brw_RNDD(p
, dst
, src
[0]);
2797 case BRW_OPCODE_RNDZ
:
2798 brw_RNDZ(p
, dst
, src
[0]);
2801 case BRW_OPCODE_AND
:
2802 brw_AND(p
, dst
, src
[0], src
[1]);
2805 brw_OR(p
, dst
, src
[0], src
[1]);
2807 case BRW_OPCODE_XOR
:
2808 brw_XOR(p
, dst
, src
[0], src
[1]);
2811 case BRW_OPCODE_CMP
:
2812 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
2814 case BRW_OPCODE_SEL
:
2815 brw_SEL(p
, dst
, src
[0], src
[1]);
2819 assert(if_stack_depth
< 16);
2820 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
2821 if_depth_in_loop
[loop_stack_depth
]++;
2824 case BRW_OPCODE_ELSE
:
2825 if_stack
[if_stack_depth
- 1] =
2826 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
2828 case BRW_OPCODE_ENDIF
:
2830 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
2831 if_depth_in_loop
[loop_stack_depth
]--;
2835 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
2836 if_depth_in_loop
[loop_stack_depth
] = 0;
2839 case BRW_OPCODE_BREAK
:
2840 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
2841 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2843 case BRW_OPCODE_CONTINUE
:
2844 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
2845 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2848 case BRW_OPCODE_WHILE
: {
2849 struct brw_instruction
*inst0
, *inst1
;
2852 if (intel
->gen
>= 5)
2855 assert(loop_stack_depth
> 0);
2857 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
2858 /* patch all the BREAK/CONT instructions from last BGNLOOP */
2859 while (inst0
> loop_stack
[loop_stack_depth
]) {
2861 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
2862 inst0
->bits3
.if_else
.jump_count
== 0) {
2863 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
2865 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
2866 inst0
->bits3
.if_else
.jump_count
== 0) {
2867 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
2875 case FS_OPCODE_SQRT
:
2876 case FS_OPCODE_EXP2
:
2877 case FS_OPCODE_LOG2
:
2881 generate_math(inst
, dst
, src
);
2883 case FS_OPCODE_LINTERP
:
2884 generate_linterp(inst
, dst
, src
);
2889 generate_tex(inst
, dst
, src
[0]);
2891 case FS_OPCODE_DISCARD
:
2892 generate_discard(inst
, dst
/* src0 == dst */);
2895 generate_ddx(inst
, dst
, src
[0]);
2898 generate_ddy(inst
, dst
, src
[0]);
2900 case FS_OPCODE_FB_WRITE
:
2901 generate_fb_write(inst
);
2904 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
2905 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
2906 brw_opcodes
[inst
->opcode
].name
);
2908 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
2913 if (annotation_len
< p
->nr_insn
) {
2914 annotation_len
*= 2;
2915 if (annotation_len
< 16)
2916 annotation_len
= 16;
2918 this->annotation_string
= talloc_realloc(this->mem_ctx
,
2922 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
2928 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
2929 this->annotation_string
[i
] = inst
->annotation
;
2930 this->annotation_ir
[i
] = inst
->ir
;
2932 last_native_inst
= p
->nr_insn
;
2937 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
2939 struct brw_compile
*p
= &c
->func
;
2940 struct intel_context
*intel
= &brw
->intel
;
2941 GLcontext
*ctx
= &intel
->ctx
;
2942 struct brw_shader
*shader
= NULL
;
2943 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
2951 for (unsigned int i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
2952 if (prog
->_LinkedShaders
[i
]->Type
== GL_FRAGMENT_SHADER
) {
2953 shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
2960 /* We always use 8-wide mode, at least for now. For one, flow
2961 * control only works in 8-wide. Also, when we're fragment shader
2962 * bound, we're almost always under register pressure as well, so
2963 * 8-wide would save us from the performance cliff of spilling
2966 c
->dispatch_width
= 8;
2968 if (INTEL_DEBUG
& DEBUG_WM
) {
2969 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
2970 _mesa_print_ir(shader
->ir
, NULL
);
2974 /* Now the main event: Visit the shader IR and generate our FS IR for it.
2976 fs_visitor
v(c
, shader
);
2981 v
.calculate_urb_setup();
2983 v
.emit_interpolation_setup_gen4();
2985 v
.emit_interpolation_setup_gen6();
2987 /* Generate FS IR for main(). (the visitor only descends into
2988 * functions called "main").
2990 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
2991 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
2997 v
.assign_curb_setup();
2998 v
.assign_urb_setup();
3004 v
.calculate_live_intervals();
3005 progress
= v
.propagate_constants() || progress
;
3006 progress
= v
.dead_code_eliminate() || progress
;
3010 v
.assign_regs_trivial();
3018 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3023 if (INTEL_DEBUG
& DEBUG_WM
) {
3024 const char *last_annotation_string
= NULL
;
3025 ir_instruction
*last_annotation_ir
= NULL
;
3027 printf("Native code for fragment shader %d:\n", prog
->Name
);
3028 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
3029 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
3030 last_annotation_ir
= v
.annotation_ir
[i
];
3031 if (last_annotation_ir
) {
3033 last_annotation_ir
->print();
3037 if (last_annotation_string
!= v
.annotation_string
[i
]) {
3038 last_annotation_string
= v
.annotation_string
[i
];
3039 if (last_annotation_string
)
3040 printf(" %s\n", last_annotation_string
);
3042 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3047 c
->prog_data
.total_grf
= v
.grf_used
;
3048 c
->prog_data
.total_scratch
= 0;