2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
47 #include "brw_dead_control_flow.h"
48 #include "main/uniforms.h"
49 #include "brw_fs_live_variables.h"
50 #include "glsl/glsl_types.h"
51 #include "program/sampler.h"
56 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
57 const fs_reg
*src
, unsigned sources
)
59 memset(this, 0, sizeof(*this));
61 this->src
= new fs_reg
[MAX2(sources
, 3)];
62 for (unsigned i
= 0; i
< sources
; i
++)
63 this->src
[i
] = src
[i
];
65 this->opcode
= opcode
;
67 this->sources
= sources
;
68 this->exec_size
= exec_size
;
70 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
72 assert(this->exec_size
!= 0);
74 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
76 /* This will be the case for almost all instructions. */
82 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
86 this->regs_written
= 0;
90 unreachable("Invalid destination register file");
92 unreachable("Invalid register file");
95 this->writes_accumulator
= false;
100 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
103 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
105 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
108 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
110 init(opcode
, exec_size
, dst
, NULL
, 0);
113 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
116 const fs_reg src
[1] = { src0
};
117 init(opcode
, exec_size
, dst
, src
, 1);
120 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
121 const fs_reg
&src0
, const fs_reg
&src1
)
123 const fs_reg src
[2] = { src0
, src1
};
124 init(opcode
, exec_size
, dst
, src
, 2);
127 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
128 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
130 const fs_reg src
[3] = { src0
, src1
, src2
};
131 init(opcode
, exec_size
, dst
, src
, 3);
134 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
135 const fs_reg src
[], unsigned sources
)
137 init(opcode
, exec_width
, dst
, src
, sources
);
140 fs_inst::fs_inst(const fs_inst
&that
)
142 memcpy(this, &that
, sizeof(that
));
144 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
146 for (unsigned i
= 0; i
< that
.sources
; i
++)
147 this->src
[i
] = that
.src
[i
];
156 fs_inst::resize_sources(uint8_t num_sources
)
158 if (this->sources
!= num_sources
) {
159 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
161 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
162 src
[i
] = this->src
[i
];
166 this->sources
= num_sources
;
171 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
173 const fs_reg
&surf_index
,
174 const fs_reg
&varying_offset
,
175 uint32_t const_offset
)
177 /* We have our constant surface use a pitch of 4 bytes, so our index can
178 * be any component of a vector, and then we load 4 contiguous
179 * components starting from that.
181 * We break down the const_offset to a portion added to the variable
182 * offset and a portion done using reg_offset, which means that if you
183 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
184 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
185 * CSE can later notice that those loads are all the same and eliminate
186 * the redundant ones.
188 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
189 bld
.ADD(vec4_offset
, varying_offset
, fs_reg(const_offset
& ~3));
192 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
193 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
194 * u, v, r) as parameters, or we can just use the SIMD16 message
195 * consisting of (header, u). We choose the second, at the cost of a
196 * longer return length.
202 if (devinfo
->gen
>= 7)
203 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
205 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
207 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
208 fs_reg vec4_result
= fs_reg(GRF
, alloc
.allocate(regs_written
), dst
.type
);
209 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
210 inst
->regs_written
= regs_written
;
212 if (devinfo
->gen
< 7) {
214 inst
->header_size
= 1;
215 if (devinfo
->gen
== 4)
218 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
221 bld
.MOV(dst
, offset(vec4_result
, bld
, (const_offset
& 3) * scale
));
225 * A helper for MOV generation for fixing up broken hardware SEND dependency
229 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
231 /* The caller always wants uncompressed to emit the minimal extra
232 * dependencies, and to avoid having to deal with aligning its regs to 2.
234 const fs_builder ubld
= bld
.annotate("send dependency resolve")
237 ubld
.MOV(ubld
.null_reg_f(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
241 fs_inst::equals(fs_inst
*inst
) const
243 return (opcode
== inst
->opcode
&&
244 dst
.equals(inst
->dst
) &&
245 src
[0].equals(inst
->src
[0]) &&
246 src
[1].equals(inst
->src
[1]) &&
247 src
[2].equals(inst
->src
[2]) &&
248 saturate
== inst
->saturate
&&
249 predicate
== inst
->predicate
&&
250 conditional_mod
== inst
->conditional_mod
&&
251 mlen
== inst
->mlen
&&
252 base_mrf
== inst
->base_mrf
&&
253 target
== inst
->target
&&
255 header_size
== inst
->header_size
&&
256 shadow_compare
== inst
->shadow_compare
&&
257 exec_size
== inst
->exec_size
&&
258 offset
== inst
->offset
);
262 fs_inst::overwrites_reg(const fs_reg
®
) const
264 return reg
.in_range(dst
, regs_written
);
268 fs_inst::is_send_from_grf() const
271 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
272 case SHADER_OPCODE_SHADER_TIME_ADD
:
273 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
274 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
275 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
276 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
277 case SHADER_OPCODE_UNTYPED_ATOMIC
:
278 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
279 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
280 case SHADER_OPCODE_TYPED_ATOMIC
:
281 case SHADER_OPCODE_TYPED_SURFACE_READ
:
282 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
283 case SHADER_OPCODE_URB_WRITE_SIMD8
:
285 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
286 return src
[1].file
== GRF
;
287 case FS_OPCODE_FB_WRITE
:
288 return src
[0].file
== GRF
;
291 return src
[0].file
== GRF
;
298 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
300 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
303 fs_reg reg
= this->src
[0];
304 if (reg
.file
!= GRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
307 if (grf_alloc
.sizes
[reg
.reg
] != this->regs_written
)
310 for (int i
= 0; i
< this->sources
; i
++) {
311 reg
.type
= this->src
[i
].type
;
312 if (!this->src
[i
].equals(reg
))
315 if (i
< this->header_size
) {
318 reg
.reg_offset
+= this->exec_size
/ 8;
326 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
328 if (devinfo
->gen
== 6 && is_math())
331 if (is_send_from_grf())
334 if (!backend_instruction::can_do_source_mods())
341 fs_inst::has_side_effects() const
343 return this->eot
|| backend_instruction::has_side_effects();
349 memset(this, 0, sizeof(*this));
353 /** Generic unset register constructor. */
357 this->file
= BAD_FILE
;
360 /** Immediate value constructor. */
361 fs_reg::fs_reg(float f
)
365 this->type
= BRW_REGISTER_TYPE_F
;
367 this->fixed_hw_reg
.dw1
.f
= f
;
370 /** Immediate value constructor. */
371 fs_reg::fs_reg(int32_t i
)
375 this->type
= BRW_REGISTER_TYPE_D
;
377 this->fixed_hw_reg
.dw1
.d
= i
;
380 /** Immediate value constructor. */
381 fs_reg::fs_reg(uint32_t u
)
385 this->type
= BRW_REGISTER_TYPE_UD
;
387 this->fixed_hw_reg
.dw1
.ud
= u
;
390 /** Vector float immediate value constructor. */
391 fs_reg::fs_reg(uint8_t vf
[4])
395 this->type
= BRW_REGISTER_TYPE_VF
;
396 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
399 /** Vector float immediate value constructor. */
400 fs_reg::fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
404 this->type
= BRW_REGISTER_TYPE_VF
;
405 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
411 /** Fixed brw_reg. */
412 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
416 this->fixed_hw_reg
= fixed_hw_reg
;
417 this->type
= fixed_hw_reg
.type
;
421 fs_reg::equals(const fs_reg
&r
) const
423 return (file
== r
.file
&&
425 reg_offset
== r
.reg_offset
&&
426 subreg_offset
== r
.subreg_offset
&&
428 negate
== r
.negate
&&
430 !reladdr
&& !r
.reladdr
&&
431 ((file
!= HW_REG
&& file
!= IMM
) ||
432 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
433 sizeof(fixed_hw_reg
)) == 0) &&
438 fs_reg::set_smear(unsigned subreg
)
440 assert(file
!= HW_REG
&& file
!= IMM
);
441 subreg_offset
= subreg
* type_sz(type
);
447 fs_reg::is_contiguous() const
453 fs_reg::component_size(unsigned width
) const
455 const unsigned stride
= (file
!= HW_REG
? this->stride
:
456 fixed_hw_reg
.hstride
== 0 ? 0 :
457 1 << (fixed_hw_reg
.hstride
- 1));
458 return MAX2(width
* stride
, 1) * type_sz(type
);
462 type_size_scalar(const struct glsl_type
*type
)
464 unsigned int size
, i
;
466 switch (type
->base_type
) {
469 case GLSL_TYPE_FLOAT
:
471 return type
->components();
472 case GLSL_TYPE_ARRAY
:
473 return type_size_scalar(type
->fields
.array
) * type
->length
;
474 case GLSL_TYPE_STRUCT
:
476 for (i
= 0; i
< type
->length
; i
++) {
477 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
480 case GLSL_TYPE_SAMPLER
:
481 /* Samplers take up no register space, since they're baked in at
485 case GLSL_TYPE_ATOMIC_UINT
:
487 case GLSL_TYPE_SUBROUTINE
:
489 case GLSL_TYPE_IMAGE
:
490 return BRW_IMAGE_PARAM_SIZE
;
492 case GLSL_TYPE_ERROR
:
493 case GLSL_TYPE_INTERFACE
:
494 case GLSL_TYPE_DOUBLE
:
495 unreachable("not reached");
502 * Create a MOV to read the timestamp register.
504 * The caller is responsible for emitting the MOV. The return value is
505 * the destination of the MOV, with extra parameters set.
508 fs_visitor::get_timestamp(const fs_builder
&bld
)
510 assert(devinfo
->gen
>= 7);
512 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
515 BRW_REGISTER_TYPE_UD
));
517 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
519 /* We want to read the 3 fields we care about even if it's not enabled in
522 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
524 /* The caller wants the low 32 bits of the timestamp. Since it's running
525 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
526 * which is plenty of time for our purposes. It is identical across the
527 * EUs, but since it's tracking GPU core speed it will increment at a
528 * varying rate as render P-states change.
530 * The caller could also check if render P-states have changed (or anything
531 * else that might disrupt timing) by setting smear to 2 and checking if
532 * that field is != 0.
540 fs_visitor::emit_shader_time_begin()
542 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
546 fs_visitor::emit_shader_time_end()
548 /* Insert our code just before the final SEND with EOT. */
549 exec_node
*end
= this->instructions
.get_tail();
550 assert(end
&& ((fs_inst
*) end
)->eot
);
551 const fs_builder ibld
= bld
.annotate("shader time end")
552 .exec_all().at(NULL
, end
);
554 fs_reg shader_end_time
= get_timestamp(ibld
);
556 /* Check that there weren't any timestamp reset events (assuming these
557 * were the only two timestamp reads that happened).
559 fs_reg reset
= shader_end_time
;
561 set_condmod(BRW_CONDITIONAL_Z
,
562 ibld
.AND(ibld
.null_reg_ud(), reset
, fs_reg(1u)));
563 ibld
.IF(BRW_PREDICATE_NORMAL
);
565 fs_reg start
= shader_start_time
;
567 fs_reg diff
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
570 const fs_builder cbld
= ibld
.group(1, 0);
571 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
573 /* If there were no instructions between the two timestamp gets, the diff
574 * is 2 cycles. Remove that overhead, so I can forget about that when
575 * trying to determine the time taken for single instructions.
577 cbld
.ADD(diff
, diff
, fs_reg(-2u));
578 SHADER_TIME_ADD(cbld
, 0, diff
);
579 SHADER_TIME_ADD(cbld
, 1, fs_reg(1u));
580 ibld
.emit(BRW_OPCODE_ELSE
);
581 SHADER_TIME_ADD(cbld
, 2, fs_reg(1u));
582 ibld
.emit(BRW_OPCODE_ENDIF
);
586 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
587 int shader_time_subindex
,
590 int index
= shader_time_index
* 3 + shader_time_subindex
;
591 fs_reg offset
= fs_reg(index
* SHADER_TIME_STRIDE
);
594 if (dispatch_width
== 8)
595 payload
= vgrf(glsl_type::uvec2_type
);
597 payload
= vgrf(glsl_type::uint_type
);
599 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
603 fs_visitor::vfail(const char *format
, va_list va
)
612 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
613 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
615 this->fail_msg
= msg
;
618 fprintf(stderr
, "%s", msg
);
623 fs_visitor::fail(const char *format
, ...)
627 va_start(va
, format
);
633 * Mark this program as impossible to compile in SIMD16 mode.
635 * During the SIMD8 compile (which happens first), we can detect and flag
636 * things that are unsupported in SIMD16 mode, so the compiler can skip
637 * the SIMD16 compile altogether.
639 * During a SIMD16 compile (if one happens anyway), this just calls fail().
642 fs_visitor::no16(const char *msg
)
644 if (dispatch_width
== 16) {
647 simd16_unsupported
= true;
649 compiler
->shader_perf_log(log_data
,
650 "SIMD16 shader failed to compile: %s", msg
);
655 * Returns true if the instruction has a flag that means it won't
656 * update an entire destination register.
658 * For example, dead code elimination and live variable analysis want to know
659 * when a write to a variable screens off any preceding values that were in
663 fs_inst::is_partial_write() const
665 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
666 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
667 !this->dst
.is_contiguous());
671 fs_inst::components_read(unsigned i
) const
674 case FS_OPCODE_LINTERP
:
680 case FS_OPCODE_PIXEL_X
:
681 case FS_OPCODE_PIXEL_Y
:
685 case FS_OPCODE_FB_WRITE_LOGICAL
:
686 assert(src
[6].file
== IMM
);
687 /* First/second FB write color. */
689 return src
[6].fixed_hw_reg
.dw1
.ud
;
693 case SHADER_OPCODE_TEX_LOGICAL
:
694 case SHADER_OPCODE_TXD_LOGICAL
:
695 case SHADER_OPCODE_TXF_LOGICAL
:
696 case SHADER_OPCODE_TXL_LOGICAL
:
697 case SHADER_OPCODE_TXS_LOGICAL
:
698 case FS_OPCODE_TXB_LOGICAL
:
699 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
700 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
701 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
702 case SHADER_OPCODE_LOD_LOGICAL
:
703 case SHADER_OPCODE_TG4_LOGICAL
:
704 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
705 assert(src
[8].file
== IMM
&& src
[9].file
== IMM
);
706 /* Texture coordinates. */
708 return src
[8].fixed_hw_reg
.dw1
.ud
;
709 /* Texture derivatives. */
710 else if ((i
== 2 || i
== 3) && opcode
== SHADER_OPCODE_TXD_LOGICAL
)
711 return src
[9].fixed_hw_reg
.dw1
.ud
;
712 /* Texture offset. */
718 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
719 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
720 assert(src
[3].file
== IMM
);
721 /* Surface coordinates. */
723 return src
[3].fixed_hw_reg
.dw1
.ud
;
724 /* Surface operation source (ignored for reads). */
730 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
731 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
732 assert(src
[3].file
== IMM
&&
734 /* Surface coordinates. */
736 return src
[3].fixed_hw_reg
.dw1
.ud
;
737 /* Surface operation source. */
739 return src
[4].fixed_hw_reg
.dw1
.ud
;
743 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
744 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
745 assert(src
[3].file
== IMM
&&
747 const unsigned op
= src
[4].fixed_hw_reg
.dw1
.ud
;
748 /* Surface coordinates. */
750 return src
[3].fixed_hw_reg
.dw1
.ud
;
751 /* Surface operation source. */
752 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
754 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
755 op
== BRW_AOP_PREDEC
))
767 fs_inst::regs_read(int arg
) const
770 case FS_OPCODE_FB_WRITE
:
771 case SHADER_OPCODE_URB_WRITE_SIMD8
:
772 case SHADER_OPCODE_UNTYPED_ATOMIC
:
773 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
774 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
775 case SHADER_OPCODE_TYPED_ATOMIC
:
776 case SHADER_OPCODE_TYPED_SURFACE_READ
:
777 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
778 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
783 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
784 /* The payload is actually stored in src1 */
789 case FS_OPCODE_LINTERP
:
794 case SHADER_OPCODE_LOAD_PAYLOAD
:
795 if (arg
< this->header_size
)
799 case CS_OPCODE_CS_TERMINATE
:
800 case SHADER_OPCODE_BARRIER
:
804 if (is_tex() && arg
== 0 && src
[0].file
== GRF
)
809 switch (src
[arg
].file
) {
818 return DIV_ROUND_UP(components_read(arg
) *
819 src
[arg
].component_size(exec_size
),
822 unreachable("MRF registers are not allowed as sources");
824 unreachable("Invalid register file");
829 fs_inst::reads_flag() const
835 fs_inst::writes_flag() const
837 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
838 opcode
!= BRW_OPCODE_IF
&&
839 opcode
!= BRW_OPCODE_WHILE
)) ||
840 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
844 * Returns how many MRFs an FS opcode will write over.
846 * Note that this is not the 0 or 1 implied writes in an actual gen
847 * instruction -- the FS opcodes often generate MOVs in addition.
850 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
855 if (inst
->base_mrf
== -1)
858 switch (inst
->opcode
) {
859 case SHADER_OPCODE_RCP
:
860 case SHADER_OPCODE_RSQ
:
861 case SHADER_OPCODE_SQRT
:
862 case SHADER_OPCODE_EXP2
:
863 case SHADER_OPCODE_LOG2
:
864 case SHADER_OPCODE_SIN
:
865 case SHADER_OPCODE_COS
:
866 return 1 * dispatch_width
/ 8;
867 case SHADER_OPCODE_POW
:
868 case SHADER_OPCODE_INT_QUOTIENT
:
869 case SHADER_OPCODE_INT_REMAINDER
:
870 return 2 * dispatch_width
/ 8;
871 case SHADER_OPCODE_TEX
:
873 case SHADER_OPCODE_TXD
:
874 case SHADER_OPCODE_TXF
:
875 case SHADER_OPCODE_TXF_CMS
:
876 case SHADER_OPCODE_TXF_MCS
:
877 case SHADER_OPCODE_TG4
:
878 case SHADER_OPCODE_TG4_OFFSET
:
879 case SHADER_OPCODE_TXL
:
880 case SHADER_OPCODE_TXS
:
881 case SHADER_OPCODE_LOD
:
882 case SHADER_OPCODE_SAMPLEINFO
:
884 case FS_OPCODE_FB_WRITE
:
886 case FS_OPCODE_GET_BUFFER_SIZE
:
887 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
888 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
890 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
892 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
894 case SHADER_OPCODE_UNTYPED_ATOMIC
:
895 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
896 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
897 case SHADER_OPCODE_TYPED_ATOMIC
:
898 case SHADER_OPCODE_TYPED_SURFACE_READ
:
899 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
900 case SHADER_OPCODE_URB_WRITE_SIMD8
:
901 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
902 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
903 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
904 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
907 unreachable("not reached");
912 fs_visitor::vgrf(const glsl_type
*const type
)
914 int reg_width
= dispatch_width
/ 8;
915 return fs_reg(GRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
916 brw_type_for_base_type(type
));
919 /** Fixed HW reg constructor. */
920 fs_reg::fs_reg(enum register_file file
, int reg
)
925 this->type
= BRW_REGISTER_TYPE_F
;
926 this->stride
= (file
== UNIFORM
? 0 : 1);
929 /** Fixed HW reg constructor. */
930 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
)
936 this->stride
= (file
== UNIFORM
? 0 : 1);
939 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
940 * This brings in those uniform definitions
943 fs_visitor::import_uniforms(fs_visitor
*v
)
945 this->push_constant_loc
= v
->push_constant_loc
;
946 this->pull_constant_loc
= v
->pull_constant_loc
;
947 this->uniforms
= v
->uniforms
;
948 this->param_size
= v
->param_size
;
952 fs_visitor::setup_vec4_uniform_value(unsigned param_offset
,
953 const gl_constant_value
*values
,
956 static const gl_constant_value zero
= { 0 };
958 for (unsigned i
= 0; i
< n
; ++i
)
959 stage_prog_data
->param
[param_offset
+ i
] = &values
[i
];
961 for (unsigned i
= n
; i
< 4; ++i
)
962 stage_prog_data
->param
[param_offset
+ i
] = &zero
;
966 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
967 bool origin_upper_left
)
969 assert(stage
== MESA_SHADER_FRAGMENT
);
970 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
971 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
973 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
976 if (pixel_center_integer
) {
977 bld
.MOV(wpos
, this->pixel_x
);
979 bld
.ADD(wpos
, this->pixel_x
, fs_reg(0.5f
));
981 wpos
= offset(wpos
, bld
, 1);
984 if (!flip
&& pixel_center_integer
) {
985 bld
.MOV(wpos
, this->pixel_y
);
987 fs_reg pixel_y
= this->pixel_y
;
988 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
991 pixel_y
.negate
= true;
992 offset
+= key
->drawable_height
- 1.0f
;
995 bld
.ADD(wpos
, pixel_y
, fs_reg(offset
));
997 wpos
= offset(wpos
, bld
, 1);
1000 if (devinfo
->gen
>= 6) {
1001 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1003 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1004 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1005 interp_reg(VARYING_SLOT_POS
, 2));
1007 wpos
= offset(wpos
, bld
, 1);
1009 /* gl_FragCoord.w: Already set up in emit_interpolation */
1010 bld
.MOV(wpos
, this->wpos_w
);
1016 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1017 glsl_interp_qualifier interpolation_mode
,
1018 bool is_centroid
, bool is_sample
)
1020 brw_wm_barycentric_interp_mode barycoord_mode
;
1021 if (devinfo
->gen
>= 6) {
1023 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1024 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1026 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1027 } else if (is_sample
) {
1028 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1029 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1031 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1033 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1034 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1036 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1039 /* On Ironlake and below, there is only one interpolation mode.
1040 * Centroid interpolation doesn't mean anything on this hardware --
1041 * there is no multisampling.
1043 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1045 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1046 this->delta_xy
[barycoord_mode
], interp
);
1050 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
1051 const glsl_type
*type
,
1052 glsl_interp_qualifier interpolation_mode
,
1053 int location
, bool mod_centroid
,
1056 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
1058 assert(stage
== MESA_SHADER_FRAGMENT
);
1059 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1060 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1062 unsigned int array_elements
;
1064 if (type
->is_array()) {
1065 array_elements
= type
->length
;
1066 if (array_elements
== 0) {
1067 fail("dereferenced array '%s' has length 0\n", name
);
1069 type
= type
->fields
.array
;
1074 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1076 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1077 if (key
->flat_shade
&& is_gl_Color
) {
1078 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1080 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1084 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1085 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1086 if (prog_data
->urb_setup
[location
] == -1) {
1087 /* If there's no incoming setup data for this slot, don't
1088 * emit interpolation for it.
1090 attr
= offset(attr
, bld
, type
->vector_elements
);
1095 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1096 /* Constant interpolation (flat shading) case. The SF has
1097 * handed us defined values in only the constant offset
1098 * field of the setup reg.
1100 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1101 struct brw_reg interp
= interp_reg(location
, k
);
1102 interp
= suboffset(interp
, 3);
1103 interp
.type
= attr
.type
;
1104 bld
.emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1105 attr
= offset(attr
, bld
, 1);
1108 /* Smooth/noperspective interpolation case. */
1109 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1110 struct brw_reg interp
= interp_reg(location
, k
);
1111 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1112 /* Get the pixel/sample mask into f0 so that we know
1113 * which pixels are lit. Then, for each channel that is
1114 * unlit, replace the centroid data with non-centroid
1117 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1120 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1122 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1123 inst
->predicate_inverse
= true;
1124 if (devinfo
->has_pln
)
1125 inst
->no_dd_clear
= true;
1127 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1128 mod_centroid
&& !key
->persample_shading
,
1129 mod_sample
|| key
->persample_shading
);
1130 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1131 inst
->predicate_inverse
= false;
1132 if (devinfo
->has_pln
)
1133 inst
->no_dd_check
= true;
1136 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1137 mod_centroid
&& !key
->persample_shading
,
1138 mod_sample
|| key
->persample_shading
);
1140 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1141 bld
.MUL(attr
, attr
, this->pixel_w
);
1143 attr
= offset(attr
, bld
, 1);
1153 fs_visitor::emit_frontfacing_interpolation()
1155 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1157 if (devinfo
->gen
>= 6) {
1158 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1159 * a boolean result from this (~0/true or 0/false).
1161 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1162 * this task in only one instruction:
1163 * - a negation source modifier will flip the bit; and
1164 * - a W -> D type conversion will sign extend the bit into the high
1165 * word of the destination.
1167 * An ASR 15 fills the low word of the destination.
1169 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1172 bld
.ASR(*reg
, g0
, fs_reg(15));
1174 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1175 * a boolean result from this (1/true or 0/false).
1177 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1178 * the negation source modifier to flip it. Unfortunately the SHR
1179 * instruction only operates on UD (or D with an abs source modifier)
1180 * sources without negation.
1182 * Instead, use ASR (which will give ~0/true or 0/false).
1184 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1187 bld
.ASR(*reg
, g1_6
, fs_reg(31));
1194 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1196 assert(stage
== MESA_SHADER_FRAGMENT
);
1197 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1198 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1200 if (key
->compute_pos_offset
) {
1201 /* Convert int_sample_pos to floating point */
1202 bld
.MOV(dst
, int_sample_pos
);
1203 /* Scale to the range [0, 1] */
1204 bld
.MUL(dst
, dst
, fs_reg(1 / 16.0f
));
1207 /* From ARB_sample_shading specification:
1208 * "When rendering to a non-multisample buffer, or if multisample
1209 * rasterization is disabled, gl_SamplePosition will always be
1212 bld
.MOV(dst
, fs_reg(0.5f
));
1217 fs_visitor::emit_samplepos_setup()
1219 assert(devinfo
->gen
>= 6);
1221 const fs_builder abld
= bld
.annotate("compute sample position");
1222 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1224 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1225 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1227 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1228 * mode will be enabled.
1230 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1231 * R31.1:0 Position Offset X/Y for Slot[3:0]
1232 * R31.3:2 Position Offset X/Y for Slot[7:4]
1235 * The X, Y sample positions come in as bytes in thread payload. So, read
1236 * the positions using vstride=16, width=8, hstride=2.
1238 struct brw_reg sample_pos_reg
=
1239 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1240 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1242 if (dispatch_width
== 8) {
1243 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1245 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1246 abld
.half(1).MOV(half(int_sample_x
, 1),
1247 fs_reg(suboffset(sample_pos_reg
, 16)));
1249 /* Compute gl_SamplePosition.x */
1250 compute_sample_position(pos
, int_sample_x
);
1251 pos
= offset(pos
, abld
, 1);
1252 if (dispatch_width
== 8) {
1253 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1255 abld
.half(0).MOV(half(int_sample_y
, 0),
1256 fs_reg(suboffset(sample_pos_reg
, 1)));
1257 abld
.half(1).MOV(half(int_sample_y
, 1),
1258 fs_reg(suboffset(sample_pos_reg
, 17)));
1260 /* Compute gl_SamplePosition.y */
1261 compute_sample_position(pos
, int_sample_y
);
1266 fs_visitor::emit_sampleid_setup()
1268 assert(stage
== MESA_SHADER_FRAGMENT
);
1269 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1270 assert(devinfo
->gen
>= 6);
1272 const fs_builder abld
= bld
.annotate("compute sample id");
1273 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1275 if (key
->compute_sample_id
) {
1276 fs_reg t1
= vgrf(glsl_type::int_type
);
1277 fs_reg t2
= vgrf(glsl_type::int_type
);
1278 t2
.type
= BRW_REGISTER_TYPE_UW
;
1280 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1281 * 8x multisampling, subspan 0 will represent sample N (where N
1282 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1283 * 7. We can find the value of N by looking at R0.0 bits 7:6
1284 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1285 * (since samples are always delivered in pairs). That is, we
1286 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1287 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1288 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1289 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1290 * populating a temporary variable with the sequence (0, 1, 2, 3),
1291 * and then reading from it using vstride=1, width=4, hstride=0.
1292 * These computations hold good for 4x multisampling as well.
1294 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1295 * the first four slots are sample 0 of subspan 0; the next four
1296 * are sample 1 of subspan 0; the third group is sample 0 of
1297 * subspan 1, and finally sample 1 of subspan 1.
1300 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1302 abld
.exec_all().SHR(t1
, t1
, fs_reg(5));
1304 /* This works for both SIMD8 and SIMD16 */
1306 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1308 /* This special instruction takes care of setting vstride=1,
1309 * width=4, hstride=0 of t2 during an ADD instruction.
1311 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1313 /* As per GL_ARB_sample_shading specification:
1314 * "When rendering to a non-multisample buffer, or if multisample
1315 * rasterization is disabled, gl_SampleID will always be zero."
1317 abld
.MOV(*reg
, fs_reg(0));
1324 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1326 if (!src
.abs
&& !src
.negate
)
1329 fs_reg temp
= bld
.vgrf(src
.type
);
1336 fs_visitor::emit_discard_jump()
1338 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1340 /* For performance, after a discard, jump to the end of the
1341 * shader if all relevant channels have been discarded.
1343 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1344 discard_jump
->flag_subreg
= 1;
1346 discard_jump
->predicate
= (dispatch_width
== 8)
1347 ? BRW_PREDICATE_ALIGN1_ANY8H
1348 : BRW_PREDICATE_ALIGN1_ANY16H
;
1349 discard_jump
->predicate_inverse
= true;
1353 fs_visitor::assign_curb_setup()
1355 if (dispatch_width
== 8) {
1356 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1358 if (stage
== MESA_SHADER_FRAGMENT
) {
1359 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1360 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1361 } else if (stage
== MESA_SHADER_COMPUTE
) {
1362 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1363 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1365 unreachable("Unsupported shader type!");
1369 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1371 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1372 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1373 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1374 if (inst
->src
[i
].file
== UNIFORM
) {
1375 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1377 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1378 constant_nr
= push_constant_loc
[uniform_nr
];
1380 /* Section 5.11 of the OpenGL 4.1 spec says:
1381 * "Out-of-bounds reads return undefined values, which include
1382 * values from other variables of the active program or zero."
1383 * Just return the first push constant.
1388 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1392 assert(inst
->src
[i
].stride
== 0);
1393 inst
->src
[i
].file
= HW_REG
;
1394 inst
->src
[i
].fixed_hw_reg
= byte_offset(
1395 retype(brw_reg
, inst
->src
[i
].type
),
1396 inst
->src
[i
].subreg_offset
);
1401 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1402 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1406 fs_visitor::calculate_urb_setup()
1408 assert(stage
== MESA_SHADER_FRAGMENT
);
1409 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1410 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1412 memset(prog_data
->urb_setup
, -1,
1413 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1416 /* Figure out where each of the incoming setup attributes lands. */
1417 if (devinfo
->gen
>= 6) {
1418 if (_mesa_bitcount_64(prog
->InputsRead
&
1419 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1420 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1421 * first 16 varying inputs, so we can put them wherever we want.
1422 * Just put them in order.
1424 * This is useful because it means that (a) inputs not used by the
1425 * fragment shader won't take up valuable register space, and (b) we
1426 * won't have to recompile the fragment shader if it gets paired with
1427 * a different vertex (or geometry) shader.
1429 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1430 if (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1431 BITFIELD64_BIT(i
)) {
1432 prog_data
->urb_setup
[i
] = urb_next
++;
1436 /* We have enough input varyings that the SF/SBE pipeline stage can't
1437 * arbitrarily rearrange them to suit our whim; we have to put them
1438 * in an order that matches the output of the previous pipeline stage
1439 * (geometry or vertex shader).
1441 struct brw_vue_map prev_stage_vue_map
;
1442 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1443 key
->input_slots_valid
,
1444 shader_prog
->SeparateShader
);
1445 int first_slot
= 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1446 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1447 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1449 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1450 /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
1453 if (varying
!= BRW_VARYING_SLOT_COUNT
&&
1454 (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1455 BITFIELD64_BIT(varying
))) {
1456 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1459 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1462 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1463 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1464 /* Point size is packed into the header, not as a general attribute */
1465 if (i
== VARYING_SLOT_PSIZ
)
1468 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1469 /* The back color slot is skipped when the front color is
1470 * also written to. In addition, some slots can be
1471 * written in the vertex shader and not read in the
1472 * fragment shader. So the register number must always be
1473 * incremented, mapped or not.
1475 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1476 prog_data
->urb_setup
[i
] = urb_next
;
1482 * It's a FS only attribute, and we did interpolation for this attribute
1483 * in SF thread. So, count it here, too.
1485 * See compile_sf_prog() for more info.
1487 if (prog
->InputsRead
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1488 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1491 prog_data
->num_varying_inputs
= urb_next
;
1495 fs_visitor::assign_urb_setup()
1497 assert(stage
== MESA_SHADER_FRAGMENT
);
1498 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1500 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1502 /* Offset all the urb_setup[] index by the actual position of the
1503 * setup regs, now that the location of the constants has been chosen.
1505 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1506 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1507 assert(inst
->src
[1].file
== HW_REG
);
1508 inst
->src
[1].fixed_hw_reg
.nr
+= urb_start
;
1511 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1512 assert(inst
->src
[0].file
== HW_REG
);
1513 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1517 /* Each attribute is 4 setup channels, each of which is half a reg. */
1518 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1522 fs_visitor::assign_vs_urb_setup()
1524 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1525 int grf
, count
, slot
, channel
, attr
;
1527 assert(stage
== MESA_SHADER_VERTEX
);
1528 count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1529 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1532 /* Each attribute is 4 regs. */
1533 this->first_non_payload_grf
+= count
* 4;
1535 unsigned vue_entries
=
1536 MAX2(count
, vs_prog_data
->base
.vue_map
.num_slots
);
1538 vs_prog_data
->base
.urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1539 vs_prog_data
->base
.urb_read_length
= (count
+ 1) / 2;
1541 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1543 /* Rewrite all ATTR file references to the hw grf that they land in. */
1544 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1545 for (int i
= 0; i
< inst
->sources
; i
++) {
1546 if (inst
->src
[i
].file
== ATTR
) {
1548 if (inst
->src
[i
].reg
== VERT_ATTRIB_MAX
) {
1551 /* Attributes come in in a contiguous block, ordered by their
1552 * gl_vert_attrib value. That means we can compute the slot
1553 * number for an attribute by masking out the enabled
1554 * attributes before it and counting the bits.
1556 attr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
/ 4;
1557 slot
= _mesa_bitcount_64(vs_prog_data
->inputs_read
&
1558 BITFIELD64_MASK(attr
));
1561 channel
= inst
->src
[i
].reg_offset
& 3;
1563 grf
= payload
.num_regs
+
1564 prog_data
->curb_read_length
+
1567 inst
->src
[i
].file
= HW_REG
;
1568 inst
->src
[i
].fixed_hw_reg
=
1569 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1570 inst
->src
[i
].subreg_offset
),
1571 inst
->exec_size
* inst
->src
[i
].stride
,
1572 inst
->exec_size
, inst
->src
[i
].stride
);
1579 * Split large virtual GRFs into separate components if we can.
1581 * This is mostly duplicated with what brw_fs_vector_splitting does,
1582 * but that's really conservative because it's afraid of doing
1583 * splitting that doesn't result in real progress after the rest of
1584 * the optimization phases, which would cause infinite looping in
1585 * optimization. We can do it once here, safely. This also has the
1586 * opportunity to split interpolated values, or maybe even uniforms,
1587 * which we don't have at the IR level.
1589 * We want to split, because virtual GRFs are what we register
1590 * allocate and spill (due to contiguousness requirements for some
1591 * instructions), and they're what we naturally generate in the
1592 * codegen process, but most virtual GRFs don't actually need to be
1593 * contiguous sets of GRFs. If we split, we'll end up with reduced
1594 * live intervals and better dead code elimination and coalescing.
1597 fs_visitor::split_virtual_grfs()
1599 int num_vars
= this->alloc
.count
;
1601 /* Count the total number of registers */
1603 int vgrf_to_reg
[num_vars
];
1604 for (int i
= 0; i
< num_vars
; i
++) {
1605 vgrf_to_reg
[i
] = reg_count
;
1606 reg_count
+= alloc
.sizes
[i
];
1609 /* An array of "split points". For each register slot, this indicates
1610 * if this slot can be separated from the previous slot. Every time an
1611 * instruction uses multiple elements of a register (as a source or
1612 * destination), we mark the used slots as inseparable. Then we go
1613 * through and split the registers into the smallest pieces we can.
1615 bool split_points
[reg_count
];
1616 memset(split_points
, 0, sizeof(split_points
));
1618 /* Mark all used registers as fully splittable */
1619 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1620 if (inst
->dst
.file
== GRF
) {
1621 int reg
= vgrf_to_reg
[inst
->dst
.reg
];
1622 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.reg
]; j
++)
1623 split_points
[reg
+ j
] = true;
1626 for (int i
= 0; i
< inst
->sources
; i
++) {
1627 if (inst
->src
[i
].file
== GRF
) {
1628 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
];
1629 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].reg
]; j
++)
1630 split_points
[reg
+ j
] = true;
1635 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1636 if (inst
->dst
.file
== GRF
) {
1637 int reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1638 for (int j
= 1; j
< inst
->regs_written
; j
++)
1639 split_points
[reg
+ j
] = false;
1641 for (int i
= 0; i
< inst
->sources
; i
++) {
1642 if (inst
->src
[i
].file
== GRF
) {
1643 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1644 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1645 split_points
[reg
+ j
] = false;
1650 int new_virtual_grf
[reg_count
];
1651 int new_reg_offset
[reg_count
];
1654 for (int i
= 0; i
< num_vars
; i
++) {
1655 /* The first one should always be 0 as a quick sanity check. */
1656 assert(split_points
[reg
] == false);
1659 new_reg_offset
[reg
] = 0;
1664 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1665 /* If this is a split point, reset the offset to 0 and allocate a
1666 * new virtual GRF for the previous offset many registers
1668 if (split_points
[reg
]) {
1669 assert(offset
<= MAX_VGRF_SIZE
);
1670 int grf
= alloc
.allocate(offset
);
1671 for (int k
= reg
- offset
; k
< reg
; k
++)
1672 new_virtual_grf
[k
] = grf
;
1675 new_reg_offset
[reg
] = offset
;
1680 /* The last one gets the original register number */
1681 assert(offset
<= MAX_VGRF_SIZE
);
1682 alloc
.sizes
[i
] = offset
;
1683 for (int k
= reg
- offset
; k
< reg
; k
++)
1684 new_virtual_grf
[k
] = i
;
1686 assert(reg
== reg_count
);
1688 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1689 if (inst
->dst
.file
== GRF
) {
1690 reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1691 inst
->dst
.reg
= new_virtual_grf
[reg
];
1692 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1693 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1695 for (int i
= 0; i
< inst
->sources
; i
++) {
1696 if (inst
->src
[i
].file
== GRF
) {
1697 reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1698 inst
->src
[i
].reg
= new_virtual_grf
[reg
];
1699 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1700 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1704 invalidate_live_intervals();
1708 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1710 * During code generation, we create tons of temporary variables, many of
1711 * which get immediately killed and are never used again. Yet, in later
1712 * optimization and analysis passes, such as compute_live_intervals, we need
1713 * to loop over all the virtual GRFs. Compacting them can save a lot of
1717 fs_visitor::compact_virtual_grfs()
1719 bool progress
= false;
1720 int remap_table
[this->alloc
.count
];
1721 memset(remap_table
, -1, sizeof(remap_table
));
1723 /* Mark which virtual GRFs are used. */
1724 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1725 if (inst
->dst
.file
== GRF
)
1726 remap_table
[inst
->dst
.reg
] = 0;
1728 for (int i
= 0; i
< inst
->sources
; i
++) {
1729 if (inst
->src
[i
].file
== GRF
)
1730 remap_table
[inst
->src
[i
].reg
] = 0;
1734 /* Compact the GRF arrays. */
1736 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1737 if (remap_table
[i
] == -1) {
1738 /* We just found an unused register. This means that we are
1739 * actually going to compact something.
1743 remap_table
[i
] = new_index
;
1744 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1745 invalidate_live_intervals();
1750 this->alloc
.count
= new_index
;
1752 /* Patch all the instructions to use the newly renumbered registers */
1753 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1754 if (inst
->dst
.file
== GRF
)
1755 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
1757 for (int i
= 0; i
< inst
->sources
; i
++) {
1758 if (inst
->src
[i
].file
== GRF
)
1759 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
1763 /* Patch all the references to delta_xy, since they're used in register
1764 * allocation. If they're unused, switch them to BAD_FILE so we don't
1765 * think some random VGRF is delta_xy.
1767 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1768 if (delta_xy
[i
].file
== GRF
) {
1769 if (remap_table
[delta_xy
[i
].reg
] != -1) {
1770 delta_xy
[i
].reg
= remap_table
[delta_xy
[i
].reg
];
1772 delta_xy
[i
].file
= BAD_FILE
;
1781 * Assign UNIFORM file registers to either push constants or pull constants.
1783 * We allow a fragment shader to have more than the specified minimum
1784 * maximum number of fragment shader uniform components (64). If
1785 * there are too many of these, they'd fill up all of register space.
1786 * So, this will push some of them out to the pull constant buffer and
1787 * update the program to load them. We also use pull constants for all
1788 * indirect constant loads because we don't support indirect accesses in
1792 fs_visitor::assign_constant_locations()
1794 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1795 if (dispatch_width
!= 8)
1798 unsigned int num_pull_constants
= 0;
1800 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1801 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1803 bool is_live
[uniforms
];
1804 memset(is_live
, 0, sizeof(is_live
));
1806 /* First, we walk through the instructions and do two things:
1808 * 1) Figure out which uniforms are live.
1810 * 2) Find all indirect access of uniform arrays and flag them as needing
1811 * to go into the pull constant buffer.
1813 * Note that we don't move constant-indexed accesses to arrays. No
1814 * testing has been done of the performance impact of this choice.
1816 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1817 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1818 if (inst
->src
[i
].file
!= UNIFORM
)
1821 if (inst
->src
[i
].reladdr
) {
1822 int uniform
= inst
->src
[i
].reg
;
1824 /* If this array isn't already present in the pull constant buffer,
1827 if (pull_constant_loc
[uniform
] == -1) {
1828 assert(param_size
[uniform
]);
1829 for (int j
= 0; j
< param_size
[uniform
]; j
++)
1830 pull_constant_loc
[uniform
+ j
] = num_pull_constants
++;
1833 /* Mark the the one accessed uniform as live */
1834 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1835 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1836 is_live
[constant_nr
] = true;
1841 /* Only allow 16 registers (128 uniform components) as push constants.
1843 * Just demote the end of the list. We could probably do better
1844 * here, demoting things that are rarely used in the program first.
1846 * If changing this value, note the limitation about total_regs in
1849 unsigned int max_push_components
= 16 * 8;
1850 unsigned int num_push_constants
= 0;
1852 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1854 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1855 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1856 /* This UNIFORM register is either dead, or has already been demoted
1857 * to a pull const. Mark it as no longer living in the param[] array.
1859 push_constant_loc
[i
] = -1;
1863 if (num_push_constants
< max_push_components
) {
1864 /* Retain as a push constant. Record the location in the params[]
1867 push_constant_loc
[i
] = num_push_constants
++;
1869 /* Demote to a pull constant. */
1870 push_constant_loc
[i
] = -1;
1871 pull_constant_loc
[i
] = num_pull_constants
++;
1875 stage_prog_data
->nr_params
= num_push_constants
;
1876 stage_prog_data
->nr_pull_params
= num_pull_constants
;
1878 /* Up until now, the param[] array has been indexed by reg + reg_offset
1879 * of UNIFORM registers. Move pull constants into pull_param[] and
1880 * condense param[] to only contain the uniforms we chose to push.
1882 * NOTE: Because we are condensing the params[] array, we know that
1883 * push_constant_loc[i] <= i and we can do it in one smooth loop without
1884 * having to make a copy.
1886 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1887 const gl_constant_value
*value
= stage_prog_data
->param
[i
];
1889 if (pull_constant_loc
[i
] != -1) {
1890 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
1891 } else if (push_constant_loc
[i
] != -1) {
1892 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
1898 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
1899 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
1902 fs_visitor::demote_pull_constants()
1904 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1905 for (int i
= 0; i
< inst
->sources
; i
++) {
1906 if (inst
->src
[i
].file
!= UNIFORM
)
1910 unsigned location
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1911 if (location
>= uniforms
) /* Out of bounds access */
1914 pull_index
= pull_constant_loc
[location
];
1916 if (pull_index
== -1)
1919 /* Set up the annotation tracking for new generated instructions. */
1920 const fs_builder
ibld(this, block
, inst
);
1921 fs_reg
surf_index(stage_prog_data
->binding_table
.pull_constants_start
);
1922 fs_reg dst
= vgrf(glsl_type::float_type
);
1924 assert(inst
->src
[i
].stride
== 0);
1926 /* Generate a pull load into dst. */
1927 if (inst
->src
[i
].reladdr
) {
1928 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
1930 *inst
->src
[i
].reladdr
,
1932 inst
->src
[i
].reladdr
= NULL
;
1933 inst
->src
[i
].stride
= 1;
1935 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
1936 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
1937 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
1938 dst
, surf_index
, offset
);
1939 inst
->src
[i
].set_smear(pull_index
& 3);
1942 /* Rewrite the instruction to use the temporary VGRF. */
1943 inst
->src
[i
].file
= GRF
;
1944 inst
->src
[i
].reg
= dst
.reg
;
1945 inst
->src
[i
].reg_offset
= 0;
1948 invalidate_live_intervals();
1952 fs_visitor::opt_algebraic()
1954 bool progress
= false;
1956 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1957 switch (inst
->opcode
) {
1958 case BRW_OPCODE_MOV
:
1959 if (inst
->src
[0].file
!= IMM
)
1962 if (inst
->saturate
) {
1963 if (inst
->dst
.type
!= inst
->src
[0].type
)
1964 assert(!"unimplemented: saturate mixed types");
1966 if (brw_saturate_immediate(inst
->dst
.type
,
1967 &inst
->src
[0].fixed_hw_reg
)) {
1968 inst
->saturate
= false;
1974 case BRW_OPCODE_MUL
:
1975 if (inst
->src
[1].file
!= IMM
)
1979 if (inst
->src
[1].is_one()) {
1980 inst
->opcode
= BRW_OPCODE_MOV
;
1981 inst
->src
[1] = reg_undef
;
1987 if (inst
->src
[1].is_negative_one()) {
1988 inst
->opcode
= BRW_OPCODE_MOV
;
1989 inst
->src
[0].negate
= !inst
->src
[0].negate
;
1990 inst
->src
[1] = reg_undef
;
1996 if (inst
->src
[1].is_zero()) {
1997 inst
->opcode
= BRW_OPCODE_MOV
;
1998 inst
->src
[0] = inst
->src
[1];
1999 inst
->src
[1] = reg_undef
;
2004 if (inst
->src
[0].file
== IMM
) {
2005 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2006 inst
->opcode
= BRW_OPCODE_MOV
;
2007 inst
->src
[0].fixed_hw_reg
.dw1
.f
*= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
2008 inst
->src
[1] = reg_undef
;
2013 case BRW_OPCODE_ADD
:
2014 if (inst
->src
[1].file
!= IMM
)
2018 if (inst
->src
[1].is_zero()) {
2019 inst
->opcode
= BRW_OPCODE_MOV
;
2020 inst
->src
[1] = reg_undef
;
2025 if (inst
->src
[0].file
== IMM
) {
2026 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2027 inst
->opcode
= BRW_OPCODE_MOV
;
2028 inst
->src
[0].fixed_hw_reg
.dw1
.f
+= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
2029 inst
->src
[1] = reg_undef
;
2035 if (inst
->src
[0].equals(inst
->src
[1])) {
2036 inst
->opcode
= BRW_OPCODE_MOV
;
2037 inst
->src
[1] = reg_undef
;
2042 case BRW_OPCODE_LRP
:
2043 if (inst
->src
[1].equals(inst
->src
[2])) {
2044 inst
->opcode
= BRW_OPCODE_MOV
;
2045 inst
->src
[0] = inst
->src
[1];
2046 inst
->src
[1] = reg_undef
;
2047 inst
->src
[2] = reg_undef
;
2052 case BRW_OPCODE_CMP
:
2053 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2055 inst
->src
[0].negate
&&
2056 inst
->src
[1].is_zero()) {
2057 inst
->src
[0].abs
= false;
2058 inst
->src
[0].negate
= false;
2059 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2064 case BRW_OPCODE_SEL
:
2065 if (inst
->src
[0].equals(inst
->src
[1])) {
2066 inst
->opcode
= BRW_OPCODE_MOV
;
2067 inst
->src
[1] = reg_undef
;
2068 inst
->predicate
= BRW_PREDICATE_NONE
;
2069 inst
->predicate_inverse
= false;
2071 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2072 switch (inst
->conditional_mod
) {
2073 case BRW_CONDITIONAL_LE
:
2074 case BRW_CONDITIONAL_L
:
2075 switch (inst
->src
[1].type
) {
2076 case BRW_REGISTER_TYPE_F
:
2077 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
>= 1.0f
) {
2078 inst
->opcode
= BRW_OPCODE_MOV
;
2079 inst
->src
[1] = reg_undef
;
2080 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2088 case BRW_CONDITIONAL_GE
:
2089 case BRW_CONDITIONAL_G
:
2090 switch (inst
->src
[1].type
) {
2091 case BRW_REGISTER_TYPE_F
:
2092 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
<= 0.0f
) {
2093 inst
->opcode
= BRW_OPCODE_MOV
;
2094 inst
->src
[1] = reg_undef
;
2095 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2107 case BRW_OPCODE_MAD
:
2108 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2109 inst
->opcode
= BRW_OPCODE_MOV
;
2110 inst
->src
[1] = reg_undef
;
2111 inst
->src
[2] = reg_undef
;
2113 } else if (inst
->src
[0].is_zero()) {
2114 inst
->opcode
= BRW_OPCODE_MUL
;
2115 inst
->src
[0] = inst
->src
[2];
2116 inst
->src
[2] = reg_undef
;
2118 } else if (inst
->src
[1].is_one()) {
2119 inst
->opcode
= BRW_OPCODE_ADD
;
2120 inst
->src
[1] = inst
->src
[2];
2121 inst
->src
[2] = reg_undef
;
2123 } else if (inst
->src
[2].is_one()) {
2124 inst
->opcode
= BRW_OPCODE_ADD
;
2125 inst
->src
[2] = reg_undef
;
2127 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2128 inst
->opcode
= BRW_OPCODE_ADD
;
2129 inst
->src
[1].fixed_hw_reg
.dw1
.f
*= inst
->src
[2].fixed_hw_reg
.dw1
.f
;
2130 inst
->src
[2] = reg_undef
;
2134 case SHADER_OPCODE_RCP
: {
2135 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2136 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2137 if (inst
->src
[0].equals(prev
->dst
)) {
2138 inst
->opcode
= SHADER_OPCODE_RSQ
;
2139 inst
->src
[0] = prev
->src
[0];
2145 case SHADER_OPCODE_BROADCAST
:
2146 if (is_uniform(inst
->src
[0])) {
2147 inst
->opcode
= BRW_OPCODE_MOV
;
2149 inst
->force_writemask_all
= true;
2151 } else if (inst
->src
[1].file
== IMM
) {
2152 inst
->opcode
= BRW_OPCODE_MOV
;
2153 inst
->src
[0] = component(inst
->src
[0],
2154 inst
->src
[1].fixed_hw_reg
.dw1
.ud
);
2156 inst
->force_writemask_all
= true;
2165 /* Swap if src[0] is immediate. */
2166 if (progress
&& inst
->is_commutative()) {
2167 if (inst
->src
[0].file
== IMM
) {
2168 fs_reg tmp
= inst
->src
[1];
2169 inst
->src
[1] = inst
->src
[0];
2178 * Optimize sample messages that have constant zero values for the trailing
2179 * texture coordinates. We can just reduce the message length for these
2180 * instructions instead of reserving a register for it. Trailing parameters
2181 * that aren't sent default to zero anyway. This will cause the dead code
2182 * eliminator to remove the MOV instruction that would otherwise be emitted to
2183 * set up the zero value.
2186 fs_visitor::opt_zero_samples()
2188 /* Gen4 infers the texturing opcode based on the message length so we can't
2191 if (devinfo
->gen
< 5)
2194 bool progress
= false;
2196 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2197 if (!inst
->is_tex())
2200 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2202 if (load_payload
->is_head_sentinel() ||
2203 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2206 /* We don't want to remove the message header or the first parameter.
2207 * Removing the first parameter is not allowed, see the Haswell PRM
2208 * volume 7, page 149:
2210 * "Parameter 0 is required except for the sampleinfo message, which
2211 * has no parameter 0"
2213 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2214 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2215 (inst
->exec_size
/ 8) +
2216 inst
->header_size
- 1].is_zero()) {
2217 inst
->mlen
-= inst
->exec_size
/ 8;
2223 invalidate_live_intervals();
2229 * Optimize sample messages which are followed by the final RT write.
2231 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2232 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2233 * final texturing results copied to the framebuffer write payload and modify
2234 * them to write to the framebuffer directly.
2237 fs_visitor::opt_sampler_eot()
2239 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2241 if (stage
!= MESA_SHADER_FRAGMENT
)
2244 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2247 /* FINISHME: It should be possible to implement this optimization when there
2248 * are multiple drawbuffers.
2250 if (key
->nr_color_regions
!= 1)
2253 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2254 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2255 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2256 assert(fb_write
->eot
);
2257 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2259 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2261 /* There wasn't one; nothing to do. */
2262 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2265 /* This optimisation doesn't seem to work for textureGather for some
2266 * reason. I can't find any documentation or known workarounds to indicate
2267 * that this is expected, but considering that it is probably pretty
2268 * unlikely that a shader would directly write out the results from
2269 * textureGather we might as well just disable it.
2271 if (tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2272 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2275 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2276 * It's very likely to be the previous instruction.
2278 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2279 if (load_payload
->is_head_sentinel() ||
2280 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2283 assert(!tex_inst
->eot
); /* We can't get here twice */
2284 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2286 const fs_builder
ibld(this, block
, tex_inst
);
2288 tex_inst
->offset
|= fb_write
->target
<< 24;
2289 tex_inst
->eot
= true;
2290 tex_inst
->dst
= ibld
.null_reg_ud();
2291 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2293 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2294 * to create a new LOAD_PAYLOAD command with the same sources and a space
2295 * saved for the header. Using a new destination register not only makes sure
2296 * we have enough space, but it will make sure the dead code eliminator kills
2297 * the instruction that this will replace.
2299 if (tex_inst
->header_size
!= 0)
2302 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2303 load_payload
->sources
+ 1);
2304 fs_reg
*new_sources
=
2305 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2307 new_sources
[0] = fs_reg();
2308 for (int i
= 0; i
< load_payload
->sources
; i
++)
2309 new_sources
[i
+1] = load_payload
->src
[i
];
2311 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2312 * requires a lot of information about the sources to appropriately figure
2313 * out the number of registers needed to be used. Given this stage in our
2314 * optimization, we may not have the appropriate GRFs required by
2315 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2316 * manually emit the instruction.
2318 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2319 load_payload
->exec_size
,
2322 load_payload
->sources
+ 1);
2324 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2325 new_load_payload
->header_size
= 1;
2327 tex_inst
->header_size
= 1;
2328 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2329 tex_inst
->src
[0] = send_header
;
2335 fs_visitor::opt_register_renaming()
2337 bool progress
= false;
2340 int remap
[alloc
.count
];
2341 memset(remap
, -1, sizeof(int) * alloc
.count
);
2343 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2344 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2346 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2347 inst
->opcode
== BRW_OPCODE_WHILE
) {
2351 /* Rewrite instruction sources. */
2352 for (int i
= 0; i
< inst
->sources
; i
++) {
2353 if (inst
->src
[i
].file
== GRF
&&
2354 remap
[inst
->src
[i
].reg
] != -1 &&
2355 remap
[inst
->src
[i
].reg
] != inst
->src
[i
].reg
) {
2356 inst
->src
[i
].reg
= remap
[inst
->src
[i
].reg
];
2361 const int dst
= inst
->dst
.reg
;
2364 inst
->dst
.file
== GRF
&&
2365 alloc
.sizes
[inst
->dst
.reg
] == inst
->exec_size
/ 8 &&
2366 !inst
->is_partial_write()) {
2367 if (remap
[dst
] == -1) {
2370 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2371 inst
->dst
.reg
= remap
[dst
];
2374 } else if (inst
->dst
.file
== GRF
&&
2376 remap
[dst
] != dst
) {
2377 inst
->dst
.reg
= remap
[dst
];
2383 invalidate_live_intervals();
2385 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2386 if (delta_xy
[i
].file
== GRF
&& remap
[delta_xy
[i
].reg
] != -1) {
2387 delta_xy
[i
].reg
= remap
[delta_xy
[i
].reg
];
2396 * Remove redundant or useless discard jumps.
2398 * For example, we can eliminate jumps in the following sequence:
2400 * discard-jump (redundant with the next jump)
2401 * discard-jump (useless; jumps to the next instruction)
2405 fs_visitor::opt_redundant_discard_jumps()
2407 bool progress
= false;
2409 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2411 fs_inst
*placeholder_halt
= NULL
;
2412 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2413 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2414 placeholder_halt
= inst
;
2419 if (!placeholder_halt
)
2422 /* Delete any HALTs immediately before the placeholder halt. */
2423 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2424 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2425 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2426 prev
->remove(last_bblock
);
2431 invalidate_live_intervals();
2437 fs_visitor::compute_to_mrf()
2439 bool progress
= false;
2442 /* No MRFs on Gen >= 7. */
2443 if (devinfo
->gen
>= 7)
2446 calculate_live_intervals();
2448 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2452 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2453 inst
->is_partial_write() ||
2454 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2455 inst
->dst
.type
!= inst
->src
[0].type
||
2456 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2457 !inst
->src
[0].is_contiguous() ||
2458 inst
->src
[0].subreg_offset
)
2461 /* Work out which hardware MRF registers are written by this
2464 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2466 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2467 mrf_high
= mrf_low
+ 4;
2468 } else if (inst
->exec_size
== 16) {
2469 mrf_high
= mrf_low
+ 1;
2474 /* Can't compute-to-MRF this GRF if someone else was going to
2477 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2480 /* Found a move of a GRF to a MRF. Let's see if we can go
2481 * rewrite the thing that made this GRF to write into the MRF.
2483 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2484 if (scan_inst
->dst
.file
== GRF
&&
2485 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2486 /* Found the last thing to write our reg we want to turn
2487 * into a compute-to-MRF.
2490 /* If this one instruction didn't populate all the
2491 * channels, bail. We might be able to rewrite everything
2492 * that writes that reg, but it would require smarter
2493 * tracking to delay the rewriting until complete success.
2495 if (scan_inst
->is_partial_write())
2498 /* Things returning more than one register would need us to
2499 * understand coalescing out more than one MOV at a time.
2501 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2504 /* SEND instructions can't have MRF as a destination. */
2505 if (scan_inst
->mlen
)
2508 if (devinfo
->gen
== 6) {
2509 /* gen6 math instructions must have the destination be
2510 * GRF, so no compute-to-MRF for them.
2512 if (scan_inst
->is_math()) {
2517 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2518 /* Found the creator of our MRF's source value. */
2519 scan_inst
->dst
.file
= MRF
;
2520 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2521 scan_inst
->saturate
|= inst
->saturate
;
2522 inst
->remove(block
);
2528 /* We don't handle control flow here. Most computation of
2529 * values that end up in MRFs are shortly before the MRF
2532 if (block
->start() == scan_inst
)
2535 /* You can't read from an MRF, so if someone else reads our
2536 * MRF's source GRF that we wanted to rewrite, that stops us.
2538 bool interfered
= false;
2539 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2540 if (scan_inst
->src
[i
].file
== GRF
&&
2541 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2542 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2549 if (scan_inst
->dst
.file
== MRF
) {
2550 /* If somebody else writes our MRF here, we can't
2551 * compute-to-MRF before that.
2553 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2556 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2557 scan_mrf_high
= scan_mrf_low
+ 4;
2558 } else if (scan_inst
->exec_size
== 16) {
2559 scan_mrf_high
= scan_mrf_low
+ 1;
2561 scan_mrf_high
= scan_mrf_low
;
2564 if (mrf_low
== scan_mrf_low
||
2565 mrf_low
== scan_mrf_high
||
2566 mrf_high
== scan_mrf_low
||
2567 mrf_high
== scan_mrf_high
) {
2572 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2573 /* Found a SEND instruction, which means that there are
2574 * live values in MRFs from base_mrf to base_mrf +
2575 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2578 if (mrf_low
>= scan_inst
->base_mrf
&&
2579 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2582 if (mrf_high
>= scan_inst
->base_mrf
&&
2583 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2591 invalidate_live_intervals();
2597 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2598 * flow. We could probably do better here with some form of divergence
2602 fs_visitor::eliminate_find_live_channel()
2604 bool progress
= false;
2607 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2608 switch (inst
->opcode
) {
2614 case BRW_OPCODE_ENDIF
:
2615 case BRW_OPCODE_WHILE
:
2619 case FS_OPCODE_DISCARD_JUMP
:
2620 /* This can potentially make control flow non-uniform until the end
2625 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2627 inst
->opcode
= BRW_OPCODE_MOV
;
2628 inst
->src
[0] = fs_reg(0);
2630 inst
->force_writemask_all
= true;
2644 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2645 * instructions to FS_OPCODE_REP_FB_WRITE.
2648 fs_visitor::emit_repclear_shader()
2650 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2652 int color_mrf
= base_mrf
+ 2;
2654 fs_inst
*mov
= bld
.exec_all().MOV(vec4(brw_message_reg(color_mrf
)),
2655 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2658 if (key
->nr_color_regions
== 1) {
2659 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2660 write
->saturate
= key
->clamp_fragment_color
;
2661 write
->base_mrf
= color_mrf
;
2663 write
->header_size
= 0;
2666 assume(key
->nr_color_regions
> 0);
2667 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2668 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2669 write
->saturate
= key
->clamp_fragment_color
;
2670 write
->base_mrf
= base_mrf
;
2672 write
->header_size
= 2;
2680 assign_constant_locations();
2681 assign_curb_setup();
2683 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2684 assert(mov
->src
[0].file
== HW_REG
);
2685 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].fixed_hw_reg
.nr
, 0);
2689 * Walks through basic blocks, looking for repeated MRF writes and
2690 * removing the later ones.
2693 fs_visitor::remove_duplicate_mrf_writes()
2695 fs_inst
*last_mrf_move
[16];
2696 bool progress
= false;
2698 /* Need to update the MRF tracking for compressed instructions. */
2699 if (dispatch_width
== 16)
2702 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2704 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2705 if (inst
->is_control_flow()) {
2706 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2709 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2710 inst
->dst
.file
== MRF
) {
2711 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2712 if (prev_inst
&& inst
->equals(prev_inst
)) {
2713 inst
->remove(block
);
2719 /* Clear out the last-write records for MRFs that were overwritten. */
2720 if (inst
->dst
.file
== MRF
) {
2721 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2724 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2725 /* Found a SEND instruction, which will include two or fewer
2726 * implied MRF writes. We could do better here.
2728 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2729 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2733 /* Clear out any MRF move records whose sources got overwritten. */
2734 if (inst
->dst
.file
== GRF
) {
2735 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2736 if (last_mrf_move
[i
] &&
2737 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2738 last_mrf_move
[i
] = NULL
;
2743 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2744 inst
->dst
.file
== MRF
&&
2745 inst
->src
[0].file
== GRF
&&
2746 !inst
->is_partial_write()) {
2747 last_mrf_move
[inst
->dst
.reg
] = inst
;
2752 invalidate_live_intervals();
2758 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2760 /* Clear the flag for registers that actually got read (as expected). */
2761 for (int i
= 0; i
< inst
->sources
; i
++) {
2763 if (inst
->src
[i
].file
== GRF
) {
2764 grf
= inst
->src
[i
].reg
;
2765 } else if (inst
->src
[i
].file
== HW_REG
&&
2766 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
2767 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
2772 if (grf
>= first_grf
&&
2773 grf
< first_grf
+ grf_len
) {
2774 deps
[grf
- first_grf
] = false;
2775 if (inst
->exec_size
== 16)
2776 deps
[grf
- first_grf
+ 1] = false;
2782 * Implements this workaround for the original 965:
2784 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2785 * check for post destination dependencies on this instruction, software
2786 * must ensure that there is no destination hazard for the case of ‘write
2787 * followed by a posted write’ shown in the following example.
2790 * 2. send r3.xy <rest of send instruction>
2793 * Due to no post-destination dependency check on the ‘send’, the above
2794 * code sequence could have two instructions (1 and 2) in flight at the
2795 * same time that both consider ‘r3’ as the target of their final writes.
2798 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2801 int write_len
= inst
->regs_written
;
2802 int first_write_grf
= inst
->dst
.reg
;
2803 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2804 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2806 memset(needs_dep
, false, sizeof(needs_dep
));
2807 memset(needs_dep
, true, write_len
);
2809 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2811 /* Walk backwards looking for writes to registers we're writing which
2812 * aren't read since being written. If we hit the start of the program,
2813 * we assume that there are no outstanding dependencies on entry to the
2816 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2817 /* If we hit control flow, assume that there *are* outstanding
2818 * dependencies, and force their cleanup before our instruction.
2820 if (block
->start() == scan_inst
) {
2821 for (int i
= 0; i
< write_len
; i
++) {
2823 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
2824 first_write_grf
+ i
);
2829 /* We insert our reads as late as possible on the assumption that any
2830 * instruction but a MOV that might have left us an outstanding
2831 * dependency has more latency than a MOV.
2833 if (scan_inst
->dst
.file
== GRF
) {
2834 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2835 int reg
= scan_inst
->dst
.reg
+ i
;
2837 if (reg
>= first_write_grf
&&
2838 reg
< first_write_grf
+ write_len
&&
2839 needs_dep
[reg
- first_write_grf
]) {
2840 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
2841 needs_dep
[reg
- first_write_grf
] = false;
2842 if (scan_inst
->exec_size
== 16)
2843 needs_dep
[reg
- first_write_grf
+ 1] = false;
2848 /* Clear the flag for registers that actually got read (as expected). */
2849 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2851 /* Continue the loop only if we haven't resolved all the dependencies */
2853 for (i
= 0; i
< write_len
; i
++) {
2863 * Implements this workaround for the original 965:
2865 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2866 * used as a destination register until after it has been sourced by an
2867 * instruction with a different destination register.
2870 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
2872 int write_len
= inst
->regs_written
;
2873 int first_write_grf
= inst
->dst
.reg
;
2874 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2875 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2877 memset(needs_dep
, false, sizeof(needs_dep
));
2878 memset(needs_dep
, true, write_len
);
2879 /* Walk forwards looking for writes to registers we're writing which aren't
2880 * read before being written.
2882 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2883 /* If we hit control flow, force resolve all remaining dependencies. */
2884 if (block
->end() == scan_inst
) {
2885 for (int i
= 0; i
< write_len
; i
++) {
2887 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
2888 first_write_grf
+ i
);
2893 /* Clear the flag for registers that actually got read (as expected). */
2894 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2896 /* We insert our reads as late as possible since they're reading the
2897 * result of a SEND, which has massive latency.
2899 if (scan_inst
->dst
.file
== GRF
&&
2900 scan_inst
->dst
.reg
>= first_write_grf
&&
2901 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
2902 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
2903 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
2904 scan_inst
->dst
.reg
);
2905 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
2908 /* Continue the loop only if we haven't resolved all the dependencies */
2910 for (i
= 0; i
< write_len
; i
++) {
2920 fs_visitor::insert_gen4_send_dependency_workarounds()
2922 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
2925 bool progress
= false;
2927 /* Note that we're done with register allocation, so GRF fs_regs always
2928 * have a .reg_offset of 0.
2931 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2932 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
2933 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
2934 insert_gen4_post_send_dependency_workarounds(block
, inst
);
2940 invalidate_live_intervals();
2944 * Turns the generic expression-style uniform pull constant load instruction
2945 * into a hardware-specific series of instructions for loading a pull
2948 * The expression style allows the CSE pass before this to optimize out
2949 * repeated loads from the same offset, and gives the pre-register-allocation
2950 * scheduling full flexibility, while the conversion to native instructions
2951 * allows the post-register-allocation scheduler the best information
2954 * Note that execution masking for setting up pull constant loads is special:
2955 * the channels that need to be written are unrelated to the current execution
2956 * mask, since a later instruction will use one of the result channels as a
2957 * source operand for all 8 or 16 of its channels.
2960 fs_visitor::lower_uniform_pull_constant_loads()
2962 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2963 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
2966 if (devinfo
->gen
>= 7) {
2967 /* The offset arg before was a vec4-aligned byte offset. We need to
2968 * turn it into a dword offset.
2970 fs_reg const_offset_reg
= inst
->src
[1];
2971 assert(const_offset_reg
.file
== IMM
&&
2972 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
2973 const_offset_reg
.fixed_hw_reg
.dw1
.ud
/= 4;
2975 fs_reg payload
, offset
;
2976 if (devinfo
->gen
>= 9) {
2977 /* We have to use a message header on Skylake to get SIMD4x2
2978 * mode. Reserve space for the register.
2980 offset
= payload
= fs_reg(GRF
, alloc
.allocate(2));
2981 offset
.reg_offset
++;
2984 offset
= payload
= fs_reg(GRF
, alloc
.allocate(1));
2988 /* This is actually going to be a MOV, but since only the first dword
2989 * is accessed, we have a special opcode to do just that one. Note
2990 * that this needs to be an operation that will be considered a def
2991 * by live variable analysis, or register allocation will explode.
2993 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
2994 8, offset
, const_offset_reg
);
2995 setup
->force_writemask_all
= true;
2997 setup
->ir
= inst
->ir
;
2998 setup
->annotation
= inst
->annotation
;
2999 inst
->insert_before(block
, setup
);
3001 /* Similarly, this will only populate the first 4 channels of the
3002 * result register (since we only use smear values from 0-3), but we
3003 * don't tell the optimizer.
3005 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3006 inst
->src
[1] = payload
;
3007 inst
->base_mrf
= -1;
3009 invalidate_live_intervals();
3011 /* Before register allocation, we didn't tell the scheduler about the
3012 * MRF we use. We know it's safe to use this MRF because nothing
3013 * else does except for register spill/unspill, which generates and
3014 * uses its MRF within a single IR instruction.
3016 inst
->base_mrf
= 14;
3023 fs_visitor::lower_load_payload()
3025 bool progress
= false;
3027 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3028 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3031 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== GRF
);
3032 assert(inst
->saturate
== false);
3033 fs_reg dst
= inst
->dst
;
3035 /* Get rid of COMPR4. We'll add it back in if we need it */
3036 if (dst
.file
== MRF
)
3037 dst
.reg
= dst
.reg
& ~BRW_MRF_COMPR4
;
3039 const fs_builder
ibld(this, block
, inst
);
3040 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3042 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3043 if (inst
->src
[i
].file
!= BAD_FILE
) {
3044 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3045 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3046 hbld
.MOV(mov_dst
, mov_src
);
3048 dst
= offset(dst
, hbld
, 1);
3051 if (inst
->dst
.file
== MRF
&& (inst
->dst
.reg
& BRW_MRF_COMPR4
) &&
3052 inst
->exec_size
> 8) {
3053 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3054 * a straightforward copy. Instead, the result of the
3055 * LOAD_PAYLOAD is treated as interleaved and the first four
3056 * non-header sources are unpacked as:
3067 * This is used for gen <= 5 fb writes.
3069 assert(inst
->exec_size
== 16);
3070 assert(inst
->header_size
+ 4 <= inst
->sources
);
3071 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3072 if (inst
->src
[i
].file
!= BAD_FILE
) {
3073 if (devinfo
->has_compr4
) {
3074 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3075 compr4_dst
.reg
|= BRW_MRF_COMPR4
;
3076 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3078 /* Platform doesn't have COMPR4. We have to fake it */
3079 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3080 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3082 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3089 /* The loop above only ever incremented us through the first set
3090 * of 4 registers. However, thanks to the magic of COMPR4, we
3091 * actually wrote to the first 8 registers, so we need to take
3092 * that into account now.
3096 /* The COMPR4 code took care of the first 4 sources. We'll let
3097 * the regular path handle any remaining sources. Yes, we are
3098 * modifying the instruction but we're about to delete it so
3099 * this really doesn't hurt anything.
3101 inst
->header_size
+= 4;
3104 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3105 if (inst
->src
[i
].file
!= BAD_FILE
)
3106 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3107 dst
= offset(dst
, ibld
, 1);
3110 inst
->remove(block
);
3115 invalidate_live_intervals();
3121 fs_visitor::lower_integer_multiplication()
3123 bool progress
= false;
3125 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3126 const fs_builder
ibld(this, block
, inst
);
3128 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3129 if (inst
->dst
.is_accumulator() ||
3130 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3131 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3134 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3135 * operation directly, but CHV/BXT cannot.
3137 if (devinfo
->gen
>= 8 &&
3138 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3141 if (inst
->src
[1].file
== IMM
&&
3142 inst
->src
[1].fixed_hw_reg
.dw1
.ud
< (1 << 16)) {
3143 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3144 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3147 * If multiplying by an immediate value that fits in 16-bits, do a
3148 * single MUL instruction with that value in the proper location.
3150 if (devinfo
->gen
< 7) {
3151 fs_reg
imm(GRF
, alloc
.allocate(dispatch_width
/ 8),
3153 ibld
.MOV(imm
, inst
->src
[1]);
3154 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3156 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3159 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3160 * do 32-bit integer multiplication in one instruction, but instead
3161 * must do a sequence (which actually calculates a 64-bit result):
3163 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3164 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3165 * mov(8) g2<1>D acc0<8,8,1>D
3167 * But on Gen > 6, the ability to use second accumulator register
3168 * (acc1) for non-float data types was removed, preventing a simple
3169 * implementation in SIMD16. A 16-channel result can be calculated by
3170 * executing the three instructions twice in SIMD8, once with quarter
3171 * control of 1Q for the first eight channels and again with 2Q for
3172 * the second eight channels.
3174 * Which accumulator register is implicitly accessed (by AccWrEnable
3175 * for instance) is determined by the quarter control. Unfortunately
3176 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3177 * implicit accumulator access by an instruction with 2Q will access
3178 * acc1 regardless of whether the data type is usable in acc1.
3180 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3181 * integer data types.
3183 * Since we only want the low 32-bits of the result, we can do two
3184 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3185 * adjust the high result and add them (like the mach is doing):
3187 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3188 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3189 * shl(8) g9<1>D g8<8,8,1>D 16D
3190 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3192 * We avoid the shl instruction by realizing that we only want to add
3193 * the low 16-bits of the "high" result to the high 16-bits of the
3194 * "low" result and using proper regioning on the add:
3196 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3197 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3198 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3200 * Since it does not use the (single) accumulator register, we can
3201 * schedule multi-component multiplications much better.
3204 fs_reg orig_dst
= inst
->dst
;
3205 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3206 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
3209 fs_reg low
= inst
->dst
;
3210 fs_reg
high(GRF
, alloc
.allocate(dispatch_width
/ 8),
3213 if (devinfo
->gen
>= 7) {
3214 fs_reg src1_0_w
= inst
->src
[1];
3215 fs_reg src1_1_w
= inst
->src
[1];
3217 if (inst
->src
[1].file
== IMM
) {
3218 src1_0_w
.fixed_hw_reg
.dw1
.ud
&= 0xffff;
3219 src1_1_w
.fixed_hw_reg
.dw1
.ud
>>= 16;
3221 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3222 if (src1_0_w
.stride
!= 0) {
3223 assert(src1_0_w
.stride
== 1);
3224 src1_0_w
.stride
= 2;
3227 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3228 if (src1_1_w
.stride
!= 0) {
3229 assert(src1_1_w
.stride
== 1);
3230 src1_1_w
.stride
= 2;
3232 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3234 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3235 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3237 fs_reg src0_0_w
= inst
->src
[0];
3238 fs_reg src0_1_w
= inst
->src
[0];
3240 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3241 if (src0_0_w
.stride
!= 0) {
3242 assert(src0_0_w
.stride
== 1);
3243 src0_0_w
.stride
= 2;
3246 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3247 if (src0_1_w
.stride
!= 0) {
3248 assert(src0_1_w
.stride
== 1);
3249 src0_1_w
.stride
= 2;
3251 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3253 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3254 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3257 fs_reg dst
= inst
->dst
;
3258 dst
.type
= BRW_REGISTER_TYPE_UW
;
3259 dst
.subreg_offset
= 2;
3262 high
.type
= BRW_REGISTER_TYPE_UW
;
3265 low
.type
= BRW_REGISTER_TYPE_UW
;
3266 low
.subreg_offset
= 2;
3269 ibld
.ADD(dst
, low
, high
);
3271 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3272 set_condmod(inst
->conditional_mod
,
3273 ibld
.MOV(orig_dst
, inst
->dst
));
3277 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3278 /* Should have been lowered to 8-wide. */
3279 assert(inst
->exec_size
<= 8);
3280 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3282 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3283 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3285 if (devinfo
->gen
>= 8) {
3286 /* Until Gen8, integer multiplies read 32-bits from one source,
3287 * and 16-bits from the other, and relying on the MACH instruction
3288 * to generate the high bits of the result.
3290 * On Gen8, the multiply instruction does a full 32x32-bit
3291 * multiply, but in order to do a 64-bit multiply we can simulate
3292 * the previous behavior and then use a MACH instruction.
3294 * FINISHME: Don't use source modifiers on src1.
3296 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3297 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3298 mul
->src
[1].type
= (type_is_signed(mul
->src
[1].type
) ?
3299 BRW_REGISTER_TYPE_W
: BRW_REGISTER_TYPE_UW
);
3300 mul
->src
[1].stride
*= 2;
3302 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3303 inst
->force_sechalf
) {
3304 /* Among other things the quarter control bits influence which
3305 * accumulator register is used by the hardware for instructions
3306 * that access the accumulator implicitly (e.g. MACH). A
3307 * second-half instruction would normally map to acc1, which
3308 * doesn't exist on Gen7 and up (the hardware does emulate it for
3309 * floating-point instructions *only* by taking advantage of the
3310 * extra precision of acc0 not normally used for floating point
3313 * HSW and up are careful enough not to try to access an
3314 * accumulator register that doesn't exist, but on earlier Gen7
3315 * hardware we need to make sure that the quarter control bits are
3316 * zero to avoid non-deterministic behaviour and emit an extra MOV
3317 * to get the result masked correctly according to the current
3320 mach
->force_sechalf
= false;
3321 mach
->force_writemask_all
= true;
3322 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3323 ibld
.MOV(inst
->dst
, mach
->dst
);
3329 inst
->remove(block
);
3334 invalidate_live_intervals();
3340 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3341 fs_reg
*dst
, fs_reg color
, unsigned components
)
3343 if (key
->clamp_fragment_color
) {
3344 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3345 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3347 for (unsigned i
= 0; i
< components
; i
++)
3349 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3354 for (unsigned i
= 0; i
< components
; i
++)
3355 dst
[i
] = offset(color
, bld
, i
);
3359 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3360 const brw_wm_prog_data
*prog_data
,
3361 const brw_wm_prog_key
*key
,
3362 const fs_visitor::thread_payload
&payload
)
3364 assert(inst
->src
[6].file
== IMM
);
3365 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3366 const fs_reg
&color0
= inst
->src
[0];
3367 const fs_reg
&color1
= inst
->src
[1];
3368 const fs_reg
&src0_alpha
= inst
->src
[2];
3369 const fs_reg
&src_depth
= inst
->src
[3];
3370 const fs_reg
&dst_depth
= inst
->src
[4];
3371 fs_reg sample_mask
= inst
->src
[5];
3372 const unsigned components
= inst
->src
[6].fixed_hw_reg
.dw1
.ud
;
3374 /* We can potentially have a message length of up to 15, so we have to set
3375 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3378 int header_size
= 2, payload_header_size
;
3379 unsigned length
= 0;
3381 /* From the Sandy Bridge PRM, volume 4, page 198:
3383 * "Dispatched Pixel Enables. One bit per pixel indicating
3384 * which pixels were originally enabled when the thread was
3385 * dispatched. This field is only required for the end-of-
3386 * thread message and on all dual-source messages."
3388 if (devinfo
->gen
>= 6 &&
3389 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3390 color1
.file
== BAD_FILE
&&
3391 key
->nr_color_regions
== 1) {
3395 if (header_size
!= 0) {
3396 assert(header_size
== 2);
3397 /* Allocate 2 registers for a header */
3401 if (payload
.aa_dest_stencil_reg
) {
3402 sources
[length
] = fs_reg(GRF
, bld
.shader
->alloc
.allocate(1));
3403 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3404 .MOV(sources
[length
],
3405 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3409 if (prog_data
->uses_omask
) {
3410 sources
[length
] = fs_reg(GRF
, bld
.shader
->alloc
.allocate(1),
3411 BRW_REGISTER_TYPE_UD
);
3413 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3414 * relevant. Since it's unsigned single words one vgrf is always
3415 * 16-wide, but only the lower or higher 8 channels will be used by the
3416 * hardware when doing a SIMD8 write depending on whether we have
3417 * selected the subspans for the first or second half respectively.
3419 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3420 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3421 sample_mask
.stride
*= 2;
3423 bld
.exec_all().annotate("FB write oMask")
3424 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3425 inst
->force_sechalf
),
3430 payload_header_size
= length
;
3432 if (src0_alpha
.file
!= BAD_FILE
) {
3433 /* FIXME: This is being passed at the wrong location in the payload and
3434 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3435 * It's supposed to be immediately before oMask but there seems to be no
3436 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3437 * requires header sources to form a contiguous segment at the beginning
3438 * of the message and src0_alpha has per-channel semantics.
3440 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3444 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3447 if (color1
.file
!= BAD_FILE
) {
3448 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3452 if (src_depth
.file
!= BAD_FILE
) {
3453 sources
[length
] = src_depth
;
3457 if (dst_depth
.file
!= BAD_FILE
) {
3458 sources
[length
] = dst_depth
;
3463 if (devinfo
->gen
>= 7) {
3464 /* Send from the GRF */
3465 fs_reg payload
= fs_reg(GRF
, -1, BRW_REGISTER_TYPE_F
);
3466 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3467 payload
.reg
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3468 load
->dst
= payload
;
3470 inst
->src
[0] = payload
;
3471 inst
->resize_sources(1);
3472 inst
->base_mrf
= -1;
3474 /* Send from the MRF */
3475 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3476 sources
, length
, payload_header_size
);
3478 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3479 * will do this for us if we just give it a COMPR4 destination.
3481 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3482 load
->dst
.reg
|= BRW_MRF_COMPR4
;
3484 inst
->resize_sources(0);
3488 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3489 inst
->mlen
= load
->regs_written
;
3490 inst
->header_size
= header_size
;
3494 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3495 const fs_reg
&coordinate
,
3496 const fs_reg
&shadow_c
,
3497 const fs_reg
&lod
, const fs_reg
&lod2
,
3498 const fs_reg
&sampler
,
3499 unsigned coord_components
,
3500 unsigned grad_components
)
3502 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3503 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3504 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3505 fs_reg msg_end
= msg_begin
;
3508 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3510 for (unsigned i
= 0; i
< coord_components
; i
++)
3511 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3512 offset(coordinate
, bld
, i
));
3514 msg_end
= offset(msg_end
, bld
, coord_components
);
3516 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3517 * require all three components to be present and zero if they are unused.
3519 if (coord_components
> 0 &&
3520 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3521 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3522 for (unsigned i
= coord_components
; i
< 3; i
++)
3523 bld
.MOV(offset(msg_end
, bld
, i
), fs_reg(0.0f
));
3525 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3528 if (op
== SHADER_OPCODE_TXD
) {
3529 /* TXD unsupported in SIMD16 mode. */
3530 assert(bld
.dispatch_width() == 8);
3532 /* the slots for u and v are always present, but r is optional */
3533 if (coord_components
< 2)
3534 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3537 * dPdx = dudx, dvdx, drdx
3538 * dPdy = dudy, dvdy, drdy
3540 * 1-arg: Does not exist.
3542 * 2-arg: dudx dvdx dudy dvdy
3543 * dPdx.x dPdx.y dPdy.x dPdy.y
3546 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3547 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3548 * m5 m6 m7 m8 m9 m10
3550 for (unsigned i
= 0; i
< grad_components
; i
++)
3551 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3553 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3555 for (unsigned i
= 0; i
< grad_components
; i
++)
3556 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3558 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3562 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3563 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3565 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3566 bld
.dispatch_width() == 16);
3568 const brw_reg_type type
=
3569 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3570 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3571 bld
.MOV(retype(msg_end
, type
), lod
);
3572 msg_end
= offset(msg_end
, bld
, 1);
3575 if (shadow_c
.file
!= BAD_FILE
) {
3576 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3577 /* There's no plain shadow compare message, so we use shadow
3578 * compare with a bias of 0.0.
3580 bld
.MOV(msg_end
, fs_reg(0.0f
));
3581 msg_end
= offset(msg_end
, bld
, 1);
3584 bld
.MOV(msg_end
, shadow_c
);
3585 msg_end
= offset(msg_end
, bld
, 1);
3589 inst
->src
[0] = reg_undef
;
3590 inst
->src
[1] = sampler
;
3591 inst
->resize_sources(2);
3592 inst
->base_mrf
= msg_begin
.reg
;
3593 inst
->mlen
= msg_end
.reg
- msg_begin
.reg
;
3594 inst
->header_size
= 1;
3598 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3600 const fs_reg
&shadow_c
,
3601 fs_reg lod
, fs_reg lod2
,
3602 const fs_reg
&sample_index
,
3603 const fs_reg
&sampler
,
3604 const fs_reg
&offset_value
,
3605 unsigned coord_components
,
3606 unsigned grad_components
)
3608 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3609 fs_reg msg_coords
= message
;
3610 unsigned header_size
= 0;
3612 if (offset_value
.file
!= BAD_FILE
) {
3613 /* The offsets set up by the visitor are in the m1 header, so we can't
3620 for (unsigned i
= 0; i
< coord_components
; i
++) {
3621 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3622 coordinate
= offset(coordinate
, bld
, 1);
3624 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3625 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3627 if (shadow_c
.file
!= BAD_FILE
) {
3628 fs_reg msg_shadow
= msg_lod
;
3629 bld
.MOV(msg_shadow
, shadow_c
);
3630 msg_lod
= offset(msg_shadow
, bld
, 1);
3635 case SHADER_OPCODE_TXL
:
3637 bld
.MOV(msg_lod
, lod
);
3638 msg_end
= offset(msg_lod
, bld
, 1);
3640 case SHADER_OPCODE_TXD
:
3643 * dPdx = dudx, dvdx, drdx
3644 * dPdy = dudy, dvdy, drdy
3646 * Load up these values:
3647 * - dudx dudy dvdx dvdy drdx drdy
3648 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3651 for (unsigned i
= 0; i
< grad_components
; i
++) {
3652 bld
.MOV(msg_end
, lod
);
3653 lod
= offset(lod
, bld
, 1);
3654 msg_end
= offset(msg_end
, bld
, 1);
3656 bld
.MOV(msg_end
, lod2
);
3657 lod2
= offset(lod2
, bld
, 1);
3658 msg_end
= offset(msg_end
, bld
, 1);
3661 case SHADER_OPCODE_TXS
:
3662 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3663 bld
.MOV(msg_lod
, lod
);
3664 msg_end
= offset(msg_lod
, bld
, 1);
3666 case SHADER_OPCODE_TXF
:
3667 msg_lod
= offset(msg_coords
, bld
, 3);
3668 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3669 msg_end
= offset(msg_lod
, bld
, 1);
3671 case SHADER_OPCODE_TXF_CMS
:
3672 msg_lod
= offset(msg_coords
, bld
, 3);
3674 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u));
3676 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3677 msg_end
= offset(msg_lod
, bld
, 2);
3684 inst
->src
[0] = reg_undef
;
3685 inst
->src
[1] = sampler
;
3686 inst
->resize_sources(2);
3687 inst
->base_mrf
= message
.reg
;
3688 inst
->mlen
= msg_end
.reg
- message
.reg
;
3689 inst
->header_size
= header_size
;
3691 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3692 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3696 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3698 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3701 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
3705 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3707 const fs_reg
&shadow_c
,
3708 fs_reg lod
, fs_reg lod2
,
3709 const fs_reg
&sample_index
,
3710 const fs_reg
&mcs
, const fs_reg
&sampler
,
3711 fs_reg offset_value
,
3712 unsigned coord_components
,
3713 unsigned grad_components
)
3715 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3716 int reg_width
= bld
.dispatch_width() / 8;
3717 unsigned header_size
= 0, length
= 0;
3718 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3719 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3720 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3722 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3723 offset_value
.file
!= BAD_FILE
||
3724 is_high_sampler(devinfo
, sampler
)) {
3725 /* For general texture offsets (no txf workaround), we need a header to
3726 * put them in. Note that we're only reserving space for it in the
3727 * message payload as it will be initialized implicitly by the
3730 * TG4 needs to place its channel select in the header, for interaction
3731 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3732 * larger sampler numbers we need to offset the Sampler State Pointer in
3736 sources
[0] = fs_reg();
3740 if (shadow_c
.file
!= BAD_FILE
) {
3741 bld
.MOV(sources
[length
], shadow_c
);
3745 bool coordinate_done
= false;
3747 /* The sampler can only meaningfully compute LOD for fragment shader
3748 * messages. For all other stages, we change the opcode to TXL and
3749 * hardcode the LOD to 0.
3751 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3752 op
== SHADER_OPCODE_TEX
) {
3753 op
= SHADER_OPCODE_TXL
;
3757 /* Set up the LOD info */
3760 case SHADER_OPCODE_TXL
:
3761 bld
.MOV(sources
[length
], lod
);
3764 case SHADER_OPCODE_TXD
:
3765 /* TXD should have been lowered in SIMD16 mode. */
3766 assert(bld
.dispatch_width() == 8);
3768 /* Load dPdx and the coordinate together:
3769 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3771 for (unsigned i
= 0; i
< coord_components
; i
++) {
3772 bld
.MOV(sources
[length
], coordinate
);
3773 coordinate
= offset(coordinate
, bld
, 1);
3776 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3777 * only derivatives for (u, v, r).
3779 if (i
< grad_components
) {
3780 bld
.MOV(sources
[length
], lod
);
3781 lod
= offset(lod
, bld
, 1);
3784 bld
.MOV(sources
[length
], lod2
);
3785 lod2
= offset(lod2
, bld
, 1);
3790 coordinate_done
= true;
3792 case SHADER_OPCODE_TXS
:
3793 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
3796 case SHADER_OPCODE_TXF
:
3797 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
3798 * On Gen9 they are u, v, lod, r
3800 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3801 coordinate
= offset(coordinate
, bld
, 1);
3804 if (devinfo
->gen
>= 9) {
3805 if (coord_components
>= 2) {
3806 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3807 coordinate
= offset(coordinate
, bld
, 1);
3812 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
3815 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
3816 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3817 coordinate
= offset(coordinate
, bld
, 1);
3821 coordinate_done
= true;
3823 case SHADER_OPCODE_TXF_CMS
:
3824 case SHADER_OPCODE_TXF_UMS
:
3825 case SHADER_OPCODE_TXF_MCS
:
3826 if (op
== SHADER_OPCODE_TXF_UMS
|| op
== SHADER_OPCODE_TXF_CMS
) {
3827 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
3831 if (op
== SHADER_OPCODE_TXF_CMS
) {
3832 /* Data from the multisample control surface. */
3833 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
3837 /* There is no offsetting for this message; just copy in the integer
3838 * texture coordinates.
3840 for (unsigned i
= 0; i
< coord_components
; i
++) {
3841 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3842 coordinate
= offset(coordinate
, bld
, 1);
3846 coordinate_done
= true;
3848 case SHADER_OPCODE_TG4_OFFSET
:
3849 /* gather4_po_c should have been lowered in SIMD16 mode. */
3850 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
3852 /* More crazy intermixing */
3853 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
3854 bld
.MOV(sources
[length
], coordinate
);
3855 coordinate
= offset(coordinate
, bld
, 1);
3859 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
3860 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
3861 offset_value
= offset(offset_value
, bld
, 1);
3865 if (coord_components
== 3) { /* r if present */
3866 bld
.MOV(sources
[length
], coordinate
);
3867 coordinate
= offset(coordinate
, bld
, 1);
3871 coordinate_done
= true;
3877 /* Set up the coordinate (except for cases where it was done above) */
3878 if (!coordinate_done
) {
3879 for (unsigned i
= 0; i
< coord_components
; i
++) {
3880 bld
.MOV(sources
[length
], coordinate
);
3881 coordinate
= offset(coordinate
, bld
, 1);
3888 mlen
= length
* reg_width
- header_size
;
3890 mlen
= length
* reg_width
;
3892 const fs_reg src_payload
= fs_reg(GRF
, bld
.shader
->alloc
.allocate(mlen
),
3893 BRW_REGISTER_TYPE_F
);
3894 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
3896 /* Generate the SEND. */
3898 inst
->src
[0] = src_payload
;
3899 inst
->src
[1] = sampler
;
3900 inst
->resize_sources(2);
3901 inst
->base_mrf
= -1;
3903 inst
->header_size
= header_size
;
3905 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3906 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3910 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
3912 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3913 const fs_reg
&coordinate
= inst
->src
[0];
3914 const fs_reg
&shadow_c
= inst
->src
[1];
3915 const fs_reg
&lod
= inst
->src
[2];
3916 const fs_reg
&lod2
= inst
->src
[3];
3917 const fs_reg
&sample_index
= inst
->src
[4];
3918 const fs_reg
&mcs
= inst
->src
[5];
3919 const fs_reg
&sampler
= inst
->src
[6];
3920 const fs_reg
&offset_value
= inst
->src
[7];
3921 assert(inst
->src
[8].file
== IMM
&& inst
->src
[9].file
== IMM
);
3922 const unsigned coord_components
= inst
->src
[8].fixed_hw_reg
.dw1
.ud
;
3923 const unsigned grad_components
= inst
->src
[9].fixed_hw_reg
.dw1
.ud
;
3925 if (devinfo
->gen
>= 7) {
3926 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
3927 shadow_c
, lod
, lod2
, sample_index
,
3928 mcs
, sampler
, offset_value
,
3929 coord_components
, grad_components
);
3930 } else if (devinfo
->gen
>= 5) {
3931 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
3932 shadow_c
, lod
, lod2
, sample_index
,
3933 sampler
, offset_value
,
3934 coord_components
, grad_components
);
3936 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
3937 shadow_c
, lod
, lod2
, sampler
,
3938 coord_components
, grad_components
);
3943 * Initialize the header present in some typed and untyped surface
3947 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
3949 fs_builder ubld
= bld
.exec_all().group(8, 0);
3950 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3951 ubld
.MOV(dst
, fs_reg(0));
3952 ubld
.MOV(component(dst
, 7), sample_mask
);
3957 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3958 const fs_reg
&sample_mask
)
3960 /* Get the logical send arguments. */
3961 const fs_reg
&addr
= inst
->src
[0];
3962 const fs_reg
&src
= inst
->src
[1];
3963 const fs_reg
&surface
= inst
->src
[2];
3964 const UNUSED fs_reg
&dims
= inst
->src
[3];
3965 const fs_reg
&arg
= inst
->src
[4];
3967 /* Calculate the total number of components of the payload. */
3968 const unsigned addr_sz
= inst
->components_read(0);
3969 const unsigned src_sz
= inst
->components_read(1);
3970 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
3971 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
3973 /* Allocate space for the payload. */
3974 fs_reg
*const components
= new fs_reg
[sz
];
3975 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
3978 /* Construct the payload. */
3980 components
[n
++] = emit_surface_header(bld
, sample_mask
);
3982 for (unsigned i
= 0; i
< addr_sz
; i
++)
3983 components
[n
++] = offset(addr
, bld
, i
);
3985 for (unsigned i
= 0; i
< src_sz
; i
++)
3986 components
[n
++] = offset(src
, bld
, i
);
3988 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
3990 /* Update the original instruction. */
3992 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
3993 inst
->header_size
= header_sz
;
3995 inst
->src
[0] = payload
;
3996 inst
->src
[1] = surface
;
3998 inst
->resize_sources(3);
4000 delete[] components
;
4004 fs_visitor::lower_logical_sends()
4006 bool progress
= false;
4008 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4009 const fs_builder
ibld(this, block
, inst
);
4011 switch (inst
->opcode
) {
4012 case FS_OPCODE_FB_WRITE_LOGICAL
:
4013 assert(stage
== MESA_SHADER_FRAGMENT
);
4014 lower_fb_write_logical_send(ibld
, inst
,
4015 (const brw_wm_prog_data
*)prog_data
,
4016 (const brw_wm_prog_key
*)key
,
4020 case SHADER_OPCODE_TEX_LOGICAL
:
4021 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4024 case SHADER_OPCODE_TXD_LOGICAL
:
4025 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4028 case SHADER_OPCODE_TXF_LOGICAL
:
4029 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4032 case SHADER_OPCODE_TXL_LOGICAL
:
4033 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4036 case SHADER_OPCODE_TXS_LOGICAL
:
4037 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4040 case FS_OPCODE_TXB_LOGICAL
:
4041 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4044 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4045 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4048 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4049 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4052 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4053 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4056 case SHADER_OPCODE_LOD_LOGICAL
:
4057 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4060 case SHADER_OPCODE_TG4_LOGICAL
:
4061 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4064 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4065 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4068 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4069 lower_surface_logical_send(ibld
, inst
,
4070 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4074 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4075 lower_surface_logical_send(ibld
, inst
,
4076 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4077 ibld
.sample_mask_reg());
4080 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4081 lower_surface_logical_send(ibld
, inst
,
4082 SHADER_OPCODE_UNTYPED_ATOMIC
,
4083 ibld
.sample_mask_reg());
4086 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4087 lower_surface_logical_send(ibld
, inst
,
4088 SHADER_OPCODE_TYPED_SURFACE_READ
,
4092 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4093 lower_surface_logical_send(ibld
, inst
,
4094 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4095 ibld
.sample_mask_reg());
4098 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4099 lower_surface_logical_send(ibld
, inst
,
4100 SHADER_OPCODE_TYPED_ATOMIC
,
4101 ibld
.sample_mask_reg());
4112 invalidate_live_intervals();
4118 * Get the closest native SIMD width supported by the hardware for instruction
4119 * \p inst. The instruction will be left untouched by
4120 * fs_visitor::lower_simd_width() if the returned value is equal to the
4121 * original execution size.
4124 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4125 const fs_inst
*inst
)
4127 switch (inst
->opcode
) {
4128 case BRW_OPCODE_MOV
:
4129 case BRW_OPCODE_SEL
:
4130 case BRW_OPCODE_NOT
:
4131 case BRW_OPCODE_AND
:
4133 case BRW_OPCODE_XOR
:
4134 case BRW_OPCODE_SHR
:
4135 case BRW_OPCODE_SHL
:
4136 case BRW_OPCODE_ASR
:
4137 case BRW_OPCODE_CMP
:
4138 case BRW_OPCODE_CMPN
:
4139 case BRW_OPCODE_CSEL
:
4140 case BRW_OPCODE_F32TO16
:
4141 case BRW_OPCODE_F16TO32
:
4142 case BRW_OPCODE_BFREV
:
4143 case BRW_OPCODE_BFE
:
4144 case BRW_OPCODE_BFI1
:
4145 case BRW_OPCODE_BFI2
:
4146 case BRW_OPCODE_ADD
:
4147 case BRW_OPCODE_MUL
:
4148 case BRW_OPCODE_AVG
:
4149 case BRW_OPCODE_FRC
:
4150 case BRW_OPCODE_RNDU
:
4151 case BRW_OPCODE_RNDD
:
4152 case BRW_OPCODE_RNDE
:
4153 case BRW_OPCODE_RNDZ
:
4154 case BRW_OPCODE_LZD
:
4155 case BRW_OPCODE_FBH
:
4156 case BRW_OPCODE_FBL
:
4157 case BRW_OPCODE_CBIT
:
4158 case BRW_OPCODE_SAD2
:
4159 case BRW_OPCODE_MAD
:
4160 case BRW_OPCODE_LRP
:
4161 case SHADER_OPCODE_RCP
:
4162 case SHADER_OPCODE_RSQ
:
4163 case SHADER_OPCODE_SQRT
:
4164 case SHADER_OPCODE_EXP2
:
4165 case SHADER_OPCODE_LOG2
:
4166 case SHADER_OPCODE_POW
:
4167 case SHADER_OPCODE_INT_QUOTIENT
:
4168 case SHADER_OPCODE_INT_REMAINDER
:
4169 case SHADER_OPCODE_SIN
:
4170 case SHADER_OPCODE_COS
: {
4171 /* According to the PRMs:
4172 * "A. In Direct Addressing mode, a source cannot span more than 2
4173 * adjacent GRF registers.
4174 * B. A destination cannot span more than 2 adjacent GRF registers."
4176 * Look for the source or destination with the largest register region
4177 * which is the one that is going to limit the overal execution size of
4178 * the instruction due to this rule.
4180 unsigned reg_count
= inst
->regs_written
;
4182 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4183 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4185 /* Calculate the maximum execution size of the instruction based on the
4186 * factor by which it goes over the hardware limit of 2 GRFs.
4188 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4190 case SHADER_OPCODE_MULH
:
4191 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4192 * is 8-wide on Gen7+.
4194 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4196 case FS_OPCODE_FB_WRITE_LOGICAL
:
4197 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4200 assert(devinfo
->gen
!= 6 || inst
->src
[3].file
== BAD_FILE
||
4201 inst
->exec_size
== 8);
4202 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4203 return (inst
->src
[1].file
!= BAD_FILE
? 8 : inst
->exec_size
);
4205 case SHADER_OPCODE_TXD_LOGICAL
:
4206 /* TXD is unsupported in SIMD16 mode. */
4209 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4210 /* gather4_po_c is unsupported in SIMD16 mode. */
4211 const fs_reg
&shadow_c
= inst
->src
[1];
4212 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4214 case SHADER_OPCODE_TXL_LOGICAL
:
4215 case FS_OPCODE_TXB_LOGICAL
: {
4216 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4217 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4218 * mode because the message exceeds the maximum length of 11.
4220 const fs_reg
&shadow_c
= inst
->src
[1];
4221 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4223 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4226 return inst
->exec_size
;
4228 case SHADER_OPCODE_TXF_LOGICAL
:
4229 case SHADER_OPCODE_TXS_LOGICAL
:
4230 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4231 * messages. Use SIMD16 instead.
4233 if (devinfo
->gen
== 4)
4236 return inst
->exec_size
;
4238 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4239 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4240 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4244 return inst
->exec_size
;
4249 * The \p rows array of registers represents a \p num_rows by \p num_columns
4250 * matrix in row-major order, write it in column-major order into the register
4251 * passed as destination. \p stride gives the separation between matrix
4252 * elements in the input in fs_builder::dispatch_width() units.
4255 emit_transpose(const fs_builder
&bld
,
4256 const fs_reg
&dst
, const fs_reg
*rows
,
4257 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4259 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4261 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4262 for (unsigned j
= 0; j
< num_rows
; ++j
)
4263 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4266 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4268 delete[] components
;
4272 fs_visitor::lower_simd_width()
4274 bool progress
= false;
4276 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4277 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4279 if (lower_width
!= inst
->exec_size
) {
4280 /* Builder matching the original instruction. We may also need to
4281 * emit an instruction of width larger than the original, set the
4282 * execution size of the builder to the highest of both for now so
4283 * we're sure that both cases can be handled.
4285 const fs_builder ibld
= bld
.at(block
, inst
)
4286 .exec_all(inst
->force_writemask_all
)
4287 .group(MAX2(inst
->exec_size
, lower_width
),
4288 inst
->force_sechalf
);
4290 /* Split the copies in chunks of the execution width of either the
4291 * original or the lowered instruction, whichever is lower.
4293 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4294 const unsigned n
= inst
->exec_size
/ copy_width
;
4295 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4296 inst
->dst
.component_size(inst
->exec_size
);
4299 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4300 !inst
->writes_accumulator
&& !inst
->mlen
);
4302 for (unsigned i
= 0; i
< n
; i
++) {
4303 /* Emit a copy of the original instruction with the lowered width.
4304 * If the EOT flag was set throw it away except for the last
4305 * instruction to avoid killing the thread prematurely.
4307 fs_inst split_inst
= *inst
;
4308 split_inst
.exec_size
= lower_width
;
4309 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4311 /* Select the correct channel enables for the i-th group, then
4312 * transform the sources and destination and emit the lowered
4315 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4317 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4318 if (inst
->src
[j
].file
!= BAD_FILE
&&
4319 !is_uniform(inst
->src
[j
])) {
4320 /* Get the i-th copy_width-wide chunk of the source. */
4321 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4322 const unsigned src_size
= inst
->components_read(j
);
4324 /* Use a trivial transposition to copy one every n
4325 * copy_width-wide components of the register into a
4326 * temporary passed as source to the lowered instruction.
4328 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4329 emit_transpose(lbld
.group(copy_width
, 0),
4330 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4334 if (inst
->regs_written
) {
4335 /* Allocate enough space to hold the result of the lowered
4336 * instruction and fix up the number of registers written.
4338 split_inst
.dst
= dsts
[i
] =
4339 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4340 split_inst
.regs_written
=
4341 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4345 lbld
.emit(split_inst
);
4348 if (inst
->regs_written
) {
4349 /* Distance between useful channels in the temporaries, skipping
4350 * garbage if the lowered instruction is wider than the original.
4352 const unsigned m
= lower_width
/ copy_width
;
4354 /* Interleave the components of the result from the lowered
4355 * instructions. We need to set exec_all() when copying more than
4356 * one half per component, because LOAD_PAYLOAD (in terms of which
4357 * emit_transpose is implemented) can only use the same channel
4358 * enable signals for all of its non-header sources.
4360 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4361 .group(copy_width
, 0),
4362 inst
->dst
, dsts
, n
, dst_size
, m
);
4365 inst
->remove(block
);
4371 invalidate_live_intervals();
4377 fs_visitor::dump_instructions()
4379 dump_instructions(NULL
);
4383 fs_visitor::dump_instructions(const char *name
)
4385 FILE *file
= stderr
;
4386 if (name
&& geteuid() != 0) {
4387 file
= fopen(name
, "w");
4393 calculate_register_pressure();
4394 int ip
= 0, max_pressure
= 0;
4395 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4396 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4397 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4398 dump_instruction(inst
, file
);
4401 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4404 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4405 fprintf(file
, "%4d: ", ip
++);
4406 dump_instruction(inst
, file
);
4410 if (file
!= stderr
) {
4416 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4418 dump_instruction(be_inst
, stderr
);
4422 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4424 fs_inst
*inst
= (fs_inst
*)be_inst
;
4426 if (inst
->predicate
) {
4427 fprintf(file
, "(%cf0.%d) ",
4428 inst
->predicate_inverse
? '-' : '+',
4432 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4434 fprintf(file
, ".sat");
4435 if (inst
->conditional_mod
) {
4436 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4437 if (!inst
->predicate
&&
4438 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4439 inst
->opcode
!= BRW_OPCODE_IF
&&
4440 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4441 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4444 fprintf(file
, "(%d) ", inst
->exec_size
);
4447 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4450 switch (inst
->dst
.file
) {
4452 fprintf(file
, "vgrf%d", inst
->dst
.reg
);
4453 if (alloc
.sizes
[inst
->dst
.reg
] != inst
->regs_written
||
4454 inst
->dst
.subreg_offset
)
4455 fprintf(file
, "+%d.%d",
4456 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4459 fprintf(file
, "m%d", inst
->dst
.reg
);
4462 fprintf(file
, "(null)");
4465 fprintf(file
, "***u%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
4468 fprintf(file
, "***attr%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
4471 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
4472 switch (inst
->dst
.fixed_hw_reg
.nr
) {
4474 fprintf(file
, "null");
4476 case BRW_ARF_ADDRESS
:
4477 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
4479 case BRW_ARF_ACCUMULATOR
:
4480 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
4483 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
4484 inst
->dst
.fixed_hw_reg
.subnr
);
4487 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
4488 inst
->dst
.fixed_hw_reg
.subnr
);
4492 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
4494 if (inst
->dst
.fixed_hw_reg
.subnr
)
4495 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
4498 fprintf(file
, "???");
4501 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4503 for (int i
= 0; i
< inst
->sources
; i
++) {
4504 if (inst
->src
[i
].negate
)
4506 if (inst
->src
[i
].abs
)
4508 switch (inst
->src
[i
].file
) {
4510 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
4511 if (alloc
.sizes
[inst
->src
[i
].reg
] != (unsigned)inst
->regs_read(i
) ||
4512 inst
->src
[i
].subreg_offset
)
4513 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4514 inst
->src
[i
].subreg_offset
);
4517 fprintf(file
, "***m%d***", inst
->src
[i
].reg
);
4520 fprintf(file
, "attr%d+%d", inst
->src
[i
].reg
, inst
->src
[i
].reg_offset
);
4523 fprintf(file
, "u%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
4524 if (inst
->src
[i
].reladdr
) {
4525 fprintf(file
, "+reladdr");
4526 } else if (inst
->src
[i
].subreg_offset
) {
4527 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4528 inst
->src
[i
].subreg_offset
);
4532 fprintf(file
, "(null)");
4535 switch (inst
->src
[i
].type
) {
4536 case BRW_REGISTER_TYPE_F
:
4537 fprintf(file
, "%ff", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
4539 case BRW_REGISTER_TYPE_W
:
4540 case BRW_REGISTER_TYPE_D
:
4541 fprintf(file
, "%dd", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
4543 case BRW_REGISTER_TYPE_UW
:
4544 case BRW_REGISTER_TYPE_UD
:
4545 fprintf(file
, "%uu", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
4547 case BRW_REGISTER_TYPE_VF
:
4548 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4549 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
4550 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
4551 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
4552 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
4555 fprintf(file
, "???");
4560 if (inst
->src
[i
].fixed_hw_reg
.negate
)
4562 if (inst
->src
[i
].fixed_hw_reg
.abs
)
4564 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
4565 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
4567 fprintf(file
, "null");
4569 case BRW_ARF_ADDRESS
:
4570 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4572 case BRW_ARF_ACCUMULATOR
:
4573 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4576 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
4577 inst
->src
[i
].fixed_hw_reg
.subnr
);
4580 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
4581 inst
->src
[i
].fixed_hw_reg
.subnr
);
4585 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
4587 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
4588 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4589 if (inst
->src
[i
].fixed_hw_reg
.abs
)
4593 fprintf(file
, "???");
4596 if (inst
->src
[i
].abs
)
4599 if (inst
->src
[i
].file
!= IMM
) {
4600 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4603 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4604 fprintf(file
, ", ");
4609 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4610 if (inst
->force_sechalf
)
4611 fprintf(file
, "2ndhalf ");
4613 fprintf(file
, "1sthalf ");
4616 fprintf(file
, "\n");
4620 * Possibly returns an instruction that set up @param reg.
4622 * Sometimes we want to take the result of some expression/variable
4623 * dereference tree and rewrite the instruction generating the result
4624 * of the tree. When processing the tree, we know that the
4625 * instructions generated are all writing temporaries that are dead
4626 * outside of this tree. So, if we have some instructions that write
4627 * a temporary, we're free to point that temp write somewhere else.
4629 * Note that this doesn't guarantee that the instruction generated
4630 * only reg -- it might be the size=4 destination of a texture instruction.
4633 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4638 end
->is_partial_write() ||
4640 !reg
.equals(end
->dst
)) {
4648 fs_visitor::setup_payload_gen6()
4651 (prog
->InputsRead
& (1 << VARYING_SLOT_POS
)) != 0;
4652 unsigned barycentric_interp_modes
=
4653 (stage
== MESA_SHADER_FRAGMENT
) ?
4654 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4656 assert(devinfo
->gen
>= 6);
4658 /* R0-1: masks, pixel X/Y coordinates. */
4659 payload
.num_regs
= 2;
4660 /* R2: only for 32-pixel dispatch.*/
4662 /* R3-26: barycentric interpolation coordinates. These appear in the
4663 * same order that they appear in the brw_wm_barycentric_interp_mode
4664 * enum. Each set of coordinates occupies 2 registers if dispatch width
4665 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4666 * appear if they were enabled using the "Barycentric Interpolation
4667 * Mode" bits in WM_STATE.
4669 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4670 if (barycentric_interp_modes
& (1 << i
)) {
4671 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4672 payload
.num_regs
+= 2;
4673 if (dispatch_width
== 16) {
4674 payload
.num_regs
+= 2;
4679 /* R27: interpolated depth if uses source depth */
4681 payload
.source_depth_reg
= payload
.num_regs
;
4683 if (dispatch_width
== 16) {
4684 /* R28: interpolated depth if not SIMD8. */
4688 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4690 payload
.source_w_reg
= payload
.num_regs
;
4692 if (dispatch_width
== 16) {
4693 /* R30: interpolated W if not SIMD8. */
4698 if (stage
== MESA_SHADER_FRAGMENT
) {
4699 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4700 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4701 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4702 /* R31: MSAA position offsets. */
4703 if (prog_data
->uses_pos_offset
) {
4704 payload
.sample_pos_reg
= payload
.num_regs
;
4709 /* R32: MSAA input coverage mask */
4710 if (prog
->SystemValuesRead
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
4711 assert(devinfo
->gen
>= 7);
4712 payload
.sample_mask_in_reg
= payload
.num_regs
;
4714 if (dispatch_width
== 16) {
4715 /* R33: input coverage mask if not SIMD8. */
4720 /* R34-: bary for 32-pixel. */
4721 /* R58-59: interp W for 32-pixel. */
4723 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4724 source_depth_to_render_target
= true;
4729 fs_visitor::setup_vs_payload()
4731 /* R0: thread header, R1: urb handles */
4732 payload
.num_regs
= 2;
4736 fs_visitor::setup_cs_payload()
4738 assert(devinfo
->gen
>= 7);
4740 payload
.num_regs
= 1;
4742 if (prog
->SystemValuesRead
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
4743 const unsigned local_id_dwords
=
4744 brw_cs_prog_local_id_payload_dwords(prog
, dispatch_width
);
4745 assert((local_id_dwords
& 0x7) == 0);
4746 const unsigned local_id_regs
= local_id_dwords
/ 8;
4747 payload
.local_invocation_id_reg
= payload
.num_regs
;
4748 payload
.num_regs
+= local_id_regs
;
4753 fs_visitor::assign_fs_binding_table_offsets()
4755 assert(stage
== MESA_SHADER_FRAGMENT
);
4756 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4757 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4758 uint32_t next_binding_table_offset
= 0;
4760 /* If there are no color regions, we still perform an FB write to a null
4761 * renderbuffer, which we place at surface index 0.
4763 prog_data
->binding_table
.render_target_start
= next_binding_table_offset
;
4764 next_binding_table_offset
+= MAX2(key
->nr_color_regions
, 1);
4766 assign_common_binding_table_offsets(next_binding_table_offset
);
4770 fs_visitor::assign_cs_binding_table_offsets()
4772 assert(stage
== MESA_SHADER_COMPUTE
);
4773 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
4774 uint32_t next_binding_table_offset
= 0;
4776 /* May not be used if the gl_NumWorkGroups variable is not accessed. */
4777 prog_data
->binding_table
.work_groups_start
= next_binding_table_offset
;
4778 next_binding_table_offset
++;
4780 assign_common_binding_table_offsets(next_binding_table_offset
);
4784 fs_visitor::calculate_register_pressure()
4786 invalidate_live_intervals();
4787 calculate_live_intervals();
4789 unsigned num_instructions
= 0;
4790 foreach_block(block
, cfg
)
4791 num_instructions
+= block
->instructions
.length();
4793 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
4795 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
4796 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
4797 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
4802 fs_visitor::optimize()
4804 /* Start by validating the shader we currently have. */
4807 /* bld is the common builder object pointing at the end of the program we
4808 * used to translate it into i965 IR. For the optimization and lowering
4809 * passes coming next, any code added after the end of the program without
4810 * having explicitly called fs_builder::at() clearly points at a mistake.
4811 * Ideally optimization passes wouldn't be part of the visitor so they
4812 * wouldn't have access to bld at all, but they do, so just in case some
4813 * pass forgets to ask for a location explicitly set it to NULL here to
4814 * make it trip. The dispatch width is initialized to a bogus value to
4815 * make sure that optimizations set the execution controls explicitly to
4816 * match the code they are manipulating instead of relying on the defaults.
4818 bld
= fs_builder(this, 64);
4820 assign_constant_locations();
4821 demote_pull_constants();
4825 split_virtual_grfs();
4828 #define OPT(pass, args...) ({ \
4830 bool this_progress = pass(args); \
4832 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
4833 char filename[64]; \
4834 snprintf(filename, 64, "%s%d-%04d-%02d-%02d-" #pass, \
4835 stage_abbrev, dispatch_width, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
4837 backend_shader::dump_instructions(filename); \
4842 progress = progress || this_progress; \
4846 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
4848 snprintf(filename
, 64, "%s%d-%04d-00-start",
4849 stage_abbrev
, dispatch_width
,
4850 shader_prog
? shader_prog
->Name
: 0);
4852 backend_shader::dump_instructions(filename
);
4855 bool progress
= false;
4859 OPT(lower_simd_width
);
4860 OPT(lower_logical_sends
);
4867 OPT(remove_duplicate_mrf_writes
);
4871 OPT(opt_copy_propagate
);
4872 OPT(opt_peephole_predicated_break
);
4873 OPT(opt_cmod_propagation
);
4874 OPT(dead_code_eliminate
);
4875 OPT(opt_peephole_sel
);
4876 OPT(dead_control_flow_eliminate
, this);
4877 OPT(opt_register_renaming
);
4878 OPT(opt_redundant_discard_jumps
);
4879 OPT(opt_saturate_propagation
);
4880 OPT(opt_zero_samples
);
4881 OPT(register_coalesce
);
4882 OPT(compute_to_mrf
);
4883 OPT(eliminate_find_live_channel
);
4885 OPT(compact_virtual_grfs
);
4890 OPT(opt_sampler_eot
);
4892 if (OPT(lower_load_payload
)) {
4893 split_virtual_grfs();
4894 OPT(register_coalesce
);
4895 OPT(compute_to_mrf
);
4896 OPT(dead_code_eliminate
);
4899 OPT(opt_combine_constants
);
4900 OPT(lower_integer_multiplication
);
4902 lower_uniform_pull_constant_loads();
4908 * Three source instruction must have a GRF/MRF destination register.
4909 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
4912 fs_visitor::fixup_3src_null_dest()
4914 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
4915 if (inst
->is_3src() && inst
->dst
.is_null()) {
4916 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
4923 fs_visitor::allocate_registers()
4925 bool allocated_without_spills
;
4927 static const enum instruction_scheduler_mode pre_modes
[] = {
4929 SCHEDULE_PRE_NON_LIFO
,
4933 /* Try each scheduling heuristic to see if it can successfully register
4934 * allocate without spilling. They should be ordered by decreasing
4935 * performance but increasing likelihood of allocating.
4937 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
4938 schedule_instructions(pre_modes
[i
]);
4941 assign_regs_trivial();
4942 allocated_without_spills
= true;
4944 allocated_without_spills
= assign_regs(false);
4946 if (allocated_without_spills
)
4950 if (!allocated_without_spills
) {
4951 /* We assume that any spilling is worse than just dropping back to
4952 * SIMD8. There's probably actually some intermediate point where
4953 * SIMD16 with a couple of spills is still better.
4955 if (dispatch_width
== 16) {
4956 fail("Failure to register allocate. Reduce number of "
4957 "live scalar values to avoid this.");
4959 compiler
->shader_perf_log(log_data
,
4960 "%s shader triggered register spilling. "
4961 "Try reducing the number of live scalar "
4962 "values to improve performance.\n",
4966 /* Since we're out of heuristics, just go spill registers until we
4967 * get an allocation.
4969 while (!assign_regs(true)) {
4975 /* This must come after all optimization and register allocation, since
4976 * it inserts dead code that happens to have side effects, and it does
4977 * so based on the actual physical registers in use.
4979 insert_gen4_send_dependency_workarounds();
4984 if (!allocated_without_spills
)
4985 schedule_instructions(SCHEDULE_POST
);
4987 if (last_scratch
> 0)
4988 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
4992 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
4994 assert(stage
== MESA_SHADER_VERTEX
);
4996 assign_common_binding_table_offsets(0);
4999 if (shader_time_index
>= 0)
5000 emit_shader_time_begin();
5007 compute_clip_distance(clip_planes
);
5011 if (shader_time_index
>= 0)
5012 emit_shader_time_end();
5018 assign_curb_setup();
5019 assign_vs_urb_setup();
5021 fixup_3src_null_dest();
5022 allocate_registers();
5028 fs_visitor::run_fs(bool do_rep_send
)
5030 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5031 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
5033 assert(stage
== MESA_SHADER_FRAGMENT
);
5035 sanity_param_count
= prog
->Parameters
->NumParameters
;
5037 assign_fs_binding_table_offsets();
5039 if (devinfo
->gen
>= 6)
5040 setup_payload_gen6();
5042 setup_payload_gen4();
5046 } else if (do_rep_send
) {
5047 assert(dispatch_width
== 16);
5048 emit_repclear_shader();
5050 if (shader_time_index
>= 0)
5051 emit_shader_time_begin();
5053 calculate_urb_setup();
5054 if (prog
->InputsRead
> 0) {
5055 if (devinfo
->gen
< 6)
5056 emit_interpolation_setup_gen4();
5058 emit_interpolation_setup_gen6();
5061 /* We handle discards by keeping track of the still-live pixels in f0.1.
5062 * Initialize it with the dispatched pixels.
5064 if (wm_prog_data
->uses_kill
) {
5065 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5066 discard_init
->flag_subreg
= 1;
5069 /* Generate FS IR for main(). (the visitor only descends into
5070 * functions called "main").
5077 if (wm_prog_data
->uses_kill
)
5078 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5080 if (wm_key
->alpha_test_func
)
5085 if (shader_time_index
>= 0)
5086 emit_shader_time_end();
5092 assign_curb_setup();
5095 fixup_3src_null_dest();
5096 allocate_registers();
5102 if (dispatch_width
== 8)
5103 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5105 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5107 /* If any state parameters were appended, then ParameterValues could have
5108 * been realloced, in which case the driver uniform storage set up by
5109 * _mesa_associate_uniform_storage() would point to freed memory. Make
5110 * sure that didn't happen.
5112 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
5118 fs_visitor::run_cs()
5120 assert(stage
== MESA_SHADER_COMPUTE
);
5123 sanity_param_count
= prog
->Parameters
->NumParameters
;
5125 assign_cs_binding_table_offsets();
5129 if (shader_time_index
>= 0)
5130 emit_shader_time_begin();
5137 emit_cs_terminate();
5139 if (shader_time_index
>= 0)
5140 emit_shader_time_end();
5146 assign_curb_setup();
5148 fixup_3src_null_dest();
5149 allocate_registers();
5154 /* If any state parameters were appended, then ParameterValues could have
5155 * been realloced, in which case the driver uniform storage set up by
5156 * _mesa_associate_uniform_storage() would point to freed memory. Make
5157 * sure that didn't happen.
5159 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
5165 brw_wm_fs_emit(struct brw_context
*brw
,
5167 const struct brw_wm_prog_key
*key
,
5168 struct brw_wm_prog_data
*prog_data
,
5169 struct gl_fragment_program
*fp
,
5170 struct gl_shader_program
*prog
,
5171 unsigned *final_assembly_size
)
5173 struct brw_shader
*shader
= NULL
;
5175 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
5177 if (unlikely(INTEL_DEBUG
& DEBUG_WM
))
5178 brw_dump_ir("fragment", prog
, &shader
->base
, &fp
->Base
);
5180 int st_index8
= -1, st_index16
= -1;
5181 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
5182 st_index8
= brw_get_shader_time_index(brw
, prog
, &fp
->Base
, ST_FS8
);
5183 st_index16
= brw_get_shader_time_index(brw
, prog
, &fp
->Base
, ST_FS16
);
5186 /* Now the main event: Visit the shader IR and generate our FS IR for it.
5188 fs_visitor
v(brw
->intelScreen
->compiler
, brw
,
5189 mem_ctx
, MESA_SHADER_FRAGMENT
, key
, &prog_data
->base
,
5190 prog
, &fp
->Base
, 8, st_index8
);
5191 if (!v
.run_fs(false /* do_rep_send */)) {
5193 prog
->LinkStatus
= false;
5194 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
5197 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
5203 cfg_t
*simd16_cfg
= NULL
;
5204 fs_visitor
v2(brw
->intelScreen
->compiler
, brw
,
5205 mem_ctx
, MESA_SHADER_FRAGMENT
, key
, &prog_data
->base
,
5206 prog
, &fp
->Base
, 16, st_index16
);
5207 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || brw
->use_rep_send
)) {
5208 if (!v
.simd16_unsupported
) {
5209 /* Try a SIMD16 compile */
5210 v2
.import_uniforms(&v
);
5211 if (!v2
.run_fs(brw
->use_rep_send
)) {
5212 perf_debug("SIMD16 shader failed to compile: %s", v2
.fail_msg
);
5214 simd16_cfg
= v2
.cfg
;
5220 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || brw
->no_simd8
;
5221 if ((no_simd8
|| brw
->gen
< 5) && simd16_cfg
) {
5223 prog_data
->no_8
= true;
5226 prog_data
->no_8
= false;
5229 fs_generator
g(brw
->intelScreen
->compiler
, brw
,
5230 mem_ctx
, (void *) key
, &prog_data
->base
,
5231 &fp
->Base
, v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
5233 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5236 name
= ralloc_asprintf(mem_ctx
, "%s fragment shader %d",
5237 prog
->Label
? prog
->Label
: "unnamed",
5240 name
= ralloc_asprintf(mem_ctx
, "fragment program %d", fp
->Base
.Id
);
5242 g
.enable_debug(name
);
5246 g
.generate_code(simd8_cfg
, 8);
5248 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5250 return g
.get_assembly(final_assembly_size
);
5254 fs_visitor::emit_cs_local_invocation_id_setup()
5256 assert(stage
== MESA_SHADER_COMPUTE
);
5258 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5260 struct brw_reg src
=
5261 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
5262 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
5264 src
.nr
+= dispatch_width
/ 8;
5265 bld
.MOV(offset(*reg
, bld
, 1), src
);
5266 src
.nr
+= dispatch_width
/ 8;
5267 bld
.MOV(offset(*reg
, bld
, 2), src
);
5273 fs_visitor::emit_cs_work_group_id_setup()
5275 assert(stage
== MESA_SHADER_COMPUTE
);
5277 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5279 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
5280 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
5281 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
5283 bld
.MOV(*reg
, r0_1
);
5284 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
5285 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
5291 brw_cs_emit(struct brw_context
*brw
,
5293 const struct brw_cs_prog_key
*key
,
5294 struct brw_cs_prog_data
*prog_data
,
5295 struct gl_compute_program
*cp
,
5296 struct gl_shader_program
*prog
,
5297 unsigned *final_assembly_size
)
5299 struct brw_shader
*shader
=
5300 (struct brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_COMPUTE
];
5302 if (unlikely(INTEL_DEBUG
& DEBUG_CS
))
5303 brw_dump_ir("compute", prog
, &shader
->base
, &cp
->Base
);
5305 prog_data
->local_size
[0] = cp
->LocalSize
[0];
5306 prog_data
->local_size
[1] = cp
->LocalSize
[1];
5307 prog_data
->local_size
[2] = cp
->LocalSize
[2];
5308 unsigned local_workgroup_size
=
5309 cp
->LocalSize
[0] * cp
->LocalSize
[1] * cp
->LocalSize
[2];
5312 const char *fail_msg
= NULL
;
5315 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
5316 st_index
= brw_get_shader_time_index(brw
, prog
, &cp
->Base
, ST_CS
);
5318 /* Now the main event: Visit the shader IR and generate our CS IR for it.
5320 fs_visitor
v8(brw
->intelScreen
->compiler
, brw
,
5321 mem_ctx
, MESA_SHADER_COMPUTE
, key
, &prog_data
->base
, prog
,
5322 &cp
->Base
, 8, st_index
);
5324 fail_msg
= v8
.fail_msg
;
5325 } else if (local_workgroup_size
<= 8 * brw
->max_cs_threads
) {
5327 prog_data
->simd_size
= 8;
5330 fs_visitor
v16(brw
->intelScreen
->compiler
, brw
,
5331 mem_ctx
, MESA_SHADER_COMPUTE
, key
, &prog_data
->base
, prog
,
5332 &cp
->Base
, 16, st_index
);
5333 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
5334 !fail_msg
&& !v8
.simd16_unsupported
&&
5335 local_workgroup_size
<= 16 * brw
->max_cs_threads
) {
5336 /* Try a SIMD16 compile */
5337 v16
.import_uniforms(&v8
);
5338 if (!v16
.run_cs()) {
5339 perf_debug("SIMD16 shader failed to compile: %s", v16
.fail_msg
);
5342 "Couldn't generate SIMD16 program and not "
5343 "enough threads for SIMD8";
5347 prog_data
->simd_size
= 16;
5351 if (unlikely(cfg
== NULL
)) {
5353 prog
->LinkStatus
= false;
5354 ralloc_strcat(&prog
->InfoLog
, fail_msg
);
5355 _mesa_problem(NULL
, "Failed to compile compute shader: %s\n",
5360 fs_generator
g(brw
->intelScreen
->compiler
, brw
,
5361 mem_ctx
, (void*) key
, &prog_data
->base
, &cp
->Base
,
5362 v8
.promoted_constants
, v8
.runtime_check_aads_emit
, "CS");
5363 if (INTEL_DEBUG
& DEBUG_CS
) {
5364 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %d",
5365 prog
->Label
? prog
->Label
: "unnamed",
5367 g
.enable_debug(name
);
5370 g
.generate_code(cfg
, prog_data
->simd_size
);
5372 return g
.get_assembly(final_assembly_size
);