2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
33 #include <sys/types.h>
35 #include "main/macros.h"
36 #include "main/shaderobj.h"
37 #include "main/uniforms.h"
38 #include "program/prog_parameter.h"
39 #include "program/prog_print.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
47 #include "brw_shader.h"
49 #include "../glsl/glsl_types.h"
50 #include "../glsl/ir_print_visitor.h"
52 #define MAX_INSTRUCTION (1 << 30)
55 fs_visitor::type_size(const struct glsl_type
*type
)
59 switch (type
->base_type
) {
64 return type
->components();
66 return type_size(type
->fields
.array
) * type
->length
;
67 case GLSL_TYPE_STRUCT
:
69 for (i
= 0; i
< type
->length
; i
++) {
70 size
+= type_size(type
->fields
.structure
[i
].type
);
73 case GLSL_TYPE_SAMPLER
:
74 /* Samplers take up no register space, since they're baked in at
79 assert(!"not reached");
85 fs_visitor::fail(const char *format
, ...)
96 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
98 msg
= ralloc_asprintf(mem_ctx
, "FS compile failed: %s\n", msg
);
100 this->fail_msg
= msg
;
102 if (INTEL_DEBUG
& DEBUG_WM
) {
103 fprintf(stderr
, "%s", msg
);
108 fs_visitor::push_force_uncompressed()
110 force_uncompressed_stack
++;
114 fs_visitor::pop_force_uncompressed()
116 force_uncompressed_stack
--;
117 assert(force_uncompressed_stack
>= 0);
121 fs_visitor::push_force_sechalf()
123 force_sechalf_stack
++;
127 fs_visitor::pop_force_sechalf()
129 force_sechalf_stack
--;
130 assert(force_sechalf_stack
>= 0);
134 * Returns how many MRFs an FS opcode will write over.
136 * Note that this is not the 0 or 1 implied writes in an actual gen
137 * instruction -- the FS opcodes often generate MOVs in addition.
140 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
145 switch (inst
->opcode
) {
153 return 1 * c
->dispatch_width
/ 8;
155 return 2 * c
->dispatch_width
/ 8;
161 case FS_OPCODE_FB_WRITE
:
163 case FS_OPCODE_PULL_CONSTANT_LOAD
:
164 case FS_OPCODE_UNSPILL
:
166 case FS_OPCODE_SPILL
:
169 assert(!"not reached");
175 fs_visitor::virtual_grf_alloc(int size
)
177 if (virtual_grf_array_size
<= virtual_grf_next
) {
178 if (virtual_grf_array_size
== 0)
179 virtual_grf_array_size
= 16;
181 virtual_grf_array_size
*= 2;
182 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
183 virtual_grf_array_size
);
185 /* This slot is always unused. */
186 virtual_grf_sizes
[0] = 0;
188 virtual_grf_sizes
[virtual_grf_next
] = size
;
189 return virtual_grf_next
++;
192 /** Fixed HW reg constructor. */
193 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
197 this->hw_reg
= hw_reg
;
198 this->type
= BRW_REGISTER_TYPE_F
;
201 /** Fixed HW reg constructor. */
202 fs_reg::fs_reg(enum register_file file
, int hw_reg
, uint32_t type
)
206 this->hw_reg
= hw_reg
;
210 /** Automatic reg constructor. */
211 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
216 this->reg
= v
->virtual_grf_alloc(v
->type_size(type
));
217 this->reg_offset
= 0;
218 this->type
= brw_type_for_base_type(type
);
222 fs_visitor::variable_storage(ir_variable
*var
)
224 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
228 import_uniforms_callback(const void *key
,
232 struct hash_table
*dst_ht
= (struct hash_table
*)closure
;
233 const fs_reg
*reg
= (const fs_reg
*)data
;
235 if (reg
->file
!= UNIFORM
)
238 hash_table_insert(dst_ht
, data
, key
);
241 /* For 16-wide, we need to follow from the uniform setup of 8-wide dispatch.
242 * This brings in those uniform definitions
245 fs_visitor::import_uniforms(struct hash_table
*src_variable_ht
)
247 hash_table_call_foreach(src_variable_ht
,
248 import_uniforms_callback
,
252 /* Our support for uniforms is piggy-backed on the struct
253 * gl_fragment_program, because that's where the values actually
254 * get stored, rather than in some global gl_shader_program uniform
258 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
260 unsigned int offset
= 0;
262 if (type
->is_matrix()) {
263 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
264 type
->vector_elements
,
267 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
268 offset
+= setup_uniform_values(loc
+ offset
, column
);
274 switch (type
->base_type
) {
275 case GLSL_TYPE_FLOAT
:
279 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
280 unsigned int param
= c
->prog_data
.nr_params
++;
282 assert(param
< ARRAY_SIZE(c
->prog_data
.param
));
284 switch (type
->base_type
) {
285 case GLSL_TYPE_FLOAT
:
286 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
289 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2U
;
292 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2I
;
295 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2B
;
298 assert(!"not reached");
299 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
302 this->param_index
[param
] = loc
;
303 this->param_offset
[param
] = i
;
307 case GLSL_TYPE_STRUCT
:
308 for (unsigned int i
= 0; i
< type
->length
; i
++) {
309 offset
+= setup_uniform_values(loc
+ offset
,
310 type
->fields
.structure
[i
].type
);
314 case GLSL_TYPE_ARRAY
:
315 for (unsigned int i
= 0; i
< type
->length
; i
++) {
316 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
320 case GLSL_TYPE_SAMPLER
:
321 /* The sampler takes up a slot, but we don't use any values from it. */
325 assert(!"not reached");
331 /* Our support for builtin uniforms is even scarier than non-builtin.
332 * It sits on top of the PROG_STATE_VAR parameters that are
333 * automatically updated from GL context state.
336 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
338 const ir_state_slot
*const slots
= ir
->state_slots
;
339 assert(ir
->state_slots
!= NULL
);
341 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
342 /* This state reference has already been setup by ir_to_mesa, but we'll
343 * get the same index back here.
345 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
346 (gl_state_index
*)slots
[i
].tokens
);
348 /* Add each of the unique swizzles of the element as a parameter.
349 * This'll end up matching the expected layout of the
350 * array/matrix/structure we're trying to fill in.
353 for (unsigned int j
= 0; j
< 4; j
++) {
354 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
355 if (swiz
== last_swiz
)
359 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
361 this->param_index
[c
->prog_data
.nr_params
] = index
;
362 this->param_offset
[c
->prog_data
.nr_params
] = swiz
;
363 c
->prog_data
.nr_params
++;
369 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
371 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
373 bool flip
= !ir
->origin_upper_left
^ c
->key
.render_to_fbo
;
376 if (ir
->pixel_center_integer
) {
377 emit(BRW_OPCODE_MOV
, wpos
, this->pixel_x
);
379 emit(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
));
384 if (!flip
&& ir
->pixel_center_integer
) {
385 emit(BRW_OPCODE_MOV
, wpos
, this->pixel_y
);
387 fs_reg pixel_y
= this->pixel_y
;
388 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
391 pixel_y
.negate
= true;
392 offset
+= c
->key
.drawable_height
- 1.0;
395 emit(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
));
400 if (intel
->gen
>= 6) {
401 emit(BRW_OPCODE_MOV
, wpos
,
402 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0)));
404 emit(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
405 interp_reg(FRAG_ATTRIB_WPOS
, 2));
409 /* gl_FragCoord.w: Already set up in emit_interpolation */
410 emit(BRW_OPCODE_MOV
, wpos
, this->wpos_w
);
416 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
418 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
419 /* Interpolation is always in floating point regs. */
420 reg
->type
= BRW_REGISTER_TYPE_F
;
423 unsigned int array_elements
;
424 const glsl_type
*type
;
426 if (ir
->type
->is_array()) {
427 array_elements
= ir
->type
->length
;
428 if (array_elements
== 0) {
429 fail("dereferenced array '%s' has length 0\n", ir
->name
);
431 type
= ir
->type
->fields
.array
;
437 int location
= ir
->location
;
438 for (unsigned int i
= 0; i
< array_elements
; i
++) {
439 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
440 if (urb_setup
[location
] == -1) {
441 /* If there's no incoming setup data for this slot, don't
442 * emit interpolation for it.
444 attr
.reg_offset
+= type
->vector_elements
;
450 location
== FRAG_ATTRIB_COL0
|| location
== FRAG_ATTRIB_COL1
;
452 if (c
->key
.flat_shade
&& is_gl_Color
) {
453 /* Constant interpolation (flat shading) case. The SF has
454 * handed us defined values in only the constant offset
455 * field of the setup reg.
457 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
458 struct brw_reg interp
= interp_reg(location
, k
);
459 interp
= suboffset(interp
, 3);
460 emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
464 /* Perspective interpolation case. */
465 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
466 struct brw_reg interp
= interp_reg(location
, k
);
467 emit(FS_OPCODE_LINTERP
, attr
,
468 this->delta_x
, this->delta_y
, fs_reg(interp
));
472 if (intel
->gen
< 6) {
473 attr
.reg_offset
-= type
->vector_elements
;
474 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
475 emit(BRW_OPCODE_MUL
, attr
, attr
, this->pixel_w
);
488 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
490 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
492 /* The frontfacing comes in as a bit in the thread payload. */
493 if (intel
->gen
>= 6) {
494 emit(BRW_OPCODE_ASR
, *reg
,
495 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
497 emit(BRW_OPCODE_NOT
, *reg
, *reg
);
498 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1));
500 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
501 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
504 fs_inst
*inst
= emit(BRW_OPCODE_CMP
, *reg
,
507 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
508 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u));
515 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src
)
527 assert(!"not reached: bad math opcode");
531 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
532 * might be able to do better by doing execsize = 1 math and then
533 * expanding that result out, but we would need to be careful with
536 * The hardware ignores source modifiers (negate and abs) on math
537 * instructions, so we also move to a temp to set those up.
539 if (intel
->gen
>= 6 && (src
.file
== UNIFORM
||
542 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
543 emit(BRW_OPCODE_MOV
, expanded
, src
);
547 fs_inst
*inst
= emit(opcode
, dst
, src
);
549 if (intel
->gen
< 6) {
551 inst
->mlen
= c
->dispatch_width
/ 8;
558 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
563 assert(opcode
== FS_OPCODE_POW
);
565 if (intel
->gen
>= 6) {
566 /* Can't do hstride == 0 args to gen6 math, so expand it out.
568 * The hardware ignores source modifiers (negate and abs) on math
569 * instructions, so we also move to a temp to set those up.
571 if (src0
.file
== UNIFORM
|| src0
.abs
|| src0
.negate
) {
572 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
573 emit(BRW_OPCODE_MOV
, expanded
, src0
);
577 if (src1
.file
== UNIFORM
|| src1
.abs
|| src1
.negate
) {
578 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
579 emit(BRW_OPCODE_MOV
, expanded
, src1
);
583 inst
= emit(opcode
, dst
, src0
, src1
);
585 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1), src1
);
586 inst
= emit(opcode
, dst
, src0
, reg_null_f
);
588 inst
->base_mrf
= base_mrf
;
589 inst
->mlen
= 2 * c
->dispatch_width
/ 8;
595 * To be called after the last _mesa_add_state_reference() call, to
596 * set up prog_data.param[] for assign_curb_setup() and
597 * setup_pull_constants().
600 fs_visitor::setup_paramvalues_refs()
602 if (c
->dispatch_width
!= 8)
605 /* Set up the pointers to ParamValues now that that array is finalized. */
606 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
607 c
->prog_data
.param
[i
] =
608 fp
->Base
.Parameters
->ParameterValues
[this->param_index
[i
]] +
609 this->param_offset
[i
];
614 fs_visitor::assign_curb_setup()
616 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
617 if (c
->dispatch_width
== 8) {
618 c
->prog_data
.first_curbe_grf
= c
->nr_payload_regs
;
620 c
->prog_data
.first_curbe_grf_16
= c
->nr_payload_regs
;
623 /* Map the offsets in the UNIFORM file to fixed HW regs. */
624 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
625 fs_inst
*inst
= (fs_inst
*)iter
.get();
627 for (unsigned int i
= 0; i
< 3; i
++) {
628 if (inst
->src
[i
].file
== UNIFORM
) {
629 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
630 struct brw_reg brw_reg
= brw_vec1_grf(c
->nr_payload_regs
+
634 inst
->src
[i
].file
= FIXED_HW_REG
;
635 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
642 fs_visitor::calculate_urb_setup()
644 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
649 /* Figure out where each of the incoming setup attributes lands. */
650 if (intel
->gen
>= 6) {
651 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
652 if (fp
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
653 urb_setup
[i
] = urb_next
++;
657 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
658 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
659 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
662 if (i
>= VERT_RESULT_VAR0
)
663 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
664 else if (i
<= VERT_RESULT_TEX7
)
670 urb_setup
[fp_index
] = urb_next
++;
675 /* Each attribute is 4 setup channels, each of which is half a reg. */
676 c
->prog_data
.urb_read_length
= urb_next
* 2;
680 fs_visitor::assign_urb_setup()
682 int urb_start
= c
->nr_payload_regs
+ c
->prog_data
.curb_read_length
;
684 /* Offset all the urb_setup[] index by the actual position of the
685 * setup regs, now that the location of the constants has been chosen.
687 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
688 fs_inst
*inst
= (fs_inst
*)iter
.get();
690 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
691 assert(inst
->src
[2].file
== FIXED_HW_REG
);
692 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
695 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
696 assert(inst
->src
[0].file
== FIXED_HW_REG
);
697 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
701 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
705 * Split large virtual GRFs into separate components if we can.
707 * This is mostly duplicated with what brw_fs_vector_splitting does,
708 * but that's really conservative because it's afraid of doing
709 * splitting that doesn't result in real progress after the rest of
710 * the optimization phases, which would cause infinite looping in
711 * optimization. We can do it once here, safely. This also has the
712 * opportunity to split interpolated values, or maybe even uniforms,
713 * which we don't have at the IR level.
715 * We want to split, because virtual GRFs are what we register
716 * allocate and spill (due to contiguousness requirements for some
717 * instructions), and they're what we naturally generate in the
718 * codegen process, but most virtual GRFs don't actually need to be
719 * contiguous sets of GRFs. If we split, we'll end up with reduced
720 * live intervals and better dead code elimination and coalescing.
723 fs_visitor::split_virtual_grfs()
725 int num_vars
= this->virtual_grf_next
;
726 bool split_grf
[num_vars
];
727 int new_virtual_grf
[num_vars
];
729 /* Try to split anything > 0 sized. */
730 for (int i
= 0; i
< num_vars
; i
++) {
731 if (this->virtual_grf_sizes
[i
] != 1)
734 split_grf
[i
] = false;
738 /* PLN opcodes rely on the delta_xy being contiguous. */
739 split_grf
[this->delta_x
.reg
] = false;
742 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
743 fs_inst
*inst
= (fs_inst
*)iter
.get();
745 /* Texturing produces 4 contiguous registers, so no splitting. */
746 if (inst
->is_tex()) {
747 split_grf
[inst
->dst
.reg
] = false;
751 /* Allocate new space for split regs. Note that the virtual
752 * numbers will be contiguous.
754 for (int i
= 0; i
< num_vars
; i
++) {
756 new_virtual_grf
[i
] = virtual_grf_alloc(1);
757 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
758 int reg
= virtual_grf_alloc(1);
759 assert(reg
== new_virtual_grf
[i
] + j
- 1);
762 this->virtual_grf_sizes
[i
] = 1;
766 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
767 fs_inst
*inst
= (fs_inst
*)iter
.get();
769 if (inst
->dst
.file
== GRF
&&
770 split_grf
[inst
->dst
.reg
] &&
771 inst
->dst
.reg_offset
!= 0) {
772 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
773 inst
->dst
.reg_offset
- 1);
774 inst
->dst
.reg_offset
= 0;
776 for (int i
= 0; i
< 3; i
++) {
777 if (inst
->src
[i
].file
== GRF
&&
778 split_grf
[inst
->src
[i
].reg
] &&
779 inst
->src
[i
].reg_offset
!= 0) {
780 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
781 inst
->src
[i
].reg_offset
- 1);
782 inst
->src
[i
].reg_offset
= 0;
786 this->live_intervals_valid
= false;
790 * Choose accesses from the UNIFORM file to demote to using the pull
793 * We allow a fragment shader to have more than the specified minimum
794 * maximum number of fragment shader uniform components (64). If
795 * there are too many of these, they'd fill up all of register space.
796 * So, this will push some of them out to the pull constant buffer and
797 * update the program to load them.
800 fs_visitor::setup_pull_constants()
802 /* Only allow 16 registers (128 uniform components) as push constants. */
803 unsigned int max_uniform_components
= 16 * 8;
804 if (c
->prog_data
.nr_params
<= max_uniform_components
)
807 if (c
->dispatch_width
== 16) {
808 fail("Pull constants not supported in 16-wide\n");
812 /* Just demote the end of the list. We could probably do better
813 * here, demoting things that are rarely used in the program first.
815 int pull_uniform_base
= max_uniform_components
;
816 int pull_uniform_count
= c
->prog_data
.nr_params
- pull_uniform_base
;
818 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
819 fs_inst
*inst
= (fs_inst
*)iter
.get();
821 for (int i
= 0; i
< 3; i
++) {
822 if (inst
->src
[i
].file
!= UNIFORM
)
825 int uniform_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
826 if (uniform_nr
< pull_uniform_base
)
829 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
830 fs_inst
*pull
= new(mem_ctx
) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD
,
832 pull
->offset
= ((uniform_nr
- pull_uniform_base
) * 4) & ~15;
834 pull
->annotation
= inst
->annotation
;
838 inst
->insert_before(pull
);
840 inst
->src
[i
].file
= GRF
;
841 inst
->src
[i
].reg
= dst
.reg
;
842 inst
->src
[i
].reg_offset
= 0;
843 inst
->src
[i
].smear
= (uniform_nr
- pull_uniform_base
) & 3;
847 for (int i
= 0; i
< pull_uniform_count
; i
++) {
848 c
->prog_data
.pull_param
[i
] = c
->prog_data
.param
[pull_uniform_base
+ i
];
849 c
->prog_data
.pull_param_convert
[i
] =
850 c
->prog_data
.param_convert
[pull_uniform_base
+ i
];
852 c
->prog_data
.nr_params
-= pull_uniform_count
;
853 c
->prog_data
.nr_pull_params
= pull_uniform_count
;
857 fs_visitor::calculate_live_intervals()
859 int num_vars
= this->virtual_grf_next
;
860 int *def
= ralloc_array(mem_ctx
, int, num_vars
);
861 int *use
= ralloc_array(mem_ctx
, int, num_vars
);
865 if (this->live_intervals_valid
)
868 for (int i
= 0; i
< num_vars
; i
++) {
869 def
[i
] = MAX_INSTRUCTION
;
874 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
875 fs_inst
*inst
= (fs_inst
*)iter
.get();
877 if (inst
->opcode
== BRW_OPCODE_DO
) {
878 if (loop_depth
++ == 0)
880 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
883 if (loop_depth
== 0) {
884 /* Patches up the use of vars marked for being live across
887 for (int i
= 0; i
< num_vars
; i
++) {
888 if (use
[i
] == loop_start
) {
894 for (unsigned int i
= 0; i
< 3; i
++) {
895 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
896 int reg
= inst
->src
[i
].reg
;
901 def
[reg
] = MIN2(loop_start
, def
[reg
]);
902 use
[reg
] = loop_start
;
904 /* Nobody else is going to go smash our start to
905 * later in the loop now, because def[reg] now
906 * points before the bb header.
911 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
912 int reg
= inst
->dst
.reg
;
915 def
[reg
] = MIN2(def
[reg
], ip
);
917 def
[reg
] = MIN2(def
[reg
], loop_start
);
925 ralloc_free(this->virtual_grf_def
);
926 ralloc_free(this->virtual_grf_use
);
927 this->virtual_grf_def
= def
;
928 this->virtual_grf_use
= use
;
930 this->live_intervals_valid
= true;
934 * Attempts to move immediate constants into the immediate
935 * constant slot of following instructions.
937 * Immediate constants are a bit tricky -- they have to be in the last
938 * operand slot, you can't do abs/negate on them,
942 fs_visitor::propagate_constants()
944 bool progress
= false;
946 calculate_live_intervals();
948 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
949 fs_inst
*inst
= (fs_inst
*)iter
.get();
951 if (inst
->opcode
!= BRW_OPCODE_MOV
||
953 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
954 inst
->dst
.type
!= inst
->src
[0].type
||
955 (c
->dispatch_width
== 16 &&
956 (inst
->force_uncompressed
|| inst
->force_sechalf
)))
959 /* Don't bother with cases where we should have had the
960 * operation on the constant folded in GLSL already.
965 /* Found a move of a constant to a GRF. Find anything else using the GRF
966 * before it's written, and replace it with the constant if we can.
968 exec_list_iterator scan_iter
= iter
;
970 for (; scan_iter
.has_next(); scan_iter
.next()) {
971 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
973 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
974 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
975 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
976 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
980 for (int i
= 2; i
>= 0; i
--) {
981 if (scan_inst
->src
[i
].file
!= GRF
||
982 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
983 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
986 /* Don't bother with cases where we should have had the
987 * operation on the constant folded in GLSL already.
989 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
992 switch (scan_inst
->opcode
) {
994 scan_inst
->src
[i
] = inst
->src
[0];
1001 scan_inst
->src
[i
] = inst
->src
[0];
1003 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
1004 /* Fit this constant in by commuting the operands */
1005 scan_inst
->src
[0] = scan_inst
->src
[1];
1006 scan_inst
->src
[1] = inst
->src
[0];
1011 case BRW_OPCODE_CMP
:
1013 scan_inst
->src
[i
] = inst
->src
[0];
1015 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
1018 new_cmod
= brw_swap_cmod(scan_inst
->conditional_mod
);
1019 if (new_cmod
!= ~0u) {
1020 /* Fit this constant in by swapping the operands and
1023 scan_inst
->src
[0] = scan_inst
->src
[1];
1024 scan_inst
->src
[1] = inst
->src
[0];
1025 scan_inst
->conditional_mod
= new_cmod
;
1031 case BRW_OPCODE_SEL
:
1033 scan_inst
->src
[i
] = inst
->src
[0];
1035 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
1036 scan_inst
->src
[0] = scan_inst
->src
[1];
1037 scan_inst
->src
[1] = inst
->src
[0];
1039 /* If this was predicated, flipping operands means
1040 * we also need to flip the predicate.
1042 if (scan_inst
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
1043 scan_inst
->predicate_inverse
=
1044 !scan_inst
->predicate_inverse
;
1052 if (scan_inst
->dst
.file
== GRF
&&
1053 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
1054 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
1055 scan_inst
->is_tex())) {
1062 this->live_intervals_valid
= false;
1067 * Must be called after calculate_live_intervales() to remove unused
1068 * writes to registers -- register allocation will fail otherwise
1069 * because something deffed but not used won't be considered to
1070 * interfere with other regs.
1073 fs_visitor::dead_code_eliminate()
1075 bool progress
= false;
1078 calculate_live_intervals();
1080 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1081 fs_inst
*inst
= (fs_inst
*)iter
.get();
1083 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
1092 live_intervals_valid
= false;
1098 fs_visitor::register_coalesce()
1100 bool progress
= false;
1104 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1105 fs_inst
*inst
= (fs_inst
*)iter
.get();
1107 /* Make sure that we dominate the instructions we're going to
1108 * scan for interfering with our coalescing, or we won't have
1109 * scanned enough to see if anything interferes with our
1110 * coalescing. We don't dominate the following instructions if
1111 * we're in a loop or an if block.
1113 switch (inst
->opcode
) {
1117 case BRW_OPCODE_WHILE
:
1123 case BRW_OPCODE_ENDIF
:
1127 if (loop_depth
|| if_depth
)
1130 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1133 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= GRF
||
1134 inst
->dst
.type
!= inst
->src
[0].type
)
1137 bool has_source_modifiers
= inst
->src
[0].abs
|| inst
->src
[0].negate
;
1139 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
1140 * them: check for no writes to either one until the exit of the
1143 bool interfered
= false;
1144 exec_list_iterator scan_iter
= iter
;
1146 for (; scan_iter
.has_next(); scan_iter
.next()) {
1147 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
1149 if (scan_inst
->dst
.file
== GRF
) {
1150 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
1151 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
1152 scan_inst
->is_tex())) {
1156 if (scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1157 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
1158 scan_inst
->is_tex())) {
1164 /* The gen6 MATH instruction can't handle source modifiers, so avoid
1165 * coalescing those for now. We should do something more specific.
1167 if (intel
->gen
>= 6 && scan_inst
->is_math() && has_source_modifiers
) {
1176 /* Rewrite the later usage to point at the source of the move to
1179 for (exec_list_iterator scan_iter
= iter
; scan_iter
.has_next();
1181 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
1183 for (int i
= 0; i
< 3; i
++) {
1184 if (scan_inst
->src
[i
].file
== GRF
&&
1185 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
1186 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
1187 scan_inst
->src
[i
].reg
= inst
->src
[0].reg
;
1188 scan_inst
->src
[i
].reg_offset
= inst
->src
[0].reg_offset
;
1189 scan_inst
->src
[i
].abs
|= inst
->src
[0].abs
;
1190 scan_inst
->src
[i
].negate
^= inst
->src
[0].negate
;
1191 scan_inst
->src
[i
].smear
= inst
->src
[0].smear
;
1201 live_intervals_valid
= false;
1208 fs_visitor::compute_to_mrf()
1210 bool progress
= false;
1213 calculate_live_intervals();
1215 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1216 fs_inst
*inst
= (fs_inst
*)iter
.get();
1221 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1223 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
1224 inst
->dst
.type
!= inst
->src
[0].type
||
1225 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
1228 /* Work out which hardware MRF registers are written by this
1231 int mrf_low
= inst
->dst
.hw_reg
& ~BRW_MRF_COMPR4
;
1233 if (inst
->dst
.hw_reg
& BRW_MRF_COMPR4
) {
1234 mrf_high
= mrf_low
+ 4;
1235 } else if (c
->dispatch_width
== 16 &&
1236 (!inst
->force_uncompressed
&& !inst
->force_sechalf
)) {
1237 mrf_high
= mrf_low
+ 1;
1242 /* Can't compute-to-MRF this GRF if someone else was going to
1245 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
1248 /* Found a move of a GRF to a MRF. Let's see if we can go
1249 * rewrite the thing that made this GRF to write into the MRF.
1252 for (scan_inst
= (fs_inst
*)inst
->prev
;
1253 scan_inst
->prev
!= NULL
;
1254 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
1255 if (scan_inst
->dst
.file
== GRF
&&
1256 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
1257 /* Found the last thing to write our reg we want to turn
1258 * into a compute-to-MRF.
1261 if (scan_inst
->is_tex()) {
1262 /* texturing writes several continuous regs, so we can't
1263 * compute-to-mrf that.
1268 /* If it's predicated, it (probably) didn't populate all
1269 * the channels. We might be able to rewrite everything
1270 * that writes that reg, but it would require smarter
1271 * tracking to delay the rewriting until complete success.
1273 if (scan_inst
->predicated
)
1276 /* If it's half of register setup and not the same half as
1277 * our MOV we're trying to remove, bail for now.
1279 if (scan_inst
->force_uncompressed
!= inst
->force_uncompressed
||
1280 scan_inst
->force_sechalf
!= inst
->force_sechalf
) {
1284 /* SEND instructions can't have MRF as a destination. */
1285 if (scan_inst
->mlen
)
1288 if (intel
->gen
>= 6) {
1289 /* gen6 math instructions must have the destination be
1290 * GRF, so no compute-to-MRF for them.
1292 if (scan_inst
->is_math()) {
1297 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1298 /* Found the creator of our MRF's source value. */
1299 scan_inst
->dst
.file
= MRF
;
1300 scan_inst
->dst
.hw_reg
= inst
->dst
.hw_reg
;
1301 scan_inst
->saturate
|= inst
->saturate
;
1308 /* We don't handle flow control here. Most computation of
1309 * values that end up in MRFs are shortly before the MRF
1312 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
1313 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
1314 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
1315 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
1319 /* You can't read from an MRF, so if someone else reads our
1320 * MRF's source GRF that we wanted to rewrite, that stops us.
1322 bool interfered
= false;
1323 for (int i
= 0; i
< 3; i
++) {
1324 if (scan_inst
->src
[i
].file
== GRF
&&
1325 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
1326 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1333 if (scan_inst
->dst
.file
== MRF
) {
1334 /* If somebody else writes our MRF here, we can't
1335 * compute-to-MRF before that.
1337 int scan_mrf_low
= scan_inst
->dst
.hw_reg
& ~BRW_MRF_COMPR4
;
1340 if (scan_inst
->dst
.hw_reg
& BRW_MRF_COMPR4
) {
1341 scan_mrf_high
= scan_mrf_low
+ 4;
1342 } else if (c
->dispatch_width
== 16 &&
1343 (!scan_inst
->force_uncompressed
&&
1344 !scan_inst
->force_sechalf
)) {
1345 scan_mrf_high
= scan_mrf_low
+ 1;
1347 scan_mrf_high
= scan_mrf_low
;
1350 if (mrf_low
== scan_mrf_low
||
1351 mrf_low
== scan_mrf_high
||
1352 mrf_high
== scan_mrf_low
||
1353 mrf_high
== scan_mrf_high
) {
1358 if (scan_inst
->mlen
> 0) {
1359 /* Found a SEND instruction, which means that there are
1360 * live values in MRFs from base_mrf to base_mrf +
1361 * scan_inst->mlen - 1. Don't go pushing our MRF write up
1364 if (mrf_low
>= scan_inst
->base_mrf
&&
1365 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1368 if (mrf_high
>= scan_inst
->base_mrf
&&
1369 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1380 * Walks through basic blocks, locking for repeated MRF writes and
1381 * removing the later ones.
1384 fs_visitor::remove_duplicate_mrf_writes()
1386 fs_inst
*last_mrf_move
[16];
1387 bool progress
= false;
1389 /* Need to update the MRF tracking for compressed instructions. */
1390 if (c
->dispatch_width
== 16)
1393 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
1395 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1396 fs_inst
*inst
= (fs_inst
*)iter
.get();
1398 switch (inst
->opcode
) {
1400 case BRW_OPCODE_WHILE
:
1402 case BRW_OPCODE_ELSE
:
1403 case BRW_OPCODE_ENDIF
:
1404 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
1410 if (inst
->opcode
== BRW_OPCODE_MOV
&&
1411 inst
->dst
.file
== MRF
) {
1412 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.hw_reg
];
1413 if (prev_inst
&& inst
->equals(prev_inst
)) {
1420 /* Clear out the last-write records for MRFs that were overwritten. */
1421 if (inst
->dst
.file
== MRF
) {
1422 last_mrf_move
[inst
->dst
.hw_reg
] = NULL
;
1425 if (inst
->mlen
> 0) {
1426 /* Found a SEND instruction, which will include two or fewer
1427 * implied MRF writes. We could do better here.
1429 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
1430 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
1434 /* Clear out any MRF move records whose sources got overwritten. */
1435 if (inst
->dst
.file
== GRF
) {
1436 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
1437 if (last_mrf_move
[i
] &&
1438 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
1439 last_mrf_move
[i
] = NULL
;
1444 if (inst
->opcode
== BRW_OPCODE_MOV
&&
1445 inst
->dst
.file
== MRF
&&
1446 inst
->src
[0].file
== GRF
&&
1447 !inst
->predicated
) {
1448 last_mrf_move
[inst
->dst
.hw_reg
] = inst
;
1456 fs_visitor::virtual_grf_interferes(int a
, int b
)
1458 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
1459 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
1461 /* We can't handle dead register writes here, without iterating
1462 * over the whole instruction stream to find every single dead
1463 * write to that register to compare to the live interval of the
1464 * other register. Just assert that dead_code_eliminate() has been
1467 assert((this->virtual_grf_use
[a
] != -1 ||
1468 this->virtual_grf_def
[a
] == MAX_INSTRUCTION
) &&
1469 (this->virtual_grf_use
[b
] != -1 ||
1470 this->virtual_grf_def
[b
] == MAX_INSTRUCTION
));
1472 /* If the register is used to store 16 values of less than float
1473 * size (only the case for pixel_[xy]), then we can't allocate
1474 * another dword-sized thing to that register that would be used in
1475 * the same instruction. This is because when the GPU decodes (for
1478 * (declare (in ) vec4 gl_FragCoord@0x97766a0)
1479 * add(16) g6<1>F g6<8,8,1>UW 0.5F { align1 compr };
1481 * it's actually processed as:
1482 * add(8) g6<1>F g6<8,8,1>UW 0.5F { align1 };
1483 * add(8) g7<1>F g6.8<8,8,1>UW 0.5F { align1 sechalf };
1485 * so our second half values in g6 got overwritten in the first
1488 if (c
->dispatch_width
== 16 && (this->pixel_x
.reg
== a
||
1489 this->pixel_x
.reg
== b
||
1490 this->pixel_y
.reg
== a
||
1491 this->pixel_y
.reg
== b
)) {
1492 return start
<= end
;
1501 uint32_t prog_offset_16
= 0;
1502 uint32_t orig_nr_params
= c
->prog_data
.nr_params
;
1504 brw_wm_payload_setup(brw
, c
);
1506 if (c
->dispatch_width
== 16) {
1507 /* align to 64 byte boundary. */
1508 while ((c
->func
.nr_insn
* sizeof(struct brw_instruction
)) % 64) {
1512 /* Save off the start of this 16-wide program in case we succeed. */
1513 prog_offset_16
= c
->func
.nr_insn
* sizeof(struct brw_instruction
);
1515 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1521 calculate_urb_setup();
1523 emit_interpolation_setup_gen4();
1525 emit_interpolation_setup_gen6();
1527 /* Generate FS IR for main(). (the visitor only descends into
1528 * functions called "main").
1530 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
1531 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1533 this->result
= reg_undef
;
1541 split_virtual_grfs();
1543 setup_paramvalues_refs();
1544 setup_pull_constants();
1550 progress
= remove_duplicate_mrf_writes() || progress
;
1552 progress
= propagate_constants() || progress
;
1553 progress
= register_coalesce() || progress
;
1554 progress
= compute_to_mrf() || progress
;
1555 progress
= dead_code_eliminate() || progress
;
1558 schedule_instructions();
1560 assign_curb_setup();
1564 /* Debug of register spilling: Go spill everything. */
1565 int virtual_grf_count
= virtual_grf_next
;
1566 for (int i
= 1; i
< virtual_grf_count
; i
++) {
1572 assign_regs_trivial();
1574 while (!assign_regs()) {
1580 assert(force_uncompressed_stack
== 0);
1581 assert(force_sechalf_stack
== 0);
1588 if (c
->dispatch_width
== 8) {
1589 c
->prog_data
.reg_blocks
= brw_register_blocks(grf_used
);
1591 c
->prog_data
.reg_blocks_16
= brw_register_blocks(grf_used
);
1592 c
->prog_data
.prog_offset_16
= prog_offset_16
;
1594 /* Make sure we didn't try to sneak in an extra uniform */
1595 assert(orig_nr_params
== c
->prog_data
.nr_params
);
1602 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
,
1603 struct gl_shader_program
*prog
)
1605 struct intel_context
*intel
= &brw
->intel
;
1610 struct brw_shader
*shader
=
1611 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
1615 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
1616 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
1617 _mesa_print_ir(shader
->ir
, NULL
);
1621 /* Now the main event: Visit the shader IR and generate our FS IR for it.
1623 c
->dispatch_width
= 8;
1625 fs_visitor
v(c
, prog
, shader
);
1627 prog
->LinkStatus
= GL_FALSE
;
1628 prog
->InfoLog
= ralloc_strdup(prog
, v
.fail_msg
);
1633 if (intel
->gen
>= 5 && c
->prog_data
.nr_pull_params
== 0) {
1634 c
->dispatch_width
= 16;
1635 fs_visitor
v2(c
, prog
, shader
);
1636 v2
.import_uniforms(v
.variable_ht
);
1640 c
->prog_data
.dispatch_width
= 8;
1646 brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
1648 struct brw_context
*brw
= brw_context(ctx
);
1649 struct brw_wm_prog_key key
;
1650 struct gl_fragment_program
*fp
= prog
->FragmentProgram
;
1651 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
1656 memset(&key
, 0, sizeof(key
));
1659 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
1661 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
1662 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
1664 /* Just assume depth testing. */
1665 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
1666 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
1668 key
.vp_outputs_written
|= BITFIELD64_BIT(FRAG_ATTRIB_WPOS
);
1669 for (int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
1672 if (!(fp
->Base
.InputsRead
& BITFIELD64_BIT(i
)))
1675 key
.proj_attrib_mask
|= 1 << i
;
1677 if (i
<= FRAG_ATTRIB_TEX7
)
1679 else if (i
>= FRAG_ATTRIB_VAR0
)
1680 vp_index
= i
- FRAG_ATTRIB_VAR0
+ VERT_RESULT_VAR0
;
1683 key
.vp_outputs_written
|= BITFIELD64_BIT(vp_index
);
1686 key
.clamp_fragment_color
= true;
1688 for (int i
= 0; i
< BRW_MAX_TEX_UNIT
; i
++) {
1689 if (fp
->Base
.ShadowSamplers
& (1 << i
))
1690 key
.compare_funcs
[i
] = GL_LESS
;
1692 /* FINISHME: depth compares might use (0,0,0,W) for example */
1693 key
.tex_swizzles
[i
] = SWIZZLE_XYZW
;
1696 if (fp
->Base
.InputsRead
& FRAG_BIT_WPOS
) {
1697 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
1698 key
.render_to_fbo
= ctx
->DrawBuffer
->Name
!= 0;
1701 key
.nr_color_regions
= 1;
1703 key
.program_string_id
= bfp
->id
;
1705 uint32_t old_prog_offset
= brw
->wm
.prog_offset
;
1706 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
1708 bool success
= do_wm_prog(brw
, prog
, bfp
, &key
);
1710 brw
->wm
.prog_offset
= old_prog_offset
;
1711 brw
->wm
.prog_data
= old_prog_data
;