2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "../glsl/glsl_types.h"
47 #include "../glsl/ir_optimization.h"
48 #include "../glsl/ir_print_visitor.h"
51 ARF
= BRW_ARCHITECTURE_REGISTER_FILE
,
52 GRF
= BRW_GENERAL_REGISTER_FILE
,
53 MRF
= BRW_MESSAGE_REGISTER_FILE
,
54 IMM
= BRW_IMMEDIATE_VALUE
,
55 FIXED_HW_REG
, /* a struct brw_reg */
56 UNIFORM
, /* prog_data->params[hw_reg] */
61 FS_OPCODE_FB_WRITE
= 256,
79 static int using_new_fs
= -1;
80 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
83 brw_new_shader(GLcontext
*ctx
, GLuint name
, GLuint type
)
85 struct brw_shader
*shader
;
87 shader
= talloc_zero(NULL
, struct brw_shader
);
89 shader
->base
.Type
= type
;
90 shader
->base
.Name
= name
;
91 _mesa_init_shader(ctx
, &shader
->base
);
97 struct gl_shader_program
*
98 brw_new_shader_program(GLcontext
*ctx
, GLuint name
)
100 struct brw_shader_program
*prog
;
101 prog
= talloc_zero(NULL
, struct brw_shader_program
);
103 prog
->base
.Name
= name
;
104 _mesa_init_shader_program(ctx
, &prog
->base
);
110 brw_compile_shader(GLcontext
*ctx
, struct gl_shader
*shader
)
112 if (!_mesa_ir_compile_shader(ctx
, shader
))
119 brw_link_shader(GLcontext
*ctx
, struct gl_shader_program
*prog
)
121 if (using_new_fs
== -1)
122 using_new_fs
= getenv("INTEL_NEW_FS") != NULL
;
124 for (unsigned i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
125 struct brw_shader
*shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
127 if (using_new_fs
&& shader
->base
.Type
== GL_FRAGMENT_SHADER
) {
128 void *mem_ctx
= talloc_new(NULL
);
132 talloc_free(shader
->ir
);
133 shader
->ir
= new(shader
) exec_list
;
134 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
136 do_mat_op_to_vec(shader
->ir
);
137 do_mod_to_fract(shader
->ir
);
138 do_div_to_mul_rcp(shader
->ir
);
139 do_sub_to_add_neg(shader
->ir
);
140 do_explog_to_explog2(shader
->ir
);
141 do_lower_texture_projection(shader
->ir
);
146 brw_do_channel_expressions(shader
->ir
);
147 brw_do_vector_splitting(shader
->ir
);
149 progress
= do_lower_jumps(shader
->ir
, true, true,
150 true, /* main return */
151 false, /* continue */
155 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
157 progress
= lower_noise(shader
->ir
) || progress
;
159 lower_variable_index_to_cond_assign(shader
->ir
,
161 GL_TRUE
, /* output */
163 GL_TRUE
/* uniform */
167 validate_ir_tree(shader
->ir
);
169 reparent_ir(shader
->ir
, shader
->ir
);
170 talloc_free(mem_ctx
);
174 if (!_mesa_ir_link_shader(ctx
, prog
))
181 type_size(const struct glsl_type
*type
)
183 unsigned int size
, i
;
185 switch (type
->base_type
) {
188 case GLSL_TYPE_FLOAT
:
190 return type
->components();
191 case GLSL_TYPE_ARRAY
:
192 return type_size(type
->fields
.array
) * type
->length
;
193 case GLSL_TYPE_STRUCT
:
195 for (i
= 0; i
< type
->length
; i
++) {
196 size
+= type_size(type
->fields
.structure
[i
].type
);
199 case GLSL_TYPE_SAMPLER
:
200 /* Samplers take up no register space, since they're baked in at
205 assert(!"not reached");
212 /* Callers of this talloc-based new need not call delete. It's
213 * easier to just talloc_free 'ctx' (or any of its ancestors). */
214 static void* operator new(size_t size
, void *ctx
)
218 node
= talloc_size(ctx
, size
);
219 assert(node
!= NULL
);
227 this->reg_offset
= 0;
233 /** Generic unset register constructor. */
237 this->file
= BAD_FILE
;
240 /** Immediate value constructor. */
245 this->type
= BRW_REGISTER_TYPE_F
;
249 /** Immediate value constructor. */
254 this->type
= BRW_REGISTER_TYPE_D
;
258 /** Immediate value constructor. */
263 this->type
= BRW_REGISTER_TYPE_UD
;
267 /** Fixed brw_reg Immediate value constructor. */
268 fs_reg(struct brw_reg fixed_hw_reg
)
271 this->file
= FIXED_HW_REG
;
272 this->fixed_hw_reg
= fixed_hw_reg
;
273 this->type
= fixed_hw_reg
.type
;
276 fs_reg(enum register_file file
, int hw_reg
);
277 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
279 /** Register file: ARF, GRF, MRF, IMM. */
280 enum register_file file
;
281 /** virtual register number. 0 = fixed hw reg */
283 /** Offset within the virtual register. */
285 /** HW register number. Generally unset until register allocation. */
287 /** Register type. BRW_REGISTER_TYPE_* */
291 struct brw_reg fixed_hw_reg
;
293 /** Value for file == BRW_IMMMEDIATE_FILE */
301 static const fs_reg reg_undef
;
302 static const fs_reg
reg_null(ARF
, BRW_ARF_NULL
);
304 class fs_inst
: public exec_node
{
306 /* Callers of this talloc-based new need not call delete. It's
307 * easier to just talloc_free 'ctx' (or any of its ancestors). */
308 static void* operator new(size_t size
, void *ctx
)
312 node
= talloc_zero_size(ctx
, size
);
313 assert(node
!= NULL
);
320 this->opcode
= BRW_OPCODE_NOP
;
321 this->saturate
= false;
322 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
323 this->predicated
= false;
327 this->shadow_compare
= false;
338 this->opcode
= opcode
;
341 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
)
344 this->opcode
= opcode
;
349 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
352 this->opcode
= opcode
;
358 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg src2
)
361 this->opcode
= opcode
;
368 int opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
373 int conditional_mod
; /**< BRW_CONDITIONAL_* */
375 int mlen
; /**< SEND message length */
377 int target
; /**< MRT target. */
382 * Annotation for the generated IR. One of the two can be set.
385 const char *annotation
;
389 class fs_visitor
: public ir_visitor
393 fs_visitor(struct brw_wm_compile
*c
, struct brw_shader
*shader
)
398 this->fp
= brw
->fragment_program
;
399 this->intel
= &brw
->intel
;
400 this->ctx
= &intel
->ctx
;
401 this->mem_ctx
= talloc_new(NULL
);
402 this->shader
= shader
;
404 this->variable_ht
= hash_table_ctor(0,
405 hash_table_pointer_hash
,
406 hash_table_pointer_compare
);
408 this->frag_color
= NULL
;
409 this->frag_data
= NULL
;
410 this->frag_depth
= NULL
;
411 this->first_non_payload_grf
= 0;
413 this->current_annotation
= NULL
;
414 this->annotation_string
= NULL
;
415 this->annotation_ir
= NULL
;
416 this->base_ir
= NULL
;
418 this->virtual_grf_sizes
= NULL
;
419 this->virtual_grf_next
= 1;
420 this->virtual_grf_array_size
= 0;
421 this->virtual_grf_def
= NULL
;
422 this->virtual_grf_use
= NULL
;
426 talloc_free(this->mem_ctx
);
427 hash_table_dtor(this->variable_ht
);
430 fs_reg
*variable_storage(ir_variable
*var
);
431 int virtual_grf_alloc(int size
);
433 void visit(ir_variable
*ir
);
434 void visit(ir_assignment
*ir
);
435 void visit(ir_dereference_variable
*ir
);
436 void visit(ir_dereference_record
*ir
);
437 void visit(ir_dereference_array
*ir
);
438 void visit(ir_expression
*ir
);
439 void visit(ir_texture
*ir
);
440 void visit(ir_if
*ir
);
441 void visit(ir_constant
*ir
);
442 void visit(ir_swizzle
*ir
);
443 void visit(ir_return
*ir
);
444 void visit(ir_loop
*ir
);
445 void visit(ir_loop_jump
*ir
);
446 void visit(ir_discard
*ir
);
447 void visit(ir_call
*ir
);
448 void visit(ir_function
*ir
);
449 void visit(ir_function_signature
*ir
);
451 fs_inst
*emit(fs_inst inst
);
452 void assign_curb_setup();
453 void calculate_urb_setup();
454 void assign_urb_setup();
456 void assign_regs_trivial();
457 void calculate_live_intervals();
458 bool virtual_grf_interferes(int a
, int b
);
459 void generate_code();
460 void generate_fb_write(fs_inst
*inst
);
461 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
462 struct brw_reg
*src
);
463 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
464 void generate_math(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg
*src
);
465 void generate_discard(fs_inst
*inst
, struct brw_reg temp
);
466 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
467 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
469 void emit_dummy_fs();
470 void emit_fragcoord_interpolation(ir_variable
*ir
);
471 void emit_general_interpolation(ir_variable
*ir
);
472 void emit_interpolation_setup_gen4();
473 void emit_interpolation_setup_gen6();
474 fs_inst
*emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
);
475 fs_inst
*emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
);
476 void emit_fb_writes();
477 void emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
478 const glsl_type
*type
, bool predicated
);
480 struct brw_reg
interp_reg(int location
, int channel
);
481 int setup_uniform_values(int loc
, const glsl_type
*type
);
482 void setup_builtin_uniform_values(ir_variable
*ir
);
484 struct brw_context
*brw
;
485 const struct gl_fragment_program
*fp
;
486 struct intel_context
*intel
;
488 struct brw_wm_compile
*c
;
489 struct brw_compile
*p
;
490 struct brw_shader
*shader
;
492 exec_list instructions
;
494 int *virtual_grf_sizes
;
495 int virtual_grf_next
;
496 int virtual_grf_array_size
;
497 int *virtual_grf_def
;
498 int *virtual_grf_use
;
500 struct hash_table
*variable_ht
;
501 ir_variable
*frag_color
, *frag_data
, *frag_depth
;
502 int first_non_payload_grf
;
503 int urb_setup
[FRAG_ATTRIB_MAX
];
505 /** @{ debug annotation info */
506 const char *current_annotation
;
507 ir_instruction
*base_ir
;
508 const char **annotation_string
;
509 ir_instruction
**annotation_ir
;
514 /* Result of last visit() method. */
529 fs_visitor::virtual_grf_alloc(int size
)
531 if (virtual_grf_array_size
<= virtual_grf_next
) {
532 if (virtual_grf_array_size
== 0)
533 virtual_grf_array_size
= 16;
535 virtual_grf_array_size
*= 2;
536 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
537 int, virtual_grf_array_size
);
539 /* This slot is always unused. */
540 virtual_grf_sizes
[0] = 0;
542 virtual_grf_sizes
[virtual_grf_next
] = size
;
543 return virtual_grf_next
++;
546 /** Fixed HW reg constructor. */
547 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
551 this->hw_reg
= hw_reg
;
552 this->type
= BRW_REGISTER_TYPE_F
;
556 brw_type_for_base_type(const struct glsl_type
*type
)
558 switch (type
->base_type
) {
559 case GLSL_TYPE_FLOAT
:
560 return BRW_REGISTER_TYPE_F
;
563 return BRW_REGISTER_TYPE_D
;
565 return BRW_REGISTER_TYPE_UD
;
566 case GLSL_TYPE_ARRAY
:
567 case GLSL_TYPE_STRUCT
:
568 /* These should be overridden with the type of the member when
569 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
570 * way to trip up if we don't.
572 return BRW_REGISTER_TYPE_UD
;
574 assert(!"not reached");
575 return BRW_REGISTER_TYPE_F
;
579 /** Automatic reg constructor. */
580 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
585 this->reg
= v
->virtual_grf_alloc(type_size(type
));
586 this->reg_offset
= 0;
587 this->type
= brw_type_for_base_type(type
);
591 fs_visitor::variable_storage(ir_variable
*var
)
593 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
596 /* Our support for uniforms is piggy-backed on the struct
597 * gl_fragment_program, because that's where the values actually
598 * get stored, rather than in some global gl_shader_program uniform
602 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
604 unsigned int offset
= 0;
607 if (type
->is_matrix()) {
608 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
609 type
->vector_elements
,
612 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
613 offset
+= setup_uniform_values(loc
+ offset
, column
);
619 switch (type
->base_type
) {
620 case GLSL_TYPE_FLOAT
:
624 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
625 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
626 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
630 case GLSL_TYPE_STRUCT
:
631 for (unsigned int i
= 0; i
< type
->length
; i
++) {
632 offset
+= setup_uniform_values(loc
+ offset
,
633 type
->fields
.structure
[i
].type
);
637 case GLSL_TYPE_ARRAY
:
638 for (unsigned int i
= 0; i
< type
->length
; i
++) {
639 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
643 case GLSL_TYPE_SAMPLER
:
644 /* The sampler takes up a slot, but we don't use any values from it. */
648 assert(!"not reached");
654 /* Our support for builtin uniforms is even scarier than non-builtin.
655 * It sits on top of the PROG_STATE_VAR parameters that are
656 * automatically updated from GL context state.
659 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
661 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
663 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
664 statevar
= &_mesa_builtin_uniform_desc
[i
];
665 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
669 if (!statevar
->name
) {
671 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
676 if (ir
->type
->is_array()) {
677 array_count
= ir
->type
->length
;
682 for (int a
= 0; a
< array_count
; a
++) {
683 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
684 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
685 int tokens
[STATE_LENGTH
];
687 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
688 if (ir
->type
->is_array()) {
692 /* This state reference has already been setup by ir_to_mesa,
693 * but we'll get the same index back here.
695 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
696 (gl_state_index
*)tokens
);
697 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
699 /* Add each of the unique swizzles of the element as a
700 * parameter. This'll end up matching the expected layout of
701 * the array/matrix/structure we're trying to fill in.
704 for (unsigned int i
= 0; i
< 4; i
++) {
705 int swiz
= GET_SWZ(element
->swizzle
, i
);
706 if (swiz
== last_swiz
)
710 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
717 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
719 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
721 fs_reg neg_y
= this->pixel_y
;
725 if (ir
->pixel_center_integer
) {
726 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
728 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
733 if (ir
->origin_upper_left
&& ir
->pixel_center_integer
) {
734 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
736 fs_reg pixel_y
= this->pixel_y
;
737 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
739 if (!ir
->origin_upper_left
) {
740 pixel_y
.negate
= true;
741 offset
+= c
->key
.drawable_height
- 1.0;
744 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
749 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
750 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
753 /* gl_FragCoord.w: Already set up in emit_interpolation */
754 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
756 hash_table_insert(this->variable_ht
, reg
, ir
);
761 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
763 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
764 /* Interpolation is always in floating point regs. */
765 reg
->type
= BRW_REGISTER_TYPE_F
;
768 unsigned int array_elements
;
769 const glsl_type
*type
;
771 if (ir
->type
->is_array()) {
772 array_elements
= ir
->type
->length
;
773 if (array_elements
== 0) {
776 type
= ir
->type
->fields
.array
;
782 int location
= ir
->location
;
783 for (unsigned int i
= 0; i
< array_elements
; i
++) {
784 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
785 if (urb_setup
[location
] == -1) {
786 /* If there's no incoming setup data for this slot, don't
787 * emit interpolation for it.
789 attr
.reg_offset
+= type
->vector_elements
;
794 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
795 struct brw_reg interp
= interp_reg(location
, c
);
796 emit(fs_inst(FS_OPCODE_LINTERP
,
803 attr
.reg_offset
-= type
->vector_elements
;
805 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
806 emit(fs_inst(BRW_OPCODE_MUL
,
816 hash_table_insert(this->variable_ht
, reg
, ir
);
820 fs_visitor::visit(ir_variable
*ir
)
824 if (variable_storage(ir
))
827 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
828 this->frag_color
= ir
;
829 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
830 this->frag_data
= ir
;
831 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
832 this->frag_depth
= ir
;
835 if (ir
->mode
== ir_var_in
) {
836 if (!strcmp(ir
->name
, "gl_FragCoord")) {
837 emit_fragcoord_interpolation(ir
);
839 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
840 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
841 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
842 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
845 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
849 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
850 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
852 emit_general_interpolation(ir
);
857 if (ir
->mode
== ir_var_uniform
) {
858 int param_index
= c
->prog_data
.nr_params
;
860 if (!strncmp(ir
->name
, "gl_", 3)) {
861 setup_builtin_uniform_values(ir
);
863 setup_uniform_values(ir
->location
, ir
->type
);
866 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
870 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
872 hash_table_insert(this->variable_ht
, reg
, ir
);
876 fs_visitor::visit(ir_dereference_variable
*ir
)
878 fs_reg
*reg
= variable_storage(ir
->var
);
883 fs_visitor::visit(ir_dereference_record
*ir
)
885 const glsl_type
*struct_type
= ir
->record
->type
;
887 ir
->record
->accept(this);
889 unsigned int offset
= 0;
890 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
891 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
893 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
895 this->result
.reg_offset
+= offset
;
896 this->result
.type
= brw_type_for_base_type(ir
->type
);
900 fs_visitor::visit(ir_dereference_array
*ir
)
905 ir
->array
->accept(this);
906 index
= ir
->array_index
->as_constant();
908 element_size
= type_size(ir
->type
);
909 this->result
.type
= brw_type_for_base_type(ir
->type
);
912 assert(this->result
.file
== UNIFORM
||
913 (this->result
.file
== GRF
&&
914 this->result
.reg
!= 0));
915 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
917 assert(!"FINISHME: non-constant array element");
922 fs_visitor::visit(ir_expression
*ir
)
924 unsigned int operand
;
929 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
930 ir
->operands
[operand
]->accept(this);
931 if (this->result
.file
== BAD_FILE
) {
933 printf("Failed to get tree for expression operand:\n");
934 ir
->operands
[operand
]->accept(&v
);
937 op
[operand
] = this->result
;
939 /* Matrix expression operands should have been broken down to vector
940 * operations already.
942 assert(!ir
->operands
[operand
]->type
->is_matrix());
943 /* And then those vector operands should have been broken down to scalar.
945 assert(!ir
->operands
[operand
]->type
->is_vector());
948 /* Storage for our result. If our result goes into an assignment, it will
949 * just get copy-propagated out, so no worries.
951 this->result
= fs_reg(this, ir
->type
);
953 switch (ir
->operation
) {
954 case ir_unop_logic_not
:
955 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], fs_reg(-1)));
958 op
[0].negate
= !op
[0].negate
;
959 this->result
= op
[0];
963 this->result
= op
[0];
966 temp
= fs_reg(this, ir
->type
);
968 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
970 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
971 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
972 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
973 inst
->predicated
= true;
975 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
976 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
977 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
978 inst
->predicated
= true;
982 emit(fs_inst(FS_OPCODE_RCP
, this->result
, op
[0]));
986 emit(fs_inst(FS_OPCODE_EXP2
, this->result
, op
[0]));
989 emit(fs_inst(FS_OPCODE_LOG2
, this->result
, op
[0]));
993 assert(!"not reached: should be handled by ir_explog_to_explog2");
996 emit(fs_inst(FS_OPCODE_SIN
, this->result
, op
[0]));
999 emit(fs_inst(FS_OPCODE_COS
, this->result
, op
[0]));
1003 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
1006 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
1010 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
1013 assert(!"not reached: should be handled by ir_sub_to_add_neg");
1017 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
1020 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1023 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1027 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1028 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1029 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1031 case ir_binop_greater
:
1032 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1033 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1034 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1036 case ir_binop_lequal
:
1037 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1038 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1039 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1041 case ir_binop_gequal
:
1042 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1043 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1044 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1046 case ir_binop_equal
:
1047 case ir_binop_all_equal
: /* same as nequal for scalars */
1048 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1049 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1050 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1052 case ir_binop_nequal
:
1053 case ir_binop_any_nequal
: /* same as nequal for scalars */
1054 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1055 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1056 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1059 case ir_binop_logic_xor
:
1060 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
1063 case ir_binop_logic_or
:
1064 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
1067 case ir_binop_logic_and
:
1068 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
1072 case ir_binop_cross
:
1074 assert(!"not reached: should be handled by brw_fs_channel_expressions");
1078 assert(!"not reached: should be handled by lower_noise");
1082 emit(fs_inst(FS_OPCODE_SQRT
, this->result
, op
[0]));
1086 emit(fs_inst(FS_OPCODE_RSQ
, this->result
, op
[0]));
1092 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1095 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1099 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
1100 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1103 emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1106 op
[0].negate
= ~op
[0].negate
;
1107 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1108 this->result
.negate
= true;
1111 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1114 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
1118 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1119 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1121 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1122 inst
->predicated
= true;
1125 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1126 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1128 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1129 inst
->predicated
= true;
1133 inst
= emit(fs_inst(FS_OPCODE_POW
, this->result
, op
[0], op
[1]));
1136 case ir_unop_bit_not
:
1138 case ir_binop_lshift
:
1139 case ir_binop_rshift
:
1140 case ir_binop_bit_and
:
1141 case ir_binop_bit_xor
:
1142 case ir_binop_bit_or
:
1143 assert(!"GLSL 1.30 features unsupported");
1149 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1150 const glsl_type
*type
, bool predicated
)
1152 switch (type
->base_type
) {
1153 case GLSL_TYPE_FLOAT
:
1154 case GLSL_TYPE_UINT
:
1156 case GLSL_TYPE_BOOL
:
1157 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1158 l
.type
= brw_type_for_base_type(type
);
1159 r
.type
= brw_type_for_base_type(type
);
1161 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1162 inst
->predicated
= predicated
;
1168 case GLSL_TYPE_ARRAY
:
1169 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1170 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1173 case GLSL_TYPE_STRUCT
:
1174 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1175 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1180 case GLSL_TYPE_SAMPLER
:
1184 assert(!"not reached");
1190 fs_visitor::visit(ir_assignment
*ir
)
1195 /* FINISHME: arrays on the lhs */
1196 ir
->lhs
->accept(this);
1199 ir
->rhs
->accept(this);
1202 assert(l
.file
!= BAD_FILE
);
1203 assert(r
.file
!= BAD_FILE
);
1205 if (ir
->condition
) {
1206 /* Get the condition bool into the predicate. */
1207 ir
->condition
->accept(this);
1208 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, this->result
, fs_reg(0)));
1209 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1212 if (ir
->lhs
->type
->is_scalar() ||
1213 ir
->lhs
->type
->is_vector()) {
1214 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1215 if (ir
->write_mask
& (1 << i
)) {
1216 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1218 inst
->predicated
= true;
1224 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1229 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1233 bool simd16
= false;
1236 if (ir
->shadow_comparitor
) {
1237 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1238 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1240 coordinate
.reg_offset
++;
1242 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1245 if (ir
->op
== ir_tex
) {
1246 /* There's no plain shadow compare message, so we use shadow
1247 * compare with a bias of 0.0.
1249 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1252 } else if (ir
->op
== ir_txb
) {
1253 ir
->lod_info
.bias
->accept(this);
1254 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1258 assert(ir
->op
== ir_txl
);
1259 ir
->lod_info
.lod
->accept(this);
1260 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1265 ir
->shadow_comparitor
->accept(this);
1266 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1268 } else if (ir
->op
== ir_tex
) {
1269 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1270 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1272 coordinate
.reg_offset
++;
1274 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1277 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1278 * instructions. We'll need to do SIMD16 here.
1280 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1282 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
* 2;) {
1283 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1285 coordinate
.reg_offset
++;
1288 /* The unused upper half. */
1292 /* lod/bias appears after u/v/r. */
1295 if (ir
->op
== ir_txb
) {
1296 ir
->lod_info
.bias
->accept(this);
1297 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1301 ir
->lod_info
.lod
->accept(this);
1302 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1307 /* The unused upper half. */
1310 /* Now, since we're doing simd16, the return is 2 interleaved
1311 * vec4s where the odd-indexed ones are junk. We'll need to move
1312 * this weirdness around to the expected layout.
1316 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1318 dst
.type
= BRW_REGISTER_TYPE_F
;
1321 fs_inst
*inst
= NULL
;
1324 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
1327 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
, fs_reg(MRF
, base_mrf
)));
1330 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
, fs_reg(MRF
, base_mrf
)));
1334 assert(!"GLSL 1.30 features unsupported");
1340 for (int i
= 0; i
< 4; i
++) {
1341 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1342 orig_dst
.reg_offset
++;
1343 dst
.reg_offset
+= 2;
1351 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1353 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1354 * optional parameters like shadow comparitor or LOD bias. If
1355 * optional parameters aren't present, those base slots are
1356 * optional and don't need to be included in the message.
1358 * We don't fill in the unnecessary slots regardless, which may
1359 * look surprising in the disassembly.
1364 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1365 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1366 coordinate
.reg_offset
++;
1369 if (ir
->shadow_comparitor
) {
1370 mlen
= MAX2(mlen
, 4);
1372 ir
->shadow_comparitor
->accept(this);
1373 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1377 fs_inst
*inst
= NULL
;
1380 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
1383 ir
->lod_info
.bias
->accept(this);
1384 mlen
= MAX2(mlen
, 4);
1385 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1388 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
, fs_reg(MRF
, base_mrf
)));
1391 ir
->lod_info
.lod
->accept(this);
1392 mlen
= MAX2(mlen
, 4);
1393 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1396 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
, fs_reg(MRF
, base_mrf
)));
1400 assert(!"GLSL 1.30 features unsupported");
1409 fs_visitor::visit(ir_texture
*ir
)
1411 fs_inst
*inst
= NULL
;
1413 ir
->coordinate
->accept(this);
1414 fs_reg coordinate
= this->result
;
1416 /* Should be lowered by do_lower_texture_projection */
1417 assert(!ir
->projector
);
1419 /* Writemasking doesn't eliminate channels on SIMD8 texture
1420 * samples, so don't worry about them.
1422 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1424 if (intel
->gen
< 5) {
1425 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1427 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1431 _mesa_get_sampler_uniform_value(ir
->sampler
,
1432 ctx
->Shader
.CurrentProgram
,
1433 &brw
->fragment_program
->Base
);
1434 inst
->sampler
= c
->fp
->program
.Base
.SamplerUnits
[inst
->sampler
];
1438 if (ir
->shadow_comparitor
)
1439 inst
->shadow_compare
= true;
1443 fs_visitor::visit(ir_swizzle
*ir
)
1445 ir
->val
->accept(this);
1446 fs_reg val
= this->result
;
1448 if (ir
->type
->vector_elements
== 1) {
1449 this->result
.reg_offset
+= ir
->mask
.x
;
1453 fs_reg result
= fs_reg(this, ir
->type
);
1454 this->result
= result
;
1456 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1457 fs_reg channel
= val
;
1475 channel
.reg_offset
+= swiz
;
1476 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1477 result
.reg_offset
++;
1482 fs_visitor::visit(ir_discard
*ir
)
1484 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1486 assert(ir
->condition
== NULL
); /* FINISHME */
1488 emit(fs_inst(FS_OPCODE_DISCARD
, temp
, temp
));
1492 fs_visitor::visit(ir_constant
*ir
)
1494 fs_reg
reg(this, ir
->type
);
1497 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1498 switch (ir
->type
->base_type
) {
1499 case GLSL_TYPE_FLOAT
:
1500 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
1502 case GLSL_TYPE_UINT
:
1503 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1506 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1508 case GLSL_TYPE_BOOL
:
1509 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1512 assert(!"Non-float/uint/int/bool constant");
1519 fs_visitor::visit(ir_if
*ir
)
1523 /* Don't point the annotation at the if statement, because then it plus
1524 * the then and else blocks get printed.
1526 this->base_ir
= ir
->condition
;
1528 /* Generate the condition into the condition code. */
1529 ir
->condition
->accept(this);
1530 inst
= emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(brw_null_reg()), this->result
));
1531 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1533 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1534 inst
->predicated
= true;
1536 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1537 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1543 if (!ir
->else_instructions
.is_empty()) {
1544 emit(fs_inst(BRW_OPCODE_ELSE
));
1546 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1547 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1554 emit(fs_inst(BRW_OPCODE_ENDIF
));
1558 fs_visitor::visit(ir_loop
*ir
)
1560 fs_reg counter
= reg_undef
;
1563 this->base_ir
= ir
->counter
;
1564 ir
->counter
->accept(this);
1565 counter
= *(variable_storage(ir
->counter
));
1568 this->base_ir
= ir
->from
;
1569 ir
->from
->accept(this);
1571 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1575 emit(fs_inst(BRW_OPCODE_DO
));
1578 this->base_ir
= ir
->to
;
1579 ir
->to
->accept(this);
1581 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
,
1582 counter
, this->result
));
1584 case ir_binop_equal
:
1585 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1587 case ir_binop_nequal
:
1588 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1590 case ir_binop_gequal
:
1591 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1593 case ir_binop_lequal
:
1594 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1596 case ir_binop_greater
:
1597 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1600 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1603 assert(!"not reached: unknown loop condition");
1608 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1609 inst
->predicated
= true;
1612 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1613 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1619 if (ir
->increment
) {
1620 this->base_ir
= ir
->increment
;
1621 ir
->increment
->accept(this);
1622 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1625 emit(fs_inst(BRW_OPCODE_WHILE
));
1629 fs_visitor::visit(ir_loop_jump
*ir
)
1632 case ir_loop_jump::jump_break
:
1633 emit(fs_inst(BRW_OPCODE_BREAK
));
1635 case ir_loop_jump::jump_continue
:
1636 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1642 fs_visitor::visit(ir_call
*ir
)
1644 assert(!"FINISHME");
1648 fs_visitor::visit(ir_return
*ir
)
1650 assert(!"FINISHME");
1654 fs_visitor::visit(ir_function
*ir
)
1656 /* Ignore function bodies other than main() -- we shouldn't see calls to
1657 * them since they should all be inlined before we get to ir_to_mesa.
1659 if (strcmp(ir
->name
, "main") == 0) {
1660 const ir_function_signature
*sig
;
1663 sig
= ir
->matching_signature(&empty
);
1667 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1668 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1677 fs_visitor::visit(ir_function_signature
*ir
)
1679 assert(!"not reached");
1684 fs_visitor::emit(fs_inst inst
)
1686 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1689 list_inst
->annotation
= this->current_annotation
;
1690 list_inst
->ir
= this->base_ir
;
1692 this->instructions
.push_tail(list_inst
);
1697 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1699 fs_visitor::emit_dummy_fs()
1701 /* Everyone's favorite color. */
1702 emit(fs_inst(BRW_OPCODE_MOV
,
1705 emit(fs_inst(BRW_OPCODE_MOV
,
1708 emit(fs_inst(BRW_OPCODE_MOV
,
1711 emit(fs_inst(BRW_OPCODE_MOV
,
1716 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1721 /* The register location here is relative to the start of the URB
1722 * data. It will get adjusted to be a real location before
1723 * generate_code() time.
1726 fs_visitor::interp_reg(int location
, int channel
)
1728 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1729 int stride
= (channel
& 1) * 4;
1731 assert(urb_setup
[location
] != -1);
1733 return brw_vec1_grf(regnr
, stride
);
1736 /** Emits the interpolation for the varying inputs. */
1738 fs_visitor::emit_interpolation_setup_gen4()
1740 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1742 this->current_annotation
= "compute pixel centers";
1743 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1744 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1745 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1746 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1747 emit(fs_inst(BRW_OPCODE_ADD
,
1749 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1750 fs_reg(brw_imm_v(0x10101010))));
1751 emit(fs_inst(BRW_OPCODE_ADD
,
1753 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1754 fs_reg(brw_imm_v(0x11001100))));
1756 this->current_annotation
= "compute pixel deltas from v0";
1758 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1759 this->delta_y
= this->delta_x
;
1760 this->delta_y
.reg_offset
++;
1762 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1763 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1765 emit(fs_inst(BRW_OPCODE_ADD
,
1768 fs_reg(negate(brw_vec1_grf(1, 0)))));
1769 emit(fs_inst(BRW_OPCODE_ADD
,
1772 fs_reg(negate(brw_vec1_grf(1, 1)))));
1774 this->current_annotation
= "compute pos.w and 1/pos.w";
1775 /* Compute wpos.w. It's always in our setup, since it's needed to
1776 * interpolate the other attributes.
1778 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1779 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1780 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1781 /* Compute the pixel 1/W value from wpos.w. */
1782 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1783 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
));
1784 this->current_annotation
= NULL
;
1787 /** Emits the interpolation for the varying inputs. */
1789 fs_visitor::emit_interpolation_setup_gen6()
1791 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1793 /* If the pixel centers end up used, the setup is the same as for gen4. */
1794 this->current_annotation
= "compute pixel centers";
1795 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1796 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1797 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1798 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1799 emit(fs_inst(BRW_OPCODE_ADD
,
1801 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1802 fs_reg(brw_imm_v(0x10101010))));
1803 emit(fs_inst(BRW_OPCODE_ADD
,
1805 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1806 fs_reg(brw_imm_v(0x11001100))));
1808 this->current_annotation
= "compute 1/pos.w";
1809 this->wpos_w
= fs_reg(brw_vec8_grf(c
->key
.source_w_reg
, 0));
1810 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1811 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
));
1813 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1814 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1816 this->current_annotation
= NULL
;
1820 fs_visitor::emit_fb_writes()
1822 this->current_annotation
= "FB write header";
1828 if (c
->key
.aa_dest_stencil_reg
) {
1829 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1830 fs_reg(brw_vec8_grf(c
->key
.aa_dest_stencil_reg
, 0))));
1833 /* Reserve space for color. It'll be filled in per MRT below. */
1837 if (c
->key
.source_depth_to_render_target
) {
1838 if (c
->key
.computes_depth
) {
1839 /* Hand over gl_FragDepth. */
1840 assert(this->frag_depth
);
1841 fs_reg depth
= *(variable_storage(this->frag_depth
));
1843 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
1845 /* Pass through the payload depth. */
1846 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1847 fs_reg(brw_vec8_grf(c
->key
.source_depth_reg
, 0))));
1851 if (c
->key
.dest_depth_reg
) {
1852 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1853 fs_reg(brw_vec8_grf(c
->key
.dest_depth_reg
, 0))));
1856 fs_reg color
= reg_undef
;
1857 if (this->frag_color
)
1858 color
= *(variable_storage(this->frag_color
));
1859 else if (this->frag_data
)
1860 color
= *(variable_storage(this->frag_data
));
1862 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1863 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1864 "FB write target %d",
1866 if (this->frag_color
|| this->frag_data
) {
1867 for (int i
= 0; i
< 4; i
++) {
1868 emit(fs_inst(BRW_OPCODE_MOV
,
1869 fs_reg(MRF
, color_mrf
+ i
),
1875 if (this->frag_color
)
1876 color
.reg_offset
-= 4;
1878 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1879 reg_undef
, reg_undef
));
1880 inst
->target
= target
;
1882 if (target
== c
->key
.nr_color_regions
- 1)
1886 if (c
->key
.nr_color_regions
== 0) {
1887 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1888 reg_undef
, reg_undef
));
1893 this->current_annotation
= NULL
;
1897 fs_visitor::generate_fb_write(fs_inst
*inst
)
1899 GLboolean eot
= inst
->eot
;
1901 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1904 brw_push_insn_state(p
);
1905 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1906 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1909 brw_vec8_grf(1, 0));
1910 brw_pop_insn_state(p
);
1913 8, /* dispatch_width */
1914 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
1916 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
1924 fs_visitor::generate_linterp(fs_inst
*inst
,
1925 struct brw_reg dst
, struct brw_reg
*src
)
1927 struct brw_reg delta_x
= src
[0];
1928 struct brw_reg delta_y
= src
[1];
1929 struct brw_reg interp
= src
[2];
1932 delta_y
.nr
== delta_x
.nr
+ 1 &&
1933 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
1934 brw_PLN(p
, dst
, interp
, delta_x
);
1936 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
1937 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
1942 fs_visitor::generate_math(fs_inst
*inst
,
1943 struct brw_reg dst
, struct brw_reg
*src
)
1947 switch (inst
->opcode
) {
1949 op
= BRW_MATH_FUNCTION_INV
;
1952 op
= BRW_MATH_FUNCTION_RSQ
;
1954 case FS_OPCODE_SQRT
:
1955 op
= BRW_MATH_FUNCTION_SQRT
;
1957 case FS_OPCODE_EXP2
:
1958 op
= BRW_MATH_FUNCTION_EXP
;
1960 case FS_OPCODE_LOG2
:
1961 op
= BRW_MATH_FUNCTION_LOG
;
1964 op
= BRW_MATH_FUNCTION_POW
;
1967 op
= BRW_MATH_FUNCTION_SIN
;
1970 op
= BRW_MATH_FUNCTION_COS
;
1973 assert(!"not reached: unknown math function");
1978 if (inst
->opcode
== FS_OPCODE_POW
) {
1979 brw_MOV(p
, brw_message_reg(3), src
[1]);
1984 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
1985 BRW_MATH_SATURATE_NONE
,
1987 BRW_MATH_DATA_VECTOR
,
1988 BRW_MATH_PRECISION_FULL
);
1992 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
1996 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1998 if (intel
->gen
== 5) {
1999 switch (inst
->opcode
) {
2001 if (inst
->shadow_compare
) {
2002 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
2004 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
2008 if (inst
->shadow_compare
) {
2009 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
2011 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
2016 switch (inst
->opcode
) {
2018 /* Note that G45 and older determines shadow compare and dispatch width
2019 * from message length for most messages.
2021 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2022 if (inst
->shadow_compare
) {
2023 assert(inst
->mlen
== 5);
2025 assert(inst
->mlen
<= 6);
2029 if (inst
->shadow_compare
) {
2030 assert(inst
->mlen
== 5);
2031 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2033 assert(inst
->mlen
== 8);
2034 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2035 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2040 assert(msg_type
!= -1);
2042 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2051 retype(dst
, BRW_REGISTER_TYPE_UW
),
2053 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2054 SURF_INDEX_TEXTURE(inst
->sampler
),
2066 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2069 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2071 * and we're trying to produce:
2074 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2075 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2076 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2077 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2078 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2079 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2080 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2081 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2083 * and add another set of two more subspans if in 16-pixel dispatch mode.
2085 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2086 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2087 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2088 * between each other. We could probably do it like ddx and swizzle the right
2089 * order later, but bail for now and just produce
2090 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2093 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2095 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2096 BRW_REGISTER_TYPE_F
,
2097 BRW_VERTICAL_STRIDE_2
,
2099 BRW_HORIZONTAL_STRIDE_0
,
2100 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2101 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2102 BRW_REGISTER_TYPE_F
,
2103 BRW_VERTICAL_STRIDE_2
,
2105 BRW_HORIZONTAL_STRIDE_0
,
2106 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2107 brw_ADD(p
, dst
, src0
, negate(src1
));
2111 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2113 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2114 BRW_REGISTER_TYPE_F
,
2115 BRW_VERTICAL_STRIDE_4
,
2117 BRW_HORIZONTAL_STRIDE_0
,
2118 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2119 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2120 BRW_REGISTER_TYPE_F
,
2121 BRW_VERTICAL_STRIDE_4
,
2123 BRW_HORIZONTAL_STRIDE_0
,
2124 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2125 brw_ADD(p
, dst
, src0
, negate(src1
));
2129 fs_visitor::generate_discard(fs_inst
*inst
, struct brw_reg temp
)
2131 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2132 temp
= brw_uw1_reg(temp
.file
, temp
.nr
, 0);
2134 brw_push_insn_state(p
);
2135 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2136 brw_NOT(p
, temp
, brw_mask_reg(1)); /* IMASK */
2137 brw_AND(p
, g0
, temp
, g0
);
2138 brw_pop_insn_state(p
);
2142 fs_visitor::assign_curb_setup()
2144 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
2145 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2147 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2148 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2149 fs_inst
*inst
= (fs_inst
*)iter
.get();
2151 for (unsigned int i
= 0; i
< 3; i
++) {
2152 if (inst
->src
[i
].file
== UNIFORM
) {
2153 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2154 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2158 inst
->src
[i
].file
= FIXED_HW_REG
;
2159 inst
->src
[i
].fixed_hw_reg
= brw_reg
;
2166 fs_visitor::calculate_urb_setup()
2168 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2173 /* Figure out where each of the incoming setup attributes lands. */
2174 if (intel
->gen
>= 6) {
2175 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2176 if (i
== FRAG_ATTRIB_WPOS
||
2177 (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
))) {
2178 urb_setup
[i
] = urb_next
++;
2182 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2183 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2184 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2187 if (i
>= VERT_RESULT_VAR0
)
2188 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2189 else if (i
<= VERT_RESULT_TEX7
)
2195 urb_setup
[fp_index
] = urb_next
++;
2200 /* Each attribute is 4 setup channels, each of which is half a reg. */
2201 c
->prog_data
.urb_read_length
= urb_next
* 2;
2205 fs_visitor::assign_urb_setup()
2207 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2209 /* Offset all the urb_setup[] index by the actual position of the
2210 * setup regs, now that the location of the constants has been chosen.
2212 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2213 fs_inst
*inst
= (fs_inst
*)iter
.get();
2215 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
2218 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2220 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2223 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2227 assign_reg(int *reg_hw_locations
, fs_reg
*reg
)
2229 if (reg
->file
== GRF
&& reg
->reg
!= 0) {
2230 reg
->hw_reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
;
2236 fs_visitor::assign_regs_trivial()
2239 int hw_reg_mapping
[this->virtual_grf_next
];
2242 hw_reg_mapping
[0] = 0;
2243 hw_reg_mapping
[1] = this->first_non_payload_grf
;
2244 for (i
= 2; i
< this->virtual_grf_next
; i
++) {
2245 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
2246 this->virtual_grf_sizes
[i
- 1]);
2248 last_grf
= hw_reg_mapping
[i
- 1] + this->virtual_grf_sizes
[i
- 1];
2250 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2251 fs_inst
*inst
= (fs_inst
*)iter
.get();
2253 assign_reg(hw_reg_mapping
, &inst
->dst
);
2254 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2255 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2258 this->grf_used
= last_grf
+ 1;
2262 fs_visitor::assign_regs()
2265 int hw_reg_mapping
[this->virtual_grf_next
+ 1];
2266 int base_reg_count
= BRW_MAX_GRF
- this->first_non_payload_grf
;
2267 int class_sizes
[base_reg_count
];
2268 int class_count
= 0;
2269 int aligned_pair_class
= -1;
2271 calculate_live_intervals();
2273 /* Set up the register classes.
2275 * The base registers store a scalar value. For texture samples,
2276 * we get virtual GRFs composed of 4 contiguous hw register. For
2277 * structures and arrays, we store them as contiguous larger things
2278 * than that, though we should be able to do better most of the
2281 class_sizes
[class_count
++] = 1;
2282 if (brw
->has_pln
&& intel
->gen
< 6) {
2283 /* Always set up the (unaligned) pairs for gen5, so we can find
2284 * them for making the aligned pair class.
2286 class_sizes
[class_count
++] = 2;
2288 for (int r
= 1; r
< this->virtual_grf_next
; r
++) {
2291 for (i
= 0; i
< class_count
; i
++) {
2292 if (class_sizes
[i
] == this->virtual_grf_sizes
[r
])
2295 if (i
== class_count
) {
2296 if (this->virtual_grf_sizes
[r
] >= base_reg_count
) {
2297 fprintf(stderr
, "Object too large to register allocate.\n");
2301 class_sizes
[class_count
++] = this->virtual_grf_sizes
[r
];
2305 int ra_reg_count
= 0;
2306 int class_base_reg
[class_count
];
2307 int class_reg_count
[class_count
];
2308 int classes
[class_count
+ 1];
2310 for (int i
= 0; i
< class_count
; i
++) {
2311 class_base_reg
[i
] = ra_reg_count
;
2312 class_reg_count
[i
] = base_reg_count
- (class_sizes
[i
] - 1);
2313 ra_reg_count
+= class_reg_count
[i
];
2316 struct ra_regs
*regs
= ra_alloc_reg_set(ra_reg_count
);
2317 for (int i
= 0; i
< class_count
; i
++) {
2318 classes
[i
] = ra_alloc_reg_class(regs
);
2320 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2321 ra_class_add_reg(regs
, classes
[i
], class_base_reg
[i
] + i_r
);
2324 /* Add conflicts between our contiguous registers aliasing
2325 * base regs and other register classes' contiguous registers
2326 * that alias base regs, or the base regs themselves for classes[0].
2328 for (int c
= 0; c
<= i
; c
++) {
2329 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2330 for (int c_r
= MAX2(0, i_r
- (class_sizes
[c
] - 1));
2331 c_r
< MIN2(class_reg_count
[c
], i_r
+ class_sizes
[i
]);
2335 printf("%d/%d conflicts %d/%d\n",
2336 class_sizes
[i
], this->first_non_payload_grf
+ i_r
,
2337 class_sizes
[c
], this->first_non_payload_grf
+ c_r
);
2340 ra_add_reg_conflict(regs
,
2341 class_base_reg
[i
] + i_r
,
2342 class_base_reg
[c
] + c_r
);
2348 /* Add a special class for aligned pairs, which we'll put delta_x/y
2349 * in on gen5 so that we can do PLN.
2351 if (brw
->has_pln
&& intel
->gen
< 6) {
2352 int reg_count
= (base_reg_count
- 1) / 2;
2353 int unaligned_pair_class
= 1;
2354 assert(class_sizes
[unaligned_pair_class
] == 2);
2356 aligned_pair_class
= class_count
;
2357 classes
[aligned_pair_class
] = ra_alloc_reg_class(regs
);
2358 class_base_reg
[aligned_pair_class
] = 0;
2359 class_reg_count
[aligned_pair_class
] = 0;
2360 int start
= (this->first_non_payload_grf
& 1) ? 1 : 0;
2362 for (int i
= 0; i
< reg_count
; i
++) {
2363 ra_class_add_reg(regs
, classes
[aligned_pair_class
],
2364 class_base_reg
[unaligned_pair_class
] + i
* 2 + start
);
2369 ra_set_finalize(regs
);
2371 struct ra_graph
*g
= ra_alloc_interference_graph(regs
,
2372 this->virtual_grf_next
);
2373 /* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1
2376 ra_set_node_class(g
, 0, classes
[0]);
2378 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2379 for (int c
= 0; c
< class_count
; c
++) {
2380 if (class_sizes
[c
] == this->virtual_grf_sizes
[i
]) {
2381 if (aligned_pair_class
>= 0 &&
2382 this->delta_x
.reg
== i
) {
2383 ra_set_node_class(g
, i
, classes
[aligned_pair_class
]);
2385 ra_set_node_class(g
, i
, classes
[c
]);
2391 for (int j
= 1; j
< i
; j
++) {
2392 if (virtual_grf_interferes(i
, j
)) {
2393 ra_add_node_interference(g
, i
, j
);
2398 /* FINISHME: Handle spilling */
2399 if (!ra_allocate_no_spills(g
)) {
2400 fprintf(stderr
, "Failed to allocate registers.\n");
2405 /* Get the chosen virtual registers for each node, and map virtual
2406 * regs in the register classes back down to real hardware reg
2409 hw_reg_mapping
[0] = 0; /* unused */
2410 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2411 int reg
= ra_get_node_reg(g
, i
);
2414 for (int c
= 0; c
< class_count
; c
++) {
2415 if (reg
>= class_base_reg
[c
] &&
2416 reg
< class_base_reg
[c
] + class_reg_count
[c
]) {
2417 hw_reg
= reg
- class_base_reg
[c
];
2422 assert(hw_reg
!= -1);
2423 hw_reg_mapping
[i
] = this->first_non_payload_grf
+ hw_reg
;
2424 last_grf
= MAX2(last_grf
,
2425 hw_reg_mapping
[i
] + this->virtual_grf_sizes
[i
] - 1);
2428 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2429 fs_inst
*inst
= (fs_inst
*)iter
.get();
2431 assign_reg(hw_reg_mapping
, &inst
->dst
);
2432 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2433 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2436 this->grf_used
= last_grf
+ 1;
2443 fs_visitor::calculate_live_intervals()
2445 int num_vars
= this->virtual_grf_next
;
2446 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2447 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2451 for (int i
= 0; i
< num_vars
; i
++) {
2457 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2458 fs_inst
*inst
= (fs_inst
*)iter
.get();
2460 if (inst
->opcode
== BRW_OPCODE_DO
) {
2461 if (loop_depth
++ == 0)
2463 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2466 if (loop_depth
== 0) {
2469 * Patches up any vars marked for use within the loop as
2470 * live until the end. This is conservative, as there
2471 * will often be variables defined and used inside the
2472 * loop but dead at the end of the loop body.
2474 for (int i
= 0; i
< num_vars
; i
++) {
2475 if (use
[i
] == loop_start
) {
2486 for (unsigned int i
= 0; i
< 3; i
++) {
2487 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2488 def
[inst
->src
[i
].reg
] = MIN2(def
[inst
->src
[i
].reg
], eip
);
2489 use
[inst
->src
[i
].reg
] = MAX2(use
[inst
->src
[i
].reg
], eip
);
2492 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2493 def
[inst
->dst
.reg
] = MIN2(def
[inst
->dst
.reg
], eip
);
2494 use
[inst
->dst
.reg
] = MAX2(use
[inst
->dst
.reg
], eip
);
2501 this->virtual_grf_def
= def
;
2502 this->virtual_grf_use
= use
;
2506 fs_visitor::virtual_grf_interferes(int a
, int b
)
2508 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
2509 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
2511 return start
<= end
;
2514 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
2516 struct brw_reg brw_reg
;
2518 switch (reg
->file
) {
2522 brw_reg
= brw_vec8_reg(reg
->file
,
2524 brw_reg
= retype(brw_reg
, reg
->type
);
2527 switch (reg
->type
) {
2528 case BRW_REGISTER_TYPE_F
:
2529 brw_reg
= brw_imm_f(reg
->imm
.f
);
2531 case BRW_REGISTER_TYPE_D
:
2532 brw_reg
= brw_imm_d(reg
->imm
.i
);
2534 case BRW_REGISTER_TYPE_UD
:
2535 brw_reg
= brw_imm_ud(reg
->imm
.u
);
2538 assert(!"not reached");
2543 brw_reg
= reg
->fixed_hw_reg
;
2546 /* Probably unused. */
2547 brw_reg
= brw_null_reg();
2550 assert(!"not reached");
2551 brw_reg
= brw_null_reg();
2555 brw_reg
= brw_abs(brw_reg
);
2557 brw_reg
= negate(brw_reg
);
2563 fs_visitor::generate_code()
2565 unsigned int annotation_len
= 0;
2566 int last_native_inst
= 0;
2567 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
2568 int if_stack_depth
= 0, loop_stack_depth
= 0;
2569 int if_depth_in_loop
[16];
2571 if_depth_in_loop
[loop_stack_depth
] = 0;
2573 memset(&if_stack
, 0, sizeof(if_stack
));
2574 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2575 fs_inst
*inst
= (fs_inst
*)iter
.get();
2576 struct brw_reg src
[3], dst
;
2578 for (unsigned int i
= 0; i
< 3; i
++) {
2579 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
2581 dst
= brw_reg_from_fs_reg(&inst
->dst
);
2583 brw_set_conditionalmod(p
, inst
->conditional_mod
);
2584 brw_set_predicate_control(p
, inst
->predicated
);
2586 switch (inst
->opcode
) {
2587 case BRW_OPCODE_MOV
:
2588 brw_MOV(p
, dst
, src
[0]);
2590 case BRW_OPCODE_ADD
:
2591 brw_ADD(p
, dst
, src
[0], src
[1]);
2593 case BRW_OPCODE_MUL
:
2594 brw_MUL(p
, dst
, src
[0], src
[1]);
2597 case BRW_OPCODE_FRC
:
2598 brw_FRC(p
, dst
, src
[0]);
2600 case BRW_OPCODE_RNDD
:
2601 brw_RNDD(p
, dst
, src
[0]);
2603 case BRW_OPCODE_RNDZ
:
2604 brw_RNDZ(p
, dst
, src
[0]);
2607 case BRW_OPCODE_AND
:
2608 brw_AND(p
, dst
, src
[0], src
[1]);
2611 brw_OR(p
, dst
, src
[0], src
[1]);
2613 case BRW_OPCODE_XOR
:
2614 brw_XOR(p
, dst
, src
[0], src
[1]);
2617 case BRW_OPCODE_CMP
:
2618 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
2620 case BRW_OPCODE_SEL
:
2621 brw_SEL(p
, dst
, src
[0], src
[1]);
2625 assert(if_stack_depth
< 16);
2626 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
2627 if_depth_in_loop
[loop_stack_depth
]++;
2630 case BRW_OPCODE_ELSE
:
2631 if_stack
[if_stack_depth
- 1] =
2632 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
2634 case BRW_OPCODE_ENDIF
:
2636 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
2637 if_depth_in_loop
[loop_stack_depth
]--;
2641 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
2642 if_depth_in_loop
[loop_stack_depth
] = 0;
2645 case BRW_OPCODE_BREAK
:
2646 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
2647 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2649 case BRW_OPCODE_CONTINUE
:
2650 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
2651 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2654 case BRW_OPCODE_WHILE
: {
2655 struct brw_instruction
*inst0
, *inst1
;
2658 if (intel
->gen
>= 5)
2661 assert(loop_stack_depth
> 0);
2663 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
2664 /* patch all the BREAK/CONT instructions from last BGNLOOP */
2665 while (inst0
> loop_stack
[loop_stack_depth
]) {
2667 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
2668 inst0
->bits3
.if_else
.jump_count
== 0) {
2669 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
2671 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
2672 inst0
->bits3
.if_else
.jump_count
== 0) {
2673 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
2681 case FS_OPCODE_SQRT
:
2682 case FS_OPCODE_EXP2
:
2683 case FS_OPCODE_LOG2
:
2687 generate_math(inst
, dst
, src
);
2689 case FS_OPCODE_LINTERP
:
2690 generate_linterp(inst
, dst
, src
);
2695 generate_tex(inst
, dst
, src
[0]);
2697 case FS_OPCODE_DISCARD
:
2698 generate_discard(inst
, dst
/* src0 == dst */);
2701 generate_ddx(inst
, dst
, src
[0]);
2704 generate_ddy(inst
, dst
, src
[0]);
2706 case FS_OPCODE_FB_WRITE
:
2707 generate_fb_write(inst
);
2710 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
2711 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
2712 brw_opcodes
[inst
->opcode
].name
);
2714 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
2719 if (annotation_len
< p
->nr_insn
) {
2720 annotation_len
*= 2;
2721 if (annotation_len
< 16)
2722 annotation_len
= 16;
2724 this->annotation_string
= talloc_realloc(this->mem_ctx
,
2728 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
2734 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
2735 this->annotation_string
[i
] = inst
->annotation
;
2736 this->annotation_ir
[i
] = inst
->ir
;
2738 last_native_inst
= p
->nr_insn
;
2743 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
2745 struct brw_compile
*p
= &c
->func
;
2746 struct intel_context
*intel
= &brw
->intel
;
2747 GLcontext
*ctx
= &intel
->ctx
;
2748 struct brw_shader
*shader
= NULL
;
2749 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
2757 for (unsigned int i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
2758 if (prog
->_LinkedShaders
[i
]->Type
== GL_FRAGMENT_SHADER
) {
2759 shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
2766 /* We always use 8-wide mode, at least for now. For one, flow
2767 * control only works in 8-wide. Also, when we're fragment shader
2768 * bound, we're almost always under register pressure as well, so
2769 * 8-wide would save us from the performance cliff of spilling
2772 c
->dispatch_width
= 8;
2774 if (INTEL_DEBUG
& DEBUG_WM
) {
2775 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
2776 _mesa_print_ir(shader
->ir
, NULL
);
2780 /* Now the main event: Visit the shader IR and generate our FS IR for it.
2782 fs_visitor
v(c
, shader
);
2787 v
.calculate_urb_setup();
2789 v
.emit_interpolation_setup_gen4();
2791 v
.emit_interpolation_setup_gen6();
2793 /* Generate FS IR for main(). (the visitor only descends into
2794 * functions called "main").
2796 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
2797 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
2803 v
.assign_curb_setup();
2804 v
.assign_urb_setup();
2806 v
.assign_regs_trivial();
2814 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
2819 if (INTEL_DEBUG
& DEBUG_WM
) {
2820 const char *last_annotation_string
= NULL
;
2821 ir_instruction
*last_annotation_ir
= NULL
;
2823 printf("Native code for fragment shader %d:\n", prog
->Name
);
2824 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
2825 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
2826 last_annotation_ir
= v
.annotation_ir
[i
];
2827 if (last_annotation_ir
) {
2829 last_annotation_ir
->print();
2833 if (last_annotation_string
!= v
.annotation_string
[i
]) {
2834 last_annotation_string
= v
.annotation_string
[i
];
2835 if (last_annotation_string
)
2836 printf(" %s\n", last_annotation_string
);
2838 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
2843 c
->prog_data
.total_grf
= v
.grf_used
;
2844 c
->prog_data
.total_scratch
= 0;