2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "brw_dead_control_flow.h"
47 #include "main/uniforms.h"
48 #include "brw_fs_live_variables.h"
49 #include "glsl/glsl_types.h"
50 #include "program/sampler.h"
55 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
56 const fs_reg
*src
, unsigned sources
)
58 memset(this, 0, sizeof(*this));
60 this->src
= new fs_reg
[MAX2(sources
, 3)];
61 for (unsigned i
= 0; i
< sources
; i
++)
62 this->src
[i
] = src
[i
];
64 this->opcode
= opcode
;
66 this->sources
= sources
;
67 this->exec_size
= exec_size
;
69 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
71 /* If exec_size == 0, try to guess it from the registers. Since all
72 * manner of things may use hardware registers, we first try to guess
73 * based on GRF registers. If this fails, we will go ahead and take the
74 * width from the destination register.
76 if (this->exec_size
== 0) {
77 if (dst
.file
== GRF
) {
78 this->exec_size
= dst
.width
;
80 for (unsigned i
= 0; i
< sources
; ++i
) {
81 if (src
[i
].file
!= GRF
&& src
[i
].file
!= ATTR
)
84 if (this->exec_size
<= 1)
85 this->exec_size
= src
[i
].width
;
86 assert(src
[i
].width
== 1 || src
[i
].width
== this->exec_size
);
90 if (this->exec_size
== 0 && dst
.file
!= BAD_FILE
)
91 this->exec_size
= dst
.width
;
93 assert(this->exec_size
!= 0);
95 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
97 /* This will be the case for almost all instructions. */
104 DIV_ROUND_UP(MAX2(dst
.width
* dst
.stride
, 1) * type_sz(dst
.type
), 32);
107 this->regs_written
= 0;
111 unreachable("Invalid destination register file");
113 unreachable("Invalid register file");
116 this->writes_accumulator
= false;
121 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
124 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
126 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
129 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
)
131 init(opcode
, 0, dst
, NULL
, 0);
134 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
137 const fs_reg src
[1] = { src0
};
138 init(opcode
, exec_size
, dst
, src
, 1);
141 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
)
143 const fs_reg src
[1] = { src0
};
144 init(opcode
, 0, dst
, src
, 1);
147 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
148 const fs_reg
&src0
, const fs_reg
&src1
)
150 const fs_reg src
[2] = { src0
, src1
};
151 init(opcode
, exec_size
, dst
, src
, 2);
154 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
157 const fs_reg src
[2] = { src0
, src1
};
158 init(opcode
, 0, dst
, src
, 2);
161 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
162 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
164 const fs_reg src
[3] = { src0
, src1
, src2
};
165 init(opcode
, exec_size
, dst
, src
, 3);
168 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
169 const fs_reg
&src1
, const fs_reg
&src2
)
171 const fs_reg src
[3] = { src0
, src1
, src2
};
172 init(opcode
, 0, dst
, src
, 3);
175 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
,
176 const fs_reg src
[], unsigned sources
)
178 init(opcode
, 0, dst
, src
, sources
);
181 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
182 const fs_reg src
[], unsigned sources
)
184 init(opcode
, exec_width
, dst
, src
, sources
);
187 fs_inst::fs_inst(const fs_inst
&that
)
189 memcpy(this, &that
, sizeof(that
));
191 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
193 for (unsigned i
= 0; i
< that
.sources
; i
++)
194 this->src
[i
] = that
.src
[i
];
203 fs_inst::resize_sources(uint8_t num_sources
)
205 if (this->sources
!= num_sources
) {
206 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
208 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
209 src
[i
] = this->src
[i
];
213 this->sources
= num_sources
;
218 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
220 const fs_reg
&surf_index
,
221 const fs_reg
&varying_offset
,
222 uint32_t const_offset
)
224 /* We have our constant surface use a pitch of 4 bytes, so our index can
225 * be any component of a vector, and then we load 4 contiguous
226 * components starting from that.
228 * We break down the const_offset to a portion added to the variable
229 * offset and a portion done using reg_offset, which means that if you
230 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
231 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
232 * CSE can later notice that those loads are all the same and eliminate
233 * the redundant ones.
235 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
236 bld
.ADD(vec4_offset
, varying_offset
, fs_reg(const_offset
& ~3));
239 if (devinfo
->gen
== 4 && dst
.width
== 8) {
240 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
241 * u, v, r) as parameters, or we can just use the SIMD16 message
242 * consisting of (header, u). We choose the second, at the cost of a
243 * longer return length.
249 if (devinfo
->gen
>= 7)
250 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
252 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
254 assert(dst
.width
% 8 == 0);
255 int regs_written
= 4 * (dst
.width
/ 8) * scale
;
256 fs_reg vec4_result
= fs_reg(GRF
, alloc
.allocate(regs_written
),
257 dst
.type
, dst
.width
);
258 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
259 inst
->regs_written
= regs_written
;
261 if (devinfo
->gen
< 7) {
263 inst
->header_size
= 1;
264 if (devinfo
->gen
== 4)
267 inst
->mlen
= 1 + dispatch_width
/ 8;
270 bld
.MOV(dst
, offset(vec4_result
, (const_offset
& 3) * scale
));
274 * A helper for MOV generation for fixing up broken hardware SEND dependency
278 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
280 /* The caller always wants uncompressed to emit the minimal extra
281 * dependencies, and to avoid having to deal with aligning its regs to 2.
283 const fs_builder ubld
= bld
.annotate("send dependency resolve")
286 ubld
.MOV(ubld
.null_reg_f(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
290 fs_inst::equals(fs_inst
*inst
) const
292 return (opcode
== inst
->opcode
&&
293 dst
.equals(inst
->dst
) &&
294 src
[0].equals(inst
->src
[0]) &&
295 src
[1].equals(inst
->src
[1]) &&
296 src
[2].equals(inst
->src
[2]) &&
297 saturate
== inst
->saturate
&&
298 predicate
== inst
->predicate
&&
299 conditional_mod
== inst
->conditional_mod
&&
300 mlen
== inst
->mlen
&&
301 base_mrf
== inst
->base_mrf
&&
302 target
== inst
->target
&&
304 header_size
== inst
->header_size
&&
305 shadow_compare
== inst
->shadow_compare
&&
306 exec_size
== inst
->exec_size
&&
307 offset
== inst
->offset
);
311 fs_inst::overwrites_reg(const fs_reg
®
) const
313 return reg
.in_range(dst
, regs_written
);
317 fs_inst::is_send_from_grf() const
320 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
321 case SHADER_OPCODE_SHADER_TIME_ADD
:
322 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
323 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
324 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
325 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
326 case SHADER_OPCODE_UNTYPED_ATOMIC
:
327 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
328 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
329 case SHADER_OPCODE_TYPED_ATOMIC
:
330 case SHADER_OPCODE_TYPED_SURFACE_READ
:
331 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
332 case SHADER_OPCODE_URB_WRITE_SIMD8
:
334 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
335 return src
[1].file
== GRF
;
336 case FS_OPCODE_FB_WRITE
:
337 return src
[0].file
== GRF
;
340 return src
[0].file
== GRF
;
347 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
349 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
352 fs_reg reg
= this->src
[0];
353 if (reg
.file
!= GRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
356 if (grf_alloc
.sizes
[reg
.reg
] != this->regs_written
)
359 for (int i
= 0; i
< this->sources
; i
++) {
360 reg
.type
= this->src
[i
].type
;
361 reg
.width
= this->src
[i
].width
;
362 if (!this->src
[i
].equals(reg
))
364 reg
= ::offset(reg
, 1);
371 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
373 if (devinfo
->gen
== 6 && is_math())
376 if (is_send_from_grf())
379 if (!backend_instruction::can_do_source_mods())
386 fs_inst::has_side_effects() const
388 return this->eot
|| backend_instruction::has_side_effects();
394 memset(this, 0, sizeof(*this));
398 /** Generic unset register constructor. */
402 this->file
= BAD_FILE
;
405 /** Immediate value constructor. */
406 fs_reg::fs_reg(float f
)
410 this->type
= BRW_REGISTER_TYPE_F
;
411 this->fixed_hw_reg
.dw1
.f
= f
;
415 /** Immediate value constructor. */
416 fs_reg::fs_reg(int32_t i
)
420 this->type
= BRW_REGISTER_TYPE_D
;
421 this->fixed_hw_reg
.dw1
.d
= i
;
425 /** Immediate value constructor. */
426 fs_reg::fs_reg(uint32_t u
)
430 this->type
= BRW_REGISTER_TYPE_UD
;
431 this->fixed_hw_reg
.dw1
.ud
= u
;
435 /** Vector float immediate value constructor. */
436 fs_reg::fs_reg(uint8_t vf
[4])
440 this->type
= BRW_REGISTER_TYPE_VF
;
441 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
444 /** Vector float immediate value constructor. */
445 fs_reg::fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
449 this->type
= BRW_REGISTER_TYPE_VF
;
450 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
456 /** Fixed brw_reg. */
457 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
461 this->fixed_hw_reg
= fixed_hw_reg
;
462 this->type
= fixed_hw_reg
.type
;
463 this->width
= 1 << fixed_hw_reg
.width
;
467 fs_reg::equals(const fs_reg
&r
) const
469 return (file
== r
.file
&&
471 reg_offset
== r
.reg_offset
&&
472 subreg_offset
== r
.subreg_offset
&&
474 negate
== r
.negate
&&
476 !reladdr
&& !r
.reladdr
&&
477 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
, sizeof(fixed_hw_reg
)) == 0 &&
483 fs_reg::set_smear(unsigned subreg
)
485 assert(file
!= HW_REG
&& file
!= IMM
);
486 subreg_offset
= subreg
* type_sz(type
);
492 fs_reg::is_contiguous() const
498 fs_visitor::type_size(const struct glsl_type
*type
)
500 unsigned int size
, i
;
502 switch (type
->base_type
) {
505 case GLSL_TYPE_FLOAT
:
507 return type
->components();
508 case GLSL_TYPE_ARRAY
:
509 return type_size(type
->fields
.array
) * type
->length
;
510 case GLSL_TYPE_STRUCT
:
512 for (i
= 0; i
< type
->length
; i
++) {
513 size
+= type_size(type
->fields
.structure
[i
].type
);
516 case GLSL_TYPE_SAMPLER
:
517 /* Samplers take up no register space, since they're baked in at
521 case GLSL_TYPE_ATOMIC_UINT
:
523 case GLSL_TYPE_IMAGE
:
525 case GLSL_TYPE_ERROR
:
526 case GLSL_TYPE_INTERFACE
:
527 case GLSL_TYPE_DOUBLE
:
528 case GLSL_TYPE_FUNCTION
:
529 unreachable("not reached");
536 * Create a MOV to read the timestamp register.
538 * The caller is responsible for emitting the MOV. The return value is
539 * the destination of the MOV, with extra parameters set.
542 fs_visitor::get_timestamp(const fs_builder
&bld
)
544 assert(devinfo
->gen
>= 7);
546 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
549 BRW_REGISTER_TYPE_UD
));
551 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
, 4);
553 /* We want to read the 3 fields we care about even if it's not enabled in
556 bld
.exec_all().MOV(dst
, ts
);
558 /* The caller wants the low 32 bits of the timestamp. Since it's running
559 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
560 * which is plenty of time for our purposes. It is identical across the
561 * EUs, but since it's tracking GPU core speed it will increment at a
562 * varying rate as render P-states change.
564 * The caller could also check if render P-states have changed (or anything
565 * else that might disrupt timing) by setting smear to 2 and checking if
566 * that field is != 0.
574 fs_visitor::emit_shader_time_begin()
576 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
580 fs_visitor::emit_shader_time_end()
582 /* Insert our code just before the final SEND with EOT. */
583 exec_node
*end
= this->instructions
.get_tail();
584 assert(end
&& ((fs_inst
*) end
)->eot
);
585 const fs_builder ibld
= bld
.annotate("shader time end")
586 .exec_all().at(NULL
, end
);
588 fs_reg shader_end_time
= get_timestamp(ibld
);
590 /* Check that there weren't any timestamp reset events (assuming these
591 * were the only two timestamp reads that happened).
593 fs_reg reset
= shader_end_time
;
595 set_condmod(BRW_CONDITIONAL_Z
,
596 ibld
.AND(ibld
.null_reg_ud(), reset
, fs_reg(1u)));
597 ibld
.IF(BRW_PREDICATE_NORMAL
);
599 fs_reg start
= shader_start_time
;
601 fs_reg diff
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
, 1);
603 ibld
.ADD(diff
, start
, shader_end_time
);
605 /* If there were no instructions between the two timestamp gets, the diff
606 * is 2 cycles. Remove that overhead, so I can forget about that when
607 * trying to determine the time taken for single instructions.
609 ibld
.ADD(diff
, diff
, fs_reg(-2u));
610 SHADER_TIME_ADD(ibld
, 0, diff
);
611 SHADER_TIME_ADD(ibld
, 1, fs_reg(1u));
612 ibld
.emit(BRW_OPCODE_ELSE
);
613 SHADER_TIME_ADD(ibld
, 2, fs_reg(1u));
614 ibld
.emit(BRW_OPCODE_ENDIF
);
618 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
619 int shader_time_subindex
,
622 int index
= shader_time_index
* 3 + shader_time_subindex
;
623 fs_reg offset
= fs_reg(index
* SHADER_TIME_STRIDE
);
626 if (dispatch_width
== 8)
627 payload
= vgrf(glsl_type::uvec2_type
);
629 payload
= vgrf(glsl_type::uint_type
);
631 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
635 fs_visitor::vfail(const char *format
, va_list va
)
644 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
645 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
647 this->fail_msg
= msg
;
650 fprintf(stderr
, "%s", msg
);
655 fs_visitor::fail(const char *format
, ...)
659 va_start(va
, format
);
665 * Mark this program as impossible to compile in SIMD16 mode.
667 * During the SIMD8 compile (which happens first), we can detect and flag
668 * things that are unsupported in SIMD16 mode, so the compiler can skip
669 * the SIMD16 compile altogether.
671 * During a SIMD16 compile (if one happens anyway), this just calls fail().
674 fs_visitor::no16(const char *msg
)
676 if (dispatch_width
== 16) {
679 simd16_unsupported
= true;
681 compiler
->shader_perf_log(log_data
,
682 "SIMD16 shader failed to compile: %s", msg
);
687 * Returns true if the instruction has a flag that means it won't
688 * update an entire destination register.
690 * For example, dead code elimination and live variable analysis want to know
691 * when a write to a variable screens off any preceding values that were in
695 fs_inst::is_partial_write() const
697 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
698 (this->dst
.width
* type_sz(this->dst
.type
)) < 32 ||
699 !this->dst
.is_contiguous());
703 fs_inst::regs_read(int arg
) const
705 if (is_tex() && arg
== 0 && src
[0].file
== GRF
) {
707 } else if (opcode
== FS_OPCODE_FB_WRITE
&& arg
== 0) {
709 } else if (opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
&& arg
== 0) {
711 } else if (opcode
== SHADER_OPCODE_UNTYPED_ATOMIC
&& arg
== 0) {
713 } else if (opcode
== SHADER_OPCODE_UNTYPED_SURFACE_READ
&& arg
== 0) {
715 } else if (opcode
== SHADER_OPCODE_UNTYPED_SURFACE_WRITE
&& arg
== 0) {
717 } else if (opcode
== SHADER_OPCODE_TYPED_ATOMIC
&& arg
== 0) {
719 } else if (opcode
== SHADER_OPCODE_TYPED_SURFACE_READ
&& arg
== 0) {
721 } else if (opcode
== SHADER_OPCODE_TYPED_SURFACE_WRITE
&& arg
== 0) {
723 } else if (opcode
== FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
&& arg
== 0) {
725 } else if (opcode
== FS_OPCODE_LINTERP
&& arg
== 0) {
726 return exec_size
/ 4;
729 switch (src
[arg
].file
) {
736 if (src
[arg
].stride
== 0) {
739 int size
= src
[arg
].width
* src
[arg
].stride
* type_sz(src
[arg
].type
);
740 return (size
+ 31) / 32;
743 unreachable("MRF registers are not allowed as sources");
745 unreachable("Invalid register file");
750 fs_inst::reads_flag() const
756 fs_inst::writes_flag() const
758 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
759 opcode
!= BRW_OPCODE_IF
&&
760 opcode
!= BRW_OPCODE_WHILE
)) ||
761 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
765 * Returns how many MRFs an FS opcode will write over.
767 * Note that this is not the 0 or 1 implied writes in an actual gen
768 * instruction -- the FS opcodes often generate MOVs in addition.
771 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
776 if (inst
->base_mrf
== -1)
779 switch (inst
->opcode
) {
780 case SHADER_OPCODE_RCP
:
781 case SHADER_OPCODE_RSQ
:
782 case SHADER_OPCODE_SQRT
:
783 case SHADER_OPCODE_EXP2
:
784 case SHADER_OPCODE_LOG2
:
785 case SHADER_OPCODE_SIN
:
786 case SHADER_OPCODE_COS
:
787 return 1 * dispatch_width
/ 8;
788 case SHADER_OPCODE_POW
:
789 case SHADER_OPCODE_INT_QUOTIENT
:
790 case SHADER_OPCODE_INT_REMAINDER
:
791 return 2 * dispatch_width
/ 8;
792 case SHADER_OPCODE_TEX
:
794 case SHADER_OPCODE_TXD
:
795 case SHADER_OPCODE_TXF
:
796 case SHADER_OPCODE_TXF_CMS
:
797 case SHADER_OPCODE_TXF_MCS
:
798 case SHADER_OPCODE_TG4
:
799 case SHADER_OPCODE_TG4_OFFSET
:
800 case SHADER_OPCODE_TXL
:
801 case SHADER_OPCODE_TXS
:
802 case SHADER_OPCODE_LOD
:
804 case FS_OPCODE_FB_WRITE
:
806 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
807 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
809 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
811 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
813 case SHADER_OPCODE_UNTYPED_ATOMIC
:
814 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
815 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
816 case SHADER_OPCODE_TYPED_ATOMIC
:
817 case SHADER_OPCODE_TYPED_SURFACE_READ
:
818 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
819 case SHADER_OPCODE_URB_WRITE_SIMD8
:
820 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
821 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
822 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
823 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
826 unreachable("not reached");
831 fs_visitor::vgrf(const glsl_type
*const type
)
833 int reg_width
= dispatch_width
/ 8;
834 return fs_reg(GRF
, alloc
.allocate(type_size(type
) * reg_width
),
835 brw_type_for_base_type(type
), dispatch_width
);
838 /** Fixed HW reg constructor. */
839 fs_reg::fs_reg(enum register_file file
, int reg
)
844 this->type
= BRW_REGISTER_TYPE_F
;
855 /** Fixed HW reg constructor. */
856 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
)
872 /** Fixed HW reg constructor. */
873 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
,
883 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
884 * This brings in those uniform definitions
887 fs_visitor::import_uniforms(fs_visitor
*v
)
889 this->push_constant_loc
= v
->push_constant_loc
;
890 this->pull_constant_loc
= v
->pull_constant_loc
;
891 this->uniforms
= v
->uniforms
;
892 this->param_size
= v
->param_size
;
896 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
897 bool origin_upper_left
)
899 assert(stage
== MESA_SHADER_FRAGMENT
);
900 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
901 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
903 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
906 if (pixel_center_integer
) {
907 bld
.MOV(wpos
, this->pixel_x
);
909 bld
.ADD(wpos
, this->pixel_x
, fs_reg(0.5f
));
911 wpos
= offset(wpos
, 1);
914 if (!flip
&& pixel_center_integer
) {
915 bld
.MOV(wpos
, this->pixel_y
);
917 fs_reg pixel_y
= this->pixel_y
;
918 float offset
= (pixel_center_integer
? 0.0 : 0.5);
921 pixel_y
.negate
= true;
922 offset
+= key
->drawable_height
- 1.0;
925 bld
.ADD(wpos
, pixel_y
, fs_reg(offset
));
927 wpos
= offset(wpos
, 1);
930 if (devinfo
->gen
>= 6) {
931 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
933 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
934 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
935 interp_reg(VARYING_SLOT_POS
, 2));
937 wpos
= offset(wpos
, 1);
939 /* gl_FragCoord.w: Already set up in emit_interpolation */
940 bld
.MOV(wpos
, this->wpos_w
);
946 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
947 glsl_interp_qualifier interpolation_mode
,
948 bool is_centroid
, bool is_sample
)
950 brw_wm_barycentric_interp_mode barycoord_mode
;
951 if (devinfo
->gen
>= 6) {
953 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
954 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
956 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
957 } else if (is_sample
) {
958 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
959 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
961 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
963 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
964 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
966 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
969 /* On Ironlake and below, there is only one interpolation mode.
970 * Centroid interpolation doesn't mean anything on this hardware --
971 * there is no multisampling.
973 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
975 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
976 this->delta_xy
[barycoord_mode
], interp
);
980 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
981 const glsl_type
*type
,
982 glsl_interp_qualifier interpolation_mode
,
983 int location
, bool mod_centroid
,
986 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
988 assert(stage
== MESA_SHADER_FRAGMENT
);
989 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
990 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
992 unsigned int array_elements
;
994 if (type
->is_array()) {
995 array_elements
= type
->length
;
996 if (array_elements
== 0) {
997 fail("dereferenced array '%s' has length 0\n", name
);
999 type
= type
->fields
.array
;
1004 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1006 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1007 if (key
->flat_shade
&& is_gl_Color
) {
1008 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1010 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1014 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1015 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1016 if (prog_data
->urb_setup
[location
] == -1) {
1017 /* If there's no incoming setup data for this slot, don't
1018 * emit interpolation for it.
1020 attr
= offset(attr
, type
->vector_elements
);
1025 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1026 /* Constant interpolation (flat shading) case. The SF has
1027 * handed us defined values in only the constant offset
1028 * field of the setup reg.
1030 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1031 struct brw_reg interp
= interp_reg(location
, k
);
1032 interp
= suboffset(interp
, 3);
1033 interp
.type
= attr
.type
;
1034 bld
.emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1035 attr
= offset(attr
, 1);
1038 /* Smooth/noperspective interpolation case. */
1039 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1040 struct brw_reg interp
= interp_reg(location
, k
);
1041 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1042 /* Get the pixel/sample mask into f0 so that we know
1043 * which pixels are lit. Then, for each channel that is
1044 * unlit, replace the centroid data with non-centroid
1047 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1050 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1052 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1053 inst
->predicate_inverse
= true;
1054 if (devinfo
->has_pln
)
1055 inst
->no_dd_clear
= true;
1057 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1058 mod_centroid
&& !key
->persample_shading
,
1059 mod_sample
|| key
->persample_shading
);
1060 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1061 inst
->predicate_inverse
= false;
1062 if (devinfo
->has_pln
)
1063 inst
->no_dd_check
= true;
1066 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1067 mod_centroid
&& !key
->persample_shading
,
1068 mod_sample
|| key
->persample_shading
);
1070 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1071 bld
.MUL(attr
, attr
, this->pixel_w
);
1073 attr
= offset(attr
, 1);
1083 fs_visitor::emit_frontfacing_interpolation()
1085 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1087 if (devinfo
->gen
>= 6) {
1088 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1089 * a boolean result from this (~0/true or 0/false).
1091 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1092 * this task in only one instruction:
1093 * - a negation source modifier will flip the bit; and
1094 * - a W -> D type conversion will sign extend the bit into the high
1095 * word of the destination.
1097 * An ASR 15 fills the low word of the destination.
1099 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1102 bld
.ASR(*reg
, g0
, fs_reg(15));
1104 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1105 * a boolean result from this (1/true or 0/false).
1107 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1108 * the negation source modifier to flip it. Unfortunately the SHR
1109 * instruction only operates on UD (or D with an abs source modifier)
1110 * sources without negation.
1112 * Instead, use ASR (which will give ~0/true or 0/false).
1114 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1117 bld
.ASR(*reg
, g1_6
, fs_reg(31));
1124 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1126 assert(stage
== MESA_SHADER_FRAGMENT
);
1127 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1128 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1130 if (key
->compute_pos_offset
) {
1131 /* Convert int_sample_pos to floating point */
1132 bld
.MOV(dst
, int_sample_pos
);
1133 /* Scale to the range [0, 1] */
1134 bld
.MUL(dst
, dst
, fs_reg(1 / 16.0f
));
1137 /* From ARB_sample_shading specification:
1138 * "When rendering to a non-multisample buffer, or if multisample
1139 * rasterization is disabled, gl_SamplePosition will always be
1142 bld
.MOV(dst
, fs_reg(0.5f
));
1147 fs_visitor::emit_samplepos_setup()
1149 assert(devinfo
->gen
>= 6);
1151 const fs_builder abld
= bld
.annotate("compute sample position");
1152 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1154 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1155 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1157 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1158 * mode will be enabled.
1160 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1161 * R31.1:0 Position Offset X/Y for Slot[3:0]
1162 * R31.3:2 Position Offset X/Y for Slot[7:4]
1165 * The X, Y sample positions come in as bytes in thread payload. So, read
1166 * the positions using vstride=16, width=8, hstride=2.
1168 struct brw_reg sample_pos_reg
=
1169 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1170 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1172 if (dispatch_width
== 8) {
1173 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1175 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1176 abld
.half(1).MOV(half(int_sample_x
, 1),
1177 fs_reg(suboffset(sample_pos_reg
, 16)));
1179 /* Compute gl_SamplePosition.x */
1180 compute_sample_position(pos
, int_sample_x
);
1181 pos
= offset(pos
, 1);
1182 if (dispatch_width
== 8) {
1183 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1185 abld
.half(0).MOV(half(int_sample_y
, 0),
1186 fs_reg(suboffset(sample_pos_reg
, 1)));
1187 abld
.half(1).MOV(half(int_sample_y
, 1),
1188 fs_reg(suboffset(sample_pos_reg
, 17)));
1190 /* Compute gl_SamplePosition.y */
1191 compute_sample_position(pos
, int_sample_y
);
1196 fs_visitor::emit_sampleid_setup()
1198 assert(stage
== MESA_SHADER_FRAGMENT
);
1199 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1200 assert(devinfo
->gen
>= 6);
1202 const fs_builder abld
= bld
.annotate("compute sample id");
1203 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1205 if (key
->compute_sample_id
) {
1206 fs_reg t1
= vgrf(glsl_type::int_type
);
1207 fs_reg t2
= vgrf(glsl_type::int_type
);
1208 t2
.type
= BRW_REGISTER_TYPE_UW
;
1210 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1211 * 8x multisampling, subspan 0 will represent sample N (where N
1212 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1213 * 7. We can find the value of N by looking at R0.0 bits 7:6
1214 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1215 * (since samples are always delivered in pairs). That is, we
1216 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1217 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1218 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1219 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1220 * populating a temporary variable with the sequence (0, 1, 2, 3),
1221 * and then reading from it using vstride=1, width=4, hstride=0.
1222 * These computations hold good for 4x multisampling as well.
1224 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1225 * the first four slots are sample 0 of subspan 0; the next four
1226 * are sample 1 of subspan 0; the third group is sample 0 of
1227 * subspan 1, and finally sample 1 of subspan 1.
1230 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1232 abld
.exec_all().SHR(t1
, t1
, fs_reg(5));
1234 /* This works for both SIMD8 and SIMD16 */
1236 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1238 /* This special instruction takes care of setting vstride=1,
1239 * width=4, hstride=0 of t2 during an ADD instruction.
1241 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1243 /* As per GL_ARB_sample_shading specification:
1244 * "When rendering to a non-multisample buffer, or if multisample
1245 * rasterization is disabled, gl_SampleID will always be zero."
1247 abld
.MOV(*reg
, fs_reg(0));
1254 fs_visitor::resolve_source_modifiers(fs_reg
*src
)
1256 if (!src
->abs
&& !src
->negate
)
1259 fs_reg temp
= bld
.vgrf(src
->type
);
1260 bld
.MOV(temp
, *src
);
1265 fs_visitor::emit_discard_jump()
1267 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1269 /* For performance, after a discard, jump to the end of the
1270 * shader if all relevant channels have been discarded.
1272 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1273 discard_jump
->flag_subreg
= 1;
1275 discard_jump
->predicate
= (dispatch_width
== 8)
1276 ? BRW_PREDICATE_ALIGN1_ANY8H
1277 : BRW_PREDICATE_ALIGN1_ANY16H
;
1278 discard_jump
->predicate_inverse
= true;
1282 fs_visitor::assign_curb_setup()
1284 if (dispatch_width
== 8) {
1285 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1287 if (stage
== MESA_SHADER_FRAGMENT
) {
1288 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1289 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1290 } else if (stage
== MESA_SHADER_COMPUTE
) {
1291 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1292 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1294 unreachable("Unsupported shader type!");
1298 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1300 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1301 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1302 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1303 if (inst
->src
[i
].file
== UNIFORM
) {
1304 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1306 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1307 constant_nr
= push_constant_loc
[uniform_nr
];
1309 /* Section 5.11 of the OpenGL 4.1 spec says:
1310 * "Out-of-bounds reads return undefined values, which include
1311 * values from other variables of the active program or zero."
1312 * Just return the first push constant.
1317 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1321 inst
->src
[i
].file
= HW_REG
;
1322 inst
->src
[i
].fixed_hw_reg
= byte_offset(
1323 retype(brw_reg
, inst
->src
[i
].type
),
1324 inst
->src
[i
].subreg_offset
);
1331 fs_visitor::calculate_urb_setup()
1333 assert(stage
== MESA_SHADER_FRAGMENT
);
1334 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1335 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1337 memset(prog_data
->urb_setup
, -1,
1338 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1341 /* Figure out where each of the incoming setup attributes lands. */
1342 if (devinfo
->gen
>= 6) {
1343 if (_mesa_bitcount_64(prog
->InputsRead
&
1344 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1345 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1346 * first 16 varying inputs, so we can put them wherever we want.
1347 * Just put them in order.
1349 * This is useful because it means that (a) inputs not used by the
1350 * fragment shader won't take up valuable register space, and (b) we
1351 * won't have to recompile the fragment shader if it gets paired with
1352 * a different vertex (or geometry) shader.
1354 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1355 if (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1356 BITFIELD64_BIT(i
)) {
1357 prog_data
->urb_setup
[i
] = urb_next
++;
1361 /* We have enough input varyings that the SF/SBE pipeline stage can't
1362 * arbitrarily rearrange them to suit our whim; we have to put them
1363 * in an order that matches the output of the previous pipeline stage
1364 * (geometry or vertex shader).
1366 struct brw_vue_map prev_stage_vue_map
;
1367 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1368 key
->input_slots_valid
);
1369 int first_slot
= 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1370 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1371 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1373 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1374 /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
1377 if (varying
!= BRW_VARYING_SLOT_COUNT
&&
1378 (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1379 BITFIELD64_BIT(varying
))) {
1380 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1383 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1386 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1387 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1388 /* Point size is packed into the header, not as a general attribute */
1389 if (i
== VARYING_SLOT_PSIZ
)
1392 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1393 /* The back color slot is skipped when the front color is
1394 * also written to. In addition, some slots can be
1395 * written in the vertex shader and not read in the
1396 * fragment shader. So the register number must always be
1397 * incremented, mapped or not.
1399 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1400 prog_data
->urb_setup
[i
] = urb_next
;
1406 * It's a FS only attribute, and we did interpolation for this attribute
1407 * in SF thread. So, count it here, too.
1409 * See compile_sf_prog() for more info.
1411 if (prog
->InputsRead
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1412 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1415 prog_data
->num_varying_inputs
= urb_next
;
1419 fs_visitor::assign_urb_setup()
1421 assert(stage
== MESA_SHADER_FRAGMENT
);
1422 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1424 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1426 /* Offset all the urb_setup[] index by the actual position of the
1427 * setup regs, now that the location of the constants has been chosen.
1429 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1430 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1431 assert(inst
->src
[1].file
== HW_REG
);
1432 inst
->src
[1].fixed_hw_reg
.nr
+= urb_start
;
1435 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1436 assert(inst
->src
[0].file
== HW_REG
);
1437 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1441 /* Each attribute is 4 setup channels, each of which is half a reg. */
1442 this->first_non_payload_grf
=
1443 urb_start
+ prog_data
->num_varying_inputs
* 2;
1447 fs_visitor::assign_vs_urb_setup()
1449 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1450 int grf
, count
, slot
, channel
, attr
;
1452 assert(stage
== MESA_SHADER_VERTEX
);
1453 count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1454 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1457 /* Each attribute is 4 regs. */
1458 this->first_non_payload_grf
=
1459 payload
.num_regs
+ prog_data
->curb_read_length
+ count
* 4;
1461 unsigned vue_entries
=
1462 MAX2(count
, vs_prog_data
->base
.vue_map
.num_slots
);
1464 /* URB entry size is counted in units of 64 bytes (for the 3DSTATE_URB_VS
1465 * command). Each attribute is 16 bytes (4 floats/dwords), so each unit
1466 * fits four attributes.
1468 vs_prog_data
->base
.urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1469 vs_prog_data
->base
.urb_read_length
= (count
+ 1) / 2;
1471 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1473 /* Rewrite all ATTR file references to the hw grf that they land in. */
1474 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1475 for (int i
= 0; i
< inst
->sources
; i
++) {
1476 if (inst
->src
[i
].file
== ATTR
) {
1478 if (inst
->src
[i
].reg
== VERT_ATTRIB_MAX
) {
1481 /* Attributes come in in a contiguous block, ordered by their
1482 * gl_vert_attrib value. That means we can compute the slot
1483 * number for an attribute by masking out the enabled
1484 * attributes before it and counting the bits.
1486 attr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
/ 4;
1487 slot
= _mesa_bitcount_64(vs_prog_data
->inputs_read
&
1488 BITFIELD64_MASK(attr
));
1491 channel
= inst
->src
[i
].reg_offset
& 3;
1493 grf
= payload
.num_regs
+
1494 prog_data
->curb_read_length
+
1497 inst
->src
[i
].file
= HW_REG
;
1498 inst
->src
[i
].fixed_hw_reg
=
1499 retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
);
1506 * Split large virtual GRFs into separate components if we can.
1508 * This is mostly duplicated with what brw_fs_vector_splitting does,
1509 * but that's really conservative because it's afraid of doing
1510 * splitting that doesn't result in real progress after the rest of
1511 * the optimization phases, which would cause infinite looping in
1512 * optimization. We can do it once here, safely. This also has the
1513 * opportunity to split interpolated values, or maybe even uniforms,
1514 * which we don't have at the IR level.
1516 * We want to split, because virtual GRFs are what we register
1517 * allocate and spill (due to contiguousness requirements for some
1518 * instructions), and they're what we naturally generate in the
1519 * codegen process, but most virtual GRFs don't actually need to be
1520 * contiguous sets of GRFs. If we split, we'll end up with reduced
1521 * live intervals and better dead code elimination and coalescing.
1524 fs_visitor::split_virtual_grfs()
1526 int num_vars
= this->alloc
.count
;
1528 /* Count the total number of registers */
1530 int vgrf_to_reg
[num_vars
];
1531 for (int i
= 0; i
< num_vars
; i
++) {
1532 vgrf_to_reg
[i
] = reg_count
;
1533 reg_count
+= alloc
.sizes
[i
];
1536 /* An array of "split points". For each register slot, this indicates
1537 * if this slot can be separated from the previous slot. Every time an
1538 * instruction uses multiple elements of a register (as a source or
1539 * destination), we mark the used slots as inseparable. Then we go
1540 * through and split the registers into the smallest pieces we can.
1542 bool split_points
[reg_count
];
1543 memset(split_points
, 0, sizeof(split_points
));
1545 /* Mark all used registers as fully splittable */
1546 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1547 if (inst
->dst
.file
== GRF
) {
1548 int reg
= vgrf_to_reg
[inst
->dst
.reg
];
1549 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.reg
]; j
++)
1550 split_points
[reg
+ j
] = true;
1553 for (int i
= 0; i
< inst
->sources
; i
++) {
1554 if (inst
->src
[i
].file
== GRF
) {
1555 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
];
1556 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].reg
]; j
++)
1557 split_points
[reg
+ j
] = true;
1562 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1563 if (inst
->dst
.file
== GRF
) {
1564 int reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1565 for (int j
= 1; j
< inst
->regs_written
; j
++)
1566 split_points
[reg
+ j
] = false;
1568 for (int i
= 0; i
< inst
->sources
; i
++) {
1569 if (inst
->src
[i
].file
== GRF
) {
1570 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1571 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1572 split_points
[reg
+ j
] = false;
1577 int new_virtual_grf
[reg_count
];
1578 int new_reg_offset
[reg_count
];
1581 for (int i
= 0; i
< num_vars
; i
++) {
1582 /* The first one should always be 0 as a quick sanity check. */
1583 assert(split_points
[reg
] == false);
1586 new_reg_offset
[reg
] = 0;
1591 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1592 /* If this is a split point, reset the offset to 0 and allocate a
1593 * new virtual GRF for the previous offset many registers
1595 if (split_points
[reg
]) {
1596 assert(offset
<= MAX_VGRF_SIZE
);
1597 int grf
= alloc
.allocate(offset
);
1598 for (int k
= reg
- offset
; k
< reg
; k
++)
1599 new_virtual_grf
[k
] = grf
;
1602 new_reg_offset
[reg
] = offset
;
1607 /* The last one gets the original register number */
1608 assert(offset
<= MAX_VGRF_SIZE
);
1609 alloc
.sizes
[i
] = offset
;
1610 for (int k
= reg
- offset
; k
< reg
; k
++)
1611 new_virtual_grf
[k
] = i
;
1613 assert(reg
== reg_count
);
1615 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1616 if (inst
->dst
.file
== GRF
) {
1617 reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1618 inst
->dst
.reg
= new_virtual_grf
[reg
];
1619 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1620 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1622 for (int i
= 0; i
< inst
->sources
; i
++) {
1623 if (inst
->src
[i
].file
== GRF
) {
1624 reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1625 inst
->src
[i
].reg
= new_virtual_grf
[reg
];
1626 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1627 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1631 invalidate_live_intervals();
1635 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1637 * During code generation, we create tons of temporary variables, many of
1638 * which get immediately killed and are never used again. Yet, in later
1639 * optimization and analysis passes, such as compute_live_intervals, we need
1640 * to loop over all the virtual GRFs. Compacting them can save a lot of
1644 fs_visitor::compact_virtual_grfs()
1646 bool progress
= false;
1647 int remap_table
[this->alloc
.count
];
1648 memset(remap_table
, -1, sizeof(remap_table
));
1650 /* Mark which virtual GRFs are used. */
1651 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1652 if (inst
->dst
.file
== GRF
)
1653 remap_table
[inst
->dst
.reg
] = 0;
1655 for (int i
= 0; i
< inst
->sources
; i
++) {
1656 if (inst
->src
[i
].file
== GRF
)
1657 remap_table
[inst
->src
[i
].reg
] = 0;
1661 /* Compact the GRF arrays. */
1663 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1664 if (remap_table
[i
] == -1) {
1665 /* We just found an unused register. This means that we are
1666 * actually going to compact something.
1670 remap_table
[i
] = new_index
;
1671 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1672 invalidate_live_intervals();
1677 this->alloc
.count
= new_index
;
1679 /* Patch all the instructions to use the newly renumbered registers */
1680 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1681 if (inst
->dst
.file
== GRF
)
1682 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
1684 for (int i
= 0; i
< inst
->sources
; i
++) {
1685 if (inst
->src
[i
].file
== GRF
)
1686 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
1690 /* Patch all the references to delta_xy, since they're used in register
1691 * allocation. If they're unused, switch them to BAD_FILE so we don't
1692 * think some random VGRF is delta_xy.
1694 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1695 if (delta_xy
[i
].file
== GRF
) {
1696 if (remap_table
[delta_xy
[i
].reg
] != -1) {
1697 delta_xy
[i
].reg
= remap_table
[delta_xy
[i
].reg
];
1699 delta_xy
[i
].file
= BAD_FILE
;
1708 * Implements array access of uniforms by inserting a
1709 * PULL_CONSTANT_LOAD instruction.
1711 * Unlike temporary GRF array access (where we don't support it due to
1712 * the difficulty of doing relative addressing on instruction
1713 * destinations), we could potentially do array access of uniforms
1714 * that were loaded in GRF space as push constants. In real-world
1715 * usage we've seen, though, the arrays being used are always larger
1716 * than we could load as push constants, so just always move all
1717 * uniform array access out to a pull constant buffer.
1720 fs_visitor::move_uniform_array_access_to_pull_constants()
1722 if (dispatch_width
!= 8)
1725 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1726 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1728 /* Walk through and find array access of uniforms. Put a copy of that
1729 * uniform in the pull constant buffer.
1731 * Note that we don't move constant-indexed accesses to arrays. No
1732 * testing has been done of the performance impact of this choice.
1734 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1735 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1736 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
1739 int uniform
= inst
->src
[i
].reg
;
1741 /* If this array isn't already present in the pull constant buffer,
1744 if (pull_constant_loc
[uniform
] == -1) {
1745 const gl_constant_value
**values
= &stage_prog_data
->param
[uniform
];
1747 assert(param_size
[uniform
]);
1749 for (int j
= 0; j
< param_size
[uniform
]; j
++) {
1750 pull_constant_loc
[uniform
+ j
] = stage_prog_data
->nr_pull_params
;
1752 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
1761 * Assign UNIFORM file registers to either push constants or pull constants.
1763 * We allow a fragment shader to have more than the specified minimum
1764 * maximum number of fragment shader uniform components (64). If
1765 * there are too many of these, they'd fill up all of register space.
1766 * So, this will push some of them out to the pull constant buffer and
1767 * update the program to load them.
1770 fs_visitor::assign_constant_locations()
1772 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1773 if (dispatch_width
!= 8)
1776 /* Find which UNIFORM registers are still in use. */
1777 bool is_live
[uniforms
];
1778 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1782 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1783 for (int i
= 0; i
< inst
->sources
; i
++) {
1784 if (inst
->src
[i
].file
!= UNIFORM
)
1787 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1788 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1789 is_live
[constant_nr
] = true;
1793 /* Only allow 16 registers (128 uniform components) as push constants.
1795 * Just demote the end of the list. We could probably do better
1796 * here, demoting things that are rarely used in the program first.
1798 * If changing this value, note the limitation about total_regs in
1801 unsigned int max_push_components
= 16 * 8;
1802 unsigned int num_push_constants
= 0;
1804 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1806 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1807 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1808 /* This UNIFORM register is either dead, or has already been demoted
1809 * to a pull const. Mark it as no longer living in the param[] array.
1811 push_constant_loc
[i
] = -1;
1815 if (num_push_constants
< max_push_components
) {
1816 /* Retain as a push constant. Record the location in the params[]
1819 push_constant_loc
[i
] = num_push_constants
++;
1821 /* Demote to a pull constant. */
1822 push_constant_loc
[i
] = -1;
1824 int pull_index
= stage_prog_data
->nr_pull_params
++;
1825 stage_prog_data
->pull_param
[pull_index
] = stage_prog_data
->param
[i
];
1826 pull_constant_loc
[i
] = pull_index
;
1830 stage_prog_data
->nr_params
= num_push_constants
;
1832 /* Up until now, the param[] array has been indexed by reg + reg_offset
1833 * of UNIFORM registers. Condense it to only contain the uniforms we
1834 * chose to upload as push constants.
1836 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1837 int remapped
= push_constant_loc
[i
];
1842 assert(remapped
<= (int)i
);
1843 stage_prog_data
->param
[remapped
] = stage_prog_data
->param
[i
];
1848 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
1849 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
1852 fs_visitor::demote_pull_constants()
1854 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1855 for (int i
= 0; i
< inst
->sources
; i
++) {
1856 if (inst
->src
[i
].file
!= UNIFORM
)
1860 unsigned location
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1861 if (location
>= uniforms
) /* Out of bounds access */
1864 pull_index
= pull_constant_loc
[location
];
1866 if (pull_index
== -1)
1869 /* Set up the annotation tracking for new generated instructions. */
1870 const fs_builder ibld
= bld
.annotate(inst
->annotation
, inst
->ir
)
1872 fs_reg
surf_index(stage_prog_data
->binding_table
.pull_constants_start
);
1873 fs_reg dst
= vgrf(glsl_type::float_type
);
1875 /* Generate a pull load into dst. */
1876 if (inst
->src
[i
].reladdr
) {
1877 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
1879 *inst
->src
[i
].reladdr
,
1881 inst
->src
[i
].reladdr
= NULL
;
1883 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
1884 ibld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
1885 dst
, surf_index
, offset
);
1886 inst
->src
[i
].set_smear(pull_index
& 3);
1889 /* Rewrite the instruction to use the temporary VGRF. */
1890 inst
->src
[i
].file
= GRF
;
1891 inst
->src
[i
].reg
= dst
.reg
;
1892 inst
->src
[i
].reg_offset
= 0;
1893 inst
->src
[i
].width
= dispatch_width
;
1896 invalidate_live_intervals();
1900 fs_visitor::opt_algebraic()
1902 bool progress
= false;
1904 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1905 switch (inst
->opcode
) {
1906 case BRW_OPCODE_MOV
:
1907 if (inst
->src
[0].file
!= IMM
)
1910 if (inst
->saturate
) {
1911 if (inst
->dst
.type
!= inst
->src
[0].type
)
1912 assert(!"unimplemented: saturate mixed types");
1914 if (brw_saturate_immediate(inst
->dst
.type
,
1915 &inst
->src
[0].fixed_hw_reg
)) {
1916 inst
->saturate
= false;
1922 case BRW_OPCODE_MUL
:
1923 if (inst
->src
[1].file
!= IMM
)
1927 if (inst
->src
[1].is_one()) {
1928 inst
->opcode
= BRW_OPCODE_MOV
;
1929 inst
->src
[1] = reg_undef
;
1935 if (inst
->src
[1].is_negative_one()) {
1936 inst
->opcode
= BRW_OPCODE_MOV
;
1937 inst
->src
[0].negate
= !inst
->src
[0].negate
;
1938 inst
->src
[1] = reg_undef
;
1944 if (inst
->src
[1].is_zero()) {
1945 inst
->opcode
= BRW_OPCODE_MOV
;
1946 inst
->src
[0] = inst
->src
[1];
1947 inst
->src
[1] = reg_undef
;
1952 if (inst
->src
[0].file
== IMM
) {
1953 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
1954 inst
->opcode
= BRW_OPCODE_MOV
;
1955 inst
->src
[0].fixed_hw_reg
.dw1
.f
*= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
1956 inst
->src
[1] = reg_undef
;
1961 case BRW_OPCODE_ADD
:
1962 if (inst
->src
[1].file
!= IMM
)
1966 if (inst
->src
[1].is_zero()) {
1967 inst
->opcode
= BRW_OPCODE_MOV
;
1968 inst
->src
[1] = reg_undef
;
1973 if (inst
->src
[0].file
== IMM
) {
1974 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
1975 inst
->opcode
= BRW_OPCODE_MOV
;
1976 inst
->src
[0].fixed_hw_reg
.dw1
.f
+= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
1977 inst
->src
[1] = reg_undef
;
1983 if (inst
->src
[0].equals(inst
->src
[1])) {
1984 inst
->opcode
= BRW_OPCODE_MOV
;
1985 inst
->src
[1] = reg_undef
;
1990 case BRW_OPCODE_LRP
:
1991 if (inst
->src
[1].equals(inst
->src
[2])) {
1992 inst
->opcode
= BRW_OPCODE_MOV
;
1993 inst
->src
[0] = inst
->src
[1];
1994 inst
->src
[1] = reg_undef
;
1995 inst
->src
[2] = reg_undef
;
2000 case BRW_OPCODE_CMP
:
2001 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2003 inst
->src
[0].negate
&&
2004 inst
->src
[1].is_zero()) {
2005 inst
->src
[0].abs
= false;
2006 inst
->src
[0].negate
= false;
2007 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2012 case BRW_OPCODE_SEL
:
2013 if (inst
->src
[0].equals(inst
->src
[1])) {
2014 inst
->opcode
= BRW_OPCODE_MOV
;
2015 inst
->src
[1] = reg_undef
;
2016 inst
->predicate
= BRW_PREDICATE_NONE
;
2017 inst
->predicate_inverse
= false;
2019 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2020 switch (inst
->conditional_mod
) {
2021 case BRW_CONDITIONAL_LE
:
2022 case BRW_CONDITIONAL_L
:
2023 switch (inst
->src
[1].type
) {
2024 case BRW_REGISTER_TYPE_F
:
2025 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
>= 1.0f
) {
2026 inst
->opcode
= BRW_OPCODE_MOV
;
2027 inst
->src
[1] = reg_undef
;
2028 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2036 case BRW_CONDITIONAL_GE
:
2037 case BRW_CONDITIONAL_G
:
2038 switch (inst
->src
[1].type
) {
2039 case BRW_REGISTER_TYPE_F
:
2040 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
<= 0.0f
) {
2041 inst
->opcode
= BRW_OPCODE_MOV
;
2042 inst
->src
[1] = reg_undef
;
2043 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2055 case BRW_OPCODE_MAD
:
2056 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2057 inst
->opcode
= BRW_OPCODE_MOV
;
2058 inst
->src
[1] = reg_undef
;
2059 inst
->src
[2] = reg_undef
;
2061 } else if (inst
->src
[0].is_zero()) {
2062 inst
->opcode
= BRW_OPCODE_MUL
;
2063 inst
->src
[0] = inst
->src
[2];
2064 inst
->src
[2] = reg_undef
;
2066 } else if (inst
->src
[1].is_one()) {
2067 inst
->opcode
= BRW_OPCODE_ADD
;
2068 inst
->src
[1] = inst
->src
[2];
2069 inst
->src
[2] = reg_undef
;
2071 } else if (inst
->src
[2].is_one()) {
2072 inst
->opcode
= BRW_OPCODE_ADD
;
2073 inst
->src
[2] = reg_undef
;
2075 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2076 inst
->opcode
= BRW_OPCODE_ADD
;
2077 inst
->src
[1].fixed_hw_reg
.dw1
.f
*= inst
->src
[2].fixed_hw_reg
.dw1
.f
;
2078 inst
->src
[2] = reg_undef
;
2082 case SHADER_OPCODE_RCP
: {
2083 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2084 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2085 if (inst
->src
[0].equals(prev
->dst
)) {
2086 inst
->opcode
= SHADER_OPCODE_RSQ
;
2087 inst
->src
[0] = prev
->src
[0];
2093 case SHADER_OPCODE_BROADCAST
:
2094 if (is_uniform(inst
->src
[0])) {
2095 inst
->opcode
= BRW_OPCODE_MOV
;
2097 inst
->force_writemask_all
= true;
2099 } else if (inst
->src
[1].file
== IMM
) {
2100 inst
->opcode
= BRW_OPCODE_MOV
;
2101 inst
->src
[0] = component(inst
->src
[0],
2102 inst
->src
[1].fixed_hw_reg
.dw1
.ud
);
2104 inst
->force_writemask_all
= true;
2113 /* Swap if src[0] is immediate. */
2114 if (progress
&& inst
->is_commutative()) {
2115 if (inst
->src
[0].file
== IMM
) {
2116 fs_reg tmp
= inst
->src
[1];
2117 inst
->src
[1] = inst
->src
[0];
2126 * Optimize sample messages that have constant zero values for the trailing
2127 * texture coordinates. We can just reduce the message length for these
2128 * instructions instead of reserving a register for it. Trailing parameters
2129 * that aren't sent default to zero anyway. This will cause the dead code
2130 * eliminator to remove the MOV instruction that would otherwise be emitted to
2131 * set up the zero value.
2134 fs_visitor::opt_zero_samples()
2136 /* Gen4 infers the texturing opcode based on the message length so we can't
2139 if (devinfo
->gen
< 5)
2142 bool progress
= false;
2144 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2145 if (!inst
->is_tex())
2148 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2150 if (load_payload
->is_head_sentinel() ||
2151 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2154 /* We don't want to remove the message header or the first parameter.
2155 * Removing the first parameter is not allowed, see the Haswell PRM
2156 * volume 7, page 149:
2158 * "Parameter 0 is required except for the sampleinfo message, which
2159 * has no parameter 0"
2161 while (inst
->mlen
> inst
->header_size
+ dispatch_width
/ 8 &&
2162 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2163 (dispatch_width
/ 8) +
2164 inst
->header_size
- 1].is_zero()) {
2165 inst
->mlen
-= dispatch_width
/ 8;
2171 invalidate_live_intervals();
2177 * Optimize sample messages which are followed by the final RT write.
2179 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2180 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2181 * final texturing results copied to the framebuffer write payload and modify
2182 * them to write to the framebuffer directly.
2185 fs_visitor::opt_sampler_eot()
2187 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2189 if (stage
!= MESA_SHADER_FRAGMENT
)
2192 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2195 /* FINISHME: It should be possible to implement this optimization when there
2196 * are multiple drawbuffers.
2198 if (key
->nr_color_regions
!= 1)
2201 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2202 fs_inst
*fb_write
= (fs_inst
*) cfg
->blocks
[cfg
->num_blocks
- 1]->end();
2203 assert(fb_write
->eot
);
2204 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2206 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2208 /* There wasn't one; nothing to do. */
2209 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2212 /* This optimisation doesn't seem to work for textureGather for some
2213 * reason. I can't find any documentation or known workarounds to indicate
2214 * that this is expected, but considering that it is probably pretty
2215 * unlikely that a shader would directly write out the results from
2216 * textureGather we might as well just disable it.
2218 if (tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2219 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2222 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2223 * It's very likely to be the previous instruction.
2225 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2226 if (load_payload
->is_head_sentinel() ||
2227 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2230 assert(!tex_inst
->eot
); /* We can't get here twice */
2231 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2233 tex_inst
->offset
|= fb_write
->target
<< 24;
2234 tex_inst
->eot
= true;
2235 tex_inst
->dst
= bld
.null_reg_ud();
2236 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2238 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2239 * to create a new LOAD_PAYLOAD command with the same sources and a space
2240 * saved for the header. Using a new destination register not only makes sure
2241 * we have enough space, but it will make sure the dead code eliminator kills
2242 * the instruction that this will replace.
2244 if (tex_inst
->header_size
!= 0)
2247 fs_reg send_header
= bld
.vgrf(BRW_REGISTER_TYPE_F
,
2248 load_payload
->sources
+ 1);
2249 fs_reg
*new_sources
=
2250 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2252 new_sources
[0] = fs_reg();
2253 for (int i
= 0; i
< load_payload
->sources
; i
++)
2254 new_sources
[i
+1] = load_payload
->src
[i
];
2256 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2257 * requires a lot of information about the sources to appropriately figure
2258 * out the number of registers needed to be used. Given this stage in our
2259 * optimization, we may not have the appropriate GRFs required by
2260 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2261 * manually emit the instruction.
2263 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2264 load_payload
->exec_size
,
2267 load_payload
->sources
+ 1);
2269 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2270 new_load_payload
->header_size
= 1;
2272 tex_inst
->header_size
= 1;
2273 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2274 tex_inst
->src
[0] = send_header
;
2280 fs_visitor::opt_register_renaming()
2282 bool progress
= false;
2285 int remap
[alloc
.count
];
2286 memset(remap
, -1, sizeof(int) * alloc
.count
);
2288 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2289 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2291 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2292 inst
->opcode
== BRW_OPCODE_WHILE
) {
2296 /* Rewrite instruction sources. */
2297 for (int i
= 0; i
< inst
->sources
; i
++) {
2298 if (inst
->src
[i
].file
== GRF
&&
2299 remap
[inst
->src
[i
].reg
] != -1 &&
2300 remap
[inst
->src
[i
].reg
] != inst
->src
[i
].reg
) {
2301 inst
->src
[i
].reg
= remap
[inst
->src
[i
].reg
];
2306 const int dst
= inst
->dst
.reg
;
2309 inst
->dst
.file
== GRF
&&
2310 alloc
.sizes
[inst
->dst
.reg
] == inst
->dst
.width
/ 8 &&
2311 !inst
->is_partial_write()) {
2312 if (remap
[dst
] == -1) {
2315 remap
[dst
] = alloc
.allocate(inst
->dst
.width
/ 8);
2316 inst
->dst
.reg
= remap
[dst
];
2319 } else if (inst
->dst
.file
== GRF
&&
2321 remap
[dst
] != dst
) {
2322 inst
->dst
.reg
= remap
[dst
];
2328 invalidate_live_intervals();
2330 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2331 if (delta_xy
[i
].file
== GRF
&& remap
[delta_xy
[i
].reg
] != -1) {
2332 delta_xy
[i
].reg
= remap
[delta_xy
[i
].reg
];
2341 * Remove redundant or useless discard jumps.
2343 * For example, we can eliminate jumps in the following sequence:
2345 * discard-jump (redundant with the next jump)
2346 * discard-jump (useless; jumps to the next instruction)
2350 fs_visitor::opt_redundant_discard_jumps()
2352 bool progress
= false;
2354 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2356 fs_inst
*placeholder_halt
= NULL
;
2357 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2358 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2359 placeholder_halt
= inst
;
2364 if (!placeholder_halt
)
2367 /* Delete any HALTs immediately before the placeholder halt. */
2368 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2369 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2370 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2371 prev
->remove(last_bblock
);
2376 invalidate_live_intervals();
2382 fs_visitor::compute_to_mrf()
2384 bool progress
= false;
2387 /* No MRFs on Gen >= 7. */
2388 if (devinfo
->gen
>= 7)
2391 calculate_live_intervals();
2393 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2397 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2398 inst
->is_partial_write() ||
2399 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2400 inst
->dst
.type
!= inst
->src
[0].type
||
2401 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2402 !inst
->src
[0].is_contiguous() ||
2403 inst
->src
[0].subreg_offset
)
2406 /* Work out which hardware MRF registers are written by this
2409 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2411 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2412 mrf_high
= mrf_low
+ 4;
2413 } else if (inst
->exec_size
== 16) {
2414 mrf_high
= mrf_low
+ 1;
2419 /* Can't compute-to-MRF this GRF if someone else was going to
2422 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2425 /* Found a move of a GRF to a MRF. Let's see if we can go
2426 * rewrite the thing that made this GRF to write into the MRF.
2428 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2429 if (scan_inst
->dst
.file
== GRF
&&
2430 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2431 /* Found the last thing to write our reg we want to turn
2432 * into a compute-to-MRF.
2435 /* If this one instruction didn't populate all the
2436 * channels, bail. We might be able to rewrite everything
2437 * that writes that reg, but it would require smarter
2438 * tracking to delay the rewriting until complete success.
2440 if (scan_inst
->is_partial_write())
2443 /* Things returning more than one register would need us to
2444 * understand coalescing out more than one MOV at a time.
2446 if (scan_inst
->regs_written
> scan_inst
->dst
.width
/ 8)
2449 /* SEND instructions can't have MRF as a destination. */
2450 if (scan_inst
->mlen
)
2453 if (devinfo
->gen
== 6) {
2454 /* gen6 math instructions must have the destination be
2455 * GRF, so no compute-to-MRF for them.
2457 if (scan_inst
->is_math()) {
2462 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2463 /* Found the creator of our MRF's source value. */
2464 scan_inst
->dst
.file
= MRF
;
2465 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2466 scan_inst
->saturate
|= inst
->saturate
;
2467 inst
->remove(block
);
2473 /* We don't handle control flow here. Most computation of
2474 * values that end up in MRFs are shortly before the MRF
2477 if (block
->start() == scan_inst
)
2480 /* You can't read from an MRF, so if someone else reads our
2481 * MRF's source GRF that we wanted to rewrite, that stops us.
2483 bool interfered
= false;
2484 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2485 if (scan_inst
->src
[i
].file
== GRF
&&
2486 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2487 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2494 if (scan_inst
->dst
.file
== MRF
) {
2495 /* If somebody else writes our MRF here, we can't
2496 * compute-to-MRF before that.
2498 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2501 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2502 scan_mrf_high
= scan_mrf_low
+ 4;
2503 } else if (scan_inst
->exec_size
== 16) {
2504 scan_mrf_high
= scan_mrf_low
+ 1;
2506 scan_mrf_high
= scan_mrf_low
;
2509 if (mrf_low
== scan_mrf_low
||
2510 mrf_low
== scan_mrf_high
||
2511 mrf_high
== scan_mrf_low
||
2512 mrf_high
== scan_mrf_high
) {
2517 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2518 /* Found a SEND instruction, which means that there are
2519 * live values in MRFs from base_mrf to base_mrf +
2520 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2523 if (mrf_low
>= scan_inst
->base_mrf
&&
2524 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2527 if (mrf_high
>= scan_inst
->base_mrf
&&
2528 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2536 invalidate_live_intervals();
2542 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2543 * flow. We could probably do better here with some form of divergence
2547 fs_visitor::eliminate_find_live_channel()
2549 bool progress
= false;
2552 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2553 switch (inst
->opcode
) {
2559 case BRW_OPCODE_ENDIF
:
2560 case BRW_OPCODE_WHILE
:
2564 case FS_OPCODE_DISCARD_JUMP
:
2565 /* This can potentially make control flow non-uniform until the end
2570 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2572 inst
->opcode
= BRW_OPCODE_MOV
;
2573 inst
->src
[0] = fs_reg(0);
2575 inst
->force_writemask_all
= true;
2589 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2590 * instructions to FS_OPCODE_REP_FB_WRITE.
2593 fs_visitor::emit_repclear_shader()
2595 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2597 int color_mrf
= base_mrf
+ 2;
2600 if (uniforms
== 1) {
2601 mov
= bld
.exec_all().MOV(vec4(brw_message_reg(color_mrf
)),
2602 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2604 struct brw_reg reg
=
2605 brw_reg(BRW_GENERAL_REGISTER_FILE
,
2606 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2607 BRW_VERTICAL_STRIDE_8
,
2609 BRW_HORIZONTAL_STRIDE_4
, BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2611 mov
= bld
.exec_all().MOV(vec4(brw_message_reg(color_mrf
)),
2616 if (key
->nr_color_regions
== 1) {
2617 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2618 write
->saturate
= key
->clamp_fragment_color
;
2619 write
->base_mrf
= color_mrf
;
2621 write
->header_size
= 0;
2624 assume(key
->nr_color_regions
> 0);
2625 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2626 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2627 write
->saturate
= key
->clamp_fragment_color
;
2628 write
->base_mrf
= base_mrf
;
2630 write
->header_size
= 2;
2638 assign_constant_locations();
2639 assign_curb_setup();
2641 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2642 if (uniforms
== 1) {
2643 assert(mov
->src
[0].file
== HW_REG
);
2644 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].fixed_hw_reg
.nr
, 0);
2649 * Walks through basic blocks, looking for repeated MRF writes and
2650 * removing the later ones.
2653 fs_visitor::remove_duplicate_mrf_writes()
2655 fs_inst
*last_mrf_move
[16];
2656 bool progress
= false;
2658 /* Need to update the MRF tracking for compressed instructions. */
2659 if (dispatch_width
== 16)
2662 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2664 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2665 if (inst
->is_control_flow()) {
2666 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2669 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2670 inst
->dst
.file
== MRF
) {
2671 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2672 if (prev_inst
&& inst
->equals(prev_inst
)) {
2673 inst
->remove(block
);
2679 /* Clear out the last-write records for MRFs that were overwritten. */
2680 if (inst
->dst
.file
== MRF
) {
2681 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2684 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2685 /* Found a SEND instruction, which will include two or fewer
2686 * implied MRF writes. We could do better here.
2688 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2689 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2693 /* Clear out any MRF move records whose sources got overwritten. */
2694 if (inst
->dst
.file
== GRF
) {
2695 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2696 if (last_mrf_move
[i
] &&
2697 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2698 last_mrf_move
[i
] = NULL
;
2703 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2704 inst
->dst
.file
== MRF
&&
2705 inst
->src
[0].file
== GRF
&&
2706 !inst
->is_partial_write()) {
2707 last_mrf_move
[inst
->dst
.reg
] = inst
;
2712 invalidate_live_intervals();
2718 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2720 /* Clear the flag for registers that actually got read (as expected). */
2721 for (int i
= 0; i
< inst
->sources
; i
++) {
2723 if (inst
->src
[i
].file
== GRF
) {
2724 grf
= inst
->src
[i
].reg
;
2725 } else if (inst
->src
[i
].file
== HW_REG
&&
2726 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
2727 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
2732 if (grf
>= first_grf
&&
2733 grf
< first_grf
+ grf_len
) {
2734 deps
[grf
- first_grf
] = false;
2735 if (inst
->exec_size
== 16)
2736 deps
[grf
- first_grf
+ 1] = false;
2742 * Implements this workaround for the original 965:
2744 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2745 * check for post destination dependencies on this instruction, software
2746 * must ensure that there is no destination hazard for the case of ‘write
2747 * followed by a posted write’ shown in the following example.
2750 * 2. send r3.xy <rest of send instruction>
2753 * Due to no post-destination dependency check on the ‘send’, the above
2754 * code sequence could have two instructions (1 and 2) in flight at the
2755 * same time that both consider ‘r3’ as the target of their final writes.
2758 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2761 int write_len
= inst
->regs_written
;
2762 int first_write_grf
= inst
->dst
.reg
;
2763 bool needs_dep
[BRW_MAX_MRF
];
2764 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2766 memset(needs_dep
, false, sizeof(needs_dep
));
2767 memset(needs_dep
, true, write_len
);
2769 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2771 /* Walk backwards looking for writes to registers we're writing which
2772 * aren't read since being written. If we hit the start of the program,
2773 * we assume that there are no outstanding dependencies on entry to the
2776 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2777 /* If we hit control flow, assume that there *are* outstanding
2778 * dependencies, and force their cleanup before our instruction.
2780 if (block
->start() == scan_inst
) {
2781 for (int i
= 0; i
< write_len
; i
++) {
2783 DEP_RESOLVE_MOV(bld
.at(block
, inst
), first_write_grf
+ i
);
2788 /* We insert our reads as late as possible on the assumption that any
2789 * instruction but a MOV that might have left us an outstanding
2790 * dependency has more latency than a MOV.
2792 if (scan_inst
->dst
.file
== GRF
) {
2793 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2794 int reg
= scan_inst
->dst
.reg
+ i
;
2796 if (reg
>= first_write_grf
&&
2797 reg
< first_write_grf
+ write_len
&&
2798 needs_dep
[reg
- first_write_grf
]) {
2799 DEP_RESOLVE_MOV(bld
.at(block
, inst
), reg
);
2800 needs_dep
[reg
- first_write_grf
] = false;
2801 if (scan_inst
->exec_size
== 16)
2802 needs_dep
[reg
- first_write_grf
+ 1] = false;
2807 /* Clear the flag for registers that actually got read (as expected). */
2808 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2810 /* Continue the loop only if we haven't resolved all the dependencies */
2812 for (i
= 0; i
< write_len
; i
++) {
2822 * Implements this workaround for the original 965:
2824 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2825 * used as a destination register until after it has been sourced by an
2826 * instruction with a different destination register.
2829 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
2831 int write_len
= inst
->regs_written
;
2832 int first_write_grf
= inst
->dst
.reg
;
2833 bool needs_dep
[BRW_MAX_MRF
];
2834 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2836 memset(needs_dep
, false, sizeof(needs_dep
));
2837 memset(needs_dep
, true, write_len
);
2838 /* Walk forwards looking for writes to registers we're writing which aren't
2839 * read before being written.
2841 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2842 /* If we hit control flow, force resolve all remaining dependencies. */
2843 if (block
->end() == scan_inst
) {
2844 for (int i
= 0; i
< write_len
; i
++) {
2846 DEP_RESOLVE_MOV(bld
.at(block
, scan_inst
), first_write_grf
+ i
);
2851 /* Clear the flag for registers that actually got read (as expected). */
2852 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2854 /* We insert our reads as late as possible since they're reading the
2855 * result of a SEND, which has massive latency.
2857 if (scan_inst
->dst
.file
== GRF
&&
2858 scan_inst
->dst
.reg
>= first_write_grf
&&
2859 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
2860 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
2861 DEP_RESOLVE_MOV(bld
.at(block
, scan_inst
), scan_inst
->dst
.reg
);
2862 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
2865 /* Continue the loop only if we haven't resolved all the dependencies */
2867 for (i
= 0; i
< write_len
; i
++) {
2877 fs_visitor::insert_gen4_send_dependency_workarounds()
2879 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
2882 bool progress
= false;
2884 /* Note that we're done with register allocation, so GRF fs_regs always
2885 * have a .reg_offset of 0.
2888 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2889 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
2890 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
2891 insert_gen4_post_send_dependency_workarounds(block
, inst
);
2897 invalidate_live_intervals();
2901 * Turns the generic expression-style uniform pull constant load instruction
2902 * into a hardware-specific series of instructions for loading a pull
2905 * The expression style allows the CSE pass before this to optimize out
2906 * repeated loads from the same offset, and gives the pre-register-allocation
2907 * scheduling full flexibility, while the conversion to native instructions
2908 * allows the post-register-allocation scheduler the best information
2911 * Note that execution masking for setting up pull constant loads is special:
2912 * the channels that need to be written are unrelated to the current execution
2913 * mask, since a later instruction will use one of the result channels as a
2914 * source operand for all 8 or 16 of its channels.
2917 fs_visitor::lower_uniform_pull_constant_loads()
2919 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2920 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
2923 if (devinfo
->gen
>= 7) {
2924 /* The offset arg before was a vec4-aligned byte offset. We need to
2925 * turn it into a dword offset.
2927 fs_reg const_offset_reg
= inst
->src
[1];
2928 assert(const_offset_reg
.file
== IMM
&&
2929 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
2930 const_offset_reg
.fixed_hw_reg
.dw1
.ud
/= 4;
2931 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1));
2933 /* We have to use a message header on Skylake to get SIMD4x2 mode.
2934 * Reserve space for the register.
2936 if (devinfo
->gen
>= 9) {
2937 payload
.reg_offset
++;
2938 alloc
.sizes
[payload
.reg
] = 2;
2941 /* This is actually going to be a MOV, but since only the first dword
2942 * is accessed, we have a special opcode to do just that one. Note
2943 * that this needs to be an operation that will be considered a def
2944 * by live variable analysis, or register allocation will explode.
2946 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
2947 8, payload
, const_offset_reg
);
2948 setup
->force_writemask_all
= true;
2950 setup
->ir
= inst
->ir
;
2951 setup
->annotation
= inst
->annotation
;
2952 inst
->insert_before(block
, setup
);
2954 /* Similarly, this will only populate the first 4 channels of the
2955 * result register (since we only use smear values from 0-3), but we
2956 * don't tell the optimizer.
2958 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
2959 inst
->src
[1] = payload
;
2961 invalidate_live_intervals();
2963 /* Before register allocation, we didn't tell the scheduler about the
2964 * MRF we use. We know it's safe to use this MRF because nothing
2965 * else does except for register spill/unspill, which generates and
2966 * uses its MRF within a single IR instruction.
2968 inst
->base_mrf
= 14;
2975 fs_visitor::lower_load_payload()
2977 bool progress
= false;
2979 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2980 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2983 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== GRF
);
2984 assert(inst
->saturate
== false);
2986 const fs_builder ibld
= bld
.group(inst
->exec_size
, inst
->force_sechalf
)
2987 .exec_all(inst
->force_writemask_all
)
2989 fs_reg dst
= inst
->dst
;
2991 /* Get rid of COMPR4. We'll add it back in if we need it */
2992 if (dst
.file
== MRF
)
2993 dst
.reg
= dst
.reg
& ~BRW_MRF_COMPR4
;
2996 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
2997 if (inst
->src
[i
].file
!= BAD_FILE
) {
2998 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
2999 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3001 ibld
.exec_all().MOV(mov_dst
, mov_src
);
3003 dst
= offset(dst
, 1);
3006 dst
.width
= inst
->exec_size
;
3007 if (inst
->dst
.file
== MRF
&& (inst
->dst
.reg
& BRW_MRF_COMPR4
) &&
3008 inst
->exec_size
> 8) {
3009 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3010 * a straightforward copy. Instead, the result of the
3011 * LOAD_PAYLOAD is treated as interleaved and the first four
3012 * non-header sources are unpacked as:
3023 * This is used for gen <= 5 fb writes.
3025 assert(inst
->exec_size
== 16);
3026 assert(inst
->header_size
+ 4 <= inst
->sources
);
3027 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3028 if (inst
->src
[i
].file
!= BAD_FILE
) {
3029 if (devinfo
->has_compr4
) {
3030 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3031 compr4_dst
.reg
|= BRW_MRF_COMPR4
;
3032 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3034 /* Platform doesn't have COMPR4. We have to fake it */
3035 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3037 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3038 ibld
.half(1).MOV(offset(mov_dst
, 4), half(inst
->src
[i
], 1));
3045 /* The loop above only ever incremented us through the first set
3046 * of 4 registers. However, thanks to the magic of COMPR4, we
3047 * actually wrote to the first 8 registers, so we need to take
3048 * that into account now.
3052 /* The COMPR4 code took care of the first 4 sources. We'll let
3053 * the regular path handle any remaining sources. Yes, we are
3054 * modifying the instruction but we're about to delete it so
3055 * this really doesn't hurt anything.
3057 inst
->header_size
+= 4;
3060 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3061 if (inst
->src
[i
].file
!= BAD_FILE
)
3062 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3063 dst
= offset(dst
, 1);
3066 inst
->remove(block
);
3071 invalidate_live_intervals();
3077 fs_visitor::lower_integer_multiplication()
3079 bool progress
= false;
3081 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit operation
3082 * directly, but Cherryview cannot.
3084 if (devinfo
->gen
>= 8 && !devinfo
->is_cherryview
)
3087 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3088 if (inst
->opcode
!= BRW_OPCODE_MUL
||
3089 inst
->dst
.is_accumulator() ||
3090 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3091 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3094 const fs_builder ibld
= bld
.at(block
, inst
);
3096 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3097 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3100 * If multiplying by an immediate value that fits in 16-bits, do a
3101 * single MUL instruction with that value in the proper location.
3103 if (inst
->src
[1].file
== IMM
&&
3104 inst
->src
[1].fixed_hw_reg
.dw1
.ud
< (1 << 16)) {
3105 if (devinfo
->gen
< 7) {
3106 fs_reg
imm(GRF
, alloc
.allocate(dispatch_width
/ 8),
3107 inst
->dst
.type
, dispatch_width
);
3108 ibld
.MOV(imm
, inst
->src
[1]);
3109 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3111 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3114 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3115 * do 32-bit integer multiplication in one instruction, but instead
3116 * must do a sequence (which actually calculates a 64-bit result):
3118 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3119 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3120 * mov(8) g2<1>D acc0<8,8,1>D
3122 * But on Gen > 6, the ability to use second accumulator register
3123 * (acc1) for non-float data types was removed, preventing a simple
3124 * implementation in SIMD16. A 16-channel result can be calculated by
3125 * executing the three instructions twice in SIMD8, once with quarter
3126 * control of 1Q for the first eight channels and again with 2Q for
3127 * the second eight channels.
3129 * Which accumulator register is implicitly accessed (by AccWrEnable
3130 * for instance) is determined by the quarter control. Unfortunately
3131 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3132 * implicit accumulator access by an instruction with 2Q will access
3133 * acc1 regardless of whether the data type is usable in acc1.
3135 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3136 * integer data types.
3138 * Since we only want the low 32-bits of the result, we can do two
3139 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3140 * adjust the high result and add them (like the mach is doing):
3142 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3143 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3144 * shl(8) g9<1>D g8<8,8,1>D 16D
3145 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3147 * We avoid the shl instruction by realizing that we only want to add
3148 * the low 16-bits of the "high" result to the high 16-bits of the
3149 * "low" result and using proper regioning on the add:
3151 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3152 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3153 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3155 * Since it does not use the (single) accumulator register, we can
3156 * schedule multi-component multiplications much better.
3159 if (inst
->conditional_mod
&& inst
->dst
.is_null()) {
3160 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
3161 inst
->dst
.type
, dispatch_width
);
3163 fs_reg low
= inst
->dst
;
3164 fs_reg
high(GRF
, alloc
.allocate(dispatch_width
/ 8),
3165 inst
->dst
.type
, dispatch_width
);
3167 if (devinfo
->gen
>= 7) {
3168 fs_reg src1_0_w
= inst
->src
[1];
3169 fs_reg src1_1_w
= inst
->src
[1];
3171 if (inst
->src
[1].file
== IMM
) {
3172 src1_0_w
.fixed_hw_reg
.dw1
.ud
&= 0xffff;
3173 src1_1_w
.fixed_hw_reg
.dw1
.ud
>>= 16;
3175 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3176 if (src1_0_w
.stride
!= 0) {
3177 assert(src1_0_w
.stride
== 1);
3178 src1_0_w
.stride
= 2;
3181 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3182 if (src1_1_w
.stride
!= 0) {
3183 assert(src1_1_w
.stride
== 1);
3184 src1_1_w
.stride
= 2;
3186 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3188 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3189 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3191 fs_reg src0_0_w
= inst
->src
[0];
3192 fs_reg src0_1_w
= inst
->src
[0];
3194 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3195 if (src0_0_w
.stride
!= 0) {
3196 assert(src0_0_w
.stride
== 1);
3197 src0_0_w
.stride
= 2;
3200 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3201 if (src0_1_w
.stride
!= 0) {
3202 assert(src0_1_w
.stride
== 1);
3203 src0_1_w
.stride
= 2;
3205 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3207 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3208 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3211 fs_reg dst
= inst
->dst
;
3212 dst
.type
= BRW_REGISTER_TYPE_UW
;
3213 dst
.subreg_offset
= 2;
3216 high
.type
= BRW_REGISTER_TYPE_UW
;
3219 low
.type
= BRW_REGISTER_TYPE_UW
;
3220 low
.subreg_offset
= 2;
3223 ibld
.ADD(dst
, low
, high
);
3225 if (inst
->conditional_mod
) {
3226 fs_reg
null(retype(ibld
.null_reg_f(), inst
->dst
.type
));
3227 set_condmod(inst
->conditional_mod
,
3228 ibld
.MOV(null
, inst
->dst
));
3232 inst
->remove(block
);
3237 invalidate_live_intervals();
3243 fs_visitor::dump_instructions()
3245 dump_instructions(NULL
);
3249 fs_visitor::dump_instructions(const char *name
)
3251 FILE *file
= stderr
;
3252 if (name
&& geteuid() != 0) {
3253 file
= fopen(name
, "w");
3259 calculate_register_pressure();
3260 int ip
= 0, max_pressure
= 0;
3261 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
3262 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
3263 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
3264 dump_instruction(inst
, file
);
3267 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
3270 foreach_in_list(backend_instruction
, inst
, &instructions
) {
3271 fprintf(file
, "%4d: ", ip
++);
3272 dump_instruction(inst
, file
);
3276 if (file
!= stderr
) {
3282 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
3284 dump_instruction(be_inst
, stderr
);
3288 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
3290 fs_inst
*inst
= (fs_inst
*)be_inst
;
3292 if (inst
->predicate
) {
3293 fprintf(file
, "(%cf0.%d) ",
3294 inst
->predicate_inverse
? '-' : '+',
3298 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
3300 fprintf(file
, ".sat");
3301 if (inst
->conditional_mod
) {
3302 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
3303 if (!inst
->predicate
&&
3304 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
3305 inst
->opcode
!= BRW_OPCODE_IF
&&
3306 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
3307 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
3310 fprintf(file
, "(%d) ", inst
->exec_size
);
3313 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
3316 switch (inst
->dst
.file
) {
3318 fprintf(file
, "vgrf%d", inst
->dst
.reg
);
3319 if (inst
->dst
.width
!= dispatch_width
)
3320 fprintf(file
, "@%d", inst
->dst
.width
);
3321 if (alloc
.sizes
[inst
->dst
.reg
] != inst
->dst
.width
/ 8 ||
3322 inst
->dst
.subreg_offset
)
3323 fprintf(file
, "+%d.%d",
3324 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
3327 fprintf(file
, "m%d", inst
->dst
.reg
);
3330 fprintf(file
, "(null)");
3333 fprintf(file
, "***u%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
3336 fprintf(file
, "***attr%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
3339 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
3340 switch (inst
->dst
.fixed_hw_reg
.nr
) {
3342 fprintf(file
, "null");
3344 case BRW_ARF_ADDRESS
:
3345 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
3347 case BRW_ARF_ACCUMULATOR
:
3348 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
3351 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
3352 inst
->dst
.fixed_hw_reg
.subnr
);
3355 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
3356 inst
->dst
.fixed_hw_reg
.subnr
);
3360 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
3362 if (inst
->dst
.fixed_hw_reg
.subnr
)
3363 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
3366 fprintf(file
, "???");
3369 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
3371 for (int i
= 0; i
< inst
->sources
; i
++) {
3372 if (inst
->src
[i
].negate
)
3374 if (inst
->src
[i
].abs
)
3376 switch (inst
->src
[i
].file
) {
3378 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
3379 if (inst
->src
[i
].width
!= dispatch_width
)
3380 fprintf(file
, "@%d", inst
->src
[i
].width
);
3381 if (alloc
.sizes
[inst
->src
[i
].reg
] != inst
->src
[i
].width
/ 8 ||
3382 inst
->src
[i
].subreg_offset
)
3383 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
3384 inst
->src
[i
].subreg_offset
);
3387 fprintf(file
, "***m%d***", inst
->src
[i
].reg
);
3390 fprintf(file
, "attr%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
3393 fprintf(file
, "u%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
3394 if (inst
->src
[i
].reladdr
) {
3395 fprintf(file
, "+reladdr");
3396 } else if (inst
->src
[i
].subreg_offset
) {
3397 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
3398 inst
->src
[i
].subreg_offset
);
3402 fprintf(file
, "(null)");
3405 switch (inst
->src
[i
].type
) {
3406 case BRW_REGISTER_TYPE_F
:
3407 fprintf(file
, "%ff", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
3409 case BRW_REGISTER_TYPE_W
:
3410 case BRW_REGISTER_TYPE_D
:
3411 fprintf(file
, "%dd", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
3413 case BRW_REGISTER_TYPE_UW
:
3414 case BRW_REGISTER_TYPE_UD
:
3415 fprintf(file
, "%uu", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
3417 case BRW_REGISTER_TYPE_VF
:
3418 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
3419 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
3420 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
3421 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
3422 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
3425 fprintf(file
, "???");
3430 if (inst
->src
[i
].fixed_hw_reg
.negate
)
3432 if (inst
->src
[i
].fixed_hw_reg
.abs
)
3434 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
3435 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
3437 fprintf(file
, "null");
3439 case BRW_ARF_ADDRESS
:
3440 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3442 case BRW_ARF_ACCUMULATOR
:
3443 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3446 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
3447 inst
->src
[i
].fixed_hw_reg
.subnr
);
3450 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
3451 inst
->src
[i
].fixed_hw_reg
.subnr
);
3455 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
3457 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
3458 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3459 if (inst
->src
[i
].fixed_hw_reg
.abs
)
3463 fprintf(file
, "???");
3466 if (inst
->src
[i
].abs
)
3469 if (inst
->src
[i
].file
!= IMM
) {
3470 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
3473 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
3474 fprintf(file
, ", ");
3479 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
3480 if (inst
->force_sechalf
)
3481 fprintf(file
, "2ndhalf ");
3483 fprintf(file
, "1sthalf ");
3486 fprintf(file
, "\n");
3490 * Possibly returns an instruction that set up @param reg.
3492 * Sometimes we want to take the result of some expression/variable
3493 * dereference tree and rewrite the instruction generating the result
3494 * of the tree. When processing the tree, we know that the
3495 * instructions generated are all writing temporaries that are dead
3496 * outside of this tree. So, if we have some instructions that write
3497 * a temporary, we're free to point that temp write somewhere else.
3499 * Note that this doesn't guarantee that the instruction generated
3500 * only reg -- it might be the size=4 destination of a texture instruction.
3503 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
3508 end
->is_partial_write() ||
3510 !reg
.equals(end
->dst
)) {
3518 fs_visitor::setup_payload_gen6()
3521 (prog
->InputsRead
& (1 << VARYING_SLOT_POS
)) != 0;
3522 unsigned barycentric_interp_modes
=
3523 (stage
== MESA_SHADER_FRAGMENT
) ?
3524 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
3526 assert(devinfo
->gen
>= 6);
3528 /* R0-1: masks, pixel X/Y coordinates. */
3529 payload
.num_regs
= 2;
3530 /* R2: only for 32-pixel dispatch.*/
3532 /* R3-26: barycentric interpolation coordinates. These appear in the
3533 * same order that they appear in the brw_wm_barycentric_interp_mode
3534 * enum. Each set of coordinates occupies 2 registers if dispatch width
3535 * == 8 and 4 registers if dispatch width == 16. Coordinates only
3536 * appear if they were enabled using the "Barycentric Interpolation
3537 * Mode" bits in WM_STATE.
3539 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
3540 if (barycentric_interp_modes
& (1 << i
)) {
3541 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
3542 payload
.num_regs
+= 2;
3543 if (dispatch_width
== 16) {
3544 payload
.num_regs
+= 2;
3549 /* R27: interpolated depth if uses source depth */
3551 payload
.source_depth_reg
= payload
.num_regs
;
3553 if (dispatch_width
== 16) {
3554 /* R28: interpolated depth if not SIMD8. */
3558 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
3560 payload
.source_w_reg
= payload
.num_regs
;
3562 if (dispatch_width
== 16) {
3563 /* R30: interpolated W if not SIMD8. */
3568 if (stage
== MESA_SHADER_FRAGMENT
) {
3569 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3570 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3571 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
3572 /* R31: MSAA position offsets. */
3573 if (prog_data
->uses_pos_offset
) {
3574 payload
.sample_pos_reg
= payload
.num_regs
;
3579 /* R32: MSAA input coverage mask */
3580 if (prog
->SystemValuesRead
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
3581 assert(devinfo
->gen
>= 7);
3582 payload
.sample_mask_in_reg
= payload
.num_regs
;
3584 if (dispatch_width
== 16) {
3585 /* R33: input coverage mask if not SIMD8. */
3590 /* R34-: bary for 32-pixel. */
3591 /* R58-59: interp W for 32-pixel. */
3593 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
3594 source_depth_to_render_target
= true;
3599 fs_visitor::setup_vs_payload()
3601 /* R0: thread header, R1: urb handles */
3602 payload
.num_regs
= 2;
3606 fs_visitor::setup_cs_payload()
3608 assert(devinfo
->gen
>= 7);
3610 payload
.num_regs
= 1;
3614 fs_visitor::assign_binding_table_offsets()
3616 assert(stage
== MESA_SHADER_FRAGMENT
);
3617 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3618 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3619 uint32_t next_binding_table_offset
= 0;
3621 /* If there are no color regions, we still perform an FB write to a null
3622 * renderbuffer, which we place at surface index 0.
3624 prog_data
->binding_table
.render_target_start
= next_binding_table_offset
;
3625 next_binding_table_offset
+= MAX2(key
->nr_color_regions
, 1);
3627 assign_common_binding_table_offsets(next_binding_table_offset
);
3631 fs_visitor::calculate_register_pressure()
3633 invalidate_live_intervals();
3634 calculate_live_intervals();
3636 unsigned num_instructions
= 0;
3637 foreach_block(block
, cfg
)
3638 num_instructions
+= block
->instructions
.length();
3640 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
3642 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
3643 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
3644 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
3649 fs_visitor::optimize()
3651 /* bld is the common builder object pointing at the end of the program we
3652 * used to translate it into i965 IR. For the optimization and lowering
3653 * passes coming next, any code added after the end of the program without
3654 * having explicitly called fs_builder::at() clearly points at a mistake.
3655 * Ideally optimization passes wouldn't be part of the visitor so they
3656 * wouldn't have access to bld at all, but they do, so just in case some
3657 * pass forgets to ask for a location explicitly set it to NULL here to
3660 bld
= bld
.at(NULL
, NULL
);
3662 split_virtual_grfs();
3664 move_uniform_array_access_to_pull_constants();
3665 assign_constant_locations();
3666 demote_pull_constants();
3668 #define OPT(pass, args...) ({ \
3670 bool this_progress = pass(args); \
3672 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
3673 char filename[64]; \
3674 snprintf(filename, 64, "%s%d-%04d-%02d-%02d-" #pass, \
3675 stage_abbrev, dispatch_width, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
3677 backend_shader::dump_instructions(filename); \
3680 progress = progress || this_progress; \
3684 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
3686 snprintf(filename
, 64, "%s%d-%04d-00-start",
3687 stage_abbrev
, dispatch_width
,
3688 shader_prog
? shader_prog
->Name
: 0);
3690 backend_shader::dump_instructions(filename
);
3701 OPT(remove_duplicate_mrf_writes
);
3705 OPT(opt_copy_propagate
);
3706 OPT(opt_peephole_predicated_break
);
3707 OPT(opt_cmod_propagation
);
3708 OPT(dead_code_eliminate
);
3709 OPT(opt_peephole_sel
);
3710 OPT(dead_control_flow_eliminate
, this);
3711 OPT(opt_register_renaming
);
3712 OPT(opt_redundant_discard_jumps
);
3713 OPT(opt_saturate_propagation
);
3714 OPT(opt_zero_samples
);
3715 OPT(register_coalesce
);
3716 OPT(compute_to_mrf
);
3717 OPT(eliminate_find_live_channel
);
3719 OPT(compact_virtual_grfs
);
3724 OPT(opt_sampler_eot
);
3726 if (OPT(lower_load_payload
)) {
3727 split_virtual_grfs();
3728 OPT(register_coalesce
);
3729 OPT(compute_to_mrf
);
3730 OPT(dead_code_eliminate
);
3733 OPT(opt_combine_constants
);
3734 OPT(lower_integer_multiplication
);
3736 lower_uniform_pull_constant_loads();
3740 * Three source instruction must have a GRF/MRF destination register.
3741 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
3744 fs_visitor::fixup_3src_null_dest()
3746 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3747 if (inst
->is_3src() && inst
->dst
.is_null()) {
3748 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
3755 fs_visitor::allocate_registers()
3757 bool allocated_without_spills
;
3759 static const enum instruction_scheduler_mode pre_modes
[] = {
3761 SCHEDULE_PRE_NON_LIFO
,
3765 /* Try each scheduling heuristic to see if it can successfully register
3766 * allocate without spilling. They should be ordered by decreasing
3767 * performance but increasing likelihood of allocating.
3769 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
3770 schedule_instructions(pre_modes
[i
]);
3773 assign_regs_trivial();
3774 allocated_without_spills
= true;
3776 allocated_without_spills
= assign_regs(false);
3778 if (allocated_without_spills
)
3782 if (!allocated_without_spills
) {
3783 /* We assume that any spilling is worse than just dropping back to
3784 * SIMD8. There's probably actually some intermediate point where
3785 * SIMD16 with a couple of spills is still better.
3787 if (dispatch_width
== 16) {
3788 fail("Failure to register allocate. Reduce number of "
3789 "live scalar values to avoid this.");
3791 compiler
->shader_perf_log(log_data
,
3792 "%s shader triggered register spilling. "
3793 "Try reducing the number of live scalar "
3794 "values to improve performance.\n",
3798 /* Since we're out of heuristics, just go spill registers until we
3799 * get an allocation.
3801 while (!assign_regs(true)) {
3807 /* This must come after all optimization and register allocation, since
3808 * it inserts dead code that happens to have side effects, and it does
3809 * so based on the actual physical registers in use.
3811 insert_gen4_send_dependency_workarounds();
3816 if (!allocated_without_spills
)
3817 schedule_instructions(SCHEDULE_POST
);
3819 if (last_scratch
> 0)
3820 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
3824 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
3826 assert(stage
== MESA_SHADER_VERTEX
);
3828 if (prog_data
->map_entries
== NULL
)
3829 assign_common_binding_table_offsets(0);
3832 if (shader_time_index
>= 0)
3833 emit_shader_time_begin();
3840 emit_urb_writes(clip_planes
);
3842 if (shader_time_index
>= 0)
3843 emit_shader_time_end();
3849 assign_curb_setup();
3850 assign_vs_urb_setup();
3852 fixup_3src_null_dest();
3853 allocate_registers();
3859 fs_visitor::run_fs(bool do_rep_send
)
3861 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3862 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
3864 assert(stage
== MESA_SHADER_FRAGMENT
);
3866 if (prog_data
->map_entries
== NULL
)
3867 assign_binding_table_offsets();
3869 if (devinfo
->gen
>= 6)
3870 setup_payload_gen6();
3872 setup_payload_gen4();
3876 } else if (do_rep_send
) {
3877 assert(dispatch_width
== 16);
3878 emit_repclear_shader();
3880 if (shader_time_index
>= 0)
3881 emit_shader_time_begin();
3883 calculate_urb_setup();
3884 if (prog
->InputsRead
> 0) {
3885 if (devinfo
->gen
< 6)
3886 emit_interpolation_setup_gen4();
3888 emit_interpolation_setup_gen6();
3891 /* We handle discards by keeping track of the still-live pixels in f0.1.
3892 * Initialize it with the dispatched pixels.
3894 if (wm_prog_data
->uses_kill
) {
3895 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
3896 discard_init
->flag_subreg
= 1;
3899 /* Generate FS IR for main(). (the visitor only descends into
3900 * functions called "main").
3907 if (wm_prog_data
->uses_kill
)
3908 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
3910 if (wm_key
->alpha_test_func
)
3915 if (shader_time_index
>= 0)
3916 emit_shader_time_end();
3922 assign_curb_setup();
3925 fixup_3src_null_dest();
3926 allocate_registers();
3932 if (dispatch_width
== 8)
3933 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
3935 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
3941 fs_visitor::run_cs()
3943 assert(stage
== MESA_SHADER_COMPUTE
);
3946 sanity_param_count
= prog
->Parameters
->NumParameters
;
3948 assign_common_binding_table_offsets(0);
3952 if (shader_time_index
>= 0)
3953 emit_shader_time_begin();
3960 emit_cs_terminate();
3962 if (shader_time_index
>= 0)
3963 emit_shader_time_end();
3969 assign_curb_setup();
3971 fixup_3src_null_dest();
3972 allocate_registers();
3977 /* If any state parameters were appended, then ParameterValues could have
3978 * been realloced, in which case the driver uniform storage set up by
3979 * _mesa_associate_uniform_storage() would point to freed memory. Make
3980 * sure that didn't happen.
3982 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
3988 brw_wm_fs_emit(struct brw_context
*brw
,
3990 const struct brw_wm_prog_key
*key
,
3991 struct brw_wm_prog_data
*prog_data
,
3992 struct gl_fragment_program
*fp
,
3993 struct gl_shader_program
*prog
,
3994 unsigned *final_assembly_size
)
3996 bool start_busy
= false;
3997 double start_time
= 0;
3999 if (unlikely(brw
->perf_debug
)) {
4000 start_busy
= (brw
->batch
.last_bo
&&
4001 drm_intel_bo_busy(brw
->batch
.last_bo
));
4002 start_time
= get_time();
4005 struct brw_shader
*shader
= NULL
;
4007 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
4009 if (unlikely(INTEL_DEBUG
& DEBUG_WM
) && shader
->base
.ir
)
4010 brw_dump_ir("fragment", prog
, &shader
->base
, &fp
->Base
);
4012 int st_index8
= -1, st_index16
= -1;
4013 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
4014 st_index8
= brw_get_shader_time_index(brw
, prog
, &fp
->Base
, ST_FS8
);
4015 st_index16
= brw_get_shader_time_index(brw
, prog
, &fp
->Base
, ST_FS16
);
4018 /* Now the main event: Visit the shader IR and generate our FS IR for it.
4020 fs_visitor
v(brw
->intelScreen
->compiler
, brw
,
4021 mem_ctx
, MESA_SHADER_FRAGMENT
, key
, &prog_data
->base
,
4022 prog
, &fp
->Base
, 8, st_index8
);
4023 if (!v
.run_fs(false /* do_rep_send */)) {
4025 prog
->LinkStatus
= false;
4026 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
4029 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
4035 cfg_t
*simd16_cfg
= NULL
;
4036 fs_visitor
v2(brw
->intelScreen
->compiler
, brw
,
4037 mem_ctx
, MESA_SHADER_FRAGMENT
, key
, &prog_data
->base
,
4038 prog
, &fp
->Base
, 16, st_index16
);
4039 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || brw
->use_rep_send
)) {
4040 if (!v
.simd16_unsupported
) {
4041 /* Try a SIMD16 compile */
4042 v2
.import_uniforms(&v
);
4043 if (!v2
.run_fs(brw
->use_rep_send
)) {
4044 perf_debug("SIMD16 shader failed to compile: %s", v2
.fail_msg
);
4046 simd16_cfg
= v2
.cfg
;
4052 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || brw
->no_simd8
;
4053 if ((no_simd8
|| brw
->gen
< 5) && simd16_cfg
) {
4055 prog_data
->no_8
= true;
4058 prog_data
->no_8
= false;
4061 fs_generator
g(brw
->intelScreen
->compiler
, brw
,
4062 mem_ctx
, (void *) key
, &prog_data
->base
,
4063 &fp
->Base
, v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
4065 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
4068 name
= ralloc_asprintf(mem_ctx
, "%s fragment shader %d",
4069 prog
->Label
? prog
->Label
: "unnamed",
4072 name
= ralloc_asprintf(mem_ctx
, "fragment program %d", fp
->Base
.Id
);
4074 g
.enable_debug(name
);
4078 g
.generate_code(simd8_cfg
, 8);
4080 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
4082 if (unlikely(brw
->perf_debug
) && shader
) {
4083 if (shader
->compiled_once
)
4084 brw_wm_debug_recompile(brw
, prog
, key
);
4085 shader
->compiled_once
= true;
4087 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
4088 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
4089 (get_time() - start_time
) * 1000);
4093 return g
.get_assembly(final_assembly_size
);
4097 brw_fs_precompile(struct gl_context
*ctx
,
4098 struct gl_shader_program
*shader_prog
,
4099 struct gl_program
*prog
)
4101 struct brw_context
*brw
= brw_context(ctx
);
4102 struct brw_wm_prog_key key
;
4104 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*) prog
;
4105 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
4106 bool program_uses_dfdy
= fp
->UsesDFdy
;
4108 memset(&key
, 0, sizeof(key
));
4112 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
4114 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
4115 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
4117 /* Just assume depth testing. */
4118 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
4119 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
4122 if (brw
->gen
< 6 || _mesa_bitcount_64(fp
->Base
.InputsRead
&
4123 BRW_FS_VARYING_INPUT_MASK
) > 16)
4124 key
.input_slots_valid
= fp
->Base
.InputsRead
| VARYING_BIT_POS
;
4126 brw_setup_tex_for_precompile(brw
, &key
.tex
, &fp
->Base
);
4128 if (fp
->Base
.InputsRead
& VARYING_BIT_POS
) {
4129 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
4132 key
.nr_color_regions
= _mesa_bitcount_64(fp
->Base
.OutputsWritten
&
4133 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
4134 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
)));
4136 if ((fp
->Base
.InputsRead
& VARYING_BIT_POS
) || program_uses_dfdy
) {
4137 key
.render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
) ||
4138 key
.nr_color_regions
> 1;
4141 key
.program_string_id
= bfp
->id
;
4143 uint32_t old_prog_offset
= brw
->wm
.base
.prog_offset
;
4144 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
4146 bool success
= brw_codegen_wm_prog(brw
, shader_prog
, bfp
, &key
);
4148 brw
->wm
.base
.prog_offset
= old_prog_offset
;
4149 brw
->wm
.prog_data
= old_prog_data
;
4155 brw_setup_tex_for_precompile(struct brw_context
*brw
,
4156 struct brw_sampler_prog_key_data
*tex
,
4157 struct gl_program
*prog
)
4159 const bool has_shader_channel_select
= brw
->is_haswell
|| brw
->gen
>= 8;
4160 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
4161 for (unsigned i
= 0; i
< sampler_count
; i
++) {
4162 if (!has_shader_channel_select
&& (prog
->ShadowSamplers
& (1 << i
))) {
4163 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
4165 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
4167 /* Color sampler: assume no swizzling. */
4168 tex
->swizzles
[i
] = SWIZZLE_XYZW
;