2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "program/prog_parameter.h"
35 #include "program/prog_print.h"
36 #include "program/prog_optimize.h"
37 #include "program/hash_table.h"
38 #include "brw_context.h"
43 #include "../glsl/glsl_types.h"
44 #include "../glsl/ir_optimization.h"
45 #include "../glsl/ir_print_visitor.h"
48 ARF
= BRW_ARCHITECTURE_REGISTER_FILE
,
49 GRF
= BRW_GENERAL_REGISTER_FILE
,
50 MRF
= BRW_MESSAGE_REGISTER_FILE
,
51 IMM
= BRW_IMMEDIATE_VALUE
,
52 FIXED_HW_REG
, /* a struct brw_reg */
53 UNIFORM
, /* prog_data->params[hw_reg] */
58 FS_OPCODE_FB_WRITE
= 256,
73 static int using_new_fs
= -1;
76 brw_new_shader(GLcontext
*ctx
, GLuint name
, GLuint type
)
78 struct brw_shader
*shader
;
80 shader
= talloc_zero(NULL
, struct brw_shader
);
82 shader
->base
.Type
= type
;
83 shader
->base
.Name
= name
;
84 _mesa_init_shader(ctx
, &shader
->base
);
90 struct gl_shader_program
*
91 brw_new_shader_program(GLcontext
*ctx
, GLuint name
)
93 struct brw_shader_program
*prog
;
94 prog
= talloc_zero(NULL
, struct brw_shader_program
);
96 prog
->base
.Name
= name
;
97 _mesa_init_shader_program(ctx
, &prog
->base
);
103 brw_compile_shader(GLcontext
*ctx
, struct gl_shader
*shader
)
105 if (!_mesa_ir_compile_shader(ctx
, shader
))
112 brw_link_shader(GLcontext
*ctx
, struct gl_shader_program
*prog
)
114 if (using_new_fs
== -1)
115 using_new_fs
= getenv("INTEL_NEW_FS") != NULL
;
117 for (unsigned i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
118 struct brw_shader
*shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
120 if (using_new_fs
&& shader
->base
.Type
== GL_FRAGMENT_SHADER
) {
121 void *mem_ctx
= talloc_new(NULL
);
125 talloc_free(shader
->ir
);
126 shader
->ir
= new(shader
) exec_list
;
127 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
129 do_mat_op_to_vec(shader
->ir
);
130 do_mod_to_fract(shader
->ir
);
131 do_div_to_mul_rcp(shader
->ir
);
132 do_sub_to_add_neg(shader
->ir
);
133 do_explog_to_explog2(shader
->ir
);
135 brw_do_channel_expressions(shader
->ir
);
136 brw_do_vector_splitting(shader
->ir
);
141 progress
= do_common_optimization(shader
->ir
, true) || progress
;
144 validate_ir_tree(shader
->ir
);
146 reparent_ir(shader
->ir
, shader
->ir
);
147 talloc_free(mem_ctx
);
151 if (!_mesa_ir_link_shader(ctx
, prog
))
158 type_size(const struct glsl_type
*type
)
160 unsigned int size
, i
;
162 switch (type
->base_type
) {
165 case GLSL_TYPE_FLOAT
:
167 return type
->components();
168 case GLSL_TYPE_ARRAY
:
169 /* FINISHME: uniform/varying arrays. */
170 return type_size(type
->fields
.array
) * type
->length
;
171 case GLSL_TYPE_STRUCT
:
173 for (i
= 0; i
< type
->length
; i
++) {
174 size
+= type_size(type
->fields
.structure
[i
].type
);
177 case GLSL_TYPE_SAMPLER
:
178 /* Samplers take up no register space, since they're baked in at
183 assert(!"not reached");
190 /* Callers of this talloc-based new need not call delete. It's
191 * easier to just talloc_free 'ctx' (or any of its ancestors). */
192 static void* operator new(size_t size
, void *ctx
)
196 node
= talloc_size(ctx
, size
);
197 assert(node
!= NULL
);
202 /** Generic unset register constructor. */
205 this->file
= BAD_FILE
;
207 this->reg_offset
= 0;
213 /** Immediate value constructor. */
219 this->type
= BRW_REGISTER_TYPE_F
;
225 /** Immediate value constructor. */
231 this->type
= BRW_REGISTER_TYPE_D
;
237 /** Immediate value constructor. */
243 this->type
= BRW_REGISTER_TYPE_UD
;
249 /** Fixed brw_reg Immediate value constructor. */
250 fs_reg(struct brw_reg fixed_hw_reg
)
252 this->file
= FIXED_HW_REG
;
253 this->fixed_hw_reg
= fixed_hw_reg
;
256 this->type
= fixed_hw_reg
.type
;
261 fs_reg(enum register_file file
, int hw_reg
);
262 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
264 /** Register file: ARF, GRF, MRF, IMM. */
265 enum register_file file
;
266 /** Abstract register number. 0 = fixed hw reg */
268 /** Offset within the abstract register. */
270 /** HW register number. Generally unset until register allocation. */
272 /** Register type. BRW_REGISTER_TYPE_* */
276 struct brw_reg fixed_hw_reg
;
278 /** Value for file == BRW_IMMMEDIATE_FILE */
286 static const fs_reg reg_undef
;
287 static const fs_reg
reg_null(ARF
, BRW_ARF_NULL
);
289 class fs_inst
: public exec_node
{
291 /* Callers of this talloc-based new need not call delete. It's
292 * easier to just talloc_free 'ctx' (or any of its ancestors). */
293 static void* operator new(size_t size
, void *ctx
)
297 node
= talloc_zero_size(ctx
, size
);
298 assert(node
!= NULL
);
305 this->opcode
= BRW_OPCODE_NOP
;
306 this->saturate
= false;
307 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
308 this->predicated
= false;
310 this->shadow_compare
= false;
321 this->opcode
= opcode
;
324 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
)
327 this->opcode
= opcode
;
332 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
335 this->opcode
= opcode
;
341 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg src2
)
344 this->opcode
= opcode
;
351 int opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
356 int conditional_mod
; /**< BRW_CONDITIONAL_* */
358 int mlen
; /** SEND message length */
363 * Annotation for the generated IR. One of the two can be set.
366 const char *annotation
;
370 class fs_visitor
: public ir_visitor
374 fs_visitor(struct brw_wm_compile
*c
, struct brw_shader
*shader
)
379 this->intel
= &brw
->intel
;
380 this->ctx
= &intel
->ctx
;
381 this->mem_ctx
= talloc_new(NULL
);
382 this->shader
= shader
;
384 this->next_abstract_grf
= 1;
385 this->variable_ht
= hash_table_ctor(0,
386 hash_table_pointer_hash
,
387 hash_table_pointer_compare
);
389 this->frag_color
= NULL
;
390 this->frag_data
= NULL
;
391 this->frag_depth
= NULL
;
392 this->first_non_payload_grf
= 0;
394 this->current_annotation
= NULL
;
395 this->annotation_string
= NULL
;
396 this->annotation_ir
= NULL
;
400 talloc_free(this->mem_ctx
);
401 hash_table_dtor(this->variable_ht
);
404 fs_reg
*variable_storage(ir_variable
*var
);
406 void visit(ir_variable
*ir
);
407 void visit(ir_assignment
*ir
);
408 void visit(ir_dereference_variable
*ir
);
409 void visit(ir_dereference_record
*ir
);
410 void visit(ir_dereference_array
*ir
);
411 void visit(ir_expression
*ir
);
412 void visit(ir_texture
*ir
);
413 void visit(ir_if
*ir
);
414 void visit(ir_constant
*ir
);
415 void visit(ir_swizzle
*ir
);
416 void visit(ir_return
*ir
);
417 void visit(ir_loop
*ir
);
418 void visit(ir_loop_jump
*ir
);
419 void visit(ir_discard
*ir
);
420 void visit(ir_call
*ir
);
421 void visit(ir_function
*ir
);
422 void visit(ir_function_signature
*ir
);
424 fs_inst
*emit(fs_inst inst
);
425 void assign_curb_setup();
426 void assign_urb_setup();
428 void generate_code();
429 void generate_fb_write(fs_inst
*inst
);
430 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
431 struct brw_reg
*src
);
432 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
433 void generate_math(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg
*src
);
435 void emit_dummy_fs();
436 void emit_interpolation();
437 void emit_pinterp(int location
);
438 void emit_fb_writes();
440 struct brw_reg
interp_reg(int location
, int channel
);
442 struct brw_context
*brw
;
443 struct intel_context
*intel
;
445 struct brw_wm_compile
*c
;
446 struct brw_compile
*p
;
447 struct brw_shader
*shader
;
449 exec_list instructions
;
450 int next_abstract_grf
;
451 struct hash_table
*variable_ht
;
452 ir_variable
*frag_color
, *frag_data
, *frag_depth
;
453 int first_non_payload_grf
;
455 /** @{ debug annotation info */
456 const char *current_annotation
;
457 ir_instruction
*base_ir
;
458 const char **annotation_string
;
459 ir_instruction
**annotation_ir
;
464 /* Result of last visit() method. */
472 fs_reg interp_attrs
[64];
478 /** Fixed HW reg constructor. */
479 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
483 this->reg_offset
= 0;
484 this->hw_reg
= hw_reg
;
485 this->type
= BRW_REGISTER_TYPE_F
;
490 /** Automatic reg constructor. */
491 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
494 this->reg
= v
->next_abstract_grf
;
495 this->reg_offset
= 0;
496 v
->next_abstract_grf
+= type_size(type
);
501 switch (type
->base_type
) {
502 case GLSL_TYPE_FLOAT
:
503 this->type
= BRW_REGISTER_TYPE_F
;
507 this->type
= BRW_REGISTER_TYPE_D
;
510 this->type
= BRW_REGISTER_TYPE_UD
;
513 assert(!"not reached");
514 this->type
= BRW_REGISTER_TYPE_F
;
520 fs_visitor::variable_storage(ir_variable
*var
)
522 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
526 fs_visitor::visit(ir_variable
*ir
)
530 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
531 this->frag_color
= ir
;
532 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
533 this->frag_data
= ir
;
534 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
535 this->frag_depth
= ir
;
536 assert(!"FINISHME: this hangs currently.");
539 if (ir
->mode
== ir_var_in
) {
540 reg
= &this->interp_attrs
[ir
->location
];
543 if (ir
->mode
== ir_var_uniform
) {
544 const float *vec_values
;
545 int param_index
= c
->prog_data
.nr_params
;
547 /* FINISHME: This is wildly incomplete. */
548 assert(ir
->type
->is_scalar() || ir
->type
->is_vector() ||
549 ir
->type
->is_sampler());
551 const struct gl_program
*fp
= &this->brw
->fragment_program
->Base
;
552 /* Our support for uniforms is piggy-backed on the struct
553 * gl_fragment_program, because that's where the values actually
554 * get stored, rather than in some global gl_shader_program uniform
557 vec_values
= fp
->Parameters
->ParameterValues
[ir
->location
];
558 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
559 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
562 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
566 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
568 hash_table_insert(this->variable_ht
, reg
, ir
);
572 fs_visitor::visit(ir_dereference_variable
*ir
)
574 fs_reg
*reg
= variable_storage(ir
->var
);
579 fs_visitor::visit(ir_dereference_record
*ir
)
585 fs_visitor::visit(ir_dereference_array
*ir
)
590 ir
->array
->accept(this);
591 index
= ir
->array_index
->as_constant();
593 if (ir
->type
->is_matrix()) {
594 element_size
= ir
->type
->vector_elements
;
596 element_size
= type_size(ir
->type
);
600 assert(this->result
.file
== UNIFORM
||
601 (this->result
.file
== GRF
&&
602 this->result
.reg
!= 0));
603 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
605 assert(!"FINISHME: non-constant matrix column");
610 fs_visitor::visit(ir_expression
*ir
)
612 unsigned int operand
;
617 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
618 ir
->operands
[operand
]->accept(this);
619 if (this->result
.file
== BAD_FILE
) {
621 printf("Failed to get tree for expression operand:\n");
622 ir
->operands
[operand
]->accept(&v
);
625 op
[operand
] = this->result
;
627 /* Matrix expression operands should have been broken down to vector
628 * operations already.
630 assert(!ir
->operands
[operand
]->type
->is_matrix());
631 /* And then those vector operands should have been broken down to scalar.
633 assert(!ir
->operands
[operand
]->type
->is_vector());
636 /* Storage for our result. If our result goes into an assignment, it will
637 * just get copy-propagated out, so no worries.
639 this->result
= fs_reg(this, ir
->type
);
641 switch (ir
->operation
) {
642 case ir_unop_logic_not
:
643 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], fs_reg(-1)));
646 op
[0].negate
= ~op
[0].negate
;
647 this->result
= op
[0];
651 this->result
= op
[0];
654 temp
= fs_reg(this, ir
->type
);
656 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
657 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
659 inst
= emit(fs_inst(BRW_OPCODE_CMP
, temp
, op
[0], fs_reg(0.0f
)));
660 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
663 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, this->result
, temp
));
667 emit(fs_inst(FS_OPCODE_RCP
, this->result
, op
[0]));
671 emit(fs_inst(FS_OPCODE_EXP2
, this->result
, op
[0]));
674 emit(fs_inst(FS_OPCODE_LOG2
, this->result
, op
[0]));
678 assert(!"not reached: should be handled by ir_explog_to_explog2");
681 emit(fs_inst(FS_OPCODE_SIN
, this->result
, op
[0]));
684 emit(fs_inst(FS_OPCODE_COS
, this->result
, op
[0]));
688 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
691 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
695 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
698 assert(!"not reached: should be handled by ir_sub_to_add_neg");
702 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
705 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
708 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
712 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
713 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
714 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
716 case ir_binop_greater
:
717 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
718 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
719 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
721 case ir_binop_lequal
:
722 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
723 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
724 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
726 case ir_binop_gequal
:
727 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
728 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
729 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
732 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
733 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
734 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
736 case ir_binop_nequal
:
737 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
738 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
739 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
742 case ir_binop_logic_xor
:
743 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
746 case ir_binop_logic_or
:
747 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
750 case ir_binop_logic_and
:
751 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
757 assert(!"not reached: should be handled by brw_channel_expressions");
761 emit(fs_inst(FS_OPCODE_SQRT
, this->result
, op
[0]));
765 emit(fs_inst(FS_OPCODE_RSQ
, this->result
, op
[0]));
771 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
774 emit(fs_inst(BRW_OPCODE_RNDZ
, this->result
, op
[0]));
778 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
779 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
782 emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
785 op
[0].negate
= ~op
[0].negate
;
786 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
787 this->result
.negate
= true;
790 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
793 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
797 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
798 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
800 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
801 inst
->predicated
= true;
804 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
805 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
807 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
808 inst
->predicated
= true;
812 inst
= emit(fs_inst(FS_OPCODE_POW
, this->result
, op
[0], op
[1]));
815 case ir_unop_bit_not
:
817 case ir_binop_lshift
:
818 case ir_binop_rshift
:
819 case ir_binop_bit_and
:
820 case ir_binop_bit_xor
:
821 case ir_binop_bit_or
:
822 assert(!"GLSL 1.30 features unsupported");
828 fs_visitor::visit(ir_assignment
*ir
)
835 /* FINISHME: arrays on the lhs */
836 ir
->lhs
->accept(this);
839 ir
->rhs
->accept(this);
842 /* FINISHME: This should really set to the correct maximal writemask for each
843 * FINISHME: component written (in the loops below). This case can only
844 * FINISHME: occur for matrices, arrays, and structures.
846 if (ir
->write_mask
== 0) {
847 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
848 write_mask
= WRITEMASK_XYZW
;
850 assert(ir
->lhs
->type
->is_vector() || ir
->lhs
->type
->is_scalar());
851 write_mask
= ir
->write_mask
;
854 assert(l
.file
!= BAD_FILE
);
855 assert(r
.file
!= BAD_FILE
);
858 /* Get the condition bool into the predicate. */
859 ir
->condition
->accept(this);
860 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, fs_reg(0)));
861 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
864 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
865 if (i
>= 4 || (write_mask
& (1 << i
))) {
866 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
868 inst
->predicated
= true;
876 fs_visitor::visit(ir_texture
*ir
)
879 fs_inst
*inst
= NULL
;
880 unsigned int mlen
= 0;
882 ir
->coordinate
->accept(this);
883 fs_reg coordinate
= this->result
;
886 fs_reg inv_proj
= fs_reg(this, glsl_type::float_type
);
888 ir
->projector
->accept(this);
889 emit(fs_inst(FS_OPCODE_RCP
, inv_proj
, this->result
));
891 fs_reg proj_coordinate
= fs_reg(this, ir
->coordinate
->type
);
892 for (unsigned int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
893 emit(fs_inst(BRW_OPCODE_MUL
, proj_coordinate
, coordinate
, inv_proj
));
894 coordinate
.reg_offset
++;
895 proj_coordinate
.reg_offset
++;
897 proj_coordinate
.reg_offset
= 0;
899 coordinate
= proj_coordinate
;
902 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
903 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
904 coordinate
.reg_offset
++;
907 /* Pre-Ironlake, the 8-wide sampler always took u,v,r. */
911 if (ir
->shadow_comparitor
) {
912 /* For shadow comparisons, we have to supply u,v,r. */
915 ir
->shadow_comparitor
->accept(this);
916 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
920 /* Do we ever want to handle writemasking on texture samples? Is it
921 * performance relevant?
923 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
928 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
936 assert(!"GLSL 1.30 features unsupported");
940 if (ir
->shadow_comparitor
)
941 inst
->shadow_compare
= true;
946 fs_visitor::visit(ir_swizzle
*ir
)
948 ir
->val
->accept(this);
949 fs_reg val
= this->result
;
951 fs_reg result
= fs_reg(this, ir
->type
);
952 this->result
= result
;
954 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
955 fs_reg channel
= val
;
973 channel
.reg_offset
+= swiz
;
974 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
980 fs_visitor::visit(ir_discard
*ir
)
986 fs_visitor::visit(ir_constant
*ir
)
988 fs_reg
reg(this, ir
->type
);
991 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
992 switch (ir
->type
->base_type
) {
993 case GLSL_TYPE_FLOAT
:
994 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
997 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1000 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1002 case GLSL_TYPE_BOOL
:
1003 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1006 assert(!"Non-float/uint/int/bool constant");
1013 fs_visitor::visit(ir_if
*ir
)
1017 /* Don't point the annotation at the if statement, because then it plus
1018 * the then and else blocks get printed.
1020 this->base_ir
= ir
->condition
;
1022 /* Generate the condition into the condition code. */
1023 ir
->condition
->accept(this);
1024 inst
= emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(brw_null_reg()), this->result
));
1025 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1027 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1028 inst
->predicated
= true;
1030 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1031 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1037 if (!ir
->else_instructions
.is_empty()) {
1038 emit(fs_inst(BRW_OPCODE_ELSE
));
1040 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1041 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1048 emit(fs_inst(BRW_OPCODE_ENDIF
));
1052 fs_visitor::visit(ir_loop
*ir
)
1054 assert(!"FINISHME");
1058 fs_visitor::visit(ir_loop_jump
*ir
)
1060 assert(!"FINISHME");
1064 fs_visitor::visit(ir_call
*ir
)
1066 assert(!"FINISHME");
1070 fs_visitor::visit(ir_return
*ir
)
1072 assert(!"FINISHME");
1076 fs_visitor::visit(ir_function
*ir
)
1078 /* Ignore function bodies other than main() -- we shouldn't see calls to
1079 * them since they should all be inlined before we get to ir_to_mesa.
1081 if (strcmp(ir
->name
, "main") == 0) {
1082 const ir_function_signature
*sig
;
1085 sig
= ir
->matching_signature(&empty
);
1089 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1090 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1099 fs_visitor::visit(ir_function_signature
*ir
)
1101 assert(!"not reached");
1106 fs_visitor::emit(fs_inst inst
)
1108 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1111 list_inst
->annotation
= this->current_annotation
;
1112 list_inst
->ir
= this->base_ir
;
1114 this->instructions
.push_tail(list_inst
);
1119 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1121 fs_visitor::emit_dummy_fs()
1123 /* Everyone's favorite color. */
1124 emit(fs_inst(BRW_OPCODE_MOV
,
1127 emit(fs_inst(BRW_OPCODE_MOV
,
1130 emit(fs_inst(BRW_OPCODE_MOV
,
1133 emit(fs_inst(BRW_OPCODE_MOV
,
1138 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1143 /* The register location here is relative to the start of the URB
1144 * data. It will get adjusted to be a real location before
1145 * generate_code() time.
1148 fs_visitor::interp_reg(int location
, int channel
)
1150 int regnr
= location
* 2 + channel
/ 2;
1151 int stride
= (channel
& 1) * 4;
1153 return brw_vec1_grf(regnr
, stride
);
1156 /** Emits the interpolation for the varying inputs. */
1158 fs_visitor::emit_interpolation()
1160 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1161 /* For now, the source regs for the setup URB data will be unset,
1162 * since we don't know until codegen how many push constants we'll
1163 * use, and therefore what the setup URB offset is.
1165 fs_reg src_reg
= reg_undef
;
1167 this->current_annotation
= "compute pixel centers";
1168 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1169 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1170 emit(fs_inst(BRW_OPCODE_ADD
,
1172 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1173 fs_reg(brw_imm_v(0x10101010))));
1174 emit(fs_inst(BRW_OPCODE_ADD
,
1176 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1177 fs_reg(brw_imm_v(0x11001100))));
1179 this->current_annotation
= "compute pixel deltas from v0";
1180 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1181 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1182 emit(fs_inst(BRW_OPCODE_ADD
,
1185 fs_reg(negate(brw_vec1_grf(1, 0)))));
1186 emit(fs_inst(BRW_OPCODE_ADD
,
1189 fs_reg(brw_vec1_grf(1, 1))));
1191 this->current_annotation
= "compute pos.w and 1/pos.w";
1192 /* Compute wpos. Unlike many other varying inputs, we usually need it
1193 * to produce 1/w, and the varying variable wouldn't show up.
1195 fs_reg wpos
= fs_reg(this, glsl_type::vec4_type
);
1196 this->interp_attrs
[FRAG_ATTRIB_WPOS
] = wpos
;
1197 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
)); /* FINISHME: ARB_fcc */
1199 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
)); /* FINISHME: ARB_fcc */
1201 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
1202 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
1204 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
1205 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1206 /* Compute the pixel W value from wpos.w. */
1207 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1208 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos
));
1210 /* FINISHME: gl_FrontFacing */
1212 foreach_iter(exec_list_iterator
, iter
, *this->shader
->ir
) {
1213 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1214 ir_variable
*var
= ir
->as_variable();
1219 if (var
->mode
!= ir_var_in
)
1222 /* If it's already set up (WPOS), skip. */
1223 if (var
->location
== 0)
1226 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1228 "(FRAG_ATTRIB[%d])",
1231 emit_pinterp(var
->location
);
1233 this->current_annotation
= NULL
;
1237 fs_visitor::emit_pinterp(int location
)
1239 fs_reg interp_attr
= fs_reg(this, glsl_type::vec4_type
);
1240 this->interp_attrs
[location
] = interp_attr
;
1242 for (unsigned int i
= 0; i
< 4; i
++) {
1243 struct brw_reg interp
= interp_reg(location
, i
);
1244 emit(fs_inst(FS_OPCODE_LINTERP
,
1249 interp_attr
.reg_offset
++;
1251 interp_attr
.reg_offset
-= 4;
1253 for (unsigned int i
= 0; i
< 4; i
++) {
1254 emit(fs_inst(BRW_OPCODE_MUL
,
1258 interp_attr
.reg_offset
++;
1263 fs_visitor::emit_fb_writes()
1265 this->current_annotation
= "FB write";
1267 assert(this->frag_color
|| !"FINISHME: MRT");
1268 fs_reg color
= *(variable_storage(this->frag_color
));
1270 for (int i
= 0; i
< 4; i
++) {
1271 emit(fs_inst(BRW_OPCODE_MOV
,
1277 emit(fs_inst(FS_OPCODE_FB_WRITE
,
1281 this->current_annotation
= NULL
;
1285 fs_visitor::generate_fb_write(fs_inst
*inst
)
1287 GLboolean eot
= 1; /* FINISHME: MRT */
1288 /* FINISHME: AADS */
1290 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1293 brw_push_insn_state(p
);
1294 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1295 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1298 brw_vec8_grf(1, 0));
1299 brw_pop_insn_state(p
);
1304 8, /* dispatch_width */
1305 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
1307 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
1308 0, /* FINISHME: MRT target */
1315 fs_visitor::generate_linterp(fs_inst
*inst
,
1316 struct brw_reg dst
, struct brw_reg
*src
)
1318 struct brw_reg delta_x
= src
[0];
1319 struct brw_reg delta_y
= src
[1];
1320 struct brw_reg interp
= src
[2];
1323 delta_y
.nr
== delta_x
.nr
+ 1 &&
1324 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
1325 brw_PLN(p
, dst
, interp
, delta_x
);
1327 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
1328 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
1333 fs_visitor::generate_math(fs_inst
*inst
,
1334 struct brw_reg dst
, struct brw_reg
*src
)
1338 switch (inst
->opcode
) {
1340 op
= BRW_MATH_FUNCTION_INV
;
1343 op
= BRW_MATH_FUNCTION_RSQ
;
1345 case FS_OPCODE_SQRT
:
1346 op
= BRW_MATH_FUNCTION_SQRT
;
1348 case FS_OPCODE_EXP2
:
1349 op
= BRW_MATH_FUNCTION_EXP
;
1351 case FS_OPCODE_LOG2
:
1352 op
= BRW_MATH_FUNCTION_LOG
;
1355 op
= BRW_MATH_FUNCTION_POW
;
1358 op
= BRW_MATH_FUNCTION_SIN
;
1361 op
= BRW_MATH_FUNCTION_COS
;
1364 assert(!"not reached: unknown math function");
1369 if (inst
->opcode
== FS_OPCODE_POW
) {
1370 brw_MOV(p
, brw_message_reg(3), src
[1]);
1375 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
1376 BRW_MATH_SATURATE_NONE
,
1378 BRW_MATH_DATA_VECTOR
,
1379 BRW_MATH_PRECISION_FULL
);
1383 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
1387 if (intel
->gen
== 5) {
1388 if (inst
->shadow_compare
)
1389 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
1391 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
1393 /* Note that G45 and older determines shadow compare and dispatch width
1394 * from message length for most messages.
1396 if (inst
->shadow_compare
)
1397 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
1399 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
1402 int response_length
= 4;
1408 retype(dst
, BRW_REGISTER_TYPE_UW
),
1410 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
1411 SURF_INDEX_TEXTURE(inst
->sampler
),
1419 BRW_SAMPLER_SIMD_MODE_SIMD8
);
1423 trivial_assign_reg(int header_size
, fs_reg
*reg
)
1425 if (reg
->file
== GRF
&& reg
->reg
!= 0) {
1426 reg
->hw_reg
= header_size
+ reg
->reg
- 1 + reg
->reg_offset
;
1432 fs_visitor::assign_curb_setup()
1434 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
1435 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
1437 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1438 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1439 fs_inst
*inst
= (fs_inst
*)iter
.get();
1441 for (unsigned int i
= 0; i
< 3; i
++) {
1442 if (inst
->src
[i
].file
== UNIFORM
) {
1443 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
1444 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
1448 inst
->src
[i
].file
= FIXED_HW_REG
;
1449 inst
->src
[i
].fixed_hw_reg
= brw_reg
;
1456 fs_visitor::assign_urb_setup()
1458 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
1459 int interp_reg_nr
[FRAG_ATTRIB_MAX
];
1461 c
->prog_data
.urb_read_length
= 0;
1463 /* Figure out where each of the incoming setup attributes lands. */
1464 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
1465 interp_reg_nr
[i
] = -1;
1467 if (i
!= FRAG_ATTRIB_WPOS
&&
1468 !(brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)))
1471 /* Each attribute is 4 setup channels, each of which is half a reg. */
1472 interp_reg_nr
[i
] = urb_start
+ c
->prog_data
.urb_read_length
;
1473 c
->prog_data
.urb_read_length
+= 2;
1476 /* Map the register numbers for FS_OPCODE_LINTERP so that it uses
1477 * the correct setup input.
1479 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1480 fs_inst
*inst
= (fs_inst
*)iter
.get();
1482 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
1485 assert(inst
->src
[2].file
== FIXED_HW_REG
);
1487 int location
= inst
->src
[2].fixed_hw_reg
.nr
/ 2;
1488 assert(interp_reg_nr
[location
] != -1);
1489 inst
->src
[2].fixed_hw_reg
.nr
= (interp_reg_nr
[location
] +
1490 (inst
->src
[2].fixed_hw_reg
.nr
& 1));
1493 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
1497 fs_visitor::assign_regs()
1499 int header_size
= this->first_non_payload_grf
;
1502 /* FINISHME: trivial assignment of register numbers */
1503 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1504 fs_inst
*inst
= (fs_inst
*)iter
.get();
1506 trivial_assign_reg(header_size
, &inst
->dst
);
1507 trivial_assign_reg(header_size
, &inst
->src
[0]);
1508 trivial_assign_reg(header_size
, &inst
->src
[1]);
1510 last_grf
= MAX2(last_grf
, inst
->dst
.hw_reg
);
1511 last_grf
= MAX2(last_grf
, inst
->src
[0].hw_reg
);
1512 last_grf
= MAX2(last_grf
, inst
->src
[1].hw_reg
);
1515 this->grf_used
= last_grf
+ 1;
1518 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
1520 struct brw_reg brw_reg
;
1522 switch (reg
->file
) {
1526 brw_reg
= brw_vec8_reg(reg
->file
,
1528 brw_reg
= retype(brw_reg
, reg
->type
);
1531 switch (reg
->type
) {
1532 case BRW_REGISTER_TYPE_F
:
1533 brw_reg
= brw_imm_f(reg
->imm
.f
);
1535 case BRW_REGISTER_TYPE_D
:
1536 brw_reg
= brw_imm_d(reg
->imm
.i
);
1538 case BRW_REGISTER_TYPE_UD
:
1539 brw_reg
= brw_imm_ud(reg
->imm
.u
);
1542 assert(!"not reached");
1547 brw_reg
= reg
->fixed_hw_reg
;
1550 /* Probably unused. */
1551 brw_reg
= brw_null_reg();
1554 assert(!"not reached");
1555 brw_reg
= brw_null_reg();
1559 brw_reg
= brw_abs(brw_reg
);
1561 brw_reg
= negate(brw_reg
);
1567 fs_visitor::generate_code()
1569 unsigned int annotation_len
= 0;
1570 int last_native_inst
= 0;
1571 struct brw_instruction
*if_stack
[16];
1572 int if_stack_depth
= 0;
1574 memset(&if_stack
, 0, sizeof(if_stack
));
1575 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1576 fs_inst
*inst
= (fs_inst
*)iter
.get();
1577 struct brw_reg src
[3], dst
;
1579 for (unsigned int i
= 0; i
< 3; i
++) {
1580 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
1582 dst
= brw_reg_from_fs_reg(&inst
->dst
);
1584 brw_set_conditionalmod(p
, inst
->conditional_mod
);
1585 brw_set_predicate_control(p
, inst
->predicated
);
1587 switch (inst
->opcode
) {
1588 case BRW_OPCODE_MOV
:
1589 brw_MOV(p
, dst
, src
[0]);
1591 case BRW_OPCODE_ADD
:
1592 brw_ADD(p
, dst
, src
[0], src
[1]);
1594 case BRW_OPCODE_MUL
:
1595 brw_MUL(p
, dst
, src
[0], src
[1]);
1598 case BRW_OPCODE_FRC
:
1599 brw_FRC(p
, dst
, src
[0]);
1601 case BRW_OPCODE_RNDD
:
1602 brw_RNDD(p
, dst
, src
[0]);
1604 case BRW_OPCODE_RNDZ
:
1605 brw_RNDZ(p
, dst
, src
[0]);
1608 case BRW_OPCODE_AND
:
1609 brw_AND(p
, dst
, src
[0], src
[1]);
1612 brw_OR(p
, dst
, src
[0], src
[1]);
1614 case BRW_OPCODE_XOR
:
1615 brw_XOR(p
, dst
, src
[0], src
[1]);
1618 case BRW_OPCODE_CMP
:
1619 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1621 case BRW_OPCODE_SEL
:
1622 brw_SEL(p
, dst
, src
[0], src
[1]);
1626 assert(if_stack_depth
< 16);
1627 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
1630 case BRW_OPCODE_ELSE
:
1631 if_stack
[if_stack_depth
- 1] =
1632 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
1634 case BRW_OPCODE_ENDIF
:
1636 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
1640 case FS_OPCODE_SQRT
:
1641 case FS_OPCODE_EXP2
:
1642 case FS_OPCODE_LOG2
:
1646 generate_math(inst
, dst
, src
);
1648 case FS_OPCODE_LINTERP
:
1649 generate_linterp(inst
, dst
, src
);
1652 generate_tex(inst
, dst
, src
[0]);
1654 case FS_OPCODE_FB_WRITE
:
1655 generate_fb_write(inst
);
1658 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
1659 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
1660 brw_opcodes
[inst
->opcode
].name
);
1662 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
1667 if (annotation_len
< p
->nr_insn
) {
1668 annotation_len
*= 2;
1669 if (annotation_len
< 16)
1670 annotation_len
= 16;
1672 this->annotation_string
= talloc_realloc(this->mem_ctx
,
1676 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
1682 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
1683 this->annotation_string
[i
] = inst
->annotation
;
1684 this->annotation_ir
[i
] = inst
->ir
;
1686 last_native_inst
= p
->nr_insn
;
1691 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
1693 struct brw_compile
*p
= &c
->func
;
1694 struct intel_context
*intel
= &brw
->intel
;
1695 GLcontext
*ctx
= &intel
->ctx
;
1696 struct brw_shader
*shader
= NULL
;
1697 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
1705 for (unsigned int i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
1706 if (prog
->_LinkedShaders
[i
]->Type
== GL_FRAGMENT_SHADER
) {
1707 shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
1714 /* We always use 8-wide mode, at least for now. For one, flow
1715 * control only works in 8-wide. Also, when we're fragment shader
1716 * bound, we're almost always under register pressure as well, so
1717 * 8-wide would save us from the performance cliff of spilling
1720 c
->dispatch_width
= 8;
1722 if (INTEL_DEBUG
& DEBUG_WM
) {
1723 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
1724 _mesa_print_ir(shader
->ir
, NULL
);
1728 /* Now the main event: Visit the shader IR and generate our FS IR for it.
1730 fs_visitor
v(c
, shader
);
1735 v
.emit_interpolation();
1737 /* Generate FS IR for main(). (the visitor only descends into
1738 * functions called "main").
1740 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
1741 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1750 v
.assign_curb_setup();
1751 v
.assign_urb_setup();
1757 if (INTEL_DEBUG
& DEBUG_WM
) {
1758 const char *last_annotation_string
= NULL
;
1759 ir_instruction
*last_annotation_ir
= NULL
;
1761 printf("Native code for fragment shader %d:\n", prog
->Name
);
1762 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
1763 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
1764 last_annotation_ir
= v
.annotation_ir
[i
];
1765 if (last_annotation_ir
) {
1767 last_annotation_ir
->print();
1771 if (last_annotation_string
!= v
.annotation_string
[i
]) {
1772 last_annotation_string
= v
.annotation_string
[i
];
1773 if (last_annotation_string
)
1774 printf(" %s\n", last_annotation_string
);
1776 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
1781 c
->prog_data
.total_grf
= v
.grf_used
;
1782 c
->prog_data
.total_scratch
= 0;