2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
33 #include <sys/types.h>
35 #include "util/hash_table.h"
36 #include "main/macros.h"
37 #include "main/shaderobj.h"
38 #include "main/fbobject.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "util/register_allocate.h"
42 #include "program/sampler.h"
43 #include "program/hash_table.h"
44 #include "brw_context.h"
50 #include "brw_dead_control_flow.h"
51 #include "main/uniforms.h"
52 #include "brw_fs_live_variables.h"
53 #include "glsl/glsl_types.h"
56 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
57 fs_reg
*src
, int sources
)
59 memset(this, 0, sizeof(*this));
61 this->opcode
= opcode
;
64 this->sources
= sources
;
65 this->exec_size
= exec_size
;
67 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
69 /* If exec_size == 0, try to guess it from the registers. Since all
70 * manner of things may use hardware registers, we first try to guess
71 * based on GRF registers. If this fails, we will go ahead and take the
72 * width from the destination register.
74 if (this->exec_size
== 0) {
75 if (dst
.file
== GRF
) {
76 this->exec_size
= dst
.width
;
78 for (int i
= 0; i
< sources
; ++i
) {
79 if (src
[i
].file
!= GRF
)
82 if (this->exec_size
<= 1)
83 this->exec_size
= src
[i
].width
;
84 assert(src
[i
].width
== 1 || src
[i
].width
== this->exec_size
);
88 if (this->exec_size
== 0 && dst
.file
!= BAD_FILE
)
89 this->exec_size
= dst
.width
;
91 assert(this->exec_size
!= 0);
93 for (int i
= 0; i
< sources
; ++i
) {
94 switch (this->src
[i
].file
) {
96 this->src
[i
].effective_width
= 8;
100 assert(this->src
[i
].width
> 0);
101 if (this->src
[i
].width
== 1) {
102 this->src
[i
].effective_width
= this->exec_size
;
104 this->src
[i
].effective_width
= this->src
[i
].width
;
109 this->src
[i
].effective_width
= this->exec_size
;
112 unreachable("Invalid source register file");
115 this->dst
.effective_width
= this->exec_size
;
117 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
119 /* This will be the case for almost all instructions. */
124 this->regs_written
= (dst
.width
* dst
.stride
* type_sz(dst
.type
) + 31) / 32;
127 this->regs_written
= 0;
131 unreachable("Invalid destination register file");
133 unreachable("Invalid register file");
136 this->writes_accumulator
= false;
141 fs_reg
*src
= ralloc_array(this, fs_reg
, 3);
142 init(BRW_OPCODE_NOP
, 8, dst
, src
, 0);
145 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
147 fs_reg
*src
= ralloc_array(this, fs_reg
, 3);
148 init(opcode
, exec_size
, reg_undef
, src
, 0);
151 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
)
153 fs_reg
*src
= ralloc_array(this, fs_reg
, 3);
154 init(opcode
, 0, dst
, src
, 0);
157 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
160 fs_reg
*src
= ralloc_array(this, fs_reg
, 3);
162 init(opcode
, exec_size
, dst
, src
, 1);
165 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
)
167 fs_reg
*src
= ralloc_array(this, fs_reg
, 3);
169 init(opcode
, 0, dst
, src
, 1);
172 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
173 const fs_reg
&src0
, const fs_reg
&src1
)
175 fs_reg
*src
= ralloc_array(this, fs_reg
, 3);
178 init(opcode
, exec_size
, dst
, src
, 2);
181 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
184 fs_reg
*src
= ralloc_array(this, fs_reg
, 3);
187 init(opcode
, 0, dst
, src
, 2);
190 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
191 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
193 fs_reg
*src
= ralloc_array(this, fs_reg
, 3);
197 init(opcode
, exec_size
, dst
, src
, 3);
200 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
201 const fs_reg
&src1
, const fs_reg
&src2
)
203 fs_reg
*src
= ralloc_array(this, fs_reg
, 3);
207 init(opcode
, 0, dst
, src
, 3);
210 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, fs_reg src
[], int sources
)
212 init(opcode
, 0, dst
, src
, sources
);
215 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
216 fs_reg src
[], int sources
)
218 init(opcode
, exec_width
, dst
, src
, sources
);
221 fs_inst::fs_inst(const fs_inst
&that
)
223 memcpy(this, &that
, sizeof(that
));
225 this->src
= ralloc_array(this, fs_reg
, that
.sources
);
227 for (int i
= 0; i
< that
.sources
; i
++)
228 this->src
[i
] = that
.src
[i
];
232 fs_inst::resize_sources(uint8_t num_sources
)
234 if (this->sources
!= num_sources
) {
235 this->src
= reralloc(this, this->src
, fs_reg
, num_sources
);
236 this->sources
= num_sources
;
242 fs_visitor::op(const fs_reg &dst, const fs_reg &src0) \
244 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0); \
249 fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
250 const fs_reg &src1) \
252 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1); \
255 #define ALU2_ACC(op) \
257 fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
258 const fs_reg &src1) \
260 fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1);\
261 inst->writes_accumulator = true; \
267 fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
268 const fs_reg &src1, const fs_reg &src2) \
270 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1, src2);\
302 /** Gen4 predicated IF. */
304 fs_visitor::IF(enum brw_predicate predicate
)
306 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
, dispatch_width
);
307 inst
->predicate
= predicate
;
311 /** Gen6 IF with embedded comparison. */
313 fs_visitor::IF(const fs_reg
&src0
, const fs_reg
&src1
,
314 enum brw_conditional_mod condition
)
316 assert(brw
->gen
== 6);
317 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
, dispatch_width
,
318 reg_null_d
, src0
, src1
);
319 inst
->conditional_mod
= condition
;
324 * CMP: Sets the low bit of the destination channels with the result
325 * of the comparison, while the upper bits are undefined, and updates
326 * the flag register with the packed 16 bits of the result.
329 fs_visitor::CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
,
330 enum brw_conditional_mod condition
)
334 /* Take the instruction:
336 * CMP null<d> src0<f> src1<f>
338 * Original gen4 does type conversion to the destination type before
339 * comparison, producing garbage results for floating point comparisons.
340 * gen5 does the comparison on the execution type (resolved source types),
341 * so dst type doesn't matter. gen6 does comparison and then uses the
342 * result as if it was the dst type with no conversion, which happens to
343 * mostly work out for float-interpreted-as-int since our comparisons are
347 dst
.type
= src0
.type
;
348 if (dst
.file
== HW_REG
)
349 dst
.fixed_hw_reg
.type
= dst
.type
;
352 resolve_ud_negate(&src0
);
353 resolve_ud_negate(&src1
);
355 inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_CMP
, dst
, src0
, src1
);
356 inst
->conditional_mod
= condition
;
362 fs_visitor::LOAD_PAYLOAD(const fs_reg
&dst
, fs_reg
*src
, int sources
)
364 uint8_t exec_size
= dst
.width
;
365 for (int i
= 0; i
< sources
; ++i
) {
366 assert(src
[i
].width
% dst
.width
== 0);
367 if (src
[i
].width
> exec_size
)
368 exec_size
= src
[i
].width
;
371 fs_inst
*inst
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
, exec_size
,
373 inst
->regs_written
= 0;
374 for (int i
= 0; i
< sources
; ++i
) {
375 /* The LOAD_PAYLOAD instruction only really makes sense if we are
376 * dealing with whole registers. If this ever changes, we can deal
379 int size
= src
[i
].effective_width
* type_sz(src
[i
].type
);
380 assert(size
% 32 == 0);
381 inst
->regs_written
+= (size
+ 31) / 32;
388 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_reg
&dst
,
389 const fs_reg
&surf_index
,
390 const fs_reg
&varying_offset
,
391 uint32_t const_offset
)
393 exec_list instructions
;
396 /* We have our constant surface use a pitch of 4 bytes, so our index can
397 * be any component of a vector, and then we load 4 contiguous
398 * components starting from that.
400 * We break down the const_offset to a portion added to the variable
401 * offset and a portion done using reg_offset, which means that if you
402 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
403 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
404 * CSE can later notice that those loads are all the same and eliminate
405 * the redundant ones.
407 fs_reg vec4_offset
= fs_reg(this, glsl_type::int_type
);
408 instructions
.push_tail(ADD(vec4_offset
,
409 varying_offset
, fs_reg(const_offset
& ~3)));
412 if (brw
->gen
== 4 && dst
.width
== 8) {
413 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
414 * u, v, r) as parameters, or we can just use the SIMD16 message
415 * consisting of (header, u). We choose the second, at the cost of a
416 * longer return length.
423 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
425 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
427 assert(dst
.width
% 8 == 0);
428 int regs_written
= 4 * (dst
.width
/ 8) * scale
;
429 fs_reg vec4_result
= fs_reg(GRF
, virtual_grf_alloc(regs_written
),
430 dst
.type
, dst
.width
);
431 inst
= new(mem_ctx
) fs_inst(op
, vec4_result
, surf_index
, vec4_offset
);
432 inst
->regs_written
= regs_written
;
433 instructions
.push_tail(inst
);
437 inst
->header_present
= true;
441 inst
->mlen
= 1 + dispatch_width
/ 8;
444 fs_reg result
= offset(vec4_result
, (const_offset
& 3) * scale
);
445 instructions
.push_tail(MOV(dst
, result
));
451 * A helper for MOV generation for fixing up broken hardware SEND dependency
455 fs_visitor::DEP_RESOLVE_MOV(int grf
)
457 fs_inst
*inst
= MOV(brw_null_reg(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
460 inst
->annotation
= "send dependency resolve";
462 /* The caller always wants uncompressed to emit the minimal extra
463 * dependencies, and to avoid having to deal with aligning its regs to 2.
471 fs_inst::equals(fs_inst
*inst
) const
473 return (opcode
== inst
->opcode
&&
474 dst
.equals(inst
->dst
) &&
475 src
[0].equals(inst
->src
[0]) &&
476 src
[1].equals(inst
->src
[1]) &&
477 src
[2].equals(inst
->src
[2]) &&
478 saturate
== inst
->saturate
&&
479 predicate
== inst
->predicate
&&
480 conditional_mod
== inst
->conditional_mod
&&
481 mlen
== inst
->mlen
&&
482 base_mrf
== inst
->base_mrf
&&
483 target
== inst
->target
&&
485 header_present
== inst
->header_present
&&
486 shadow_compare
== inst
->shadow_compare
&&
487 exec_size
== inst
->exec_size
&&
488 offset
== inst
->offset
);
492 fs_inst::overwrites_reg(const fs_reg
®
) const
494 return (reg
.file
== dst
.file
&&
495 reg
.reg
== dst
.reg
&&
496 reg
.reg_offset
>= dst
.reg_offset
&&
497 reg
.reg_offset
< dst
.reg_offset
+ regs_written
);
501 fs_inst::is_send_from_grf() const
504 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
505 case SHADER_OPCODE_SHADER_TIME_ADD
:
506 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
507 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
508 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
509 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
510 case SHADER_OPCODE_UNTYPED_ATOMIC
:
511 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
513 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
514 return src
[1].file
== GRF
;
515 case FS_OPCODE_FB_WRITE
:
516 return src
[0].file
== GRF
;
519 return src
[0].file
== GRF
;
526 fs_inst::can_do_source_mods(struct brw_context
*brw
)
528 if (brw
->gen
== 6 && is_math())
531 if (is_send_from_grf())
534 if (!backend_instruction::can_do_source_mods())
543 memset(this, 0, sizeof(*this));
547 /** Generic unset register constructor. */
551 this->file
= BAD_FILE
;
554 /** Immediate value constructor. */
555 fs_reg::fs_reg(float f
)
559 this->type
= BRW_REGISTER_TYPE_F
;
560 this->fixed_hw_reg
.dw1
.f
= f
;
564 /** Immediate value constructor. */
565 fs_reg::fs_reg(int32_t i
)
569 this->type
= BRW_REGISTER_TYPE_D
;
570 this->fixed_hw_reg
.dw1
.d
= i
;
574 /** Immediate value constructor. */
575 fs_reg::fs_reg(uint32_t u
)
579 this->type
= BRW_REGISTER_TYPE_UD
;
580 this->fixed_hw_reg
.dw1
.ud
= u
;
584 /** Vector float immediate value constructor. */
585 fs_reg::fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
589 this->type
= BRW_REGISTER_TYPE_VF
;
590 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
596 /** Fixed brw_reg. */
597 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
601 this->fixed_hw_reg
= fixed_hw_reg
;
602 this->type
= fixed_hw_reg
.type
;
603 this->width
= 1 << fixed_hw_reg
.width
;
607 fs_reg::equals(const fs_reg
&r
) const
609 return (file
== r
.file
&&
611 reg_offset
== r
.reg_offset
&&
612 subreg_offset
== r
.subreg_offset
&&
614 negate
== r
.negate
&&
616 !reladdr
&& !r
.reladdr
&&
617 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
, sizeof(fixed_hw_reg
)) == 0 &&
623 fs_reg::set_smear(unsigned subreg
)
625 assert(file
!= HW_REG
&& file
!= IMM
);
626 subreg_offset
= subreg
* type_sz(type
);
632 fs_reg::is_contiguous() const
638 fs_visitor::type_size(const struct glsl_type
*type
)
640 unsigned int size
, i
;
642 switch (type
->base_type
) {
645 case GLSL_TYPE_FLOAT
:
647 return type
->components();
648 case GLSL_TYPE_ARRAY
:
649 return type_size(type
->fields
.array
) * type
->length
;
650 case GLSL_TYPE_STRUCT
:
652 for (i
= 0; i
< type
->length
; i
++) {
653 size
+= type_size(type
->fields
.structure
[i
].type
);
656 case GLSL_TYPE_SAMPLER
:
657 /* Samplers take up no register space, since they're baked in at
661 case GLSL_TYPE_ATOMIC_UINT
:
663 case GLSL_TYPE_IMAGE
:
665 case GLSL_TYPE_ERROR
:
666 case GLSL_TYPE_INTERFACE
:
667 unreachable("not reached");
674 fs_visitor::get_timestamp()
676 assert(brw
->gen
>= 7);
678 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
681 BRW_REGISTER_TYPE_UD
));
683 fs_reg dst
= fs_reg(GRF
, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD
, 4);
685 fs_inst
*mov
= emit(MOV(dst
, ts
));
686 /* We want to read the 3 fields we care about even if it's not enabled in
689 mov
->force_writemask_all
= true;
691 /* The caller wants the low 32 bits of the timestamp. Since it's running
692 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
693 * which is plenty of time for our purposes. It is identical across the
694 * EUs, but since it's tracking GPU core speed it will increment at a
695 * varying rate as render P-states change.
697 * The caller could also check if render P-states have changed (or anything
698 * else that might disrupt timing) by setting smear to 2 and checking if
699 * that field is != 0.
707 fs_visitor::emit_shader_time_begin()
709 current_annotation
= "shader time start";
710 shader_start_time
= get_timestamp();
714 fs_visitor::emit_shader_time_end()
716 current_annotation
= "shader time end";
718 enum shader_time_shader_type type
, written_type
, reset_type
;
719 if (dispatch_width
== 8) {
721 written_type
= ST_FS8_WRITTEN
;
722 reset_type
= ST_FS8_RESET
;
724 assert(dispatch_width
== 16);
726 written_type
= ST_FS16_WRITTEN
;
727 reset_type
= ST_FS16_RESET
;
730 fs_reg shader_end_time
= get_timestamp();
732 /* Check that there weren't any timestamp reset events (assuming these
733 * were the only two timestamp reads that happened).
735 fs_reg reset
= shader_end_time
;
737 fs_inst
*test
= emit(AND(reg_null_d
, reset
, fs_reg(1u)));
738 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
739 emit(IF(BRW_PREDICATE_NORMAL
));
741 fs_reg start
= shader_start_time
;
743 fs_reg diff
= fs_reg(GRF
, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD
, 1);
744 emit(ADD(diff
, start
, shader_end_time
));
746 /* If there were no instructions between the two timestamp gets, the diff
747 * is 2 cycles. Remove that overhead, so I can forget about that when
748 * trying to determine the time taken for single instructions.
750 emit(ADD(diff
, diff
, fs_reg(-2u)));
752 emit_shader_time_write(type
, diff
);
753 emit_shader_time_write(written_type
, fs_reg(1u));
754 emit(BRW_OPCODE_ELSE
);
755 emit_shader_time_write(reset_type
, fs_reg(1u));
756 emit(BRW_OPCODE_ENDIF
);
760 fs_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
763 int shader_time_index
=
764 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
765 fs_reg offset
= fs_reg(shader_time_index
* SHADER_TIME_STRIDE
);
768 if (dispatch_width
== 8)
769 payload
= fs_reg(this, glsl_type::uvec2_type
);
771 payload
= fs_reg(this, glsl_type::uint_type
);
773 emit(new(mem_ctx
) fs_inst(SHADER_OPCODE_SHADER_TIME_ADD
,
774 fs_reg(), payload
, offset
, value
));
778 fs_visitor::vfail(const char *format
, va_list va
)
787 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
788 msg
= ralloc_asprintf(mem_ctx
, "FS compile failed: %s\n", msg
);
790 this->fail_msg
= msg
;
792 if (INTEL_DEBUG
& DEBUG_WM
) {
793 fprintf(stderr
, "%s", msg
);
798 fs_visitor::fail(const char *format
, ...)
802 va_start(va
, format
);
808 * Mark this program as impossible to compile in SIMD16 mode.
810 * During the SIMD8 compile (which happens first), we can detect and flag
811 * things that are unsupported in SIMD16 mode, so the compiler can skip
812 * the SIMD16 compile altogether.
814 * During a SIMD16 compile (if one happens anyway), this just calls fail().
817 fs_visitor::no16(const char *format
, ...)
821 va_start(va
, format
);
823 if (dispatch_width
== 16) {
826 simd16_unsupported
= true;
828 if (brw
->perf_debug
) {
830 ralloc_vasprintf_append(&no16_msg
, format
, va
);
832 no16_msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
840 fs_visitor::emit(enum opcode opcode
)
842 return emit(new(mem_ctx
) fs_inst(opcode
, dispatch_width
));
846 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
)
848 return emit(new(mem_ctx
) fs_inst(opcode
, dst
));
852 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
)
854 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
));
858 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
861 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
, src1
));
865 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
866 const fs_reg
&src1
, const fs_reg
&src2
)
868 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
, src1
, src2
));
872 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
,
873 fs_reg src
[], int sources
)
875 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src
, sources
));
879 * Returns true if the instruction has a flag that means it won't
880 * update an entire destination register.
882 * For example, dead code elimination and live variable analysis want to know
883 * when a write to a variable screens off any preceding values that were in
887 fs_inst::is_partial_write() const
889 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
890 (this->dst
.width
* type_sz(this->dst
.type
)) < 32 ||
891 !this->dst
.is_contiguous());
895 fs_inst::regs_read(fs_visitor
*v
, int arg
) const
897 if (is_tex() && arg
== 0 && src
[0].file
== GRF
) {
899 } else if (opcode
== FS_OPCODE_FB_WRITE
&& arg
== 0) {
901 } else if (opcode
== SHADER_OPCODE_UNTYPED_ATOMIC
&& arg
== 0) {
903 } else if (opcode
== SHADER_OPCODE_UNTYPED_SURFACE_READ
&& arg
== 0) {
905 } else if (opcode
== FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
&& arg
== 0) {
909 switch (src
[arg
].file
) {
916 if (src
[arg
].stride
== 0) {
919 int size
= src
[arg
].width
* src
[arg
].stride
* type_sz(src
[arg
].type
);
920 return (size
+ 31) / 32;
923 unreachable("MRF registers are not allowed as sources");
925 unreachable("Invalid register file");
930 fs_inst::reads_flag() const
936 fs_inst::writes_flag() const
938 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
939 opcode
!= BRW_OPCODE_IF
&&
940 opcode
!= BRW_OPCODE_WHILE
)) ||
941 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
945 * Returns how many MRFs an FS opcode will write over.
947 * Note that this is not the 0 or 1 implied writes in an actual gen
948 * instruction -- the FS opcodes often generate MOVs in addition.
951 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
956 if (inst
->base_mrf
== -1)
959 switch (inst
->opcode
) {
960 case SHADER_OPCODE_RCP
:
961 case SHADER_OPCODE_RSQ
:
962 case SHADER_OPCODE_SQRT
:
963 case SHADER_OPCODE_EXP2
:
964 case SHADER_OPCODE_LOG2
:
965 case SHADER_OPCODE_SIN
:
966 case SHADER_OPCODE_COS
:
967 return 1 * dispatch_width
/ 8;
968 case SHADER_OPCODE_POW
:
969 case SHADER_OPCODE_INT_QUOTIENT
:
970 case SHADER_OPCODE_INT_REMAINDER
:
971 return 2 * dispatch_width
/ 8;
972 case SHADER_OPCODE_TEX
:
974 case SHADER_OPCODE_TXD
:
975 case SHADER_OPCODE_TXF
:
976 case SHADER_OPCODE_TXF_CMS
:
977 case SHADER_OPCODE_TXF_MCS
:
978 case SHADER_OPCODE_TG4
:
979 case SHADER_OPCODE_TG4_OFFSET
:
980 case SHADER_OPCODE_TXL
:
981 case SHADER_OPCODE_TXS
:
982 case SHADER_OPCODE_LOD
:
984 case FS_OPCODE_FB_WRITE
:
986 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
987 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
989 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
991 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
993 case SHADER_OPCODE_UNTYPED_ATOMIC
:
994 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
995 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
996 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
997 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
998 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
1001 unreachable("not reached");
1006 fs_visitor::virtual_grf_alloc(int size
)
1008 if (virtual_grf_array_size
<= virtual_grf_count
) {
1009 if (virtual_grf_array_size
== 0)
1010 virtual_grf_array_size
= 16;
1012 virtual_grf_array_size
*= 2;
1013 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
1014 virtual_grf_array_size
);
1016 virtual_grf_sizes
[virtual_grf_count
] = size
;
1017 return virtual_grf_count
++;
1020 /** Fixed HW reg constructor. */
1021 fs_reg::fs_reg(enum register_file file
, int reg
)
1026 this->type
= BRW_REGISTER_TYPE_F
;
1037 /** Fixed HW reg constructor. */
1038 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
)
1054 /** Fixed HW reg constructor. */
1055 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
,
1062 this->width
= width
;
1065 /** Automatic reg constructor. */
1066 fs_reg::fs_reg(fs_visitor
*v
, const struct glsl_type
*type
)
1069 int reg_width
= v
->dispatch_width
/ 8;
1072 this->reg
= v
->virtual_grf_alloc(v
->type_size(type
) * reg_width
);
1073 this->reg_offset
= 0;
1074 this->type
= brw_type_for_base_type(type
);
1075 this->width
= v
->dispatch_width
;
1076 assert(this->width
== 8 || this->width
== 16);
1080 fs_visitor::variable_storage(ir_variable
*var
)
1082 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
1086 import_uniforms_callback(const void *key
,
1090 struct hash_table
*dst_ht
= (struct hash_table
*)closure
;
1091 const fs_reg
*reg
= (const fs_reg
*)data
;
1093 if (reg
->file
!= UNIFORM
)
1096 hash_table_insert(dst_ht
, data
, key
);
1099 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1100 * This brings in those uniform definitions
1103 fs_visitor::import_uniforms(fs_visitor
*v
)
1105 hash_table_call_foreach(v
->variable_ht
,
1106 import_uniforms_callback
,
1108 this->push_constant_loc
= v
->push_constant_loc
;
1109 this->pull_constant_loc
= v
->pull_constant_loc
;
1110 this->uniforms
= v
->uniforms
;
1111 this->param_size
= v
->param_size
;
1114 /* Our support for uniforms is piggy-backed on the struct
1115 * gl_fragment_program, because that's where the values actually
1116 * get stored, rather than in some global gl_shader_program uniform
1120 fs_visitor::setup_uniform_values(ir_variable
*ir
)
1122 int namelen
= strlen(ir
->name
);
1124 /* The data for our (non-builtin) uniforms is stored in a series of
1125 * gl_uniform_driver_storage structs for each subcomponent that
1126 * glGetUniformLocation() could name. We know it's been set up in the same
1127 * order we'd walk the type, so walk the list of storage and find anything
1128 * with our name, or the prefix of a component that starts with our name.
1130 unsigned params_before
= uniforms
;
1131 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
1132 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
1134 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
1135 (storage
->name
[namelen
] != 0 &&
1136 storage
->name
[namelen
] != '.' &&
1137 storage
->name
[namelen
] != '[')) {
1141 unsigned slots
= storage
->type
->component_slots();
1142 if (storage
->array_elements
)
1143 slots
*= storage
->array_elements
;
1145 for (unsigned i
= 0; i
< slots
; i
++) {
1146 stage_prog_data
->param
[uniforms
++] = &storage
->storage
[i
];
1150 /* Make sure we actually initialized the right amount of stuff here. */
1151 assert(params_before
+ ir
->type
->component_slots() == uniforms
);
1152 (void)params_before
;
1156 /* Our support for builtin uniforms is even scarier than non-builtin.
1157 * It sits on top of the PROG_STATE_VAR parameters that are
1158 * automatically updated from GL context state.
1161 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
1163 const ir_state_slot
*const slots
= ir
->get_state_slots();
1164 assert(slots
!= NULL
);
1166 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1167 /* This state reference has already been setup by ir_to_mesa, but we'll
1168 * get the same index back here.
1170 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1171 (gl_state_index
*)slots
[i
].tokens
);
1173 /* Add each of the unique swizzles of the element as a parameter.
1174 * This'll end up matching the expected layout of the
1175 * array/matrix/structure we're trying to fill in.
1178 for (unsigned int j
= 0; j
< 4; j
++) {
1179 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
1180 if (swiz
== last_swiz
)
1184 stage_prog_data
->param
[uniforms
++] =
1185 &prog
->Parameters
->ParameterValues
[index
][swiz
];
1191 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
1193 assert(stage
== MESA_SHADER_FRAGMENT
);
1194 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1195 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1197 bool flip
= !ir
->data
.origin_upper_left
^ key
->render_to_fbo
;
1199 /* gl_FragCoord.x */
1200 if (ir
->data
.pixel_center_integer
) {
1201 emit(MOV(wpos
, this->pixel_x
));
1203 emit(ADD(wpos
, this->pixel_x
, fs_reg(0.5f
)));
1205 wpos
= offset(wpos
, 1);
1207 /* gl_FragCoord.y */
1208 if (!flip
&& ir
->data
.pixel_center_integer
) {
1209 emit(MOV(wpos
, this->pixel_y
));
1211 fs_reg pixel_y
= this->pixel_y
;
1212 float offset
= (ir
->data
.pixel_center_integer
? 0.0 : 0.5);
1215 pixel_y
.negate
= true;
1216 offset
+= key
->drawable_height
- 1.0;
1219 emit(ADD(wpos
, pixel_y
, fs_reg(offset
)));
1221 wpos
= offset(wpos
, 1);
1223 /* gl_FragCoord.z */
1224 if (brw
->gen
>= 6) {
1225 emit(MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0))));
1227 emit(FS_OPCODE_LINTERP
, wpos
,
1228 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1229 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1230 interp_reg(VARYING_SLOT_POS
, 2));
1232 wpos
= offset(wpos
, 1);
1234 /* gl_FragCoord.w: Already set up in emit_interpolation */
1235 emit(BRW_OPCODE_MOV
, wpos
, this->wpos_w
);
1241 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1242 glsl_interp_qualifier interpolation_mode
,
1243 bool is_centroid
, bool is_sample
)
1245 brw_wm_barycentric_interp_mode barycoord_mode
;
1246 if (brw
->gen
>= 6) {
1248 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1249 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1251 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1252 } else if (is_sample
) {
1253 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1254 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1256 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1258 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1259 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1261 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1264 /* On Ironlake and below, there is only one interpolation mode.
1265 * Centroid interpolation doesn't mean anything on this hardware --
1266 * there is no multisampling.
1268 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1270 return emit(FS_OPCODE_LINTERP
, attr
,
1271 this->delta_x
[barycoord_mode
],
1272 this->delta_y
[barycoord_mode
], interp
);
1276 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
1278 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1279 reg
->type
= brw_type_for_base_type(ir
->type
->get_scalar_type());
1282 assert(stage
== MESA_SHADER_FRAGMENT
);
1283 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1284 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1286 unsigned int array_elements
;
1287 const glsl_type
*type
;
1289 if (ir
->type
->is_array()) {
1290 array_elements
= ir
->type
->length
;
1291 if (array_elements
== 0) {
1292 fail("dereferenced array '%s' has length 0\n", ir
->name
);
1294 type
= ir
->type
->fields
.array
;
1300 glsl_interp_qualifier interpolation_mode
=
1301 ir
->determine_interpolation_mode(key
->flat_shade
);
1303 int location
= ir
->data
.location
;
1304 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1305 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1306 if (prog_data
->urb_setup
[location
] == -1) {
1307 /* If there's no incoming setup data for this slot, don't
1308 * emit interpolation for it.
1310 attr
= offset(attr
, type
->vector_elements
);
1315 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1316 /* Constant interpolation (flat shading) case. The SF has
1317 * handed us defined values in only the constant offset
1318 * field of the setup reg.
1320 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1321 struct brw_reg interp
= interp_reg(location
, k
);
1322 interp
= suboffset(interp
, 3);
1323 interp
.type
= reg
->type
;
1324 emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1325 attr
= offset(attr
, 1);
1328 /* Smooth/noperspective interpolation case. */
1329 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1330 struct brw_reg interp
= interp_reg(location
, k
);
1331 if (brw
->needs_unlit_centroid_workaround
&& ir
->data
.centroid
) {
1332 /* Get the pixel/sample mask into f0 so that we know
1333 * which pixels are lit. Then, for each channel that is
1334 * unlit, replace the centroid data with non-centroid
1337 emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1340 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1342 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1343 inst
->predicate_inverse
= true;
1345 inst
->no_dd_clear
= true;
1347 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1348 ir
->data
.centroid
&& !key
->persample_shading
,
1349 ir
->data
.sample
|| key
->persample_shading
);
1350 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1351 inst
->predicate_inverse
= false;
1353 inst
->no_dd_check
= true;
1356 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1357 ir
->data
.centroid
&& !key
->persample_shading
,
1358 ir
->data
.sample
|| key
->persample_shading
);
1360 if (brw
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1361 emit(BRW_OPCODE_MUL
, attr
, attr
, this->pixel_w
);
1363 attr
= offset(attr
, 1);
1375 fs_visitor::emit_frontfacing_interpolation()
1377 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, glsl_type::bool_type
);
1379 if (brw
->gen
>= 6) {
1380 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1381 * a boolean result from this (~0/true or 0/false).
1383 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1384 * this task in only one instruction:
1385 * - a negation source modifier will flip the bit; and
1386 * - a W -> D type conversion will sign extend the bit into the high
1387 * word of the destination.
1389 * An ASR 15 fills the low word of the destination.
1391 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1394 emit(ASR(*reg
, g0
, fs_reg(15)));
1396 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1397 * a boolean result from this (1/true or 0/false).
1399 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1400 * the negation source modifier to flip it. Unfortunately the SHR
1401 * instruction only operates on UD (or D with an abs source modifier)
1402 * sources without negation.
1404 * Instead, use ASR (which will give ~0/true or 0/false).
1406 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1409 emit(ASR(*reg
, g1_6
, fs_reg(31)));
1416 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1418 assert(stage
== MESA_SHADER_FRAGMENT
);
1419 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1420 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1422 if (key
->compute_pos_offset
) {
1423 /* Convert int_sample_pos to floating point */
1424 emit(MOV(dst
, int_sample_pos
));
1425 /* Scale to the range [0, 1] */
1426 emit(MUL(dst
, dst
, fs_reg(1 / 16.0f
)));
1429 /* From ARB_sample_shading specification:
1430 * "When rendering to a non-multisample buffer, or if multisample
1431 * rasterization is disabled, gl_SamplePosition will always be
1434 emit(MOV(dst
, fs_reg(0.5f
)));
1439 fs_visitor::emit_samplepos_setup()
1441 assert(brw
->gen
>= 6);
1443 this->current_annotation
= "compute sample position";
1444 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, glsl_type::vec2_type
);
1446 fs_reg int_sample_x
= fs_reg(this, glsl_type::int_type
);
1447 fs_reg int_sample_y
= fs_reg(this, glsl_type::int_type
);
1449 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1450 * mode will be enabled.
1452 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1453 * R31.1:0 Position Offset X/Y for Slot[3:0]
1454 * R31.3:2 Position Offset X/Y for Slot[7:4]
1457 * The X, Y sample positions come in as bytes in thread payload. So, read
1458 * the positions using vstride=16, width=8, hstride=2.
1460 struct brw_reg sample_pos_reg
=
1461 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1462 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1464 if (dispatch_width
== 8) {
1465 emit(MOV(int_sample_x
, fs_reg(sample_pos_reg
)));
1467 emit(MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
)));
1468 emit(MOV(half(int_sample_x
, 1), fs_reg(suboffset(sample_pos_reg
, 16))))
1469 ->force_sechalf
= true;
1471 /* Compute gl_SamplePosition.x */
1472 compute_sample_position(pos
, int_sample_x
);
1473 pos
= offset(pos
, 1);
1474 if (dispatch_width
== 8) {
1475 emit(MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1))));
1477 emit(MOV(half(int_sample_y
, 0),
1478 fs_reg(suboffset(sample_pos_reg
, 1))));
1479 emit(MOV(half(int_sample_y
, 1), fs_reg(suboffset(sample_pos_reg
, 17))))
1480 ->force_sechalf
= true;
1482 /* Compute gl_SamplePosition.y */
1483 compute_sample_position(pos
, int_sample_y
);
1488 fs_visitor::emit_sampleid_setup()
1490 assert(stage
== MESA_SHADER_FRAGMENT
);
1491 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1492 assert(brw
->gen
>= 6);
1494 this->current_annotation
= "compute sample id";
1495 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, glsl_type::int_type
);
1497 if (key
->compute_sample_id
) {
1498 fs_reg t1
= fs_reg(this, glsl_type::int_type
);
1499 fs_reg t2
= fs_reg(this, glsl_type::int_type
);
1500 t2
.type
= BRW_REGISTER_TYPE_UW
;
1502 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1503 * 8x multisampling, subspan 0 will represent sample N (where N
1504 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1505 * 7. We can find the value of N by looking at R0.0 bits 7:6
1506 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1507 * (since samples are always delivered in pairs). That is, we
1508 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1509 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1510 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1511 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1512 * populating a temporary variable with the sequence (0, 1, 2, 3),
1513 * and then reading from it using vstride=1, width=4, hstride=0.
1514 * These computations hold good for 4x multisampling as well.
1516 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1517 * the first four slots are sample 0 of subspan 0; the next four
1518 * are sample 1 of subspan 0; the third group is sample 0 of
1519 * subspan 1, and finally sample 1 of subspan 1.
1522 inst
= emit(BRW_OPCODE_AND
, t1
,
1523 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1525 inst
->force_writemask_all
= true;
1526 inst
= emit(BRW_OPCODE_SHR
, t1
, t1
, fs_reg(5));
1527 inst
->force_writemask_all
= true;
1528 /* This works for both SIMD8 and SIMD16 */
1529 inst
= emit(MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210)));
1530 inst
->force_writemask_all
= true;
1531 /* This special instruction takes care of setting vstride=1,
1532 * width=4, hstride=0 of t2 during an ADD instruction.
1534 emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1536 /* As per GL_ARB_sample_shading specification:
1537 * "When rendering to a non-multisample buffer, or if multisample
1538 * rasterization is disabled, gl_SampleID will always be zero."
1540 emit(BRW_OPCODE_MOV
, *reg
, fs_reg(0));
1547 fs_visitor::fix_math_operand(fs_reg src
)
1549 /* Can't do hstride == 0 args on gen6 math, so expand it out. We
1550 * might be able to do better by doing execsize = 1 math and then
1551 * expanding that result out, but we would need to be careful with
1554 * The hardware ignores source modifiers (negate and abs) on math
1555 * instructions, so we also move to a temp to set those up.
1557 if (brw
->gen
== 6 && src
.file
!= UNIFORM
&& src
.file
!= IMM
&&
1558 !src
.abs
&& !src
.negate
)
1561 /* Gen7 relaxes most of the above restrictions, but still can't use IMM
1564 if (brw
->gen
>= 7 && src
.file
!= IMM
)
1567 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
1568 expanded
.type
= src
.type
;
1569 emit(BRW_OPCODE_MOV
, expanded
, src
);
1574 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src
)
1577 case SHADER_OPCODE_RCP
:
1578 case SHADER_OPCODE_RSQ
:
1579 case SHADER_OPCODE_SQRT
:
1580 case SHADER_OPCODE_EXP2
:
1581 case SHADER_OPCODE_LOG2
:
1582 case SHADER_OPCODE_SIN
:
1583 case SHADER_OPCODE_COS
:
1586 unreachable("not reached: bad math opcode");
1589 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
1590 * might be able to do better by doing execsize = 1 math and then
1591 * expanding that result out, but we would need to be careful with
1594 * Gen 6 hardware ignores source modifiers (negate and abs) on math
1595 * instructions, so we also move to a temp to set those up.
1597 if (brw
->gen
== 6 || brw
->gen
== 7)
1598 src
= fix_math_operand(src
);
1600 fs_inst
*inst
= emit(opcode
, dst
, src
);
1604 inst
->mlen
= dispatch_width
/ 8;
1611 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
1616 if (brw
->gen
>= 8) {
1617 inst
= emit(opcode
, dst
, src0
, src1
);
1618 } else if (brw
->gen
>= 6) {
1619 src0
= fix_math_operand(src0
);
1620 src1
= fix_math_operand(src1
);
1622 inst
= emit(opcode
, dst
, src0
, src1
);
1624 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
1625 * "Message Payload":
1627 * "Operand0[7]. For the INT DIV functions, this operand is the
1630 * "Operand1[7]. For the INT DIV functions, this operand is the
1633 bool is_int_div
= opcode
!= SHADER_OPCODE_POW
;
1634 fs_reg
&op0
= is_int_div
? src1
: src0
;
1635 fs_reg
&op1
= is_int_div
? src0
: src1
;
1637 emit(MOV(fs_reg(MRF
, base_mrf
+ 1, op1
.type
, dispatch_width
), op1
));
1638 inst
= emit(opcode
, dst
, op0
, reg_null_f
);
1640 inst
->base_mrf
= base_mrf
;
1641 inst
->mlen
= 2 * dispatch_width
/ 8;
1647 fs_visitor::assign_curb_setup()
1649 if (dispatch_width
== 8) {
1650 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1652 assert(stage
== MESA_SHADER_FRAGMENT
);
1653 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1654 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1657 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1659 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1660 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1661 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1662 if (inst
->src
[i
].file
== UNIFORM
) {
1663 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1665 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1666 constant_nr
= push_constant_loc
[uniform_nr
];
1668 /* Section 5.11 of the OpenGL 4.1 spec says:
1669 * "Out-of-bounds reads return undefined values, which include
1670 * values from other variables of the active program or zero."
1671 * Just return the first push constant.
1676 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1680 inst
->src
[i
].file
= HW_REG
;
1681 inst
->src
[i
].fixed_hw_reg
= byte_offset(
1682 retype(brw_reg
, inst
->src
[i
].type
),
1683 inst
->src
[i
].subreg_offset
);
1690 fs_visitor::calculate_urb_setup()
1692 assert(stage
== MESA_SHADER_FRAGMENT
);
1693 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1694 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1696 memset(prog_data
->urb_setup
, -1,
1697 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1700 /* Figure out where each of the incoming setup attributes lands. */
1701 if (brw
->gen
>= 6) {
1702 if (_mesa_bitcount_64(prog
->InputsRead
&
1703 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1704 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1705 * first 16 varying inputs, so we can put them wherever we want.
1706 * Just put them in order.
1708 * This is useful because it means that (a) inputs not used by the
1709 * fragment shader won't take up valuable register space, and (b) we
1710 * won't have to recompile the fragment shader if it gets paired with
1711 * a different vertex (or geometry) shader.
1713 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1714 if (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1715 BITFIELD64_BIT(i
)) {
1716 prog_data
->urb_setup
[i
] = urb_next
++;
1720 /* We have enough input varyings that the SF/SBE pipeline stage can't
1721 * arbitrarily rearrange them to suit our whim; we have to put them
1722 * in an order that matches the output of the previous pipeline stage
1723 * (geometry or vertex shader).
1725 struct brw_vue_map prev_stage_vue_map
;
1726 brw_compute_vue_map(brw
, &prev_stage_vue_map
,
1727 key
->input_slots_valid
);
1728 int first_slot
= 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1729 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1730 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1732 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1733 /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
1736 if (varying
!= BRW_VARYING_SLOT_COUNT
&&
1737 (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1738 BITFIELD64_BIT(varying
))) {
1739 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1742 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1745 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1746 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1747 /* Point size is packed into the header, not as a general attribute */
1748 if (i
== VARYING_SLOT_PSIZ
)
1751 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1752 /* The back color slot is skipped when the front color is
1753 * also written to. In addition, some slots can be
1754 * written in the vertex shader and not read in the
1755 * fragment shader. So the register number must always be
1756 * incremented, mapped or not.
1758 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1759 prog_data
->urb_setup
[i
] = urb_next
;
1765 * It's a FS only attribute, and we did interpolation for this attribute
1766 * in SF thread. So, count it here, too.
1768 * See compile_sf_prog() for more info.
1770 if (prog
->InputsRead
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1771 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1774 prog_data
->num_varying_inputs
= urb_next
;
1778 fs_visitor::assign_urb_setup()
1780 assert(stage
== MESA_SHADER_FRAGMENT
);
1781 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1783 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1785 /* Offset all the urb_setup[] index by the actual position of the
1786 * setup regs, now that the location of the constants has been chosen.
1788 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1789 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1790 assert(inst
->src
[2].file
== HW_REG
);
1791 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
1794 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1795 assert(inst
->src
[0].file
== HW_REG
);
1796 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1800 /* Each attribute is 4 setup channels, each of which is half a reg. */
1801 this->first_non_payload_grf
=
1802 urb_start
+ prog_data
->num_varying_inputs
* 2;
1806 * Split large virtual GRFs into separate components if we can.
1808 * This is mostly duplicated with what brw_fs_vector_splitting does,
1809 * but that's really conservative because it's afraid of doing
1810 * splitting that doesn't result in real progress after the rest of
1811 * the optimization phases, which would cause infinite looping in
1812 * optimization. We can do it once here, safely. This also has the
1813 * opportunity to split interpolated values, or maybe even uniforms,
1814 * which we don't have at the IR level.
1816 * We want to split, because virtual GRFs are what we register
1817 * allocate and spill (due to contiguousness requirements for some
1818 * instructions), and they're what we naturally generate in the
1819 * codegen process, but most virtual GRFs don't actually need to be
1820 * contiguous sets of GRFs. If we split, we'll end up with reduced
1821 * live intervals and better dead code elimination and coalescing.
1824 fs_visitor::split_virtual_grfs()
1826 int num_vars
= this->virtual_grf_count
;
1828 /* Count the total number of registers */
1830 int vgrf_to_reg
[num_vars
];
1831 for (int i
= 0; i
< num_vars
; i
++) {
1832 vgrf_to_reg
[i
] = reg_count
;
1833 reg_count
+= virtual_grf_sizes
[i
];
1836 /* An array of "split points". For each register slot, this indicates
1837 * if this slot can be separated from the previous slot. Every time an
1838 * instruction uses multiple elements of a register (as a source or
1839 * destination), we mark the used slots as inseparable. Then we go
1840 * through and split the registers into the smallest pieces we can.
1842 bool split_points
[reg_count
];
1843 memset(split_points
, 0, sizeof(split_points
));
1845 /* Mark all used registers as fully splittable */
1846 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1847 if (inst
->dst
.file
== GRF
) {
1848 int reg
= vgrf_to_reg
[inst
->dst
.reg
];
1849 for (int j
= 1; j
< this->virtual_grf_sizes
[inst
->dst
.reg
]; j
++)
1850 split_points
[reg
+ j
] = true;
1853 for (int i
= 0; i
< inst
->sources
; i
++) {
1854 if (inst
->src
[i
].file
== GRF
) {
1855 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
];
1856 for (int j
= 1; j
< this->virtual_grf_sizes
[inst
->src
[i
].reg
]; j
++)
1857 split_points
[reg
+ j
] = true;
1863 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].file
== GRF
) {
1864 /* PLN opcodes rely on the delta_xy being contiguous. We only have to
1865 * check this for BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because prior to
1866 * Gen6, that was the only supported interpolation mode, and since Gen6,
1867 * delta_x and delta_y are in fixed hardware registers.
1869 int vgrf
= this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
;
1870 split_points
[vgrf_to_reg
[vgrf
] + 1] = false;
1873 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1874 if (inst
->dst
.file
== GRF
) {
1875 int reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1876 for (int j
= 1; j
< inst
->regs_written
; j
++)
1877 split_points
[reg
+ j
] = false;
1879 for (int i
= 0; i
< inst
->sources
; i
++) {
1880 if (inst
->src
[i
].file
== GRF
) {
1881 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1882 for (int j
= 1; j
< inst
->regs_read(this, i
); j
++)
1883 split_points
[reg
+ j
] = false;
1888 int new_virtual_grf
[reg_count
];
1889 int new_reg_offset
[reg_count
];
1892 for (int i
= 0; i
< num_vars
; i
++) {
1893 /* The first one should always be 0 as a quick sanity check. */
1894 assert(split_points
[reg
] == false);
1897 new_reg_offset
[reg
] = 0;
1902 for (int j
= 1; j
< virtual_grf_sizes
[i
]; j
++) {
1903 /* If this is a split point, reset the offset to 0 and allocate a
1904 * new virtual GRF for the previous offset many registers
1906 if (split_points
[reg
]) {
1907 assert(offset
<= MAX_VGRF_SIZE
);
1908 int grf
= virtual_grf_alloc(offset
);
1909 for (int k
= reg
- offset
; k
< reg
; k
++)
1910 new_virtual_grf
[k
] = grf
;
1913 new_reg_offset
[reg
] = offset
;
1918 /* The last one gets the original register number */
1919 assert(offset
<= MAX_VGRF_SIZE
);
1920 virtual_grf_sizes
[i
] = offset
;
1921 for (int k
= reg
- offset
; k
< reg
; k
++)
1922 new_virtual_grf
[k
] = i
;
1924 assert(reg
== reg_count
);
1926 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1927 if (inst
->dst
.file
== GRF
) {
1928 reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1929 inst
->dst
.reg
= new_virtual_grf
[reg
];
1930 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1931 assert(new_reg_offset
[reg
] < virtual_grf_sizes
[new_virtual_grf
[reg
]]);
1933 for (int i
= 0; i
< inst
->sources
; i
++) {
1934 if (inst
->src
[i
].file
== GRF
) {
1935 reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1936 inst
->src
[i
].reg
= new_virtual_grf
[reg
];
1937 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1938 assert(new_reg_offset
[reg
] < virtual_grf_sizes
[new_virtual_grf
[reg
]]);
1942 invalidate_live_intervals();
1946 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1948 * During code generation, we create tons of temporary variables, many of
1949 * which get immediately killed and are never used again. Yet, in later
1950 * optimization and analysis passes, such as compute_live_intervals, we need
1951 * to loop over all the virtual GRFs. Compacting them can save a lot of
1955 fs_visitor::compact_virtual_grfs()
1957 bool progress
= false;
1958 int remap_table
[this->virtual_grf_count
];
1959 memset(remap_table
, -1, sizeof(remap_table
));
1961 /* Mark which virtual GRFs are used. */
1962 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1963 if (inst
->dst
.file
== GRF
)
1964 remap_table
[inst
->dst
.reg
] = 0;
1966 for (int i
= 0; i
< inst
->sources
; i
++) {
1967 if (inst
->src
[i
].file
== GRF
)
1968 remap_table
[inst
->src
[i
].reg
] = 0;
1972 /* Compact the GRF arrays. */
1974 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
1975 if (remap_table
[i
] == -1) {
1976 /* We just found an unused register. This means that we are
1977 * actually going to compact something.
1981 remap_table
[i
] = new_index
;
1982 virtual_grf_sizes
[new_index
] = virtual_grf_sizes
[i
];
1983 invalidate_live_intervals();
1988 this->virtual_grf_count
= new_index
;
1990 /* Patch all the instructions to use the newly renumbered registers */
1991 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1992 if (inst
->dst
.file
== GRF
)
1993 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
1995 for (int i
= 0; i
< inst
->sources
; i
++) {
1996 if (inst
->src
[i
].file
== GRF
)
1997 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
2001 /* Patch all the references to delta_x/delta_y, since they're used in
2002 * register allocation. If they're unused, switch them to BAD_FILE so
2003 * we don't think some random VGRF is delta_x/delta_y.
2005 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_x
); i
++) {
2006 if (delta_x
[i
].file
== GRF
) {
2007 if (remap_table
[delta_x
[i
].reg
] != -1) {
2008 delta_x
[i
].reg
= remap_table
[delta_x
[i
].reg
];
2010 delta_x
[i
].file
= BAD_FILE
;
2014 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_y
); i
++) {
2015 if (delta_y
[i
].file
== GRF
) {
2016 if (remap_table
[delta_y
[i
].reg
] != -1) {
2017 delta_y
[i
].reg
= remap_table
[delta_y
[i
].reg
];
2019 delta_y
[i
].file
= BAD_FILE
;
2028 * Implements array access of uniforms by inserting a
2029 * PULL_CONSTANT_LOAD instruction.
2031 * Unlike temporary GRF array access (where we don't support it due to
2032 * the difficulty of doing relative addressing on instruction
2033 * destinations), we could potentially do array access of uniforms
2034 * that were loaded in GRF space as push constants. In real-world
2035 * usage we've seen, though, the arrays being used are always larger
2036 * than we could load as push constants, so just always move all
2037 * uniform array access out to a pull constant buffer.
2040 fs_visitor::move_uniform_array_access_to_pull_constants()
2042 if (dispatch_width
!= 8)
2045 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2046 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
2048 /* Walk through and find array access of uniforms. Put a copy of that
2049 * uniform in the pull constant buffer.
2051 * Note that we don't move constant-indexed accesses to arrays. No
2052 * testing has been done of the performance impact of this choice.
2054 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2055 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2056 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
2059 int uniform
= inst
->src
[i
].reg
;
2061 /* If this array isn't already present in the pull constant buffer,
2064 if (pull_constant_loc
[uniform
] == -1) {
2065 const gl_constant_value
**values
= &stage_prog_data
->param
[uniform
];
2067 assert(param_size
[uniform
]);
2069 for (int j
= 0; j
< param_size
[uniform
]; j
++) {
2070 pull_constant_loc
[uniform
+ j
] = stage_prog_data
->nr_pull_params
;
2072 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
2081 * Assign UNIFORM file registers to either push constants or pull constants.
2083 * We allow a fragment shader to have more than the specified minimum
2084 * maximum number of fragment shader uniform components (64). If
2085 * there are too many of these, they'd fill up all of register space.
2086 * So, this will push some of them out to the pull constant buffer and
2087 * update the program to load them.
2090 fs_visitor::assign_constant_locations()
2092 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
2093 if (dispatch_width
!= 8)
2096 /* Find which UNIFORM registers are still in use. */
2097 bool is_live
[uniforms
];
2098 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2102 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2103 for (int i
= 0; i
< inst
->sources
; i
++) {
2104 if (inst
->src
[i
].file
!= UNIFORM
)
2107 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
2108 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
2109 is_live
[constant_nr
] = true;
2113 /* Only allow 16 registers (128 uniform components) as push constants.
2115 * Just demote the end of the list. We could probably do better
2116 * here, demoting things that are rarely used in the program first.
2118 * If changing this value, note the limitation about total_regs in
2121 unsigned int max_push_components
= 16 * 8;
2122 unsigned int num_push_constants
= 0;
2124 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2126 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2127 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
2128 /* This UNIFORM register is either dead, or has already been demoted
2129 * to a pull const. Mark it as no longer living in the param[] array.
2131 push_constant_loc
[i
] = -1;
2135 if (num_push_constants
< max_push_components
) {
2136 /* Retain as a push constant. Record the location in the params[]
2139 push_constant_loc
[i
] = num_push_constants
++;
2141 /* Demote to a pull constant. */
2142 push_constant_loc
[i
] = -1;
2144 int pull_index
= stage_prog_data
->nr_pull_params
++;
2145 stage_prog_data
->pull_param
[pull_index
] = stage_prog_data
->param
[i
];
2146 pull_constant_loc
[i
] = pull_index
;
2150 stage_prog_data
->nr_params
= num_push_constants
;
2152 /* Up until now, the param[] array has been indexed by reg + reg_offset
2153 * of UNIFORM registers. Condense it to only contain the uniforms we
2154 * chose to upload as push constants.
2156 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2157 int remapped
= push_constant_loc
[i
];
2162 assert(remapped
<= (int)i
);
2163 stage_prog_data
->param
[remapped
] = stage_prog_data
->param
[i
];
2168 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2169 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2172 fs_visitor::demote_pull_constants()
2174 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2175 for (int i
= 0; i
< inst
->sources
; i
++) {
2176 if (inst
->src
[i
].file
!= UNIFORM
)
2179 int pull_index
= pull_constant_loc
[inst
->src
[i
].reg
+
2180 inst
->src
[i
].reg_offset
];
2181 if (pull_index
== -1)
2184 /* Set up the annotation tracking for new generated instructions. */
2186 current_annotation
= inst
->annotation
;
2188 fs_reg
surf_index(stage_prog_data
->binding_table
.pull_constants_start
);
2189 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
2191 /* Generate a pull load into dst. */
2192 if (inst
->src
[i
].reladdr
) {
2193 exec_list list
= VARYING_PULL_CONSTANT_LOAD(dst
,
2195 *inst
->src
[i
].reladdr
,
2197 inst
->insert_before(block
, &list
);
2198 inst
->src
[i
].reladdr
= NULL
;
2200 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
2202 new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, 8,
2203 dst
, surf_index
, offset
);
2204 inst
->insert_before(block
, pull
);
2205 inst
->src
[i
].set_smear(pull_index
& 3);
2208 /* Rewrite the instruction to use the temporary VGRF. */
2209 inst
->src
[i
].file
= GRF
;
2210 inst
->src
[i
].reg
= dst
.reg
;
2211 inst
->src
[i
].reg_offset
= 0;
2212 inst
->src
[i
].width
= dispatch_width
;
2215 invalidate_live_intervals();
2219 fs_visitor::opt_algebraic()
2221 bool progress
= false;
2223 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2224 switch (inst
->opcode
) {
2225 case BRW_OPCODE_MUL
:
2226 if (inst
->src
[1].file
!= IMM
)
2230 if (inst
->src
[1].is_one()) {
2231 inst
->opcode
= BRW_OPCODE_MOV
;
2232 inst
->src
[1] = reg_undef
;
2238 if (inst
->src
[1].is_zero()) {
2239 inst
->opcode
= BRW_OPCODE_MOV
;
2240 inst
->src
[0] = inst
->src
[1];
2241 inst
->src
[1] = reg_undef
;
2247 case BRW_OPCODE_ADD
:
2248 if (inst
->src
[1].file
!= IMM
)
2252 if (inst
->src
[1].is_zero()) {
2253 inst
->opcode
= BRW_OPCODE_MOV
;
2254 inst
->src
[1] = reg_undef
;
2260 if (inst
->src
[0].equals(inst
->src
[1])) {
2261 inst
->opcode
= BRW_OPCODE_MOV
;
2262 inst
->src
[1] = reg_undef
;
2267 case BRW_OPCODE_LRP
:
2268 if (inst
->src
[1].equals(inst
->src
[2])) {
2269 inst
->opcode
= BRW_OPCODE_MOV
;
2270 inst
->src
[0] = inst
->src
[1];
2271 inst
->src
[1] = reg_undef
;
2272 inst
->src
[2] = reg_undef
;
2277 case BRW_OPCODE_SEL
:
2278 if (inst
->src
[0].equals(inst
->src
[1])) {
2279 inst
->opcode
= BRW_OPCODE_MOV
;
2280 inst
->src
[1] = reg_undef
;
2281 inst
->predicate
= BRW_PREDICATE_NONE
;
2282 inst
->predicate_inverse
= false;
2284 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2285 switch (inst
->conditional_mod
) {
2286 case BRW_CONDITIONAL_LE
:
2287 case BRW_CONDITIONAL_L
:
2288 switch (inst
->src
[1].type
) {
2289 case BRW_REGISTER_TYPE_F
:
2290 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
>= 1.0f
) {
2291 inst
->opcode
= BRW_OPCODE_MOV
;
2292 inst
->src
[1] = reg_undef
;
2300 case BRW_CONDITIONAL_GE
:
2301 case BRW_CONDITIONAL_G
:
2302 switch (inst
->src
[1].type
) {
2303 case BRW_REGISTER_TYPE_F
:
2304 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
<= 0.0f
) {
2305 inst
->opcode
= BRW_OPCODE_MOV
;
2306 inst
->src
[1] = reg_undef
;
2307 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2319 case SHADER_OPCODE_RCP
: {
2320 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2321 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2322 if (inst
->src
[0].equals(prev
->dst
)) {
2323 inst
->opcode
= SHADER_OPCODE_RSQ
;
2324 inst
->src
[0] = prev
->src
[0];
2339 fs_visitor::opt_register_renaming()
2341 bool progress
= false;
2344 int remap
[virtual_grf_count
];
2345 memset(remap
, -1, sizeof(int) * virtual_grf_count
);
2347 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2348 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2350 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2351 inst
->opcode
== BRW_OPCODE_WHILE
) {
2355 /* Rewrite instruction sources. */
2356 for (int i
= 0; i
< inst
->sources
; i
++) {
2357 if (inst
->src
[i
].file
== GRF
&&
2358 remap
[inst
->src
[i
].reg
] != -1 &&
2359 remap
[inst
->src
[i
].reg
] != inst
->src
[i
].reg
) {
2360 inst
->src
[i
].reg
= remap
[inst
->src
[i
].reg
];
2365 const int dst
= inst
->dst
.reg
;
2368 inst
->dst
.file
== GRF
&&
2369 virtual_grf_sizes
[inst
->dst
.reg
] == inst
->dst
.width
/ 8 &&
2370 !inst
->is_partial_write()) {
2371 if (remap
[dst
] == -1) {
2374 remap
[dst
] = virtual_grf_alloc(inst
->dst
.width
/ 8);
2375 inst
->dst
.reg
= remap
[dst
];
2378 } else if (inst
->dst
.file
== GRF
&&
2380 remap
[dst
] != dst
) {
2381 inst
->dst
.reg
= remap
[dst
];
2387 invalidate_live_intervals();
2389 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_x
); i
++) {
2390 if (delta_x
[i
].file
== GRF
&& remap
[delta_x
[i
].reg
] != -1) {
2391 delta_x
[i
].reg
= remap
[delta_x
[i
].reg
];
2394 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_y
); i
++) {
2395 if (delta_y
[i
].file
== GRF
&& remap
[delta_y
[i
].reg
] != -1) {
2396 delta_y
[i
].reg
= remap
[delta_y
[i
].reg
];
2405 fs_visitor::compute_to_mrf()
2407 bool progress
= false;
2410 /* No MRFs on Gen >= 7. */
2414 calculate_live_intervals();
2416 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2420 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2421 inst
->is_partial_write() ||
2422 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2423 inst
->dst
.type
!= inst
->src
[0].type
||
2424 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2425 !inst
->src
[0].is_contiguous() ||
2426 inst
->src
[0].subreg_offset
)
2429 /* Work out which hardware MRF registers are written by this
2432 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2434 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2435 mrf_high
= mrf_low
+ 4;
2436 } else if (inst
->exec_size
== 16) {
2437 mrf_high
= mrf_low
+ 1;
2442 /* Can't compute-to-MRF this GRF if someone else was going to
2445 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2448 /* Found a move of a GRF to a MRF. Let's see if we can go
2449 * rewrite the thing that made this GRF to write into the MRF.
2451 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2452 if (scan_inst
->dst
.file
== GRF
&&
2453 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2454 /* Found the last thing to write our reg we want to turn
2455 * into a compute-to-MRF.
2458 /* If this one instruction didn't populate all the
2459 * channels, bail. We might be able to rewrite everything
2460 * that writes that reg, but it would require smarter
2461 * tracking to delay the rewriting until complete success.
2463 if (scan_inst
->is_partial_write())
2466 /* Things returning more than one register would need us to
2467 * understand coalescing out more than one MOV at a time.
2469 if (scan_inst
->regs_written
> scan_inst
->dst
.width
/ 8)
2472 /* SEND instructions can't have MRF as a destination. */
2473 if (scan_inst
->mlen
)
2476 if (brw
->gen
== 6) {
2477 /* gen6 math instructions must have the destination be
2478 * GRF, so no compute-to-MRF for them.
2480 if (scan_inst
->is_math()) {
2485 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2486 /* Found the creator of our MRF's source value. */
2487 scan_inst
->dst
.file
= MRF
;
2488 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2489 scan_inst
->saturate
|= inst
->saturate
;
2490 inst
->remove(block
);
2496 /* We don't handle control flow here. Most computation of
2497 * values that end up in MRFs are shortly before the MRF
2500 if (block
->start() == scan_inst
)
2503 /* You can't read from an MRF, so if someone else reads our
2504 * MRF's source GRF that we wanted to rewrite, that stops us.
2506 bool interfered
= false;
2507 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2508 if (scan_inst
->src
[i
].file
== GRF
&&
2509 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2510 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2517 if (scan_inst
->dst
.file
== MRF
) {
2518 /* If somebody else writes our MRF here, we can't
2519 * compute-to-MRF before that.
2521 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2524 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2525 scan_mrf_high
= scan_mrf_low
+ 4;
2526 } else if (scan_inst
->exec_size
== 16) {
2527 scan_mrf_high
= scan_mrf_low
+ 1;
2529 scan_mrf_high
= scan_mrf_low
;
2532 if (mrf_low
== scan_mrf_low
||
2533 mrf_low
== scan_mrf_high
||
2534 mrf_high
== scan_mrf_low
||
2535 mrf_high
== scan_mrf_high
) {
2540 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2541 /* Found a SEND instruction, which means that there are
2542 * live values in MRFs from base_mrf to base_mrf +
2543 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2546 if (mrf_low
>= scan_inst
->base_mrf
&&
2547 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2550 if (mrf_high
>= scan_inst
->base_mrf
&&
2551 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2559 invalidate_live_intervals();
2565 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2566 * instructions to FS_OPCODE_REP_FB_WRITE.
2569 fs_visitor::emit_repclear_shader()
2571 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2573 int color_mrf
= base_mrf
+ 2;
2575 fs_inst
*mov
= emit(MOV(vec4(brw_message_reg(color_mrf
)),
2576 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
)));
2577 mov
->force_writemask_all
= true;
2580 if (key
->nr_color_regions
== 1) {
2581 write
= emit(FS_OPCODE_REP_FB_WRITE
);
2582 write
->saturate
= key
->clamp_fragment_color
;
2583 write
->base_mrf
= color_mrf
;
2585 write
->header_present
= false;
2588 assume(key
->nr_color_regions
> 0);
2589 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2590 write
= emit(FS_OPCODE_REP_FB_WRITE
);
2591 write
->saturate
= key
->clamp_fragment_color
;
2592 write
->base_mrf
= base_mrf
;
2594 write
->header_present
= true;
2602 assign_constant_locations();
2603 assign_curb_setup();
2605 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2606 assert(mov
->src
[0].file
== HW_REG
);
2607 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].fixed_hw_reg
.nr
, 0);
2611 * Walks through basic blocks, looking for repeated MRF writes and
2612 * removing the later ones.
2615 fs_visitor::remove_duplicate_mrf_writes()
2617 fs_inst
*last_mrf_move
[16];
2618 bool progress
= false;
2620 /* Need to update the MRF tracking for compressed instructions. */
2621 if (dispatch_width
== 16)
2624 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2626 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2627 if (inst
->is_control_flow()) {
2628 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2631 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2632 inst
->dst
.file
== MRF
) {
2633 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2634 if (prev_inst
&& inst
->equals(prev_inst
)) {
2635 inst
->remove(block
);
2641 /* Clear out the last-write records for MRFs that were overwritten. */
2642 if (inst
->dst
.file
== MRF
) {
2643 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2646 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2647 /* Found a SEND instruction, which will include two or fewer
2648 * implied MRF writes. We could do better here.
2650 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2651 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2655 /* Clear out any MRF move records whose sources got overwritten. */
2656 if (inst
->dst
.file
== GRF
) {
2657 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
2658 if (last_mrf_move
[i
] &&
2659 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2660 last_mrf_move
[i
] = NULL
;
2665 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2666 inst
->dst
.file
== MRF
&&
2667 inst
->src
[0].file
== GRF
&&
2668 !inst
->is_partial_write()) {
2669 last_mrf_move
[inst
->dst
.reg
] = inst
;
2674 invalidate_live_intervals();
2680 clear_deps_for_inst_src(fs_inst
*inst
, int dispatch_width
, bool *deps
,
2681 int first_grf
, int grf_len
)
2683 /* Clear the flag for registers that actually got read (as expected). */
2684 for (int i
= 0; i
< inst
->sources
; i
++) {
2686 if (inst
->src
[i
].file
== GRF
) {
2687 grf
= inst
->src
[i
].reg
;
2688 } else if (inst
->src
[i
].file
== HW_REG
&&
2689 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
2690 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
2695 if (grf
>= first_grf
&&
2696 grf
< first_grf
+ grf_len
) {
2697 deps
[grf
- first_grf
] = false;
2698 if (inst
->exec_size
== 16)
2699 deps
[grf
- first_grf
+ 1] = false;
2705 * Implements this workaround for the original 965:
2707 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2708 * check for post destination dependencies on this instruction, software
2709 * must ensure that there is no destination hazard for the case of ‘write
2710 * followed by a posted write’ shown in the following example.
2713 * 2. send r3.xy <rest of send instruction>
2716 * Due to no post-destination dependency check on the ‘send’, the above
2717 * code sequence could have two instructions (1 and 2) in flight at the
2718 * same time that both consider ‘r3’ as the target of their final writes.
2721 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2724 int write_len
= inst
->regs_written
;
2725 int first_write_grf
= inst
->dst
.reg
;
2726 bool needs_dep
[BRW_MAX_MRF
];
2727 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2729 memset(needs_dep
, false, sizeof(needs_dep
));
2730 memset(needs_dep
, true, write_len
);
2732 clear_deps_for_inst_src(inst
, dispatch_width
,
2733 needs_dep
, first_write_grf
, write_len
);
2735 /* Walk backwards looking for writes to registers we're writing which
2736 * aren't read since being written. If we hit the start of the program,
2737 * we assume that there are no outstanding dependencies on entry to the
2740 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2741 /* If we hit control flow, assume that there *are* outstanding
2742 * dependencies, and force their cleanup before our instruction.
2744 if (block
->start() == scan_inst
) {
2745 for (int i
= 0; i
< write_len
; i
++) {
2747 inst
->insert_before(block
, DEP_RESOLVE_MOV(first_write_grf
+ i
));
2753 /* We insert our reads as late as possible on the assumption that any
2754 * instruction but a MOV that might have left us an outstanding
2755 * dependency has more latency than a MOV.
2757 if (scan_inst
->dst
.file
== GRF
) {
2758 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2759 int reg
= scan_inst
->dst
.reg
+ i
;
2761 if (reg
>= first_write_grf
&&
2762 reg
< first_write_grf
+ write_len
&&
2763 needs_dep
[reg
- first_write_grf
]) {
2764 inst
->insert_before(block
, DEP_RESOLVE_MOV(reg
));
2765 needs_dep
[reg
- first_write_grf
] = false;
2766 if (scan_inst
->exec_size
== 16)
2767 needs_dep
[reg
- first_write_grf
+ 1] = false;
2772 /* Clear the flag for registers that actually got read (as expected). */
2773 clear_deps_for_inst_src(scan_inst
, dispatch_width
,
2774 needs_dep
, first_write_grf
, write_len
);
2776 /* Continue the loop only if we haven't resolved all the dependencies */
2778 for (i
= 0; i
< write_len
; i
++) {
2788 * Implements this workaround for the original 965:
2790 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2791 * used as a destination register until after it has been sourced by an
2792 * instruction with a different destination register.
2795 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
2797 int write_len
= inst
->regs_written
;
2798 int first_write_grf
= inst
->dst
.reg
;
2799 bool needs_dep
[BRW_MAX_MRF
];
2800 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2802 memset(needs_dep
, false, sizeof(needs_dep
));
2803 memset(needs_dep
, true, write_len
);
2804 /* Walk forwards looking for writes to registers we're writing which aren't
2805 * read before being written.
2807 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2808 /* If we hit control flow, force resolve all remaining dependencies. */
2809 if (block
->end() == scan_inst
) {
2810 for (int i
= 0; i
< write_len
; i
++) {
2812 scan_inst
->insert_before(block
,
2813 DEP_RESOLVE_MOV(first_write_grf
+ i
));
2818 /* Clear the flag for registers that actually got read (as expected). */
2819 clear_deps_for_inst_src(scan_inst
, dispatch_width
,
2820 needs_dep
, first_write_grf
, write_len
);
2822 /* We insert our reads as late as possible since they're reading the
2823 * result of a SEND, which has massive latency.
2825 if (scan_inst
->dst
.file
== GRF
&&
2826 scan_inst
->dst
.reg
>= first_write_grf
&&
2827 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
2828 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
2829 scan_inst
->insert_before(block
, DEP_RESOLVE_MOV(scan_inst
->dst
.reg
));
2830 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
2833 /* Continue the loop only if we haven't resolved all the dependencies */
2835 for (i
= 0; i
< write_len
; i
++) {
2843 /* If we hit the end of the program, resolve all remaining dependencies out
2846 fs_inst
*last_inst
= (fs_inst
*)this->instructions
.get_tail();
2847 assert(last_inst
->eot
);
2848 for (int i
= 0; i
< write_len
; i
++) {
2850 last_inst
->insert_before(block
, DEP_RESOLVE_MOV(first_write_grf
+ i
));
2855 fs_visitor::insert_gen4_send_dependency_workarounds()
2857 if (brw
->gen
!= 4 || brw
->is_g4x
)
2860 bool progress
= false;
2862 /* Note that we're done with register allocation, so GRF fs_regs always
2863 * have a .reg_offset of 0.
2866 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2867 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
2868 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
2869 insert_gen4_post_send_dependency_workarounds(block
, inst
);
2875 invalidate_live_intervals();
2879 * Turns the generic expression-style uniform pull constant load instruction
2880 * into a hardware-specific series of instructions for loading a pull
2883 * The expression style allows the CSE pass before this to optimize out
2884 * repeated loads from the same offset, and gives the pre-register-allocation
2885 * scheduling full flexibility, while the conversion to native instructions
2886 * allows the post-register-allocation scheduler the best information
2889 * Note that execution masking for setting up pull constant loads is special:
2890 * the channels that need to be written are unrelated to the current execution
2891 * mask, since a later instruction will use one of the result channels as a
2892 * source operand for all 8 or 16 of its channels.
2895 fs_visitor::lower_uniform_pull_constant_loads()
2897 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2898 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
2901 if (brw
->gen
>= 7) {
2902 /* The offset arg before was a vec4-aligned byte offset. We need to
2903 * turn it into a dword offset.
2905 fs_reg const_offset_reg
= inst
->src
[1];
2906 assert(const_offset_reg
.file
== IMM
&&
2907 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
2908 const_offset_reg
.fixed_hw_reg
.dw1
.ud
/= 4;
2909 fs_reg payload
= fs_reg(this, glsl_type::uint_type
);
2911 /* This is actually going to be a MOV, but since only the first dword
2912 * is accessed, we have a special opcode to do just that one. Note
2913 * that this needs to be an operation that will be considered a def
2914 * by live variable analysis, or register allocation will explode.
2916 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
2917 8, payload
, const_offset_reg
);
2918 setup
->force_writemask_all
= true;
2920 setup
->ir
= inst
->ir
;
2921 setup
->annotation
= inst
->annotation
;
2922 inst
->insert_before(block
, setup
);
2924 /* Similarly, this will only populate the first 4 channels of the
2925 * result register (since we only use smear values from 0-3), but we
2926 * don't tell the optimizer.
2928 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
2929 inst
->src
[1] = payload
;
2931 invalidate_live_intervals();
2933 /* Before register allocation, we didn't tell the scheduler about the
2934 * MRF we use. We know it's safe to use this MRF because nothing
2935 * else does except for register spill/unspill, which generates and
2936 * uses its MRF within a single IR instruction.
2938 inst
->base_mrf
= 14;
2945 fs_visitor::lower_load_payload()
2947 bool progress
= false;
2949 int vgrf_to_reg
[virtual_grf_count
];
2950 int reg_count
= 16; /* Leave room for MRF */
2951 for (int i
= 0; i
< virtual_grf_count
; ++i
) {
2952 vgrf_to_reg
[i
] = reg_count
;
2953 reg_count
+= virtual_grf_sizes
[i
];
2957 bool written
:1; /* Whether this register has ever been written */
2958 bool force_writemask_all
:1;
2959 bool force_sechalf
:1;
2960 } metadata
[reg_count
];
2961 memset(metadata
, 0, sizeof(metadata
));
2963 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2965 if (inst
->dst
.file
== GRF
) {
2966 dst_reg
= vgrf_to_reg
[inst
->dst
.reg
];
2969 dst_reg
= inst
->dst
.reg
;
2972 if (inst
->dst
.file
== MRF
|| inst
->dst
.file
== GRF
) {
2973 bool force_sechalf
= inst
->force_sechalf
;
2974 bool toggle_sechalf
= inst
->dst
.width
== 16 &&
2975 type_sz(inst
->dst
.type
) == 4;
2976 for (int i
= 0; i
< inst
->regs_written
; ++i
) {
2977 metadata
[dst_reg
+ i
].written
= true;
2978 metadata
[dst_reg
+ i
].force_sechalf
= force_sechalf
;
2979 metadata
[dst_reg
+ i
].force_writemask_all
= inst
->force_writemask_all
;
2980 force_sechalf
= (toggle_sechalf
!= force_sechalf
);
2984 if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
) {
2985 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== GRF
);
2986 fs_reg dst
= inst
->dst
;
2988 for (int i
= 0; i
< inst
->sources
; i
++) {
2989 dst
.width
= inst
->src
[i
].effective_width
;
2990 dst
.type
= inst
->src
[i
].type
;
2992 if (inst
->src
[i
].file
== BAD_FILE
) {
2993 /* Do nothing but otherwise increment as normal */
2994 } else if (dst
.file
== MRF
&&
2997 i
+ 4 < inst
->sources
&&
2998 inst
->src
[i
+ 4].equals(horiz_offset(inst
->src
[i
], 8))) {
2999 fs_reg compr4_dst
= dst
;
3000 compr4_dst
.reg
+= BRW_MRF_COMPR4
;
3001 compr4_dst
.width
= 16;
3002 fs_reg compr4_src
= inst
->src
[i
];
3003 compr4_src
.width
= 16;
3004 fs_inst
*mov
= MOV(compr4_dst
, compr4_src
);
3005 mov
->force_writemask_all
= true;
3006 inst
->insert_before(block
, mov
);
3007 /* Mark i+4 as BAD_FILE so we don't emit a MOV for it */
3008 inst
->src
[i
+ 4].file
= BAD_FILE
;
3010 fs_inst
*mov
= MOV(dst
, inst
->src
[i
]);
3011 if (inst
->src
[i
].file
== GRF
) {
3012 int src_reg
= vgrf_to_reg
[inst
->src
[i
].reg
] +
3013 inst
->src
[i
].reg_offset
;
3014 mov
->force_sechalf
= metadata
[src_reg
].force_sechalf
;
3015 mov
->force_writemask_all
= metadata
[src_reg
].force_writemask_all
;
3016 metadata
[dst_reg
] = metadata
[src_reg
];
3017 if (dst
.width
* type_sz(dst
.type
) > 32) {
3018 assert((!metadata
[src_reg
].written
||
3019 !metadata
[src_reg
].force_sechalf
) &&
3020 (!metadata
[src_reg
+ 1].written
||
3021 metadata
[src_reg
+ 1].force_sechalf
));
3022 metadata
[dst_reg
+ 1] = metadata
[src_reg
+ 1];
3025 metadata
[dst_reg
].force_writemask_all
= false;
3026 metadata
[dst_reg
].force_sechalf
= false;
3027 if (dst
.width
== 16) {
3028 metadata
[dst_reg
+ 1].force_writemask_all
= false;
3029 metadata
[dst_reg
+ 1].force_sechalf
= true;
3032 inst
->insert_before(block
, mov
);
3035 dst
= offset(dst
, 1);
3038 inst
->remove(block
);
3044 invalidate_live_intervals();
3050 fs_visitor::dump_instructions()
3052 dump_instructions(NULL
);
3056 fs_visitor::dump_instructions(const char *name
)
3058 calculate_register_pressure();
3059 FILE *file
= stderr
;
3060 if (name
&& geteuid() != 0) {
3061 file
= fopen(name
, "w");
3066 int ip
= 0, max_pressure
= 0;
3067 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
3068 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
3069 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
3070 dump_instruction(inst
, file
);
3073 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
3075 if (file
!= stderr
) {
3081 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
3083 dump_instruction(be_inst
, stderr
);
3087 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
3089 fs_inst
*inst
= (fs_inst
*)be_inst
;
3091 if (inst
->predicate
) {
3092 fprintf(file
, "(%cf0.%d) ",
3093 inst
->predicate_inverse
? '-' : '+',
3097 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
3099 fprintf(file
, ".sat");
3100 if (inst
->conditional_mod
) {
3101 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
3102 if (!inst
->predicate
&&
3103 (brw
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
3104 inst
->opcode
!= BRW_OPCODE_IF
&&
3105 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
3106 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
3109 fprintf(file
, "(%d) ", inst
->exec_size
);
3112 switch (inst
->dst
.file
) {
3114 fprintf(file
, "vgrf%d", inst
->dst
.reg
);
3115 if (inst
->dst
.width
!= dispatch_width
)
3116 fprintf(file
, "@%d", inst
->dst
.width
);
3117 if (virtual_grf_sizes
[inst
->dst
.reg
] != inst
->dst
.width
/ 8 ||
3118 inst
->dst
.subreg_offset
)
3119 fprintf(file
, "+%d.%d",
3120 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
3123 fprintf(file
, "m%d", inst
->dst
.reg
);
3126 fprintf(file
, "(null)");
3129 fprintf(file
, "***u%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
3132 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
3133 switch (inst
->dst
.fixed_hw_reg
.nr
) {
3135 fprintf(file
, "null");
3137 case BRW_ARF_ADDRESS
:
3138 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
3140 case BRW_ARF_ACCUMULATOR
:
3141 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
3144 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
3145 inst
->dst
.fixed_hw_reg
.subnr
);
3148 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
3149 inst
->dst
.fixed_hw_reg
.subnr
);
3153 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
3155 if (inst
->dst
.fixed_hw_reg
.subnr
)
3156 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
3159 fprintf(file
, "???");
3162 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
3164 for (int i
= 0; i
< inst
->sources
; i
++) {
3165 if (inst
->src
[i
].negate
)
3167 if (inst
->src
[i
].abs
)
3169 switch (inst
->src
[i
].file
) {
3171 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
3172 if (inst
->src
[i
].width
!= dispatch_width
)
3173 fprintf(file
, "@%d", inst
->src
[i
].width
);
3174 if (virtual_grf_sizes
[inst
->src
[i
].reg
] != inst
->src
[i
].width
/ 8 ||
3175 inst
->src
[i
].subreg_offset
)
3176 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
3177 inst
->src
[i
].subreg_offset
);
3180 fprintf(file
, "***m%d***", inst
->src
[i
].reg
);
3183 fprintf(file
, "u%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
3184 if (inst
->src
[i
].reladdr
) {
3185 fprintf(file
, "+reladdr");
3186 } else if (inst
->src
[i
].subreg_offset
) {
3187 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
3188 inst
->src
[i
].subreg_offset
);
3192 fprintf(file
, "(null)");
3195 switch (inst
->src
[i
].type
) {
3196 case BRW_REGISTER_TYPE_F
:
3197 fprintf(file
, "%ff", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
3199 case BRW_REGISTER_TYPE_D
:
3200 fprintf(file
, "%dd", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
3202 case BRW_REGISTER_TYPE_UD
:
3203 fprintf(file
, "%uu", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
3205 case BRW_REGISTER_TYPE_VF
:
3206 fprintf(stderr
, "[%-gF, %-gF, %-gF, %-gF]",
3207 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
3208 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
3209 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
3210 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
3213 fprintf(file
, "???");
3218 if (inst
->src
[i
].fixed_hw_reg
.negate
)
3220 if (inst
->src
[i
].fixed_hw_reg
.abs
)
3222 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
3223 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
3225 fprintf(file
, "null");
3227 case BRW_ARF_ADDRESS
:
3228 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3230 case BRW_ARF_ACCUMULATOR
:
3231 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3234 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
3235 inst
->src
[i
].fixed_hw_reg
.subnr
);
3238 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
3239 inst
->src
[i
].fixed_hw_reg
.subnr
);
3243 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
3245 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
3246 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3247 if (inst
->src
[i
].fixed_hw_reg
.abs
)
3251 fprintf(file
, "???");
3254 if (inst
->src
[i
].abs
)
3257 if (inst
->src
[i
].file
!= IMM
) {
3258 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
3261 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
3262 fprintf(file
, ", ");
3267 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
3268 if (inst
->force_sechalf
)
3269 fprintf(file
, "2ndhalf ");
3271 fprintf(file
, "1sthalf ");
3274 fprintf(file
, "\n");
3278 * Possibly returns an instruction that set up @param reg.
3280 * Sometimes we want to take the result of some expression/variable
3281 * dereference tree and rewrite the instruction generating the result
3282 * of the tree. When processing the tree, we know that the
3283 * instructions generated are all writing temporaries that are dead
3284 * outside of this tree. So, if we have some instructions that write
3285 * a temporary, we're free to point that temp write somewhere else.
3287 * Note that this doesn't guarantee that the instruction generated
3288 * only reg -- it might be the size=4 destination of a texture instruction.
3291 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
3296 end
->is_partial_write() ||
3298 !reg
.equals(end
->dst
)) {
3306 fs_visitor::setup_payload_gen6()
3309 (prog
->InputsRead
& (1 << VARYING_SLOT_POS
)) != 0;
3310 unsigned barycentric_interp_modes
=
3311 (stage
== MESA_SHADER_FRAGMENT
) ?
3312 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
3314 assert(brw
->gen
>= 6);
3316 /* R0-1: masks, pixel X/Y coordinates. */
3317 payload
.num_regs
= 2;
3318 /* R2: only for 32-pixel dispatch.*/
3320 /* R3-26: barycentric interpolation coordinates. These appear in the
3321 * same order that they appear in the brw_wm_barycentric_interp_mode
3322 * enum. Each set of coordinates occupies 2 registers if dispatch width
3323 * == 8 and 4 registers if dispatch width == 16. Coordinates only
3324 * appear if they were enabled using the "Barycentric Interpolation
3325 * Mode" bits in WM_STATE.
3327 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
3328 if (barycentric_interp_modes
& (1 << i
)) {
3329 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
3330 payload
.num_regs
+= 2;
3331 if (dispatch_width
== 16) {
3332 payload
.num_regs
+= 2;
3337 /* R27: interpolated depth if uses source depth */
3339 payload
.source_depth_reg
= payload
.num_regs
;
3341 if (dispatch_width
== 16) {
3342 /* R28: interpolated depth if not SIMD8. */
3346 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
3348 payload
.source_w_reg
= payload
.num_regs
;
3350 if (dispatch_width
== 16) {
3351 /* R30: interpolated W if not SIMD8. */
3356 if (stage
== MESA_SHADER_FRAGMENT
) {
3357 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3358 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3359 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
3360 /* R31: MSAA position offsets. */
3361 if (prog_data
->uses_pos_offset
) {
3362 payload
.sample_pos_reg
= payload
.num_regs
;
3367 /* R32: MSAA input coverage mask */
3368 if (prog
->SystemValuesRead
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
3369 assert(brw
->gen
>= 7);
3370 payload
.sample_mask_in_reg
= payload
.num_regs
;
3372 if (dispatch_width
== 16) {
3373 /* R33: input coverage mask if not SIMD8. */
3378 /* R34-: bary for 32-pixel. */
3379 /* R58-59: interp W for 32-pixel. */
3381 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
3382 source_depth_to_render_target
= true;
3387 fs_visitor::assign_binding_table_offsets()
3389 assert(stage
== MESA_SHADER_FRAGMENT
);
3390 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3391 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3392 uint32_t next_binding_table_offset
= 0;
3394 /* If there are no color regions, we still perform an FB write to a null
3395 * renderbuffer, which we place at surface index 0.
3397 prog_data
->binding_table
.render_target_start
= next_binding_table_offset
;
3398 next_binding_table_offset
+= MAX2(key
->nr_color_regions
, 1);
3400 assign_common_binding_table_offsets(next_binding_table_offset
);
3404 fs_visitor::calculate_register_pressure()
3406 invalidate_live_intervals();
3407 calculate_live_intervals();
3409 unsigned num_instructions
= 0;
3410 foreach_block(block
, cfg
)
3411 num_instructions
+= block
->instructions
.length();
3413 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
3415 for (int reg
= 0; reg
< virtual_grf_count
; reg
++) {
3416 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
3417 regs_live_at_ip
[ip
] += virtual_grf_sizes
[reg
];
3422 fs_visitor::optimize()
3426 split_virtual_grfs();
3428 move_uniform_array_access_to_pull_constants();
3429 assign_constant_locations();
3430 demote_pull_constants();
3432 #define OPT(pass, args...) do { \
3434 bool this_progress = pass(args); \
3436 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
3437 char filename[64]; \
3438 snprintf(filename, 64, "fs%d-%04d-%02d-%02d-" #pass, \
3439 dispatch_width, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
3441 backend_visitor::dump_instructions(filename); \
3444 progress = progress || this_progress; \
3447 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
3449 snprintf(filename
, 64, "fs%d-%04d-00-start",
3450 dispatch_width
, shader_prog
? shader_prog
->Name
: 0);
3452 backend_visitor::dump_instructions(filename
);
3462 OPT(remove_duplicate_mrf_writes
);
3466 OPT(opt_copy_propagate
);
3467 OPT(opt_peephole_predicated_break
);
3468 OPT(dead_code_eliminate
);
3469 OPT(opt_peephole_sel
);
3470 OPT(dead_control_flow_eliminate
, this);
3471 OPT(opt_register_renaming
);
3472 OPT(opt_saturate_propagation
);
3473 OPT(register_coalesce
);
3474 OPT(compute_to_mrf
);
3476 OPT(compact_virtual_grfs
);
3479 if (lower_load_payload()) {
3480 split_virtual_grfs();
3481 register_coalesce();
3483 dead_code_eliminate();
3486 lower_uniform_pull_constant_loads();
3490 fs_visitor::allocate_registers()
3492 bool allocated_without_spills
;
3494 static enum instruction_scheduler_mode pre_modes
[] = {
3496 SCHEDULE_PRE_NON_LIFO
,
3500 /* Try each scheduling heuristic to see if it can successfully register
3501 * allocate without spilling. They should be ordered by decreasing
3502 * performance but increasing likelihood of allocating.
3504 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
3505 schedule_instructions(pre_modes
[i
]);
3508 assign_regs_trivial();
3509 allocated_without_spills
= true;
3511 allocated_without_spills
= assign_regs(false);
3513 if (allocated_without_spills
)
3517 if (!allocated_without_spills
) {
3518 /* We assume that any spilling is worse than just dropping back to
3519 * SIMD8. There's probably actually some intermediate point where
3520 * SIMD16 with a couple of spills is still better.
3522 if (dispatch_width
== 16) {
3523 fail("Failure to register allocate. Reduce number of "
3524 "live scalar values to avoid this.");
3526 perf_debug("Fragment shader triggered register spilling. "
3527 "Try reducing the number of live scalar values to "
3528 "improve performance.\n");
3531 /* Since we're out of heuristics, just go spill registers until we
3532 * get an allocation.
3534 while (!assign_regs(true)) {
3540 /* This must come after all optimization and register allocation, since
3541 * it inserts dead code that happens to have side effects, and it does
3542 * so based on the actual physical registers in use.
3544 insert_gen4_send_dependency_workarounds();
3549 if (!allocated_without_spills
)
3550 schedule_instructions(SCHEDULE_POST
);
3552 if (last_scratch
> 0)
3553 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
3559 sanity_param_count
= prog
->Parameters
->NumParameters
;
3561 assign_binding_table_offsets();
3564 setup_payload_gen6();
3566 setup_payload_gen4();
3570 } else if (brw
->use_rep_send
&& dispatch_width
== 16) {
3571 emit_repclear_shader();
3573 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3574 emit_shader_time_begin();
3576 calculate_urb_setup();
3577 if (prog
->InputsRead
> 0) {
3579 emit_interpolation_setup_gen4();
3581 emit_interpolation_setup_gen6();
3584 /* We handle discards by keeping track of the still-live pixels in f0.1.
3585 * Initialize it with the dispatched pixels.
3588 (stage
== MESA_SHADER_FRAGMENT
) &&
3589 ((brw_wm_prog_data
*) this->prog_data
)->uses_kill
;
3590 bool alpha_test_func
=
3591 (stage
== MESA_SHADER_FRAGMENT
) &&
3592 ((brw_wm_prog_key
*) this->key
)->alpha_test_func
;
3594 fs_inst
*discard_init
= emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
3595 discard_init
->flag_subreg
= 1;
3598 /* Generate FS IR for main(). (the visitor only descends into
3599 * functions called "main").
3602 foreach_in_list(ir_instruction
, ir
, shader
->base
.ir
) {
3604 this->result
= reg_undef
;
3608 emit_fragment_program_code();
3614 emit(FS_OPCODE_PLACEHOLDER_HALT
);
3616 if (alpha_test_func
)
3623 assign_curb_setup();
3626 allocate_registers();
3632 if (stage
== MESA_SHADER_FRAGMENT
) {
3633 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3634 if (dispatch_width
== 8)
3635 prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
3637 prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
3640 /* If any state parameters were appended, then ParameterValues could have
3641 * been realloced, in which case the driver uniform storage set up by
3642 * _mesa_associate_uniform_storage() would point to freed memory. Make
3643 * sure that didn't happen.
3645 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
3651 brw_wm_fs_emit(struct brw_context
*brw
,
3653 const struct brw_wm_prog_key
*key
,
3654 struct brw_wm_prog_data
*prog_data
,
3655 struct gl_fragment_program
*fp
,
3656 struct gl_shader_program
*prog
,
3657 unsigned *final_assembly_size
)
3659 bool start_busy
= false;
3660 double start_time
= 0;
3662 if (unlikely(brw
->perf_debug
)) {
3663 start_busy
= (brw
->batch
.last_bo
&&
3664 drm_intel_bo_busy(brw
->batch
.last_bo
));
3665 start_time
= get_time();
3668 struct brw_shader
*shader
= NULL
;
3670 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3672 if (unlikely(INTEL_DEBUG
& DEBUG_WM
))
3673 brw_dump_ir("fragment", prog
, &shader
->base
, &fp
->Base
);
3675 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3677 fs_visitor
v(brw
, mem_ctx
, key
, prog_data
, prog
, fp
, 8);
3680 prog
->LinkStatus
= false;
3681 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
3684 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
3690 cfg_t
*simd16_cfg
= NULL
;
3691 fs_visitor
v2(brw
, mem_ctx
, key
, prog_data
, prog
, fp
, 16);
3692 if (brw
->gen
>= 5 && likely(!(INTEL_DEBUG
& DEBUG_NO16
) ||
3693 brw
->use_rep_send
)) {
3694 if (!v
.simd16_unsupported
) {
3695 /* Try a SIMD16 compile */
3696 v2
.import_uniforms(&v
);
3698 perf_debug("SIMD16 shader failed to compile, falling back to "
3699 "SIMD8 at a 10-20%% performance cost: %s", v2
.fail_msg
);
3701 simd16_cfg
= v2
.cfg
;
3704 perf_debug("SIMD16 shader unsupported, falling back to "
3705 "SIMD8 at a 10-20%% performance cost: %s", v
.no16_msg
);
3710 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || brw
->no_simd8
;
3711 if (no_simd8
&& simd16_cfg
) {
3713 prog_data
->no_8
= true;
3716 prog_data
->no_8
= false;
3719 fs_generator
g(brw
, mem_ctx
, (void *) key
, &prog_data
->base
, prog
, &fp
->Base
,
3720 v
.runtime_check_aads_emit
, INTEL_DEBUG
& DEBUG_WM
);
3722 g
.generate_code(simd8_cfg
, 8);
3724 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
3726 if (unlikely(brw
->perf_debug
) && shader
) {
3727 if (shader
->compiled_once
)
3728 brw_wm_debug_recompile(brw
, prog
, key
);
3729 shader
->compiled_once
= true;
3731 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
3732 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
3733 (get_time() - start_time
) * 1000);
3737 return g
.get_assembly(final_assembly_size
);
3741 brw_fs_precompile(struct gl_context
*ctx
,
3742 struct gl_shader_program
*shader_prog
,
3743 struct gl_program
*prog
)
3745 struct brw_context
*brw
= brw_context(ctx
);
3746 struct brw_wm_prog_key key
;
3748 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*) prog
;
3749 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
3750 bool program_uses_dfdy
= fp
->UsesDFdy
;
3752 memset(&key
, 0, sizeof(key
));
3756 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
3758 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
3759 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
3761 /* Just assume depth testing. */
3762 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
3763 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
3766 if (brw
->gen
< 6 || _mesa_bitcount_64(fp
->Base
.InputsRead
&
3767 BRW_FS_VARYING_INPUT_MASK
) > 16)
3768 key
.input_slots_valid
= fp
->Base
.InputsRead
| VARYING_BIT_POS
;
3770 unsigned sampler_count
= _mesa_fls(fp
->Base
.SamplersUsed
);
3771 for (unsigned i
= 0; i
< sampler_count
; i
++) {
3772 if (fp
->Base
.ShadowSamplers
& (1 << i
)) {
3773 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
3774 key
.tex
.swizzles
[i
] =
3775 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
3777 /* Color sampler: assume no swizzling. */
3778 key
.tex
.swizzles
[i
] = SWIZZLE_XYZW
;
3782 if (fp
->Base
.InputsRead
& VARYING_BIT_POS
) {
3783 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
3786 key
.nr_color_regions
= _mesa_bitcount_64(fp
->Base
.OutputsWritten
&
3787 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
3788 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
)));
3790 if ((fp
->Base
.InputsRead
& VARYING_BIT_POS
) || program_uses_dfdy
) {
3791 key
.render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
) ||
3792 key
.nr_color_regions
> 1;
3795 key
.program_string_id
= bfp
->id
;
3797 uint32_t old_prog_offset
= brw
->wm
.base
.prog_offset
;
3798 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
3800 bool success
= do_wm_prog(brw
, shader_prog
, bfp
, &key
);
3802 brw
->wm
.base
.prog_offset
= old_prog_offset
;
3803 brw
->wm
.prog_data
= old_prog_data
;