2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "brw_vec4_gs_visitor.h"
48 #include "brw_dead_control_flow.h"
49 #include "main/uniforms.h"
50 #include "brw_fs_live_variables.h"
51 #include "glsl/nir/glsl_types.h"
52 #include "program/sampler.h"
57 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
58 const fs_reg
*src
, unsigned sources
)
60 memset(this, 0, sizeof(*this));
62 this->src
= new fs_reg
[MAX2(sources
, 3)];
63 for (unsigned i
= 0; i
< sources
; i
++)
64 this->src
[i
] = src
[i
];
66 this->opcode
= opcode
;
68 this->sources
= sources
;
69 this->exec_size
= exec_size
;
71 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
73 assert(this->exec_size
!= 0);
75 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
77 /* This will be the case for almost all instructions. */
83 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
87 this->regs_written
= 0;
91 unreachable("Invalid destination register file");
94 this->writes_accumulator
= false;
99 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
104 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
107 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
109 init(opcode
, exec_size
, dst
, NULL
, 0);
112 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
115 const fs_reg src
[1] = { src0
};
116 init(opcode
, exec_size
, dst
, src
, 1);
119 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
120 const fs_reg
&src0
, const fs_reg
&src1
)
122 const fs_reg src
[2] = { src0
, src1
};
123 init(opcode
, exec_size
, dst
, src
, 2);
126 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
127 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
129 const fs_reg src
[3] = { src0
, src1
, src2
};
130 init(opcode
, exec_size
, dst
, src
, 3);
133 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
134 const fs_reg src
[], unsigned sources
)
136 init(opcode
, exec_width
, dst
, src
, sources
);
139 fs_inst::fs_inst(const fs_inst
&that
)
141 memcpy(this, &that
, sizeof(that
));
143 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
145 for (unsigned i
= 0; i
< that
.sources
; i
++)
146 this->src
[i
] = that
.src
[i
];
155 fs_inst::resize_sources(uint8_t num_sources
)
157 if (this->sources
!= num_sources
) {
158 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
160 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
161 src
[i
] = this->src
[i
];
165 this->sources
= num_sources
;
170 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
172 const fs_reg
&surf_index
,
173 const fs_reg
&varying_offset
,
174 uint32_t const_offset
)
176 /* We have our constant surface use a pitch of 4 bytes, so our index can
177 * be any component of a vector, and then we load 4 contiguous
178 * components starting from that.
180 * We break down the const_offset to a portion added to the variable
181 * offset and a portion done using reg_offset, which means that if you
182 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
183 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
184 * CSE can later notice that those loads are all the same and eliminate
185 * the redundant ones.
187 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
188 bld
.ADD(vec4_offset
, varying_offset
, fs_reg(const_offset
& ~3));
191 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
192 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
193 * u, v, r) as parameters, or we can just use the SIMD16 message
194 * consisting of (header, u). We choose the second, at the cost of a
195 * longer return length.
201 if (devinfo
->gen
>= 7)
202 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
204 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
206 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
207 fs_reg vec4_result
= fs_reg(GRF
, alloc
.allocate(regs_written
), dst
.type
);
208 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
209 inst
->regs_written
= regs_written
;
211 if (devinfo
->gen
< 7) {
212 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
);
213 inst
->header_size
= 1;
214 if (devinfo
->gen
== 4)
217 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
220 bld
.MOV(dst
, offset(vec4_result
, bld
, (const_offset
& 3) * scale
));
224 * A helper for MOV generation for fixing up broken hardware SEND dependency
228 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
230 /* The caller always wants uncompressed to emit the minimal extra
231 * dependencies, and to avoid having to deal with aligning its regs to 2.
233 const fs_builder ubld
= bld
.annotate("send dependency resolve")
236 ubld
.MOV(ubld
.null_reg_f(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
240 fs_inst::equals(fs_inst
*inst
) const
242 return (opcode
== inst
->opcode
&&
243 dst
.equals(inst
->dst
) &&
244 src
[0].equals(inst
->src
[0]) &&
245 src
[1].equals(inst
->src
[1]) &&
246 src
[2].equals(inst
->src
[2]) &&
247 saturate
== inst
->saturate
&&
248 predicate
== inst
->predicate
&&
249 conditional_mod
== inst
->conditional_mod
&&
250 mlen
== inst
->mlen
&&
251 base_mrf
== inst
->base_mrf
&&
252 target
== inst
->target
&&
254 header_size
== inst
->header_size
&&
255 shadow_compare
== inst
->shadow_compare
&&
256 exec_size
== inst
->exec_size
&&
257 offset
== inst
->offset
);
261 fs_inst::overwrites_reg(const fs_reg
®
) const
263 return reg
.in_range(dst
, regs_written
);
267 fs_inst::is_send_from_grf() const
270 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
271 case SHADER_OPCODE_SHADER_TIME_ADD
:
272 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
273 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
274 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
275 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
276 case SHADER_OPCODE_UNTYPED_ATOMIC
:
277 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
278 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
279 case SHADER_OPCODE_TYPED_ATOMIC
:
280 case SHADER_OPCODE_TYPED_SURFACE_READ
:
281 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
282 case SHADER_OPCODE_URB_WRITE_SIMD8
:
283 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
284 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
285 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
286 case SHADER_OPCODE_URB_READ_SIMD8
:
288 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
289 return src
[1].file
== GRF
;
290 case FS_OPCODE_FB_WRITE
:
291 return src
[0].file
== GRF
;
294 return src
[0].file
== GRF
;
301 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
303 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
306 fs_reg reg
= this->src
[0];
307 if (reg
.file
!= GRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
310 if (grf_alloc
.sizes
[reg
.reg
] != this->regs_written
)
313 for (int i
= 0; i
< this->sources
; i
++) {
314 reg
.type
= this->src
[i
].type
;
315 if (!this->src
[i
].equals(reg
))
318 if (i
< this->header_size
) {
321 reg
.reg_offset
+= this->exec_size
/ 8;
329 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
331 if (devinfo
->gen
== 6 && is_math())
334 if (is_send_from_grf())
337 if (!backend_instruction::can_do_source_mods())
344 fs_inst::can_change_types() const
346 return dst
.type
== src
[0].type
&&
347 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
348 (opcode
== BRW_OPCODE_MOV
||
349 (opcode
== BRW_OPCODE_SEL
&&
350 dst
.type
== src
[1].type
&&
351 predicate
!= BRW_PREDICATE_NONE
&&
352 !src
[1].abs
&& !src
[1].negate
));
356 fs_inst::has_side_effects() const
358 return this->eot
|| backend_instruction::has_side_effects();
364 memset(this, 0, sizeof(*this));
368 /** Generic unset register constructor. */
372 this->file
= BAD_FILE
;
375 /** Immediate value constructor. */
376 fs_reg::fs_reg(float f
)
380 this->type
= BRW_REGISTER_TYPE_F
;
382 this->fixed_hw_reg
.dw1
.f
= f
;
385 /** Immediate value constructor. */
386 fs_reg::fs_reg(int32_t i
)
390 this->type
= BRW_REGISTER_TYPE_D
;
392 this->fixed_hw_reg
.dw1
.d
= i
;
395 /** Immediate value constructor. */
396 fs_reg::fs_reg(uint32_t u
)
400 this->type
= BRW_REGISTER_TYPE_UD
;
402 this->fixed_hw_reg
.dw1
.ud
= u
;
405 /** Vector float immediate value constructor. */
406 fs_reg::fs_reg(uint8_t vf
[4])
410 this->type
= BRW_REGISTER_TYPE_VF
;
411 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
414 /** Vector float immediate value constructor. */
415 fs_reg::fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
419 this->type
= BRW_REGISTER_TYPE_VF
;
420 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
426 /** Fixed brw_reg. */
427 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
431 this->fixed_hw_reg
= fixed_hw_reg
;
432 this->type
= fixed_hw_reg
.type
;
436 fs_reg::equals(const fs_reg
&r
) const
438 return (file
== r
.file
&&
440 reg_offset
== r
.reg_offset
&&
441 subreg_offset
== r
.subreg_offset
&&
443 negate
== r
.negate
&&
445 !reladdr
&& !r
.reladdr
&&
446 ((file
!= HW_REG
&& file
!= IMM
) ||
447 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
448 sizeof(fixed_hw_reg
)) == 0) &&
453 fs_reg::set_smear(unsigned subreg
)
455 assert(file
!= HW_REG
&& file
!= IMM
);
456 subreg_offset
= subreg
* type_sz(type
);
462 fs_reg::is_contiguous() const
468 fs_reg::component_size(unsigned width
) const
470 const unsigned stride
= (file
!= HW_REG
? this->stride
:
471 fixed_hw_reg
.hstride
== 0 ? 0 :
472 1 << (fixed_hw_reg
.hstride
- 1));
473 return MAX2(width
* stride
, 1) * type_sz(type
);
477 type_size_scalar(const struct glsl_type
*type
)
479 unsigned int size
, i
;
481 switch (type
->base_type
) {
484 case GLSL_TYPE_FLOAT
:
486 return type
->components();
487 case GLSL_TYPE_ARRAY
:
488 return type_size_scalar(type
->fields
.array
) * type
->length
;
489 case GLSL_TYPE_STRUCT
:
491 for (i
= 0; i
< type
->length
; i
++) {
492 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
495 case GLSL_TYPE_SAMPLER
:
496 /* Samplers take up no register space, since they're baked in at
500 case GLSL_TYPE_ATOMIC_UINT
:
502 case GLSL_TYPE_SUBROUTINE
:
504 case GLSL_TYPE_IMAGE
:
505 return BRW_IMAGE_PARAM_SIZE
;
507 case GLSL_TYPE_ERROR
:
508 case GLSL_TYPE_INTERFACE
:
509 case GLSL_TYPE_DOUBLE
:
510 unreachable("not reached");
517 * Returns the number of scalar components needed to store type, assuming
518 * that vectors are padded out to vec4.
520 * This has the packing rules of type_size_vec4(), but counts components
521 * similar to type_size_scalar().
524 type_size_vec4_times_4(const struct glsl_type
*type
)
526 return 4 * type_size_vec4(type
);
530 * Create a MOV to read the timestamp register.
532 * The caller is responsible for emitting the MOV. The return value is
533 * the destination of the MOV, with extra parameters set.
536 fs_visitor::get_timestamp(const fs_builder
&bld
)
538 assert(devinfo
->gen
>= 7);
540 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
543 BRW_REGISTER_TYPE_UD
));
545 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
547 /* We want to read the 3 fields we care about even if it's not enabled in
550 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
556 fs_visitor::emit_shader_time_begin()
558 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
560 /* We want only the low 32 bits of the timestamp. Since it's running
561 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
562 * which is plenty of time for our purposes. It is identical across the
563 * EUs, but since it's tracking GPU core speed it will increment at a
564 * varying rate as render P-states change.
566 shader_start_time
.set_smear(0);
570 fs_visitor::emit_shader_time_end()
572 /* Insert our code just before the final SEND with EOT. */
573 exec_node
*end
= this->instructions
.get_tail();
574 assert(end
&& ((fs_inst
*) end
)->eot
);
575 const fs_builder ibld
= bld
.annotate("shader time end")
576 .exec_all().at(NULL
, end
);
578 fs_reg shader_end_time
= get_timestamp(ibld
);
580 /* We only use the low 32 bits of the timestamp - see
581 * emit_shader_time_begin()).
583 * We could also check if render P-states have changed (or anything
584 * else that might disrupt timing) by setting smear to 2 and checking if
585 * that field is != 0.
587 shader_end_time
.set_smear(0);
589 /* Check that there weren't any timestamp reset events (assuming these
590 * were the only two timestamp reads that happened).
592 fs_reg reset
= shader_end_time
;
594 set_condmod(BRW_CONDITIONAL_Z
,
595 ibld
.AND(ibld
.null_reg_ud(), reset
, fs_reg(1u)));
596 ibld
.IF(BRW_PREDICATE_NORMAL
);
598 fs_reg start
= shader_start_time
;
600 fs_reg diff
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
603 const fs_builder cbld
= ibld
.group(1, 0);
604 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
606 /* If there were no instructions between the two timestamp gets, the diff
607 * is 2 cycles. Remove that overhead, so I can forget about that when
608 * trying to determine the time taken for single instructions.
610 cbld
.ADD(diff
, diff
, fs_reg(-2u));
611 SHADER_TIME_ADD(cbld
, 0, diff
);
612 SHADER_TIME_ADD(cbld
, 1, fs_reg(1u));
613 ibld
.emit(BRW_OPCODE_ELSE
);
614 SHADER_TIME_ADD(cbld
, 2, fs_reg(1u));
615 ibld
.emit(BRW_OPCODE_ENDIF
);
619 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
620 int shader_time_subindex
,
623 int index
= shader_time_index
* 3 + shader_time_subindex
;
624 fs_reg offset
= fs_reg(index
* SHADER_TIME_STRIDE
);
627 if (dispatch_width
== 8)
628 payload
= vgrf(glsl_type::uvec2_type
);
630 payload
= vgrf(glsl_type::uint_type
);
632 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
636 fs_visitor::vfail(const char *format
, va_list va
)
645 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
646 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
648 this->fail_msg
= msg
;
651 fprintf(stderr
, "%s", msg
);
656 fs_visitor::fail(const char *format
, ...)
660 va_start(va
, format
);
666 * Mark this program as impossible to compile in SIMD16 mode.
668 * During the SIMD8 compile (which happens first), we can detect and flag
669 * things that are unsupported in SIMD16 mode, so the compiler can skip
670 * the SIMD16 compile altogether.
672 * During a SIMD16 compile (if one happens anyway), this just calls fail().
675 fs_visitor::no16(const char *msg
)
677 if (dispatch_width
== 16) {
680 simd16_unsupported
= true;
682 compiler
->shader_perf_log(log_data
,
683 "SIMD16 shader failed to compile: %s", msg
);
688 * Returns true if the instruction has a flag that means it won't
689 * update an entire destination register.
691 * For example, dead code elimination and live variable analysis want to know
692 * when a write to a variable screens off any preceding values that were in
696 fs_inst::is_partial_write() const
698 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
699 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
700 !this->dst
.is_contiguous());
704 fs_inst::components_read(unsigned i
) const
707 case FS_OPCODE_LINTERP
:
713 case FS_OPCODE_PIXEL_X
:
714 case FS_OPCODE_PIXEL_Y
:
718 case FS_OPCODE_FB_WRITE_LOGICAL
:
719 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
720 /* First/second FB write color. */
722 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].fixed_hw_reg
.dw1
.ud
;
726 case SHADER_OPCODE_TEX_LOGICAL
:
727 case SHADER_OPCODE_TXD_LOGICAL
:
728 case SHADER_OPCODE_TXF_LOGICAL
:
729 case SHADER_OPCODE_TXL_LOGICAL
:
730 case SHADER_OPCODE_TXS_LOGICAL
:
731 case FS_OPCODE_TXB_LOGICAL
:
732 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
733 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
734 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
735 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
736 case SHADER_OPCODE_LOD_LOGICAL
:
737 case SHADER_OPCODE_TG4_LOGICAL
:
738 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
739 assert(src
[8].file
== IMM
&& src
[9].file
== IMM
);
740 /* Texture coordinates. */
742 return src
[8].fixed_hw_reg
.dw1
.ud
;
743 /* Texture derivatives. */
744 else if ((i
== 2 || i
== 3) && opcode
== SHADER_OPCODE_TXD_LOGICAL
)
745 return src
[9].fixed_hw_reg
.dw1
.ud
;
746 /* Texture offset. */
750 else if (i
== 5 && opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
755 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
756 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
757 assert(src
[3].file
== IMM
);
758 /* Surface coordinates. */
760 return src
[3].fixed_hw_reg
.dw1
.ud
;
761 /* Surface operation source (ignored for reads). */
767 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
768 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
769 assert(src
[3].file
== IMM
&&
771 /* Surface coordinates. */
773 return src
[3].fixed_hw_reg
.dw1
.ud
;
774 /* Surface operation source. */
776 return src
[4].fixed_hw_reg
.dw1
.ud
;
780 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
781 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
782 assert(src
[3].file
== IMM
&&
784 const unsigned op
= src
[4].fixed_hw_reg
.dw1
.ud
;
785 /* Surface coordinates. */
787 return src
[3].fixed_hw_reg
.dw1
.ud
;
788 /* Surface operation source. */
789 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
791 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
792 op
== BRW_AOP_PREDEC
))
804 fs_inst::regs_read(int arg
) const
807 case FS_OPCODE_FB_WRITE
:
808 case SHADER_OPCODE_URB_WRITE_SIMD8
:
809 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
810 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
811 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
812 case SHADER_OPCODE_URB_READ_SIMD8
:
813 case SHADER_OPCODE_UNTYPED_ATOMIC
:
814 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
815 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
816 case SHADER_OPCODE_TYPED_ATOMIC
:
817 case SHADER_OPCODE_TYPED_SURFACE_READ
:
818 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
819 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
824 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
825 /* The payload is actually stored in src1 */
830 case FS_OPCODE_LINTERP
:
835 case SHADER_OPCODE_LOAD_PAYLOAD
:
836 if (arg
< this->header_size
)
840 case CS_OPCODE_CS_TERMINATE
:
841 case SHADER_OPCODE_BARRIER
:
845 if (is_tex() && arg
== 0 && src
[0].file
== GRF
)
850 switch (src
[arg
].file
) {
859 return DIV_ROUND_UP(components_read(arg
) *
860 src
[arg
].component_size(exec_size
),
863 unreachable("MRF registers are not allowed as sources");
869 fs_inst::reads_flag() const
875 fs_inst::writes_flag() const
877 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
878 opcode
!= BRW_OPCODE_IF
&&
879 opcode
!= BRW_OPCODE_WHILE
)) ||
880 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
884 * Returns how many MRFs an FS opcode will write over.
886 * Note that this is not the 0 or 1 implied writes in an actual gen
887 * instruction -- the FS opcodes often generate MOVs in addition.
890 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
895 if (inst
->base_mrf
== -1)
898 switch (inst
->opcode
) {
899 case SHADER_OPCODE_RCP
:
900 case SHADER_OPCODE_RSQ
:
901 case SHADER_OPCODE_SQRT
:
902 case SHADER_OPCODE_EXP2
:
903 case SHADER_OPCODE_LOG2
:
904 case SHADER_OPCODE_SIN
:
905 case SHADER_OPCODE_COS
:
906 return 1 * dispatch_width
/ 8;
907 case SHADER_OPCODE_POW
:
908 case SHADER_OPCODE_INT_QUOTIENT
:
909 case SHADER_OPCODE_INT_REMAINDER
:
910 return 2 * dispatch_width
/ 8;
911 case SHADER_OPCODE_TEX
:
913 case SHADER_OPCODE_TXD
:
914 case SHADER_OPCODE_TXF
:
915 case SHADER_OPCODE_TXF_CMS
:
916 case SHADER_OPCODE_TXF_CMS_W
:
917 case SHADER_OPCODE_TXF_MCS
:
918 case SHADER_OPCODE_TG4
:
919 case SHADER_OPCODE_TG4_OFFSET
:
920 case SHADER_OPCODE_TXL
:
921 case SHADER_OPCODE_TXS
:
922 case SHADER_OPCODE_LOD
:
923 case SHADER_OPCODE_SAMPLEINFO
:
925 case FS_OPCODE_FB_WRITE
:
927 case FS_OPCODE_GET_BUFFER_SIZE
:
928 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
929 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
931 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
933 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
935 case SHADER_OPCODE_UNTYPED_ATOMIC
:
936 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
937 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
938 case SHADER_OPCODE_TYPED_ATOMIC
:
939 case SHADER_OPCODE_TYPED_SURFACE_READ
:
940 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
941 case SHADER_OPCODE_URB_WRITE_SIMD8
:
942 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
943 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
944 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
945 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
946 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
947 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
948 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
951 unreachable("not reached");
956 fs_visitor::vgrf(const glsl_type
*const type
)
958 int reg_width
= dispatch_width
/ 8;
959 return fs_reg(GRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
960 brw_type_for_base_type(type
));
963 /** Fixed HW reg constructor. */
964 fs_reg::fs_reg(enum register_file file
, int reg
)
969 this->type
= BRW_REGISTER_TYPE_F
;
970 this->stride
= (file
== UNIFORM
? 0 : 1);
973 /** Fixed HW reg constructor. */
974 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
)
980 this->stride
= (file
== UNIFORM
? 0 : 1);
983 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
984 * This brings in those uniform definitions
987 fs_visitor::import_uniforms(fs_visitor
*v
)
989 this->push_constant_loc
= v
->push_constant_loc
;
990 this->pull_constant_loc
= v
->pull_constant_loc
;
991 this->uniforms
= v
->uniforms
;
992 this->param_size
= v
->param_size
;
996 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
997 bool origin_upper_left
)
999 assert(stage
== MESA_SHADER_FRAGMENT
);
1000 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1001 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
1003 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
1005 /* gl_FragCoord.x */
1006 if (pixel_center_integer
) {
1007 bld
.MOV(wpos
, this->pixel_x
);
1009 bld
.ADD(wpos
, this->pixel_x
, fs_reg(0.5f
));
1011 wpos
= offset(wpos
, bld
, 1);
1013 /* gl_FragCoord.y */
1014 if (!flip
&& pixel_center_integer
) {
1015 bld
.MOV(wpos
, this->pixel_y
);
1017 fs_reg pixel_y
= this->pixel_y
;
1018 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
1021 pixel_y
.negate
= true;
1022 offset
+= key
->drawable_height
- 1.0f
;
1025 bld
.ADD(wpos
, pixel_y
, fs_reg(offset
));
1027 wpos
= offset(wpos
, bld
, 1);
1029 /* gl_FragCoord.z */
1030 if (devinfo
->gen
>= 6) {
1031 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1033 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1034 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1035 interp_reg(VARYING_SLOT_POS
, 2));
1037 wpos
= offset(wpos
, bld
, 1);
1039 /* gl_FragCoord.w: Already set up in emit_interpolation */
1040 bld
.MOV(wpos
, this->wpos_w
);
1046 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1047 glsl_interp_qualifier interpolation_mode
,
1048 bool is_centroid
, bool is_sample
)
1050 brw_wm_barycentric_interp_mode barycoord_mode
;
1051 if (devinfo
->gen
>= 6) {
1053 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1054 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1056 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1057 } else if (is_sample
) {
1058 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1059 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1061 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1063 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1064 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1066 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1069 /* On Ironlake and below, there is only one interpolation mode.
1070 * Centroid interpolation doesn't mean anything on this hardware --
1071 * there is no multisampling.
1073 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1075 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1076 this->delta_xy
[barycoord_mode
], interp
);
1080 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
1081 const glsl_type
*type
,
1082 glsl_interp_qualifier interpolation_mode
,
1083 int location
, bool mod_centroid
,
1086 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
1088 assert(stage
== MESA_SHADER_FRAGMENT
);
1089 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1090 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1092 unsigned int array_elements
;
1094 if (type
->is_array()) {
1095 array_elements
= type
->arrays_of_arrays_size();
1096 if (array_elements
== 0) {
1097 fail("dereferenced array '%s' has length 0\n", name
);
1099 type
= type
->without_array();
1104 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1106 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1107 if (key
->flat_shade
&& is_gl_Color
) {
1108 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1110 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1114 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1115 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1116 if (prog_data
->urb_setup
[location
] == -1) {
1117 /* If there's no incoming setup data for this slot, don't
1118 * emit interpolation for it.
1120 attr
= offset(attr
, bld
, type
->vector_elements
);
1125 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1126 /* Constant interpolation (flat shading) case. The SF has
1127 * handed us defined values in only the constant offset
1128 * field of the setup reg.
1130 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1131 struct brw_reg interp
= interp_reg(location
, k
);
1132 interp
= suboffset(interp
, 3);
1133 interp
.type
= attr
.type
;
1134 bld
.emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1135 attr
= offset(attr
, bld
, 1);
1138 /* Smooth/noperspective interpolation case. */
1139 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1140 struct brw_reg interp
= interp_reg(location
, k
);
1141 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1142 /* Get the pixel/sample mask into f0 so that we know
1143 * which pixels are lit. Then, for each channel that is
1144 * unlit, replace the centroid data with non-centroid
1147 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1150 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1152 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1153 inst
->predicate_inverse
= true;
1154 if (devinfo
->has_pln
)
1155 inst
->no_dd_clear
= true;
1157 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1158 mod_centroid
&& !key
->persample_shading
,
1159 mod_sample
|| key
->persample_shading
);
1160 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1161 inst
->predicate_inverse
= false;
1162 if (devinfo
->has_pln
)
1163 inst
->no_dd_check
= true;
1166 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1167 mod_centroid
&& !key
->persample_shading
,
1168 mod_sample
|| key
->persample_shading
);
1170 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1171 bld
.MUL(attr
, attr
, this->pixel_w
);
1173 attr
= offset(attr
, bld
, 1);
1183 fs_visitor::emit_frontfacing_interpolation()
1185 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1187 if (devinfo
->gen
>= 6) {
1188 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1189 * a boolean result from this (~0/true or 0/false).
1191 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1192 * this task in only one instruction:
1193 * - a negation source modifier will flip the bit; and
1194 * - a W -> D type conversion will sign extend the bit into the high
1195 * word of the destination.
1197 * An ASR 15 fills the low word of the destination.
1199 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1202 bld
.ASR(*reg
, g0
, fs_reg(15));
1204 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1205 * a boolean result from this (1/true or 0/false).
1207 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1208 * the negation source modifier to flip it. Unfortunately the SHR
1209 * instruction only operates on UD (or D with an abs source modifier)
1210 * sources without negation.
1212 * Instead, use ASR (which will give ~0/true or 0/false).
1214 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1217 bld
.ASR(*reg
, g1_6
, fs_reg(31));
1224 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1226 assert(stage
== MESA_SHADER_FRAGMENT
);
1227 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1228 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1230 if (key
->compute_pos_offset
) {
1231 /* Convert int_sample_pos to floating point */
1232 bld
.MOV(dst
, int_sample_pos
);
1233 /* Scale to the range [0, 1] */
1234 bld
.MUL(dst
, dst
, fs_reg(1 / 16.0f
));
1237 /* From ARB_sample_shading specification:
1238 * "When rendering to a non-multisample buffer, or if multisample
1239 * rasterization is disabled, gl_SamplePosition will always be
1242 bld
.MOV(dst
, fs_reg(0.5f
));
1247 fs_visitor::emit_samplepos_setup()
1249 assert(devinfo
->gen
>= 6);
1251 const fs_builder abld
= bld
.annotate("compute sample position");
1252 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1254 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1255 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1257 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1258 * mode will be enabled.
1260 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1261 * R31.1:0 Position Offset X/Y for Slot[3:0]
1262 * R31.3:2 Position Offset X/Y for Slot[7:4]
1265 * The X, Y sample positions come in as bytes in thread payload. So, read
1266 * the positions using vstride=16, width=8, hstride=2.
1268 struct brw_reg sample_pos_reg
=
1269 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1270 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1272 if (dispatch_width
== 8) {
1273 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1275 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1276 abld
.half(1).MOV(half(int_sample_x
, 1),
1277 fs_reg(suboffset(sample_pos_reg
, 16)));
1279 /* Compute gl_SamplePosition.x */
1280 compute_sample_position(pos
, int_sample_x
);
1281 pos
= offset(pos
, abld
, 1);
1282 if (dispatch_width
== 8) {
1283 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1285 abld
.half(0).MOV(half(int_sample_y
, 0),
1286 fs_reg(suboffset(sample_pos_reg
, 1)));
1287 abld
.half(1).MOV(half(int_sample_y
, 1),
1288 fs_reg(suboffset(sample_pos_reg
, 17)));
1290 /* Compute gl_SamplePosition.y */
1291 compute_sample_position(pos
, int_sample_y
);
1296 fs_visitor::emit_sampleid_setup()
1298 assert(stage
== MESA_SHADER_FRAGMENT
);
1299 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1300 assert(devinfo
->gen
>= 6);
1302 const fs_builder abld
= bld
.annotate("compute sample id");
1303 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1305 if (key
->compute_sample_id
) {
1306 fs_reg
t1(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1308 fs_reg
t2(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1310 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1311 * 8x multisampling, subspan 0 will represent sample N (where N
1312 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1313 * 7. We can find the value of N by looking at R0.0 bits 7:6
1314 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1315 * (since samples are always delivered in pairs). That is, we
1316 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1317 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1318 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1319 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1320 * populating a temporary variable with the sequence (0, 1, 2, 3),
1321 * and then reading from it using vstride=1, width=4, hstride=0.
1322 * These computations hold good for 4x multisampling as well.
1324 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1325 * the first four slots are sample 0 of subspan 0; the next four
1326 * are sample 1 of subspan 0; the third group is sample 0 of
1327 * subspan 1, and finally sample 1 of subspan 1.
1330 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1331 * accomodate 16x MSAA.
1333 unsigned sspi_mask
= devinfo
->gen
>= 9 ? 0x1c0 : 0xc0;
1335 abld
.exec_all().group(1, 0)
1336 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1338 abld
.exec_all().group(1, 0).SHR(t1
, t1
, fs_reg(5));
1340 /* This works for both SIMD8 and SIMD16 */
1341 abld
.exec_all().group(4, 0)
1342 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1344 /* This special instruction takes care of setting vstride=1,
1345 * width=4, hstride=0 of t2 during an ADD instruction.
1347 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1349 /* As per GL_ARB_sample_shading specification:
1350 * "When rendering to a non-multisample buffer, or if multisample
1351 * rasterization is disabled, gl_SampleID will always be zero."
1353 abld
.MOV(*reg
, fs_reg(0));
1360 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1362 if (!src
.abs
&& !src
.negate
)
1365 fs_reg temp
= bld
.vgrf(src
.type
);
1372 fs_visitor::emit_discard_jump()
1374 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1376 /* For performance, after a discard, jump to the end of the
1377 * shader if all relevant channels have been discarded.
1379 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1380 discard_jump
->flag_subreg
= 1;
1382 discard_jump
->predicate
= (dispatch_width
== 8)
1383 ? BRW_PREDICATE_ALIGN1_ANY8H
1384 : BRW_PREDICATE_ALIGN1_ANY16H
;
1385 discard_jump
->predicate_inverse
= true;
1389 fs_visitor::emit_gs_thread_end()
1391 assert(stage
== MESA_SHADER_GEOMETRY
);
1393 struct brw_gs_prog_data
*gs_prog_data
=
1394 (struct brw_gs_prog_data
*) prog_data
;
1396 if (gs_compile
->control_data_header_size_bits
> 0) {
1397 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1400 const fs_builder abld
= bld
.annotate("thread end");
1403 if (gs_prog_data
->static_vertex_count
!= -1) {
1404 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1405 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1406 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1407 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1408 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1411 /* Delete now dead instructions. */
1412 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1418 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1422 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1423 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1424 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1427 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1428 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1429 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1430 sources
[1] = this->final_gs_vertex_count
;
1431 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1432 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1440 fs_visitor::assign_curb_setup()
1442 if (dispatch_width
== 8) {
1443 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1445 if (stage
== MESA_SHADER_FRAGMENT
) {
1446 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1447 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1448 } else if (stage
== MESA_SHADER_COMPUTE
) {
1449 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1450 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1452 unreachable("Unsupported shader type!");
1456 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1458 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1459 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1460 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1461 if (inst
->src
[i
].file
== UNIFORM
) {
1462 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1464 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1465 constant_nr
= push_constant_loc
[uniform_nr
];
1467 /* Section 5.11 of the OpenGL 4.1 spec says:
1468 * "Out-of-bounds reads return undefined values, which include
1469 * values from other variables of the active program or zero."
1470 * Just return the first push constant.
1475 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1479 assert(inst
->src
[i
].stride
== 0);
1480 inst
->src
[i
].file
= HW_REG
;
1481 inst
->src
[i
].fixed_hw_reg
= byte_offset(
1482 retype(brw_reg
, inst
->src
[i
].type
),
1483 inst
->src
[i
].subreg_offset
);
1488 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1489 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1493 fs_visitor::calculate_urb_setup()
1495 assert(stage
== MESA_SHADER_FRAGMENT
);
1496 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1497 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1499 memset(prog_data
->urb_setup
, -1,
1500 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1503 /* Figure out where each of the incoming setup attributes lands. */
1504 if (devinfo
->gen
>= 6) {
1505 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1506 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1507 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1508 * first 16 varying inputs, so we can put them wherever we want.
1509 * Just put them in order.
1511 * This is useful because it means that (a) inputs not used by the
1512 * fragment shader won't take up valuable register space, and (b) we
1513 * won't have to recompile the fragment shader if it gets paired with
1514 * a different vertex (or geometry) shader.
1516 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1517 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1518 BITFIELD64_BIT(i
)) {
1519 prog_data
->urb_setup
[i
] = urb_next
++;
1523 bool include_vue_header
=
1524 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1526 /* We have enough input varyings that the SF/SBE pipeline stage can't
1527 * arbitrarily rearrange them to suit our whim; we have to put them
1528 * in an order that matches the output of the previous pipeline stage
1529 * (geometry or vertex shader).
1531 struct brw_vue_map prev_stage_vue_map
;
1532 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1533 key
->input_slots_valid
,
1534 nir
->info
.separate_shader
);
1536 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1538 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1539 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1541 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1542 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1543 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1544 BITFIELD64_BIT(varying
))) {
1545 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1548 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1551 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1552 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1553 /* Point size is packed into the header, not as a general attribute */
1554 if (i
== VARYING_SLOT_PSIZ
)
1557 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1558 /* The back color slot is skipped when the front color is
1559 * also written to. In addition, some slots can be
1560 * written in the vertex shader and not read in the
1561 * fragment shader. So the register number must always be
1562 * incremented, mapped or not.
1564 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1565 prog_data
->urb_setup
[i
] = urb_next
;
1571 * It's a FS only attribute, and we did interpolation for this attribute
1572 * in SF thread. So, count it here, too.
1574 * See compile_sf_prog() for more info.
1576 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1577 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1580 prog_data
->num_varying_inputs
= urb_next
;
1584 fs_visitor::assign_urb_setup()
1586 assert(stage
== MESA_SHADER_FRAGMENT
);
1587 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1589 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1591 /* Offset all the urb_setup[] index by the actual position of the
1592 * setup regs, now that the location of the constants has been chosen.
1594 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1595 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1596 assert(inst
->src
[1].file
== HW_REG
);
1597 inst
->src
[1].fixed_hw_reg
.nr
+= urb_start
;
1600 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1601 assert(inst
->src
[0].file
== HW_REG
);
1602 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1606 /* Each attribute is 4 setup channels, each of which is half a reg. */
1607 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1611 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1613 for (int i
= 0; i
< inst
->sources
; i
++) {
1614 if (inst
->src
[i
].file
== ATTR
) {
1615 int grf
= payload
.num_regs
+
1616 prog_data
->curb_read_length
+
1618 inst
->src
[i
].reg_offset
;
1620 inst
->src
[i
].file
= HW_REG
;
1621 inst
->src
[i
].fixed_hw_reg
=
1622 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1623 inst
->src
[i
].subreg_offset
),
1624 inst
->exec_size
* inst
->src
[i
].stride
,
1625 inst
->exec_size
, inst
->src
[i
].stride
);
1631 fs_visitor::assign_vs_urb_setup()
1633 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1635 assert(stage
== MESA_SHADER_VERTEX
);
1636 int count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1637 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1640 /* Each attribute is 4 regs. */
1641 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attributes
;
1643 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1645 /* Rewrite all ATTR file references to the hw grf that they land in. */
1646 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1647 convert_attr_sources_to_hw_regs(inst
);
1652 fs_visitor::assign_gs_urb_setup()
1654 assert(stage
== MESA_SHADER_GEOMETRY
);
1656 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1658 first_non_payload_grf
+=
1659 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1661 const unsigned first_icp_handle
= payload
.num_regs
-
1662 (vue_prog_data
->include_vue_handles
? nir
->info
.gs
.vertices_in
: 0);
1664 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1665 /* Lower URB_READ_SIMD8 opcodes into real messages. */
1666 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8
) {
1667 assert(inst
->src
[0].file
== IMM
);
1668 inst
->src
[0] = retype(brw_vec8_grf(first_icp_handle
+
1669 inst
->src
[0].fixed_hw_reg
.dw1
.ud
,
1670 0), BRW_REGISTER_TYPE_UD
);
1671 /* for now, assume constant - we can do per-slot offsets later */
1672 assert(inst
->src
[1].file
== IMM
);
1673 inst
->offset
= inst
->src
[1].fixed_hw_reg
.dw1
.ud
;
1674 inst
->src
[1] = fs_reg();
1676 inst
->base_mrf
= -1;
1679 /* Rewrite all ATTR file references to HW_REGs. */
1680 convert_attr_sources_to_hw_regs(inst
);
1686 * Split large virtual GRFs into separate components if we can.
1688 * This is mostly duplicated with what brw_fs_vector_splitting does,
1689 * but that's really conservative because it's afraid of doing
1690 * splitting that doesn't result in real progress after the rest of
1691 * the optimization phases, which would cause infinite looping in
1692 * optimization. We can do it once here, safely. This also has the
1693 * opportunity to split interpolated values, or maybe even uniforms,
1694 * which we don't have at the IR level.
1696 * We want to split, because virtual GRFs are what we register
1697 * allocate and spill (due to contiguousness requirements for some
1698 * instructions), and they're what we naturally generate in the
1699 * codegen process, but most virtual GRFs don't actually need to be
1700 * contiguous sets of GRFs. If we split, we'll end up with reduced
1701 * live intervals and better dead code elimination and coalescing.
1704 fs_visitor::split_virtual_grfs()
1706 int num_vars
= this->alloc
.count
;
1708 /* Count the total number of registers */
1710 int vgrf_to_reg
[num_vars
];
1711 for (int i
= 0; i
< num_vars
; i
++) {
1712 vgrf_to_reg
[i
] = reg_count
;
1713 reg_count
+= alloc
.sizes
[i
];
1716 /* An array of "split points". For each register slot, this indicates
1717 * if this slot can be separated from the previous slot. Every time an
1718 * instruction uses multiple elements of a register (as a source or
1719 * destination), we mark the used slots as inseparable. Then we go
1720 * through and split the registers into the smallest pieces we can.
1722 bool split_points
[reg_count
];
1723 memset(split_points
, 0, sizeof(split_points
));
1725 /* Mark all used registers as fully splittable */
1726 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1727 if (inst
->dst
.file
== GRF
) {
1728 int reg
= vgrf_to_reg
[inst
->dst
.reg
];
1729 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.reg
]; j
++)
1730 split_points
[reg
+ j
] = true;
1733 for (int i
= 0; i
< inst
->sources
; i
++) {
1734 if (inst
->src
[i
].file
== GRF
) {
1735 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
];
1736 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].reg
]; j
++)
1737 split_points
[reg
+ j
] = true;
1742 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1743 if (inst
->dst
.file
== GRF
) {
1744 int reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1745 for (int j
= 1; j
< inst
->regs_written
; j
++)
1746 split_points
[reg
+ j
] = false;
1748 for (int i
= 0; i
< inst
->sources
; i
++) {
1749 if (inst
->src
[i
].file
== GRF
) {
1750 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1751 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1752 split_points
[reg
+ j
] = false;
1757 int new_virtual_grf
[reg_count
];
1758 int new_reg_offset
[reg_count
];
1761 for (int i
= 0; i
< num_vars
; i
++) {
1762 /* The first one should always be 0 as a quick sanity check. */
1763 assert(split_points
[reg
] == false);
1766 new_reg_offset
[reg
] = 0;
1771 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1772 /* If this is a split point, reset the offset to 0 and allocate a
1773 * new virtual GRF for the previous offset many registers
1775 if (split_points
[reg
]) {
1776 assert(offset
<= MAX_VGRF_SIZE
);
1777 int grf
= alloc
.allocate(offset
);
1778 for (int k
= reg
- offset
; k
< reg
; k
++)
1779 new_virtual_grf
[k
] = grf
;
1782 new_reg_offset
[reg
] = offset
;
1787 /* The last one gets the original register number */
1788 assert(offset
<= MAX_VGRF_SIZE
);
1789 alloc
.sizes
[i
] = offset
;
1790 for (int k
= reg
- offset
; k
< reg
; k
++)
1791 new_virtual_grf
[k
] = i
;
1793 assert(reg
== reg_count
);
1795 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1796 if (inst
->dst
.file
== GRF
) {
1797 reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1798 inst
->dst
.reg
= new_virtual_grf
[reg
];
1799 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1800 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1802 for (int i
= 0; i
< inst
->sources
; i
++) {
1803 if (inst
->src
[i
].file
== GRF
) {
1804 reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1805 inst
->src
[i
].reg
= new_virtual_grf
[reg
];
1806 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1807 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1811 invalidate_live_intervals();
1815 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1817 * During code generation, we create tons of temporary variables, many of
1818 * which get immediately killed and are never used again. Yet, in later
1819 * optimization and analysis passes, such as compute_live_intervals, we need
1820 * to loop over all the virtual GRFs. Compacting them can save a lot of
1824 fs_visitor::compact_virtual_grfs()
1826 bool progress
= false;
1827 int remap_table
[this->alloc
.count
];
1828 memset(remap_table
, -1, sizeof(remap_table
));
1830 /* Mark which virtual GRFs are used. */
1831 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1832 if (inst
->dst
.file
== GRF
)
1833 remap_table
[inst
->dst
.reg
] = 0;
1835 for (int i
= 0; i
< inst
->sources
; i
++) {
1836 if (inst
->src
[i
].file
== GRF
)
1837 remap_table
[inst
->src
[i
].reg
] = 0;
1841 /* Compact the GRF arrays. */
1843 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1844 if (remap_table
[i
] == -1) {
1845 /* We just found an unused register. This means that we are
1846 * actually going to compact something.
1850 remap_table
[i
] = new_index
;
1851 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1852 invalidate_live_intervals();
1857 this->alloc
.count
= new_index
;
1859 /* Patch all the instructions to use the newly renumbered registers */
1860 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1861 if (inst
->dst
.file
== GRF
)
1862 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
1864 for (int i
= 0; i
< inst
->sources
; i
++) {
1865 if (inst
->src
[i
].file
== GRF
)
1866 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
1870 /* Patch all the references to delta_xy, since they're used in register
1871 * allocation. If they're unused, switch them to BAD_FILE so we don't
1872 * think some random VGRF is delta_xy.
1874 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1875 if (delta_xy
[i
].file
== GRF
) {
1876 if (remap_table
[delta_xy
[i
].reg
] != -1) {
1877 delta_xy
[i
].reg
= remap_table
[delta_xy
[i
].reg
];
1879 delta_xy
[i
].file
= BAD_FILE
;
1888 * Assign UNIFORM file registers to either push constants or pull constants.
1890 * We allow a fragment shader to have more than the specified minimum
1891 * maximum number of fragment shader uniform components (64). If
1892 * there are too many of these, they'd fill up all of register space.
1893 * So, this will push some of them out to the pull constant buffer and
1894 * update the program to load them. We also use pull constants for all
1895 * indirect constant loads because we don't support indirect accesses in
1899 fs_visitor::assign_constant_locations()
1901 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1902 if (dispatch_width
!= 8)
1905 unsigned int num_pull_constants
= 0;
1907 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1908 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1910 bool is_live
[uniforms
];
1911 memset(is_live
, 0, sizeof(is_live
));
1913 /* First, we walk through the instructions and do two things:
1915 * 1) Figure out which uniforms are live.
1917 * 2) Find all indirect access of uniform arrays and flag them as needing
1918 * to go into the pull constant buffer.
1920 * Note that we don't move constant-indexed accesses to arrays. No
1921 * testing has been done of the performance impact of this choice.
1923 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1924 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1925 if (inst
->src
[i
].file
!= UNIFORM
)
1928 if (inst
->src
[i
].reladdr
) {
1929 int uniform
= inst
->src
[i
].reg
;
1931 /* If this array isn't already present in the pull constant buffer,
1934 if (pull_constant_loc
[uniform
] == -1) {
1935 assert(param_size
[uniform
]);
1936 for (int j
= 0; j
< param_size
[uniform
]; j
++)
1937 pull_constant_loc
[uniform
+ j
] = num_pull_constants
++;
1940 /* Mark the the one accessed uniform as live */
1941 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1942 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1943 is_live
[constant_nr
] = true;
1948 /* Only allow 16 registers (128 uniform components) as push constants.
1950 * Just demote the end of the list. We could probably do better
1951 * here, demoting things that are rarely used in the program first.
1953 * If changing this value, note the limitation about total_regs in
1956 unsigned int max_push_components
= 16 * 8;
1957 unsigned int num_push_constants
= 0;
1959 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1961 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1962 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1963 /* This UNIFORM register is either dead, or has already been demoted
1964 * to a pull const. Mark it as no longer living in the param[] array.
1966 push_constant_loc
[i
] = -1;
1970 if (num_push_constants
< max_push_components
) {
1971 /* Retain as a push constant. Record the location in the params[]
1974 push_constant_loc
[i
] = num_push_constants
++;
1976 /* Demote to a pull constant. */
1977 push_constant_loc
[i
] = -1;
1978 pull_constant_loc
[i
] = num_pull_constants
++;
1982 stage_prog_data
->nr_params
= num_push_constants
;
1983 stage_prog_data
->nr_pull_params
= num_pull_constants
;
1985 /* Up until now, the param[] array has been indexed by reg + reg_offset
1986 * of UNIFORM registers. Move pull constants into pull_param[] and
1987 * condense param[] to only contain the uniforms we chose to push.
1989 * NOTE: Because we are condensing the params[] array, we know that
1990 * push_constant_loc[i] <= i and we can do it in one smooth loop without
1991 * having to make a copy.
1993 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1994 const gl_constant_value
*value
= stage_prog_data
->param
[i
];
1996 if (pull_constant_loc
[i
] != -1) {
1997 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
1998 } else if (push_constant_loc
[i
] != -1) {
1999 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2005 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2006 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2009 fs_visitor::demote_pull_constants()
2011 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2012 for (int i
= 0; i
< inst
->sources
; i
++) {
2013 if (inst
->src
[i
].file
!= UNIFORM
)
2017 unsigned location
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
2018 if (location
>= uniforms
) /* Out of bounds access */
2021 pull_index
= pull_constant_loc
[location
];
2023 if (pull_index
== -1)
2026 /* Set up the annotation tracking for new generated instructions. */
2027 const fs_builder
ibld(this, block
, inst
);
2028 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2029 fs_reg dst
= vgrf(glsl_type::float_type
);
2031 assert(inst
->src
[i
].stride
== 0);
2033 /* Generate a pull load into dst. */
2034 if (inst
->src
[i
].reladdr
) {
2035 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
2037 *inst
->src
[i
].reladdr
,
2039 inst
->src
[i
].reladdr
= NULL
;
2040 inst
->src
[i
].stride
= 1;
2042 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2043 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
2044 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2045 dst
, fs_reg(index
), offset
);
2046 inst
->src
[i
].set_smear(pull_index
& 3);
2048 brw_mark_surface_used(prog_data
, index
);
2050 /* Rewrite the instruction to use the temporary VGRF. */
2051 inst
->src
[i
].file
= GRF
;
2052 inst
->src
[i
].reg
= dst
.reg
;
2053 inst
->src
[i
].reg_offset
= 0;
2056 invalidate_live_intervals();
2060 fs_visitor::opt_algebraic()
2062 bool progress
= false;
2064 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2065 switch (inst
->opcode
) {
2066 case BRW_OPCODE_MOV
:
2067 if (inst
->src
[0].file
!= IMM
)
2070 if (inst
->saturate
) {
2071 if (inst
->dst
.type
!= inst
->src
[0].type
)
2072 assert(!"unimplemented: saturate mixed types");
2074 if (brw_saturate_immediate(inst
->dst
.type
,
2075 &inst
->src
[0].fixed_hw_reg
)) {
2076 inst
->saturate
= false;
2082 case BRW_OPCODE_MUL
:
2083 if (inst
->src
[1].file
!= IMM
)
2087 if (inst
->src
[1].is_one()) {
2088 inst
->opcode
= BRW_OPCODE_MOV
;
2089 inst
->src
[1] = reg_undef
;
2095 if (inst
->src
[1].is_negative_one()) {
2096 inst
->opcode
= BRW_OPCODE_MOV
;
2097 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2098 inst
->src
[1] = reg_undef
;
2104 if (inst
->src
[1].is_zero()) {
2105 inst
->opcode
= BRW_OPCODE_MOV
;
2106 inst
->src
[0] = inst
->src
[1];
2107 inst
->src
[1] = reg_undef
;
2112 if (inst
->src
[0].file
== IMM
) {
2113 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2114 inst
->opcode
= BRW_OPCODE_MOV
;
2115 inst
->src
[0].fixed_hw_reg
.dw1
.f
*= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
2116 inst
->src
[1] = reg_undef
;
2121 case BRW_OPCODE_ADD
:
2122 if (inst
->src
[1].file
!= IMM
)
2126 if (inst
->src
[1].is_zero()) {
2127 inst
->opcode
= BRW_OPCODE_MOV
;
2128 inst
->src
[1] = reg_undef
;
2133 if (inst
->src
[0].file
== IMM
) {
2134 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2135 inst
->opcode
= BRW_OPCODE_MOV
;
2136 inst
->src
[0].fixed_hw_reg
.dw1
.f
+= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
2137 inst
->src
[1] = reg_undef
;
2143 if (inst
->src
[0].equals(inst
->src
[1])) {
2144 inst
->opcode
= BRW_OPCODE_MOV
;
2145 inst
->src
[1] = reg_undef
;
2150 case BRW_OPCODE_LRP
:
2151 if (inst
->src
[1].equals(inst
->src
[2])) {
2152 inst
->opcode
= BRW_OPCODE_MOV
;
2153 inst
->src
[0] = inst
->src
[1];
2154 inst
->src
[1] = reg_undef
;
2155 inst
->src
[2] = reg_undef
;
2160 case BRW_OPCODE_CMP
:
2161 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2163 inst
->src
[0].negate
&&
2164 inst
->src
[1].is_zero()) {
2165 inst
->src
[0].abs
= false;
2166 inst
->src
[0].negate
= false;
2167 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2172 case BRW_OPCODE_SEL
:
2173 if (inst
->src
[0].equals(inst
->src
[1])) {
2174 inst
->opcode
= BRW_OPCODE_MOV
;
2175 inst
->src
[1] = reg_undef
;
2176 inst
->predicate
= BRW_PREDICATE_NONE
;
2177 inst
->predicate_inverse
= false;
2179 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2180 switch (inst
->conditional_mod
) {
2181 case BRW_CONDITIONAL_LE
:
2182 case BRW_CONDITIONAL_L
:
2183 switch (inst
->src
[1].type
) {
2184 case BRW_REGISTER_TYPE_F
:
2185 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
>= 1.0f
) {
2186 inst
->opcode
= BRW_OPCODE_MOV
;
2187 inst
->src
[1] = reg_undef
;
2188 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2196 case BRW_CONDITIONAL_GE
:
2197 case BRW_CONDITIONAL_G
:
2198 switch (inst
->src
[1].type
) {
2199 case BRW_REGISTER_TYPE_F
:
2200 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
<= 0.0f
) {
2201 inst
->opcode
= BRW_OPCODE_MOV
;
2202 inst
->src
[1] = reg_undef
;
2203 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2215 case BRW_OPCODE_MAD
:
2216 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2217 inst
->opcode
= BRW_OPCODE_MOV
;
2218 inst
->src
[1] = reg_undef
;
2219 inst
->src
[2] = reg_undef
;
2221 } else if (inst
->src
[0].is_zero()) {
2222 inst
->opcode
= BRW_OPCODE_MUL
;
2223 inst
->src
[0] = inst
->src
[2];
2224 inst
->src
[2] = reg_undef
;
2226 } else if (inst
->src
[1].is_one()) {
2227 inst
->opcode
= BRW_OPCODE_ADD
;
2228 inst
->src
[1] = inst
->src
[2];
2229 inst
->src
[2] = reg_undef
;
2231 } else if (inst
->src
[2].is_one()) {
2232 inst
->opcode
= BRW_OPCODE_ADD
;
2233 inst
->src
[2] = reg_undef
;
2235 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2236 inst
->opcode
= BRW_OPCODE_ADD
;
2237 inst
->src
[1].fixed_hw_reg
.dw1
.f
*= inst
->src
[2].fixed_hw_reg
.dw1
.f
;
2238 inst
->src
[2] = reg_undef
;
2242 case SHADER_OPCODE_RCP
: {
2243 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2244 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2245 if (inst
->src
[0].equals(prev
->dst
)) {
2246 inst
->opcode
= SHADER_OPCODE_RSQ
;
2247 inst
->src
[0] = prev
->src
[0];
2253 case SHADER_OPCODE_BROADCAST
:
2254 if (is_uniform(inst
->src
[0])) {
2255 inst
->opcode
= BRW_OPCODE_MOV
;
2257 inst
->force_writemask_all
= true;
2259 } else if (inst
->src
[1].file
== IMM
) {
2260 inst
->opcode
= BRW_OPCODE_MOV
;
2261 inst
->src
[0] = component(inst
->src
[0],
2262 inst
->src
[1].fixed_hw_reg
.dw1
.ud
);
2264 inst
->force_writemask_all
= true;
2273 /* Swap if src[0] is immediate. */
2274 if (progress
&& inst
->is_commutative()) {
2275 if (inst
->src
[0].file
== IMM
) {
2276 fs_reg tmp
= inst
->src
[1];
2277 inst
->src
[1] = inst
->src
[0];
2286 * Optimize sample messages that have constant zero values for the trailing
2287 * texture coordinates. We can just reduce the message length for these
2288 * instructions instead of reserving a register for it. Trailing parameters
2289 * that aren't sent default to zero anyway. This will cause the dead code
2290 * eliminator to remove the MOV instruction that would otherwise be emitted to
2291 * set up the zero value.
2294 fs_visitor::opt_zero_samples()
2296 /* Gen4 infers the texturing opcode based on the message length so we can't
2299 if (devinfo
->gen
< 5)
2302 bool progress
= false;
2304 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2305 if (!inst
->is_tex())
2308 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2310 if (load_payload
->is_head_sentinel() ||
2311 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2314 /* We don't want to remove the message header or the first parameter.
2315 * Removing the first parameter is not allowed, see the Haswell PRM
2316 * volume 7, page 149:
2318 * "Parameter 0 is required except for the sampleinfo message, which
2319 * has no parameter 0"
2321 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2322 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2323 (inst
->exec_size
/ 8) +
2324 inst
->header_size
- 1].is_zero()) {
2325 inst
->mlen
-= inst
->exec_size
/ 8;
2331 invalidate_live_intervals();
2337 * Optimize sample messages which are followed by the final RT write.
2339 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2340 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2341 * final texturing results copied to the framebuffer write payload and modify
2342 * them to write to the framebuffer directly.
2345 fs_visitor::opt_sampler_eot()
2347 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2349 if (stage
!= MESA_SHADER_FRAGMENT
)
2352 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2355 /* FINISHME: It should be possible to implement this optimization when there
2356 * are multiple drawbuffers.
2358 if (key
->nr_color_regions
!= 1)
2361 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2362 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2363 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2364 assert(fb_write
->eot
);
2365 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2367 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2369 /* There wasn't one; nothing to do. */
2370 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2373 /* 3D Sampler » Messages » Message Format
2375 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2376 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2378 if (tex_inst
->opcode
== SHADER_OPCODE_TXS
||
2379 tex_inst
->opcode
== SHADER_OPCODE_SAMPLEINFO
||
2380 tex_inst
->opcode
== SHADER_OPCODE_LOD
||
2381 tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2382 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2385 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2386 * It's very likely to be the previous instruction.
2388 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2389 if (load_payload
->is_head_sentinel() ||
2390 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2393 assert(!tex_inst
->eot
); /* We can't get here twice */
2394 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2396 const fs_builder
ibld(this, block
, tex_inst
);
2398 tex_inst
->offset
|= fb_write
->target
<< 24;
2399 tex_inst
->eot
= true;
2400 tex_inst
->dst
= ibld
.null_reg_ud();
2401 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2403 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2404 * to create a new LOAD_PAYLOAD command with the same sources and a space
2405 * saved for the header. Using a new destination register not only makes sure
2406 * we have enough space, but it will make sure the dead code eliminator kills
2407 * the instruction that this will replace.
2409 if (tex_inst
->header_size
!= 0)
2412 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2413 load_payload
->sources
+ 1);
2414 fs_reg
*new_sources
=
2415 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2417 new_sources
[0] = fs_reg();
2418 for (int i
= 0; i
< load_payload
->sources
; i
++)
2419 new_sources
[i
+1] = load_payload
->src
[i
];
2421 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2422 * requires a lot of information about the sources to appropriately figure
2423 * out the number of registers needed to be used. Given this stage in our
2424 * optimization, we may not have the appropriate GRFs required by
2425 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2426 * manually emit the instruction.
2428 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2429 load_payload
->exec_size
,
2432 load_payload
->sources
+ 1);
2434 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2435 new_load_payload
->header_size
= 1;
2437 tex_inst
->header_size
= 1;
2438 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2439 tex_inst
->src
[0] = send_header
;
2445 fs_visitor::opt_register_renaming()
2447 bool progress
= false;
2450 int remap
[alloc
.count
];
2451 memset(remap
, -1, sizeof(int) * alloc
.count
);
2453 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2454 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2456 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2457 inst
->opcode
== BRW_OPCODE_WHILE
) {
2461 /* Rewrite instruction sources. */
2462 for (int i
= 0; i
< inst
->sources
; i
++) {
2463 if (inst
->src
[i
].file
== GRF
&&
2464 remap
[inst
->src
[i
].reg
] != -1 &&
2465 remap
[inst
->src
[i
].reg
] != inst
->src
[i
].reg
) {
2466 inst
->src
[i
].reg
= remap
[inst
->src
[i
].reg
];
2471 const int dst
= inst
->dst
.reg
;
2474 inst
->dst
.file
== GRF
&&
2475 alloc
.sizes
[inst
->dst
.reg
] == inst
->exec_size
/ 8 &&
2476 !inst
->is_partial_write()) {
2477 if (remap
[dst
] == -1) {
2480 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2481 inst
->dst
.reg
= remap
[dst
];
2484 } else if (inst
->dst
.file
== GRF
&&
2486 remap
[dst
] != dst
) {
2487 inst
->dst
.reg
= remap
[dst
];
2493 invalidate_live_intervals();
2495 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2496 if (delta_xy
[i
].file
== GRF
&& remap
[delta_xy
[i
].reg
] != -1) {
2497 delta_xy
[i
].reg
= remap
[delta_xy
[i
].reg
];
2506 * Remove redundant or useless discard jumps.
2508 * For example, we can eliminate jumps in the following sequence:
2510 * discard-jump (redundant with the next jump)
2511 * discard-jump (useless; jumps to the next instruction)
2515 fs_visitor::opt_redundant_discard_jumps()
2517 bool progress
= false;
2519 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2521 fs_inst
*placeholder_halt
= NULL
;
2522 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2523 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2524 placeholder_halt
= inst
;
2529 if (!placeholder_halt
)
2532 /* Delete any HALTs immediately before the placeholder halt. */
2533 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2534 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2535 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2536 prev
->remove(last_bblock
);
2541 invalidate_live_intervals();
2547 fs_visitor::compute_to_mrf()
2549 bool progress
= false;
2552 /* No MRFs on Gen >= 7. */
2553 if (devinfo
->gen
>= 7)
2556 calculate_live_intervals();
2558 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2562 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2563 inst
->is_partial_write() ||
2564 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2565 inst
->dst
.type
!= inst
->src
[0].type
||
2566 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2567 !inst
->src
[0].is_contiguous() ||
2568 inst
->src
[0].subreg_offset
)
2571 /* Work out which hardware MRF registers are written by this
2574 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2576 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2577 mrf_high
= mrf_low
+ 4;
2578 } else if (inst
->exec_size
== 16) {
2579 mrf_high
= mrf_low
+ 1;
2584 /* Can't compute-to-MRF this GRF if someone else was going to
2587 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2590 /* Found a move of a GRF to a MRF. Let's see if we can go
2591 * rewrite the thing that made this GRF to write into the MRF.
2593 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2594 if (scan_inst
->dst
.file
== GRF
&&
2595 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2596 /* Found the last thing to write our reg we want to turn
2597 * into a compute-to-MRF.
2600 /* If this one instruction didn't populate all the
2601 * channels, bail. We might be able to rewrite everything
2602 * that writes that reg, but it would require smarter
2603 * tracking to delay the rewriting until complete success.
2605 if (scan_inst
->is_partial_write())
2608 /* Things returning more than one register would need us to
2609 * understand coalescing out more than one MOV at a time.
2611 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2614 /* SEND instructions can't have MRF as a destination. */
2615 if (scan_inst
->mlen
)
2618 if (devinfo
->gen
== 6) {
2619 /* gen6 math instructions must have the destination be
2620 * GRF, so no compute-to-MRF for them.
2622 if (scan_inst
->is_math()) {
2627 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2628 /* Found the creator of our MRF's source value. */
2629 scan_inst
->dst
.file
= MRF
;
2630 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2631 scan_inst
->saturate
|= inst
->saturate
;
2632 inst
->remove(block
);
2638 /* We don't handle control flow here. Most computation of
2639 * values that end up in MRFs are shortly before the MRF
2642 if (block
->start() == scan_inst
)
2645 /* You can't read from an MRF, so if someone else reads our
2646 * MRF's source GRF that we wanted to rewrite, that stops us.
2648 bool interfered
= false;
2649 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2650 if (scan_inst
->src
[i
].file
== GRF
&&
2651 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2652 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2659 if (scan_inst
->dst
.file
== MRF
) {
2660 /* If somebody else writes our MRF here, we can't
2661 * compute-to-MRF before that.
2663 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2666 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2667 scan_mrf_high
= scan_mrf_low
+ 4;
2668 } else if (scan_inst
->exec_size
== 16) {
2669 scan_mrf_high
= scan_mrf_low
+ 1;
2671 scan_mrf_high
= scan_mrf_low
;
2674 if (mrf_low
== scan_mrf_low
||
2675 mrf_low
== scan_mrf_high
||
2676 mrf_high
== scan_mrf_low
||
2677 mrf_high
== scan_mrf_high
) {
2682 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2683 /* Found a SEND instruction, which means that there are
2684 * live values in MRFs from base_mrf to base_mrf +
2685 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2688 if (mrf_low
>= scan_inst
->base_mrf
&&
2689 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2692 if (mrf_high
>= scan_inst
->base_mrf
&&
2693 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2701 invalidate_live_intervals();
2707 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2708 * flow. We could probably do better here with some form of divergence
2712 fs_visitor::eliminate_find_live_channel()
2714 bool progress
= false;
2717 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2718 switch (inst
->opcode
) {
2724 case BRW_OPCODE_ENDIF
:
2725 case BRW_OPCODE_WHILE
:
2729 case FS_OPCODE_DISCARD_JUMP
:
2730 /* This can potentially make control flow non-uniform until the end
2735 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2737 inst
->opcode
= BRW_OPCODE_MOV
;
2738 inst
->src
[0] = fs_reg(0u);
2740 inst
->force_writemask_all
= true;
2754 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2755 * instructions to FS_OPCODE_REP_FB_WRITE.
2758 fs_visitor::emit_repclear_shader()
2760 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2762 int color_mrf
= base_mrf
+ 2;
2764 fs_inst
*mov
= bld
.exec_all().group(4, 0)
2765 .MOV(brw_message_reg(color_mrf
),
2766 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2769 if (key
->nr_color_regions
== 1) {
2770 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2771 write
->saturate
= key
->clamp_fragment_color
;
2772 write
->base_mrf
= color_mrf
;
2774 write
->header_size
= 0;
2777 assume(key
->nr_color_regions
> 0);
2778 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2779 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2780 write
->saturate
= key
->clamp_fragment_color
;
2781 write
->base_mrf
= base_mrf
;
2783 write
->header_size
= 2;
2791 assign_constant_locations();
2792 assign_curb_setup();
2794 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2795 assert(mov
->src
[0].file
== HW_REG
);
2796 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].fixed_hw_reg
.nr
, 0);
2800 * Walks through basic blocks, looking for repeated MRF writes and
2801 * removing the later ones.
2804 fs_visitor::remove_duplicate_mrf_writes()
2806 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2807 bool progress
= false;
2809 /* Need to update the MRF tracking for compressed instructions. */
2810 if (dispatch_width
== 16)
2813 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2815 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2816 if (inst
->is_control_flow()) {
2817 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2820 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2821 inst
->dst
.file
== MRF
) {
2822 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2823 if (prev_inst
&& inst
->equals(prev_inst
)) {
2824 inst
->remove(block
);
2830 /* Clear out the last-write records for MRFs that were overwritten. */
2831 if (inst
->dst
.file
== MRF
) {
2832 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2835 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2836 /* Found a SEND instruction, which will include two or fewer
2837 * implied MRF writes. We could do better here.
2839 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2840 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2844 /* Clear out any MRF move records whose sources got overwritten. */
2845 if (inst
->dst
.file
== GRF
) {
2846 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2847 if (last_mrf_move
[i
] &&
2848 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2849 last_mrf_move
[i
] = NULL
;
2854 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2855 inst
->dst
.file
== MRF
&&
2856 inst
->src
[0].file
== GRF
&&
2857 !inst
->is_partial_write()) {
2858 last_mrf_move
[inst
->dst
.reg
] = inst
;
2863 invalidate_live_intervals();
2869 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2871 /* Clear the flag for registers that actually got read (as expected). */
2872 for (int i
= 0; i
< inst
->sources
; i
++) {
2874 if (inst
->src
[i
].file
== GRF
) {
2875 grf
= inst
->src
[i
].reg
;
2876 } else if (inst
->src
[i
].file
== HW_REG
&&
2877 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
2878 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
2883 if (grf
>= first_grf
&&
2884 grf
< first_grf
+ grf_len
) {
2885 deps
[grf
- first_grf
] = false;
2886 if (inst
->exec_size
== 16)
2887 deps
[grf
- first_grf
+ 1] = false;
2893 * Implements this workaround for the original 965:
2895 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2896 * check for post destination dependencies on this instruction, software
2897 * must ensure that there is no destination hazard for the case of ‘write
2898 * followed by a posted write’ shown in the following example.
2901 * 2. send r3.xy <rest of send instruction>
2904 * Due to no post-destination dependency check on the ‘send’, the above
2905 * code sequence could have two instructions (1 and 2) in flight at the
2906 * same time that both consider ‘r3’ as the target of their final writes.
2909 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2912 int write_len
= inst
->regs_written
;
2913 int first_write_grf
= inst
->dst
.reg
;
2914 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2915 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2917 memset(needs_dep
, false, sizeof(needs_dep
));
2918 memset(needs_dep
, true, write_len
);
2920 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2922 /* Walk backwards looking for writes to registers we're writing which
2923 * aren't read since being written. If we hit the start of the program,
2924 * we assume that there are no outstanding dependencies on entry to the
2927 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2928 /* If we hit control flow, assume that there *are* outstanding
2929 * dependencies, and force their cleanup before our instruction.
2931 if (block
->start() == scan_inst
) {
2932 for (int i
= 0; i
< write_len
; i
++) {
2934 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
2935 first_write_grf
+ i
);
2940 /* We insert our reads as late as possible on the assumption that any
2941 * instruction but a MOV that might have left us an outstanding
2942 * dependency has more latency than a MOV.
2944 if (scan_inst
->dst
.file
== GRF
) {
2945 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2946 int reg
= scan_inst
->dst
.reg
+ i
;
2948 if (reg
>= first_write_grf
&&
2949 reg
< first_write_grf
+ write_len
&&
2950 needs_dep
[reg
- first_write_grf
]) {
2951 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
2952 needs_dep
[reg
- first_write_grf
] = false;
2953 if (scan_inst
->exec_size
== 16)
2954 needs_dep
[reg
- first_write_grf
+ 1] = false;
2959 /* Clear the flag for registers that actually got read (as expected). */
2960 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2962 /* Continue the loop only if we haven't resolved all the dependencies */
2964 for (i
= 0; i
< write_len
; i
++) {
2974 * Implements this workaround for the original 965:
2976 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2977 * used as a destination register until after it has been sourced by an
2978 * instruction with a different destination register.
2981 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
2983 int write_len
= inst
->regs_written
;
2984 int first_write_grf
= inst
->dst
.reg
;
2985 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2986 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2988 memset(needs_dep
, false, sizeof(needs_dep
));
2989 memset(needs_dep
, true, write_len
);
2990 /* Walk forwards looking for writes to registers we're writing which aren't
2991 * read before being written.
2993 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
2994 /* If we hit control flow, force resolve all remaining dependencies. */
2995 if (block
->end() == scan_inst
) {
2996 for (int i
= 0; i
< write_len
; i
++) {
2998 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
2999 first_write_grf
+ i
);
3004 /* Clear the flag for registers that actually got read (as expected). */
3005 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3007 /* We insert our reads as late as possible since they're reading the
3008 * result of a SEND, which has massive latency.
3010 if (scan_inst
->dst
.file
== GRF
&&
3011 scan_inst
->dst
.reg
>= first_write_grf
&&
3012 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
3013 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
3014 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3015 scan_inst
->dst
.reg
);
3016 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
3019 /* Continue the loop only if we haven't resolved all the dependencies */
3021 for (i
= 0; i
< write_len
; i
++) {
3031 fs_visitor::insert_gen4_send_dependency_workarounds()
3033 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3036 bool progress
= false;
3038 /* Note that we're done with register allocation, so GRF fs_regs always
3039 * have a .reg_offset of 0.
3042 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3043 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
3044 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3045 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3051 invalidate_live_intervals();
3055 * Turns the generic expression-style uniform pull constant load instruction
3056 * into a hardware-specific series of instructions for loading a pull
3059 * The expression style allows the CSE pass before this to optimize out
3060 * repeated loads from the same offset, and gives the pre-register-allocation
3061 * scheduling full flexibility, while the conversion to native instructions
3062 * allows the post-register-allocation scheduler the best information
3065 * Note that execution masking for setting up pull constant loads is special:
3066 * the channels that need to be written are unrelated to the current execution
3067 * mask, since a later instruction will use one of the result channels as a
3068 * source operand for all 8 or 16 of its channels.
3071 fs_visitor::lower_uniform_pull_constant_loads()
3073 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3074 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3077 if (devinfo
->gen
>= 7) {
3078 /* The offset arg before was a vec4-aligned byte offset. We need to
3079 * turn it into a dword offset.
3081 fs_reg const_offset_reg
= inst
->src
[1];
3082 assert(const_offset_reg
.file
== IMM
&&
3083 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3084 const_offset_reg
.fixed_hw_reg
.dw1
.ud
/= 4;
3086 fs_reg payload
, offset
;
3087 if (devinfo
->gen
>= 9) {
3088 /* We have to use a message header on Skylake to get SIMD4x2
3089 * mode. Reserve space for the register.
3091 offset
= payload
= fs_reg(GRF
, alloc
.allocate(2));
3092 offset
.reg_offset
++;
3095 offset
= payload
= fs_reg(GRF
, alloc
.allocate(1));
3099 /* This is actually going to be a MOV, but since only the first dword
3100 * is accessed, we have a special opcode to do just that one. Note
3101 * that this needs to be an operation that will be considered a def
3102 * by live variable analysis, or register allocation will explode.
3104 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3105 8, offset
, const_offset_reg
);
3106 setup
->force_writemask_all
= true;
3108 setup
->ir
= inst
->ir
;
3109 setup
->annotation
= inst
->annotation
;
3110 inst
->insert_before(block
, setup
);
3112 /* Similarly, this will only populate the first 4 channels of the
3113 * result register (since we only use smear values from 0-3), but we
3114 * don't tell the optimizer.
3116 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3117 inst
->src
[1] = payload
;
3118 inst
->base_mrf
= -1;
3120 invalidate_live_intervals();
3122 /* Before register allocation, we didn't tell the scheduler about the
3123 * MRF we use. We know it's safe to use this MRF because nothing
3124 * else does except for register spill/unspill, which generates and
3125 * uses its MRF within a single IR instruction.
3127 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3134 fs_visitor::lower_load_payload()
3136 bool progress
= false;
3138 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3139 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3142 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== GRF
);
3143 assert(inst
->saturate
== false);
3144 fs_reg dst
= inst
->dst
;
3146 /* Get rid of COMPR4. We'll add it back in if we need it */
3147 if (dst
.file
== MRF
)
3148 dst
.reg
= dst
.reg
& ~BRW_MRF_COMPR4
;
3150 const fs_builder
ibld(this, block
, inst
);
3151 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3153 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3154 if (inst
->src
[i
].file
!= BAD_FILE
) {
3155 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3156 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3157 hbld
.MOV(mov_dst
, mov_src
);
3159 dst
= offset(dst
, hbld
, 1);
3162 if (inst
->dst
.file
== MRF
&& (inst
->dst
.reg
& BRW_MRF_COMPR4
) &&
3163 inst
->exec_size
> 8) {
3164 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3165 * a straightforward copy. Instead, the result of the
3166 * LOAD_PAYLOAD is treated as interleaved and the first four
3167 * non-header sources are unpacked as:
3178 * This is used for gen <= 5 fb writes.
3180 assert(inst
->exec_size
== 16);
3181 assert(inst
->header_size
+ 4 <= inst
->sources
);
3182 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3183 if (inst
->src
[i
].file
!= BAD_FILE
) {
3184 if (devinfo
->has_compr4
) {
3185 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3186 compr4_dst
.reg
|= BRW_MRF_COMPR4
;
3187 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3189 /* Platform doesn't have COMPR4. We have to fake it */
3190 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3191 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3193 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3200 /* The loop above only ever incremented us through the first set
3201 * of 4 registers. However, thanks to the magic of COMPR4, we
3202 * actually wrote to the first 8 registers, so we need to take
3203 * that into account now.
3207 /* The COMPR4 code took care of the first 4 sources. We'll let
3208 * the regular path handle any remaining sources. Yes, we are
3209 * modifying the instruction but we're about to delete it so
3210 * this really doesn't hurt anything.
3212 inst
->header_size
+= 4;
3215 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3216 if (inst
->src
[i
].file
!= BAD_FILE
)
3217 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3218 dst
= offset(dst
, ibld
, 1);
3221 inst
->remove(block
);
3226 invalidate_live_intervals();
3232 fs_visitor::lower_integer_multiplication()
3234 bool progress
= false;
3236 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3237 const fs_builder
ibld(this, block
, inst
);
3239 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3240 if (inst
->dst
.is_accumulator() ||
3241 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3242 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3245 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3246 * operation directly, but CHV/BXT cannot.
3248 if (devinfo
->gen
>= 8 &&
3249 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3252 if (inst
->src
[1].file
== IMM
&&
3253 inst
->src
[1].fixed_hw_reg
.dw1
.ud
< (1 << 16)) {
3254 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3255 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3258 * If multiplying by an immediate value that fits in 16-bits, do a
3259 * single MUL instruction with that value in the proper location.
3261 if (devinfo
->gen
< 7) {
3262 fs_reg
imm(GRF
, alloc
.allocate(dispatch_width
/ 8),
3264 ibld
.MOV(imm
, inst
->src
[1]);
3265 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3267 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3270 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3271 * do 32-bit integer multiplication in one instruction, but instead
3272 * must do a sequence (which actually calculates a 64-bit result):
3274 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3275 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3276 * mov(8) g2<1>D acc0<8,8,1>D
3278 * But on Gen > 6, the ability to use second accumulator register
3279 * (acc1) for non-float data types was removed, preventing a simple
3280 * implementation in SIMD16. A 16-channel result can be calculated by
3281 * executing the three instructions twice in SIMD8, once with quarter
3282 * control of 1Q for the first eight channels and again with 2Q for
3283 * the second eight channels.
3285 * Which accumulator register is implicitly accessed (by AccWrEnable
3286 * for instance) is determined by the quarter control. Unfortunately
3287 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3288 * implicit accumulator access by an instruction with 2Q will access
3289 * acc1 regardless of whether the data type is usable in acc1.
3291 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3292 * integer data types.
3294 * Since we only want the low 32-bits of the result, we can do two
3295 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3296 * adjust the high result and add them (like the mach is doing):
3298 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3299 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3300 * shl(8) g9<1>D g8<8,8,1>D 16D
3301 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3303 * We avoid the shl instruction by realizing that we only want to add
3304 * the low 16-bits of the "high" result to the high 16-bits of the
3305 * "low" result and using proper regioning on the add:
3307 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3308 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3309 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3311 * Since it does not use the (single) accumulator register, we can
3312 * schedule multi-component multiplications much better.
3315 fs_reg orig_dst
= inst
->dst
;
3316 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3317 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
3320 fs_reg low
= inst
->dst
;
3321 fs_reg
high(GRF
, alloc
.allocate(dispatch_width
/ 8),
3324 if (devinfo
->gen
>= 7) {
3325 fs_reg src1_0_w
= inst
->src
[1];
3326 fs_reg src1_1_w
= inst
->src
[1];
3328 if (inst
->src
[1].file
== IMM
) {
3329 src1_0_w
.fixed_hw_reg
.dw1
.ud
&= 0xffff;
3330 src1_1_w
.fixed_hw_reg
.dw1
.ud
>>= 16;
3332 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3333 if (src1_0_w
.stride
!= 0) {
3334 assert(src1_0_w
.stride
== 1);
3335 src1_0_w
.stride
= 2;
3338 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3339 if (src1_1_w
.stride
!= 0) {
3340 assert(src1_1_w
.stride
== 1);
3341 src1_1_w
.stride
= 2;
3343 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3345 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3346 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3348 fs_reg src0_0_w
= inst
->src
[0];
3349 fs_reg src0_1_w
= inst
->src
[0];
3351 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3352 if (src0_0_w
.stride
!= 0) {
3353 assert(src0_0_w
.stride
== 1);
3354 src0_0_w
.stride
= 2;
3357 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3358 if (src0_1_w
.stride
!= 0) {
3359 assert(src0_1_w
.stride
== 1);
3360 src0_1_w
.stride
= 2;
3362 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3364 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3365 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3368 fs_reg dst
= inst
->dst
;
3369 dst
.type
= BRW_REGISTER_TYPE_UW
;
3370 dst
.subreg_offset
= 2;
3373 high
.type
= BRW_REGISTER_TYPE_UW
;
3376 low
.type
= BRW_REGISTER_TYPE_UW
;
3377 low
.subreg_offset
= 2;
3380 ibld
.ADD(dst
, low
, high
);
3382 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3383 set_condmod(inst
->conditional_mod
,
3384 ibld
.MOV(orig_dst
, inst
->dst
));
3388 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3389 /* Should have been lowered to 8-wide. */
3390 assert(inst
->exec_size
<= 8);
3391 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3393 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3394 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3396 if (devinfo
->gen
>= 8) {
3397 /* Until Gen8, integer multiplies read 32-bits from one source,
3398 * and 16-bits from the other, and relying on the MACH instruction
3399 * to generate the high bits of the result.
3401 * On Gen8, the multiply instruction does a full 32x32-bit
3402 * multiply, but in order to do a 64-bit multiply we can simulate
3403 * the previous behavior and then use a MACH instruction.
3405 * FINISHME: Don't use source modifiers on src1.
3407 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3408 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3409 mul
->src
[1].type
= (type_is_signed(mul
->src
[1].type
) ?
3410 BRW_REGISTER_TYPE_W
: BRW_REGISTER_TYPE_UW
);
3411 mul
->src
[1].stride
*= 2;
3413 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3414 inst
->force_sechalf
) {
3415 /* Among other things the quarter control bits influence which
3416 * accumulator register is used by the hardware for instructions
3417 * that access the accumulator implicitly (e.g. MACH). A
3418 * second-half instruction would normally map to acc1, which
3419 * doesn't exist on Gen7 and up (the hardware does emulate it for
3420 * floating-point instructions *only* by taking advantage of the
3421 * extra precision of acc0 not normally used for floating point
3424 * HSW and up are careful enough not to try to access an
3425 * accumulator register that doesn't exist, but on earlier Gen7
3426 * hardware we need to make sure that the quarter control bits are
3427 * zero to avoid non-deterministic behaviour and emit an extra MOV
3428 * to get the result masked correctly according to the current
3431 mach
->force_sechalf
= false;
3432 mach
->force_writemask_all
= true;
3433 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3434 ibld
.MOV(inst
->dst
, mach
->dst
);
3440 inst
->remove(block
);
3445 invalidate_live_intervals();
3451 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3452 fs_reg
*dst
, fs_reg color
, unsigned components
)
3454 if (key
->clamp_fragment_color
) {
3455 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3456 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3458 for (unsigned i
= 0; i
< components
; i
++)
3460 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3465 for (unsigned i
= 0; i
< components
; i
++)
3466 dst
[i
] = offset(color
, bld
, i
);
3470 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3471 const brw_wm_prog_data
*prog_data
,
3472 const brw_wm_prog_key
*key
,
3473 const fs_visitor::thread_payload
&payload
)
3475 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3476 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3477 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3478 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3479 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3480 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3481 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3482 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3483 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3484 const unsigned components
=
3485 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].fixed_hw_reg
.dw1
.ud
;
3487 /* We can potentially have a message length of up to 15, so we have to set
3488 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3491 int header_size
= 2, payload_header_size
;
3492 unsigned length
= 0;
3494 /* From the Sandy Bridge PRM, volume 4, page 198:
3496 * "Dispatched Pixel Enables. One bit per pixel indicating
3497 * which pixels were originally enabled when the thread was
3498 * dispatched. This field is only required for the end-of-
3499 * thread message and on all dual-source messages."
3501 if (devinfo
->gen
>= 6 &&
3502 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3503 color1
.file
== BAD_FILE
&&
3504 key
->nr_color_regions
== 1) {
3508 if (header_size
!= 0) {
3509 assert(header_size
== 2);
3510 /* Allocate 2 registers for a header */
3514 if (payload
.aa_dest_stencil_reg
) {
3515 sources
[length
] = fs_reg(GRF
, bld
.shader
->alloc
.allocate(1));
3516 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3517 .MOV(sources
[length
],
3518 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3522 if (prog_data
->uses_omask
) {
3523 sources
[length
] = fs_reg(GRF
, bld
.shader
->alloc
.allocate(1),
3524 BRW_REGISTER_TYPE_UD
);
3526 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3527 * relevant. Since it's unsigned single words one vgrf is always
3528 * 16-wide, but only the lower or higher 8 channels will be used by the
3529 * hardware when doing a SIMD8 write depending on whether we have
3530 * selected the subspans for the first or second half respectively.
3532 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3533 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3534 sample_mask
.stride
*= 2;
3536 bld
.exec_all().annotate("FB write oMask")
3537 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3538 inst
->force_sechalf
),
3543 payload_header_size
= length
;
3545 if (src0_alpha
.file
!= BAD_FILE
) {
3546 /* FIXME: This is being passed at the wrong location in the payload and
3547 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3548 * It's supposed to be immediately before oMask but there seems to be no
3549 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3550 * requires header sources to form a contiguous segment at the beginning
3551 * of the message and src0_alpha has per-channel semantics.
3553 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3557 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3560 if (color1
.file
!= BAD_FILE
) {
3561 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3565 if (src_depth
.file
!= BAD_FILE
) {
3566 sources
[length
] = src_depth
;
3570 if (dst_depth
.file
!= BAD_FILE
) {
3571 sources
[length
] = dst_depth
;
3575 if (src_stencil
.file
!= BAD_FILE
) {
3576 assert(devinfo
->gen
>= 9);
3577 assert(bld
.dispatch_width() != 16);
3579 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3580 bld
.exec_all().annotate("FB write OS")
3581 .emit(FS_OPCODE_PACK_STENCIL_REF
, sources
[length
],
3582 retype(src_stencil
, BRW_REGISTER_TYPE_UB
));
3587 if (devinfo
->gen
>= 7) {
3588 /* Send from the GRF */
3589 fs_reg payload
= fs_reg(GRF
, -1, BRW_REGISTER_TYPE_F
);
3590 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3591 payload
.reg
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3592 load
->dst
= payload
;
3594 inst
->src
[0] = payload
;
3595 inst
->resize_sources(1);
3596 inst
->base_mrf
= -1;
3598 /* Send from the MRF */
3599 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3600 sources
, length
, payload_header_size
);
3602 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3603 * will do this for us if we just give it a COMPR4 destination.
3605 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3606 load
->dst
.reg
|= BRW_MRF_COMPR4
;
3608 inst
->resize_sources(0);
3612 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3613 inst
->mlen
= load
->regs_written
;
3614 inst
->header_size
= header_size
;
3618 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3619 const fs_reg
&coordinate
,
3620 const fs_reg
&shadow_c
,
3621 const fs_reg
&lod
, const fs_reg
&lod2
,
3622 const fs_reg
&sampler
,
3623 unsigned coord_components
,
3624 unsigned grad_components
)
3626 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3627 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3628 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3629 fs_reg msg_end
= msg_begin
;
3632 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3634 for (unsigned i
= 0; i
< coord_components
; i
++)
3635 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3636 offset(coordinate
, bld
, i
));
3638 msg_end
= offset(msg_end
, bld
, coord_components
);
3640 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3641 * require all three components to be present and zero if they are unused.
3643 if (coord_components
> 0 &&
3644 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3645 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3646 for (unsigned i
= coord_components
; i
< 3; i
++)
3647 bld
.MOV(offset(msg_end
, bld
, i
), fs_reg(0.0f
));
3649 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3652 if (op
== SHADER_OPCODE_TXD
) {
3653 /* TXD unsupported in SIMD16 mode. */
3654 assert(bld
.dispatch_width() == 8);
3656 /* the slots for u and v are always present, but r is optional */
3657 if (coord_components
< 2)
3658 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3661 * dPdx = dudx, dvdx, drdx
3662 * dPdy = dudy, dvdy, drdy
3664 * 1-arg: Does not exist.
3666 * 2-arg: dudx dvdx dudy dvdy
3667 * dPdx.x dPdx.y dPdy.x dPdy.y
3670 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3671 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3672 * m5 m6 m7 m8 m9 m10
3674 for (unsigned i
= 0; i
< grad_components
; i
++)
3675 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3677 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3679 for (unsigned i
= 0; i
< grad_components
; i
++)
3680 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3682 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3686 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3687 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3689 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3690 bld
.dispatch_width() == 16);
3692 const brw_reg_type type
=
3693 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3694 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3695 bld
.MOV(retype(msg_end
, type
), lod
);
3696 msg_end
= offset(msg_end
, bld
, 1);
3699 if (shadow_c
.file
!= BAD_FILE
) {
3700 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3701 /* There's no plain shadow compare message, so we use shadow
3702 * compare with a bias of 0.0.
3704 bld
.MOV(msg_end
, fs_reg(0.0f
));
3705 msg_end
= offset(msg_end
, bld
, 1);
3708 bld
.MOV(msg_end
, shadow_c
);
3709 msg_end
= offset(msg_end
, bld
, 1);
3713 inst
->src
[0] = reg_undef
;
3714 inst
->src
[1] = sampler
;
3715 inst
->resize_sources(2);
3716 inst
->base_mrf
= msg_begin
.reg
;
3717 inst
->mlen
= msg_end
.reg
- msg_begin
.reg
;
3718 inst
->header_size
= 1;
3722 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3724 const fs_reg
&shadow_c
,
3725 fs_reg lod
, fs_reg lod2
,
3726 const fs_reg
&sample_index
,
3727 const fs_reg
&sampler
,
3728 const fs_reg
&offset_value
,
3729 unsigned coord_components
,
3730 unsigned grad_components
)
3732 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3733 fs_reg msg_coords
= message
;
3734 unsigned header_size
= 0;
3736 if (offset_value
.file
!= BAD_FILE
) {
3737 /* The offsets set up by the visitor are in the m1 header, so we can't
3744 for (unsigned i
= 0; i
< coord_components
; i
++) {
3745 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3746 coordinate
= offset(coordinate
, bld
, 1);
3748 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3749 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3751 if (shadow_c
.file
!= BAD_FILE
) {
3752 fs_reg msg_shadow
= msg_lod
;
3753 bld
.MOV(msg_shadow
, shadow_c
);
3754 msg_lod
= offset(msg_shadow
, bld
, 1);
3759 case SHADER_OPCODE_TXL
:
3761 bld
.MOV(msg_lod
, lod
);
3762 msg_end
= offset(msg_lod
, bld
, 1);
3764 case SHADER_OPCODE_TXD
:
3767 * dPdx = dudx, dvdx, drdx
3768 * dPdy = dudy, dvdy, drdy
3770 * Load up these values:
3771 * - dudx dudy dvdx dvdy drdx drdy
3772 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3775 for (unsigned i
= 0; i
< grad_components
; i
++) {
3776 bld
.MOV(msg_end
, lod
);
3777 lod
= offset(lod
, bld
, 1);
3778 msg_end
= offset(msg_end
, bld
, 1);
3780 bld
.MOV(msg_end
, lod2
);
3781 lod2
= offset(lod2
, bld
, 1);
3782 msg_end
= offset(msg_end
, bld
, 1);
3785 case SHADER_OPCODE_TXS
:
3786 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3787 bld
.MOV(msg_lod
, lod
);
3788 msg_end
= offset(msg_lod
, bld
, 1);
3790 case SHADER_OPCODE_TXF
:
3791 msg_lod
= offset(msg_coords
, bld
, 3);
3792 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3793 msg_end
= offset(msg_lod
, bld
, 1);
3795 case SHADER_OPCODE_TXF_CMS
:
3796 msg_lod
= offset(msg_coords
, bld
, 3);
3798 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u));
3800 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3801 msg_end
= offset(msg_lod
, bld
, 2);
3808 inst
->src
[0] = reg_undef
;
3809 inst
->src
[1] = sampler
;
3810 inst
->resize_sources(2);
3811 inst
->base_mrf
= message
.reg
;
3812 inst
->mlen
= msg_end
.reg
- message
.reg
;
3813 inst
->header_size
= header_size
;
3815 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3816 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3820 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3822 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3825 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
3829 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3831 const fs_reg
&shadow_c
,
3832 fs_reg lod
, fs_reg lod2
,
3833 const fs_reg
&sample_index
,
3834 const fs_reg
&mcs
, const fs_reg
&sampler
,
3835 fs_reg offset_value
,
3836 unsigned coord_components
,
3837 unsigned grad_components
)
3839 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3840 int reg_width
= bld
.dispatch_width() / 8;
3841 unsigned header_size
= 0, length
= 0;
3842 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3843 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3844 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3846 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3847 offset_value
.file
!= BAD_FILE
||
3848 is_high_sampler(devinfo
, sampler
)) {
3849 /* For general texture offsets (no txf workaround), we need a header to
3850 * put them in. Note that we're only reserving space for it in the
3851 * message payload as it will be initialized implicitly by the
3854 * TG4 needs to place its channel select in the header, for interaction
3855 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3856 * larger sampler numbers we need to offset the Sampler State Pointer in
3860 sources
[0] = fs_reg();
3864 if (shadow_c
.file
!= BAD_FILE
) {
3865 bld
.MOV(sources
[length
], shadow_c
);
3869 bool coordinate_done
= false;
3871 /* The sampler can only meaningfully compute LOD for fragment shader
3872 * messages. For all other stages, we change the opcode to TXL and
3873 * hardcode the LOD to 0.
3875 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3876 op
== SHADER_OPCODE_TEX
) {
3877 op
= SHADER_OPCODE_TXL
;
3881 /* Set up the LOD info */
3884 case SHADER_OPCODE_TXL
:
3885 bld
.MOV(sources
[length
], lod
);
3888 case SHADER_OPCODE_TXD
:
3889 /* TXD should have been lowered in SIMD16 mode. */
3890 assert(bld
.dispatch_width() == 8);
3892 /* Load dPdx and the coordinate together:
3893 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3895 for (unsigned i
= 0; i
< coord_components
; i
++) {
3896 bld
.MOV(sources
[length
], coordinate
);
3897 coordinate
= offset(coordinate
, bld
, 1);
3900 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3901 * only derivatives for (u, v, r).
3903 if (i
< grad_components
) {
3904 bld
.MOV(sources
[length
], lod
);
3905 lod
= offset(lod
, bld
, 1);
3908 bld
.MOV(sources
[length
], lod2
);
3909 lod2
= offset(lod2
, bld
, 1);
3914 coordinate_done
= true;
3916 case SHADER_OPCODE_TXS
:
3917 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
3920 case SHADER_OPCODE_TXF
:
3921 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
3922 * On Gen9 they are u, v, lod, r
3924 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3925 coordinate
= offset(coordinate
, bld
, 1);
3928 if (devinfo
->gen
>= 9) {
3929 if (coord_components
>= 2) {
3930 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3931 coordinate
= offset(coordinate
, bld
, 1);
3936 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
3939 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
3940 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3941 coordinate
= offset(coordinate
, bld
, 1);
3945 coordinate_done
= true;
3947 case SHADER_OPCODE_TXF_CMS
:
3948 case SHADER_OPCODE_TXF_CMS_W
:
3949 case SHADER_OPCODE_TXF_UMS
:
3950 case SHADER_OPCODE_TXF_MCS
:
3951 if (op
== SHADER_OPCODE_TXF_UMS
||
3952 op
== SHADER_OPCODE_TXF_CMS
||
3953 op
== SHADER_OPCODE_TXF_CMS_W
) {
3954 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
3958 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
3959 /* Data from the multisample control surface. */
3960 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
3963 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
3966 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
3967 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
3970 offset(mcs
, bld
, 1));
3975 /* There is no offsetting for this message; just copy in the integer
3976 * texture coordinates.
3978 for (unsigned i
= 0; i
< coord_components
; i
++) {
3979 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3980 coordinate
= offset(coordinate
, bld
, 1);
3984 coordinate_done
= true;
3986 case SHADER_OPCODE_TG4_OFFSET
:
3987 /* gather4_po_c should have been lowered in SIMD16 mode. */
3988 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
3990 /* More crazy intermixing */
3991 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
3992 bld
.MOV(sources
[length
], coordinate
);
3993 coordinate
= offset(coordinate
, bld
, 1);
3997 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
3998 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
3999 offset_value
= offset(offset_value
, bld
, 1);
4003 if (coord_components
== 3) { /* r if present */
4004 bld
.MOV(sources
[length
], coordinate
);
4005 coordinate
= offset(coordinate
, bld
, 1);
4009 coordinate_done
= true;
4015 /* Set up the coordinate (except for cases where it was done above) */
4016 if (!coordinate_done
) {
4017 for (unsigned i
= 0; i
< coord_components
; i
++) {
4018 bld
.MOV(sources
[length
], coordinate
);
4019 coordinate
= offset(coordinate
, bld
, 1);
4026 mlen
= length
* reg_width
- header_size
;
4028 mlen
= length
* reg_width
;
4030 const fs_reg src_payload
= fs_reg(GRF
, bld
.shader
->alloc
.allocate(mlen
),
4031 BRW_REGISTER_TYPE_F
);
4032 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4034 /* Generate the SEND. */
4036 inst
->src
[0] = src_payload
;
4037 inst
->src
[1] = sampler
;
4038 inst
->resize_sources(2);
4039 inst
->base_mrf
= -1;
4041 inst
->header_size
= header_size
;
4043 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4044 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4048 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4050 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4051 const fs_reg
&coordinate
= inst
->src
[0];
4052 const fs_reg
&shadow_c
= inst
->src
[1];
4053 const fs_reg
&lod
= inst
->src
[2];
4054 const fs_reg
&lod2
= inst
->src
[3];
4055 const fs_reg
&sample_index
= inst
->src
[4];
4056 const fs_reg
&mcs
= inst
->src
[5];
4057 const fs_reg
&sampler
= inst
->src
[6];
4058 const fs_reg
&offset_value
= inst
->src
[7];
4059 assert(inst
->src
[8].file
== IMM
&& inst
->src
[9].file
== IMM
);
4060 const unsigned coord_components
= inst
->src
[8].fixed_hw_reg
.dw1
.ud
;
4061 const unsigned grad_components
= inst
->src
[9].fixed_hw_reg
.dw1
.ud
;
4063 if (devinfo
->gen
>= 7) {
4064 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4065 shadow_c
, lod
, lod2
, sample_index
,
4066 mcs
, sampler
, offset_value
,
4067 coord_components
, grad_components
);
4068 } else if (devinfo
->gen
>= 5) {
4069 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4070 shadow_c
, lod
, lod2
, sample_index
,
4071 sampler
, offset_value
,
4072 coord_components
, grad_components
);
4074 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4075 shadow_c
, lod
, lod2
, sampler
,
4076 coord_components
, grad_components
);
4081 * Initialize the header present in some typed and untyped surface
4085 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4087 fs_builder ubld
= bld
.exec_all().group(8, 0);
4088 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4089 ubld
.MOV(dst
, fs_reg(0));
4090 ubld
.MOV(component(dst
, 7), sample_mask
);
4095 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4096 const fs_reg
&sample_mask
)
4098 /* Get the logical send arguments. */
4099 const fs_reg
&addr
= inst
->src
[0];
4100 const fs_reg
&src
= inst
->src
[1];
4101 const fs_reg
&surface
= inst
->src
[2];
4102 const UNUSED fs_reg
&dims
= inst
->src
[3];
4103 const fs_reg
&arg
= inst
->src
[4];
4105 /* Calculate the total number of components of the payload. */
4106 const unsigned addr_sz
= inst
->components_read(0);
4107 const unsigned src_sz
= inst
->components_read(1);
4108 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4109 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4111 /* Allocate space for the payload. */
4112 fs_reg
*const components
= new fs_reg
[sz
];
4113 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4116 /* Construct the payload. */
4118 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4120 for (unsigned i
= 0; i
< addr_sz
; i
++)
4121 components
[n
++] = offset(addr
, bld
, i
);
4123 for (unsigned i
= 0; i
< src_sz
; i
++)
4124 components
[n
++] = offset(src
, bld
, i
);
4126 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4128 /* Update the original instruction. */
4130 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4131 inst
->header_size
= header_sz
;
4133 inst
->src
[0] = payload
;
4134 inst
->src
[1] = surface
;
4136 inst
->resize_sources(3);
4138 delete[] components
;
4142 fs_visitor::lower_logical_sends()
4144 bool progress
= false;
4146 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4147 const fs_builder
ibld(this, block
, inst
);
4149 switch (inst
->opcode
) {
4150 case FS_OPCODE_FB_WRITE_LOGICAL
:
4151 assert(stage
== MESA_SHADER_FRAGMENT
);
4152 lower_fb_write_logical_send(ibld
, inst
,
4153 (const brw_wm_prog_data
*)prog_data
,
4154 (const brw_wm_prog_key
*)key
,
4158 case SHADER_OPCODE_TEX_LOGICAL
:
4159 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4162 case SHADER_OPCODE_TXD_LOGICAL
:
4163 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4166 case SHADER_OPCODE_TXF_LOGICAL
:
4167 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4170 case SHADER_OPCODE_TXL_LOGICAL
:
4171 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4174 case SHADER_OPCODE_TXS_LOGICAL
:
4175 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4178 case FS_OPCODE_TXB_LOGICAL
:
4179 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4182 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4183 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4186 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4187 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4190 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4191 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4194 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4195 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4198 case SHADER_OPCODE_LOD_LOGICAL
:
4199 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4202 case SHADER_OPCODE_TG4_LOGICAL
:
4203 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4206 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4207 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4210 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4211 lower_surface_logical_send(ibld
, inst
,
4212 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4216 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4217 lower_surface_logical_send(ibld
, inst
,
4218 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4219 ibld
.sample_mask_reg());
4222 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4223 lower_surface_logical_send(ibld
, inst
,
4224 SHADER_OPCODE_UNTYPED_ATOMIC
,
4225 ibld
.sample_mask_reg());
4228 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4229 lower_surface_logical_send(ibld
, inst
,
4230 SHADER_OPCODE_TYPED_SURFACE_READ
,
4234 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4235 lower_surface_logical_send(ibld
, inst
,
4236 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4237 ibld
.sample_mask_reg());
4240 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4241 lower_surface_logical_send(ibld
, inst
,
4242 SHADER_OPCODE_TYPED_ATOMIC
,
4243 ibld
.sample_mask_reg());
4254 invalidate_live_intervals();
4260 * Get the closest native SIMD width supported by the hardware for instruction
4261 * \p inst. The instruction will be left untouched by
4262 * fs_visitor::lower_simd_width() if the returned value is equal to the
4263 * original execution size.
4266 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4267 const fs_inst
*inst
)
4269 switch (inst
->opcode
) {
4270 case BRW_OPCODE_MOV
:
4271 case BRW_OPCODE_SEL
:
4272 case BRW_OPCODE_NOT
:
4273 case BRW_OPCODE_AND
:
4275 case BRW_OPCODE_XOR
:
4276 case BRW_OPCODE_SHR
:
4277 case BRW_OPCODE_SHL
:
4278 case BRW_OPCODE_ASR
:
4279 case BRW_OPCODE_CMP
:
4280 case BRW_OPCODE_CMPN
:
4281 case BRW_OPCODE_CSEL
:
4282 case BRW_OPCODE_F32TO16
:
4283 case BRW_OPCODE_F16TO32
:
4284 case BRW_OPCODE_BFREV
:
4285 case BRW_OPCODE_BFE
:
4286 case BRW_OPCODE_BFI1
:
4287 case BRW_OPCODE_BFI2
:
4288 case BRW_OPCODE_ADD
:
4289 case BRW_OPCODE_MUL
:
4290 case BRW_OPCODE_AVG
:
4291 case BRW_OPCODE_FRC
:
4292 case BRW_OPCODE_RNDU
:
4293 case BRW_OPCODE_RNDD
:
4294 case BRW_OPCODE_RNDE
:
4295 case BRW_OPCODE_RNDZ
:
4296 case BRW_OPCODE_LZD
:
4297 case BRW_OPCODE_FBH
:
4298 case BRW_OPCODE_FBL
:
4299 case BRW_OPCODE_CBIT
:
4300 case BRW_OPCODE_SAD2
:
4301 case BRW_OPCODE_MAD
:
4302 case BRW_OPCODE_LRP
:
4303 case SHADER_OPCODE_RCP
:
4304 case SHADER_OPCODE_RSQ
:
4305 case SHADER_OPCODE_SQRT
:
4306 case SHADER_OPCODE_EXP2
:
4307 case SHADER_OPCODE_LOG2
:
4308 case SHADER_OPCODE_POW
:
4309 case SHADER_OPCODE_INT_QUOTIENT
:
4310 case SHADER_OPCODE_INT_REMAINDER
:
4311 case SHADER_OPCODE_SIN
:
4312 case SHADER_OPCODE_COS
: {
4313 /* According to the PRMs:
4314 * "A. In Direct Addressing mode, a source cannot span more than 2
4315 * adjacent GRF registers.
4316 * B. A destination cannot span more than 2 adjacent GRF registers."
4318 * Look for the source or destination with the largest register region
4319 * which is the one that is going to limit the overal execution size of
4320 * the instruction due to this rule.
4322 unsigned reg_count
= inst
->regs_written
;
4324 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4325 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4327 /* Calculate the maximum execution size of the instruction based on the
4328 * factor by which it goes over the hardware limit of 2 GRFs.
4330 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4332 case SHADER_OPCODE_MULH
:
4333 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4334 * is 8-wide on Gen7+.
4336 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4338 case FS_OPCODE_FB_WRITE_LOGICAL
:
4339 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4342 assert(devinfo
->gen
!= 6 ||
4343 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4344 inst
->exec_size
== 8);
4345 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4346 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4347 8 : inst
->exec_size
);
4349 case SHADER_OPCODE_TXD_LOGICAL
:
4350 /* TXD is unsupported in SIMD16 mode. */
4353 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4354 /* gather4_po_c is unsupported in SIMD16 mode. */
4355 const fs_reg
&shadow_c
= inst
->src
[1];
4356 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4358 case SHADER_OPCODE_TXL_LOGICAL
:
4359 case FS_OPCODE_TXB_LOGICAL
: {
4360 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4361 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4362 * mode because the message exceeds the maximum length of 11.
4364 const fs_reg
&shadow_c
= inst
->src
[1];
4365 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4367 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4370 return inst
->exec_size
;
4372 case SHADER_OPCODE_TXF_LOGICAL
:
4373 case SHADER_OPCODE_TXS_LOGICAL
:
4374 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4375 * messages. Use SIMD16 instead.
4377 if (devinfo
->gen
== 4)
4380 return inst
->exec_size
;
4382 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4383 /* This opcode can take up to 6 arguments which means that in some
4384 * circumstances it can end up with a message that is too long in SIMD16
4387 const unsigned coord_components
= inst
->src
[8].fixed_hw_reg
.dw1
.ud
;
4388 /* First three arguments are the sample index and the two arguments for
4391 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
4394 return inst
->exec_size
;
4397 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4398 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4399 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4403 return inst
->exec_size
;
4408 * The \p rows array of registers represents a \p num_rows by \p num_columns
4409 * matrix in row-major order, write it in column-major order into the register
4410 * passed as destination. \p stride gives the separation between matrix
4411 * elements in the input in fs_builder::dispatch_width() units.
4414 emit_transpose(const fs_builder
&bld
,
4415 const fs_reg
&dst
, const fs_reg
*rows
,
4416 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4418 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4420 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4421 for (unsigned j
= 0; j
< num_rows
; ++j
)
4422 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4425 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4427 delete[] components
;
4431 fs_visitor::lower_simd_width()
4433 bool progress
= false;
4435 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4436 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4438 if (lower_width
!= inst
->exec_size
) {
4439 /* Builder matching the original instruction. We may also need to
4440 * emit an instruction of width larger than the original, set the
4441 * execution size of the builder to the highest of both for now so
4442 * we're sure that both cases can be handled.
4444 const fs_builder ibld
= bld
.at(block
, inst
)
4445 .exec_all(inst
->force_writemask_all
)
4446 .group(MAX2(inst
->exec_size
, lower_width
),
4447 inst
->force_sechalf
);
4449 /* Split the copies in chunks of the execution width of either the
4450 * original or the lowered instruction, whichever is lower.
4452 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4453 const unsigned n
= inst
->exec_size
/ copy_width
;
4454 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4455 inst
->dst
.component_size(inst
->exec_size
);
4458 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4459 !inst
->writes_accumulator
&& !inst
->mlen
);
4461 for (unsigned i
= 0; i
< n
; i
++) {
4462 /* Emit a copy of the original instruction with the lowered width.
4463 * If the EOT flag was set throw it away except for the last
4464 * instruction to avoid killing the thread prematurely.
4466 fs_inst split_inst
= *inst
;
4467 split_inst
.exec_size
= lower_width
;
4468 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4470 /* Select the correct channel enables for the i-th group, then
4471 * transform the sources and destination and emit the lowered
4474 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4476 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4477 if (inst
->src
[j
].file
!= BAD_FILE
&&
4478 !is_uniform(inst
->src
[j
])) {
4479 /* Get the i-th copy_width-wide chunk of the source. */
4480 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4481 const unsigned src_size
= inst
->components_read(j
);
4483 /* Use a trivial transposition to copy one every n
4484 * copy_width-wide components of the register into a
4485 * temporary passed as source to the lowered instruction.
4487 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4488 emit_transpose(lbld
.group(copy_width
, 0),
4489 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4493 if (inst
->regs_written
) {
4494 /* Allocate enough space to hold the result of the lowered
4495 * instruction and fix up the number of registers written.
4497 split_inst
.dst
= dsts
[i
] =
4498 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4499 split_inst
.regs_written
=
4500 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4504 lbld
.emit(split_inst
);
4507 if (inst
->regs_written
) {
4508 /* Distance between useful channels in the temporaries, skipping
4509 * garbage if the lowered instruction is wider than the original.
4511 const unsigned m
= lower_width
/ copy_width
;
4513 /* Interleave the components of the result from the lowered
4514 * instructions. We need to set exec_all() when copying more than
4515 * one half per component, because LOAD_PAYLOAD (in terms of which
4516 * emit_transpose is implemented) can only use the same channel
4517 * enable signals for all of its non-header sources.
4519 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4520 .group(copy_width
, 0),
4521 inst
->dst
, dsts
, n
, dst_size
, m
);
4524 inst
->remove(block
);
4530 invalidate_live_intervals();
4536 fs_visitor::dump_instructions()
4538 dump_instructions(NULL
);
4542 fs_visitor::dump_instructions(const char *name
)
4544 FILE *file
= stderr
;
4545 if (name
&& geteuid() != 0) {
4546 file
= fopen(name
, "w");
4552 calculate_register_pressure();
4553 int ip
= 0, max_pressure
= 0;
4554 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4555 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4556 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4557 dump_instruction(inst
, file
);
4560 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4563 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4564 fprintf(file
, "%4d: ", ip
++);
4565 dump_instruction(inst
, file
);
4569 if (file
!= stderr
) {
4575 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4577 dump_instruction(be_inst
, stderr
);
4581 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4583 fs_inst
*inst
= (fs_inst
*)be_inst
;
4585 if (inst
->predicate
) {
4586 fprintf(file
, "(%cf0.%d) ",
4587 inst
->predicate_inverse
? '-' : '+',
4591 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4593 fprintf(file
, ".sat");
4594 if (inst
->conditional_mod
) {
4595 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4596 if (!inst
->predicate
&&
4597 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4598 inst
->opcode
!= BRW_OPCODE_IF
&&
4599 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4600 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4603 fprintf(file
, "(%d) ", inst
->exec_size
);
4606 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4609 switch (inst
->dst
.file
) {
4611 fprintf(file
, "vgrf%d", inst
->dst
.reg
);
4612 if (alloc
.sizes
[inst
->dst
.reg
] != inst
->regs_written
||
4613 inst
->dst
.subreg_offset
)
4614 fprintf(file
, "+%d.%d",
4615 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4618 fprintf(file
, "m%d", inst
->dst
.reg
);
4621 fprintf(file
, "(null)");
4624 fprintf(file
, "***u%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
4627 fprintf(file
, "***attr%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
4630 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
4631 switch (inst
->dst
.fixed_hw_reg
.nr
) {
4633 fprintf(file
, "null");
4635 case BRW_ARF_ADDRESS
:
4636 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
4638 case BRW_ARF_ACCUMULATOR
:
4639 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
4642 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
4643 inst
->dst
.fixed_hw_reg
.subnr
);
4646 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
4647 inst
->dst
.fixed_hw_reg
.subnr
);
4651 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
4653 if (inst
->dst
.fixed_hw_reg
.subnr
)
4654 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
4657 unreachable("not reached");
4659 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4661 for (int i
= 0; i
< inst
->sources
; i
++) {
4662 if (inst
->src
[i
].negate
)
4664 if (inst
->src
[i
].abs
)
4666 switch (inst
->src
[i
].file
) {
4668 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
4669 if (alloc
.sizes
[inst
->src
[i
].reg
] != (unsigned)inst
->regs_read(i
) ||
4670 inst
->src
[i
].subreg_offset
)
4671 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4672 inst
->src
[i
].subreg_offset
);
4675 fprintf(file
, "***m%d***", inst
->src
[i
].reg
);
4678 fprintf(file
, "attr%d+%d", inst
->src
[i
].reg
, inst
->src
[i
].reg_offset
);
4681 fprintf(file
, "u%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
4682 if (inst
->src
[i
].reladdr
) {
4683 fprintf(file
, "+reladdr");
4684 } else if (inst
->src
[i
].subreg_offset
) {
4685 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4686 inst
->src
[i
].subreg_offset
);
4690 fprintf(file
, "(null)");
4693 switch (inst
->src
[i
].type
) {
4694 case BRW_REGISTER_TYPE_F
:
4695 fprintf(file
, "%ff", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
4697 case BRW_REGISTER_TYPE_W
:
4698 case BRW_REGISTER_TYPE_D
:
4699 fprintf(file
, "%dd", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
4701 case BRW_REGISTER_TYPE_UW
:
4702 case BRW_REGISTER_TYPE_UD
:
4703 fprintf(file
, "%uu", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
4705 case BRW_REGISTER_TYPE_VF
:
4706 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4707 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
4708 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
4709 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
4710 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
4713 fprintf(file
, "???");
4718 if (inst
->src
[i
].fixed_hw_reg
.negate
)
4720 if (inst
->src
[i
].fixed_hw_reg
.abs
)
4722 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
4723 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
4725 fprintf(file
, "null");
4727 case BRW_ARF_ADDRESS
:
4728 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4730 case BRW_ARF_ACCUMULATOR
:
4731 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4734 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
4735 inst
->src
[i
].fixed_hw_reg
.subnr
);
4738 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
4739 inst
->src
[i
].fixed_hw_reg
.subnr
);
4743 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
4745 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
4746 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4747 if (inst
->src
[i
].fixed_hw_reg
.abs
)
4751 if (inst
->src
[i
].abs
)
4754 if (inst
->src
[i
].file
!= IMM
) {
4755 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4758 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4759 fprintf(file
, ", ");
4764 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4765 if (inst
->force_sechalf
)
4766 fprintf(file
, "2ndhalf ");
4768 fprintf(file
, "1sthalf ");
4771 fprintf(file
, "\n");
4775 * Possibly returns an instruction that set up @param reg.
4777 * Sometimes we want to take the result of some expression/variable
4778 * dereference tree and rewrite the instruction generating the result
4779 * of the tree. When processing the tree, we know that the
4780 * instructions generated are all writing temporaries that are dead
4781 * outside of this tree. So, if we have some instructions that write
4782 * a temporary, we're free to point that temp write somewhere else.
4784 * Note that this doesn't guarantee that the instruction generated
4785 * only reg -- it might be the size=4 destination of a texture instruction.
4788 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4793 end
->is_partial_write() ||
4795 !reg
.equals(end
->dst
)) {
4803 fs_visitor::setup_payload_gen6()
4806 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
4807 unsigned barycentric_interp_modes
=
4808 (stage
== MESA_SHADER_FRAGMENT
) ?
4809 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4811 assert(devinfo
->gen
>= 6);
4813 /* R0-1: masks, pixel X/Y coordinates. */
4814 payload
.num_regs
= 2;
4815 /* R2: only for 32-pixel dispatch.*/
4817 /* R3-26: barycentric interpolation coordinates. These appear in the
4818 * same order that they appear in the brw_wm_barycentric_interp_mode
4819 * enum. Each set of coordinates occupies 2 registers if dispatch width
4820 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4821 * appear if they were enabled using the "Barycentric Interpolation
4822 * Mode" bits in WM_STATE.
4824 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4825 if (barycentric_interp_modes
& (1 << i
)) {
4826 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4827 payload
.num_regs
+= 2;
4828 if (dispatch_width
== 16) {
4829 payload
.num_regs
+= 2;
4834 /* R27: interpolated depth if uses source depth */
4836 payload
.source_depth_reg
= payload
.num_regs
;
4838 if (dispatch_width
== 16) {
4839 /* R28: interpolated depth if not SIMD8. */
4843 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4845 payload
.source_w_reg
= payload
.num_regs
;
4847 if (dispatch_width
== 16) {
4848 /* R30: interpolated W if not SIMD8. */
4853 if (stage
== MESA_SHADER_FRAGMENT
) {
4854 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4855 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4856 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4857 /* R31: MSAA position offsets. */
4858 if (prog_data
->uses_pos_offset
) {
4859 payload
.sample_pos_reg
= payload
.num_regs
;
4864 /* R32: MSAA input coverage mask */
4865 if (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
4866 assert(devinfo
->gen
>= 7);
4867 payload
.sample_mask_in_reg
= payload
.num_regs
;
4869 if (dispatch_width
== 16) {
4870 /* R33: input coverage mask if not SIMD8. */
4875 /* R34-: bary for 32-pixel. */
4876 /* R58-59: interp W for 32-pixel. */
4878 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4879 source_depth_to_render_target
= true;
4884 fs_visitor::setup_vs_payload()
4886 /* R0: thread header, R1: urb handles */
4887 payload
.num_regs
= 2;
4891 * We are building the local ID push constant data using the simplest possible
4892 * method. We simply push the local IDs directly as they should appear in the
4893 * registers for the uvec3 gl_LocalInvocationID variable.
4895 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
4896 * registers worth of push constant space.
4898 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
4899 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
4902 * FINISHME: There are a few easy optimizations to consider.
4904 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
4905 * no need for using push constant space for that dimension.
4907 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
4908 * easily use 16-bit words rather than 32-bit dwords in the push constant
4911 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
4912 * conveying the data, and thereby reduce push constant usage.
4916 fs_visitor::setup_gs_payload()
4918 assert(stage
== MESA_SHADER_GEOMETRY
);
4920 struct brw_gs_prog_data
*gs_prog_data
=
4921 (struct brw_gs_prog_data
*) prog_data
;
4922 struct brw_vue_prog_data
*vue_prog_data
=
4923 (struct brw_vue_prog_data
*) prog_data
;
4925 /* R0: thread header, R1: output URB handles */
4926 payload
.num_regs
= 2;
4928 if (gs_prog_data
->include_primitive_id
) {
4929 /* R2: Primitive ID 0..7 */
4933 /* Use a maximum of 32 registers for push-model inputs. */
4934 const unsigned max_push_components
= 32;
4936 /* If pushing our inputs would take too many registers, reduce the URB read
4937 * length (which is in HWords, or 8 registers), and resort to pulling.
4939 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
4940 * have to multiply by VerticesIn to obtain the total storage requirement.
4942 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
4943 max_push_components
) {
4944 gs_prog_data
->base
.include_vue_handles
= true;
4946 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
4947 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
4949 vue_prog_data
->urb_read_length
=
4950 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
4955 fs_visitor::setup_cs_payload()
4957 assert(devinfo
->gen
>= 7);
4958 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
4960 payload
.num_regs
= 1;
4962 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
4963 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
4964 payload
.local_invocation_id_reg
= payload
.num_regs
;
4965 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
4970 fs_visitor::calculate_register_pressure()
4972 invalidate_live_intervals();
4973 calculate_live_intervals();
4975 unsigned num_instructions
= 0;
4976 foreach_block(block
, cfg
)
4977 num_instructions
+= block
->instructions
.length();
4979 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
4981 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
4982 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
4983 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
4988 fs_visitor::optimize()
4990 /* Start by validating the shader we currently have. */
4993 /* bld is the common builder object pointing at the end of the program we
4994 * used to translate it into i965 IR. For the optimization and lowering
4995 * passes coming next, any code added after the end of the program without
4996 * having explicitly called fs_builder::at() clearly points at a mistake.
4997 * Ideally optimization passes wouldn't be part of the visitor so they
4998 * wouldn't have access to bld at all, but they do, so just in case some
4999 * pass forgets to ask for a location explicitly set it to NULL here to
5000 * make it trip. The dispatch width is initialized to a bogus value to
5001 * make sure that optimizations set the execution controls explicitly to
5002 * match the code they are manipulating instead of relying on the defaults.
5004 bld
= fs_builder(this, 64);
5006 assign_constant_locations();
5007 demote_pull_constants();
5011 split_virtual_grfs();
5014 #define OPT(pass, args...) ({ \
5016 bool this_progress = pass(args); \
5018 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5019 char filename[64]; \
5020 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5021 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5023 backend_shader::dump_instructions(filename); \
5028 progress = progress || this_progress; \
5032 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5034 snprintf(filename
, 64, "%s%d-%s-00-start",
5035 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5037 backend_shader::dump_instructions(filename
);
5040 bool progress
= false;
5044 OPT(lower_simd_width
);
5045 OPT(lower_logical_sends
);
5052 OPT(remove_duplicate_mrf_writes
);
5056 OPT(opt_copy_propagate
);
5057 OPT(opt_predicated_break
, this);
5058 OPT(opt_cmod_propagation
);
5059 OPT(dead_code_eliminate
);
5060 OPT(opt_peephole_sel
);
5061 OPT(dead_control_flow_eliminate
, this);
5062 OPT(opt_register_renaming
);
5063 OPT(opt_redundant_discard_jumps
);
5064 OPT(opt_saturate_propagation
);
5065 OPT(opt_zero_samples
);
5066 OPT(register_coalesce
);
5067 OPT(compute_to_mrf
);
5068 OPT(eliminate_find_live_channel
);
5070 OPT(compact_virtual_grfs
);
5075 OPT(opt_sampler_eot
);
5077 if (OPT(lower_load_payload
)) {
5078 split_virtual_grfs();
5079 OPT(register_coalesce
);
5080 OPT(compute_to_mrf
);
5081 OPT(dead_code_eliminate
);
5084 OPT(opt_combine_constants
);
5085 OPT(lower_integer_multiplication
);
5087 lower_uniform_pull_constant_loads();
5093 * Three source instruction must have a GRF/MRF destination register.
5094 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5097 fs_visitor::fixup_3src_null_dest()
5099 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5100 if (inst
->is_3src() && inst
->dst
.is_null()) {
5101 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
5108 fs_visitor::allocate_registers()
5110 bool allocated_without_spills
;
5112 static const enum instruction_scheduler_mode pre_modes
[] = {
5114 SCHEDULE_PRE_NON_LIFO
,
5118 /* Try each scheduling heuristic to see if it can successfully register
5119 * allocate without spilling. They should be ordered by decreasing
5120 * performance but increasing likelihood of allocating.
5122 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5123 schedule_instructions(pre_modes
[i
]);
5126 assign_regs_trivial();
5127 allocated_without_spills
= true;
5129 allocated_without_spills
= assign_regs(false);
5131 if (allocated_without_spills
)
5135 if (!allocated_without_spills
) {
5136 /* We assume that any spilling is worse than just dropping back to
5137 * SIMD8. There's probably actually some intermediate point where
5138 * SIMD16 with a couple of spills is still better.
5140 if (dispatch_width
== 16) {
5141 fail("Failure to register allocate. Reduce number of "
5142 "live scalar values to avoid this.");
5144 compiler
->shader_perf_log(log_data
,
5145 "%s shader triggered register spilling. "
5146 "Try reducing the number of live scalar "
5147 "values to improve performance.\n",
5151 /* Since we're out of heuristics, just go spill registers until we
5152 * get an allocation.
5154 while (!assign_regs(true)) {
5160 /* This must come after all optimization and register allocation, since
5161 * it inserts dead code that happens to have side effects, and it does
5162 * so based on the actual physical registers in use.
5164 insert_gen4_send_dependency_workarounds();
5169 schedule_instructions(SCHEDULE_POST
);
5171 if (last_scratch
> 0)
5172 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5176 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5178 assert(stage
== MESA_SHADER_VERTEX
);
5182 if (shader_time_index
>= 0)
5183 emit_shader_time_begin();
5190 compute_clip_distance(clip_planes
);
5194 if (shader_time_index
>= 0)
5195 emit_shader_time_end();
5201 assign_curb_setup();
5202 assign_vs_urb_setup();
5204 fixup_3src_null_dest();
5205 allocate_registers();
5211 fs_visitor::run_gs()
5213 assert(stage
== MESA_SHADER_GEOMETRY
);
5217 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
5219 if (gs_compile
->control_data_header_size_bits
> 0) {
5220 /* Create a VGRF to store accumulated control data bits. */
5221 this->control_data_bits
= vgrf(glsl_type::uint_type
);
5223 /* If we're outputting more than 32 control data bits, then EmitVertex()
5224 * will set control_data_bits to 0 after emitting the first vertex.
5225 * Otherwise, we need to initialize it to 0 here.
5227 if (gs_compile
->control_data_header_size_bits
<= 32) {
5228 const fs_builder abld
= bld
.annotate("initialize control data bits");
5229 abld
.MOV(this->control_data_bits
, fs_reg(0u));
5233 if (shader_time_index
>= 0)
5234 emit_shader_time_begin();
5238 emit_gs_thread_end();
5240 if (shader_time_index
>= 0)
5241 emit_shader_time_end();
5250 assign_curb_setup();
5251 assign_gs_urb_setup();
5253 fixup_3src_null_dest();
5254 allocate_registers();
5260 fs_visitor::run_fs(bool do_rep_send
)
5262 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5263 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
5265 assert(stage
== MESA_SHADER_FRAGMENT
);
5267 if (devinfo
->gen
>= 6)
5268 setup_payload_gen6();
5270 setup_payload_gen4();
5274 } else if (do_rep_send
) {
5275 assert(dispatch_width
== 16);
5276 emit_repclear_shader();
5278 if (shader_time_index
>= 0)
5279 emit_shader_time_begin();
5281 calculate_urb_setup();
5282 if (nir
->info
.inputs_read
> 0) {
5283 if (devinfo
->gen
< 6)
5284 emit_interpolation_setup_gen4();
5286 emit_interpolation_setup_gen6();
5289 /* We handle discards by keeping track of the still-live pixels in f0.1.
5290 * Initialize it with the dispatched pixels.
5292 if (wm_prog_data
->uses_kill
) {
5293 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5294 discard_init
->flag_subreg
= 1;
5297 /* Generate FS IR for main(). (the visitor only descends into
5298 * functions called "main").
5305 if (wm_prog_data
->uses_kill
)
5306 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5308 if (wm_key
->alpha_test_func
)
5313 if (shader_time_index
>= 0)
5314 emit_shader_time_end();
5320 assign_curb_setup();
5323 fixup_3src_null_dest();
5324 allocate_registers();
5330 if (dispatch_width
== 8)
5331 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5333 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5339 fs_visitor::run_cs()
5341 assert(stage
== MESA_SHADER_COMPUTE
);
5345 if (shader_time_index
>= 0)
5346 emit_shader_time_begin();
5353 emit_cs_terminate();
5355 if (shader_time_index
>= 0)
5356 emit_shader_time_end();
5362 assign_curb_setup();
5364 fixup_3src_null_dest();
5365 allocate_registers();
5374 * Return a bitfield where bit n is set if barycentric interpolation mode n
5375 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
5378 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
5379 bool shade_model_flat
,
5380 bool persample_shading
,
5381 const nir_shader
*shader
)
5383 unsigned barycentric_interp_modes
= 0;
5385 nir_foreach_variable(var
, &shader
->inputs
) {
5386 enum glsl_interp_qualifier interp_qualifier
=
5387 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5388 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
5389 bool is_sample
= var
->data
.sample
|| persample_shading
;
5390 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5391 (var
->data
.location
== VARYING_SLOT_COL1
);
5393 /* Ignore WPOS and FACE, because they don't require interpolation. */
5394 if (var
->data
.location
== VARYING_SLOT_POS
||
5395 var
->data
.location
== VARYING_SLOT_FACE
)
5398 /* Determine the set (or sets) of barycentric coordinates needed to
5399 * interpolate this variable. Note that when
5400 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
5401 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
5402 * for lit pixels, so we need both sets of barycentric coordinates.
5404 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
5406 barycentric_interp_modes
|=
5407 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
5408 } else if (is_sample
) {
5409 barycentric_interp_modes
|=
5410 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
5412 if ((!is_centroid
&& !is_sample
) ||
5413 devinfo
->needs_unlit_centroid_workaround
) {
5414 barycentric_interp_modes
|=
5415 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
5417 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
5418 (!(shade_model_flat
&& is_gl_Color
) &&
5419 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
5421 barycentric_interp_modes
|=
5422 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
5423 } else if (is_sample
) {
5424 barycentric_interp_modes
|=
5425 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
5427 if ((!is_centroid
&& !is_sample
) ||
5428 devinfo
->needs_unlit_centroid_workaround
) {
5429 barycentric_interp_modes
|=
5430 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
5435 return barycentric_interp_modes
;
5439 computed_depth_mode(const nir_shader
*shader
)
5441 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5442 switch (shader
->info
.fs
.depth_layout
) {
5443 case FRAG_DEPTH_LAYOUT_NONE
:
5444 case FRAG_DEPTH_LAYOUT_ANY
:
5445 return BRW_PSCDEPTH_ON
;
5446 case FRAG_DEPTH_LAYOUT_GREATER
:
5447 return BRW_PSCDEPTH_ON_GE
;
5448 case FRAG_DEPTH_LAYOUT_LESS
:
5449 return BRW_PSCDEPTH_ON_LE
;
5450 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
5451 return BRW_PSCDEPTH_OFF
;
5454 return BRW_PSCDEPTH_OFF
;
5458 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
5460 const struct brw_wm_prog_key
*key
,
5461 struct brw_wm_prog_data
*prog_data
,
5462 const nir_shader
*shader
,
5463 struct gl_program
*prog
,
5464 int shader_time_index8
, int shader_time_index16
,
5466 unsigned *final_assembly_size
,
5469 /* key->alpha_test_func means simulating alpha testing via discards,
5470 * so the shader definitely kills pixels.
5472 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
5473 prog_data
->uses_omask
=
5474 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
5475 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
5476 prog_data
->computed_stencil
=
5477 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
5479 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
5481 prog_data
->barycentric_interp_modes
=
5482 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
5484 key
->persample_shading
,
5487 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
,
5488 &prog_data
->base
, prog
, shader
, 8,
5489 shader_time_index8
);
5490 if (!v
.run_fs(false /* do_rep_send */)) {
5492 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
5497 cfg_t
*simd16_cfg
= NULL
;
5498 fs_visitor
v2(compiler
, log_data
, mem_ctx
, key
,
5499 &prog_data
->base
, prog
, shader
, 16,
5500 shader_time_index16
);
5501 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
5502 if (!v
.simd16_unsupported
) {
5503 /* Try a SIMD16 compile */
5504 v2
.import_uniforms(&v
);
5505 if (!v2
.run_fs(use_rep_send
)) {
5506 compiler
->shader_perf_log(log_data
,
5507 "SIMD16 shader failed to compile: %s",
5510 simd16_cfg
= v2
.cfg
;
5516 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || use_rep_send
;
5517 if ((no_simd8
|| compiler
->devinfo
->gen
< 5) && simd16_cfg
) {
5519 prog_data
->no_8
= true;
5522 prog_data
->no_8
= false;
5525 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
5526 v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
5528 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5529 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
5530 shader
->info
.label
? shader
->info
.label
:
5532 shader
->info
.name
));
5536 g
.generate_code(simd8_cfg
, 8);
5538 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5540 return g
.get_assembly(final_assembly_size
);
5544 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*prog_data
,
5545 void *buffer
, uint32_t threads
, uint32_t stride
)
5547 if (prog_data
->local_invocation_id_regs
== 0)
5550 /* 'stride' should be an integer number of registers, that is, a multiple
5553 assert(stride
% 32 == 0);
5555 unsigned x
= 0, y
= 0, z
= 0;
5556 for (unsigned t
= 0; t
< threads
; t
++) {
5557 uint32_t *param
= (uint32_t *) buffer
+ stride
* t
/ 4;
5559 for (unsigned i
= 0; i
< prog_data
->simd_size
; i
++) {
5560 param
[0 * prog_data
->simd_size
+ i
] = x
;
5561 param
[1 * prog_data
->simd_size
+ i
] = y
;
5562 param
[2 * prog_data
->simd_size
+ i
] = z
;
5565 if (x
== prog_data
->local_size
[0]) {
5568 if (y
== prog_data
->local_size
[1]) {
5571 if (z
== prog_data
->local_size
[2])
5580 fs_visitor::emit_cs_local_invocation_id_setup()
5582 assert(stage
== MESA_SHADER_COMPUTE
);
5584 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5586 struct brw_reg src
=
5587 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
5588 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
5590 src
.nr
+= dispatch_width
/ 8;
5591 bld
.MOV(offset(*reg
, bld
, 1), src
);
5592 src
.nr
+= dispatch_width
/ 8;
5593 bld
.MOV(offset(*reg
, bld
, 2), src
);
5599 fs_visitor::emit_cs_work_group_id_setup()
5601 assert(stage
== MESA_SHADER_COMPUTE
);
5603 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5605 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
5606 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
5607 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
5609 bld
.MOV(*reg
, r0_1
);
5610 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
5611 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
5617 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
5619 const struct brw_cs_prog_key
*key
,
5620 struct brw_cs_prog_data
*prog_data
,
5621 const nir_shader
*shader
,
5622 int shader_time_index
,
5623 unsigned *final_assembly_size
,
5626 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
5627 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
5628 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
5629 unsigned local_workgroup_size
=
5630 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
5631 shader
->info
.cs
.local_size
[2];
5633 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
5636 const char *fail_msg
= NULL
;
5638 /* Now the main event: Visit the shader IR and generate our CS IR for it.
5640 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5641 NULL
, /* Never used in core profile */
5642 shader
, 8, shader_time_index
);
5644 fail_msg
= v8
.fail_msg
;
5645 } else if (local_workgroup_size
<= 8 * max_cs_threads
) {
5647 prog_data
->simd_size
= 8;
5650 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5651 NULL
, /* Never used in core profile */
5652 shader
, 16, shader_time_index
);
5653 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
5654 !fail_msg
&& !v8
.simd16_unsupported
&&
5655 local_workgroup_size
<= 16 * max_cs_threads
) {
5656 /* Try a SIMD16 compile */
5657 v16
.import_uniforms(&v8
);
5658 if (!v16
.run_cs()) {
5659 compiler
->shader_perf_log(log_data
,
5660 "SIMD16 shader failed to compile: %s",
5664 "Couldn't generate SIMD16 program and not "
5665 "enough threads for SIMD8";
5669 prog_data
->simd_size
= 16;
5673 if (unlikely(cfg
== NULL
)) {
5676 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
5681 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
5682 v8
.promoted_constants
, v8
.runtime_check_aads_emit
, "CS");
5683 if (INTEL_DEBUG
& DEBUG_CS
) {
5684 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
5685 shader
->info
.label
? shader
->info
.label
:
5688 g
.enable_debug(name
);
5691 g
.generate_code(cfg
, prog_data
->simd_size
);
5693 return g
.get_assembly(final_assembly_size
);