2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
32 #include "brw_context.h"
37 #include "brw_vec4_gs_visitor.h"
39 #include "brw_program.h"
40 #include "brw_dead_control_flow.h"
41 #include "compiler/glsl_types.h"
46 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
47 const fs_reg
*src
, unsigned sources
)
49 memset(this, 0, sizeof(*this));
51 this->src
= new fs_reg
[MAX2(sources
, 3)];
52 for (unsigned i
= 0; i
< sources
; i
++)
53 this->src
[i
] = src
[i
];
55 this->opcode
= opcode
;
57 this->sources
= sources
;
58 this->exec_size
= exec_size
;
60 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
62 assert(this->exec_size
!= 0);
64 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
66 /* This will be the case for almost all instructions. */
73 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
77 this->regs_written
= 0;
81 unreachable("Invalid destination register file");
84 this->writes_accumulator
= false;
89 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
92 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
94 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
97 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
99 init(opcode
, exec_size
, dst
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
105 const fs_reg src
[1] = { src0
};
106 init(opcode
, exec_size
, dst
, src
, 1);
109 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
110 const fs_reg
&src0
, const fs_reg
&src1
)
112 const fs_reg src
[2] = { src0
, src1
};
113 init(opcode
, exec_size
, dst
, src
, 2);
116 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
117 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
119 const fs_reg src
[3] = { src0
, src1
, src2
};
120 init(opcode
, exec_size
, dst
, src
, 3);
123 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
124 const fs_reg src
[], unsigned sources
)
126 init(opcode
, exec_width
, dst
, src
, sources
);
129 fs_inst::fs_inst(const fs_inst
&that
)
131 memcpy(this, &that
, sizeof(that
));
133 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
135 for (unsigned i
= 0; i
< that
.sources
; i
++)
136 this->src
[i
] = that
.src
[i
];
145 fs_inst::resize_sources(uint8_t num_sources
)
147 if (this->sources
!= num_sources
) {
148 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
150 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
151 src
[i
] = this->src
[i
];
155 this->sources
= num_sources
;
160 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
162 const fs_reg
&surf_index
,
163 const fs_reg
&varying_offset
,
164 uint32_t const_offset
)
166 /* We have our constant surface use a pitch of 4 bytes, so our index can
167 * be any component of a vector, and then we load 4 contiguous
168 * components starting from that.
170 * We break down the const_offset to a portion added to the variable
171 * offset and a portion done using reg_offset, which means that if you
172 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
173 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
174 * CSE can later notice that those loads are all the same and eliminate
175 * the redundant ones.
177 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
178 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
181 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
182 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
183 * u, v, r) as parameters, or we can just use the SIMD16 message
184 * consisting of (header, u). We choose the second, at the cost of a
185 * longer return length.
191 if (devinfo
->gen
>= 7)
192 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
194 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
196 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
197 fs_reg vec4_result
= fs_reg(VGRF
, alloc
.allocate(regs_written
), dst
.type
);
198 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
199 inst
->regs_written
= regs_written
;
201 if (devinfo
->gen
< 7) {
202 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
);
203 inst
->header_size
= 1;
204 if (devinfo
->gen
== 4)
207 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
210 bld
.MOV(dst
, offset(vec4_result
, bld
, ((const_offset
& 0xf) / 4) * scale
));
214 * A helper for MOV generation for fixing up broken hardware SEND dependency
218 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
220 /* The caller always wants uncompressed to emit the minimal extra
221 * dependencies, and to avoid having to deal with aligning its regs to 2.
223 const fs_builder ubld
= bld
.annotate("send dependency resolve")
226 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
230 fs_inst::equals(fs_inst
*inst
) const
232 return (opcode
== inst
->opcode
&&
233 dst
.equals(inst
->dst
) &&
234 src
[0].equals(inst
->src
[0]) &&
235 src
[1].equals(inst
->src
[1]) &&
236 src
[2].equals(inst
->src
[2]) &&
237 saturate
== inst
->saturate
&&
238 predicate
== inst
->predicate
&&
239 conditional_mod
== inst
->conditional_mod
&&
240 mlen
== inst
->mlen
&&
241 base_mrf
== inst
->base_mrf
&&
242 target
== inst
->target
&&
244 header_size
== inst
->header_size
&&
245 shadow_compare
== inst
->shadow_compare
&&
246 exec_size
== inst
->exec_size
&&
247 offset
== inst
->offset
);
251 fs_inst::overwrites_reg(const fs_reg
®
) const
253 return reg
.in_range(dst
, regs_written
);
257 fs_inst::is_send_from_grf() const
260 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
261 case SHADER_OPCODE_SHADER_TIME_ADD
:
262 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
263 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
264 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
265 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
266 case SHADER_OPCODE_UNTYPED_ATOMIC
:
267 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
268 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
269 case SHADER_OPCODE_TYPED_ATOMIC
:
270 case SHADER_OPCODE_TYPED_SURFACE_READ
:
271 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
272 case SHADER_OPCODE_URB_WRITE_SIMD8
:
273 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
274 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
275 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
276 case SHADER_OPCODE_URB_READ_SIMD8
:
277 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
279 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
280 return src
[1].file
== VGRF
;
281 case FS_OPCODE_FB_WRITE
:
282 return src
[0].file
== VGRF
;
285 return src
[0].file
== VGRF
;
292 * Returns true if this instruction's sources and destinations cannot
293 * safely be the same register.
295 * In most cases, a register can be written over safely by the same
296 * instruction that is its last use. For a single instruction, the
297 * sources are dereferenced before writing of the destination starts
300 * However, there are a few cases where this can be problematic:
302 * - Virtual opcodes that translate to multiple instructions in the
303 * code generator: if src == dst and one instruction writes the
304 * destination before a later instruction reads the source, then
305 * src will have been clobbered.
307 * - SIMD16 compressed instructions with certain regioning (see below).
309 * The register allocator uses this information to set up conflicts between
310 * GRF sources and the destination.
313 fs_inst::has_source_and_destination_hazard() const
316 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
317 /* Multiple partial writes to the destination */
320 /* The SIMD16 compressed instruction
322 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
324 * is actually decoded in hardware as:
326 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
327 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
329 * Which is safe. However, if we have uniform accesses
330 * happening, we get into trouble:
332 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
333 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
335 * Now our destination for the first instruction overwrote the
336 * second instruction's src0, and we get garbage for those 8
337 * pixels. There's a similar issue for the pre-gen6
338 * pixel_x/pixel_y, which are registers of 16-bit values and thus
339 * would get stomped by the first decode as well.
341 if (exec_size
== 16) {
342 for (int i
= 0; i
< sources
; i
++) {
343 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
344 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
345 src
[i
].type
== BRW_REGISTER_TYPE_W
||
346 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
347 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
357 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
359 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
362 fs_reg reg
= this->src
[0];
363 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
366 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
369 for (int i
= 0; i
< this->sources
; i
++) {
370 reg
.type
= this->src
[i
].type
;
371 if (!this->src
[i
].equals(reg
))
374 if (i
< this->header_size
) {
377 reg
.reg_offset
+= this->exec_size
/ 8;
385 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
387 if (devinfo
->gen
== 6 && is_math())
390 if (is_send_from_grf())
393 if (!backend_instruction::can_do_source_mods())
400 fs_inst::can_change_types() const
402 return dst
.type
== src
[0].type
&&
403 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
404 (opcode
== BRW_OPCODE_MOV
||
405 (opcode
== BRW_OPCODE_SEL
&&
406 dst
.type
== src
[1].type
&&
407 predicate
!= BRW_PREDICATE_NONE
&&
408 !src
[1].abs
&& !src
[1].negate
));
412 fs_inst::has_side_effects() const
414 return this->eot
|| backend_instruction::has_side_effects();
420 memset(this, 0, sizeof(*this));
424 /** Generic unset register constructor. */
428 this->file
= BAD_FILE
;
431 fs_reg::fs_reg(struct ::brw_reg reg
) :
434 this->reg_offset
= 0;
435 this->subreg_offset
= 0;
436 this->reladdr
= NULL
;
438 if (this->file
== IMM
&&
439 (this->type
!= BRW_REGISTER_TYPE_V
&&
440 this->type
!= BRW_REGISTER_TYPE_UV
&&
441 this->type
!= BRW_REGISTER_TYPE_VF
)) {
447 fs_reg::equals(const fs_reg
&r
) const
449 return (this->backend_reg::equals(r
) &&
450 subreg_offset
== r
.subreg_offset
&&
451 !reladdr
&& !r
.reladdr
&&
456 fs_reg::set_smear(unsigned subreg
)
458 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
459 subreg_offset
= subreg
* type_sz(type
);
465 fs_reg::is_contiguous() const
471 fs_reg::component_size(unsigned width
) const
473 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
476 return MAX2(width
* stride
, 1) * type_sz(type
);
480 type_size_scalar(const struct glsl_type
*type
)
482 unsigned int size
, i
;
484 switch (type
->base_type
) {
487 case GLSL_TYPE_FLOAT
:
489 return type
->components();
490 case GLSL_TYPE_ARRAY
:
491 return type_size_scalar(type
->fields
.array
) * type
->length
;
492 case GLSL_TYPE_STRUCT
:
494 for (i
= 0; i
< type
->length
; i
++) {
495 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
498 case GLSL_TYPE_SAMPLER
:
499 /* Samplers take up no register space, since they're baked in at
503 case GLSL_TYPE_ATOMIC_UINT
:
505 case GLSL_TYPE_SUBROUTINE
:
507 case GLSL_TYPE_IMAGE
:
508 return BRW_IMAGE_PARAM_SIZE
;
510 case GLSL_TYPE_ERROR
:
511 case GLSL_TYPE_INTERFACE
:
512 case GLSL_TYPE_DOUBLE
:
513 case GLSL_TYPE_FUNCTION
:
514 unreachable("not reached");
521 * Returns the number of scalar components needed to store type, assuming
522 * that vectors are padded out to vec4.
524 * This has the packing rules of type_size_vec4(), but counts components
525 * similar to type_size_scalar().
528 type_size_vec4_times_4(const struct glsl_type
*type
)
530 return 4 * type_size_vec4(type
);
534 * Create a MOV to read the timestamp register.
536 * The caller is responsible for emitting the MOV. The return value is
537 * the destination of the MOV, with extra parameters set.
540 fs_visitor::get_timestamp(const fs_builder
&bld
)
542 assert(devinfo
->gen
>= 7);
544 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
547 BRW_REGISTER_TYPE_UD
));
549 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
551 /* We want to read the 3 fields we care about even if it's not enabled in
554 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
560 fs_visitor::emit_shader_time_begin()
562 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
564 /* We want only the low 32 bits of the timestamp. Since it's running
565 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
566 * which is plenty of time for our purposes. It is identical across the
567 * EUs, but since it's tracking GPU core speed it will increment at a
568 * varying rate as render P-states change.
570 shader_start_time
.set_smear(0);
574 fs_visitor::emit_shader_time_end()
576 /* Insert our code just before the final SEND with EOT. */
577 exec_node
*end
= this->instructions
.get_tail();
578 assert(end
&& ((fs_inst
*) end
)->eot
);
579 const fs_builder ibld
= bld
.annotate("shader time end")
580 .exec_all().at(NULL
, end
);
582 fs_reg shader_end_time
= get_timestamp(ibld
);
584 /* We only use the low 32 bits of the timestamp - see
585 * emit_shader_time_begin()).
587 * We could also check if render P-states have changed (or anything
588 * else that might disrupt timing) by setting smear to 2 and checking if
589 * that field is != 0.
591 shader_end_time
.set_smear(0);
593 /* Check that there weren't any timestamp reset events (assuming these
594 * were the only two timestamp reads that happened).
596 fs_reg reset
= shader_end_time
;
598 set_condmod(BRW_CONDITIONAL_Z
,
599 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
600 ibld
.IF(BRW_PREDICATE_NORMAL
);
602 fs_reg start
= shader_start_time
;
604 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
607 const fs_builder cbld
= ibld
.group(1, 0);
608 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
610 /* If there were no instructions between the two timestamp gets, the diff
611 * is 2 cycles. Remove that overhead, so I can forget about that when
612 * trying to determine the time taken for single instructions.
614 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
615 SHADER_TIME_ADD(cbld
, 0, diff
);
616 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
617 ibld
.emit(BRW_OPCODE_ELSE
);
618 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
619 ibld
.emit(BRW_OPCODE_ENDIF
);
623 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
624 int shader_time_subindex
,
627 int index
= shader_time_index
* 3 + shader_time_subindex
;
628 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
631 if (dispatch_width
== 8)
632 payload
= vgrf(glsl_type::uvec2_type
);
634 payload
= vgrf(glsl_type::uint_type
);
636 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
640 fs_visitor::vfail(const char *format
, va_list va
)
649 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
650 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
652 this->fail_msg
= msg
;
655 fprintf(stderr
, "%s", msg
);
660 fs_visitor::fail(const char *format
, ...)
664 va_start(va
, format
);
670 * Mark this program as impossible to compile in SIMD16 mode.
672 * During the SIMD8 compile (which happens first), we can detect and flag
673 * things that are unsupported in SIMD16 mode, so the compiler can skip
674 * the SIMD16 compile altogether.
676 * During a SIMD16 compile (if one happens anyway), this just calls fail().
679 fs_visitor::no16(const char *msg
)
681 if (dispatch_width
== 16) {
684 simd16_unsupported
= true;
686 compiler
->shader_perf_log(log_data
,
687 "SIMD16 shader failed to compile: %s", msg
);
692 * Returns true if the instruction has a flag that means it won't
693 * update an entire destination register.
695 * For example, dead code elimination and live variable analysis want to know
696 * when a write to a variable screens off any preceding values that were in
700 fs_inst::is_partial_write() const
702 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
703 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
704 !this->dst
.is_contiguous());
708 fs_inst::components_read(unsigned i
) const
711 case FS_OPCODE_LINTERP
:
717 case FS_OPCODE_PIXEL_X
:
718 case FS_OPCODE_PIXEL_Y
:
722 case FS_OPCODE_FB_WRITE_LOGICAL
:
723 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
724 /* First/second FB write color. */
726 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
730 case SHADER_OPCODE_TEX_LOGICAL
:
731 case SHADER_OPCODE_TXD_LOGICAL
:
732 case SHADER_OPCODE_TXF_LOGICAL
:
733 case SHADER_OPCODE_TXL_LOGICAL
:
734 case SHADER_OPCODE_TXS_LOGICAL
:
735 case FS_OPCODE_TXB_LOGICAL
:
736 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
737 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
738 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
739 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
740 case SHADER_OPCODE_LOD_LOGICAL
:
741 case SHADER_OPCODE_TG4_LOGICAL
:
742 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
743 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
744 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
745 /* Texture coordinates. */
746 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
747 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
748 /* Texture derivatives. */
749 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
750 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
751 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
752 /* Texture offset. */
753 else if (i
== TEX_LOGICAL_SRC_OFFSET_VALUE
)
756 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
761 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
762 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
763 assert(src
[3].file
== IMM
);
764 /* Surface coordinates. */
767 /* Surface operation source (ignored for reads). */
773 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
774 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
775 assert(src
[3].file
== IMM
&&
777 /* Surface coordinates. */
780 /* Surface operation source. */
786 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
787 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
788 assert(src
[3].file
== IMM
&&
790 const unsigned op
= src
[4].ud
;
791 /* Surface coordinates. */
794 /* Surface operation source. */
795 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
797 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
798 op
== BRW_AOP_PREDEC
))
810 fs_inst::regs_read(int arg
) const
813 case FS_OPCODE_FB_WRITE
:
814 case SHADER_OPCODE_URB_WRITE_SIMD8
:
815 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
816 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
817 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
818 case SHADER_OPCODE_URB_READ_SIMD8
:
819 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
820 case SHADER_OPCODE_UNTYPED_ATOMIC
:
821 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
822 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
823 case SHADER_OPCODE_TYPED_ATOMIC
:
824 case SHADER_OPCODE_TYPED_SURFACE_READ
:
825 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
826 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
831 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
832 /* The payload is actually stored in src1 */
837 case FS_OPCODE_LINTERP
:
842 case SHADER_OPCODE_LOAD_PAYLOAD
:
843 if (arg
< this->header_size
)
847 case CS_OPCODE_CS_TERMINATE
:
848 case SHADER_OPCODE_BARRIER
:
851 case SHADER_OPCODE_MOV_INDIRECT
:
853 assert(src
[2].file
== IMM
);
854 unsigned region_length
= src
[2].ud
;
856 if (src
[0].file
== FIXED_GRF
) {
857 /* If the start of the region is not register aligned, then
858 * there's some portion of the register that's technically
859 * unread at the beginning.
861 * However, the register allocator works in terms of whole
862 * registers, and does not use subnr. It assumes that the
863 * read starts at the beginning of the register, and extends
864 * regs_read() whole registers beyond that.
866 * To compensate, we extend the region length to include this
867 * unread portion at the beginning.
870 region_length
+= src
[0].subnr
* type_sz(src
[0].type
);
872 return DIV_ROUND_UP(region_length
, REG_SIZE
);
874 assert(!"Invalid register file");
880 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
885 switch (src
[arg
].file
) {
895 return DIV_ROUND_UP(components_read(arg
) *
896 src
[arg
].component_size(exec_size
),
899 unreachable("MRF registers are not allowed as sources");
905 fs_inst::reads_flag() const
911 fs_inst::writes_flag() const
913 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
914 opcode
!= BRW_OPCODE_IF
&&
915 opcode
!= BRW_OPCODE_WHILE
)) ||
916 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
920 * Returns how many MRFs an FS opcode will write over.
922 * Note that this is not the 0 or 1 implied writes in an actual gen
923 * instruction -- the FS opcodes often generate MOVs in addition.
926 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
931 if (inst
->base_mrf
== -1)
934 switch (inst
->opcode
) {
935 case SHADER_OPCODE_RCP
:
936 case SHADER_OPCODE_RSQ
:
937 case SHADER_OPCODE_SQRT
:
938 case SHADER_OPCODE_EXP2
:
939 case SHADER_OPCODE_LOG2
:
940 case SHADER_OPCODE_SIN
:
941 case SHADER_OPCODE_COS
:
942 return 1 * dispatch_width
/ 8;
943 case SHADER_OPCODE_POW
:
944 case SHADER_OPCODE_INT_QUOTIENT
:
945 case SHADER_OPCODE_INT_REMAINDER
:
946 return 2 * dispatch_width
/ 8;
947 case SHADER_OPCODE_TEX
:
949 case SHADER_OPCODE_TXD
:
950 case SHADER_OPCODE_TXF
:
951 case SHADER_OPCODE_TXF_CMS
:
952 case SHADER_OPCODE_TXF_CMS_W
:
953 case SHADER_OPCODE_TXF_MCS
:
954 case SHADER_OPCODE_TG4
:
955 case SHADER_OPCODE_TG4_OFFSET
:
956 case SHADER_OPCODE_TXL
:
957 case SHADER_OPCODE_TXS
:
958 case SHADER_OPCODE_LOD
:
959 case SHADER_OPCODE_SAMPLEINFO
:
961 case FS_OPCODE_FB_WRITE
:
963 case FS_OPCODE_GET_BUFFER_SIZE
:
964 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
965 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
967 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
969 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
971 case SHADER_OPCODE_UNTYPED_ATOMIC
:
972 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
973 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
974 case SHADER_OPCODE_TYPED_ATOMIC
:
975 case SHADER_OPCODE_TYPED_SURFACE_READ
:
976 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
977 case SHADER_OPCODE_URB_WRITE_SIMD8
:
978 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
979 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
980 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
981 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
982 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
983 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
984 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
987 unreachable("not reached");
992 fs_visitor::vgrf(const glsl_type
*const type
)
994 int reg_width
= dispatch_width
/ 8;
995 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
996 brw_type_for_base_type(type
));
999 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1004 this->type
= BRW_REGISTER_TYPE_F
;
1005 this->stride
= (file
== UNIFORM
? 0 : 1);
1008 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1014 this->stride
= (file
== UNIFORM
? 0 : 1);
1017 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1018 * This brings in those uniform definitions
1021 fs_visitor::import_uniforms(fs_visitor
*v
)
1023 this->push_constant_loc
= v
->push_constant_loc
;
1024 this->pull_constant_loc
= v
->pull_constant_loc
;
1025 this->uniforms
= v
->uniforms
;
1026 this->param_size
= v
->param_size
;
1030 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
1031 bool origin_upper_left
)
1033 assert(stage
== MESA_SHADER_FRAGMENT
);
1034 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1035 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
1037 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
1039 /* gl_FragCoord.x */
1040 if (pixel_center_integer
) {
1041 bld
.MOV(wpos
, this->pixel_x
);
1043 bld
.ADD(wpos
, this->pixel_x
, brw_imm_f(0.5f
));
1045 wpos
= offset(wpos
, bld
, 1);
1047 /* gl_FragCoord.y */
1048 if (!flip
&& pixel_center_integer
) {
1049 bld
.MOV(wpos
, this->pixel_y
);
1051 fs_reg pixel_y
= this->pixel_y
;
1052 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
1055 pixel_y
.negate
= true;
1056 offset
+= key
->drawable_height
- 1.0f
;
1059 bld
.ADD(wpos
, pixel_y
, brw_imm_f(offset
));
1061 wpos
= offset(wpos
, bld
, 1);
1063 /* gl_FragCoord.z */
1064 if (devinfo
->gen
>= 6) {
1065 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1067 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1068 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1069 interp_reg(VARYING_SLOT_POS
, 2));
1071 wpos
= offset(wpos
, bld
, 1);
1073 /* gl_FragCoord.w: Already set up in emit_interpolation */
1074 bld
.MOV(wpos
, this->wpos_w
);
1080 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1081 glsl_interp_qualifier interpolation_mode
,
1082 bool is_centroid
, bool is_sample
)
1084 brw_wm_barycentric_interp_mode barycoord_mode
;
1085 if (devinfo
->gen
>= 6) {
1087 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1088 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1090 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1091 } else if (is_sample
) {
1092 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1093 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1095 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1097 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1098 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1100 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1103 /* On Ironlake and below, there is only one interpolation mode.
1104 * Centroid interpolation doesn't mean anything on this hardware --
1105 * there is no multisampling.
1107 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1109 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1110 this->delta_xy
[barycoord_mode
], interp
);
1114 fs_visitor::emit_general_interpolation(fs_reg
*attr
, const char *name
,
1115 const glsl_type
*type
,
1116 glsl_interp_qualifier interpolation_mode
,
1117 int *location
, bool mod_centroid
,
1120 assert(stage
== MESA_SHADER_FRAGMENT
);
1121 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1122 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1124 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1126 *location
== VARYING_SLOT_COL0
|| *location
== VARYING_SLOT_COL1
;
1127 if (key
->flat_shade
&& is_gl_Color
) {
1128 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1130 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1134 if (type
->is_array() || type
->is_matrix()) {
1135 const glsl_type
*elem_type
= glsl_get_array_element(type
);
1136 const unsigned length
= glsl_get_length(type
);
1138 for (unsigned i
= 0; i
< length
; i
++) {
1139 emit_general_interpolation(attr
, name
, elem_type
, interpolation_mode
,
1140 location
, mod_centroid
, mod_sample
);
1142 } else if (type
->is_record()) {
1143 for (unsigned i
= 0; i
< type
->length
; i
++) {
1144 const glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
1145 emit_general_interpolation(attr
, name
, field_type
, interpolation_mode
,
1146 location
, mod_centroid
, mod_sample
);
1149 assert(type
->is_scalar() || type
->is_vector());
1151 if (prog_data
->urb_setup
[*location
] == -1) {
1152 /* If there's no incoming setup data for this slot, don't
1153 * emit interpolation for it.
1155 *attr
= offset(*attr
, bld
, type
->vector_elements
);
1160 attr
->type
= brw_type_for_base_type(type
->get_scalar_type());
1162 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1163 /* Constant interpolation (flat shading) case. The SF has
1164 * handed us defined values in only the constant offset
1165 * field of the setup reg.
1167 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1168 struct brw_reg interp
= interp_reg(*location
, i
);
1169 interp
= suboffset(interp
, 3);
1170 interp
.type
= attr
->type
;
1171 bld
.emit(FS_OPCODE_CINTERP
, *attr
, fs_reg(interp
));
1172 *attr
= offset(*attr
, bld
, 1);
1175 /* Smooth/noperspective interpolation case. */
1176 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1177 struct brw_reg interp
= interp_reg(*location
, i
);
1178 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1179 /* Get the pixel/sample mask into f0 so that we know
1180 * which pixels are lit. Then, for each channel that is
1181 * unlit, replace the centroid data with non-centroid
1184 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1187 inst
= emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1189 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1190 inst
->predicate_inverse
= true;
1191 if (devinfo
->has_pln
)
1192 inst
->no_dd_clear
= true;
1194 inst
= emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1195 mod_centroid
&& !key
->persample_shading
,
1196 mod_sample
|| key
->persample_shading
);
1197 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1198 inst
->predicate_inverse
= false;
1199 if (devinfo
->has_pln
)
1200 inst
->no_dd_check
= true;
1203 emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1204 mod_centroid
&& !key
->persample_shading
,
1205 mod_sample
|| key
->persample_shading
);
1207 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1208 bld
.MUL(*attr
, *attr
, this->pixel_w
);
1210 *attr
= offset(*attr
, bld
, 1);
1218 fs_visitor::emit_frontfacing_interpolation()
1220 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1222 if (devinfo
->gen
>= 6) {
1223 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1224 * a boolean result from this (~0/true or 0/false).
1226 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1227 * this task in only one instruction:
1228 * - a negation source modifier will flip the bit; and
1229 * - a W -> D type conversion will sign extend the bit into the high
1230 * word of the destination.
1232 * An ASR 15 fills the low word of the destination.
1234 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1237 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1239 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1240 * a boolean result from this (1/true or 0/false).
1242 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1243 * the negation source modifier to flip it. Unfortunately the SHR
1244 * instruction only operates on UD (or D with an abs source modifier)
1245 * sources without negation.
1247 * Instead, use ASR (which will give ~0/true or 0/false).
1249 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1252 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1259 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1261 assert(stage
== MESA_SHADER_FRAGMENT
);
1262 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1263 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1265 if (key
->compute_pos_offset
) {
1266 /* Convert int_sample_pos to floating point */
1267 bld
.MOV(dst
, int_sample_pos
);
1268 /* Scale to the range [0, 1] */
1269 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1272 /* From ARB_sample_shading specification:
1273 * "When rendering to a non-multisample buffer, or if multisample
1274 * rasterization is disabled, gl_SamplePosition will always be
1277 bld
.MOV(dst
, brw_imm_f(0.5f
));
1282 fs_visitor::emit_samplepos_setup()
1284 assert(devinfo
->gen
>= 6);
1286 const fs_builder abld
= bld
.annotate("compute sample position");
1287 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1289 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1290 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1292 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1293 * mode will be enabled.
1295 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1296 * R31.1:0 Position Offset X/Y for Slot[3:0]
1297 * R31.3:2 Position Offset X/Y for Slot[7:4]
1300 * The X, Y sample positions come in as bytes in thread payload. So, read
1301 * the positions using vstride=16, width=8, hstride=2.
1303 struct brw_reg sample_pos_reg
=
1304 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1305 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1307 if (dispatch_width
== 8) {
1308 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1310 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1311 abld
.half(1).MOV(half(int_sample_x
, 1),
1312 fs_reg(suboffset(sample_pos_reg
, 16)));
1314 /* Compute gl_SamplePosition.x */
1315 compute_sample_position(pos
, int_sample_x
);
1316 pos
= offset(pos
, abld
, 1);
1317 if (dispatch_width
== 8) {
1318 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1320 abld
.half(0).MOV(half(int_sample_y
, 0),
1321 fs_reg(suboffset(sample_pos_reg
, 1)));
1322 abld
.half(1).MOV(half(int_sample_y
, 1),
1323 fs_reg(suboffset(sample_pos_reg
, 17)));
1325 /* Compute gl_SamplePosition.y */
1326 compute_sample_position(pos
, int_sample_y
);
1331 fs_visitor::emit_sampleid_setup()
1333 assert(stage
== MESA_SHADER_FRAGMENT
);
1334 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1335 assert(devinfo
->gen
>= 6);
1337 const fs_builder abld
= bld
.annotate("compute sample id");
1338 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1340 if (key
->compute_sample_id
) {
1341 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1343 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1345 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1346 * 8x multisampling, subspan 0 will represent sample N (where N
1347 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1348 * 7. We can find the value of N by looking at R0.0 bits 7:6
1349 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1350 * (since samples are always delivered in pairs). That is, we
1351 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1352 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1353 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1354 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1355 * populating a temporary variable with the sequence (0, 1, 2, 3),
1356 * and then reading from it using vstride=1, width=4, hstride=0.
1357 * These computations hold good for 4x multisampling as well.
1359 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1360 * the first four slots are sample 0 of subspan 0; the next four
1361 * are sample 1 of subspan 0; the third group is sample 0 of
1362 * subspan 1, and finally sample 1 of subspan 1.
1365 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1366 * accomodate 16x MSAA.
1368 unsigned sspi_mask
= devinfo
->gen
>= 9 ? 0x1c0 : 0xc0;
1370 abld
.exec_all().group(1, 0)
1371 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1372 brw_imm_ud(sspi_mask
));
1373 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1375 /* This works for both SIMD8 and SIMD16 */
1376 abld
.exec_all().group(4, 0)
1377 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1379 /* This special instruction takes care of setting vstride=1,
1380 * width=4, hstride=0 of t2 during an ADD instruction.
1382 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1384 /* As per GL_ARB_sample_shading specification:
1385 * "When rendering to a non-multisample buffer, or if multisample
1386 * rasterization is disabled, gl_SampleID will always be zero."
1388 abld
.MOV(*reg
, brw_imm_d(0));
1395 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1397 if (!src
.abs
&& !src
.negate
)
1400 fs_reg temp
= bld
.vgrf(src
.type
);
1407 fs_visitor::emit_discard_jump()
1409 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1411 /* For performance, after a discard, jump to the end of the
1412 * shader if all relevant channels have been discarded.
1414 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1415 discard_jump
->flag_subreg
= 1;
1417 discard_jump
->predicate
= (dispatch_width
== 8)
1418 ? BRW_PREDICATE_ALIGN1_ANY8H
1419 : BRW_PREDICATE_ALIGN1_ANY16H
;
1420 discard_jump
->predicate_inverse
= true;
1424 fs_visitor::emit_gs_thread_end()
1426 assert(stage
== MESA_SHADER_GEOMETRY
);
1428 struct brw_gs_prog_data
*gs_prog_data
=
1429 (struct brw_gs_prog_data
*) prog_data
;
1431 if (gs_compile
->control_data_header_size_bits
> 0) {
1432 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1435 const fs_builder abld
= bld
.annotate("thread end");
1438 if (gs_prog_data
->static_vertex_count
!= -1) {
1439 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1440 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1441 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1442 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1443 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1446 /* Delete now dead instructions. */
1447 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1453 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1457 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1458 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1459 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1462 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1463 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1464 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1465 sources
[1] = this->final_gs_vertex_count
;
1466 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1467 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1475 fs_visitor::assign_curb_setup()
1477 if (dispatch_width
== 8) {
1478 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1480 if (stage
== MESA_SHADER_FRAGMENT
) {
1481 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1482 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1483 } else if (stage
== MESA_SHADER_COMPUTE
) {
1484 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1485 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1487 unreachable("Unsupported shader type!");
1491 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1493 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1494 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1495 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1496 if (inst
->src
[i
].file
== UNIFORM
) {
1497 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1499 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1500 constant_nr
= push_constant_loc
[uniform_nr
];
1502 /* Section 5.11 of the OpenGL 4.1 spec says:
1503 * "Out-of-bounds reads return undefined values, which include
1504 * values from other variables of the active program or zero."
1505 * Just return the first push constant.
1510 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1513 brw_reg
.abs
= inst
->src
[i
].abs
;
1514 brw_reg
.negate
= inst
->src
[i
].negate
;
1516 assert(inst
->src
[i
].stride
== 0);
1517 inst
->src
[i
] = byte_offset(
1518 retype(brw_reg
, inst
->src
[i
].type
),
1519 inst
->src
[i
].subreg_offset
);
1524 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1525 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1529 fs_visitor::calculate_urb_setup()
1531 assert(stage
== MESA_SHADER_FRAGMENT
);
1532 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1533 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1535 memset(prog_data
->urb_setup
, -1,
1536 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1539 /* Figure out where each of the incoming setup attributes lands. */
1540 if (devinfo
->gen
>= 6) {
1541 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1542 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1543 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1544 * first 16 varying inputs, so we can put them wherever we want.
1545 * Just put them in order.
1547 * This is useful because it means that (a) inputs not used by the
1548 * fragment shader won't take up valuable register space, and (b) we
1549 * won't have to recompile the fragment shader if it gets paired with
1550 * a different vertex (or geometry) shader.
1552 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1553 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1554 BITFIELD64_BIT(i
)) {
1555 prog_data
->urb_setup
[i
] = urb_next
++;
1559 bool include_vue_header
=
1560 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1562 /* We have enough input varyings that the SF/SBE pipeline stage can't
1563 * arbitrarily rearrange them to suit our whim; we have to put them
1564 * in an order that matches the output of the previous pipeline stage
1565 * (geometry or vertex shader).
1567 struct brw_vue_map prev_stage_vue_map
;
1568 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1569 key
->input_slots_valid
,
1570 nir
->info
.separate_shader
);
1572 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1574 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1575 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1577 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1578 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1579 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1580 BITFIELD64_BIT(varying
))) {
1581 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1584 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1587 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1588 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1589 /* Point size is packed into the header, not as a general attribute */
1590 if (i
== VARYING_SLOT_PSIZ
)
1593 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1594 /* The back color slot is skipped when the front color is
1595 * also written to. In addition, some slots can be
1596 * written in the vertex shader and not read in the
1597 * fragment shader. So the register number must always be
1598 * incremented, mapped or not.
1600 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1601 prog_data
->urb_setup
[i
] = urb_next
;
1607 * It's a FS only attribute, and we did interpolation for this attribute
1608 * in SF thread. So, count it here, too.
1610 * See compile_sf_prog() for more info.
1612 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1613 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1616 prog_data
->num_varying_inputs
= urb_next
;
1620 fs_visitor::assign_urb_setup()
1622 assert(stage
== MESA_SHADER_FRAGMENT
);
1623 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1625 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1627 /* Offset all the urb_setup[] index by the actual position of the
1628 * setup regs, now that the location of the constants has been chosen.
1630 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1631 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1632 assert(inst
->src
[1].file
== FIXED_GRF
);
1633 inst
->src
[1].nr
+= urb_start
;
1636 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1637 assert(inst
->src
[0].file
== FIXED_GRF
);
1638 inst
->src
[0].nr
+= urb_start
;
1642 /* Each attribute is 4 setup channels, each of which is half a reg. */
1643 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1647 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1649 for (int i
= 0; i
< inst
->sources
; i
++) {
1650 if (inst
->src
[i
].file
== ATTR
) {
1651 int grf
= payload
.num_regs
+
1652 prog_data
->curb_read_length
+
1654 inst
->src
[i
].reg_offset
;
1656 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : inst
->exec_size
;
1657 struct brw_reg reg
=
1658 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1659 inst
->src
[i
].subreg_offset
),
1660 inst
->exec_size
* inst
->src
[i
].stride
,
1661 width
, inst
->src
[i
].stride
);
1662 reg
.abs
= inst
->src
[i
].abs
;
1663 reg
.negate
= inst
->src
[i
].negate
;
1671 fs_visitor::assign_vs_urb_setup()
1673 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1675 assert(stage
== MESA_SHADER_VERTEX
);
1677 /* Each attribute is 4 regs. */
1678 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attributes
;
1680 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1682 /* Rewrite all ATTR file references to the hw grf that they land in. */
1683 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1684 convert_attr_sources_to_hw_regs(inst
);
1689 fs_visitor::assign_tes_urb_setup()
1691 assert(stage
== MESA_SHADER_TESS_EVAL
);
1693 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1695 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1697 /* Rewrite all ATTR file references to HW_REGs. */
1698 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1699 convert_attr_sources_to_hw_regs(inst
);
1704 fs_visitor::assign_gs_urb_setup()
1706 assert(stage
== MESA_SHADER_GEOMETRY
);
1708 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1710 first_non_payload_grf
+=
1711 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1713 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1714 /* Rewrite all ATTR file references to GRFs. */
1715 convert_attr_sources_to_hw_regs(inst
);
1721 * Split large virtual GRFs into separate components if we can.
1723 * This is mostly duplicated with what brw_fs_vector_splitting does,
1724 * but that's really conservative because it's afraid of doing
1725 * splitting that doesn't result in real progress after the rest of
1726 * the optimization phases, which would cause infinite looping in
1727 * optimization. We can do it once here, safely. This also has the
1728 * opportunity to split interpolated values, or maybe even uniforms,
1729 * which we don't have at the IR level.
1731 * We want to split, because virtual GRFs are what we register
1732 * allocate and spill (due to contiguousness requirements for some
1733 * instructions), and they're what we naturally generate in the
1734 * codegen process, but most virtual GRFs don't actually need to be
1735 * contiguous sets of GRFs. If we split, we'll end up with reduced
1736 * live intervals and better dead code elimination and coalescing.
1739 fs_visitor::split_virtual_grfs()
1741 int num_vars
= this->alloc
.count
;
1743 /* Count the total number of registers */
1745 int vgrf_to_reg
[num_vars
];
1746 for (int i
= 0; i
< num_vars
; i
++) {
1747 vgrf_to_reg
[i
] = reg_count
;
1748 reg_count
+= alloc
.sizes
[i
];
1751 /* An array of "split points". For each register slot, this indicates
1752 * if this slot can be separated from the previous slot. Every time an
1753 * instruction uses multiple elements of a register (as a source or
1754 * destination), we mark the used slots as inseparable. Then we go
1755 * through and split the registers into the smallest pieces we can.
1757 bool split_points
[reg_count
];
1758 memset(split_points
, 0, sizeof(split_points
));
1760 /* Mark all used registers as fully splittable */
1761 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1762 if (inst
->dst
.file
== VGRF
) {
1763 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1764 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1765 split_points
[reg
+ j
] = true;
1768 for (int i
= 0; i
< inst
->sources
; i
++) {
1769 if (inst
->src
[i
].file
== VGRF
) {
1770 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1771 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1772 split_points
[reg
+ j
] = true;
1777 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1778 if (inst
->dst
.file
== VGRF
) {
1779 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1780 for (int j
= 1; j
< inst
->regs_written
; j
++)
1781 split_points
[reg
+ j
] = false;
1783 for (int i
= 0; i
< inst
->sources
; i
++) {
1784 if (inst
->src
[i
].file
== VGRF
) {
1785 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1786 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1787 split_points
[reg
+ j
] = false;
1792 int new_virtual_grf
[reg_count
];
1793 int new_reg_offset
[reg_count
];
1796 for (int i
= 0; i
< num_vars
; i
++) {
1797 /* The first one should always be 0 as a quick sanity check. */
1798 assert(split_points
[reg
] == false);
1801 new_reg_offset
[reg
] = 0;
1806 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1807 /* If this is a split point, reset the offset to 0 and allocate a
1808 * new virtual GRF for the previous offset many registers
1810 if (split_points
[reg
]) {
1811 assert(offset
<= MAX_VGRF_SIZE
);
1812 int grf
= alloc
.allocate(offset
);
1813 for (int k
= reg
- offset
; k
< reg
; k
++)
1814 new_virtual_grf
[k
] = grf
;
1817 new_reg_offset
[reg
] = offset
;
1822 /* The last one gets the original register number */
1823 assert(offset
<= MAX_VGRF_SIZE
);
1824 alloc
.sizes
[i
] = offset
;
1825 for (int k
= reg
- offset
; k
< reg
; k
++)
1826 new_virtual_grf
[k
] = i
;
1828 assert(reg
== reg_count
);
1830 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1831 if (inst
->dst
.file
== VGRF
) {
1832 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1833 inst
->dst
.nr
= new_virtual_grf
[reg
];
1834 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1835 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1837 for (int i
= 0; i
< inst
->sources
; i
++) {
1838 if (inst
->src
[i
].file
== VGRF
) {
1839 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1840 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1841 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1842 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1846 invalidate_live_intervals();
1850 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1852 * During code generation, we create tons of temporary variables, many of
1853 * which get immediately killed and are never used again. Yet, in later
1854 * optimization and analysis passes, such as compute_live_intervals, we need
1855 * to loop over all the virtual GRFs. Compacting them can save a lot of
1859 fs_visitor::compact_virtual_grfs()
1861 bool progress
= false;
1862 int remap_table
[this->alloc
.count
];
1863 memset(remap_table
, -1, sizeof(remap_table
));
1865 /* Mark which virtual GRFs are used. */
1866 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1867 if (inst
->dst
.file
== VGRF
)
1868 remap_table
[inst
->dst
.nr
] = 0;
1870 for (int i
= 0; i
< inst
->sources
; i
++) {
1871 if (inst
->src
[i
].file
== VGRF
)
1872 remap_table
[inst
->src
[i
].nr
] = 0;
1876 /* Compact the GRF arrays. */
1878 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1879 if (remap_table
[i
] == -1) {
1880 /* We just found an unused register. This means that we are
1881 * actually going to compact something.
1885 remap_table
[i
] = new_index
;
1886 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1887 invalidate_live_intervals();
1892 this->alloc
.count
= new_index
;
1894 /* Patch all the instructions to use the newly renumbered registers */
1895 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1896 if (inst
->dst
.file
== VGRF
)
1897 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1899 for (int i
= 0; i
< inst
->sources
; i
++) {
1900 if (inst
->src
[i
].file
== VGRF
)
1901 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1905 /* Patch all the references to delta_xy, since they're used in register
1906 * allocation. If they're unused, switch them to BAD_FILE so we don't
1907 * think some random VGRF is delta_xy.
1909 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1910 if (delta_xy
[i
].file
== VGRF
) {
1911 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1912 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1914 delta_xy
[i
].file
= BAD_FILE
;
1923 * Assign UNIFORM file registers to either push constants or pull constants.
1925 * We allow a fragment shader to have more than the specified minimum
1926 * maximum number of fragment shader uniform components (64). If
1927 * there are too many of these, they'd fill up all of register space.
1928 * So, this will push some of them out to the pull constant buffer and
1929 * update the program to load them. We also use pull constants for all
1930 * indirect constant loads because we don't support indirect accesses in
1934 fs_visitor::assign_constant_locations()
1936 /* Only the first compile gets to decide on locations. */
1937 if (dispatch_width
!= min_dispatch_width
)
1940 unsigned int num_pull_constants
= 0;
1942 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1943 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1945 bool is_live
[uniforms
];
1946 memset(is_live
, 0, sizeof(is_live
));
1948 /* First, we walk through the instructions and do two things:
1950 * 1) Figure out which uniforms are live.
1952 * 2) Find all indirect access of uniform arrays and flag them as needing
1953 * to go into the pull constant buffer.
1955 * Note that we don't move constant-indexed accesses to arrays. No
1956 * testing has been done of the performance impact of this choice.
1958 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1959 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1960 if (inst
->src
[i
].file
!= UNIFORM
)
1963 if (inst
->src
[i
].reladdr
) {
1964 int uniform
= inst
->src
[i
].nr
;
1966 /* If this array isn't already present in the pull constant buffer,
1969 if (pull_constant_loc
[uniform
] == -1) {
1970 assert(param_size
[uniform
]);
1971 for (int j
= 0; j
< param_size
[uniform
]; j
++)
1972 pull_constant_loc
[uniform
+ j
] = num_pull_constants
++;
1975 /* Mark the the one accessed uniform as live */
1976 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1977 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1978 is_live
[constant_nr
] = true;
1983 /* Only allow 16 registers (128 uniform components) as push constants.
1985 * Just demote the end of the list. We could probably do better
1986 * here, demoting things that are rarely used in the program first.
1988 * If changing this value, note the limitation about total_regs in
1991 unsigned int max_push_components
= 16 * 8;
1992 unsigned int num_push_constants
= 0;
1994 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1996 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1997 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1998 /* This UNIFORM register is either dead, or has already been demoted
1999 * to a pull const. Mark it as no longer living in the param[] array.
2001 push_constant_loc
[i
] = -1;
2005 if (num_push_constants
< max_push_components
) {
2006 /* Retain as a push constant. Record the location in the params[]
2009 push_constant_loc
[i
] = num_push_constants
++;
2011 /* Demote to a pull constant. */
2012 push_constant_loc
[i
] = -1;
2013 pull_constant_loc
[i
] = num_pull_constants
++;
2017 stage_prog_data
->nr_params
= num_push_constants
;
2018 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2020 /* Up until now, the param[] array has been indexed by reg + reg_offset
2021 * of UNIFORM registers. Move pull constants into pull_param[] and
2022 * condense param[] to only contain the uniforms we chose to push.
2024 * NOTE: Because we are condensing the params[] array, we know that
2025 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2026 * having to make a copy.
2028 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2029 const gl_constant_value
*value
= stage_prog_data
->param
[i
];
2031 if (pull_constant_loc
[i
] != -1) {
2032 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2033 } else if (push_constant_loc
[i
] != -1) {
2034 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2040 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2041 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2044 fs_visitor::demote_pull_constants()
2046 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2047 for (int i
= 0; i
< inst
->sources
; i
++) {
2048 if (inst
->src
[i
].file
!= UNIFORM
)
2052 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2053 if (location
>= uniforms
) /* Out of bounds access */
2056 pull_index
= pull_constant_loc
[location
];
2058 if (pull_index
== -1)
2061 /* Set up the annotation tracking for new generated instructions. */
2062 const fs_builder
ibld(this, block
, inst
);
2063 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2064 fs_reg dst
= vgrf(glsl_type::float_type
);
2066 assert(inst
->src
[i
].stride
== 0);
2068 /* Generate a pull load into dst. */
2069 if (inst
->src
[i
].reladdr
) {
2070 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
2072 *inst
->src
[i
].reladdr
,
2074 inst
->src
[i
].reladdr
= NULL
;
2075 inst
->src
[i
].stride
= 1;
2077 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2078 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2079 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2080 dst
, brw_imm_ud(index
), offset
);
2081 inst
->src
[i
].set_smear(pull_index
& 3);
2083 brw_mark_surface_used(prog_data
, index
);
2085 /* Rewrite the instruction to use the temporary VGRF. */
2086 inst
->src
[i
].file
= VGRF
;
2087 inst
->src
[i
].nr
= dst
.nr
;
2088 inst
->src
[i
].reg_offset
= 0;
2091 invalidate_live_intervals();
2095 fs_visitor::opt_algebraic()
2097 bool progress
= false;
2099 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2100 switch (inst
->opcode
) {
2101 case BRW_OPCODE_MOV
:
2102 if (inst
->src
[0].file
!= IMM
)
2105 if (inst
->saturate
) {
2106 if (inst
->dst
.type
!= inst
->src
[0].type
)
2107 assert(!"unimplemented: saturate mixed types");
2109 if (brw_saturate_immediate(inst
->dst
.type
,
2110 &inst
->src
[0].as_brw_reg())) {
2111 inst
->saturate
= false;
2117 case BRW_OPCODE_MUL
:
2118 if (inst
->src
[1].file
!= IMM
)
2122 if (inst
->src
[1].is_one()) {
2123 inst
->opcode
= BRW_OPCODE_MOV
;
2124 inst
->src
[1] = reg_undef
;
2130 if (inst
->src
[1].is_negative_one()) {
2131 inst
->opcode
= BRW_OPCODE_MOV
;
2132 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2133 inst
->src
[1] = reg_undef
;
2139 if (inst
->src
[1].is_zero()) {
2140 inst
->opcode
= BRW_OPCODE_MOV
;
2141 inst
->src
[0] = inst
->src
[1];
2142 inst
->src
[1] = reg_undef
;
2147 if (inst
->src
[0].file
== IMM
) {
2148 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2149 inst
->opcode
= BRW_OPCODE_MOV
;
2150 inst
->src
[0].f
*= inst
->src
[1].f
;
2151 inst
->src
[1] = reg_undef
;
2156 case BRW_OPCODE_ADD
:
2157 if (inst
->src
[1].file
!= IMM
)
2161 if (inst
->src
[1].is_zero()) {
2162 inst
->opcode
= BRW_OPCODE_MOV
;
2163 inst
->src
[1] = reg_undef
;
2168 if (inst
->src
[0].file
== IMM
) {
2169 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2170 inst
->opcode
= BRW_OPCODE_MOV
;
2171 inst
->src
[0].f
+= inst
->src
[1].f
;
2172 inst
->src
[1] = reg_undef
;
2178 if (inst
->src
[0].equals(inst
->src
[1])) {
2179 inst
->opcode
= BRW_OPCODE_MOV
;
2180 inst
->src
[1] = reg_undef
;
2185 case BRW_OPCODE_LRP
:
2186 if (inst
->src
[1].equals(inst
->src
[2])) {
2187 inst
->opcode
= BRW_OPCODE_MOV
;
2188 inst
->src
[0] = inst
->src
[1];
2189 inst
->src
[1] = reg_undef
;
2190 inst
->src
[2] = reg_undef
;
2195 case BRW_OPCODE_CMP
:
2196 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2198 inst
->src
[0].negate
&&
2199 inst
->src
[1].is_zero()) {
2200 inst
->src
[0].abs
= false;
2201 inst
->src
[0].negate
= false;
2202 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2207 case BRW_OPCODE_SEL
:
2208 if (inst
->src
[0].equals(inst
->src
[1])) {
2209 inst
->opcode
= BRW_OPCODE_MOV
;
2210 inst
->src
[1] = reg_undef
;
2211 inst
->predicate
= BRW_PREDICATE_NONE
;
2212 inst
->predicate_inverse
= false;
2214 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2215 switch (inst
->conditional_mod
) {
2216 case BRW_CONDITIONAL_LE
:
2217 case BRW_CONDITIONAL_L
:
2218 switch (inst
->src
[1].type
) {
2219 case BRW_REGISTER_TYPE_F
:
2220 if (inst
->src
[1].f
>= 1.0f
) {
2221 inst
->opcode
= BRW_OPCODE_MOV
;
2222 inst
->src
[1] = reg_undef
;
2223 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2231 case BRW_CONDITIONAL_GE
:
2232 case BRW_CONDITIONAL_G
:
2233 switch (inst
->src
[1].type
) {
2234 case BRW_REGISTER_TYPE_F
:
2235 if (inst
->src
[1].f
<= 0.0f
) {
2236 inst
->opcode
= BRW_OPCODE_MOV
;
2237 inst
->src
[1] = reg_undef
;
2238 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2250 case BRW_OPCODE_MAD
:
2251 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2252 inst
->opcode
= BRW_OPCODE_MOV
;
2253 inst
->src
[1] = reg_undef
;
2254 inst
->src
[2] = reg_undef
;
2256 } else if (inst
->src
[0].is_zero()) {
2257 inst
->opcode
= BRW_OPCODE_MUL
;
2258 inst
->src
[0] = inst
->src
[2];
2259 inst
->src
[2] = reg_undef
;
2261 } else if (inst
->src
[1].is_one()) {
2262 inst
->opcode
= BRW_OPCODE_ADD
;
2263 inst
->src
[1] = inst
->src
[2];
2264 inst
->src
[2] = reg_undef
;
2266 } else if (inst
->src
[2].is_one()) {
2267 inst
->opcode
= BRW_OPCODE_ADD
;
2268 inst
->src
[2] = reg_undef
;
2270 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2271 inst
->opcode
= BRW_OPCODE_ADD
;
2272 inst
->src
[1].f
*= inst
->src
[2].f
;
2273 inst
->src
[2] = reg_undef
;
2277 case SHADER_OPCODE_RCP
: {
2278 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2279 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2280 if (inst
->src
[0].equals(prev
->dst
)) {
2281 inst
->opcode
= SHADER_OPCODE_RSQ
;
2282 inst
->src
[0] = prev
->src
[0];
2288 case SHADER_OPCODE_BROADCAST
:
2289 if (is_uniform(inst
->src
[0])) {
2290 inst
->opcode
= BRW_OPCODE_MOV
;
2292 inst
->force_writemask_all
= true;
2294 } else if (inst
->src
[1].file
== IMM
) {
2295 inst
->opcode
= BRW_OPCODE_MOV
;
2296 inst
->src
[0] = component(inst
->src
[0],
2299 inst
->force_writemask_all
= true;
2308 /* Swap if src[0] is immediate. */
2309 if (progress
&& inst
->is_commutative()) {
2310 if (inst
->src
[0].file
== IMM
) {
2311 fs_reg tmp
= inst
->src
[1];
2312 inst
->src
[1] = inst
->src
[0];
2321 * Optimize sample messages that have constant zero values for the trailing
2322 * texture coordinates. We can just reduce the message length for these
2323 * instructions instead of reserving a register for it. Trailing parameters
2324 * that aren't sent default to zero anyway. This will cause the dead code
2325 * eliminator to remove the MOV instruction that would otherwise be emitted to
2326 * set up the zero value.
2329 fs_visitor::opt_zero_samples()
2331 /* Gen4 infers the texturing opcode based on the message length so we can't
2334 if (devinfo
->gen
< 5)
2337 bool progress
= false;
2339 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2340 if (!inst
->is_tex())
2343 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2345 if (load_payload
->is_head_sentinel() ||
2346 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2349 /* We don't want to remove the message header or the first parameter.
2350 * Removing the first parameter is not allowed, see the Haswell PRM
2351 * volume 7, page 149:
2353 * "Parameter 0 is required except for the sampleinfo message, which
2354 * has no parameter 0"
2356 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2357 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2358 (inst
->exec_size
/ 8) +
2359 inst
->header_size
- 1].is_zero()) {
2360 inst
->mlen
-= inst
->exec_size
/ 8;
2366 invalidate_live_intervals();
2372 * Optimize sample messages which are followed by the final RT write.
2374 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2375 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2376 * final texturing results copied to the framebuffer write payload and modify
2377 * them to write to the framebuffer directly.
2380 fs_visitor::opt_sampler_eot()
2382 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2384 if (stage
!= MESA_SHADER_FRAGMENT
)
2387 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2390 /* FINISHME: It should be possible to implement this optimization when there
2391 * are multiple drawbuffers.
2393 if (key
->nr_color_regions
!= 1)
2396 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2397 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2398 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2399 assert(fb_write
->eot
);
2400 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2402 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2404 /* There wasn't one; nothing to do. */
2405 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2408 /* 3D Sampler » Messages » Message Format
2410 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2411 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2413 if (tex_inst
->opcode
== SHADER_OPCODE_TXS
||
2414 tex_inst
->opcode
== SHADER_OPCODE_SAMPLEINFO
||
2415 tex_inst
->opcode
== SHADER_OPCODE_LOD
||
2416 tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2417 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2420 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2421 * It's very likely to be the previous instruction.
2423 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2424 if (load_payload
->is_head_sentinel() ||
2425 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2428 assert(!tex_inst
->eot
); /* We can't get here twice */
2429 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2431 const fs_builder
ibld(this, block
, tex_inst
);
2433 tex_inst
->offset
|= fb_write
->target
<< 24;
2434 tex_inst
->eot
= true;
2435 tex_inst
->dst
= ibld
.null_reg_ud();
2436 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2438 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2439 * to create a new LOAD_PAYLOAD command with the same sources and a space
2440 * saved for the header. Using a new destination register not only makes sure
2441 * we have enough space, but it will make sure the dead code eliminator kills
2442 * the instruction that this will replace.
2444 if (tex_inst
->header_size
!= 0)
2447 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2448 load_payload
->sources
+ 1);
2449 fs_reg
*new_sources
=
2450 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2452 new_sources
[0] = fs_reg();
2453 for (int i
= 0; i
< load_payload
->sources
; i
++)
2454 new_sources
[i
+1] = load_payload
->src
[i
];
2456 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2457 * requires a lot of information about the sources to appropriately figure
2458 * out the number of registers needed to be used. Given this stage in our
2459 * optimization, we may not have the appropriate GRFs required by
2460 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2461 * manually emit the instruction.
2463 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2464 load_payload
->exec_size
,
2467 load_payload
->sources
+ 1);
2469 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2470 new_load_payload
->header_size
= 1;
2472 tex_inst
->header_size
= 1;
2473 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2474 tex_inst
->src
[0] = send_header
;
2480 fs_visitor::opt_register_renaming()
2482 bool progress
= false;
2485 int remap
[alloc
.count
];
2486 memset(remap
, -1, sizeof(int) * alloc
.count
);
2488 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2489 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2491 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2492 inst
->opcode
== BRW_OPCODE_WHILE
) {
2496 /* Rewrite instruction sources. */
2497 for (int i
= 0; i
< inst
->sources
; i
++) {
2498 if (inst
->src
[i
].file
== VGRF
&&
2499 remap
[inst
->src
[i
].nr
] != -1 &&
2500 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2501 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2506 const int dst
= inst
->dst
.nr
;
2509 inst
->dst
.file
== VGRF
&&
2510 alloc
.sizes
[inst
->dst
.nr
] == inst
->exec_size
/ 8 &&
2511 !inst
->is_partial_write()) {
2512 if (remap
[dst
] == -1) {
2515 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2516 inst
->dst
.nr
= remap
[dst
];
2519 } else if (inst
->dst
.file
== VGRF
&&
2521 remap
[dst
] != dst
) {
2522 inst
->dst
.nr
= remap
[dst
];
2528 invalidate_live_intervals();
2530 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2531 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2532 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2541 * Remove redundant or useless discard jumps.
2543 * For example, we can eliminate jumps in the following sequence:
2545 * discard-jump (redundant with the next jump)
2546 * discard-jump (useless; jumps to the next instruction)
2550 fs_visitor::opt_redundant_discard_jumps()
2552 bool progress
= false;
2554 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2556 fs_inst
*placeholder_halt
= NULL
;
2557 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2558 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2559 placeholder_halt
= inst
;
2564 if (!placeholder_halt
)
2567 /* Delete any HALTs immediately before the placeholder halt. */
2568 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2569 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2570 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2571 prev
->remove(last_bblock
);
2576 invalidate_live_intervals();
2582 fs_visitor::compute_to_mrf()
2584 bool progress
= false;
2587 /* No MRFs on Gen >= 7. */
2588 if (devinfo
->gen
>= 7)
2591 calculate_live_intervals();
2593 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2597 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2598 inst
->is_partial_write() ||
2599 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2600 inst
->dst
.type
!= inst
->src
[0].type
||
2601 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2602 !inst
->src
[0].is_contiguous() ||
2603 inst
->src
[0].subreg_offset
)
2606 /* Work out which hardware MRF registers are written by this
2609 int mrf_low
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2611 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2612 mrf_high
= mrf_low
+ 4;
2613 } else if (inst
->exec_size
== 16) {
2614 mrf_high
= mrf_low
+ 1;
2619 /* Can't compute-to-MRF this GRF if someone else was going to
2622 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2625 /* Found a move of a GRF to a MRF. Let's see if we can go
2626 * rewrite the thing that made this GRF to write into the MRF.
2628 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2629 if (scan_inst
->dst
.file
== VGRF
&&
2630 scan_inst
->dst
.nr
== inst
->src
[0].nr
) {
2631 /* Found the last thing to write our reg we want to turn
2632 * into a compute-to-MRF.
2635 /* If this one instruction didn't populate all the
2636 * channels, bail. We might be able to rewrite everything
2637 * that writes that reg, but it would require smarter
2638 * tracking to delay the rewriting until complete success.
2640 if (scan_inst
->is_partial_write())
2643 /* Things returning more than one register would need us to
2644 * understand coalescing out more than one MOV at a time.
2646 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2649 /* SEND instructions can't have MRF as a destination. */
2650 if (scan_inst
->mlen
)
2653 if (devinfo
->gen
== 6) {
2654 /* gen6 math instructions must have the destination be
2655 * GRF, so no compute-to-MRF for them.
2657 if (scan_inst
->is_math()) {
2662 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2663 /* Found the creator of our MRF's source value. */
2664 scan_inst
->dst
.file
= MRF
;
2665 scan_inst
->dst
.nr
= inst
->dst
.nr
;
2666 scan_inst
->saturate
|= inst
->saturate
;
2667 inst
->remove(block
);
2673 /* We don't handle control flow here. Most computation of
2674 * values that end up in MRFs are shortly before the MRF
2677 if (block
->start() == scan_inst
)
2680 /* You can't read from an MRF, so if someone else reads our
2681 * MRF's source GRF that we wanted to rewrite, that stops us.
2683 bool interfered
= false;
2684 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2685 if (scan_inst
->src
[i
].file
== VGRF
&&
2686 scan_inst
->src
[i
].nr
== inst
->src
[0].nr
&&
2687 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2694 if (scan_inst
->dst
.file
== MRF
) {
2695 /* If somebody else writes our MRF here, we can't
2696 * compute-to-MRF before that.
2698 int scan_mrf_low
= scan_inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2701 if (scan_inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2702 scan_mrf_high
= scan_mrf_low
+ 4;
2703 } else if (scan_inst
->exec_size
== 16) {
2704 scan_mrf_high
= scan_mrf_low
+ 1;
2706 scan_mrf_high
= scan_mrf_low
;
2709 if (mrf_low
== scan_mrf_low
||
2710 mrf_low
== scan_mrf_high
||
2711 mrf_high
== scan_mrf_low
||
2712 mrf_high
== scan_mrf_high
) {
2717 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2718 /* Found a SEND instruction, which means that there are
2719 * live values in MRFs from base_mrf to base_mrf +
2720 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2723 if (mrf_low
>= scan_inst
->base_mrf
&&
2724 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2727 if (mrf_high
>= scan_inst
->base_mrf
&&
2728 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2736 invalidate_live_intervals();
2742 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2743 * flow. We could probably do better here with some form of divergence
2747 fs_visitor::eliminate_find_live_channel()
2749 bool progress
= false;
2752 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2753 switch (inst
->opcode
) {
2759 case BRW_OPCODE_ENDIF
:
2760 case BRW_OPCODE_WHILE
:
2764 case FS_OPCODE_DISCARD_JUMP
:
2765 /* This can potentially make control flow non-uniform until the end
2770 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2772 inst
->opcode
= BRW_OPCODE_MOV
;
2773 inst
->src
[0] = brw_imm_ud(0u);
2775 inst
->force_writemask_all
= true;
2789 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2790 * instructions to FS_OPCODE_REP_FB_WRITE.
2793 fs_visitor::emit_repclear_shader()
2795 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2797 int color_mrf
= base_mrf
+ 2;
2799 fs_inst
*mov
= bld
.exec_all().group(4, 0)
2800 .MOV(brw_message_reg(color_mrf
),
2801 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2804 if (key
->nr_color_regions
== 1) {
2805 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2806 write
->saturate
= key
->clamp_fragment_color
;
2807 write
->base_mrf
= color_mrf
;
2809 write
->header_size
= 0;
2812 assume(key
->nr_color_regions
> 0);
2813 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2814 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2815 write
->saturate
= key
->clamp_fragment_color
;
2816 write
->base_mrf
= base_mrf
;
2818 write
->header_size
= 2;
2826 assign_constant_locations();
2827 assign_curb_setup();
2829 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2830 assert(mov
->src
[0].file
== FIXED_GRF
);
2831 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2835 * Walks through basic blocks, looking for repeated MRF writes and
2836 * removing the later ones.
2839 fs_visitor::remove_duplicate_mrf_writes()
2841 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2842 bool progress
= false;
2844 /* Need to update the MRF tracking for compressed instructions. */
2845 if (dispatch_width
== 16)
2848 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2850 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2851 if (inst
->is_control_flow()) {
2852 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2855 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2856 inst
->dst
.file
== MRF
) {
2857 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
2858 if (prev_inst
&& inst
->equals(prev_inst
)) {
2859 inst
->remove(block
);
2865 /* Clear out the last-write records for MRFs that were overwritten. */
2866 if (inst
->dst
.file
== MRF
) {
2867 last_mrf_move
[inst
->dst
.nr
] = NULL
;
2870 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2871 /* Found a SEND instruction, which will include two or fewer
2872 * implied MRF writes. We could do better here.
2874 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2875 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2879 /* Clear out any MRF move records whose sources got overwritten. */
2880 if (inst
->dst
.file
== VGRF
) {
2881 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2882 if (last_mrf_move
[i
] &&
2883 last_mrf_move
[i
]->src
[0].nr
== inst
->dst
.nr
) {
2884 last_mrf_move
[i
] = NULL
;
2889 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2890 inst
->dst
.file
== MRF
&&
2891 inst
->src
[0].file
== VGRF
&&
2892 !inst
->is_partial_write()) {
2893 last_mrf_move
[inst
->dst
.nr
] = inst
;
2898 invalidate_live_intervals();
2904 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2906 /* Clear the flag for registers that actually got read (as expected). */
2907 for (int i
= 0; i
< inst
->sources
; i
++) {
2909 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
2910 grf
= inst
->src
[i
].nr
;
2915 if (grf
>= first_grf
&&
2916 grf
< first_grf
+ grf_len
) {
2917 deps
[grf
- first_grf
] = false;
2918 if (inst
->exec_size
== 16)
2919 deps
[grf
- first_grf
+ 1] = false;
2925 * Implements this workaround for the original 965:
2927 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2928 * check for post destination dependencies on this instruction, software
2929 * must ensure that there is no destination hazard for the case of ‘write
2930 * followed by a posted write’ shown in the following example.
2933 * 2. send r3.xy <rest of send instruction>
2936 * Due to no post-destination dependency check on the ‘send’, the above
2937 * code sequence could have two instructions (1 and 2) in flight at the
2938 * same time that both consider ‘r3’ as the target of their final writes.
2941 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2944 int write_len
= inst
->regs_written
;
2945 int first_write_grf
= inst
->dst
.nr
;
2946 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2947 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2949 memset(needs_dep
, false, sizeof(needs_dep
));
2950 memset(needs_dep
, true, write_len
);
2952 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2954 /* Walk backwards looking for writes to registers we're writing which
2955 * aren't read since being written. If we hit the start of the program,
2956 * we assume that there are no outstanding dependencies on entry to the
2959 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2960 /* If we hit control flow, assume that there *are* outstanding
2961 * dependencies, and force their cleanup before our instruction.
2963 if (block
->start() == scan_inst
) {
2964 for (int i
= 0; i
< write_len
; i
++) {
2966 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
2967 first_write_grf
+ i
);
2972 /* We insert our reads as late as possible on the assumption that any
2973 * instruction but a MOV that might have left us an outstanding
2974 * dependency has more latency than a MOV.
2976 if (scan_inst
->dst
.file
== VGRF
) {
2977 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2978 int reg
= scan_inst
->dst
.nr
+ i
;
2980 if (reg
>= first_write_grf
&&
2981 reg
< first_write_grf
+ write_len
&&
2982 needs_dep
[reg
- first_write_grf
]) {
2983 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
2984 needs_dep
[reg
- first_write_grf
] = false;
2985 if (scan_inst
->exec_size
== 16)
2986 needs_dep
[reg
- first_write_grf
+ 1] = false;
2991 /* Clear the flag for registers that actually got read (as expected). */
2992 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2994 /* Continue the loop only if we haven't resolved all the dependencies */
2996 for (i
= 0; i
< write_len
; i
++) {
3006 * Implements this workaround for the original 965:
3008 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3009 * used as a destination register until after it has been sourced by an
3010 * instruction with a different destination register.
3013 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3015 int write_len
= inst
->regs_written
;
3016 int first_write_grf
= inst
->dst
.nr
;
3017 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3018 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3020 memset(needs_dep
, false, sizeof(needs_dep
));
3021 memset(needs_dep
, true, write_len
);
3022 /* Walk forwards looking for writes to registers we're writing which aren't
3023 * read before being written.
3025 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3026 /* If we hit control flow, force resolve all remaining dependencies. */
3027 if (block
->end() == scan_inst
) {
3028 for (int i
= 0; i
< write_len
; i
++) {
3030 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3031 first_write_grf
+ i
);
3036 /* Clear the flag for registers that actually got read (as expected). */
3037 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3039 /* We insert our reads as late as possible since they're reading the
3040 * result of a SEND, which has massive latency.
3042 if (scan_inst
->dst
.file
== VGRF
&&
3043 scan_inst
->dst
.nr
>= first_write_grf
&&
3044 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3045 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3046 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3048 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3051 /* Continue the loop only if we haven't resolved all the dependencies */
3053 for (i
= 0; i
< write_len
; i
++) {
3063 fs_visitor::insert_gen4_send_dependency_workarounds()
3065 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3068 bool progress
= false;
3070 /* Note that we're done with register allocation, so GRF fs_regs always
3071 * have a .reg_offset of 0.
3074 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3075 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3076 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3077 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3083 invalidate_live_intervals();
3087 * Turns the generic expression-style uniform pull constant load instruction
3088 * into a hardware-specific series of instructions for loading a pull
3091 * The expression style allows the CSE pass before this to optimize out
3092 * repeated loads from the same offset, and gives the pre-register-allocation
3093 * scheduling full flexibility, while the conversion to native instructions
3094 * allows the post-register-allocation scheduler the best information
3097 * Note that execution masking for setting up pull constant loads is special:
3098 * the channels that need to be written are unrelated to the current execution
3099 * mask, since a later instruction will use one of the result channels as a
3100 * source operand for all 8 or 16 of its channels.
3103 fs_visitor::lower_uniform_pull_constant_loads()
3105 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3106 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3109 if (devinfo
->gen
>= 7) {
3110 /* The offset arg is a vec4-aligned immediate byte offset. */
3111 fs_reg const_offset_reg
= inst
->src
[1];
3112 assert(const_offset_reg
.file
== IMM
&&
3113 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3114 assert(const_offset_reg
.ud
% 16 == 0);
3116 fs_reg payload
, offset
;
3117 if (devinfo
->gen
>= 9) {
3118 /* We have to use a message header on Skylake to get SIMD4x2
3119 * mode. Reserve space for the register.
3121 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3122 offset
.reg_offset
++;
3125 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3129 /* This is actually going to be a MOV, but since only the first dword
3130 * is accessed, we have a special opcode to do just that one. Note
3131 * that this needs to be an operation that will be considered a def
3132 * by live variable analysis, or register allocation will explode.
3134 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3135 8, offset
, const_offset_reg
);
3136 setup
->force_writemask_all
= true;
3138 setup
->ir
= inst
->ir
;
3139 setup
->annotation
= inst
->annotation
;
3140 inst
->insert_before(block
, setup
);
3142 /* Similarly, this will only populate the first 4 channels of the
3143 * result register (since we only use smear values from 0-3), but we
3144 * don't tell the optimizer.
3146 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3147 inst
->src
[1] = payload
;
3148 inst
->base_mrf
= -1;
3150 invalidate_live_intervals();
3152 /* Before register allocation, we didn't tell the scheduler about the
3153 * MRF we use. We know it's safe to use this MRF because nothing
3154 * else does except for register spill/unspill, which generates and
3155 * uses its MRF within a single IR instruction.
3157 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3164 fs_visitor::lower_load_payload()
3166 bool progress
= false;
3168 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3169 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3172 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3173 assert(inst
->saturate
== false);
3174 fs_reg dst
= inst
->dst
;
3176 /* Get rid of COMPR4. We'll add it back in if we need it */
3177 if (dst
.file
== MRF
)
3178 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3180 const fs_builder
ibld(this, block
, inst
);
3181 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3183 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3184 if (inst
->src
[i
].file
!= BAD_FILE
) {
3185 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3186 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3187 hbld
.MOV(mov_dst
, mov_src
);
3189 dst
= offset(dst
, hbld
, 1);
3192 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3193 inst
->exec_size
> 8) {
3194 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3195 * a straightforward copy. Instead, the result of the
3196 * LOAD_PAYLOAD is treated as interleaved and the first four
3197 * non-header sources are unpacked as:
3208 * This is used for gen <= 5 fb writes.
3210 assert(inst
->exec_size
== 16);
3211 assert(inst
->header_size
+ 4 <= inst
->sources
);
3212 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3213 if (inst
->src
[i
].file
!= BAD_FILE
) {
3214 if (devinfo
->has_compr4
) {
3215 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3216 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3217 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3219 /* Platform doesn't have COMPR4. We have to fake it */
3220 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3221 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3223 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3230 /* The loop above only ever incremented us through the first set
3231 * of 4 registers. However, thanks to the magic of COMPR4, we
3232 * actually wrote to the first 8 registers, so we need to take
3233 * that into account now.
3237 /* The COMPR4 code took care of the first 4 sources. We'll let
3238 * the regular path handle any remaining sources. Yes, we are
3239 * modifying the instruction but we're about to delete it so
3240 * this really doesn't hurt anything.
3242 inst
->header_size
+= 4;
3245 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3246 if (inst
->src
[i
].file
!= BAD_FILE
)
3247 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3248 dst
= offset(dst
, ibld
, 1);
3251 inst
->remove(block
);
3256 invalidate_live_intervals();
3262 fs_visitor::lower_integer_multiplication()
3264 bool progress
= false;
3266 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3267 const fs_builder
ibld(this, block
, inst
);
3269 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3270 if (inst
->dst
.is_accumulator() ||
3271 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3272 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3275 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3276 * operation directly, but CHV/BXT cannot.
3278 if (devinfo
->gen
>= 8 &&
3279 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3282 if (inst
->src
[1].file
== IMM
&&
3283 inst
->src
[1].ud
< (1 << 16)) {
3284 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3285 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3288 * If multiplying by an immediate value that fits in 16-bits, do a
3289 * single MUL instruction with that value in the proper location.
3291 if (devinfo
->gen
< 7) {
3292 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3294 ibld
.MOV(imm
, inst
->src
[1]);
3295 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3297 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3300 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3301 * do 32-bit integer multiplication in one instruction, but instead
3302 * must do a sequence (which actually calculates a 64-bit result):
3304 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3305 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3306 * mov(8) g2<1>D acc0<8,8,1>D
3308 * But on Gen > 6, the ability to use second accumulator register
3309 * (acc1) for non-float data types was removed, preventing a simple
3310 * implementation in SIMD16. A 16-channel result can be calculated by
3311 * executing the three instructions twice in SIMD8, once with quarter
3312 * control of 1Q for the first eight channels and again with 2Q for
3313 * the second eight channels.
3315 * Which accumulator register is implicitly accessed (by AccWrEnable
3316 * for instance) is determined by the quarter control. Unfortunately
3317 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3318 * implicit accumulator access by an instruction with 2Q will access
3319 * acc1 regardless of whether the data type is usable in acc1.
3321 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3322 * integer data types.
3324 * Since we only want the low 32-bits of the result, we can do two
3325 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3326 * adjust the high result and add them (like the mach is doing):
3328 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3329 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3330 * shl(8) g9<1>D g8<8,8,1>D 16D
3331 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3333 * We avoid the shl instruction by realizing that we only want to add
3334 * the low 16-bits of the "high" result to the high 16-bits of the
3335 * "low" result and using proper regioning on the add:
3337 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3338 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3339 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3341 * Since it does not use the (single) accumulator register, we can
3342 * schedule multi-component multiplications much better.
3345 fs_reg orig_dst
= inst
->dst
;
3346 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3347 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3350 fs_reg low
= inst
->dst
;
3351 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3354 if (devinfo
->gen
>= 7) {
3355 fs_reg src1_0_w
= inst
->src
[1];
3356 fs_reg src1_1_w
= inst
->src
[1];
3358 if (inst
->src
[1].file
== IMM
) {
3359 src1_0_w
.ud
&= 0xffff;
3362 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3363 if (src1_0_w
.stride
!= 0) {
3364 assert(src1_0_w
.stride
== 1);
3365 src1_0_w
.stride
= 2;
3368 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3369 if (src1_1_w
.stride
!= 0) {
3370 assert(src1_1_w
.stride
== 1);
3371 src1_1_w
.stride
= 2;
3373 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3375 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3376 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3378 fs_reg src0_0_w
= inst
->src
[0];
3379 fs_reg src0_1_w
= inst
->src
[0];
3381 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3382 if (src0_0_w
.stride
!= 0) {
3383 assert(src0_0_w
.stride
== 1);
3384 src0_0_w
.stride
= 2;
3387 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3388 if (src0_1_w
.stride
!= 0) {
3389 assert(src0_1_w
.stride
== 1);
3390 src0_1_w
.stride
= 2;
3392 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3394 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3395 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3398 fs_reg dst
= inst
->dst
;
3399 dst
.type
= BRW_REGISTER_TYPE_UW
;
3400 dst
.subreg_offset
= 2;
3403 high
.type
= BRW_REGISTER_TYPE_UW
;
3406 low
.type
= BRW_REGISTER_TYPE_UW
;
3407 low
.subreg_offset
= 2;
3410 ibld
.ADD(dst
, low
, high
);
3412 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3413 set_condmod(inst
->conditional_mod
,
3414 ibld
.MOV(orig_dst
, inst
->dst
));
3418 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3419 /* Should have been lowered to 8-wide. */
3420 assert(inst
->exec_size
<= 8);
3421 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3423 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3424 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3426 if (devinfo
->gen
>= 8) {
3427 /* Until Gen8, integer multiplies read 32-bits from one source,
3428 * and 16-bits from the other, and relying on the MACH instruction
3429 * to generate the high bits of the result.
3431 * On Gen8, the multiply instruction does a full 32x32-bit
3432 * multiply, but in order to do a 64-bit multiply we can simulate
3433 * the previous behavior and then use a MACH instruction.
3435 * FINISHME: Don't use source modifiers on src1.
3437 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3438 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3439 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3440 mul
->src
[1].stride
*= 2;
3442 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3443 inst
->force_sechalf
) {
3444 /* Among other things the quarter control bits influence which
3445 * accumulator register is used by the hardware for instructions
3446 * that access the accumulator implicitly (e.g. MACH). A
3447 * second-half instruction would normally map to acc1, which
3448 * doesn't exist on Gen7 and up (the hardware does emulate it for
3449 * floating-point instructions *only* by taking advantage of the
3450 * extra precision of acc0 not normally used for floating point
3453 * HSW and up are careful enough not to try to access an
3454 * accumulator register that doesn't exist, but on earlier Gen7
3455 * hardware we need to make sure that the quarter control bits are
3456 * zero to avoid non-deterministic behaviour and emit an extra MOV
3457 * to get the result masked correctly according to the current
3460 mach
->force_sechalf
= false;
3461 mach
->force_writemask_all
= true;
3462 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3463 ibld
.MOV(inst
->dst
, mach
->dst
);
3469 inst
->remove(block
);
3474 invalidate_live_intervals();
3480 fs_visitor::lower_minmax()
3482 assert(devinfo
->gen
< 6);
3484 bool progress
= false;
3486 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3487 const fs_builder
ibld(this, block
, inst
);
3489 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3490 inst
->predicate
== BRW_PREDICATE_NONE
) {
3491 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3492 * the original SEL.L/GE instruction
3494 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3495 inst
->conditional_mod
);
3496 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3497 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3504 invalidate_live_intervals();
3510 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3511 fs_reg
*dst
, fs_reg color
, unsigned components
)
3513 if (key
->clamp_fragment_color
) {
3514 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3515 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3517 for (unsigned i
= 0; i
< components
; i
++)
3519 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3524 for (unsigned i
= 0; i
< components
; i
++)
3525 dst
[i
] = offset(color
, bld
, i
);
3529 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3530 const brw_wm_prog_data
*prog_data
,
3531 const brw_wm_prog_key
*key
,
3532 const fs_visitor::thread_payload
&payload
)
3534 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3535 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3536 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3537 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3538 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3539 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3540 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3541 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3542 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3543 const unsigned components
=
3544 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3546 /* We can potentially have a message length of up to 15, so we have to set
3547 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3550 int header_size
= 2, payload_header_size
;
3551 unsigned length
= 0;
3553 /* From the Sandy Bridge PRM, volume 4, page 198:
3555 * "Dispatched Pixel Enables. One bit per pixel indicating
3556 * which pixels were originally enabled when the thread was
3557 * dispatched. This field is only required for the end-of-
3558 * thread message and on all dual-source messages."
3560 if (devinfo
->gen
>= 6 &&
3561 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3562 color1
.file
== BAD_FILE
&&
3563 key
->nr_color_regions
== 1) {
3567 if (header_size
!= 0) {
3568 assert(header_size
== 2);
3569 /* Allocate 2 registers for a header */
3573 if (payload
.aa_dest_stencil_reg
) {
3574 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3575 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3576 .MOV(sources
[length
],
3577 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3581 if (prog_data
->uses_omask
) {
3582 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3583 BRW_REGISTER_TYPE_UD
);
3585 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3586 * relevant. Since it's unsigned single words one vgrf is always
3587 * 16-wide, but only the lower or higher 8 channels will be used by the
3588 * hardware when doing a SIMD8 write depending on whether we have
3589 * selected the subspans for the first or second half respectively.
3591 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3592 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3593 sample_mask
.stride
*= 2;
3595 bld
.exec_all().annotate("FB write oMask")
3596 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3597 inst
->force_sechalf
),
3602 payload_header_size
= length
;
3604 if (src0_alpha
.file
!= BAD_FILE
) {
3605 /* FIXME: This is being passed at the wrong location in the payload and
3606 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3607 * It's supposed to be immediately before oMask but there seems to be no
3608 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3609 * requires header sources to form a contiguous segment at the beginning
3610 * of the message and src0_alpha has per-channel semantics.
3612 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3616 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3619 if (color1
.file
!= BAD_FILE
) {
3620 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3624 if (src_depth
.file
!= BAD_FILE
) {
3625 sources
[length
] = src_depth
;
3629 if (dst_depth
.file
!= BAD_FILE
) {
3630 sources
[length
] = dst_depth
;
3634 if (src_stencil
.file
!= BAD_FILE
) {
3635 assert(devinfo
->gen
>= 9);
3636 assert(bld
.dispatch_width() != 16);
3638 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3639 * available on gen9+. As such it's impossible to have both enabled at the
3640 * same time and therefore length cannot overrun the array.
3642 assert(length
< 15);
3644 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3645 bld
.exec_all().annotate("FB write OS")
3646 .emit(FS_OPCODE_PACK_STENCIL_REF
, sources
[length
],
3647 retype(src_stencil
, BRW_REGISTER_TYPE_UB
));
3652 if (devinfo
->gen
>= 7) {
3653 /* Send from the GRF */
3654 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3655 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3656 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3657 load
->dst
= payload
;
3659 inst
->src
[0] = payload
;
3660 inst
->resize_sources(1);
3661 inst
->base_mrf
= -1;
3663 /* Send from the MRF */
3664 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3665 sources
, length
, payload_header_size
);
3667 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3668 * will do this for us if we just give it a COMPR4 destination.
3670 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3671 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3673 inst
->resize_sources(0);
3677 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3678 inst
->mlen
= load
->regs_written
;
3679 inst
->header_size
= header_size
;
3683 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3684 const fs_reg
&coordinate
,
3685 const fs_reg
&shadow_c
,
3686 const fs_reg
&lod
, const fs_reg
&lod2
,
3687 const fs_reg
&surface
,
3688 const fs_reg
&sampler
,
3689 unsigned coord_components
,
3690 unsigned grad_components
)
3692 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3693 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3694 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3695 fs_reg msg_end
= msg_begin
;
3698 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3700 for (unsigned i
= 0; i
< coord_components
; i
++)
3701 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3702 offset(coordinate
, bld
, i
));
3704 msg_end
= offset(msg_end
, bld
, coord_components
);
3706 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3707 * require all three components to be present and zero if they are unused.
3709 if (coord_components
> 0 &&
3710 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3711 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3712 for (unsigned i
= coord_components
; i
< 3; i
++)
3713 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3715 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3718 if (op
== SHADER_OPCODE_TXD
) {
3719 /* TXD unsupported in SIMD16 mode. */
3720 assert(bld
.dispatch_width() == 8);
3722 /* the slots for u and v are always present, but r is optional */
3723 if (coord_components
< 2)
3724 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3727 * dPdx = dudx, dvdx, drdx
3728 * dPdy = dudy, dvdy, drdy
3730 * 1-arg: Does not exist.
3732 * 2-arg: dudx dvdx dudy dvdy
3733 * dPdx.x dPdx.y dPdy.x dPdy.y
3736 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3737 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3738 * m5 m6 m7 m8 m9 m10
3740 for (unsigned i
= 0; i
< grad_components
; i
++)
3741 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3743 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3745 for (unsigned i
= 0; i
< grad_components
; i
++)
3746 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3748 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3752 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3753 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3755 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3756 bld
.dispatch_width() == 16);
3758 const brw_reg_type type
=
3759 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3760 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3761 bld
.MOV(retype(msg_end
, type
), lod
);
3762 msg_end
= offset(msg_end
, bld
, 1);
3765 if (shadow_c
.file
!= BAD_FILE
) {
3766 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3767 /* There's no plain shadow compare message, so we use shadow
3768 * compare with a bias of 0.0.
3770 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3771 msg_end
= offset(msg_end
, bld
, 1);
3774 bld
.MOV(msg_end
, shadow_c
);
3775 msg_end
= offset(msg_end
, bld
, 1);
3779 inst
->src
[0] = reg_undef
;
3780 inst
->src
[1] = surface
;
3781 inst
->src
[2] = sampler
;
3782 inst
->resize_sources(3);
3783 inst
->base_mrf
= msg_begin
.nr
;
3784 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3785 inst
->header_size
= 1;
3789 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3791 const fs_reg
&shadow_c
,
3792 fs_reg lod
, fs_reg lod2
,
3793 const fs_reg
&sample_index
,
3794 const fs_reg
&surface
,
3795 const fs_reg
&sampler
,
3796 const fs_reg
&offset_value
,
3797 unsigned coord_components
,
3798 unsigned grad_components
)
3800 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3801 fs_reg msg_coords
= message
;
3802 unsigned header_size
= 0;
3804 if (offset_value
.file
!= BAD_FILE
) {
3805 /* The offsets set up by the visitor are in the m1 header, so we can't
3812 for (unsigned i
= 0; i
< coord_components
; i
++) {
3813 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3814 coordinate
= offset(coordinate
, bld
, 1);
3816 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3817 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3819 if (shadow_c
.file
!= BAD_FILE
) {
3820 fs_reg msg_shadow
= msg_lod
;
3821 bld
.MOV(msg_shadow
, shadow_c
);
3822 msg_lod
= offset(msg_shadow
, bld
, 1);
3827 case SHADER_OPCODE_TXL
:
3829 bld
.MOV(msg_lod
, lod
);
3830 msg_end
= offset(msg_lod
, bld
, 1);
3832 case SHADER_OPCODE_TXD
:
3835 * dPdx = dudx, dvdx, drdx
3836 * dPdy = dudy, dvdy, drdy
3838 * Load up these values:
3839 * - dudx dudy dvdx dvdy drdx drdy
3840 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3843 for (unsigned i
= 0; i
< grad_components
; i
++) {
3844 bld
.MOV(msg_end
, lod
);
3845 lod
= offset(lod
, bld
, 1);
3846 msg_end
= offset(msg_end
, bld
, 1);
3848 bld
.MOV(msg_end
, lod2
);
3849 lod2
= offset(lod2
, bld
, 1);
3850 msg_end
= offset(msg_end
, bld
, 1);
3853 case SHADER_OPCODE_TXS
:
3854 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3855 bld
.MOV(msg_lod
, lod
);
3856 msg_end
= offset(msg_lod
, bld
, 1);
3858 case SHADER_OPCODE_TXF
:
3859 msg_lod
= offset(msg_coords
, bld
, 3);
3860 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3861 msg_end
= offset(msg_lod
, bld
, 1);
3863 case SHADER_OPCODE_TXF_CMS
:
3864 msg_lod
= offset(msg_coords
, bld
, 3);
3866 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
3868 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3869 msg_end
= offset(msg_lod
, bld
, 2);
3876 inst
->src
[0] = reg_undef
;
3877 inst
->src
[1] = surface
;
3878 inst
->src
[2] = sampler
;
3879 inst
->resize_sources(3);
3880 inst
->base_mrf
= message
.nr
;
3881 inst
->mlen
= msg_end
.nr
- message
.nr
;
3882 inst
->header_size
= header_size
;
3884 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3885 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3889 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3891 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3894 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
3898 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3900 const fs_reg
&shadow_c
,
3901 fs_reg lod
, fs_reg lod2
,
3902 const fs_reg
&sample_index
,
3904 const fs_reg
&surface
,
3905 const fs_reg
&sampler
,
3906 fs_reg offset_value
,
3907 unsigned coord_components
,
3908 unsigned grad_components
)
3910 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3911 int reg_width
= bld
.dispatch_width() / 8;
3912 unsigned header_size
= 0, length
= 0;
3913 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3914 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3915 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3917 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3918 offset_value
.file
!= BAD_FILE
||
3919 is_high_sampler(devinfo
, sampler
)) {
3920 /* For general texture offsets (no txf workaround), we need a header to
3921 * put them in. Note that we're only reserving space for it in the
3922 * message payload as it will be initialized implicitly by the
3925 * TG4 needs to place its channel select in the header, for interaction
3926 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3927 * larger sampler numbers we need to offset the Sampler State Pointer in
3931 sources
[0] = fs_reg();
3935 if (shadow_c
.file
!= BAD_FILE
) {
3936 bld
.MOV(sources
[length
], shadow_c
);
3940 bool coordinate_done
= false;
3942 /* The sampler can only meaningfully compute LOD for fragment shader
3943 * messages. For all other stages, we change the opcode to TXL and
3944 * hardcode the LOD to 0.
3946 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3947 op
== SHADER_OPCODE_TEX
) {
3948 op
= SHADER_OPCODE_TXL
;
3949 lod
= brw_imm_f(0.0f
);
3952 /* Set up the LOD info */
3955 case SHADER_OPCODE_TXL
:
3956 bld
.MOV(sources
[length
], lod
);
3959 case SHADER_OPCODE_TXD
:
3960 /* TXD should have been lowered in SIMD16 mode. */
3961 assert(bld
.dispatch_width() == 8);
3963 /* Load dPdx and the coordinate together:
3964 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3966 for (unsigned i
= 0; i
< coord_components
; i
++) {
3967 bld
.MOV(sources
[length
], coordinate
);
3968 coordinate
= offset(coordinate
, bld
, 1);
3971 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3972 * only derivatives for (u, v, r).
3974 if (i
< grad_components
) {
3975 bld
.MOV(sources
[length
], lod
);
3976 lod
= offset(lod
, bld
, 1);
3979 bld
.MOV(sources
[length
], lod2
);
3980 lod2
= offset(lod2
, bld
, 1);
3985 coordinate_done
= true;
3987 case SHADER_OPCODE_TXS
:
3988 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
3991 case SHADER_OPCODE_TXF
:
3992 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
3993 * On Gen9 they are u, v, lod, r
3995 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3996 coordinate
= offset(coordinate
, bld
, 1);
3999 if (devinfo
->gen
>= 9) {
4000 if (coord_components
>= 2) {
4001 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4002 coordinate
= offset(coordinate
, bld
, 1);
4007 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4010 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
4011 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4012 coordinate
= offset(coordinate
, bld
, 1);
4016 coordinate_done
= true;
4018 case SHADER_OPCODE_TXF_CMS
:
4019 case SHADER_OPCODE_TXF_CMS_W
:
4020 case SHADER_OPCODE_TXF_UMS
:
4021 case SHADER_OPCODE_TXF_MCS
:
4022 if (op
== SHADER_OPCODE_TXF_UMS
||
4023 op
== SHADER_OPCODE_TXF_CMS
||
4024 op
== SHADER_OPCODE_TXF_CMS_W
) {
4025 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4029 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4030 /* Data from the multisample control surface. */
4031 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4034 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4037 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4038 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4041 offset(mcs
, bld
, 1));
4046 /* There is no offsetting for this message; just copy in the integer
4047 * texture coordinates.
4049 for (unsigned i
= 0; i
< coord_components
; i
++) {
4050 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4051 coordinate
= offset(coordinate
, bld
, 1);
4055 coordinate_done
= true;
4057 case SHADER_OPCODE_TG4_OFFSET
:
4058 /* gather4_po_c should have been lowered in SIMD16 mode. */
4059 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
4061 /* More crazy intermixing */
4062 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
4063 bld
.MOV(sources
[length
], coordinate
);
4064 coordinate
= offset(coordinate
, bld
, 1);
4068 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
4069 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
4070 offset_value
= offset(offset_value
, bld
, 1);
4074 if (coord_components
== 3) { /* r if present */
4075 bld
.MOV(sources
[length
], coordinate
);
4076 coordinate
= offset(coordinate
, bld
, 1);
4080 coordinate_done
= true;
4086 /* Set up the coordinate (except for cases where it was done above) */
4087 if (!coordinate_done
) {
4088 for (unsigned i
= 0; i
< coord_components
; i
++) {
4089 bld
.MOV(sources
[length
], coordinate
);
4090 coordinate
= offset(coordinate
, bld
, 1);
4097 mlen
= length
* reg_width
- header_size
;
4099 mlen
= length
* reg_width
;
4101 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4102 BRW_REGISTER_TYPE_F
);
4103 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4105 /* Generate the SEND. */
4107 inst
->src
[0] = src_payload
;
4108 inst
->src
[1] = surface
;
4109 inst
->src
[2] = sampler
;
4110 inst
->resize_sources(3);
4111 inst
->base_mrf
= -1;
4113 inst
->header_size
= header_size
;
4115 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4116 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4120 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4122 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4123 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4124 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4125 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4126 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4127 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4128 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4129 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4130 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4131 const fs_reg
&offset_value
= inst
->src
[TEX_LOGICAL_SRC_OFFSET_VALUE
];
4132 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4133 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4134 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4135 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4137 if (devinfo
->gen
>= 7) {
4138 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4139 shadow_c
, lod
, lod2
, sample_index
,
4140 mcs
, surface
, sampler
, offset_value
,
4141 coord_components
, grad_components
);
4142 } else if (devinfo
->gen
>= 5) {
4143 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4144 shadow_c
, lod
, lod2
, sample_index
,
4145 surface
, sampler
, offset_value
,
4146 coord_components
, grad_components
);
4148 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4149 shadow_c
, lod
, lod2
,
4151 coord_components
, grad_components
);
4156 * Initialize the header present in some typed and untyped surface
4160 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4162 fs_builder ubld
= bld
.exec_all().group(8, 0);
4163 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4164 ubld
.MOV(dst
, brw_imm_d(0));
4165 ubld
.MOV(component(dst
, 7), sample_mask
);
4170 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4171 const fs_reg
&sample_mask
)
4173 /* Get the logical send arguments. */
4174 const fs_reg
&addr
= inst
->src
[0];
4175 const fs_reg
&src
= inst
->src
[1];
4176 const fs_reg
&surface
= inst
->src
[2];
4177 const UNUSED fs_reg
&dims
= inst
->src
[3];
4178 const fs_reg
&arg
= inst
->src
[4];
4180 /* Calculate the total number of components of the payload. */
4181 const unsigned addr_sz
= inst
->components_read(0);
4182 const unsigned src_sz
= inst
->components_read(1);
4183 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4184 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4186 /* Allocate space for the payload. */
4187 fs_reg
*const components
= new fs_reg
[sz
];
4188 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4191 /* Construct the payload. */
4193 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4195 for (unsigned i
= 0; i
< addr_sz
; i
++)
4196 components
[n
++] = offset(addr
, bld
, i
);
4198 for (unsigned i
= 0; i
< src_sz
; i
++)
4199 components
[n
++] = offset(src
, bld
, i
);
4201 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4203 /* Update the original instruction. */
4205 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4206 inst
->header_size
= header_sz
;
4208 inst
->src
[0] = payload
;
4209 inst
->src
[1] = surface
;
4211 inst
->resize_sources(3);
4213 delete[] components
;
4217 fs_visitor::lower_logical_sends()
4219 bool progress
= false;
4221 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4222 const fs_builder
ibld(this, block
, inst
);
4224 switch (inst
->opcode
) {
4225 case FS_OPCODE_FB_WRITE_LOGICAL
:
4226 assert(stage
== MESA_SHADER_FRAGMENT
);
4227 lower_fb_write_logical_send(ibld
, inst
,
4228 (const brw_wm_prog_data
*)prog_data
,
4229 (const brw_wm_prog_key
*)key
,
4233 case SHADER_OPCODE_TEX_LOGICAL
:
4234 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4237 case SHADER_OPCODE_TXD_LOGICAL
:
4238 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4241 case SHADER_OPCODE_TXF_LOGICAL
:
4242 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4245 case SHADER_OPCODE_TXL_LOGICAL
:
4246 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4249 case SHADER_OPCODE_TXS_LOGICAL
:
4250 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4253 case FS_OPCODE_TXB_LOGICAL
:
4254 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4257 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4258 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4261 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4262 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4265 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4266 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4269 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4270 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4273 case SHADER_OPCODE_LOD_LOGICAL
:
4274 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4277 case SHADER_OPCODE_TG4_LOGICAL
:
4278 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4281 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4282 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4285 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4286 lower_surface_logical_send(ibld
, inst
,
4287 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4291 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4292 lower_surface_logical_send(ibld
, inst
,
4293 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4294 ibld
.sample_mask_reg());
4297 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4298 lower_surface_logical_send(ibld
, inst
,
4299 SHADER_OPCODE_UNTYPED_ATOMIC
,
4300 ibld
.sample_mask_reg());
4303 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4304 lower_surface_logical_send(ibld
, inst
,
4305 SHADER_OPCODE_TYPED_SURFACE_READ
,
4309 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4310 lower_surface_logical_send(ibld
, inst
,
4311 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4312 ibld
.sample_mask_reg());
4315 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4316 lower_surface_logical_send(ibld
, inst
,
4317 SHADER_OPCODE_TYPED_ATOMIC
,
4318 ibld
.sample_mask_reg());
4329 invalidate_live_intervals();
4335 * Get the closest native SIMD width supported by the hardware for instruction
4336 * \p inst. The instruction will be left untouched by
4337 * fs_visitor::lower_simd_width() if the returned value is equal to the
4338 * original execution size.
4341 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4342 const fs_inst
*inst
)
4344 switch (inst
->opcode
) {
4345 case BRW_OPCODE_MOV
:
4346 case BRW_OPCODE_SEL
:
4347 case BRW_OPCODE_NOT
:
4348 case BRW_OPCODE_AND
:
4350 case BRW_OPCODE_XOR
:
4351 case BRW_OPCODE_SHR
:
4352 case BRW_OPCODE_SHL
:
4353 case BRW_OPCODE_ASR
:
4354 case BRW_OPCODE_CMP
:
4355 case BRW_OPCODE_CMPN
:
4356 case BRW_OPCODE_CSEL
:
4357 case BRW_OPCODE_F32TO16
:
4358 case BRW_OPCODE_F16TO32
:
4359 case BRW_OPCODE_BFREV
:
4360 case BRW_OPCODE_BFE
:
4361 case BRW_OPCODE_BFI1
:
4362 case BRW_OPCODE_BFI2
:
4363 case BRW_OPCODE_ADD
:
4364 case BRW_OPCODE_MUL
:
4365 case BRW_OPCODE_AVG
:
4366 case BRW_OPCODE_FRC
:
4367 case BRW_OPCODE_RNDU
:
4368 case BRW_OPCODE_RNDD
:
4369 case BRW_OPCODE_RNDE
:
4370 case BRW_OPCODE_RNDZ
:
4371 case BRW_OPCODE_LZD
:
4372 case BRW_OPCODE_FBH
:
4373 case BRW_OPCODE_FBL
:
4374 case BRW_OPCODE_CBIT
:
4375 case BRW_OPCODE_SAD2
:
4376 case BRW_OPCODE_MAD
:
4377 case BRW_OPCODE_LRP
:
4378 case SHADER_OPCODE_RCP
:
4379 case SHADER_OPCODE_RSQ
:
4380 case SHADER_OPCODE_SQRT
:
4381 case SHADER_OPCODE_EXP2
:
4382 case SHADER_OPCODE_LOG2
:
4383 case SHADER_OPCODE_POW
:
4384 case SHADER_OPCODE_INT_QUOTIENT
:
4385 case SHADER_OPCODE_INT_REMAINDER
:
4386 case SHADER_OPCODE_SIN
:
4387 case SHADER_OPCODE_COS
: {
4388 /* According to the PRMs:
4389 * "A. In Direct Addressing mode, a source cannot span more than 2
4390 * adjacent GRF registers.
4391 * B. A destination cannot span more than 2 adjacent GRF registers."
4393 * Look for the source or destination with the largest register region
4394 * which is the one that is going to limit the overal execution size of
4395 * the instruction due to this rule.
4397 unsigned reg_count
= inst
->regs_written
;
4399 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4400 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4402 /* Calculate the maximum execution size of the instruction based on the
4403 * factor by which it goes over the hardware limit of 2 GRFs.
4405 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4407 case SHADER_OPCODE_MULH
:
4408 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4409 * is 8-wide on Gen7+.
4411 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4413 case FS_OPCODE_FB_WRITE_LOGICAL
:
4414 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4417 assert(devinfo
->gen
!= 6 ||
4418 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4419 inst
->exec_size
== 8);
4420 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4421 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4422 8 : inst
->exec_size
);
4424 case SHADER_OPCODE_TXD_LOGICAL
:
4425 /* TXD is unsupported in SIMD16 mode. */
4428 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4429 /* gather4_po_c is unsupported in SIMD16 mode. */
4430 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4431 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4433 case SHADER_OPCODE_TXL_LOGICAL
:
4434 case FS_OPCODE_TXB_LOGICAL
: {
4435 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4436 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4437 * mode because the message exceeds the maximum length of 11.
4439 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4440 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4442 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4445 return inst
->exec_size
;
4447 case SHADER_OPCODE_TXF_LOGICAL
:
4448 case SHADER_OPCODE_TXS_LOGICAL
:
4449 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4450 * messages. Use SIMD16 instead.
4452 if (devinfo
->gen
== 4)
4455 return inst
->exec_size
;
4457 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4458 /* This opcode can take up to 6 arguments which means that in some
4459 * circumstances it can end up with a message that is too long in SIMD16
4462 const unsigned coord_components
=
4463 inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4464 /* First three arguments are the sample index and the two arguments for
4467 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
4470 return inst
->exec_size
;
4473 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4474 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4475 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4479 return inst
->exec_size
;
4484 * The \p rows array of registers represents a \p num_rows by \p num_columns
4485 * matrix in row-major order, write it in column-major order into the register
4486 * passed as destination. \p stride gives the separation between matrix
4487 * elements in the input in fs_builder::dispatch_width() units.
4490 emit_transpose(const fs_builder
&bld
,
4491 const fs_reg
&dst
, const fs_reg
*rows
,
4492 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4494 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4496 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4497 for (unsigned j
= 0; j
< num_rows
; ++j
)
4498 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4501 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4503 delete[] components
;
4507 fs_visitor::lower_simd_width()
4509 bool progress
= false;
4511 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4512 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4514 if (lower_width
!= inst
->exec_size
) {
4515 /* Builder matching the original instruction. We may also need to
4516 * emit an instruction of width larger than the original, set the
4517 * execution size of the builder to the highest of both for now so
4518 * we're sure that both cases can be handled.
4520 const fs_builder ibld
= bld
.at(block
, inst
)
4521 .exec_all(inst
->force_writemask_all
)
4522 .group(MAX2(inst
->exec_size
, lower_width
),
4523 inst
->force_sechalf
);
4525 /* Split the copies in chunks of the execution width of either the
4526 * original or the lowered instruction, whichever is lower.
4528 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4529 const unsigned n
= inst
->exec_size
/ copy_width
;
4530 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4531 inst
->dst
.component_size(inst
->exec_size
);
4534 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4535 !inst
->writes_accumulator
&& !inst
->mlen
);
4537 for (unsigned i
= 0; i
< n
; i
++) {
4538 /* Emit a copy of the original instruction with the lowered width.
4539 * If the EOT flag was set throw it away except for the last
4540 * instruction to avoid killing the thread prematurely.
4542 fs_inst split_inst
= *inst
;
4543 split_inst
.exec_size
= lower_width
;
4544 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4546 /* Select the correct channel enables for the i-th group, then
4547 * transform the sources and destination and emit the lowered
4550 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4552 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4553 if (inst
->src
[j
].file
!= BAD_FILE
&&
4554 !is_uniform(inst
->src
[j
])) {
4555 /* Get the i-th copy_width-wide chunk of the source. */
4556 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4557 const unsigned src_size
= inst
->components_read(j
);
4559 /* Use a trivial transposition to copy one every n
4560 * copy_width-wide components of the register into a
4561 * temporary passed as source to the lowered instruction.
4563 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4564 emit_transpose(lbld
.group(copy_width
, 0),
4565 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4569 if (inst
->regs_written
) {
4570 /* Allocate enough space to hold the result of the lowered
4571 * instruction and fix up the number of registers written.
4573 split_inst
.dst
= dsts
[i
] =
4574 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4575 split_inst
.regs_written
=
4576 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4580 lbld
.emit(split_inst
);
4583 if (inst
->regs_written
) {
4584 /* Distance between useful channels in the temporaries, skipping
4585 * garbage if the lowered instruction is wider than the original.
4587 const unsigned m
= lower_width
/ copy_width
;
4589 /* Interleave the components of the result from the lowered
4590 * instructions. We need to set exec_all() when copying more than
4591 * one half per component, because LOAD_PAYLOAD (in terms of which
4592 * emit_transpose is implemented) can only use the same channel
4593 * enable signals for all of its non-header sources.
4595 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4596 .group(copy_width
, 0),
4597 inst
->dst
, dsts
, n
, dst_size
, m
);
4600 inst
->remove(block
);
4606 invalidate_live_intervals();
4612 fs_visitor::dump_instructions()
4614 dump_instructions(NULL
);
4618 fs_visitor::dump_instructions(const char *name
)
4620 FILE *file
= stderr
;
4621 if (name
&& geteuid() != 0) {
4622 file
= fopen(name
, "w");
4628 calculate_register_pressure();
4629 int ip
= 0, max_pressure
= 0;
4630 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4631 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4632 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4633 dump_instruction(inst
, file
);
4636 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4639 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4640 fprintf(file
, "%4d: ", ip
++);
4641 dump_instruction(inst
, file
);
4645 if (file
!= stderr
) {
4651 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4653 dump_instruction(be_inst
, stderr
);
4657 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4659 fs_inst
*inst
= (fs_inst
*)be_inst
;
4661 if (inst
->predicate
) {
4662 fprintf(file
, "(%cf0.%d) ",
4663 inst
->predicate_inverse
? '-' : '+',
4667 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4669 fprintf(file
, ".sat");
4670 if (inst
->conditional_mod
) {
4671 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4672 if (!inst
->predicate
&&
4673 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4674 inst
->opcode
!= BRW_OPCODE_IF
&&
4675 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4676 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4679 fprintf(file
, "(%d) ", inst
->exec_size
);
4682 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4685 switch (inst
->dst
.file
) {
4687 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
4688 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
4689 inst
->dst
.subreg_offset
)
4690 fprintf(file
, "+%d.%d",
4691 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4694 fprintf(file
, "g%d", inst
->dst
.nr
);
4697 fprintf(file
, "m%d", inst
->dst
.nr
);
4700 fprintf(file
, "(null)");
4703 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4706 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4709 switch (inst
->dst
.nr
) {
4711 fprintf(file
, "null");
4713 case BRW_ARF_ADDRESS
:
4714 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
4716 case BRW_ARF_ACCUMULATOR
:
4717 fprintf(file
, "acc%d", inst
->dst
.subnr
);
4720 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4723 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4726 if (inst
->dst
.subnr
)
4727 fprintf(file
, "+%d", inst
->dst
.subnr
);
4730 unreachable("not reached");
4732 if (inst
->dst
.stride
!= 1)
4733 fprintf(file
, "<%u>", inst
->dst
.stride
);
4734 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4736 for (int i
= 0; i
< inst
->sources
; i
++) {
4737 if (inst
->src
[i
].negate
)
4739 if (inst
->src
[i
].abs
)
4741 switch (inst
->src
[i
].file
) {
4743 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
4744 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
4745 inst
->src
[i
].subreg_offset
)
4746 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4747 inst
->src
[i
].subreg_offset
);
4750 fprintf(file
, "g%d", inst
->src
[i
].nr
);
4753 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
4756 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
4759 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
4760 if (inst
->src
[i
].reladdr
) {
4761 fprintf(file
, "+reladdr");
4762 } else if (inst
->src
[i
].subreg_offset
) {
4763 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4764 inst
->src
[i
].subreg_offset
);
4768 fprintf(file
, "(null)");
4771 switch (inst
->src
[i
].type
) {
4772 case BRW_REGISTER_TYPE_F
:
4773 fprintf(file
, "%-gf", inst
->src
[i
].f
);
4775 case BRW_REGISTER_TYPE_W
:
4776 case BRW_REGISTER_TYPE_D
:
4777 fprintf(file
, "%dd", inst
->src
[i
].d
);
4779 case BRW_REGISTER_TYPE_UW
:
4780 case BRW_REGISTER_TYPE_UD
:
4781 fprintf(file
, "%uu", inst
->src
[i
].ud
);
4783 case BRW_REGISTER_TYPE_VF
:
4784 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4785 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
4786 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
4787 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
4788 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
4791 fprintf(file
, "???");
4796 switch (inst
->src
[i
].nr
) {
4798 fprintf(file
, "null");
4800 case BRW_ARF_ADDRESS
:
4801 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
4803 case BRW_ARF_ACCUMULATOR
:
4804 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
4807 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4810 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4813 if (inst
->src
[i
].subnr
)
4814 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
4817 if (inst
->src
[i
].abs
)
4820 if (inst
->src
[i
].file
!= IMM
) {
4822 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
4823 unsigned hstride
= inst
->src
[i
].hstride
;
4824 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
4826 stride
= inst
->src
[i
].stride
;
4829 fprintf(file
, "<%u>", stride
);
4831 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4834 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4835 fprintf(file
, ", ");
4840 if (inst
->force_writemask_all
)
4841 fprintf(file
, "NoMask ");
4843 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4844 if (inst
->force_sechalf
)
4845 fprintf(file
, "2ndhalf ");
4847 fprintf(file
, "1sthalf ");
4850 fprintf(file
, "\n");
4854 * Possibly returns an instruction that set up @param reg.
4856 * Sometimes we want to take the result of some expression/variable
4857 * dereference tree and rewrite the instruction generating the result
4858 * of the tree. When processing the tree, we know that the
4859 * instructions generated are all writing temporaries that are dead
4860 * outside of this tree. So, if we have some instructions that write
4861 * a temporary, we're free to point that temp write somewhere else.
4863 * Note that this doesn't guarantee that the instruction generated
4864 * only reg -- it might be the size=4 destination of a texture instruction.
4867 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4872 end
->is_partial_write() ||
4874 !reg
.equals(end
->dst
)) {
4882 fs_visitor::setup_fs_payload_gen6()
4884 assert(stage
== MESA_SHADER_FRAGMENT
);
4885 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4886 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4888 unsigned barycentric_interp_modes
=
4889 (stage
== MESA_SHADER_FRAGMENT
) ?
4890 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4892 assert(devinfo
->gen
>= 6);
4894 /* R0-1: masks, pixel X/Y coordinates. */
4895 payload
.num_regs
= 2;
4896 /* R2: only for 32-pixel dispatch.*/
4898 /* R3-26: barycentric interpolation coordinates. These appear in the
4899 * same order that they appear in the brw_wm_barycentric_interp_mode
4900 * enum. Each set of coordinates occupies 2 registers if dispatch width
4901 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4902 * appear if they were enabled using the "Barycentric Interpolation
4903 * Mode" bits in WM_STATE.
4905 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4906 if (barycentric_interp_modes
& (1 << i
)) {
4907 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4908 payload
.num_regs
+= 2;
4909 if (dispatch_width
== 16) {
4910 payload
.num_regs
+= 2;
4915 /* R27: interpolated depth if uses source depth */
4916 prog_data
->uses_src_depth
=
4917 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
4918 if (prog_data
->uses_src_depth
) {
4919 payload
.source_depth_reg
= payload
.num_regs
;
4921 if (dispatch_width
== 16) {
4922 /* R28: interpolated depth if not SIMD8. */
4927 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4928 prog_data
->uses_src_w
=
4929 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
4930 if (prog_data
->uses_src_w
) {
4931 payload
.source_w_reg
= payload
.num_regs
;
4933 if (dispatch_width
== 16) {
4934 /* R30: interpolated W if not SIMD8. */
4939 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4940 /* R31: MSAA position offsets. */
4941 if (prog_data
->uses_pos_offset
) {
4942 payload
.sample_pos_reg
= payload
.num_regs
;
4946 /* R32: MSAA input coverage mask */
4947 prog_data
->uses_sample_mask
=
4948 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
4949 if (prog_data
->uses_sample_mask
) {
4950 assert(devinfo
->gen
>= 7);
4951 payload
.sample_mask_in_reg
= payload
.num_regs
;
4953 if (dispatch_width
== 16) {
4954 /* R33: input coverage mask if not SIMD8. */
4959 /* R34-: bary for 32-pixel. */
4960 /* R58-59: interp W for 32-pixel. */
4962 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4963 source_depth_to_render_target
= true;
4968 fs_visitor::setup_vs_payload()
4970 /* R0: thread header, R1: urb handles */
4971 payload
.num_regs
= 2;
4975 * We are building the local ID push constant data using the simplest possible
4976 * method. We simply push the local IDs directly as they should appear in the
4977 * registers for the uvec3 gl_LocalInvocationID variable.
4979 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
4980 * registers worth of push constant space.
4982 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
4983 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
4986 * FINISHME: There are a few easy optimizations to consider.
4988 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
4989 * no need for using push constant space for that dimension.
4991 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
4992 * easily use 16-bit words rather than 32-bit dwords in the push constant
4995 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
4996 * conveying the data, and thereby reduce push constant usage.
5000 fs_visitor::setup_gs_payload()
5002 assert(stage
== MESA_SHADER_GEOMETRY
);
5004 struct brw_gs_prog_data
*gs_prog_data
=
5005 (struct brw_gs_prog_data
*) prog_data
;
5006 struct brw_vue_prog_data
*vue_prog_data
=
5007 (struct brw_vue_prog_data
*) prog_data
;
5009 /* R0: thread header, R1: output URB handles */
5010 payload
.num_regs
= 2;
5012 if (gs_prog_data
->include_primitive_id
) {
5013 /* R2: Primitive ID 0..7 */
5017 /* Use a maximum of 32 registers for push-model inputs. */
5018 const unsigned max_push_components
= 32;
5020 /* If pushing our inputs would take too many registers, reduce the URB read
5021 * length (which is in HWords, or 8 registers), and resort to pulling.
5023 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5024 * have to multiply by VerticesIn to obtain the total storage requirement.
5026 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5027 max_push_components
) {
5028 gs_prog_data
->base
.include_vue_handles
= true;
5030 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5031 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5033 vue_prog_data
->urb_read_length
=
5034 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5039 fs_visitor::setup_cs_payload()
5041 assert(devinfo
->gen
>= 7);
5042 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
5044 payload
.num_regs
= 1;
5046 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
5047 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
5048 payload
.local_invocation_id_reg
= payload
.num_regs
;
5049 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
5054 fs_visitor::calculate_register_pressure()
5056 invalidate_live_intervals();
5057 calculate_live_intervals();
5059 unsigned num_instructions
= 0;
5060 foreach_block(block
, cfg
)
5061 num_instructions
+= block
->instructions
.length();
5063 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5065 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5066 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5067 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5072 fs_visitor::optimize()
5074 /* Start by validating the shader we currently have. */
5077 /* bld is the common builder object pointing at the end of the program we
5078 * used to translate it into i965 IR. For the optimization and lowering
5079 * passes coming next, any code added after the end of the program without
5080 * having explicitly called fs_builder::at() clearly points at a mistake.
5081 * Ideally optimization passes wouldn't be part of the visitor so they
5082 * wouldn't have access to bld at all, but they do, so just in case some
5083 * pass forgets to ask for a location explicitly set it to NULL here to
5084 * make it trip. The dispatch width is initialized to a bogus value to
5085 * make sure that optimizations set the execution controls explicitly to
5086 * match the code they are manipulating instead of relying on the defaults.
5088 bld
= fs_builder(this, 64);
5090 assign_constant_locations();
5091 demote_pull_constants();
5095 split_virtual_grfs();
5098 #define OPT(pass, args...) ({ \
5100 bool this_progress = pass(args); \
5102 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5103 char filename[64]; \
5104 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5105 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5107 backend_shader::dump_instructions(filename); \
5112 progress = progress || this_progress; \
5116 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5118 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5119 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5121 backend_shader::dump_instructions(filename
);
5124 bool progress
= false;
5128 OPT(lower_simd_width
);
5129 OPT(lower_logical_sends
);
5136 OPT(remove_duplicate_mrf_writes
);
5140 OPT(opt_copy_propagate
);
5141 OPT(opt_predicated_break
, this);
5142 OPT(opt_cmod_propagation
);
5143 OPT(dead_code_eliminate
);
5144 OPT(opt_peephole_sel
);
5145 OPT(dead_control_flow_eliminate
, this);
5146 OPT(opt_register_renaming
);
5147 OPT(opt_redundant_discard_jumps
);
5148 OPT(opt_saturate_propagation
);
5149 OPT(opt_zero_samples
);
5150 OPT(register_coalesce
);
5151 OPT(compute_to_mrf
);
5152 OPT(eliminate_find_live_channel
);
5154 OPT(compact_virtual_grfs
);
5159 OPT(opt_sampler_eot
);
5161 if (OPT(lower_load_payload
)) {
5162 split_virtual_grfs();
5163 OPT(register_coalesce
);
5164 OPT(compute_to_mrf
);
5165 OPT(dead_code_eliminate
);
5168 OPT(opt_combine_constants
);
5169 OPT(lower_integer_multiplication
);
5171 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5172 OPT(opt_cmod_propagation
);
5174 OPT(opt_copy_propagate
);
5175 OPT(dead_code_eliminate
);
5178 lower_uniform_pull_constant_loads();
5184 * Three source instruction must have a GRF/MRF destination register.
5185 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5188 fs_visitor::fixup_3src_null_dest()
5190 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5191 if (inst
->is_3src() && inst
->dst
.is_null()) {
5192 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5199 fs_visitor::allocate_registers()
5201 bool allocated_without_spills
;
5203 static const enum instruction_scheduler_mode pre_modes
[] = {
5205 SCHEDULE_PRE_NON_LIFO
,
5209 /* Try each scheduling heuristic to see if it can successfully register
5210 * allocate without spilling. They should be ordered by decreasing
5211 * performance but increasing likelihood of allocating.
5213 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5214 schedule_instructions(pre_modes
[i
]);
5217 assign_regs_trivial();
5218 allocated_without_spills
= true;
5220 allocated_without_spills
= assign_regs(false);
5222 if (allocated_without_spills
)
5226 if (!allocated_without_spills
) {
5227 /* We assume that any spilling is worse than just dropping back to
5228 * SIMD8. There's probably actually some intermediate point where
5229 * SIMD16 with a couple of spills is still better.
5231 if (dispatch_width
== 16 && min_dispatch_width
<= 8) {
5232 fail("Failure to register allocate. Reduce number of "
5233 "live scalar values to avoid this.");
5235 compiler
->shader_perf_log(log_data
,
5236 "%s shader triggered register spilling. "
5237 "Try reducing the number of live scalar "
5238 "values to improve performance.\n",
5242 /* Since we're out of heuristics, just go spill registers until we
5243 * get an allocation.
5245 while (!assign_regs(true)) {
5251 /* This must come after all optimization and register allocation, since
5252 * it inserts dead code that happens to have side effects, and it does
5253 * so based on the actual physical registers in use.
5255 insert_gen4_send_dependency_workarounds();
5260 schedule_instructions(SCHEDULE_POST
);
5262 if (last_scratch
> 0)
5263 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5267 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5269 assert(stage
== MESA_SHADER_VERTEX
);
5273 if (shader_time_index
>= 0)
5274 emit_shader_time_begin();
5281 compute_clip_distance(clip_planes
);
5285 if (shader_time_index
>= 0)
5286 emit_shader_time_end();
5292 assign_curb_setup();
5293 assign_vs_urb_setup();
5295 fixup_3src_null_dest();
5296 allocate_registers();
5302 fs_visitor::run_tes()
5304 assert(stage
== MESA_SHADER_TESS_EVAL
);
5306 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
5307 payload
.num_regs
= 5;
5309 if (shader_time_index
>= 0)
5310 emit_shader_time_begin();
5319 if (shader_time_index
>= 0)
5320 emit_shader_time_end();
5326 assign_curb_setup();
5327 assign_tes_urb_setup();
5329 fixup_3src_null_dest();
5330 allocate_registers();
5336 fs_visitor::run_gs()
5338 assert(stage
== MESA_SHADER_GEOMETRY
);
5342 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
5344 if (gs_compile
->control_data_header_size_bits
> 0) {
5345 /* Create a VGRF to store accumulated control data bits. */
5346 this->control_data_bits
= vgrf(glsl_type::uint_type
);
5348 /* If we're outputting more than 32 control data bits, then EmitVertex()
5349 * will set control_data_bits to 0 after emitting the first vertex.
5350 * Otherwise, we need to initialize it to 0 here.
5352 if (gs_compile
->control_data_header_size_bits
<= 32) {
5353 const fs_builder abld
= bld
.annotate("initialize control data bits");
5354 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
5358 if (shader_time_index
>= 0)
5359 emit_shader_time_begin();
5363 emit_gs_thread_end();
5365 if (shader_time_index
>= 0)
5366 emit_shader_time_end();
5375 assign_curb_setup();
5376 assign_gs_urb_setup();
5378 fixup_3src_null_dest();
5379 allocate_registers();
5385 fs_visitor::run_fs(bool do_rep_send
)
5387 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5388 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
5390 assert(stage
== MESA_SHADER_FRAGMENT
);
5392 if (devinfo
->gen
>= 6)
5393 setup_fs_payload_gen6();
5395 setup_fs_payload_gen4();
5399 } else if (do_rep_send
) {
5400 assert(dispatch_width
== 16);
5401 emit_repclear_shader();
5403 if (shader_time_index
>= 0)
5404 emit_shader_time_begin();
5406 calculate_urb_setup();
5407 if (nir
->info
.inputs_read
> 0) {
5408 if (devinfo
->gen
< 6)
5409 emit_interpolation_setup_gen4();
5411 emit_interpolation_setup_gen6();
5414 /* We handle discards by keeping track of the still-live pixels in f0.1.
5415 * Initialize it with the dispatched pixels.
5417 if (wm_prog_data
->uses_kill
) {
5418 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5419 discard_init
->flag_subreg
= 1;
5422 /* Generate FS IR for main(). (the visitor only descends into
5423 * functions called "main").
5430 if (wm_prog_data
->uses_kill
)
5431 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5433 if (wm_key
->alpha_test_func
)
5438 if (shader_time_index
>= 0)
5439 emit_shader_time_end();
5445 assign_curb_setup();
5448 fixup_3src_null_dest();
5449 allocate_registers();
5455 if (dispatch_width
== 8)
5456 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5458 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5464 fs_visitor::run_cs()
5466 assert(stage
== MESA_SHADER_COMPUTE
);
5470 if (shader_time_index
>= 0)
5471 emit_shader_time_begin();
5473 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
5474 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
5475 const fs_builder abld
= bld
.exec_all().group(1, 0);
5476 abld
.MOV(retype(suboffset(brw_sr0_reg(), 1), BRW_REGISTER_TYPE_UW
),
5477 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
5485 emit_cs_terminate();
5487 if (shader_time_index
>= 0)
5488 emit_shader_time_end();
5494 assign_curb_setup();
5496 fixup_3src_null_dest();
5497 allocate_registers();
5506 * Return a bitfield where bit n is set if barycentric interpolation mode n
5507 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
5510 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
5511 bool shade_model_flat
,
5512 bool persample_shading
,
5513 const nir_shader
*shader
)
5515 unsigned barycentric_interp_modes
= 0;
5517 nir_foreach_variable(var
, &shader
->inputs
) {
5518 enum glsl_interp_qualifier interp_qualifier
=
5519 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5520 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
5521 bool is_sample
= var
->data
.sample
|| persample_shading
;
5522 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5523 (var
->data
.location
== VARYING_SLOT_COL1
);
5525 /* Ignore WPOS and FACE, because they don't require interpolation. */
5526 if (var
->data
.location
== VARYING_SLOT_POS
||
5527 var
->data
.location
== VARYING_SLOT_FACE
)
5530 /* Determine the set (or sets) of barycentric coordinates needed to
5531 * interpolate this variable. Note that when
5532 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
5533 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
5534 * for lit pixels, so we need both sets of barycentric coordinates.
5536 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
5538 barycentric_interp_modes
|=
5539 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
5540 } else if (is_sample
) {
5541 barycentric_interp_modes
|=
5542 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
5544 if ((!is_centroid
&& !is_sample
) ||
5545 devinfo
->needs_unlit_centroid_workaround
) {
5546 barycentric_interp_modes
|=
5547 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
5549 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
5550 (!(shade_model_flat
&& is_gl_Color
) &&
5551 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
5553 barycentric_interp_modes
|=
5554 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
5555 } else if (is_sample
) {
5556 barycentric_interp_modes
|=
5557 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
5559 if ((!is_centroid
&& !is_sample
) ||
5560 devinfo
->needs_unlit_centroid_workaround
) {
5561 barycentric_interp_modes
|=
5562 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
5567 return barycentric_interp_modes
;
5571 computed_depth_mode(const nir_shader
*shader
)
5573 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5574 switch (shader
->info
.fs
.depth_layout
) {
5575 case FRAG_DEPTH_LAYOUT_NONE
:
5576 case FRAG_DEPTH_LAYOUT_ANY
:
5577 return BRW_PSCDEPTH_ON
;
5578 case FRAG_DEPTH_LAYOUT_GREATER
:
5579 return BRW_PSCDEPTH_ON_GE
;
5580 case FRAG_DEPTH_LAYOUT_LESS
:
5581 return BRW_PSCDEPTH_ON_LE
;
5582 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
5583 return BRW_PSCDEPTH_OFF
;
5586 return BRW_PSCDEPTH_OFF
;
5590 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
5592 const struct brw_wm_prog_key
*key
,
5593 struct brw_wm_prog_data
*prog_data
,
5594 const nir_shader
*src_shader
,
5595 struct gl_program
*prog
,
5596 int shader_time_index8
, int shader_time_index16
,
5598 unsigned *final_assembly_size
,
5601 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
5602 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
5604 brw_nir_lower_fs_inputs(shader
);
5605 brw_nir_lower_fs_outputs(shader
);
5606 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
5608 /* key->alpha_test_func means simulating alpha testing via discards,
5609 * so the shader definitely kills pixels.
5611 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
5612 prog_data
->uses_omask
=
5613 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
5614 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
5615 prog_data
->computed_stencil
=
5616 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
5618 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
5620 prog_data
->barycentric_interp_modes
=
5621 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
5623 key
->persample_shading
,
5626 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
,
5627 &prog_data
->base
, prog
, shader
, 8,
5628 shader_time_index8
);
5629 if (!v
.run_fs(false /* do_rep_send */)) {
5631 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
5636 cfg_t
*simd16_cfg
= NULL
;
5637 fs_visitor
v2(compiler
, log_data
, mem_ctx
, key
,
5638 &prog_data
->base
, prog
, shader
, 16,
5639 shader_time_index16
);
5640 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
5641 if (!v
.simd16_unsupported
) {
5642 /* Try a SIMD16 compile */
5643 v2
.import_uniforms(&v
);
5644 if (!v2
.run_fs(use_rep_send
)) {
5645 compiler
->shader_perf_log(log_data
,
5646 "SIMD16 shader failed to compile: %s",
5649 simd16_cfg
= v2
.cfg
;
5655 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || use_rep_send
;
5656 if ((no_simd8
|| compiler
->devinfo
->gen
< 5) && simd16_cfg
) {
5658 prog_data
->no_8
= true;
5661 prog_data
->no_8
= false;
5664 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
5665 v
.promoted_constants
, v
.runtime_check_aads_emit
,
5666 MESA_SHADER_FRAGMENT
);
5668 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5669 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
5670 shader
->info
.label
? shader
->info
.label
:
5672 shader
->info
.name
));
5676 g
.generate_code(simd8_cfg
, 8);
5678 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5680 return g
.get_assembly(final_assembly_size
);
5684 fs_visitor::emit_cs_local_invocation_id_setup()
5686 assert(stage
== MESA_SHADER_COMPUTE
);
5688 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5690 struct brw_reg src
=
5691 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
5692 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
5694 src
.nr
+= dispatch_width
/ 8;
5695 bld
.MOV(offset(*reg
, bld
, 1), src
);
5696 src
.nr
+= dispatch_width
/ 8;
5697 bld
.MOV(offset(*reg
, bld
, 2), src
);
5703 fs_visitor::emit_cs_work_group_id_setup()
5705 assert(stage
== MESA_SHADER_COMPUTE
);
5707 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5709 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
5710 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
5711 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
5713 bld
.MOV(*reg
, r0_1
);
5714 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
5715 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
5721 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
5723 const struct brw_cs_prog_key
*key
,
5724 struct brw_cs_prog_data
*prog_data
,
5725 const nir_shader
*src_shader
,
5726 int shader_time_index
,
5727 unsigned *final_assembly_size
,
5730 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
5731 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
5733 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
5735 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
5736 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
5737 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
5738 unsigned local_workgroup_size
=
5739 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
5740 shader
->info
.cs
.local_size
[2];
5742 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
5743 unsigned simd_required
= DIV_ROUND_UP(local_workgroup_size
, max_cs_threads
);
5746 const char *fail_msg
= NULL
;
5748 /* Now the main event: Visit the shader IR and generate our CS IR for it.
5750 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5751 NULL
, /* Never used in core profile */
5752 shader
, 8, shader_time_index
);
5753 if (simd_required
<= 8) {
5755 fail_msg
= v8
.fail_msg
;
5758 prog_data
->simd_size
= 8;
5762 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5763 NULL
, /* Never used in core profile */
5764 shader
, 16, shader_time_index
);
5765 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
5766 !fail_msg
&& !v8
.simd16_unsupported
&&
5767 local_workgroup_size
<= 16 * max_cs_threads
) {
5768 /* Try a SIMD16 compile */
5769 if (simd_required
<= 8)
5770 v16
.import_uniforms(&v8
);
5771 if (!v16
.run_cs()) {
5772 compiler
->shader_perf_log(log_data
,
5773 "SIMD16 shader failed to compile: %s",
5777 "Couldn't generate SIMD16 program and not "
5778 "enough threads for SIMD8";
5782 prog_data
->simd_size
= 16;
5786 if (unlikely(cfg
== NULL
)) {
5789 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
5794 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
5795 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
5796 MESA_SHADER_COMPUTE
);
5797 if (INTEL_DEBUG
& DEBUG_CS
) {
5798 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
5799 shader
->info
.label
? shader
->info
.label
:
5802 g
.enable_debug(name
);
5805 g
.generate_code(cfg
, prog_data
->simd_size
);
5807 return g
.get_assembly(final_assembly_size
);
5811 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*prog_data
,
5812 void *buffer
, uint32_t threads
, uint32_t stride
)
5814 if (prog_data
->local_invocation_id_regs
== 0)
5817 /* 'stride' should be an integer number of registers, that is, a multiple
5820 assert(stride
% 32 == 0);
5822 unsigned x
= 0, y
= 0, z
= 0;
5823 for (unsigned t
= 0; t
< threads
; t
++) {
5824 uint32_t *param
= (uint32_t *) buffer
+ stride
* t
/ 4;
5826 for (unsigned i
= 0; i
< prog_data
->simd_size
; i
++) {
5827 param
[0 * prog_data
->simd_size
+ i
] = x
;
5828 param
[1 * prog_data
->simd_size
+ i
] = y
;
5829 param
[2 * prog_data
->simd_size
+ i
] = z
;
5832 if (x
== prog_data
->local_size
[0]) {
5835 if (y
== prog_data
->local_size
[1]) {
5838 if (z
== prog_data
->local_size
[2])