2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
47 #include "brw_dead_control_flow.h"
48 #include "main/uniforms.h"
49 #include "brw_fs_live_variables.h"
50 #include "glsl/nir/glsl_types.h"
51 #include "program/sampler.h"
56 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
57 const fs_reg
*src
, unsigned sources
)
59 memset(this, 0, sizeof(*this));
61 this->src
= new fs_reg
[MAX2(sources
, 3)];
62 for (unsigned i
= 0; i
< sources
; i
++)
63 this->src
[i
] = src
[i
];
65 this->opcode
= opcode
;
67 this->sources
= sources
;
68 this->exec_size
= exec_size
;
70 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
72 assert(this->exec_size
!= 0);
74 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
76 /* This will be the case for almost all instructions. */
82 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
86 this->regs_written
= 0;
90 unreachable("Invalid destination register file");
92 unreachable("Invalid register file");
95 this->writes_accumulator
= false;
100 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
103 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
105 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
108 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
110 init(opcode
, exec_size
, dst
, NULL
, 0);
113 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
116 const fs_reg src
[1] = { src0
};
117 init(opcode
, exec_size
, dst
, src
, 1);
120 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
121 const fs_reg
&src0
, const fs_reg
&src1
)
123 const fs_reg src
[2] = { src0
, src1
};
124 init(opcode
, exec_size
, dst
, src
, 2);
127 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
128 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
130 const fs_reg src
[3] = { src0
, src1
, src2
};
131 init(opcode
, exec_size
, dst
, src
, 3);
134 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
135 const fs_reg src
[], unsigned sources
)
137 init(opcode
, exec_width
, dst
, src
, sources
);
140 fs_inst::fs_inst(const fs_inst
&that
)
142 memcpy(this, &that
, sizeof(that
));
144 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
146 for (unsigned i
= 0; i
< that
.sources
; i
++)
147 this->src
[i
] = that
.src
[i
];
156 fs_inst::resize_sources(uint8_t num_sources
)
158 if (this->sources
!= num_sources
) {
159 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
161 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
162 src
[i
] = this->src
[i
];
166 this->sources
= num_sources
;
171 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
173 const fs_reg
&surf_index
,
174 const fs_reg
&varying_offset
,
175 uint32_t const_offset
)
177 /* We have our constant surface use a pitch of 4 bytes, so our index can
178 * be any component of a vector, and then we load 4 contiguous
179 * components starting from that.
181 * We break down the const_offset to a portion added to the variable
182 * offset and a portion done using reg_offset, which means that if you
183 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
184 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
185 * CSE can later notice that those loads are all the same and eliminate
186 * the redundant ones.
188 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
189 bld
.ADD(vec4_offset
, varying_offset
, fs_reg(const_offset
& ~3));
192 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
193 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
194 * u, v, r) as parameters, or we can just use the SIMD16 message
195 * consisting of (header, u). We choose the second, at the cost of a
196 * longer return length.
202 if (devinfo
->gen
>= 7)
203 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
205 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
207 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
208 fs_reg vec4_result
= fs_reg(GRF
, alloc
.allocate(regs_written
), dst
.type
);
209 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
210 inst
->regs_written
= regs_written
;
212 if (devinfo
->gen
< 7) {
213 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
);
214 inst
->header_size
= 1;
215 if (devinfo
->gen
== 4)
218 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
221 bld
.MOV(dst
, offset(vec4_result
, bld
, (const_offset
& 3) * scale
));
225 * A helper for MOV generation for fixing up broken hardware SEND dependency
229 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
231 /* The caller always wants uncompressed to emit the minimal extra
232 * dependencies, and to avoid having to deal with aligning its regs to 2.
234 const fs_builder ubld
= bld
.annotate("send dependency resolve")
237 ubld
.MOV(ubld
.null_reg_f(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
241 fs_inst::equals(fs_inst
*inst
) const
243 return (opcode
== inst
->opcode
&&
244 dst
.equals(inst
->dst
) &&
245 src
[0].equals(inst
->src
[0]) &&
246 src
[1].equals(inst
->src
[1]) &&
247 src
[2].equals(inst
->src
[2]) &&
248 saturate
== inst
->saturate
&&
249 predicate
== inst
->predicate
&&
250 conditional_mod
== inst
->conditional_mod
&&
251 mlen
== inst
->mlen
&&
252 base_mrf
== inst
->base_mrf
&&
253 target
== inst
->target
&&
255 header_size
== inst
->header_size
&&
256 shadow_compare
== inst
->shadow_compare
&&
257 exec_size
== inst
->exec_size
&&
258 offset
== inst
->offset
);
262 fs_inst::overwrites_reg(const fs_reg
®
) const
264 return reg
.in_range(dst
, regs_written
);
268 fs_inst::is_send_from_grf() const
271 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
272 case SHADER_OPCODE_SHADER_TIME_ADD
:
273 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
274 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
275 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
276 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
277 case SHADER_OPCODE_UNTYPED_ATOMIC
:
278 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
279 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
280 case SHADER_OPCODE_TYPED_ATOMIC
:
281 case SHADER_OPCODE_TYPED_SURFACE_READ
:
282 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
283 case SHADER_OPCODE_URB_WRITE_SIMD8
:
284 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
285 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
286 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
287 case SHADER_OPCODE_URB_READ_SIMD8
:
289 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
290 return src
[1].file
== GRF
;
291 case FS_OPCODE_FB_WRITE
:
292 return src
[0].file
== GRF
;
295 return src
[0].file
== GRF
;
302 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
304 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
307 fs_reg reg
= this->src
[0];
308 if (reg
.file
!= GRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
311 if (grf_alloc
.sizes
[reg
.reg
] != this->regs_written
)
314 for (int i
= 0; i
< this->sources
; i
++) {
315 reg
.type
= this->src
[i
].type
;
316 if (!this->src
[i
].equals(reg
))
319 if (i
< this->header_size
) {
322 reg
.reg_offset
+= this->exec_size
/ 8;
330 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
332 if (devinfo
->gen
== 6 && is_math())
335 if (is_send_from_grf())
338 if (!backend_instruction::can_do_source_mods())
345 fs_inst::can_change_types() const
347 return dst
.type
== src
[0].type
&&
348 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
349 (opcode
== BRW_OPCODE_MOV
||
350 (opcode
== BRW_OPCODE_SEL
&&
351 dst
.type
== src
[1].type
&&
352 predicate
!= BRW_PREDICATE_NONE
&&
353 !src
[1].abs
&& !src
[1].negate
));
357 fs_inst::has_side_effects() const
359 return this->eot
|| backend_instruction::has_side_effects();
365 memset(this, 0, sizeof(*this));
369 /** Generic unset register constructor. */
373 this->file
= BAD_FILE
;
376 /** Immediate value constructor. */
377 fs_reg::fs_reg(float f
)
381 this->type
= BRW_REGISTER_TYPE_F
;
383 this->fixed_hw_reg
.dw1
.f
= f
;
386 /** Immediate value constructor. */
387 fs_reg::fs_reg(int32_t i
)
391 this->type
= BRW_REGISTER_TYPE_D
;
393 this->fixed_hw_reg
.dw1
.d
= i
;
396 /** Immediate value constructor. */
397 fs_reg::fs_reg(uint32_t u
)
401 this->type
= BRW_REGISTER_TYPE_UD
;
403 this->fixed_hw_reg
.dw1
.ud
= u
;
406 /** Vector float immediate value constructor. */
407 fs_reg::fs_reg(uint8_t vf
[4])
411 this->type
= BRW_REGISTER_TYPE_VF
;
412 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
415 /** Vector float immediate value constructor. */
416 fs_reg::fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
420 this->type
= BRW_REGISTER_TYPE_VF
;
421 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
427 /** Fixed brw_reg. */
428 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
432 this->fixed_hw_reg
= fixed_hw_reg
;
433 this->type
= fixed_hw_reg
.type
;
437 fs_reg::equals(const fs_reg
&r
) const
439 return (file
== r
.file
&&
441 reg_offset
== r
.reg_offset
&&
442 subreg_offset
== r
.subreg_offset
&&
444 negate
== r
.negate
&&
446 !reladdr
&& !r
.reladdr
&&
447 ((file
!= HW_REG
&& file
!= IMM
) ||
448 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
449 sizeof(fixed_hw_reg
)) == 0) &&
454 fs_reg::set_smear(unsigned subreg
)
456 assert(file
!= HW_REG
&& file
!= IMM
);
457 subreg_offset
= subreg
* type_sz(type
);
463 fs_reg::is_contiguous() const
469 fs_reg::component_size(unsigned width
) const
471 const unsigned stride
= (file
!= HW_REG
? this->stride
:
472 fixed_hw_reg
.hstride
== 0 ? 0 :
473 1 << (fixed_hw_reg
.hstride
- 1));
474 return MAX2(width
* stride
, 1) * type_sz(type
);
478 type_size_scalar(const struct glsl_type
*type
)
480 unsigned int size
, i
;
482 switch (type
->base_type
) {
485 case GLSL_TYPE_FLOAT
:
487 return type
->components();
488 case GLSL_TYPE_ARRAY
:
489 return type_size_scalar(type
->fields
.array
) * type
->length
;
490 case GLSL_TYPE_STRUCT
:
492 for (i
= 0; i
< type
->length
; i
++) {
493 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
496 case GLSL_TYPE_SAMPLER
:
497 /* Samplers take up no register space, since they're baked in at
501 case GLSL_TYPE_ATOMIC_UINT
:
503 case GLSL_TYPE_SUBROUTINE
:
505 case GLSL_TYPE_IMAGE
:
506 return BRW_IMAGE_PARAM_SIZE
;
508 case GLSL_TYPE_ERROR
:
509 case GLSL_TYPE_INTERFACE
:
510 case GLSL_TYPE_DOUBLE
:
511 unreachable("not reached");
518 * Create a MOV to read the timestamp register.
520 * The caller is responsible for emitting the MOV. The return value is
521 * the destination of the MOV, with extra parameters set.
524 fs_visitor::get_timestamp(const fs_builder
&bld
)
526 assert(devinfo
->gen
>= 7);
528 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
531 BRW_REGISTER_TYPE_UD
));
533 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
535 /* We want to read the 3 fields we care about even if it's not enabled in
538 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
540 /* The caller wants the low 32 bits of the timestamp. Since it's running
541 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
542 * which is plenty of time for our purposes. It is identical across the
543 * EUs, but since it's tracking GPU core speed it will increment at a
544 * varying rate as render P-states change.
546 * The caller could also check if render P-states have changed (or anything
547 * else that might disrupt timing) by setting smear to 2 and checking if
548 * that field is != 0.
556 fs_visitor::emit_shader_time_begin()
558 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
562 fs_visitor::emit_shader_time_end()
564 /* Insert our code just before the final SEND with EOT. */
565 exec_node
*end
= this->instructions
.get_tail();
566 assert(end
&& ((fs_inst
*) end
)->eot
);
567 const fs_builder ibld
= bld
.annotate("shader time end")
568 .exec_all().at(NULL
, end
);
570 fs_reg shader_end_time
= get_timestamp(ibld
);
572 /* Check that there weren't any timestamp reset events (assuming these
573 * were the only two timestamp reads that happened).
575 fs_reg reset
= shader_end_time
;
577 set_condmod(BRW_CONDITIONAL_Z
,
578 ibld
.AND(ibld
.null_reg_ud(), reset
, fs_reg(1u)));
579 ibld
.IF(BRW_PREDICATE_NORMAL
);
581 fs_reg start
= shader_start_time
;
583 fs_reg diff
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
586 const fs_builder cbld
= ibld
.group(1, 0);
587 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
589 /* If there were no instructions between the two timestamp gets, the diff
590 * is 2 cycles. Remove that overhead, so I can forget about that when
591 * trying to determine the time taken for single instructions.
593 cbld
.ADD(diff
, diff
, fs_reg(-2u));
594 SHADER_TIME_ADD(cbld
, 0, diff
);
595 SHADER_TIME_ADD(cbld
, 1, fs_reg(1u));
596 ibld
.emit(BRW_OPCODE_ELSE
);
597 SHADER_TIME_ADD(cbld
, 2, fs_reg(1u));
598 ibld
.emit(BRW_OPCODE_ENDIF
);
602 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
603 int shader_time_subindex
,
606 int index
= shader_time_index
* 3 + shader_time_subindex
;
607 fs_reg offset
= fs_reg(index
* SHADER_TIME_STRIDE
);
610 if (dispatch_width
== 8)
611 payload
= vgrf(glsl_type::uvec2_type
);
613 payload
= vgrf(glsl_type::uint_type
);
615 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
619 fs_visitor::vfail(const char *format
, va_list va
)
628 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
629 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
631 this->fail_msg
= msg
;
634 fprintf(stderr
, "%s", msg
);
639 fs_visitor::fail(const char *format
, ...)
643 va_start(va
, format
);
649 * Mark this program as impossible to compile in SIMD16 mode.
651 * During the SIMD8 compile (which happens first), we can detect and flag
652 * things that are unsupported in SIMD16 mode, so the compiler can skip
653 * the SIMD16 compile altogether.
655 * During a SIMD16 compile (if one happens anyway), this just calls fail().
658 fs_visitor::no16(const char *msg
)
660 if (dispatch_width
== 16) {
663 simd16_unsupported
= true;
665 compiler
->shader_perf_log(log_data
,
666 "SIMD16 shader failed to compile: %s", msg
);
671 * Returns true if the instruction has a flag that means it won't
672 * update an entire destination register.
674 * For example, dead code elimination and live variable analysis want to know
675 * when a write to a variable screens off any preceding values that were in
679 fs_inst::is_partial_write() const
681 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
682 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
683 !this->dst
.is_contiguous());
687 fs_inst::components_read(unsigned i
) const
690 case FS_OPCODE_LINTERP
:
696 case FS_OPCODE_PIXEL_X
:
697 case FS_OPCODE_PIXEL_Y
:
701 case FS_OPCODE_FB_WRITE_LOGICAL
:
702 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
703 /* First/second FB write color. */
705 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].fixed_hw_reg
.dw1
.ud
;
709 case SHADER_OPCODE_TEX_LOGICAL
:
710 case SHADER_OPCODE_TXD_LOGICAL
:
711 case SHADER_OPCODE_TXF_LOGICAL
:
712 case SHADER_OPCODE_TXL_LOGICAL
:
713 case SHADER_OPCODE_TXS_LOGICAL
:
714 case FS_OPCODE_TXB_LOGICAL
:
715 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
716 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
717 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
718 case SHADER_OPCODE_LOD_LOGICAL
:
719 case SHADER_OPCODE_TG4_LOGICAL
:
720 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
721 assert(src
[8].file
== IMM
&& src
[9].file
== IMM
);
722 /* Texture coordinates. */
724 return src
[8].fixed_hw_reg
.dw1
.ud
;
725 /* Texture derivatives. */
726 else if ((i
== 2 || i
== 3) && opcode
== SHADER_OPCODE_TXD_LOGICAL
)
727 return src
[9].fixed_hw_reg
.dw1
.ud
;
728 /* Texture offset. */
734 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
735 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
736 assert(src
[3].file
== IMM
);
737 /* Surface coordinates. */
739 return src
[3].fixed_hw_reg
.dw1
.ud
;
740 /* Surface operation source (ignored for reads). */
746 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
747 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
748 assert(src
[3].file
== IMM
&&
750 /* Surface coordinates. */
752 return src
[3].fixed_hw_reg
.dw1
.ud
;
753 /* Surface operation source. */
755 return src
[4].fixed_hw_reg
.dw1
.ud
;
759 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
760 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
761 assert(src
[3].file
== IMM
&&
763 const unsigned op
= src
[4].fixed_hw_reg
.dw1
.ud
;
764 /* Surface coordinates. */
766 return src
[3].fixed_hw_reg
.dw1
.ud
;
767 /* Surface operation source. */
768 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
770 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
771 op
== BRW_AOP_PREDEC
))
783 fs_inst::regs_read(int arg
) const
786 case FS_OPCODE_FB_WRITE
:
787 case SHADER_OPCODE_URB_WRITE_SIMD8
:
788 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
789 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
790 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
791 case SHADER_OPCODE_URB_READ_SIMD8
:
792 case SHADER_OPCODE_UNTYPED_ATOMIC
:
793 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
794 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
795 case SHADER_OPCODE_TYPED_ATOMIC
:
796 case SHADER_OPCODE_TYPED_SURFACE_READ
:
797 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
798 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
803 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
804 /* The payload is actually stored in src1 */
809 case FS_OPCODE_LINTERP
:
814 case SHADER_OPCODE_LOAD_PAYLOAD
:
815 if (arg
< this->header_size
)
819 case CS_OPCODE_CS_TERMINATE
:
820 case SHADER_OPCODE_BARRIER
:
824 if (is_tex() && arg
== 0 && src
[0].file
== GRF
)
829 switch (src
[arg
].file
) {
838 return DIV_ROUND_UP(components_read(arg
) *
839 src
[arg
].component_size(exec_size
),
842 unreachable("MRF registers are not allowed as sources");
844 unreachable("Invalid register file");
849 fs_inst::reads_flag() const
855 fs_inst::writes_flag() const
857 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
858 opcode
!= BRW_OPCODE_IF
&&
859 opcode
!= BRW_OPCODE_WHILE
)) ||
860 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
864 * Returns how many MRFs an FS opcode will write over.
866 * Note that this is not the 0 or 1 implied writes in an actual gen
867 * instruction -- the FS opcodes often generate MOVs in addition.
870 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
875 if (inst
->base_mrf
== -1)
878 switch (inst
->opcode
) {
879 case SHADER_OPCODE_RCP
:
880 case SHADER_OPCODE_RSQ
:
881 case SHADER_OPCODE_SQRT
:
882 case SHADER_OPCODE_EXP2
:
883 case SHADER_OPCODE_LOG2
:
884 case SHADER_OPCODE_SIN
:
885 case SHADER_OPCODE_COS
:
886 return 1 * dispatch_width
/ 8;
887 case SHADER_OPCODE_POW
:
888 case SHADER_OPCODE_INT_QUOTIENT
:
889 case SHADER_OPCODE_INT_REMAINDER
:
890 return 2 * dispatch_width
/ 8;
891 case SHADER_OPCODE_TEX
:
893 case SHADER_OPCODE_TXD
:
894 case SHADER_OPCODE_TXF
:
895 case SHADER_OPCODE_TXF_CMS
:
896 case SHADER_OPCODE_TXF_MCS
:
897 case SHADER_OPCODE_TG4
:
898 case SHADER_OPCODE_TG4_OFFSET
:
899 case SHADER_OPCODE_TXL
:
900 case SHADER_OPCODE_TXS
:
901 case SHADER_OPCODE_LOD
:
902 case SHADER_OPCODE_SAMPLEINFO
:
904 case FS_OPCODE_FB_WRITE
:
906 case FS_OPCODE_GET_BUFFER_SIZE
:
907 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
908 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
910 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
912 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
914 case SHADER_OPCODE_UNTYPED_ATOMIC
:
915 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
916 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
917 case SHADER_OPCODE_TYPED_ATOMIC
:
918 case SHADER_OPCODE_TYPED_SURFACE_READ
:
919 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
920 case SHADER_OPCODE_URB_WRITE_SIMD8
:
921 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
922 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
923 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
924 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
925 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
926 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
927 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
930 unreachable("not reached");
935 fs_visitor::vgrf(const glsl_type
*const type
)
937 int reg_width
= dispatch_width
/ 8;
938 return fs_reg(GRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
939 brw_type_for_base_type(type
));
942 /** Fixed HW reg constructor. */
943 fs_reg::fs_reg(enum register_file file
, int reg
)
948 this->type
= BRW_REGISTER_TYPE_F
;
949 this->stride
= (file
== UNIFORM
? 0 : 1);
952 /** Fixed HW reg constructor. */
953 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
)
959 this->stride
= (file
== UNIFORM
? 0 : 1);
962 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
963 * This brings in those uniform definitions
966 fs_visitor::import_uniforms(fs_visitor
*v
)
968 this->push_constant_loc
= v
->push_constant_loc
;
969 this->pull_constant_loc
= v
->pull_constant_loc
;
970 this->uniforms
= v
->uniforms
;
971 this->param_size
= v
->param_size
;
975 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
976 bool origin_upper_left
)
978 assert(stage
== MESA_SHADER_FRAGMENT
);
979 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
980 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
982 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
985 if (pixel_center_integer
) {
986 bld
.MOV(wpos
, this->pixel_x
);
988 bld
.ADD(wpos
, this->pixel_x
, fs_reg(0.5f
));
990 wpos
= offset(wpos
, bld
, 1);
993 if (!flip
&& pixel_center_integer
) {
994 bld
.MOV(wpos
, this->pixel_y
);
996 fs_reg pixel_y
= this->pixel_y
;
997 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
1000 pixel_y
.negate
= true;
1001 offset
+= key
->drawable_height
- 1.0f
;
1004 bld
.ADD(wpos
, pixel_y
, fs_reg(offset
));
1006 wpos
= offset(wpos
, bld
, 1);
1008 /* gl_FragCoord.z */
1009 if (devinfo
->gen
>= 6) {
1010 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1012 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1013 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1014 interp_reg(VARYING_SLOT_POS
, 2));
1016 wpos
= offset(wpos
, bld
, 1);
1018 /* gl_FragCoord.w: Already set up in emit_interpolation */
1019 bld
.MOV(wpos
, this->wpos_w
);
1025 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1026 glsl_interp_qualifier interpolation_mode
,
1027 bool is_centroid
, bool is_sample
)
1029 brw_wm_barycentric_interp_mode barycoord_mode
;
1030 if (devinfo
->gen
>= 6) {
1032 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1033 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1035 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1036 } else if (is_sample
) {
1037 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1038 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1040 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1042 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1043 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1045 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1048 /* On Ironlake and below, there is only one interpolation mode.
1049 * Centroid interpolation doesn't mean anything on this hardware --
1050 * there is no multisampling.
1052 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1054 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1055 this->delta_xy
[barycoord_mode
], interp
);
1059 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
1060 const glsl_type
*type
,
1061 glsl_interp_qualifier interpolation_mode
,
1062 int location
, bool mod_centroid
,
1065 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
1067 assert(stage
== MESA_SHADER_FRAGMENT
);
1068 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1069 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1071 unsigned int array_elements
;
1073 if (type
->is_array()) {
1074 array_elements
= type
->arrays_of_arrays_size();
1075 if (array_elements
== 0) {
1076 fail("dereferenced array '%s' has length 0\n", name
);
1078 type
= type
->without_array();
1083 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1085 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1086 if (key
->flat_shade
&& is_gl_Color
) {
1087 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1089 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1093 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1094 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1095 if (prog_data
->urb_setup
[location
] == -1) {
1096 /* If there's no incoming setup data for this slot, don't
1097 * emit interpolation for it.
1099 attr
= offset(attr
, bld
, type
->vector_elements
);
1104 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1105 /* Constant interpolation (flat shading) case. The SF has
1106 * handed us defined values in only the constant offset
1107 * field of the setup reg.
1109 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1110 struct brw_reg interp
= interp_reg(location
, k
);
1111 interp
= suboffset(interp
, 3);
1112 interp
.type
= attr
.type
;
1113 bld
.emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1114 attr
= offset(attr
, bld
, 1);
1117 /* Smooth/noperspective interpolation case. */
1118 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1119 struct brw_reg interp
= interp_reg(location
, k
);
1120 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1121 /* Get the pixel/sample mask into f0 so that we know
1122 * which pixels are lit. Then, for each channel that is
1123 * unlit, replace the centroid data with non-centroid
1126 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1129 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1131 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1132 inst
->predicate_inverse
= true;
1133 if (devinfo
->has_pln
)
1134 inst
->no_dd_clear
= true;
1136 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1137 mod_centroid
&& !key
->persample_shading
,
1138 mod_sample
|| key
->persample_shading
);
1139 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1140 inst
->predicate_inverse
= false;
1141 if (devinfo
->has_pln
)
1142 inst
->no_dd_check
= true;
1145 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1146 mod_centroid
&& !key
->persample_shading
,
1147 mod_sample
|| key
->persample_shading
);
1149 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1150 bld
.MUL(attr
, attr
, this->pixel_w
);
1152 attr
= offset(attr
, bld
, 1);
1162 fs_visitor::emit_frontfacing_interpolation()
1164 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1166 if (devinfo
->gen
>= 6) {
1167 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1168 * a boolean result from this (~0/true or 0/false).
1170 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1171 * this task in only one instruction:
1172 * - a negation source modifier will flip the bit; and
1173 * - a W -> D type conversion will sign extend the bit into the high
1174 * word of the destination.
1176 * An ASR 15 fills the low word of the destination.
1178 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1181 bld
.ASR(*reg
, g0
, fs_reg(15));
1183 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1184 * a boolean result from this (1/true or 0/false).
1186 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1187 * the negation source modifier to flip it. Unfortunately the SHR
1188 * instruction only operates on UD (or D with an abs source modifier)
1189 * sources without negation.
1191 * Instead, use ASR (which will give ~0/true or 0/false).
1193 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1196 bld
.ASR(*reg
, g1_6
, fs_reg(31));
1203 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1205 assert(stage
== MESA_SHADER_FRAGMENT
);
1206 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1207 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1209 if (key
->compute_pos_offset
) {
1210 /* Convert int_sample_pos to floating point */
1211 bld
.MOV(dst
, int_sample_pos
);
1212 /* Scale to the range [0, 1] */
1213 bld
.MUL(dst
, dst
, fs_reg(1 / 16.0f
));
1216 /* From ARB_sample_shading specification:
1217 * "When rendering to a non-multisample buffer, or if multisample
1218 * rasterization is disabled, gl_SamplePosition will always be
1221 bld
.MOV(dst
, fs_reg(0.5f
));
1226 fs_visitor::emit_samplepos_setup()
1228 assert(devinfo
->gen
>= 6);
1230 const fs_builder abld
= bld
.annotate("compute sample position");
1231 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1233 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1234 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1236 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1237 * mode will be enabled.
1239 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1240 * R31.1:0 Position Offset X/Y for Slot[3:0]
1241 * R31.3:2 Position Offset X/Y for Slot[7:4]
1244 * The X, Y sample positions come in as bytes in thread payload. So, read
1245 * the positions using vstride=16, width=8, hstride=2.
1247 struct brw_reg sample_pos_reg
=
1248 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1249 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1251 if (dispatch_width
== 8) {
1252 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1254 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1255 abld
.half(1).MOV(half(int_sample_x
, 1),
1256 fs_reg(suboffset(sample_pos_reg
, 16)));
1258 /* Compute gl_SamplePosition.x */
1259 compute_sample_position(pos
, int_sample_x
);
1260 pos
= offset(pos
, abld
, 1);
1261 if (dispatch_width
== 8) {
1262 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1264 abld
.half(0).MOV(half(int_sample_y
, 0),
1265 fs_reg(suboffset(sample_pos_reg
, 1)));
1266 abld
.half(1).MOV(half(int_sample_y
, 1),
1267 fs_reg(suboffset(sample_pos_reg
, 17)));
1269 /* Compute gl_SamplePosition.y */
1270 compute_sample_position(pos
, int_sample_y
);
1275 fs_visitor::emit_sampleid_setup()
1277 assert(stage
== MESA_SHADER_FRAGMENT
);
1278 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1279 assert(devinfo
->gen
>= 6);
1281 const fs_builder abld
= bld
.annotate("compute sample id");
1282 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1284 if (key
->compute_sample_id
) {
1285 fs_reg
t1(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1287 fs_reg
t2(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1289 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1290 * 8x multisampling, subspan 0 will represent sample N (where N
1291 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1292 * 7. We can find the value of N by looking at R0.0 bits 7:6
1293 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1294 * (since samples are always delivered in pairs). That is, we
1295 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1296 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1297 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1298 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1299 * populating a temporary variable with the sequence (0, 1, 2, 3),
1300 * and then reading from it using vstride=1, width=4, hstride=0.
1301 * These computations hold good for 4x multisampling as well.
1303 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1304 * the first four slots are sample 0 of subspan 0; the next four
1305 * are sample 1 of subspan 0; the third group is sample 0 of
1306 * subspan 1, and finally sample 1 of subspan 1.
1308 abld
.exec_all().group(1, 0)
1309 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1311 abld
.exec_all().group(1, 0).SHR(t1
, t1
, fs_reg(5));
1313 /* This works for both SIMD8 and SIMD16 */
1314 abld
.exec_all().group(4, 0)
1315 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1317 /* This special instruction takes care of setting vstride=1,
1318 * width=4, hstride=0 of t2 during an ADD instruction.
1320 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1322 /* As per GL_ARB_sample_shading specification:
1323 * "When rendering to a non-multisample buffer, or if multisample
1324 * rasterization is disabled, gl_SampleID will always be zero."
1326 abld
.MOV(*reg
, fs_reg(0));
1333 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1335 if (!src
.abs
&& !src
.negate
)
1338 fs_reg temp
= bld
.vgrf(src
.type
);
1345 fs_visitor::emit_discard_jump()
1347 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1349 /* For performance, after a discard, jump to the end of the
1350 * shader if all relevant channels have been discarded.
1352 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1353 discard_jump
->flag_subreg
= 1;
1355 discard_jump
->predicate
= (dispatch_width
== 8)
1356 ? BRW_PREDICATE_ALIGN1_ANY8H
1357 : BRW_PREDICATE_ALIGN1_ANY16H
;
1358 discard_jump
->predicate_inverse
= true;
1362 fs_visitor::assign_curb_setup()
1364 if (dispatch_width
== 8) {
1365 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1367 if (stage
== MESA_SHADER_FRAGMENT
) {
1368 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1369 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1370 } else if (stage
== MESA_SHADER_COMPUTE
) {
1371 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1372 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1374 unreachable("Unsupported shader type!");
1378 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1380 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1381 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1382 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1383 if (inst
->src
[i
].file
== UNIFORM
) {
1384 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1386 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1387 constant_nr
= push_constant_loc
[uniform_nr
];
1389 /* Section 5.11 of the OpenGL 4.1 spec says:
1390 * "Out-of-bounds reads return undefined values, which include
1391 * values from other variables of the active program or zero."
1392 * Just return the first push constant.
1397 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1401 assert(inst
->src
[i
].stride
== 0);
1402 inst
->src
[i
].file
= HW_REG
;
1403 inst
->src
[i
].fixed_hw_reg
= byte_offset(
1404 retype(brw_reg
, inst
->src
[i
].type
),
1405 inst
->src
[i
].subreg_offset
);
1410 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1411 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1415 fs_visitor::calculate_urb_setup()
1417 assert(stage
== MESA_SHADER_FRAGMENT
);
1418 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1419 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1421 memset(prog_data
->urb_setup
, -1,
1422 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1425 /* Figure out where each of the incoming setup attributes lands. */
1426 if (devinfo
->gen
>= 6) {
1427 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1428 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1429 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1430 * first 16 varying inputs, so we can put them wherever we want.
1431 * Just put them in order.
1433 * This is useful because it means that (a) inputs not used by the
1434 * fragment shader won't take up valuable register space, and (b) we
1435 * won't have to recompile the fragment shader if it gets paired with
1436 * a different vertex (or geometry) shader.
1438 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1439 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1440 BITFIELD64_BIT(i
)) {
1441 prog_data
->urb_setup
[i
] = urb_next
++;
1445 /* We have enough input varyings that the SF/SBE pipeline stage can't
1446 * arbitrarily rearrange them to suit our whim; we have to put them
1447 * in an order that matches the output of the previous pipeline stage
1448 * (geometry or vertex shader).
1450 struct brw_vue_map prev_stage_vue_map
;
1451 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1452 key
->input_slots_valid
,
1453 nir
->info
.separate_shader
);
1454 int first_slot
= 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1455 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1456 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1458 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1459 /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
1462 if (varying
!= BRW_VARYING_SLOT_COUNT
&&
1463 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1464 BITFIELD64_BIT(varying
))) {
1465 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1468 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1471 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1472 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1473 /* Point size is packed into the header, not as a general attribute */
1474 if (i
== VARYING_SLOT_PSIZ
)
1477 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1478 /* The back color slot is skipped when the front color is
1479 * also written to. In addition, some slots can be
1480 * written in the vertex shader and not read in the
1481 * fragment shader. So the register number must always be
1482 * incremented, mapped or not.
1484 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1485 prog_data
->urb_setup
[i
] = urb_next
;
1491 * It's a FS only attribute, and we did interpolation for this attribute
1492 * in SF thread. So, count it here, too.
1494 * See compile_sf_prog() for more info.
1496 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1497 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1500 prog_data
->num_varying_inputs
= urb_next
;
1504 fs_visitor::assign_urb_setup()
1506 assert(stage
== MESA_SHADER_FRAGMENT
);
1507 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1509 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1511 /* Offset all the urb_setup[] index by the actual position of the
1512 * setup regs, now that the location of the constants has been chosen.
1514 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1515 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1516 assert(inst
->src
[1].file
== HW_REG
);
1517 inst
->src
[1].fixed_hw_reg
.nr
+= urb_start
;
1520 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1521 assert(inst
->src
[0].file
== HW_REG
);
1522 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1526 /* Each attribute is 4 setup channels, each of which is half a reg. */
1527 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1531 fs_visitor::assign_vs_urb_setup()
1533 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1535 assert(stage
== MESA_SHADER_VERTEX
);
1536 int count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1537 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1540 /* Each attribute is 4 regs. */
1541 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attributes
;
1543 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1545 /* Rewrite all ATTR file references to the hw grf that they land in. */
1546 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1547 for (int i
= 0; i
< inst
->sources
; i
++) {
1548 if (inst
->src
[i
].file
== ATTR
) {
1549 int grf
= payload
.num_regs
+
1550 prog_data
->curb_read_length
+
1552 inst
->src
[i
].reg_offset
;
1554 inst
->src
[i
].file
= HW_REG
;
1555 inst
->src
[i
].fixed_hw_reg
=
1556 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1557 inst
->src
[i
].subreg_offset
),
1558 inst
->exec_size
* inst
->src
[i
].stride
,
1559 inst
->exec_size
, inst
->src
[i
].stride
);
1566 * Split large virtual GRFs into separate components if we can.
1568 * This is mostly duplicated with what brw_fs_vector_splitting does,
1569 * but that's really conservative because it's afraid of doing
1570 * splitting that doesn't result in real progress after the rest of
1571 * the optimization phases, which would cause infinite looping in
1572 * optimization. We can do it once here, safely. This also has the
1573 * opportunity to split interpolated values, or maybe even uniforms,
1574 * which we don't have at the IR level.
1576 * We want to split, because virtual GRFs are what we register
1577 * allocate and spill (due to contiguousness requirements for some
1578 * instructions), and they're what we naturally generate in the
1579 * codegen process, but most virtual GRFs don't actually need to be
1580 * contiguous sets of GRFs. If we split, we'll end up with reduced
1581 * live intervals and better dead code elimination and coalescing.
1584 fs_visitor::split_virtual_grfs()
1586 int num_vars
= this->alloc
.count
;
1588 /* Count the total number of registers */
1590 int vgrf_to_reg
[num_vars
];
1591 for (int i
= 0; i
< num_vars
; i
++) {
1592 vgrf_to_reg
[i
] = reg_count
;
1593 reg_count
+= alloc
.sizes
[i
];
1596 /* An array of "split points". For each register slot, this indicates
1597 * if this slot can be separated from the previous slot. Every time an
1598 * instruction uses multiple elements of a register (as a source or
1599 * destination), we mark the used slots as inseparable. Then we go
1600 * through and split the registers into the smallest pieces we can.
1602 bool split_points
[reg_count
];
1603 memset(split_points
, 0, sizeof(split_points
));
1605 /* Mark all used registers as fully splittable */
1606 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1607 if (inst
->dst
.file
== GRF
) {
1608 int reg
= vgrf_to_reg
[inst
->dst
.reg
];
1609 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.reg
]; j
++)
1610 split_points
[reg
+ j
] = true;
1613 for (int i
= 0; i
< inst
->sources
; i
++) {
1614 if (inst
->src
[i
].file
== GRF
) {
1615 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
];
1616 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].reg
]; j
++)
1617 split_points
[reg
+ j
] = true;
1622 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1623 if (inst
->dst
.file
== GRF
) {
1624 int reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1625 for (int j
= 1; j
< inst
->regs_written
; j
++)
1626 split_points
[reg
+ j
] = false;
1628 for (int i
= 0; i
< inst
->sources
; i
++) {
1629 if (inst
->src
[i
].file
== GRF
) {
1630 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1631 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1632 split_points
[reg
+ j
] = false;
1637 int new_virtual_grf
[reg_count
];
1638 int new_reg_offset
[reg_count
];
1641 for (int i
= 0; i
< num_vars
; i
++) {
1642 /* The first one should always be 0 as a quick sanity check. */
1643 assert(split_points
[reg
] == false);
1646 new_reg_offset
[reg
] = 0;
1651 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1652 /* If this is a split point, reset the offset to 0 and allocate a
1653 * new virtual GRF for the previous offset many registers
1655 if (split_points
[reg
]) {
1656 assert(offset
<= MAX_VGRF_SIZE
);
1657 int grf
= alloc
.allocate(offset
);
1658 for (int k
= reg
- offset
; k
< reg
; k
++)
1659 new_virtual_grf
[k
] = grf
;
1662 new_reg_offset
[reg
] = offset
;
1667 /* The last one gets the original register number */
1668 assert(offset
<= MAX_VGRF_SIZE
);
1669 alloc
.sizes
[i
] = offset
;
1670 for (int k
= reg
- offset
; k
< reg
; k
++)
1671 new_virtual_grf
[k
] = i
;
1673 assert(reg
== reg_count
);
1675 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1676 if (inst
->dst
.file
== GRF
) {
1677 reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1678 inst
->dst
.reg
= new_virtual_grf
[reg
];
1679 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1680 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1682 for (int i
= 0; i
< inst
->sources
; i
++) {
1683 if (inst
->src
[i
].file
== GRF
) {
1684 reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1685 inst
->src
[i
].reg
= new_virtual_grf
[reg
];
1686 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1687 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1691 invalidate_live_intervals();
1695 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1697 * During code generation, we create tons of temporary variables, many of
1698 * which get immediately killed and are never used again. Yet, in later
1699 * optimization and analysis passes, such as compute_live_intervals, we need
1700 * to loop over all the virtual GRFs. Compacting them can save a lot of
1704 fs_visitor::compact_virtual_grfs()
1706 bool progress
= false;
1707 int remap_table
[this->alloc
.count
];
1708 memset(remap_table
, -1, sizeof(remap_table
));
1710 /* Mark which virtual GRFs are used. */
1711 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1712 if (inst
->dst
.file
== GRF
)
1713 remap_table
[inst
->dst
.reg
] = 0;
1715 for (int i
= 0; i
< inst
->sources
; i
++) {
1716 if (inst
->src
[i
].file
== GRF
)
1717 remap_table
[inst
->src
[i
].reg
] = 0;
1721 /* Compact the GRF arrays. */
1723 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1724 if (remap_table
[i
] == -1) {
1725 /* We just found an unused register. This means that we are
1726 * actually going to compact something.
1730 remap_table
[i
] = new_index
;
1731 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1732 invalidate_live_intervals();
1737 this->alloc
.count
= new_index
;
1739 /* Patch all the instructions to use the newly renumbered registers */
1740 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1741 if (inst
->dst
.file
== GRF
)
1742 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
1744 for (int i
= 0; i
< inst
->sources
; i
++) {
1745 if (inst
->src
[i
].file
== GRF
)
1746 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
1750 /* Patch all the references to delta_xy, since they're used in register
1751 * allocation. If they're unused, switch them to BAD_FILE so we don't
1752 * think some random VGRF is delta_xy.
1754 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1755 if (delta_xy
[i
].file
== GRF
) {
1756 if (remap_table
[delta_xy
[i
].reg
] != -1) {
1757 delta_xy
[i
].reg
= remap_table
[delta_xy
[i
].reg
];
1759 delta_xy
[i
].file
= BAD_FILE
;
1768 * Assign UNIFORM file registers to either push constants or pull constants.
1770 * We allow a fragment shader to have more than the specified minimum
1771 * maximum number of fragment shader uniform components (64). If
1772 * there are too many of these, they'd fill up all of register space.
1773 * So, this will push some of them out to the pull constant buffer and
1774 * update the program to load them. We also use pull constants for all
1775 * indirect constant loads because we don't support indirect accesses in
1779 fs_visitor::assign_constant_locations()
1781 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1782 if (dispatch_width
!= 8)
1785 unsigned int num_pull_constants
= 0;
1787 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1788 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1790 bool is_live
[uniforms
];
1791 memset(is_live
, 0, sizeof(is_live
));
1793 /* First, we walk through the instructions and do two things:
1795 * 1) Figure out which uniforms are live.
1797 * 2) Find all indirect access of uniform arrays and flag them as needing
1798 * to go into the pull constant buffer.
1800 * Note that we don't move constant-indexed accesses to arrays. No
1801 * testing has been done of the performance impact of this choice.
1803 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1804 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1805 if (inst
->src
[i
].file
!= UNIFORM
)
1808 if (inst
->src
[i
].reladdr
) {
1809 int uniform
= inst
->src
[i
].reg
;
1811 /* If this array isn't already present in the pull constant buffer,
1814 if (pull_constant_loc
[uniform
] == -1) {
1815 assert(param_size
[uniform
]);
1816 for (int j
= 0; j
< param_size
[uniform
]; j
++)
1817 pull_constant_loc
[uniform
+ j
] = num_pull_constants
++;
1820 /* Mark the the one accessed uniform as live */
1821 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1822 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1823 is_live
[constant_nr
] = true;
1828 /* Only allow 16 registers (128 uniform components) as push constants.
1830 * Just demote the end of the list. We could probably do better
1831 * here, demoting things that are rarely used in the program first.
1833 * If changing this value, note the limitation about total_regs in
1836 unsigned int max_push_components
= 16 * 8;
1837 unsigned int num_push_constants
= 0;
1839 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1841 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1842 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1843 /* This UNIFORM register is either dead, or has already been demoted
1844 * to a pull const. Mark it as no longer living in the param[] array.
1846 push_constant_loc
[i
] = -1;
1850 if (num_push_constants
< max_push_components
) {
1851 /* Retain as a push constant. Record the location in the params[]
1854 push_constant_loc
[i
] = num_push_constants
++;
1856 /* Demote to a pull constant. */
1857 push_constant_loc
[i
] = -1;
1858 pull_constant_loc
[i
] = num_pull_constants
++;
1862 stage_prog_data
->nr_params
= num_push_constants
;
1863 stage_prog_data
->nr_pull_params
= num_pull_constants
;
1865 /* Up until now, the param[] array has been indexed by reg + reg_offset
1866 * of UNIFORM registers. Move pull constants into pull_param[] and
1867 * condense param[] to only contain the uniforms we chose to push.
1869 * NOTE: Because we are condensing the params[] array, we know that
1870 * push_constant_loc[i] <= i and we can do it in one smooth loop without
1871 * having to make a copy.
1873 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1874 const gl_constant_value
*value
= stage_prog_data
->param
[i
];
1876 if (pull_constant_loc
[i
] != -1) {
1877 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
1878 } else if (push_constant_loc
[i
] != -1) {
1879 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
1885 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
1886 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
1889 fs_visitor::demote_pull_constants()
1891 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1892 for (int i
= 0; i
< inst
->sources
; i
++) {
1893 if (inst
->src
[i
].file
!= UNIFORM
)
1897 unsigned location
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1898 if (location
>= uniforms
) /* Out of bounds access */
1901 pull_index
= pull_constant_loc
[location
];
1903 if (pull_index
== -1)
1906 /* Set up the annotation tracking for new generated instructions. */
1907 const fs_builder
ibld(this, block
, inst
);
1908 fs_reg
surf_index(stage_prog_data
->binding_table
.pull_constants_start
);
1909 fs_reg dst
= vgrf(glsl_type::float_type
);
1911 assert(inst
->src
[i
].stride
== 0);
1913 /* Generate a pull load into dst. */
1914 if (inst
->src
[i
].reladdr
) {
1915 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
1917 *inst
->src
[i
].reladdr
,
1919 inst
->src
[i
].reladdr
= NULL
;
1920 inst
->src
[i
].stride
= 1;
1922 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
1923 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
1924 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
1925 dst
, surf_index
, offset
);
1926 inst
->src
[i
].set_smear(pull_index
& 3);
1929 /* Rewrite the instruction to use the temporary VGRF. */
1930 inst
->src
[i
].file
= GRF
;
1931 inst
->src
[i
].reg
= dst
.reg
;
1932 inst
->src
[i
].reg_offset
= 0;
1935 invalidate_live_intervals();
1939 fs_visitor::opt_algebraic()
1941 bool progress
= false;
1943 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1944 switch (inst
->opcode
) {
1945 case BRW_OPCODE_MOV
:
1946 if (inst
->src
[0].file
!= IMM
)
1949 if (inst
->saturate
) {
1950 if (inst
->dst
.type
!= inst
->src
[0].type
)
1951 assert(!"unimplemented: saturate mixed types");
1953 if (brw_saturate_immediate(inst
->dst
.type
,
1954 &inst
->src
[0].fixed_hw_reg
)) {
1955 inst
->saturate
= false;
1961 case BRW_OPCODE_MUL
:
1962 if (inst
->src
[1].file
!= IMM
)
1966 if (inst
->src
[1].is_one()) {
1967 inst
->opcode
= BRW_OPCODE_MOV
;
1968 inst
->src
[1] = reg_undef
;
1974 if (inst
->src
[1].is_negative_one()) {
1975 inst
->opcode
= BRW_OPCODE_MOV
;
1976 inst
->src
[0].negate
= !inst
->src
[0].negate
;
1977 inst
->src
[1] = reg_undef
;
1983 if (inst
->src
[1].is_zero()) {
1984 inst
->opcode
= BRW_OPCODE_MOV
;
1985 inst
->src
[0] = inst
->src
[1];
1986 inst
->src
[1] = reg_undef
;
1991 if (inst
->src
[0].file
== IMM
) {
1992 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
1993 inst
->opcode
= BRW_OPCODE_MOV
;
1994 inst
->src
[0].fixed_hw_reg
.dw1
.f
*= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
1995 inst
->src
[1] = reg_undef
;
2000 case BRW_OPCODE_ADD
:
2001 if (inst
->src
[1].file
!= IMM
)
2005 if (inst
->src
[1].is_zero()) {
2006 inst
->opcode
= BRW_OPCODE_MOV
;
2007 inst
->src
[1] = reg_undef
;
2012 if (inst
->src
[0].file
== IMM
) {
2013 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2014 inst
->opcode
= BRW_OPCODE_MOV
;
2015 inst
->src
[0].fixed_hw_reg
.dw1
.f
+= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
2016 inst
->src
[1] = reg_undef
;
2022 if (inst
->src
[0].equals(inst
->src
[1])) {
2023 inst
->opcode
= BRW_OPCODE_MOV
;
2024 inst
->src
[1] = reg_undef
;
2029 case BRW_OPCODE_LRP
:
2030 if (inst
->src
[1].equals(inst
->src
[2])) {
2031 inst
->opcode
= BRW_OPCODE_MOV
;
2032 inst
->src
[0] = inst
->src
[1];
2033 inst
->src
[1] = reg_undef
;
2034 inst
->src
[2] = reg_undef
;
2039 case BRW_OPCODE_CMP
:
2040 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2042 inst
->src
[0].negate
&&
2043 inst
->src
[1].is_zero()) {
2044 inst
->src
[0].abs
= false;
2045 inst
->src
[0].negate
= false;
2046 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2051 case BRW_OPCODE_SEL
:
2052 if (inst
->src
[0].equals(inst
->src
[1])) {
2053 inst
->opcode
= BRW_OPCODE_MOV
;
2054 inst
->src
[1] = reg_undef
;
2055 inst
->predicate
= BRW_PREDICATE_NONE
;
2056 inst
->predicate_inverse
= false;
2058 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2059 switch (inst
->conditional_mod
) {
2060 case BRW_CONDITIONAL_LE
:
2061 case BRW_CONDITIONAL_L
:
2062 switch (inst
->src
[1].type
) {
2063 case BRW_REGISTER_TYPE_F
:
2064 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
>= 1.0f
) {
2065 inst
->opcode
= BRW_OPCODE_MOV
;
2066 inst
->src
[1] = reg_undef
;
2067 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2075 case BRW_CONDITIONAL_GE
:
2076 case BRW_CONDITIONAL_G
:
2077 switch (inst
->src
[1].type
) {
2078 case BRW_REGISTER_TYPE_F
:
2079 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
<= 0.0f
) {
2080 inst
->opcode
= BRW_OPCODE_MOV
;
2081 inst
->src
[1] = reg_undef
;
2082 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2094 case BRW_OPCODE_MAD
:
2095 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2096 inst
->opcode
= BRW_OPCODE_MOV
;
2097 inst
->src
[1] = reg_undef
;
2098 inst
->src
[2] = reg_undef
;
2100 } else if (inst
->src
[0].is_zero()) {
2101 inst
->opcode
= BRW_OPCODE_MUL
;
2102 inst
->src
[0] = inst
->src
[2];
2103 inst
->src
[2] = reg_undef
;
2105 } else if (inst
->src
[1].is_one()) {
2106 inst
->opcode
= BRW_OPCODE_ADD
;
2107 inst
->src
[1] = inst
->src
[2];
2108 inst
->src
[2] = reg_undef
;
2110 } else if (inst
->src
[2].is_one()) {
2111 inst
->opcode
= BRW_OPCODE_ADD
;
2112 inst
->src
[2] = reg_undef
;
2114 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2115 inst
->opcode
= BRW_OPCODE_ADD
;
2116 inst
->src
[1].fixed_hw_reg
.dw1
.f
*= inst
->src
[2].fixed_hw_reg
.dw1
.f
;
2117 inst
->src
[2] = reg_undef
;
2121 case SHADER_OPCODE_RCP
: {
2122 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2123 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2124 if (inst
->src
[0].equals(prev
->dst
)) {
2125 inst
->opcode
= SHADER_OPCODE_RSQ
;
2126 inst
->src
[0] = prev
->src
[0];
2132 case SHADER_OPCODE_BROADCAST
:
2133 if (is_uniform(inst
->src
[0])) {
2134 inst
->opcode
= BRW_OPCODE_MOV
;
2136 inst
->force_writemask_all
= true;
2138 } else if (inst
->src
[1].file
== IMM
) {
2139 inst
->opcode
= BRW_OPCODE_MOV
;
2140 inst
->src
[0] = component(inst
->src
[0],
2141 inst
->src
[1].fixed_hw_reg
.dw1
.ud
);
2143 inst
->force_writemask_all
= true;
2152 /* Swap if src[0] is immediate. */
2153 if (progress
&& inst
->is_commutative()) {
2154 if (inst
->src
[0].file
== IMM
) {
2155 fs_reg tmp
= inst
->src
[1];
2156 inst
->src
[1] = inst
->src
[0];
2165 * Optimize sample messages that have constant zero values for the trailing
2166 * texture coordinates. We can just reduce the message length for these
2167 * instructions instead of reserving a register for it. Trailing parameters
2168 * that aren't sent default to zero anyway. This will cause the dead code
2169 * eliminator to remove the MOV instruction that would otherwise be emitted to
2170 * set up the zero value.
2173 fs_visitor::opt_zero_samples()
2175 /* Gen4 infers the texturing opcode based on the message length so we can't
2178 if (devinfo
->gen
< 5)
2181 bool progress
= false;
2183 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2184 if (!inst
->is_tex())
2187 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2189 if (load_payload
->is_head_sentinel() ||
2190 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2193 /* We don't want to remove the message header or the first parameter.
2194 * Removing the first parameter is not allowed, see the Haswell PRM
2195 * volume 7, page 149:
2197 * "Parameter 0 is required except for the sampleinfo message, which
2198 * has no parameter 0"
2200 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2201 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2202 (inst
->exec_size
/ 8) +
2203 inst
->header_size
- 1].is_zero()) {
2204 inst
->mlen
-= inst
->exec_size
/ 8;
2210 invalidate_live_intervals();
2216 * Optimize sample messages which are followed by the final RT write.
2218 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2219 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2220 * final texturing results copied to the framebuffer write payload and modify
2221 * them to write to the framebuffer directly.
2224 fs_visitor::opt_sampler_eot()
2226 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2228 if (stage
!= MESA_SHADER_FRAGMENT
)
2231 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2234 /* FINISHME: It should be possible to implement this optimization when there
2235 * are multiple drawbuffers.
2237 if (key
->nr_color_regions
!= 1)
2240 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2241 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2242 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2243 assert(fb_write
->eot
);
2244 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2246 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2248 /* There wasn't one; nothing to do. */
2249 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2252 /* 3D Sampler » Messages » Message Format
2254 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2255 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2257 if (tex_inst
->opcode
== SHADER_OPCODE_TXS
||
2258 tex_inst
->opcode
== SHADER_OPCODE_SAMPLEINFO
||
2259 tex_inst
->opcode
== SHADER_OPCODE_LOD
||
2260 tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2261 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2264 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2265 * It's very likely to be the previous instruction.
2267 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2268 if (load_payload
->is_head_sentinel() ||
2269 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2272 assert(!tex_inst
->eot
); /* We can't get here twice */
2273 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2275 const fs_builder
ibld(this, block
, tex_inst
);
2277 tex_inst
->offset
|= fb_write
->target
<< 24;
2278 tex_inst
->eot
= true;
2279 tex_inst
->dst
= ibld
.null_reg_ud();
2280 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2282 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2283 * to create a new LOAD_PAYLOAD command with the same sources and a space
2284 * saved for the header. Using a new destination register not only makes sure
2285 * we have enough space, but it will make sure the dead code eliminator kills
2286 * the instruction that this will replace.
2288 if (tex_inst
->header_size
!= 0)
2291 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2292 load_payload
->sources
+ 1);
2293 fs_reg
*new_sources
=
2294 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2296 new_sources
[0] = fs_reg();
2297 for (int i
= 0; i
< load_payload
->sources
; i
++)
2298 new_sources
[i
+1] = load_payload
->src
[i
];
2300 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2301 * requires a lot of information about the sources to appropriately figure
2302 * out the number of registers needed to be used. Given this stage in our
2303 * optimization, we may not have the appropriate GRFs required by
2304 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2305 * manually emit the instruction.
2307 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2308 load_payload
->exec_size
,
2311 load_payload
->sources
+ 1);
2313 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2314 new_load_payload
->header_size
= 1;
2316 tex_inst
->header_size
= 1;
2317 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2318 tex_inst
->src
[0] = send_header
;
2324 fs_visitor::opt_register_renaming()
2326 bool progress
= false;
2329 int remap
[alloc
.count
];
2330 memset(remap
, -1, sizeof(int) * alloc
.count
);
2332 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2333 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2335 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2336 inst
->opcode
== BRW_OPCODE_WHILE
) {
2340 /* Rewrite instruction sources. */
2341 for (int i
= 0; i
< inst
->sources
; i
++) {
2342 if (inst
->src
[i
].file
== GRF
&&
2343 remap
[inst
->src
[i
].reg
] != -1 &&
2344 remap
[inst
->src
[i
].reg
] != inst
->src
[i
].reg
) {
2345 inst
->src
[i
].reg
= remap
[inst
->src
[i
].reg
];
2350 const int dst
= inst
->dst
.reg
;
2353 inst
->dst
.file
== GRF
&&
2354 alloc
.sizes
[inst
->dst
.reg
] == inst
->exec_size
/ 8 &&
2355 !inst
->is_partial_write()) {
2356 if (remap
[dst
] == -1) {
2359 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2360 inst
->dst
.reg
= remap
[dst
];
2363 } else if (inst
->dst
.file
== GRF
&&
2365 remap
[dst
] != dst
) {
2366 inst
->dst
.reg
= remap
[dst
];
2372 invalidate_live_intervals();
2374 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2375 if (delta_xy
[i
].file
== GRF
&& remap
[delta_xy
[i
].reg
] != -1) {
2376 delta_xy
[i
].reg
= remap
[delta_xy
[i
].reg
];
2385 * Remove redundant or useless discard jumps.
2387 * For example, we can eliminate jumps in the following sequence:
2389 * discard-jump (redundant with the next jump)
2390 * discard-jump (useless; jumps to the next instruction)
2394 fs_visitor::opt_redundant_discard_jumps()
2396 bool progress
= false;
2398 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2400 fs_inst
*placeholder_halt
= NULL
;
2401 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2402 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2403 placeholder_halt
= inst
;
2408 if (!placeholder_halt
)
2411 /* Delete any HALTs immediately before the placeholder halt. */
2412 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2413 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2414 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2415 prev
->remove(last_bblock
);
2420 invalidate_live_intervals();
2426 fs_visitor::compute_to_mrf()
2428 bool progress
= false;
2431 /* No MRFs on Gen >= 7. */
2432 if (devinfo
->gen
>= 7)
2435 calculate_live_intervals();
2437 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2441 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2442 inst
->is_partial_write() ||
2443 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2444 inst
->dst
.type
!= inst
->src
[0].type
||
2445 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2446 !inst
->src
[0].is_contiguous() ||
2447 inst
->src
[0].subreg_offset
)
2450 /* Work out which hardware MRF registers are written by this
2453 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2455 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2456 mrf_high
= mrf_low
+ 4;
2457 } else if (inst
->exec_size
== 16) {
2458 mrf_high
= mrf_low
+ 1;
2463 /* Can't compute-to-MRF this GRF if someone else was going to
2466 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2469 /* Found a move of a GRF to a MRF. Let's see if we can go
2470 * rewrite the thing that made this GRF to write into the MRF.
2472 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2473 if (scan_inst
->dst
.file
== GRF
&&
2474 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2475 /* Found the last thing to write our reg we want to turn
2476 * into a compute-to-MRF.
2479 /* If this one instruction didn't populate all the
2480 * channels, bail. We might be able to rewrite everything
2481 * that writes that reg, but it would require smarter
2482 * tracking to delay the rewriting until complete success.
2484 if (scan_inst
->is_partial_write())
2487 /* Things returning more than one register would need us to
2488 * understand coalescing out more than one MOV at a time.
2490 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2493 /* SEND instructions can't have MRF as a destination. */
2494 if (scan_inst
->mlen
)
2497 if (devinfo
->gen
== 6) {
2498 /* gen6 math instructions must have the destination be
2499 * GRF, so no compute-to-MRF for them.
2501 if (scan_inst
->is_math()) {
2506 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2507 /* Found the creator of our MRF's source value. */
2508 scan_inst
->dst
.file
= MRF
;
2509 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2510 scan_inst
->saturate
|= inst
->saturate
;
2511 inst
->remove(block
);
2517 /* We don't handle control flow here. Most computation of
2518 * values that end up in MRFs are shortly before the MRF
2521 if (block
->start() == scan_inst
)
2524 /* You can't read from an MRF, so if someone else reads our
2525 * MRF's source GRF that we wanted to rewrite, that stops us.
2527 bool interfered
= false;
2528 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2529 if (scan_inst
->src
[i
].file
== GRF
&&
2530 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2531 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2538 if (scan_inst
->dst
.file
== MRF
) {
2539 /* If somebody else writes our MRF here, we can't
2540 * compute-to-MRF before that.
2542 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2545 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2546 scan_mrf_high
= scan_mrf_low
+ 4;
2547 } else if (scan_inst
->exec_size
== 16) {
2548 scan_mrf_high
= scan_mrf_low
+ 1;
2550 scan_mrf_high
= scan_mrf_low
;
2553 if (mrf_low
== scan_mrf_low
||
2554 mrf_low
== scan_mrf_high
||
2555 mrf_high
== scan_mrf_low
||
2556 mrf_high
== scan_mrf_high
) {
2561 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2562 /* Found a SEND instruction, which means that there are
2563 * live values in MRFs from base_mrf to base_mrf +
2564 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2567 if (mrf_low
>= scan_inst
->base_mrf
&&
2568 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2571 if (mrf_high
>= scan_inst
->base_mrf
&&
2572 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2580 invalidate_live_intervals();
2586 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2587 * flow. We could probably do better here with some form of divergence
2591 fs_visitor::eliminate_find_live_channel()
2593 bool progress
= false;
2596 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2597 switch (inst
->opcode
) {
2603 case BRW_OPCODE_ENDIF
:
2604 case BRW_OPCODE_WHILE
:
2608 case FS_OPCODE_DISCARD_JUMP
:
2609 /* This can potentially make control flow non-uniform until the end
2614 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2616 inst
->opcode
= BRW_OPCODE_MOV
;
2617 inst
->src
[0] = fs_reg(0u);
2619 inst
->force_writemask_all
= true;
2633 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2634 * instructions to FS_OPCODE_REP_FB_WRITE.
2637 fs_visitor::emit_repclear_shader()
2639 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2641 int color_mrf
= base_mrf
+ 2;
2643 fs_inst
*mov
= bld
.exec_all().MOV(vec4(brw_message_reg(color_mrf
)),
2644 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2647 if (key
->nr_color_regions
== 1) {
2648 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2649 write
->saturate
= key
->clamp_fragment_color
;
2650 write
->base_mrf
= color_mrf
;
2652 write
->header_size
= 0;
2655 assume(key
->nr_color_regions
> 0);
2656 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2657 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2658 write
->saturate
= key
->clamp_fragment_color
;
2659 write
->base_mrf
= base_mrf
;
2661 write
->header_size
= 2;
2669 assign_constant_locations();
2670 assign_curb_setup();
2672 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2673 assert(mov
->src
[0].file
== HW_REG
);
2674 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].fixed_hw_reg
.nr
, 0);
2678 * Walks through basic blocks, looking for repeated MRF writes and
2679 * removing the later ones.
2682 fs_visitor::remove_duplicate_mrf_writes()
2684 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2685 bool progress
= false;
2687 /* Need to update the MRF tracking for compressed instructions. */
2688 if (dispatch_width
== 16)
2691 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2693 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2694 if (inst
->is_control_flow()) {
2695 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2698 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2699 inst
->dst
.file
== MRF
) {
2700 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2701 if (prev_inst
&& inst
->equals(prev_inst
)) {
2702 inst
->remove(block
);
2708 /* Clear out the last-write records for MRFs that were overwritten. */
2709 if (inst
->dst
.file
== MRF
) {
2710 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2713 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2714 /* Found a SEND instruction, which will include two or fewer
2715 * implied MRF writes. We could do better here.
2717 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2718 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2722 /* Clear out any MRF move records whose sources got overwritten. */
2723 if (inst
->dst
.file
== GRF
) {
2724 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2725 if (last_mrf_move
[i
] &&
2726 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2727 last_mrf_move
[i
] = NULL
;
2732 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2733 inst
->dst
.file
== MRF
&&
2734 inst
->src
[0].file
== GRF
&&
2735 !inst
->is_partial_write()) {
2736 last_mrf_move
[inst
->dst
.reg
] = inst
;
2741 invalidate_live_intervals();
2747 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2749 /* Clear the flag for registers that actually got read (as expected). */
2750 for (int i
= 0; i
< inst
->sources
; i
++) {
2752 if (inst
->src
[i
].file
== GRF
) {
2753 grf
= inst
->src
[i
].reg
;
2754 } else if (inst
->src
[i
].file
== HW_REG
&&
2755 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
2756 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
2761 if (grf
>= first_grf
&&
2762 grf
< first_grf
+ grf_len
) {
2763 deps
[grf
- first_grf
] = false;
2764 if (inst
->exec_size
== 16)
2765 deps
[grf
- first_grf
+ 1] = false;
2771 * Implements this workaround for the original 965:
2773 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2774 * check for post destination dependencies on this instruction, software
2775 * must ensure that there is no destination hazard for the case of ‘write
2776 * followed by a posted write’ shown in the following example.
2779 * 2. send r3.xy <rest of send instruction>
2782 * Due to no post-destination dependency check on the ‘send’, the above
2783 * code sequence could have two instructions (1 and 2) in flight at the
2784 * same time that both consider ‘r3’ as the target of their final writes.
2787 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2790 int write_len
= inst
->regs_written
;
2791 int first_write_grf
= inst
->dst
.reg
;
2792 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2793 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2795 memset(needs_dep
, false, sizeof(needs_dep
));
2796 memset(needs_dep
, true, write_len
);
2798 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2800 /* Walk backwards looking for writes to registers we're writing which
2801 * aren't read since being written. If we hit the start of the program,
2802 * we assume that there are no outstanding dependencies on entry to the
2805 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2806 /* If we hit control flow, assume that there *are* outstanding
2807 * dependencies, and force their cleanup before our instruction.
2809 if (block
->start() == scan_inst
) {
2810 for (int i
= 0; i
< write_len
; i
++) {
2812 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
2813 first_write_grf
+ i
);
2818 /* We insert our reads as late as possible on the assumption that any
2819 * instruction but a MOV that might have left us an outstanding
2820 * dependency has more latency than a MOV.
2822 if (scan_inst
->dst
.file
== GRF
) {
2823 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2824 int reg
= scan_inst
->dst
.reg
+ i
;
2826 if (reg
>= first_write_grf
&&
2827 reg
< first_write_grf
+ write_len
&&
2828 needs_dep
[reg
- first_write_grf
]) {
2829 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
2830 needs_dep
[reg
- first_write_grf
] = false;
2831 if (scan_inst
->exec_size
== 16)
2832 needs_dep
[reg
- first_write_grf
+ 1] = false;
2837 /* Clear the flag for registers that actually got read (as expected). */
2838 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2840 /* Continue the loop only if we haven't resolved all the dependencies */
2842 for (i
= 0; i
< write_len
; i
++) {
2852 * Implements this workaround for the original 965:
2854 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2855 * used as a destination register until after it has been sourced by an
2856 * instruction with a different destination register.
2859 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
2861 int write_len
= inst
->regs_written
;
2862 int first_write_grf
= inst
->dst
.reg
;
2863 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2864 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2866 memset(needs_dep
, false, sizeof(needs_dep
));
2867 memset(needs_dep
, true, write_len
);
2868 /* Walk forwards looking for writes to registers we're writing which aren't
2869 * read before being written.
2871 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
2872 /* If we hit control flow, force resolve all remaining dependencies. */
2873 if (block
->end() == scan_inst
) {
2874 for (int i
= 0; i
< write_len
; i
++) {
2876 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
2877 first_write_grf
+ i
);
2882 /* Clear the flag for registers that actually got read (as expected). */
2883 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2885 /* We insert our reads as late as possible since they're reading the
2886 * result of a SEND, which has massive latency.
2888 if (scan_inst
->dst
.file
== GRF
&&
2889 scan_inst
->dst
.reg
>= first_write_grf
&&
2890 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
2891 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
2892 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
2893 scan_inst
->dst
.reg
);
2894 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
2897 /* Continue the loop only if we haven't resolved all the dependencies */
2899 for (i
= 0; i
< write_len
; i
++) {
2909 fs_visitor::insert_gen4_send_dependency_workarounds()
2911 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
2914 bool progress
= false;
2916 /* Note that we're done with register allocation, so GRF fs_regs always
2917 * have a .reg_offset of 0.
2920 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2921 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
2922 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
2923 insert_gen4_post_send_dependency_workarounds(block
, inst
);
2929 invalidate_live_intervals();
2933 * Turns the generic expression-style uniform pull constant load instruction
2934 * into a hardware-specific series of instructions for loading a pull
2937 * The expression style allows the CSE pass before this to optimize out
2938 * repeated loads from the same offset, and gives the pre-register-allocation
2939 * scheduling full flexibility, while the conversion to native instructions
2940 * allows the post-register-allocation scheduler the best information
2943 * Note that execution masking for setting up pull constant loads is special:
2944 * the channels that need to be written are unrelated to the current execution
2945 * mask, since a later instruction will use one of the result channels as a
2946 * source operand for all 8 or 16 of its channels.
2949 fs_visitor::lower_uniform_pull_constant_loads()
2951 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2952 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
2955 if (devinfo
->gen
>= 7) {
2956 /* The offset arg before was a vec4-aligned byte offset. We need to
2957 * turn it into a dword offset.
2959 fs_reg const_offset_reg
= inst
->src
[1];
2960 assert(const_offset_reg
.file
== IMM
&&
2961 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
2962 const_offset_reg
.fixed_hw_reg
.dw1
.ud
/= 4;
2964 fs_reg payload
, offset
;
2965 if (devinfo
->gen
>= 9) {
2966 /* We have to use a message header on Skylake to get SIMD4x2
2967 * mode. Reserve space for the register.
2969 offset
= payload
= fs_reg(GRF
, alloc
.allocate(2));
2970 offset
.reg_offset
++;
2973 offset
= payload
= fs_reg(GRF
, alloc
.allocate(1));
2977 /* This is actually going to be a MOV, but since only the first dword
2978 * is accessed, we have a special opcode to do just that one. Note
2979 * that this needs to be an operation that will be considered a def
2980 * by live variable analysis, or register allocation will explode.
2982 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
2983 8, offset
, const_offset_reg
);
2984 setup
->force_writemask_all
= true;
2986 setup
->ir
= inst
->ir
;
2987 setup
->annotation
= inst
->annotation
;
2988 inst
->insert_before(block
, setup
);
2990 /* Similarly, this will only populate the first 4 channels of the
2991 * result register (since we only use smear values from 0-3), but we
2992 * don't tell the optimizer.
2994 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
2995 inst
->src
[1] = payload
;
2996 inst
->base_mrf
= -1;
2998 invalidate_live_intervals();
3000 /* Before register allocation, we didn't tell the scheduler about the
3001 * MRF we use. We know it's safe to use this MRF because nothing
3002 * else does except for register spill/unspill, which generates and
3003 * uses its MRF within a single IR instruction.
3005 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3012 fs_visitor::lower_load_payload()
3014 bool progress
= false;
3016 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3017 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3020 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== GRF
);
3021 assert(inst
->saturate
== false);
3022 fs_reg dst
= inst
->dst
;
3024 /* Get rid of COMPR4. We'll add it back in if we need it */
3025 if (dst
.file
== MRF
)
3026 dst
.reg
= dst
.reg
& ~BRW_MRF_COMPR4
;
3028 const fs_builder
ibld(this, block
, inst
);
3029 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3031 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3032 if (inst
->src
[i
].file
!= BAD_FILE
) {
3033 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3034 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3035 hbld
.MOV(mov_dst
, mov_src
);
3037 dst
= offset(dst
, hbld
, 1);
3040 if (inst
->dst
.file
== MRF
&& (inst
->dst
.reg
& BRW_MRF_COMPR4
) &&
3041 inst
->exec_size
> 8) {
3042 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3043 * a straightforward copy. Instead, the result of the
3044 * LOAD_PAYLOAD is treated as interleaved and the first four
3045 * non-header sources are unpacked as:
3056 * This is used for gen <= 5 fb writes.
3058 assert(inst
->exec_size
== 16);
3059 assert(inst
->header_size
+ 4 <= inst
->sources
);
3060 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3061 if (inst
->src
[i
].file
!= BAD_FILE
) {
3062 if (devinfo
->has_compr4
) {
3063 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3064 compr4_dst
.reg
|= BRW_MRF_COMPR4
;
3065 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3067 /* Platform doesn't have COMPR4. We have to fake it */
3068 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3069 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3071 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3078 /* The loop above only ever incremented us through the first set
3079 * of 4 registers. However, thanks to the magic of COMPR4, we
3080 * actually wrote to the first 8 registers, so we need to take
3081 * that into account now.
3085 /* The COMPR4 code took care of the first 4 sources. We'll let
3086 * the regular path handle any remaining sources. Yes, we are
3087 * modifying the instruction but we're about to delete it so
3088 * this really doesn't hurt anything.
3090 inst
->header_size
+= 4;
3093 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3094 if (inst
->src
[i
].file
!= BAD_FILE
)
3095 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3096 dst
= offset(dst
, ibld
, 1);
3099 inst
->remove(block
);
3104 invalidate_live_intervals();
3110 fs_visitor::lower_integer_multiplication()
3112 bool progress
= false;
3114 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3115 const fs_builder
ibld(this, block
, inst
);
3117 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3118 if (inst
->dst
.is_accumulator() ||
3119 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3120 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3123 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3124 * operation directly, but CHV/BXT cannot.
3126 if (devinfo
->gen
>= 8 &&
3127 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3130 if (inst
->src
[1].file
== IMM
&&
3131 inst
->src
[1].fixed_hw_reg
.dw1
.ud
< (1 << 16)) {
3132 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3133 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3136 * If multiplying by an immediate value that fits in 16-bits, do a
3137 * single MUL instruction with that value in the proper location.
3139 if (devinfo
->gen
< 7) {
3140 fs_reg
imm(GRF
, alloc
.allocate(dispatch_width
/ 8),
3142 ibld
.MOV(imm
, inst
->src
[1]);
3143 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3145 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3148 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3149 * do 32-bit integer multiplication in one instruction, but instead
3150 * must do a sequence (which actually calculates a 64-bit result):
3152 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3153 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3154 * mov(8) g2<1>D acc0<8,8,1>D
3156 * But on Gen > 6, the ability to use second accumulator register
3157 * (acc1) for non-float data types was removed, preventing a simple
3158 * implementation in SIMD16. A 16-channel result can be calculated by
3159 * executing the three instructions twice in SIMD8, once with quarter
3160 * control of 1Q for the first eight channels and again with 2Q for
3161 * the second eight channels.
3163 * Which accumulator register is implicitly accessed (by AccWrEnable
3164 * for instance) is determined by the quarter control. Unfortunately
3165 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3166 * implicit accumulator access by an instruction with 2Q will access
3167 * acc1 regardless of whether the data type is usable in acc1.
3169 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3170 * integer data types.
3172 * Since we only want the low 32-bits of the result, we can do two
3173 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3174 * adjust the high result and add them (like the mach is doing):
3176 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3177 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3178 * shl(8) g9<1>D g8<8,8,1>D 16D
3179 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3181 * We avoid the shl instruction by realizing that we only want to add
3182 * the low 16-bits of the "high" result to the high 16-bits of the
3183 * "low" result and using proper regioning on the add:
3185 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3186 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3187 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3189 * Since it does not use the (single) accumulator register, we can
3190 * schedule multi-component multiplications much better.
3193 fs_reg orig_dst
= inst
->dst
;
3194 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3195 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
3198 fs_reg low
= inst
->dst
;
3199 fs_reg
high(GRF
, alloc
.allocate(dispatch_width
/ 8),
3202 if (devinfo
->gen
>= 7) {
3203 fs_reg src1_0_w
= inst
->src
[1];
3204 fs_reg src1_1_w
= inst
->src
[1];
3206 if (inst
->src
[1].file
== IMM
) {
3207 src1_0_w
.fixed_hw_reg
.dw1
.ud
&= 0xffff;
3208 src1_1_w
.fixed_hw_reg
.dw1
.ud
>>= 16;
3210 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3211 if (src1_0_w
.stride
!= 0) {
3212 assert(src1_0_w
.stride
== 1);
3213 src1_0_w
.stride
= 2;
3216 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3217 if (src1_1_w
.stride
!= 0) {
3218 assert(src1_1_w
.stride
== 1);
3219 src1_1_w
.stride
= 2;
3221 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3223 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3224 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3226 fs_reg src0_0_w
= inst
->src
[0];
3227 fs_reg src0_1_w
= inst
->src
[0];
3229 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3230 if (src0_0_w
.stride
!= 0) {
3231 assert(src0_0_w
.stride
== 1);
3232 src0_0_w
.stride
= 2;
3235 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3236 if (src0_1_w
.stride
!= 0) {
3237 assert(src0_1_w
.stride
== 1);
3238 src0_1_w
.stride
= 2;
3240 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3242 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3243 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3246 fs_reg dst
= inst
->dst
;
3247 dst
.type
= BRW_REGISTER_TYPE_UW
;
3248 dst
.subreg_offset
= 2;
3251 high
.type
= BRW_REGISTER_TYPE_UW
;
3254 low
.type
= BRW_REGISTER_TYPE_UW
;
3255 low
.subreg_offset
= 2;
3258 ibld
.ADD(dst
, low
, high
);
3260 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3261 set_condmod(inst
->conditional_mod
,
3262 ibld
.MOV(orig_dst
, inst
->dst
));
3266 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3267 /* Should have been lowered to 8-wide. */
3268 assert(inst
->exec_size
<= 8);
3269 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3271 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3272 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3274 if (devinfo
->gen
>= 8) {
3275 /* Until Gen8, integer multiplies read 32-bits from one source,
3276 * and 16-bits from the other, and relying on the MACH instruction
3277 * to generate the high bits of the result.
3279 * On Gen8, the multiply instruction does a full 32x32-bit
3280 * multiply, but in order to do a 64-bit multiply we can simulate
3281 * the previous behavior and then use a MACH instruction.
3283 * FINISHME: Don't use source modifiers on src1.
3285 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3286 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3287 mul
->src
[1].type
= (type_is_signed(mul
->src
[1].type
) ?
3288 BRW_REGISTER_TYPE_W
: BRW_REGISTER_TYPE_UW
);
3289 mul
->src
[1].stride
*= 2;
3291 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3292 inst
->force_sechalf
) {
3293 /* Among other things the quarter control bits influence which
3294 * accumulator register is used by the hardware for instructions
3295 * that access the accumulator implicitly (e.g. MACH). A
3296 * second-half instruction would normally map to acc1, which
3297 * doesn't exist on Gen7 and up (the hardware does emulate it for
3298 * floating-point instructions *only* by taking advantage of the
3299 * extra precision of acc0 not normally used for floating point
3302 * HSW and up are careful enough not to try to access an
3303 * accumulator register that doesn't exist, but on earlier Gen7
3304 * hardware we need to make sure that the quarter control bits are
3305 * zero to avoid non-deterministic behaviour and emit an extra MOV
3306 * to get the result masked correctly according to the current
3309 mach
->force_sechalf
= false;
3310 mach
->force_writemask_all
= true;
3311 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3312 ibld
.MOV(inst
->dst
, mach
->dst
);
3318 inst
->remove(block
);
3323 invalidate_live_intervals();
3329 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3330 fs_reg
*dst
, fs_reg color
, unsigned components
)
3332 if (key
->clamp_fragment_color
) {
3333 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3334 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3336 for (unsigned i
= 0; i
< components
; i
++)
3338 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3343 for (unsigned i
= 0; i
< components
; i
++)
3344 dst
[i
] = offset(color
, bld
, i
);
3348 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3349 const brw_wm_prog_data
*prog_data
,
3350 const brw_wm_prog_key
*key
,
3351 const fs_visitor::thread_payload
&payload
)
3353 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3354 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3355 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3356 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3357 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3358 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3359 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3360 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3361 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3362 const unsigned components
=
3363 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].fixed_hw_reg
.dw1
.ud
;
3365 /* We can potentially have a message length of up to 15, so we have to set
3366 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3369 int header_size
= 2, payload_header_size
;
3370 unsigned length
= 0;
3372 /* From the Sandy Bridge PRM, volume 4, page 198:
3374 * "Dispatched Pixel Enables. One bit per pixel indicating
3375 * which pixels were originally enabled when the thread was
3376 * dispatched. This field is only required for the end-of-
3377 * thread message and on all dual-source messages."
3379 if (devinfo
->gen
>= 6 &&
3380 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3381 color1
.file
== BAD_FILE
&&
3382 key
->nr_color_regions
== 1) {
3386 if (header_size
!= 0) {
3387 assert(header_size
== 2);
3388 /* Allocate 2 registers for a header */
3392 if (payload
.aa_dest_stencil_reg
) {
3393 sources
[length
] = fs_reg(GRF
, bld
.shader
->alloc
.allocate(1));
3394 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3395 .MOV(sources
[length
],
3396 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3400 if (prog_data
->uses_omask
) {
3401 sources
[length
] = fs_reg(GRF
, bld
.shader
->alloc
.allocate(1),
3402 BRW_REGISTER_TYPE_UD
);
3404 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3405 * relevant. Since it's unsigned single words one vgrf is always
3406 * 16-wide, but only the lower or higher 8 channels will be used by the
3407 * hardware when doing a SIMD8 write depending on whether we have
3408 * selected the subspans for the first or second half respectively.
3410 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3411 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3412 sample_mask
.stride
*= 2;
3414 bld
.exec_all().annotate("FB write oMask")
3415 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3416 inst
->force_sechalf
),
3421 payload_header_size
= length
;
3423 if (src0_alpha
.file
!= BAD_FILE
) {
3424 /* FIXME: This is being passed at the wrong location in the payload and
3425 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3426 * It's supposed to be immediately before oMask but there seems to be no
3427 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3428 * requires header sources to form a contiguous segment at the beginning
3429 * of the message and src0_alpha has per-channel semantics.
3431 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3435 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3438 if (color1
.file
!= BAD_FILE
) {
3439 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3443 if (src_depth
.file
!= BAD_FILE
) {
3444 sources
[length
] = src_depth
;
3448 if (dst_depth
.file
!= BAD_FILE
) {
3449 sources
[length
] = dst_depth
;
3453 if (src_stencil
.file
!= BAD_FILE
) {
3454 assert(devinfo
->gen
>= 9);
3455 assert(bld
.dispatch_width() != 16);
3457 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3458 bld
.exec_all().annotate("FB write OS")
3459 .emit(FS_OPCODE_PACK_STENCIL_REF
, sources
[length
],
3460 retype(src_stencil
, BRW_REGISTER_TYPE_UB
));
3465 if (devinfo
->gen
>= 7) {
3466 /* Send from the GRF */
3467 fs_reg payload
= fs_reg(GRF
, -1, BRW_REGISTER_TYPE_F
);
3468 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3469 payload
.reg
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3470 load
->dst
= payload
;
3472 inst
->src
[0] = payload
;
3473 inst
->resize_sources(1);
3474 inst
->base_mrf
= -1;
3476 /* Send from the MRF */
3477 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3478 sources
, length
, payload_header_size
);
3480 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3481 * will do this for us if we just give it a COMPR4 destination.
3483 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3484 load
->dst
.reg
|= BRW_MRF_COMPR4
;
3486 inst
->resize_sources(0);
3490 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3491 inst
->mlen
= load
->regs_written
;
3492 inst
->header_size
= header_size
;
3496 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3497 const fs_reg
&coordinate
,
3498 const fs_reg
&shadow_c
,
3499 const fs_reg
&lod
, const fs_reg
&lod2
,
3500 const fs_reg
&sampler
,
3501 unsigned coord_components
,
3502 unsigned grad_components
)
3504 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3505 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3506 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3507 fs_reg msg_end
= msg_begin
;
3510 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3512 for (unsigned i
= 0; i
< coord_components
; i
++)
3513 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3514 offset(coordinate
, bld
, i
));
3516 msg_end
= offset(msg_end
, bld
, coord_components
);
3518 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3519 * require all three components to be present and zero if they are unused.
3521 if (coord_components
> 0 &&
3522 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3523 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3524 for (unsigned i
= coord_components
; i
< 3; i
++)
3525 bld
.MOV(offset(msg_end
, bld
, i
), fs_reg(0.0f
));
3527 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3530 if (op
== SHADER_OPCODE_TXD
) {
3531 /* TXD unsupported in SIMD16 mode. */
3532 assert(bld
.dispatch_width() == 8);
3534 /* the slots for u and v are always present, but r is optional */
3535 if (coord_components
< 2)
3536 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3539 * dPdx = dudx, dvdx, drdx
3540 * dPdy = dudy, dvdy, drdy
3542 * 1-arg: Does not exist.
3544 * 2-arg: dudx dvdx dudy dvdy
3545 * dPdx.x dPdx.y dPdy.x dPdy.y
3548 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3549 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3550 * m5 m6 m7 m8 m9 m10
3552 for (unsigned i
= 0; i
< grad_components
; i
++)
3553 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3555 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3557 for (unsigned i
= 0; i
< grad_components
; i
++)
3558 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3560 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3564 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3565 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3567 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3568 bld
.dispatch_width() == 16);
3570 const brw_reg_type type
=
3571 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3572 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3573 bld
.MOV(retype(msg_end
, type
), lod
);
3574 msg_end
= offset(msg_end
, bld
, 1);
3577 if (shadow_c
.file
!= BAD_FILE
) {
3578 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3579 /* There's no plain shadow compare message, so we use shadow
3580 * compare with a bias of 0.0.
3582 bld
.MOV(msg_end
, fs_reg(0.0f
));
3583 msg_end
= offset(msg_end
, bld
, 1);
3586 bld
.MOV(msg_end
, shadow_c
);
3587 msg_end
= offset(msg_end
, bld
, 1);
3591 inst
->src
[0] = reg_undef
;
3592 inst
->src
[1] = sampler
;
3593 inst
->resize_sources(2);
3594 inst
->base_mrf
= msg_begin
.reg
;
3595 inst
->mlen
= msg_end
.reg
- msg_begin
.reg
;
3596 inst
->header_size
= 1;
3600 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3602 const fs_reg
&shadow_c
,
3603 fs_reg lod
, fs_reg lod2
,
3604 const fs_reg
&sample_index
,
3605 const fs_reg
&sampler
,
3606 const fs_reg
&offset_value
,
3607 unsigned coord_components
,
3608 unsigned grad_components
)
3610 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3611 fs_reg msg_coords
= message
;
3612 unsigned header_size
= 0;
3614 if (offset_value
.file
!= BAD_FILE
) {
3615 /* The offsets set up by the visitor are in the m1 header, so we can't
3622 for (unsigned i
= 0; i
< coord_components
; i
++) {
3623 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3624 coordinate
= offset(coordinate
, bld
, 1);
3626 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3627 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3629 if (shadow_c
.file
!= BAD_FILE
) {
3630 fs_reg msg_shadow
= msg_lod
;
3631 bld
.MOV(msg_shadow
, shadow_c
);
3632 msg_lod
= offset(msg_shadow
, bld
, 1);
3637 case SHADER_OPCODE_TXL
:
3639 bld
.MOV(msg_lod
, lod
);
3640 msg_end
= offset(msg_lod
, bld
, 1);
3642 case SHADER_OPCODE_TXD
:
3645 * dPdx = dudx, dvdx, drdx
3646 * dPdy = dudy, dvdy, drdy
3648 * Load up these values:
3649 * - dudx dudy dvdx dvdy drdx drdy
3650 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3653 for (unsigned i
= 0; i
< grad_components
; i
++) {
3654 bld
.MOV(msg_end
, lod
);
3655 lod
= offset(lod
, bld
, 1);
3656 msg_end
= offset(msg_end
, bld
, 1);
3658 bld
.MOV(msg_end
, lod2
);
3659 lod2
= offset(lod2
, bld
, 1);
3660 msg_end
= offset(msg_end
, bld
, 1);
3663 case SHADER_OPCODE_TXS
:
3664 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3665 bld
.MOV(msg_lod
, lod
);
3666 msg_end
= offset(msg_lod
, bld
, 1);
3668 case SHADER_OPCODE_TXF
:
3669 msg_lod
= offset(msg_coords
, bld
, 3);
3670 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3671 msg_end
= offset(msg_lod
, bld
, 1);
3673 case SHADER_OPCODE_TXF_CMS
:
3674 msg_lod
= offset(msg_coords
, bld
, 3);
3676 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u));
3678 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3679 msg_end
= offset(msg_lod
, bld
, 2);
3686 inst
->src
[0] = reg_undef
;
3687 inst
->src
[1] = sampler
;
3688 inst
->resize_sources(2);
3689 inst
->base_mrf
= message
.reg
;
3690 inst
->mlen
= msg_end
.reg
- message
.reg
;
3691 inst
->header_size
= header_size
;
3693 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3694 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3698 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3700 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3703 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
3707 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3709 const fs_reg
&shadow_c
,
3710 fs_reg lod
, fs_reg lod2
,
3711 const fs_reg
&sample_index
,
3712 const fs_reg
&mcs
, const fs_reg
&sampler
,
3713 fs_reg offset_value
,
3714 unsigned coord_components
,
3715 unsigned grad_components
)
3717 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3718 int reg_width
= bld
.dispatch_width() / 8;
3719 unsigned header_size
= 0, length
= 0;
3720 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3721 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3722 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3724 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3725 offset_value
.file
!= BAD_FILE
||
3726 is_high_sampler(devinfo
, sampler
)) {
3727 /* For general texture offsets (no txf workaround), we need a header to
3728 * put them in. Note that we're only reserving space for it in the
3729 * message payload as it will be initialized implicitly by the
3732 * TG4 needs to place its channel select in the header, for interaction
3733 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3734 * larger sampler numbers we need to offset the Sampler State Pointer in
3738 sources
[0] = fs_reg();
3742 if (shadow_c
.file
!= BAD_FILE
) {
3743 bld
.MOV(sources
[length
], shadow_c
);
3747 bool coordinate_done
= false;
3749 /* The sampler can only meaningfully compute LOD for fragment shader
3750 * messages. For all other stages, we change the opcode to TXL and
3751 * hardcode the LOD to 0.
3753 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3754 op
== SHADER_OPCODE_TEX
) {
3755 op
= SHADER_OPCODE_TXL
;
3759 /* Set up the LOD info */
3762 case SHADER_OPCODE_TXL
:
3763 bld
.MOV(sources
[length
], lod
);
3766 case SHADER_OPCODE_TXD
:
3767 /* TXD should have been lowered in SIMD16 mode. */
3768 assert(bld
.dispatch_width() == 8);
3770 /* Load dPdx and the coordinate together:
3771 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3773 for (unsigned i
= 0; i
< coord_components
; i
++) {
3774 bld
.MOV(sources
[length
], coordinate
);
3775 coordinate
= offset(coordinate
, bld
, 1);
3778 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3779 * only derivatives for (u, v, r).
3781 if (i
< grad_components
) {
3782 bld
.MOV(sources
[length
], lod
);
3783 lod
= offset(lod
, bld
, 1);
3786 bld
.MOV(sources
[length
], lod2
);
3787 lod2
= offset(lod2
, bld
, 1);
3792 coordinate_done
= true;
3794 case SHADER_OPCODE_TXS
:
3795 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
3798 case SHADER_OPCODE_TXF
:
3799 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
3800 * On Gen9 they are u, v, lod, r
3802 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3803 coordinate
= offset(coordinate
, bld
, 1);
3806 if (devinfo
->gen
>= 9) {
3807 if (coord_components
>= 2) {
3808 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3809 coordinate
= offset(coordinate
, bld
, 1);
3814 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
3817 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
3818 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3819 coordinate
= offset(coordinate
, bld
, 1);
3823 coordinate_done
= true;
3825 case SHADER_OPCODE_TXF_CMS
:
3826 case SHADER_OPCODE_TXF_UMS
:
3827 case SHADER_OPCODE_TXF_MCS
:
3828 if (op
== SHADER_OPCODE_TXF_UMS
|| op
== SHADER_OPCODE_TXF_CMS
) {
3829 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
3833 if (op
== SHADER_OPCODE_TXF_CMS
) {
3834 /* Data from the multisample control surface. */
3835 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
3839 /* There is no offsetting for this message; just copy in the integer
3840 * texture coordinates.
3842 for (unsigned i
= 0; i
< coord_components
; i
++) {
3843 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3844 coordinate
= offset(coordinate
, bld
, 1);
3848 coordinate_done
= true;
3850 case SHADER_OPCODE_TG4_OFFSET
:
3851 /* gather4_po_c should have been lowered in SIMD16 mode. */
3852 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
3854 /* More crazy intermixing */
3855 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
3856 bld
.MOV(sources
[length
], coordinate
);
3857 coordinate
= offset(coordinate
, bld
, 1);
3861 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
3862 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
3863 offset_value
= offset(offset_value
, bld
, 1);
3867 if (coord_components
== 3) { /* r if present */
3868 bld
.MOV(sources
[length
], coordinate
);
3869 coordinate
= offset(coordinate
, bld
, 1);
3873 coordinate_done
= true;
3879 /* Set up the coordinate (except for cases where it was done above) */
3880 if (!coordinate_done
) {
3881 for (unsigned i
= 0; i
< coord_components
; i
++) {
3882 bld
.MOV(sources
[length
], coordinate
);
3883 coordinate
= offset(coordinate
, bld
, 1);
3890 mlen
= length
* reg_width
- header_size
;
3892 mlen
= length
* reg_width
;
3894 const fs_reg src_payload
= fs_reg(GRF
, bld
.shader
->alloc
.allocate(mlen
),
3895 BRW_REGISTER_TYPE_F
);
3896 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
3898 /* Generate the SEND. */
3900 inst
->src
[0] = src_payload
;
3901 inst
->src
[1] = sampler
;
3902 inst
->resize_sources(2);
3903 inst
->base_mrf
= -1;
3905 inst
->header_size
= header_size
;
3907 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3908 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3912 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
3914 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3915 const fs_reg
&coordinate
= inst
->src
[0];
3916 const fs_reg
&shadow_c
= inst
->src
[1];
3917 const fs_reg
&lod
= inst
->src
[2];
3918 const fs_reg
&lod2
= inst
->src
[3];
3919 const fs_reg
&sample_index
= inst
->src
[4];
3920 const fs_reg
&mcs
= inst
->src
[5];
3921 const fs_reg
&sampler
= inst
->src
[6];
3922 const fs_reg
&offset_value
= inst
->src
[7];
3923 assert(inst
->src
[8].file
== IMM
&& inst
->src
[9].file
== IMM
);
3924 const unsigned coord_components
= inst
->src
[8].fixed_hw_reg
.dw1
.ud
;
3925 const unsigned grad_components
= inst
->src
[9].fixed_hw_reg
.dw1
.ud
;
3927 if (devinfo
->gen
>= 7) {
3928 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
3929 shadow_c
, lod
, lod2
, sample_index
,
3930 mcs
, sampler
, offset_value
,
3931 coord_components
, grad_components
);
3932 } else if (devinfo
->gen
>= 5) {
3933 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
3934 shadow_c
, lod
, lod2
, sample_index
,
3935 sampler
, offset_value
,
3936 coord_components
, grad_components
);
3938 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
3939 shadow_c
, lod
, lod2
, sampler
,
3940 coord_components
, grad_components
);
3945 * Initialize the header present in some typed and untyped surface
3949 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
3951 fs_builder ubld
= bld
.exec_all().group(8, 0);
3952 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3953 ubld
.MOV(dst
, fs_reg(0));
3954 ubld
.MOV(component(dst
, 7), sample_mask
);
3959 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3960 const fs_reg
&sample_mask
)
3962 /* Get the logical send arguments. */
3963 const fs_reg
&addr
= inst
->src
[0];
3964 const fs_reg
&src
= inst
->src
[1];
3965 const fs_reg
&surface
= inst
->src
[2];
3966 const UNUSED fs_reg
&dims
= inst
->src
[3];
3967 const fs_reg
&arg
= inst
->src
[4];
3969 /* Calculate the total number of components of the payload. */
3970 const unsigned addr_sz
= inst
->components_read(0);
3971 const unsigned src_sz
= inst
->components_read(1);
3972 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
3973 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
3975 /* Allocate space for the payload. */
3976 fs_reg
*const components
= new fs_reg
[sz
];
3977 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
3980 /* Construct the payload. */
3982 components
[n
++] = emit_surface_header(bld
, sample_mask
);
3984 for (unsigned i
= 0; i
< addr_sz
; i
++)
3985 components
[n
++] = offset(addr
, bld
, i
);
3987 for (unsigned i
= 0; i
< src_sz
; i
++)
3988 components
[n
++] = offset(src
, bld
, i
);
3990 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
3992 /* Update the original instruction. */
3994 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
3995 inst
->header_size
= header_sz
;
3997 inst
->src
[0] = payload
;
3998 inst
->src
[1] = surface
;
4000 inst
->resize_sources(3);
4002 delete[] components
;
4006 fs_visitor::lower_logical_sends()
4008 bool progress
= false;
4010 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4011 const fs_builder
ibld(this, block
, inst
);
4013 switch (inst
->opcode
) {
4014 case FS_OPCODE_FB_WRITE_LOGICAL
:
4015 assert(stage
== MESA_SHADER_FRAGMENT
);
4016 lower_fb_write_logical_send(ibld
, inst
,
4017 (const brw_wm_prog_data
*)prog_data
,
4018 (const brw_wm_prog_key
*)key
,
4022 case SHADER_OPCODE_TEX_LOGICAL
:
4023 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4026 case SHADER_OPCODE_TXD_LOGICAL
:
4027 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4030 case SHADER_OPCODE_TXF_LOGICAL
:
4031 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4034 case SHADER_OPCODE_TXL_LOGICAL
:
4035 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4038 case SHADER_OPCODE_TXS_LOGICAL
:
4039 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4042 case FS_OPCODE_TXB_LOGICAL
:
4043 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4046 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4047 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4050 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4051 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4054 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4055 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4058 case SHADER_OPCODE_LOD_LOGICAL
:
4059 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4062 case SHADER_OPCODE_TG4_LOGICAL
:
4063 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4066 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4067 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4070 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4071 lower_surface_logical_send(ibld
, inst
,
4072 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4076 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4077 lower_surface_logical_send(ibld
, inst
,
4078 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4079 ibld
.sample_mask_reg());
4082 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4083 lower_surface_logical_send(ibld
, inst
,
4084 SHADER_OPCODE_UNTYPED_ATOMIC
,
4085 ibld
.sample_mask_reg());
4088 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4089 lower_surface_logical_send(ibld
, inst
,
4090 SHADER_OPCODE_TYPED_SURFACE_READ
,
4094 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4095 lower_surface_logical_send(ibld
, inst
,
4096 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4097 ibld
.sample_mask_reg());
4100 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4101 lower_surface_logical_send(ibld
, inst
,
4102 SHADER_OPCODE_TYPED_ATOMIC
,
4103 ibld
.sample_mask_reg());
4114 invalidate_live_intervals();
4120 * Get the closest native SIMD width supported by the hardware for instruction
4121 * \p inst. The instruction will be left untouched by
4122 * fs_visitor::lower_simd_width() if the returned value is equal to the
4123 * original execution size.
4126 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4127 const fs_inst
*inst
)
4129 switch (inst
->opcode
) {
4130 case BRW_OPCODE_MOV
:
4131 case BRW_OPCODE_SEL
:
4132 case BRW_OPCODE_NOT
:
4133 case BRW_OPCODE_AND
:
4135 case BRW_OPCODE_XOR
:
4136 case BRW_OPCODE_SHR
:
4137 case BRW_OPCODE_SHL
:
4138 case BRW_OPCODE_ASR
:
4139 case BRW_OPCODE_CMP
:
4140 case BRW_OPCODE_CMPN
:
4141 case BRW_OPCODE_CSEL
:
4142 case BRW_OPCODE_F32TO16
:
4143 case BRW_OPCODE_F16TO32
:
4144 case BRW_OPCODE_BFREV
:
4145 case BRW_OPCODE_BFE
:
4146 case BRW_OPCODE_BFI1
:
4147 case BRW_OPCODE_BFI2
:
4148 case BRW_OPCODE_ADD
:
4149 case BRW_OPCODE_MUL
:
4150 case BRW_OPCODE_AVG
:
4151 case BRW_OPCODE_FRC
:
4152 case BRW_OPCODE_RNDU
:
4153 case BRW_OPCODE_RNDD
:
4154 case BRW_OPCODE_RNDE
:
4155 case BRW_OPCODE_RNDZ
:
4156 case BRW_OPCODE_LZD
:
4157 case BRW_OPCODE_FBH
:
4158 case BRW_OPCODE_FBL
:
4159 case BRW_OPCODE_CBIT
:
4160 case BRW_OPCODE_SAD2
:
4161 case BRW_OPCODE_MAD
:
4162 case BRW_OPCODE_LRP
:
4163 case SHADER_OPCODE_RCP
:
4164 case SHADER_OPCODE_RSQ
:
4165 case SHADER_OPCODE_SQRT
:
4166 case SHADER_OPCODE_EXP2
:
4167 case SHADER_OPCODE_LOG2
:
4168 case SHADER_OPCODE_POW
:
4169 case SHADER_OPCODE_INT_QUOTIENT
:
4170 case SHADER_OPCODE_INT_REMAINDER
:
4171 case SHADER_OPCODE_SIN
:
4172 case SHADER_OPCODE_COS
: {
4173 /* According to the PRMs:
4174 * "A. In Direct Addressing mode, a source cannot span more than 2
4175 * adjacent GRF registers.
4176 * B. A destination cannot span more than 2 adjacent GRF registers."
4178 * Look for the source or destination with the largest register region
4179 * which is the one that is going to limit the overal execution size of
4180 * the instruction due to this rule.
4182 unsigned reg_count
= inst
->regs_written
;
4184 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4185 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4187 /* Calculate the maximum execution size of the instruction based on the
4188 * factor by which it goes over the hardware limit of 2 GRFs.
4190 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4192 case SHADER_OPCODE_MULH
:
4193 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4194 * is 8-wide on Gen7+.
4196 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4198 case FS_OPCODE_FB_WRITE_LOGICAL
:
4199 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4202 assert(devinfo
->gen
!= 6 ||
4203 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4204 inst
->exec_size
== 8);
4205 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4206 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4207 8 : inst
->exec_size
);
4209 case SHADER_OPCODE_TXD_LOGICAL
:
4210 /* TXD is unsupported in SIMD16 mode. */
4213 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4214 /* gather4_po_c is unsupported in SIMD16 mode. */
4215 const fs_reg
&shadow_c
= inst
->src
[1];
4216 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4218 case SHADER_OPCODE_TXL_LOGICAL
:
4219 case FS_OPCODE_TXB_LOGICAL
: {
4220 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4221 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4222 * mode because the message exceeds the maximum length of 11.
4224 const fs_reg
&shadow_c
= inst
->src
[1];
4225 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4227 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4230 return inst
->exec_size
;
4232 case SHADER_OPCODE_TXF_LOGICAL
:
4233 case SHADER_OPCODE_TXS_LOGICAL
:
4234 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4235 * messages. Use SIMD16 instead.
4237 if (devinfo
->gen
== 4)
4240 return inst
->exec_size
;
4242 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4243 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4244 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4248 return inst
->exec_size
;
4253 * The \p rows array of registers represents a \p num_rows by \p num_columns
4254 * matrix in row-major order, write it in column-major order into the register
4255 * passed as destination. \p stride gives the separation between matrix
4256 * elements in the input in fs_builder::dispatch_width() units.
4259 emit_transpose(const fs_builder
&bld
,
4260 const fs_reg
&dst
, const fs_reg
*rows
,
4261 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4263 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4265 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4266 for (unsigned j
= 0; j
< num_rows
; ++j
)
4267 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4270 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4272 delete[] components
;
4276 fs_visitor::lower_simd_width()
4278 bool progress
= false;
4280 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4281 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4283 if (lower_width
!= inst
->exec_size
) {
4284 /* Builder matching the original instruction. We may also need to
4285 * emit an instruction of width larger than the original, set the
4286 * execution size of the builder to the highest of both for now so
4287 * we're sure that both cases can be handled.
4289 const fs_builder ibld
= bld
.at(block
, inst
)
4290 .exec_all(inst
->force_writemask_all
)
4291 .group(MAX2(inst
->exec_size
, lower_width
),
4292 inst
->force_sechalf
);
4294 /* Split the copies in chunks of the execution width of either the
4295 * original or the lowered instruction, whichever is lower.
4297 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4298 const unsigned n
= inst
->exec_size
/ copy_width
;
4299 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4300 inst
->dst
.component_size(inst
->exec_size
);
4303 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4304 !inst
->writes_accumulator
&& !inst
->mlen
);
4306 for (unsigned i
= 0; i
< n
; i
++) {
4307 /* Emit a copy of the original instruction with the lowered width.
4308 * If the EOT flag was set throw it away except for the last
4309 * instruction to avoid killing the thread prematurely.
4311 fs_inst split_inst
= *inst
;
4312 split_inst
.exec_size
= lower_width
;
4313 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4315 /* Select the correct channel enables for the i-th group, then
4316 * transform the sources and destination and emit the lowered
4319 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4321 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4322 if (inst
->src
[j
].file
!= BAD_FILE
&&
4323 !is_uniform(inst
->src
[j
])) {
4324 /* Get the i-th copy_width-wide chunk of the source. */
4325 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4326 const unsigned src_size
= inst
->components_read(j
);
4328 /* Use a trivial transposition to copy one every n
4329 * copy_width-wide components of the register into a
4330 * temporary passed as source to the lowered instruction.
4332 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4333 emit_transpose(lbld
.group(copy_width
, 0),
4334 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4338 if (inst
->regs_written
) {
4339 /* Allocate enough space to hold the result of the lowered
4340 * instruction and fix up the number of registers written.
4342 split_inst
.dst
= dsts
[i
] =
4343 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4344 split_inst
.regs_written
=
4345 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4349 lbld
.emit(split_inst
);
4352 if (inst
->regs_written
) {
4353 /* Distance between useful channels in the temporaries, skipping
4354 * garbage if the lowered instruction is wider than the original.
4356 const unsigned m
= lower_width
/ copy_width
;
4358 /* Interleave the components of the result from the lowered
4359 * instructions. We need to set exec_all() when copying more than
4360 * one half per component, because LOAD_PAYLOAD (in terms of which
4361 * emit_transpose is implemented) can only use the same channel
4362 * enable signals for all of its non-header sources.
4364 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4365 .group(copy_width
, 0),
4366 inst
->dst
, dsts
, n
, dst_size
, m
);
4369 inst
->remove(block
);
4375 invalidate_live_intervals();
4381 fs_visitor::dump_instructions()
4383 dump_instructions(NULL
);
4387 fs_visitor::dump_instructions(const char *name
)
4389 FILE *file
= stderr
;
4390 if (name
&& geteuid() != 0) {
4391 file
= fopen(name
, "w");
4397 calculate_register_pressure();
4398 int ip
= 0, max_pressure
= 0;
4399 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4400 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4401 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4402 dump_instruction(inst
, file
);
4405 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4408 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4409 fprintf(file
, "%4d: ", ip
++);
4410 dump_instruction(inst
, file
);
4414 if (file
!= stderr
) {
4420 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4422 dump_instruction(be_inst
, stderr
);
4426 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4428 fs_inst
*inst
= (fs_inst
*)be_inst
;
4430 if (inst
->predicate
) {
4431 fprintf(file
, "(%cf0.%d) ",
4432 inst
->predicate_inverse
? '-' : '+',
4436 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4438 fprintf(file
, ".sat");
4439 if (inst
->conditional_mod
) {
4440 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4441 if (!inst
->predicate
&&
4442 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4443 inst
->opcode
!= BRW_OPCODE_IF
&&
4444 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4445 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4448 fprintf(file
, "(%d) ", inst
->exec_size
);
4451 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4454 switch (inst
->dst
.file
) {
4456 fprintf(file
, "vgrf%d", inst
->dst
.reg
);
4457 if (alloc
.sizes
[inst
->dst
.reg
] != inst
->regs_written
||
4458 inst
->dst
.subreg_offset
)
4459 fprintf(file
, "+%d.%d",
4460 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4463 fprintf(file
, "m%d", inst
->dst
.reg
);
4466 fprintf(file
, "(null)");
4469 fprintf(file
, "***u%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
4472 fprintf(file
, "***attr%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
4475 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
4476 switch (inst
->dst
.fixed_hw_reg
.nr
) {
4478 fprintf(file
, "null");
4480 case BRW_ARF_ADDRESS
:
4481 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
4483 case BRW_ARF_ACCUMULATOR
:
4484 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
4487 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
4488 inst
->dst
.fixed_hw_reg
.subnr
);
4491 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
4492 inst
->dst
.fixed_hw_reg
.subnr
);
4496 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
4498 if (inst
->dst
.fixed_hw_reg
.subnr
)
4499 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
4502 fprintf(file
, "???");
4505 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4507 for (int i
= 0; i
< inst
->sources
; i
++) {
4508 if (inst
->src
[i
].negate
)
4510 if (inst
->src
[i
].abs
)
4512 switch (inst
->src
[i
].file
) {
4514 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
4515 if (alloc
.sizes
[inst
->src
[i
].reg
] != (unsigned)inst
->regs_read(i
) ||
4516 inst
->src
[i
].subreg_offset
)
4517 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4518 inst
->src
[i
].subreg_offset
);
4521 fprintf(file
, "***m%d***", inst
->src
[i
].reg
);
4524 fprintf(file
, "attr%d+%d", inst
->src
[i
].reg
, inst
->src
[i
].reg_offset
);
4527 fprintf(file
, "u%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
4528 if (inst
->src
[i
].reladdr
) {
4529 fprintf(file
, "+reladdr");
4530 } else if (inst
->src
[i
].subreg_offset
) {
4531 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4532 inst
->src
[i
].subreg_offset
);
4536 fprintf(file
, "(null)");
4539 switch (inst
->src
[i
].type
) {
4540 case BRW_REGISTER_TYPE_F
:
4541 fprintf(file
, "%ff", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
4543 case BRW_REGISTER_TYPE_W
:
4544 case BRW_REGISTER_TYPE_D
:
4545 fprintf(file
, "%dd", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
4547 case BRW_REGISTER_TYPE_UW
:
4548 case BRW_REGISTER_TYPE_UD
:
4549 fprintf(file
, "%uu", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
4551 case BRW_REGISTER_TYPE_VF
:
4552 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4553 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
4554 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
4555 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
4556 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
4559 fprintf(file
, "???");
4564 if (inst
->src
[i
].fixed_hw_reg
.negate
)
4566 if (inst
->src
[i
].fixed_hw_reg
.abs
)
4568 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
4569 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
4571 fprintf(file
, "null");
4573 case BRW_ARF_ADDRESS
:
4574 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4576 case BRW_ARF_ACCUMULATOR
:
4577 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4580 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
4581 inst
->src
[i
].fixed_hw_reg
.subnr
);
4584 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
4585 inst
->src
[i
].fixed_hw_reg
.subnr
);
4589 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
4591 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
4592 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4593 if (inst
->src
[i
].fixed_hw_reg
.abs
)
4597 fprintf(file
, "???");
4600 if (inst
->src
[i
].abs
)
4603 if (inst
->src
[i
].file
!= IMM
) {
4604 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4607 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4608 fprintf(file
, ", ");
4613 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4614 if (inst
->force_sechalf
)
4615 fprintf(file
, "2ndhalf ");
4617 fprintf(file
, "1sthalf ");
4620 fprintf(file
, "\n");
4624 * Possibly returns an instruction that set up @param reg.
4626 * Sometimes we want to take the result of some expression/variable
4627 * dereference tree and rewrite the instruction generating the result
4628 * of the tree. When processing the tree, we know that the
4629 * instructions generated are all writing temporaries that are dead
4630 * outside of this tree. So, if we have some instructions that write
4631 * a temporary, we're free to point that temp write somewhere else.
4633 * Note that this doesn't guarantee that the instruction generated
4634 * only reg -- it might be the size=4 destination of a texture instruction.
4637 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4642 end
->is_partial_write() ||
4644 !reg
.equals(end
->dst
)) {
4652 fs_visitor::setup_payload_gen6()
4655 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
4656 unsigned barycentric_interp_modes
=
4657 (stage
== MESA_SHADER_FRAGMENT
) ?
4658 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4660 assert(devinfo
->gen
>= 6);
4662 /* R0-1: masks, pixel X/Y coordinates. */
4663 payload
.num_regs
= 2;
4664 /* R2: only for 32-pixel dispatch.*/
4666 /* R3-26: barycentric interpolation coordinates. These appear in the
4667 * same order that they appear in the brw_wm_barycentric_interp_mode
4668 * enum. Each set of coordinates occupies 2 registers if dispatch width
4669 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4670 * appear if they were enabled using the "Barycentric Interpolation
4671 * Mode" bits in WM_STATE.
4673 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4674 if (barycentric_interp_modes
& (1 << i
)) {
4675 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4676 payload
.num_regs
+= 2;
4677 if (dispatch_width
== 16) {
4678 payload
.num_regs
+= 2;
4683 /* R27: interpolated depth if uses source depth */
4685 payload
.source_depth_reg
= payload
.num_regs
;
4687 if (dispatch_width
== 16) {
4688 /* R28: interpolated depth if not SIMD8. */
4692 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4694 payload
.source_w_reg
= payload
.num_regs
;
4696 if (dispatch_width
== 16) {
4697 /* R30: interpolated W if not SIMD8. */
4702 if (stage
== MESA_SHADER_FRAGMENT
) {
4703 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4704 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4705 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4706 /* R31: MSAA position offsets. */
4707 if (prog_data
->uses_pos_offset
) {
4708 payload
.sample_pos_reg
= payload
.num_regs
;
4713 /* R32: MSAA input coverage mask */
4714 if (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
4715 assert(devinfo
->gen
>= 7);
4716 payload
.sample_mask_in_reg
= payload
.num_regs
;
4718 if (dispatch_width
== 16) {
4719 /* R33: input coverage mask if not SIMD8. */
4724 /* R34-: bary for 32-pixel. */
4725 /* R58-59: interp W for 32-pixel. */
4727 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4728 source_depth_to_render_target
= true;
4733 fs_visitor::setup_vs_payload()
4735 /* R0: thread header, R1: urb handles */
4736 payload
.num_regs
= 2;
4740 * We are building the local ID push constant data using the simplest possible
4741 * method. We simply push the local IDs directly as they should appear in the
4742 * registers for the uvec3 gl_LocalInvocationID variable.
4744 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
4745 * registers worth of push constant space.
4747 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
4748 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
4751 * FINISHME: There are a few easy optimizations to consider.
4753 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
4754 * no need for using push constant space for that dimension.
4756 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
4757 * easily use 16-bit words rather than 32-bit dwords in the push constant
4760 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
4761 * conveying the data, and thereby reduce push constant usage.
4765 fs_visitor::setup_cs_payload()
4767 assert(devinfo
->gen
>= 7);
4768 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
4770 payload
.num_regs
= 1;
4772 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
4773 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
4774 payload
.local_invocation_id_reg
= payload
.num_regs
;
4775 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
4780 fs_visitor::calculate_register_pressure()
4782 invalidate_live_intervals();
4783 calculate_live_intervals();
4785 unsigned num_instructions
= 0;
4786 foreach_block(block
, cfg
)
4787 num_instructions
+= block
->instructions
.length();
4789 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
4791 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
4792 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
4793 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
4798 fs_visitor::optimize()
4800 /* Start by validating the shader we currently have. */
4803 /* bld is the common builder object pointing at the end of the program we
4804 * used to translate it into i965 IR. For the optimization and lowering
4805 * passes coming next, any code added after the end of the program without
4806 * having explicitly called fs_builder::at() clearly points at a mistake.
4807 * Ideally optimization passes wouldn't be part of the visitor so they
4808 * wouldn't have access to bld at all, but they do, so just in case some
4809 * pass forgets to ask for a location explicitly set it to NULL here to
4810 * make it trip. The dispatch width is initialized to a bogus value to
4811 * make sure that optimizations set the execution controls explicitly to
4812 * match the code they are manipulating instead of relying on the defaults.
4814 bld
= fs_builder(this, 64);
4816 assign_constant_locations();
4817 demote_pull_constants();
4821 split_virtual_grfs();
4824 #define OPT(pass, args...) ({ \
4826 bool this_progress = pass(args); \
4828 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
4829 char filename[64]; \
4830 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
4831 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
4833 backend_shader::dump_instructions(filename); \
4838 progress = progress || this_progress; \
4842 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
4844 snprintf(filename
, 64, "%s%d-%s-00-start",
4845 stage_abbrev
, dispatch_width
, nir
->info
.name
);
4847 backend_shader::dump_instructions(filename
);
4850 bool progress
= false;
4854 OPT(lower_simd_width
);
4855 OPT(lower_logical_sends
);
4862 OPT(remove_duplicate_mrf_writes
);
4866 OPT(opt_copy_propagate
);
4867 OPT(opt_predicated_break
, this);
4868 OPT(opt_cmod_propagation
);
4869 OPT(dead_code_eliminate
);
4870 OPT(opt_peephole_sel
);
4871 OPT(dead_control_flow_eliminate
, this);
4872 OPT(opt_register_renaming
);
4873 OPT(opt_redundant_discard_jumps
);
4874 OPT(opt_saturate_propagation
);
4875 OPT(opt_zero_samples
);
4876 OPT(register_coalesce
);
4877 OPT(compute_to_mrf
);
4878 OPT(eliminate_find_live_channel
);
4880 OPT(compact_virtual_grfs
);
4885 OPT(opt_sampler_eot
);
4887 if (OPT(lower_load_payload
)) {
4888 split_virtual_grfs();
4889 OPT(register_coalesce
);
4890 OPT(compute_to_mrf
);
4891 OPT(dead_code_eliminate
);
4894 OPT(opt_combine_constants
);
4895 OPT(lower_integer_multiplication
);
4897 lower_uniform_pull_constant_loads();
4903 * Three source instruction must have a GRF/MRF destination register.
4904 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
4907 fs_visitor::fixup_3src_null_dest()
4909 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
4910 if (inst
->is_3src() && inst
->dst
.is_null()) {
4911 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
4918 fs_visitor::allocate_registers()
4920 bool allocated_without_spills
;
4922 static const enum instruction_scheduler_mode pre_modes
[] = {
4924 SCHEDULE_PRE_NON_LIFO
,
4928 /* Try each scheduling heuristic to see if it can successfully register
4929 * allocate without spilling. They should be ordered by decreasing
4930 * performance but increasing likelihood of allocating.
4932 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
4933 schedule_instructions(pre_modes
[i
]);
4936 assign_regs_trivial();
4937 allocated_without_spills
= true;
4939 allocated_without_spills
= assign_regs(false);
4941 if (allocated_without_spills
)
4945 if (!allocated_without_spills
) {
4946 /* We assume that any spilling is worse than just dropping back to
4947 * SIMD8. There's probably actually some intermediate point where
4948 * SIMD16 with a couple of spills is still better.
4950 if (dispatch_width
== 16) {
4951 fail("Failure to register allocate. Reduce number of "
4952 "live scalar values to avoid this.");
4954 compiler
->shader_perf_log(log_data
,
4955 "%s shader triggered register spilling. "
4956 "Try reducing the number of live scalar "
4957 "values to improve performance.\n",
4961 /* Since we're out of heuristics, just go spill registers until we
4962 * get an allocation.
4964 while (!assign_regs(true)) {
4970 /* This must come after all optimization and register allocation, since
4971 * it inserts dead code that happens to have side effects, and it does
4972 * so based on the actual physical registers in use.
4974 insert_gen4_send_dependency_workarounds();
4979 if (!allocated_without_spills
)
4980 schedule_instructions(SCHEDULE_POST
);
4982 if (last_scratch
> 0)
4983 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
4987 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
4989 assert(stage
== MESA_SHADER_VERTEX
);
4993 if (shader_time_index
>= 0)
4994 emit_shader_time_begin();
5001 compute_clip_distance(clip_planes
);
5005 if (shader_time_index
>= 0)
5006 emit_shader_time_end();
5012 assign_curb_setup();
5013 assign_vs_urb_setup();
5015 fixup_3src_null_dest();
5016 allocate_registers();
5022 fs_visitor::run_fs(bool do_rep_send
)
5024 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5025 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
5027 assert(stage
== MESA_SHADER_FRAGMENT
);
5029 if (devinfo
->gen
>= 6)
5030 setup_payload_gen6();
5032 setup_payload_gen4();
5036 } else if (do_rep_send
) {
5037 assert(dispatch_width
== 16);
5038 emit_repclear_shader();
5040 if (shader_time_index
>= 0)
5041 emit_shader_time_begin();
5043 calculate_urb_setup();
5044 if (nir
->info
.inputs_read
> 0) {
5045 if (devinfo
->gen
< 6)
5046 emit_interpolation_setup_gen4();
5048 emit_interpolation_setup_gen6();
5051 /* We handle discards by keeping track of the still-live pixels in f0.1.
5052 * Initialize it with the dispatched pixels.
5054 if (wm_prog_data
->uses_kill
) {
5055 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5056 discard_init
->flag_subreg
= 1;
5059 /* Generate FS IR for main(). (the visitor only descends into
5060 * functions called "main").
5067 if (wm_prog_data
->uses_kill
)
5068 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5070 if (wm_key
->alpha_test_func
)
5075 if (shader_time_index
>= 0)
5076 emit_shader_time_end();
5082 assign_curb_setup();
5085 fixup_3src_null_dest();
5086 allocate_registers();
5092 if (dispatch_width
== 8)
5093 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5095 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5101 fs_visitor::run_cs()
5103 assert(stage
== MESA_SHADER_COMPUTE
);
5107 if (shader_time_index
>= 0)
5108 emit_shader_time_begin();
5115 emit_cs_terminate();
5117 if (shader_time_index
>= 0)
5118 emit_shader_time_end();
5124 assign_curb_setup();
5126 fixup_3src_null_dest();
5127 allocate_registers();
5136 * Return a bitfield where bit n is set if barycentric interpolation mode n
5137 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
5140 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
5141 bool shade_model_flat
,
5142 bool persample_shading
,
5143 const nir_shader
*shader
)
5145 unsigned barycentric_interp_modes
= 0;
5147 nir_foreach_variable(var
, &shader
->inputs
) {
5148 enum glsl_interp_qualifier interp_qualifier
=
5149 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5150 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
5151 bool is_sample
= var
->data
.sample
|| persample_shading
;
5152 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5153 (var
->data
.location
== VARYING_SLOT_COL1
);
5155 /* Ignore WPOS and FACE, because they don't require interpolation. */
5156 if (var
->data
.location
== VARYING_SLOT_POS
||
5157 var
->data
.location
== VARYING_SLOT_FACE
)
5160 /* Determine the set (or sets) of barycentric coordinates needed to
5161 * interpolate this variable. Note that when
5162 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
5163 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
5164 * for lit pixels, so we need both sets of barycentric coordinates.
5166 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
5168 barycentric_interp_modes
|=
5169 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
5170 } else if (is_sample
) {
5171 barycentric_interp_modes
|=
5172 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
5174 if ((!is_centroid
&& !is_sample
) ||
5175 devinfo
->needs_unlit_centroid_workaround
) {
5176 barycentric_interp_modes
|=
5177 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
5179 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
5180 (!(shade_model_flat
&& is_gl_Color
) &&
5181 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
5183 barycentric_interp_modes
|=
5184 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
5185 } else if (is_sample
) {
5186 barycentric_interp_modes
|=
5187 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
5189 if ((!is_centroid
&& !is_sample
) ||
5190 devinfo
->needs_unlit_centroid_workaround
) {
5191 barycentric_interp_modes
|=
5192 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
5197 return barycentric_interp_modes
;
5201 computed_depth_mode(const nir_shader
*shader
)
5203 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5204 switch (shader
->info
.fs
.depth_layout
) {
5205 case FRAG_DEPTH_LAYOUT_NONE
:
5206 case FRAG_DEPTH_LAYOUT_ANY
:
5207 return BRW_PSCDEPTH_ON
;
5208 case FRAG_DEPTH_LAYOUT_GREATER
:
5209 return BRW_PSCDEPTH_ON_GE
;
5210 case FRAG_DEPTH_LAYOUT_LESS
:
5211 return BRW_PSCDEPTH_ON_LE
;
5212 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
5213 return BRW_PSCDEPTH_OFF
;
5216 return BRW_PSCDEPTH_OFF
;
5220 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
5222 const struct brw_wm_prog_key
*key
,
5223 struct brw_wm_prog_data
*prog_data
,
5224 const nir_shader
*shader
,
5225 struct gl_program
*prog
,
5226 int shader_time_index8
, int shader_time_index16
,
5228 unsigned *final_assembly_size
,
5231 /* key->alpha_test_func means simulating alpha testing via discards,
5232 * so the shader definitely kills pixels.
5234 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
5235 prog_data
->uses_omask
=
5236 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
5237 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
5238 prog_data
->computed_stencil
=
5239 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
5241 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
5243 prog_data
->barycentric_interp_modes
=
5244 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
5246 key
->persample_shading
,
5249 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
,
5250 &prog_data
->base
, prog
, shader
, 8,
5251 shader_time_index8
);
5252 if (!v
.run_fs(false /* do_rep_send */)) {
5254 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
5259 cfg_t
*simd16_cfg
= NULL
;
5260 fs_visitor
v2(compiler
, log_data
, mem_ctx
, key
,
5261 &prog_data
->base
, prog
, shader
, 16,
5262 shader_time_index16
);
5263 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
5264 if (!v
.simd16_unsupported
) {
5265 /* Try a SIMD16 compile */
5266 v2
.import_uniforms(&v
);
5267 if (!v2
.run_fs(use_rep_send
)) {
5268 compiler
->shader_perf_log(log_data
,
5269 "SIMD16 shader failed to compile: %s",
5272 simd16_cfg
= v2
.cfg
;
5278 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || use_rep_send
;
5279 if ((no_simd8
|| compiler
->devinfo
->gen
< 5) && simd16_cfg
) {
5281 prog_data
->no_8
= true;
5284 prog_data
->no_8
= false;
5287 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
5288 v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
5290 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5291 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
5292 shader
->info
.label
? shader
->info
.label
:
5294 shader
->info
.name
));
5298 g
.generate_code(simd8_cfg
, 8);
5300 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5302 return g
.get_assembly(final_assembly_size
);
5306 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*prog_data
,
5307 void *buffer
, uint32_t threads
, uint32_t stride
)
5309 if (prog_data
->local_invocation_id_regs
== 0)
5312 /* 'stride' should be an integer number of registers, that is, a multiple
5315 assert(stride
% 32 == 0);
5317 unsigned x
= 0, y
= 0, z
= 0;
5318 for (unsigned t
= 0; t
< threads
; t
++) {
5319 uint32_t *param
= (uint32_t *) buffer
+ stride
* t
/ 4;
5321 for (unsigned i
= 0; i
< prog_data
->simd_size
; i
++) {
5322 param
[0 * prog_data
->simd_size
+ i
] = x
;
5323 param
[1 * prog_data
->simd_size
+ i
] = y
;
5324 param
[2 * prog_data
->simd_size
+ i
] = z
;
5327 if (x
== prog_data
->local_size
[0]) {
5330 if (y
== prog_data
->local_size
[1]) {
5333 if (z
== prog_data
->local_size
[2])
5342 fs_visitor::emit_cs_local_invocation_id_setup()
5344 assert(stage
== MESA_SHADER_COMPUTE
);
5346 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5348 struct brw_reg src
=
5349 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
5350 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
5352 src
.nr
+= dispatch_width
/ 8;
5353 bld
.MOV(offset(*reg
, bld
, 1), src
);
5354 src
.nr
+= dispatch_width
/ 8;
5355 bld
.MOV(offset(*reg
, bld
, 2), src
);
5361 fs_visitor::emit_cs_work_group_id_setup()
5363 assert(stage
== MESA_SHADER_COMPUTE
);
5365 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5367 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
5368 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
5369 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
5371 bld
.MOV(*reg
, r0_1
);
5372 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
5373 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
5379 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
5381 const struct brw_cs_prog_key
*key
,
5382 struct brw_cs_prog_data
*prog_data
,
5383 const nir_shader
*shader
,
5384 int shader_time_index
,
5385 unsigned *final_assembly_size
,
5388 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
5389 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
5390 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
5391 unsigned local_workgroup_size
=
5392 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
5393 shader
->info
.cs
.local_size
[2];
5395 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
5398 const char *fail_msg
= NULL
;
5400 /* Now the main event: Visit the shader IR and generate our CS IR for it.
5402 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5403 NULL
, /* Never used in core profile */
5404 shader
, 8, shader_time_index
);
5406 fail_msg
= v8
.fail_msg
;
5407 } else if (local_workgroup_size
<= 8 * max_cs_threads
) {
5409 prog_data
->simd_size
= 8;
5412 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5413 NULL
, /* Never used in core profile */
5414 shader
, 16, shader_time_index
);
5415 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
5416 !fail_msg
&& !v8
.simd16_unsupported
&&
5417 local_workgroup_size
<= 16 * max_cs_threads
) {
5418 /* Try a SIMD16 compile */
5419 v16
.import_uniforms(&v8
);
5420 if (!v16
.run_cs()) {
5421 compiler
->shader_perf_log(log_data
,
5422 "SIMD16 shader failed to compile: %s",
5426 "Couldn't generate SIMD16 program and not "
5427 "enough threads for SIMD8";
5431 prog_data
->simd_size
= 16;
5435 if (unlikely(cfg
== NULL
)) {
5438 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
5443 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
5444 v8
.promoted_constants
, v8
.runtime_check_aads_emit
, "CS");
5445 if (INTEL_DEBUG
& DEBUG_CS
) {
5446 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
5447 shader
->info
.label
? shader
->info
.label
:
5450 g
.enable_debug(name
);
5453 g
.generate_code(cfg
, prog_data
->simd_size
);
5455 return g
.get_assembly(final_assembly_size
);