2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
32 #include "brw_context.h"
37 #include "brw_vec4_gs_visitor.h"
39 #include "brw_program.h"
40 #include "brw_dead_control_flow.h"
41 #include "compiler/glsl_types.h"
42 #include "compiler/nir/nir_builder.h"
43 #include "program/prog_parameter.h"
47 static unsigned get_lowered_simd_width(const struct brw_device_info
*devinfo
,
51 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
52 const fs_reg
*src
, unsigned sources
)
54 memset(this, 0, sizeof(*this));
56 this->src
= new fs_reg
[MAX2(sources
, 3)];
57 for (unsigned i
= 0; i
< sources
; i
++)
58 this->src
[i
] = src
[i
];
60 this->opcode
= opcode
;
62 this->sources
= sources
;
63 this->exec_size
= exec_size
;
66 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
68 assert(this->exec_size
!= 0);
70 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
72 /* This will be the case for almost all instructions. */
79 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
83 this->regs_written
= 0;
87 unreachable("Invalid destination register file");
90 this->writes_accumulator
= false;
95 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
98 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
100 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
103 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
105 init(opcode
, exec_size
, dst
, NULL
, 0);
108 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
111 const fs_reg src
[1] = { src0
};
112 init(opcode
, exec_size
, dst
, src
, 1);
115 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
116 const fs_reg
&src0
, const fs_reg
&src1
)
118 const fs_reg src
[2] = { src0
, src1
};
119 init(opcode
, exec_size
, dst
, src
, 2);
122 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
123 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
125 const fs_reg src
[3] = { src0
, src1
, src2
};
126 init(opcode
, exec_size
, dst
, src
, 3);
129 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
130 const fs_reg src
[], unsigned sources
)
132 init(opcode
, exec_width
, dst
, src
, sources
);
135 fs_inst::fs_inst(const fs_inst
&that
)
137 memcpy(this, &that
, sizeof(that
));
139 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
141 for (unsigned i
= 0; i
< that
.sources
; i
++)
142 this->src
[i
] = that
.src
[i
];
151 fs_inst::resize_sources(uint8_t num_sources
)
153 if (this->sources
!= num_sources
) {
154 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
156 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
157 src
[i
] = this->src
[i
];
161 this->sources
= num_sources
;
166 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
168 const fs_reg
&surf_index
,
169 const fs_reg
&varying_offset
,
170 uint32_t const_offset
)
172 /* We have our constant surface use a pitch of 4 bytes, so our index can
173 * be any component of a vector, and then we load 4 contiguous
174 * components starting from that.
176 * We break down the const_offset to a portion added to the variable
177 * offset and a portion done using reg_offset, which means that if you
178 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
179 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
180 * CSE can later notice that those loads are all the same and eliminate
181 * the redundant ones.
183 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
184 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
186 /* The pull load message will load a vec4 (16 bytes). If we are loading
187 * a double this means we are only loading 2 elements worth of data.
188 * We also want to use a 32-bit data type for the dst of the load operation
189 * so other parts of the driver don't get confused about the size of the
192 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
193 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
194 vec4_result
, surf_index
, vec4_offset
);
195 inst
->regs_written
= 4 * bld
.dispatch_width() / 8;
197 if (type_sz(dst
.type
) == 8) {
198 shuffle_32bit_load_result_to_64bit_data(
199 bld
, retype(vec4_result
, dst
.type
), vec4_result
, 2);
202 vec4_result
.type
= dst
.type
;
203 bld
.MOV(dst
, offset(vec4_result
, bld
,
204 (const_offset
& 0xf) / type_sz(vec4_result
.type
)));
208 * A helper for MOV generation for fixing up broken hardware SEND dependency
212 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
214 /* The caller always wants uncompressed to emit the minimal extra
215 * dependencies, and to avoid having to deal with aligning its regs to 2.
217 const fs_builder ubld
= bld
.annotate("send dependency resolve")
220 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
224 fs_inst::equals(fs_inst
*inst
) const
226 return (opcode
== inst
->opcode
&&
227 dst
.equals(inst
->dst
) &&
228 src
[0].equals(inst
->src
[0]) &&
229 src
[1].equals(inst
->src
[1]) &&
230 src
[2].equals(inst
->src
[2]) &&
231 saturate
== inst
->saturate
&&
232 predicate
== inst
->predicate
&&
233 conditional_mod
== inst
->conditional_mod
&&
234 mlen
== inst
->mlen
&&
235 base_mrf
== inst
->base_mrf
&&
236 target
== inst
->target
&&
238 header_size
== inst
->header_size
&&
239 shadow_compare
== inst
->shadow_compare
&&
240 exec_size
== inst
->exec_size
&&
241 offset
== inst
->offset
);
245 fs_inst::overwrites_reg(const fs_reg
®
) const
247 return reg
.in_range(dst
, regs_written
);
251 fs_inst::is_send_from_grf() const
254 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
255 case SHADER_OPCODE_SHADER_TIME_ADD
:
256 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
257 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
258 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
259 case SHADER_OPCODE_UNTYPED_ATOMIC
:
260 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
261 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
262 case SHADER_OPCODE_TYPED_ATOMIC
:
263 case SHADER_OPCODE_TYPED_SURFACE_READ
:
264 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
265 case SHADER_OPCODE_URB_WRITE_SIMD8
:
266 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
267 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
268 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
269 case SHADER_OPCODE_URB_READ_SIMD8
:
270 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
272 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
273 return src
[1].file
== VGRF
;
274 case FS_OPCODE_FB_WRITE
:
275 return src
[0].file
== VGRF
;
278 return src
[0].file
== VGRF
;
285 * Returns true if this instruction's sources and destinations cannot
286 * safely be the same register.
288 * In most cases, a register can be written over safely by the same
289 * instruction that is its last use. For a single instruction, the
290 * sources are dereferenced before writing of the destination starts
293 * However, there are a few cases where this can be problematic:
295 * - Virtual opcodes that translate to multiple instructions in the
296 * code generator: if src == dst and one instruction writes the
297 * destination before a later instruction reads the source, then
298 * src will have been clobbered.
300 * - SIMD16 compressed instructions with certain regioning (see below).
302 * The register allocator uses this information to set up conflicts between
303 * GRF sources and the destination.
306 fs_inst::has_source_and_destination_hazard() const
309 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
310 /* Multiple partial writes to the destination */
313 /* The SIMD16 compressed instruction
315 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
317 * is actually decoded in hardware as:
319 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
320 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
322 * Which is safe. However, if we have uniform accesses
323 * happening, we get into trouble:
325 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
326 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
328 * Now our destination for the first instruction overwrote the
329 * second instruction's src0, and we get garbage for those 8
330 * pixels. There's a similar issue for the pre-gen6
331 * pixel_x/pixel_y, which are registers of 16-bit values and thus
332 * would get stomped by the first decode as well.
334 if (exec_size
== 16) {
335 for (int i
= 0; i
< sources
; i
++) {
336 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
337 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
338 src
[i
].type
== BRW_REGISTER_TYPE_W
||
339 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
340 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
350 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
352 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
355 fs_reg reg
= this->src
[0];
356 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
359 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
362 for (int i
= 0; i
< this->sources
; i
++) {
363 reg
.type
= this->src
[i
].type
;
364 if (!this->src
[i
].equals(reg
))
367 if (i
< this->header_size
) {
370 reg
= horiz_offset(reg
, this->exec_size
);
378 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
380 if (devinfo
->gen
== 6 && is_math())
383 if (is_send_from_grf())
386 if (!backend_instruction::can_do_source_mods())
393 fs_inst::can_change_types() const
395 return dst
.type
== src
[0].type
&&
396 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
397 (opcode
== BRW_OPCODE_MOV
||
398 (opcode
== BRW_OPCODE_SEL
&&
399 dst
.type
== src
[1].type
&&
400 predicate
!= BRW_PREDICATE_NONE
&&
401 !src
[1].abs
&& !src
[1].negate
));
405 fs_inst::has_side_effects() const
407 return this->eot
|| backend_instruction::has_side_effects();
413 memset(this, 0, sizeof(*this));
417 /** Generic unset register constructor. */
421 this->file
= BAD_FILE
;
424 fs_reg::fs_reg(struct ::brw_reg reg
) :
427 this->reg_offset
= 0;
428 this->subreg_offset
= 0;
430 if (this->file
== IMM
&&
431 (this->type
!= BRW_REGISTER_TYPE_V
&&
432 this->type
!= BRW_REGISTER_TYPE_UV
&&
433 this->type
!= BRW_REGISTER_TYPE_VF
)) {
439 fs_reg::equals(const fs_reg
&r
) const
441 return (this->backend_reg::equals(r
) &&
442 subreg_offset
== r
.subreg_offset
&&
447 fs_reg::set_smear(unsigned subreg
)
449 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
450 subreg_offset
= subreg
* type_sz(type
);
456 fs_reg::is_contiguous() const
462 fs_reg::component_size(unsigned width
) const
464 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
467 return MAX2(width
* stride
, 1) * type_sz(type
);
471 type_size_scalar(const struct glsl_type
*type
)
473 unsigned int size
, i
;
475 switch (type
->base_type
) {
478 case GLSL_TYPE_FLOAT
:
480 return type
->components();
481 case GLSL_TYPE_DOUBLE
:
482 return type
->components() * 2;
483 case GLSL_TYPE_ARRAY
:
484 return type_size_scalar(type
->fields
.array
) * type
->length
;
485 case GLSL_TYPE_STRUCT
:
487 for (i
= 0; i
< type
->length
; i
++) {
488 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
491 case GLSL_TYPE_SAMPLER
:
492 /* Samplers take up no register space, since they're baked in at
496 case GLSL_TYPE_ATOMIC_UINT
:
498 case GLSL_TYPE_SUBROUTINE
:
500 case GLSL_TYPE_IMAGE
:
501 return BRW_IMAGE_PARAM_SIZE
;
503 case GLSL_TYPE_ERROR
:
504 case GLSL_TYPE_INTERFACE
:
505 case GLSL_TYPE_FUNCTION
:
506 unreachable("not reached");
513 * Returns the number of scalar components needed to store type, assuming
514 * that vectors are padded out to vec4.
516 * This has the packing rules of type_size_vec4(), but counts components
517 * similar to type_size_scalar().
520 type_size_vec4_times_4(const struct glsl_type
*type
)
522 return 4 * type_size_vec4(type
);
525 /* Attribute arrays are loaded as one vec4 per element (or matrix column),
526 * except for double-precision types, which are loaded as one dvec4.
529 type_size_vs_input(const struct glsl_type
*type
)
531 if (type
->is_double()) {
532 return type_size_dvec4(type
);
534 return type_size_vec4(type
);
539 * Create a MOV to read the timestamp register.
541 * The caller is responsible for emitting the MOV. The return value is
542 * the destination of the MOV, with extra parameters set.
545 fs_visitor::get_timestamp(const fs_builder
&bld
)
547 assert(devinfo
->gen
>= 7);
549 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
552 BRW_REGISTER_TYPE_UD
));
554 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
556 /* We want to read the 3 fields we care about even if it's not enabled in
559 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
565 fs_visitor::emit_shader_time_begin()
567 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
569 /* We want only the low 32 bits of the timestamp. Since it's running
570 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
571 * which is plenty of time for our purposes. It is identical across the
572 * EUs, but since it's tracking GPU core speed it will increment at a
573 * varying rate as render P-states change.
575 shader_start_time
.set_smear(0);
579 fs_visitor::emit_shader_time_end()
581 /* Insert our code just before the final SEND with EOT. */
582 exec_node
*end
= this->instructions
.get_tail();
583 assert(end
&& ((fs_inst
*) end
)->eot
);
584 const fs_builder ibld
= bld
.annotate("shader time end")
585 .exec_all().at(NULL
, end
);
587 fs_reg shader_end_time
= get_timestamp(ibld
);
589 /* We only use the low 32 bits of the timestamp - see
590 * emit_shader_time_begin()).
592 * We could also check if render P-states have changed (or anything
593 * else that might disrupt timing) by setting smear to 2 and checking if
594 * that field is != 0.
596 shader_end_time
.set_smear(0);
598 /* Check that there weren't any timestamp reset events (assuming these
599 * were the only two timestamp reads that happened).
601 fs_reg reset
= shader_end_time
;
603 set_condmod(BRW_CONDITIONAL_Z
,
604 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
605 ibld
.IF(BRW_PREDICATE_NORMAL
);
607 fs_reg start
= shader_start_time
;
609 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
612 const fs_builder cbld
= ibld
.group(1, 0);
613 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
615 /* If there were no instructions between the two timestamp gets, the diff
616 * is 2 cycles. Remove that overhead, so I can forget about that when
617 * trying to determine the time taken for single instructions.
619 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
620 SHADER_TIME_ADD(cbld
, 0, diff
);
621 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
622 ibld
.emit(BRW_OPCODE_ELSE
);
623 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
624 ibld
.emit(BRW_OPCODE_ENDIF
);
628 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
629 int shader_time_subindex
,
632 int index
= shader_time_index
* 3 + shader_time_subindex
;
633 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
636 if (dispatch_width
== 8)
637 payload
= vgrf(glsl_type::uvec2_type
);
639 payload
= vgrf(glsl_type::uint_type
);
641 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
645 fs_visitor::vfail(const char *format
, va_list va
)
654 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
655 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
657 this->fail_msg
= msg
;
660 fprintf(stderr
, "%s", msg
);
665 fs_visitor::fail(const char *format
, ...)
669 va_start(va
, format
);
675 * Mark this program as impossible to compile with dispatch width greater
678 * During the SIMD8 compile (which happens first), we can detect and flag
679 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
680 * SIMD16+ compile altogether.
682 * During a compile of dispatch width greater than n (if one happens anyway),
683 * this just calls fail().
686 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
688 if (dispatch_width
> n
) {
691 max_dispatch_width
= n
;
692 compiler
->shader_perf_log(log_data
,
693 "Shader dispatch width limited to SIMD%d: %s",
699 * Returns true if the instruction has a flag that means it won't
700 * update an entire destination register.
702 * For example, dead code elimination and live variable analysis want to know
703 * when a write to a variable screens off any preceding values that were in
707 fs_inst::is_partial_write() const
709 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
710 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
711 !this->dst
.is_contiguous() ||
712 this->dst
.subreg_offset
> 0);
716 fs_inst::components_read(unsigned i
) const
718 /* Return zero if the source is not present. */
719 if (src
[i
].file
== BAD_FILE
)
723 case FS_OPCODE_LINTERP
:
729 case FS_OPCODE_PIXEL_X
:
730 case FS_OPCODE_PIXEL_Y
:
734 case FS_OPCODE_FB_WRITE_LOGICAL
:
735 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
736 /* First/second FB write color. */
738 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
742 case SHADER_OPCODE_TEX_LOGICAL
:
743 case SHADER_OPCODE_TXD_LOGICAL
:
744 case SHADER_OPCODE_TXF_LOGICAL
:
745 case SHADER_OPCODE_TXL_LOGICAL
:
746 case SHADER_OPCODE_TXS_LOGICAL
:
747 case FS_OPCODE_TXB_LOGICAL
:
748 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
749 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
750 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
751 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
752 case SHADER_OPCODE_LOD_LOGICAL
:
753 case SHADER_OPCODE_TG4_LOGICAL
:
754 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
755 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
756 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
757 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
758 /* Texture coordinates. */
759 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
760 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
761 /* Texture derivatives. */
762 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
763 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
764 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
765 /* Texture offset. */
766 else if (i
== TEX_LOGICAL_SRC_OFFSET_VALUE
)
769 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
774 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
775 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
776 assert(src
[3].file
== IMM
);
777 /* Surface coordinates. */
780 /* Surface operation source (ignored for reads). */
786 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
787 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
788 assert(src
[3].file
== IMM
&&
790 /* Surface coordinates. */
793 /* Surface operation source. */
799 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
800 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
801 assert(src
[3].file
== IMM
&&
803 const unsigned op
= src
[4].ud
;
804 /* Surface coordinates. */
807 /* Surface operation source. */
808 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
810 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
811 op
== BRW_AOP_PREDEC
))
823 fs_inst::regs_read(int arg
) const
826 case FS_OPCODE_FB_WRITE
:
827 case SHADER_OPCODE_URB_WRITE_SIMD8
:
828 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
829 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
830 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
831 case SHADER_OPCODE_URB_READ_SIMD8
:
832 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
833 case SHADER_OPCODE_UNTYPED_ATOMIC
:
834 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
835 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
836 case SHADER_OPCODE_TYPED_ATOMIC
:
837 case SHADER_OPCODE_TYPED_SURFACE_READ
:
838 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
839 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
844 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
845 /* The payload is actually stored in src1 */
850 case FS_OPCODE_LINTERP
:
855 case SHADER_OPCODE_LOAD_PAYLOAD
:
856 if (arg
< this->header_size
)
860 case CS_OPCODE_CS_TERMINATE
:
861 case SHADER_OPCODE_BARRIER
:
864 case SHADER_OPCODE_MOV_INDIRECT
:
866 assert(src
[2].file
== IMM
);
867 unsigned region_length
= src
[2].ud
;
869 if (src
[0].file
== UNIFORM
) {
870 assert(region_length
% 4 == 0);
871 return region_length
/ 4;
872 } else if (src
[0].file
== FIXED_GRF
) {
873 /* If the start of the region is not register aligned, then
874 * there's some portion of the register that's technically
875 * unread at the beginning.
877 * However, the register allocator works in terms of whole
878 * registers, and does not use subnr. It assumes that the
879 * read starts at the beginning of the register, and extends
880 * regs_read() whole registers beyond that.
882 * To compensate, we extend the region length to include this
883 * unread portion at the beginning.
886 region_length
+= src
[0].subnr
;
888 return DIV_ROUND_UP(region_length
, REG_SIZE
);
890 assert(!"Invalid register file");
896 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
901 switch (src
[arg
].file
) {
910 return DIV_ROUND_UP(components_read(arg
) *
911 src
[arg
].component_size(exec_size
),
914 unreachable("MRF registers are not allowed as sources");
920 /* Return the subset of flag registers that an instruction could
921 * potentially read or write based on the execution controls and flag
922 * subregister number of the instruction.
925 flag_mask(const fs_inst
*inst
)
927 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
928 const unsigned end
= start
+ inst
->exec_size
;
929 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
934 fs_inst::flags_read(const brw_device_info
*devinfo
) const
936 /* XXX - This doesn't consider explicit uses of the flag register as source
939 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
940 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
941 /* The vertical predication modes combine corresponding bits from
942 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
944 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
945 return flag_mask(this) << shift
| flag_mask(this);
946 } else if (predicate
) {
947 return flag_mask(this);
954 fs_inst::flags_written() const
956 /* XXX - This doesn't consider explicit uses of the flag register as
957 * destination region.
959 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
960 opcode
!= BRW_OPCODE_IF
&&
961 opcode
!= BRW_OPCODE_WHILE
)) ||
962 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
963 return flag_mask(this);
970 * Returns how many MRFs an FS opcode will write over.
972 * Note that this is not the 0 or 1 implied writes in an actual gen
973 * instruction -- the FS opcodes often generate MOVs in addition.
976 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
981 if (inst
->base_mrf
== -1)
984 switch (inst
->opcode
) {
985 case SHADER_OPCODE_RCP
:
986 case SHADER_OPCODE_RSQ
:
987 case SHADER_OPCODE_SQRT
:
988 case SHADER_OPCODE_EXP2
:
989 case SHADER_OPCODE_LOG2
:
990 case SHADER_OPCODE_SIN
:
991 case SHADER_OPCODE_COS
:
992 return 1 * dispatch_width
/ 8;
993 case SHADER_OPCODE_POW
:
994 case SHADER_OPCODE_INT_QUOTIENT
:
995 case SHADER_OPCODE_INT_REMAINDER
:
996 return 2 * dispatch_width
/ 8;
997 case SHADER_OPCODE_TEX
:
999 case SHADER_OPCODE_TXD
:
1000 case SHADER_OPCODE_TXF
:
1001 case SHADER_OPCODE_TXF_CMS
:
1002 case SHADER_OPCODE_TXF_MCS
:
1003 case SHADER_OPCODE_TG4
:
1004 case SHADER_OPCODE_TG4_OFFSET
:
1005 case SHADER_OPCODE_TXL
:
1006 case SHADER_OPCODE_TXS
:
1007 case SHADER_OPCODE_LOD
:
1008 case SHADER_OPCODE_SAMPLEINFO
:
1010 case FS_OPCODE_FB_WRITE
:
1012 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1013 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1015 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
1017 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1020 unreachable("not reached");
1025 fs_visitor::vgrf(const glsl_type
*const type
)
1027 int reg_width
= dispatch_width
/ 8;
1028 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
1029 brw_type_for_base_type(type
));
1032 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1037 this->type
= BRW_REGISTER_TYPE_F
;
1038 this->stride
= (file
== UNIFORM
? 0 : 1);
1041 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1047 this->stride
= (file
== UNIFORM
? 0 : 1);
1050 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1051 * This brings in those uniform definitions
1054 fs_visitor::import_uniforms(fs_visitor
*v
)
1056 this->push_constant_loc
= v
->push_constant_loc
;
1057 this->pull_constant_loc
= v
->pull_constant_loc
;
1058 this->uniforms
= v
->uniforms
;
1062 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1064 assert(stage
== MESA_SHADER_FRAGMENT
);
1066 /* gl_FragCoord.x */
1067 bld
.MOV(wpos
, this->pixel_x
);
1068 wpos
= offset(wpos
, bld
, 1);
1070 /* gl_FragCoord.y */
1071 bld
.MOV(wpos
, this->pixel_y
);
1072 wpos
= offset(wpos
, bld
, 1);
1074 /* gl_FragCoord.z */
1075 if (devinfo
->gen
>= 6) {
1076 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1078 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1079 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1080 interp_reg(VARYING_SLOT_POS
, 2));
1082 wpos
= offset(wpos
, bld
, 1);
1084 /* gl_FragCoord.w: Already set up in emit_interpolation */
1085 bld
.MOV(wpos
, this->wpos_w
);
1088 enum brw_barycentric_mode
1089 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1091 /* Barycentric modes don't make sense for flat inputs. */
1092 assert(mode
!= INTERP_MODE_FLAT
);
1096 case nir_intrinsic_load_barycentric_pixel
:
1097 case nir_intrinsic_load_barycentric_at_offset
:
1098 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1100 case nir_intrinsic_load_barycentric_centroid
:
1101 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1103 case nir_intrinsic_load_barycentric_sample
:
1104 case nir_intrinsic_load_barycentric_at_sample
:
1105 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1108 unreachable("invalid intrinsic");
1111 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1114 return (enum brw_barycentric_mode
) bary
;
1118 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1120 static enum brw_barycentric_mode
1121 centroid_to_pixel(enum brw_barycentric_mode bary
)
1123 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1124 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1125 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1129 fs_visitor::emit_frontfacing_interpolation()
1131 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1133 if (devinfo
->gen
>= 6) {
1134 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1135 * a boolean result from this (~0/true or 0/false).
1137 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1138 * this task in only one instruction:
1139 * - a negation source modifier will flip the bit; and
1140 * - a W -> D type conversion will sign extend the bit into the high
1141 * word of the destination.
1143 * An ASR 15 fills the low word of the destination.
1145 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1148 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1150 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1151 * a boolean result from this (1/true or 0/false).
1153 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1154 * the negation source modifier to flip it. Unfortunately the SHR
1155 * instruction only operates on UD (or D with an abs source modifier)
1156 * sources without negation.
1158 * Instead, use ASR (which will give ~0/true or 0/false).
1160 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1163 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1170 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1172 assert(stage
== MESA_SHADER_FRAGMENT
);
1173 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1174 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1176 if (wm_prog_data
->persample_dispatch
) {
1177 /* Convert int_sample_pos to floating point */
1178 bld
.MOV(dst
, int_sample_pos
);
1179 /* Scale to the range [0, 1] */
1180 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1183 /* From ARB_sample_shading specification:
1184 * "When rendering to a non-multisample buffer, or if multisample
1185 * rasterization is disabled, gl_SamplePosition will always be
1188 bld
.MOV(dst
, brw_imm_f(0.5f
));
1193 fs_visitor::emit_samplepos_setup()
1195 assert(devinfo
->gen
>= 6);
1197 const fs_builder abld
= bld
.annotate("compute sample position");
1198 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1200 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1201 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1203 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1204 * mode will be enabled.
1206 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1207 * R31.1:0 Position Offset X/Y for Slot[3:0]
1208 * R31.3:2 Position Offset X/Y for Slot[7:4]
1211 * The X, Y sample positions come in as bytes in thread payload. So, read
1212 * the positions using vstride=16, width=8, hstride=2.
1214 struct brw_reg sample_pos_reg
=
1215 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1216 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1218 if (dispatch_width
== 8) {
1219 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1221 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1222 abld
.half(1).MOV(half(int_sample_x
, 1),
1223 fs_reg(suboffset(sample_pos_reg
, 16)));
1225 /* Compute gl_SamplePosition.x */
1226 compute_sample_position(pos
, int_sample_x
);
1227 pos
= offset(pos
, abld
, 1);
1228 if (dispatch_width
== 8) {
1229 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1231 abld
.half(0).MOV(half(int_sample_y
, 0),
1232 fs_reg(suboffset(sample_pos_reg
, 1)));
1233 abld
.half(1).MOV(half(int_sample_y
, 1),
1234 fs_reg(suboffset(sample_pos_reg
, 17)));
1236 /* Compute gl_SamplePosition.y */
1237 compute_sample_position(pos
, int_sample_y
);
1242 fs_visitor::emit_sampleid_setup()
1244 assert(stage
== MESA_SHADER_FRAGMENT
);
1245 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1246 assert(devinfo
->gen
>= 6);
1248 const fs_builder abld
= bld
.annotate("compute sample id");
1249 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1251 if (!key
->multisample_fbo
) {
1252 /* As per GL_ARB_sample_shading specification:
1253 * "When rendering to a non-multisample buffer, or if multisample
1254 * rasterization is disabled, gl_SampleID will always be zero."
1256 abld
.MOV(*reg
, brw_imm_d(0));
1257 } else if (devinfo
->gen
>= 8) {
1258 /* Sample ID comes in as 4-bit numbers in g1.0:
1260 * 15:12 Slot 3 SampleID (only used in SIMD16)
1261 * 11:8 Slot 2 SampleID (only used in SIMD16)
1262 * 7:4 Slot 1 SampleID
1263 * 3:0 Slot 0 SampleID
1265 * Each slot corresponds to four channels, so we want to replicate each
1266 * half-byte value to 4 channels in a row:
1268 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1269 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1271 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1272 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1274 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1275 * channels to read the first byte (7:0), and the second group of 8
1276 * channels to read the second byte (15:8). Then, we shift right by
1277 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1278 * values into place. Finally, we AND with 0xf to keep the low nibble.
1280 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1281 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1283 * TODO: These payload bits exist on Gen7 too, but they appear to always
1284 * be zero, so this code fails to work. We should find out why.
1286 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1288 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1289 BRW_REGISTER_TYPE_B
), 1, 8, 0)),
1290 brw_imm_v(0x44440000));
1291 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1293 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1295 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1297 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1298 * 8x multisampling, subspan 0 will represent sample N (where N
1299 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1300 * 7. We can find the value of N by looking at R0.0 bits 7:6
1301 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1302 * (since samples are always delivered in pairs). That is, we
1303 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1304 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1305 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1306 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1307 * populating a temporary variable with the sequence (0, 1, 2, 3),
1308 * and then reading from it using vstride=1, width=4, hstride=0.
1309 * These computations hold good for 4x multisampling as well.
1311 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1312 * the first four slots are sample 0 of subspan 0; the next four
1313 * are sample 1 of subspan 0; the third group is sample 0 of
1314 * subspan 1, and finally sample 1 of subspan 1.
1317 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1318 * accomodate 16x MSAA.
1320 abld
.exec_all().group(1, 0)
1321 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1323 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1325 /* This works for both SIMD8 and SIMD16 */
1326 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1328 /* This special instruction takes care of setting vstride=1,
1329 * width=4, hstride=0 of t2 during an ADD instruction.
1331 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1338 fs_visitor::emit_samplemaskin_setup()
1340 assert(stage
== MESA_SHADER_FRAGMENT
);
1341 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1342 assert(devinfo
->gen
>= 6);
1344 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1346 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1347 BRW_REGISTER_TYPE_D
));
1349 if (wm_prog_data
->persample_dispatch
) {
1350 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1351 * and a mask representing which sample is being processed by the
1352 * current shader invocation.
1354 * From the OES_sample_variables specification:
1355 * "When per-sample shading is active due to the use of a fragment input
1356 * qualified by "sample" or due to the use of the gl_SampleID or
1357 * gl_SamplePosition variables, only the bit for the current sample is
1358 * set in gl_SampleMaskIn."
1360 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1362 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1363 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1365 fs_reg one
= vgrf(glsl_type::int_type
);
1366 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1367 abld
.MOV(one
, brw_imm_d(1));
1368 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1369 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1371 /* In per-pixel mode, the coverage mask is sufficient. */
1372 *reg
= coverage_mask
;
1378 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1380 if (!src
.abs
&& !src
.negate
)
1383 fs_reg temp
= bld
.vgrf(src
.type
);
1390 fs_visitor::emit_discard_jump()
1392 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1394 /* For performance, after a discard, jump to the end of the
1395 * shader if all relevant channels have been discarded.
1397 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1398 discard_jump
->flag_subreg
= 1;
1400 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1401 discard_jump
->predicate_inverse
= true;
1405 fs_visitor::emit_gs_thread_end()
1407 assert(stage
== MESA_SHADER_GEOMETRY
);
1409 struct brw_gs_prog_data
*gs_prog_data
=
1410 (struct brw_gs_prog_data
*) prog_data
;
1412 if (gs_compile
->control_data_header_size_bits
> 0) {
1413 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1416 const fs_builder abld
= bld
.annotate("thread end");
1419 if (gs_prog_data
->static_vertex_count
!= -1) {
1420 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1421 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1422 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1423 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1424 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1427 /* Delete now dead instructions. */
1428 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1434 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1438 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1439 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1440 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1443 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1444 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1445 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1446 sources
[1] = this->final_gs_vertex_count
;
1447 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1448 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1456 fs_visitor::assign_curb_setup()
1458 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1460 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1461 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1462 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1463 if (inst
->src
[i
].file
== UNIFORM
) {
1464 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1466 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1467 constant_nr
= push_constant_loc
[uniform_nr
];
1469 /* Section 5.11 of the OpenGL 4.1 spec says:
1470 * "Out-of-bounds reads return undefined values, which include
1471 * values from other variables of the active program or zero."
1472 * Just return the first push constant.
1477 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1480 brw_reg
.abs
= inst
->src
[i
].abs
;
1481 brw_reg
.negate
= inst
->src
[i
].negate
;
1483 assert(inst
->src
[i
].stride
== 0);
1484 inst
->src
[i
] = byte_offset(
1485 retype(brw_reg
, inst
->src
[i
].type
),
1486 inst
->src
[i
].subreg_offset
);
1491 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1492 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1496 fs_visitor::calculate_urb_setup()
1498 assert(stage
== MESA_SHADER_FRAGMENT
);
1499 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1500 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1502 memset(prog_data
->urb_setup
, -1,
1503 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1506 /* Figure out where each of the incoming setup attributes lands. */
1507 if (devinfo
->gen
>= 6) {
1508 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1509 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1510 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1511 * first 16 varying inputs, so we can put them wherever we want.
1512 * Just put them in order.
1514 * This is useful because it means that (a) inputs not used by the
1515 * fragment shader won't take up valuable register space, and (b) we
1516 * won't have to recompile the fragment shader if it gets paired with
1517 * a different vertex (or geometry) shader.
1519 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1520 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1521 BITFIELD64_BIT(i
)) {
1522 prog_data
->urb_setup
[i
] = urb_next
++;
1526 bool include_vue_header
=
1527 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1529 /* We have enough input varyings that the SF/SBE pipeline stage can't
1530 * arbitrarily rearrange them to suit our whim; we have to put them
1531 * in an order that matches the output of the previous pipeline stage
1532 * (geometry or vertex shader).
1534 struct brw_vue_map prev_stage_vue_map
;
1535 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1536 key
->input_slots_valid
,
1537 nir
->info
.separate_shader
);
1539 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1541 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1542 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1544 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1545 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1546 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1547 BITFIELD64_BIT(varying
))) {
1548 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1551 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1554 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1555 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1556 /* Point size is packed into the header, not as a general attribute */
1557 if (i
== VARYING_SLOT_PSIZ
)
1560 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1561 /* The back color slot is skipped when the front color is
1562 * also written to. In addition, some slots can be
1563 * written in the vertex shader and not read in the
1564 * fragment shader. So the register number must always be
1565 * incremented, mapped or not.
1567 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1568 prog_data
->urb_setup
[i
] = urb_next
;
1574 * It's a FS only attribute, and we did interpolation for this attribute
1575 * in SF thread. So, count it here, too.
1577 * See compile_sf_prog() for more info.
1579 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1580 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1583 prog_data
->num_varying_inputs
= urb_next
;
1587 fs_visitor::assign_urb_setup()
1589 assert(stage
== MESA_SHADER_FRAGMENT
);
1590 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1592 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1594 /* Offset all the urb_setup[] index by the actual position of the
1595 * setup regs, now that the location of the constants has been chosen.
1597 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1598 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1599 assert(inst
->src
[1].file
== FIXED_GRF
);
1600 inst
->src
[1].nr
+= urb_start
;
1603 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1604 assert(inst
->src
[0].file
== FIXED_GRF
);
1605 inst
->src
[0].nr
+= urb_start
;
1609 /* Each attribute is 4 setup channels, each of which is half a reg. */
1610 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1614 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1616 for (int i
= 0; i
< inst
->sources
; i
++) {
1617 if (inst
->src
[i
].file
== ATTR
) {
1618 int grf
= payload
.num_regs
+
1619 prog_data
->curb_read_length
+
1621 inst
->src
[i
].reg_offset
;
1623 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1625 * VertStride must be used to cross GRF register boundaries. This
1626 * rule implies that elements within a 'Width' cannot cross GRF
1629 * So, for registers that are large enough, we have to split the exec
1630 * size in two and trust the compression state to sort it out.
1632 unsigned total_size
= inst
->exec_size
*
1633 inst
->src
[i
].stride
*
1634 type_sz(inst
->src
[i
].type
);
1636 assert(total_size
<= 2 * REG_SIZE
);
1637 const unsigned exec_size
=
1638 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1640 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1641 struct brw_reg reg
=
1642 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1643 inst
->src
[i
].subreg_offset
),
1644 exec_size
* inst
->src
[i
].stride
,
1645 width
, inst
->src
[i
].stride
);
1646 reg
.abs
= inst
->src
[i
].abs
;
1647 reg
.negate
= inst
->src
[i
].negate
;
1655 fs_visitor::assign_vs_urb_setup()
1657 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1659 assert(stage
== MESA_SHADER_VERTEX
);
1661 /* Each attribute is 4 regs. */
1662 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1664 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1666 /* Rewrite all ATTR file references to the hw grf that they land in. */
1667 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1668 convert_attr_sources_to_hw_regs(inst
);
1673 fs_visitor::assign_tcs_single_patch_urb_setup()
1675 assert(stage
== MESA_SHADER_TESS_CTRL
);
1677 /* Rewrite all ATTR file references to HW_REGs. */
1678 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1679 convert_attr_sources_to_hw_regs(inst
);
1684 fs_visitor::assign_tes_urb_setup()
1686 assert(stage
== MESA_SHADER_TESS_EVAL
);
1688 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1690 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1692 /* Rewrite all ATTR file references to HW_REGs. */
1693 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1694 convert_attr_sources_to_hw_regs(inst
);
1699 fs_visitor::assign_gs_urb_setup()
1701 assert(stage
== MESA_SHADER_GEOMETRY
);
1703 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1705 first_non_payload_grf
+=
1706 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1708 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1709 /* Rewrite all ATTR file references to GRFs. */
1710 convert_attr_sources_to_hw_regs(inst
);
1716 * Split large virtual GRFs into separate components if we can.
1718 * This is mostly duplicated with what brw_fs_vector_splitting does,
1719 * but that's really conservative because it's afraid of doing
1720 * splitting that doesn't result in real progress after the rest of
1721 * the optimization phases, which would cause infinite looping in
1722 * optimization. We can do it once here, safely. This also has the
1723 * opportunity to split interpolated values, or maybe even uniforms,
1724 * which we don't have at the IR level.
1726 * We want to split, because virtual GRFs are what we register
1727 * allocate and spill (due to contiguousness requirements for some
1728 * instructions), and they're what we naturally generate in the
1729 * codegen process, but most virtual GRFs don't actually need to be
1730 * contiguous sets of GRFs. If we split, we'll end up with reduced
1731 * live intervals and better dead code elimination and coalescing.
1734 fs_visitor::split_virtual_grfs()
1736 int num_vars
= this->alloc
.count
;
1738 /* Count the total number of registers */
1740 int vgrf_to_reg
[num_vars
];
1741 for (int i
= 0; i
< num_vars
; i
++) {
1742 vgrf_to_reg
[i
] = reg_count
;
1743 reg_count
+= alloc
.sizes
[i
];
1746 /* An array of "split points". For each register slot, this indicates
1747 * if this slot can be separated from the previous slot. Every time an
1748 * instruction uses multiple elements of a register (as a source or
1749 * destination), we mark the used slots as inseparable. Then we go
1750 * through and split the registers into the smallest pieces we can.
1752 bool split_points
[reg_count
];
1753 memset(split_points
, 0, sizeof(split_points
));
1755 /* Mark all used registers as fully splittable */
1756 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1757 if (inst
->dst
.file
== VGRF
) {
1758 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1759 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1760 split_points
[reg
+ j
] = true;
1763 for (int i
= 0; i
< inst
->sources
; i
++) {
1764 if (inst
->src
[i
].file
== VGRF
) {
1765 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1766 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1767 split_points
[reg
+ j
] = true;
1772 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1773 if (inst
->dst
.file
== VGRF
) {
1774 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1775 for (int j
= 1; j
< inst
->regs_written
; j
++)
1776 split_points
[reg
+ j
] = false;
1778 for (int i
= 0; i
< inst
->sources
; i
++) {
1779 if (inst
->src
[i
].file
== VGRF
) {
1780 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1781 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1782 split_points
[reg
+ j
] = false;
1787 int new_virtual_grf
[reg_count
];
1788 int new_reg_offset
[reg_count
];
1791 for (int i
= 0; i
< num_vars
; i
++) {
1792 /* The first one should always be 0 as a quick sanity check. */
1793 assert(split_points
[reg
] == false);
1796 new_reg_offset
[reg
] = 0;
1801 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1802 /* If this is a split point, reset the offset to 0 and allocate a
1803 * new virtual GRF for the previous offset many registers
1805 if (split_points
[reg
]) {
1806 assert(offset
<= MAX_VGRF_SIZE
);
1807 int grf
= alloc
.allocate(offset
);
1808 for (int k
= reg
- offset
; k
< reg
; k
++)
1809 new_virtual_grf
[k
] = grf
;
1812 new_reg_offset
[reg
] = offset
;
1817 /* The last one gets the original register number */
1818 assert(offset
<= MAX_VGRF_SIZE
);
1819 alloc
.sizes
[i
] = offset
;
1820 for (int k
= reg
- offset
; k
< reg
; k
++)
1821 new_virtual_grf
[k
] = i
;
1823 assert(reg
== reg_count
);
1825 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1826 if (inst
->dst
.file
== VGRF
) {
1827 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1828 inst
->dst
.nr
= new_virtual_grf
[reg
];
1829 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1830 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1832 for (int i
= 0; i
< inst
->sources
; i
++) {
1833 if (inst
->src
[i
].file
== VGRF
) {
1834 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1835 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1836 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1837 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1841 invalidate_live_intervals();
1845 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1847 * During code generation, we create tons of temporary variables, many of
1848 * which get immediately killed and are never used again. Yet, in later
1849 * optimization and analysis passes, such as compute_live_intervals, we need
1850 * to loop over all the virtual GRFs. Compacting them can save a lot of
1854 fs_visitor::compact_virtual_grfs()
1856 bool progress
= false;
1857 int remap_table
[this->alloc
.count
];
1858 memset(remap_table
, -1, sizeof(remap_table
));
1860 /* Mark which virtual GRFs are used. */
1861 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1862 if (inst
->dst
.file
== VGRF
)
1863 remap_table
[inst
->dst
.nr
] = 0;
1865 for (int i
= 0; i
< inst
->sources
; i
++) {
1866 if (inst
->src
[i
].file
== VGRF
)
1867 remap_table
[inst
->src
[i
].nr
] = 0;
1871 /* Compact the GRF arrays. */
1873 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1874 if (remap_table
[i
] == -1) {
1875 /* We just found an unused register. This means that we are
1876 * actually going to compact something.
1880 remap_table
[i
] = new_index
;
1881 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1882 invalidate_live_intervals();
1887 this->alloc
.count
= new_index
;
1889 /* Patch all the instructions to use the newly renumbered registers */
1890 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1891 if (inst
->dst
.file
== VGRF
)
1892 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1894 for (int i
= 0; i
< inst
->sources
; i
++) {
1895 if (inst
->src
[i
].file
== VGRF
)
1896 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1900 /* Patch all the references to delta_xy, since they're used in register
1901 * allocation. If they're unused, switch them to BAD_FILE so we don't
1902 * think some random VGRF is delta_xy.
1904 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1905 if (delta_xy
[i
].file
== VGRF
) {
1906 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1907 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1909 delta_xy
[i
].file
= BAD_FILE
;
1918 set_push_pull_constant_loc(unsigned uniform
, int *chunk_start
, bool contiguous
,
1919 int *push_constant_loc
, int *pull_constant_loc
,
1920 unsigned *num_push_constants
,
1921 unsigned *num_pull_constants
,
1922 const unsigned max_push_components
,
1923 const unsigned max_chunk_size
,
1924 struct brw_stage_prog_data
*stage_prog_data
)
1926 /* This is the first live uniform in the chunk */
1927 if (*chunk_start
< 0)
1928 *chunk_start
= uniform
;
1930 /* If this element does not need to be contiguous with the next, we
1931 * split at this point and everything between chunk_start and u forms a
1935 unsigned chunk_size
= uniform
- *chunk_start
+ 1;
1937 /* Decide whether we should push or pull this parameter. In the
1938 * Vulkan driver, push constants are explicitly exposed via the API
1939 * so we push everything. In GL, we only push small arrays.
1941 if (stage_prog_data
->pull_param
== NULL
||
1942 (*num_push_constants
+ chunk_size
<= max_push_components
&&
1943 chunk_size
<= max_chunk_size
)) {
1944 assert(*num_push_constants
+ chunk_size
<= max_push_components
);
1945 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1946 push_constant_loc
[j
] = (*num_push_constants
)++;
1948 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1949 pull_constant_loc
[j
] = (*num_pull_constants
)++;
1957 * Assign UNIFORM file registers to either push constants or pull constants.
1959 * We allow a fragment shader to have more than the specified minimum
1960 * maximum number of fragment shader uniform components (64). If
1961 * there are too many of these, they'd fill up all of register space.
1962 * So, this will push some of them out to the pull constant buffer and
1963 * update the program to load them.
1966 fs_visitor::assign_constant_locations()
1968 /* Only the first compile gets to decide on locations. */
1969 if (dispatch_width
!= min_dispatch_width
)
1972 bool is_live
[uniforms
];
1973 memset(is_live
, 0, sizeof(is_live
));
1974 bool is_live_64bit
[uniforms
];
1975 memset(is_live_64bit
, 0, sizeof(is_live_64bit
));
1977 /* For each uniform slot, a value of true indicates that the given slot and
1978 * the next slot must remain contiguous. This is used to keep us from
1979 * splitting arrays apart.
1981 bool contiguous
[uniforms
];
1982 memset(contiguous
, 0, sizeof(contiguous
));
1984 int thread_local_id_index
=
1985 (stage
== MESA_SHADER_COMPUTE
) ?
1986 ((brw_cs_prog_data
*)stage_prog_data
)->thread_local_id_index
: -1;
1988 /* First, we walk through the instructions and do two things:
1990 * 1) Figure out which uniforms are live.
1992 * 2) Mark any indirectly used ranges of registers as contiguous.
1994 * Note that we don't move constant-indexed accesses to arrays. No
1995 * testing has been done of the performance impact of this choice.
1997 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1998 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1999 if (inst
->src
[i
].file
!= UNIFORM
)
2002 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2004 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2005 assert(inst
->src
[2].ud
% 4 == 0);
2006 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
2007 assert(last
< uniforms
);
2009 for (unsigned j
= constant_nr
; j
< last
; j
++) {
2011 contiguous
[j
] = true;
2012 if (type_sz(inst
->src
[i
].type
) == 8) {
2013 is_live_64bit
[j
] = true;
2016 is_live
[last
] = true;
2018 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
) {
2019 int regs_read
= inst
->components_read(i
) *
2020 type_sz(inst
->src
[i
].type
) / 4;
2021 for (int j
= 0; j
< regs_read
; j
++) {
2022 is_live
[constant_nr
+ j
] = true;
2023 if (type_sz(inst
->src
[i
].type
) == 8) {
2024 is_live_64bit
[constant_nr
+ j
] = true;
2032 if (thread_local_id_index
>= 0 && !is_live
[thread_local_id_index
])
2033 thread_local_id_index
= -1;
2035 /* Only allow 16 registers (128 uniform components) as push constants.
2037 * Just demote the end of the list. We could probably do better
2038 * here, demoting things that are rarely used in the program first.
2040 * If changing this value, note the limitation about total_regs in
2043 unsigned int max_push_components
= 16 * 8;
2044 if (thread_local_id_index
>= 0)
2045 max_push_components
--; /* Save a slot for the thread ID */
2047 /* We push small arrays, but no bigger than 16 floats. This is big enough
2048 * for a vec4 but hopefully not large enough to push out other stuff. We
2049 * should probably use a better heuristic at some point.
2051 const unsigned int max_chunk_size
= 16;
2053 unsigned int num_push_constants
= 0;
2054 unsigned int num_pull_constants
= 0;
2056 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2057 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2059 /* Default to -1 meaning no location */
2060 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2061 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2063 int chunk_start
= -1;
2065 /* First push 64-bit uniforms to ensure they are properly aligned */
2066 for (unsigned u
= 0; u
< uniforms
; u
++) {
2067 if (!is_live
[u
] || !is_live_64bit
[u
])
2070 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2071 push_constant_loc
, pull_constant_loc
,
2072 &num_push_constants
, &num_pull_constants
,
2073 max_push_components
, max_chunk_size
,
2078 /* Then push the rest of uniforms */
2079 for (unsigned u
= 0; u
< uniforms
; u
++) {
2080 if (!is_live
[u
] || is_live_64bit
[u
])
2083 /* Skip thread_local_id_index to put it in the last push register. */
2084 if (thread_local_id_index
== (int)u
)
2087 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2088 push_constant_loc
, pull_constant_loc
,
2089 &num_push_constants
, &num_pull_constants
,
2090 max_push_components
, max_chunk_size
,
2094 /* Add the CS local thread ID uniform at the end of the push constants */
2095 if (thread_local_id_index
>= 0)
2096 push_constant_loc
[thread_local_id_index
] = num_push_constants
++;
2098 /* As the uniforms are going to be reordered, take the data from a temporary
2099 * copy of the original param[].
2101 gl_constant_value
**param
= ralloc_array(NULL
, gl_constant_value
*,
2102 stage_prog_data
->nr_params
);
2103 memcpy(param
, stage_prog_data
->param
,
2104 sizeof(gl_constant_value
*) * stage_prog_data
->nr_params
);
2105 stage_prog_data
->nr_params
= num_push_constants
;
2106 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2108 /* Up until now, the param[] array has been indexed by reg + reg_offset
2109 * of UNIFORM registers. Move pull constants into pull_param[] and
2110 * condense param[] to only contain the uniforms we chose to push.
2112 * NOTE: Because we are condensing the params[] array, we know that
2113 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2114 * having to make a copy.
2116 int new_thread_local_id_index
= -1;
2117 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2118 const gl_constant_value
*value
= param
[i
];
2120 if (pull_constant_loc
[i
] != -1) {
2121 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2122 } else if (push_constant_loc
[i
] != -1) {
2123 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2124 if (thread_local_id_index
== (int)i
)
2125 new_thread_local_id_index
= push_constant_loc
[i
];
2130 if (stage
== MESA_SHADER_COMPUTE
)
2131 ((brw_cs_prog_data
*)stage_prog_data
)->thread_local_id_index
=
2132 new_thread_local_id_index
;
2136 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2137 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2140 fs_visitor::lower_constant_loads()
2142 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2144 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2145 /* Set up the annotation tracking for new generated instructions. */
2146 const fs_builder
ibld(this, block
, inst
);
2148 for (int i
= 0; i
< inst
->sources
; i
++) {
2149 if (inst
->src
[i
].file
!= UNIFORM
)
2152 /* We'll handle this case later */
2153 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2156 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2157 if (location
>= uniforms
)
2158 continue; /* Out of bounds access */
2160 int pull_index
= pull_constant_loc
[location
];
2162 if (pull_index
== -1)
2165 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2168 if (type_sz(inst
->src
[i
].type
) <= 4)
2169 dst
= vgrf(glsl_type::float_type
);
2171 dst
= vgrf(glsl_type::double_type
);
2173 assert(inst
->src
[i
].stride
== 0);
2175 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2176 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2177 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2178 dst
, brw_imm_ud(index
), offset
);
2180 /* Rewrite the instruction to use the temporary VGRF. */
2181 inst
->src
[i
].file
= VGRF
;
2182 inst
->src
[i
].nr
= dst
.nr
;
2183 inst
->src
[i
].reg_offset
= 0;
2184 inst
->src
[i
].set_smear((pull_index
& 3) * 4 /
2185 type_sz(inst
->src
[i
].type
));
2187 brw_mark_surface_used(prog_data
, index
);
2190 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2191 inst
->src
[0].file
== UNIFORM
) {
2193 unsigned location
= inst
->src
[0].nr
+ inst
->src
[0].reg_offset
;
2194 if (location
>= uniforms
)
2195 continue; /* Out of bounds access */
2197 int pull_index
= pull_constant_loc
[location
];
2199 if (pull_index
== -1)
2202 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2206 inst
->remove(block
);
2208 brw_mark_surface_used(prog_data
, index
);
2211 invalidate_live_intervals();
2215 fs_visitor::opt_algebraic()
2217 bool progress
= false;
2219 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2220 switch (inst
->opcode
) {
2221 case BRW_OPCODE_MOV
:
2222 if (inst
->src
[0].file
!= IMM
)
2225 if (inst
->saturate
) {
2226 if (inst
->dst
.type
!= inst
->src
[0].type
)
2227 assert(!"unimplemented: saturate mixed types");
2229 if (brw_saturate_immediate(inst
->dst
.type
,
2230 &inst
->src
[0].as_brw_reg())) {
2231 inst
->saturate
= false;
2237 case BRW_OPCODE_MUL
:
2238 if (inst
->src
[1].file
!= IMM
)
2242 if (inst
->src
[1].is_one()) {
2243 inst
->opcode
= BRW_OPCODE_MOV
;
2244 inst
->src
[1] = reg_undef
;
2250 if (inst
->src
[1].is_negative_one()) {
2251 inst
->opcode
= BRW_OPCODE_MOV
;
2252 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2253 inst
->src
[1] = reg_undef
;
2259 if (inst
->src
[1].is_zero()) {
2260 inst
->opcode
= BRW_OPCODE_MOV
;
2261 inst
->src
[0] = inst
->src
[1];
2262 inst
->src
[1] = reg_undef
;
2267 if (inst
->src
[0].file
== IMM
) {
2268 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2269 inst
->opcode
= BRW_OPCODE_MOV
;
2270 inst
->src
[0].f
*= inst
->src
[1].f
;
2271 inst
->src
[1] = reg_undef
;
2276 case BRW_OPCODE_ADD
:
2277 if (inst
->src
[1].file
!= IMM
)
2281 if (inst
->src
[1].is_zero()) {
2282 inst
->opcode
= BRW_OPCODE_MOV
;
2283 inst
->src
[1] = reg_undef
;
2288 if (inst
->src
[0].file
== IMM
) {
2289 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2290 inst
->opcode
= BRW_OPCODE_MOV
;
2291 inst
->src
[0].f
+= inst
->src
[1].f
;
2292 inst
->src
[1] = reg_undef
;
2298 if (inst
->src
[0].equals(inst
->src
[1])) {
2299 inst
->opcode
= BRW_OPCODE_MOV
;
2300 inst
->src
[1] = reg_undef
;
2305 case BRW_OPCODE_LRP
:
2306 if (inst
->src
[1].equals(inst
->src
[2])) {
2307 inst
->opcode
= BRW_OPCODE_MOV
;
2308 inst
->src
[0] = inst
->src
[1];
2309 inst
->src
[1] = reg_undef
;
2310 inst
->src
[2] = reg_undef
;
2315 case BRW_OPCODE_CMP
:
2316 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2318 inst
->src
[0].negate
&&
2319 inst
->src
[1].is_zero()) {
2320 inst
->src
[0].abs
= false;
2321 inst
->src
[0].negate
= false;
2322 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2327 case BRW_OPCODE_SEL
:
2328 if (inst
->src
[0].equals(inst
->src
[1])) {
2329 inst
->opcode
= BRW_OPCODE_MOV
;
2330 inst
->src
[1] = reg_undef
;
2331 inst
->predicate
= BRW_PREDICATE_NONE
;
2332 inst
->predicate_inverse
= false;
2334 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2335 switch (inst
->conditional_mod
) {
2336 case BRW_CONDITIONAL_LE
:
2337 case BRW_CONDITIONAL_L
:
2338 switch (inst
->src
[1].type
) {
2339 case BRW_REGISTER_TYPE_F
:
2340 if (inst
->src
[1].f
>= 1.0f
) {
2341 inst
->opcode
= BRW_OPCODE_MOV
;
2342 inst
->src
[1] = reg_undef
;
2343 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2351 case BRW_CONDITIONAL_GE
:
2352 case BRW_CONDITIONAL_G
:
2353 switch (inst
->src
[1].type
) {
2354 case BRW_REGISTER_TYPE_F
:
2355 if (inst
->src
[1].f
<= 0.0f
) {
2356 inst
->opcode
= BRW_OPCODE_MOV
;
2357 inst
->src
[1] = reg_undef
;
2358 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2370 case BRW_OPCODE_MAD
:
2371 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2372 inst
->opcode
= BRW_OPCODE_MOV
;
2373 inst
->src
[1] = reg_undef
;
2374 inst
->src
[2] = reg_undef
;
2376 } else if (inst
->src
[0].is_zero()) {
2377 inst
->opcode
= BRW_OPCODE_MUL
;
2378 inst
->src
[0] = inst
->src
[2];
2379 inst
->src
[2] = reg_undef
;
2381 } else if (inst
->src
[1].is_one()) {
2382 inst
->opcode
= BRW_OPCODE_ADD
;
2383 inst
->src
[1] = inst
->src
[2];
2384 inst
->src
[2] = reg_undef
;
2386 } else if (inst
->src
[2].is_one()) {
2387 inst
->opcode
= BRW_OPCODE_ADD
;
2388 inst
->src
[2] = reg_undef
;
2390 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2391 inst
->opcode
= BRW_OPCODE_ADD
;
2392 inst
->src
[1].f
*= inst
->src
[2].f
;
2393 inst
->src
[2] = reg_undef
;
2397 case SHADER_OPCODE_BROADCAST
:
2398 if (is_uniform(inst
->src
[0])) {
2399 inst
->opcode
= BRW_OPCODE_MOV
;
2401 inst
->force_writemask_all
= true;
2403 } else if (inst
->src
[1].file
== IMM
) {
2404 inst
->opcode
= BRW_OPCODE_MOV
;
2405 inst
->src
[0] = component(inst
->src
[0],
2408 inst
->force_writemask_all
= true;
2417 /* Swap if src[0] is immediate. */
2418 if (progress
&& inst
->is_commutative()) {
2419 if (inst
->src
[0].file
== IMM
) {
2420 fs_reg tmp
= inst
->src
[1];
2421 inst
->src
[1] = inst
->src
[0];
2430 * Optimize sample messages that have constant zero values for the trailing
2431 * texture coordinates. We can just reduce the message length for these
2432 * instructions instead of reserving a register for it. Trailing parameters
2433 * that aren't sent default to zero anyway. This will cause the dead code
2434 * eliminator to remove the MOV instruction that would otherwise be emitted to
2435 * set up the zero value.
2438 fs_visitor::opt_zero_samples()
2440 /* Gen4 infers the texturing opcode based on the message length so we can't
2443 if (devinfo
->gen
< 5)
2446 bool progress
= false;
2448 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2449 if (!inst
->is_tex())
2452 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2454 if (load_payload
->is_head_sentinel() ||
2455 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2458 /* We don't want to remove the message header or the first parameter.
2459 * Removing the first parameter is not allowed, see the Haswell PRM
2460 * volume 7, page 149:
2462 * "Parameter 0 is required except for the sampleinfo message, which
2463 * has no parameter 0"
2465 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2466 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2467 (inst
->exec_size
/ 8) +
2468 inst
->header_size
- 1].is_zero()) {
2469 inst
->mlen
-= inst
->exec_size
/ 8;
2475 invalidate_live_intervals();
2481 * Optimize sample messages which are followed by the final RT write.
2483 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2484 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2485 * final texturing results copied to the framebuffer write payload and modify
2486 * them to write to the framebuffer directly.
2489 fs_visitor::opt_sampler_eot()
2491 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2493 if (stage
!= MESA_SHADER_FRAGMENT
)
2496 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2499 /* FINISHME: It should be possible to implement this optimization when there
2500 * are multiple drawbuffers.
2502 if (key
->nr_color_regions
!= 1)
2505 /* Requires emitting a bunch of saturating MOV instructions during logical
2506 * send lowering to clamp the color payload, which the sampler unit isn't
2507 * going to do for us.
2509 if (key
->clamp_fragment_color
)
2512 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2513 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2514 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2515 assert(fb_write
->eot
);
2516 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2518 /* There wasn't one; nothing to do. */
2519 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2522 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2524 /* 3D Sampler » Messages » Message Format
2526 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2527 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2529 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2530 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2531 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2532 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2533 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2534 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2535 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2536 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2539 /* XXX - This shouldn't be necessary. */
2540 if (tex_inst
->prev
->is_head_sentinel())
2543 /* Check that the FB write sources are fully initialized by the single
2544 * texturing instruction.
2546 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2547 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2548 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2549 fb_write
->regs_read(i
) != tex_inst
->regs_written
)
2551 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2552 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2557 assert(!tex_inst
->eot
); /* We can't get here twice */
2558 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2560 const fs_builder
ibld(this, block
, tex_inst
);
2562 tex_inst
->offset
|= fb_write
->target
<< 24;
2563 tex_inst
->eot
= true;
2564 tex_inst
->dst
= ibld
.null_reg_ud();
2565 tex_inst
->regs_written
= 0;
2566 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2568 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2569 * flag and submit a header together with the sampler message as required
2572 invalidate_live_intervals();
2577 fs_visitor::opt_register_renaming()
2579 bool progress
= false;
2582 int remap
[alloc
.count
];
2583 memset(remap
, -1, sizeof(int) * alloc
.count
);
2585 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2586 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2588 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2589 inst
->opcode
== BRW_OPCODE_WHILE
) {
2593 /* Rewrite instruction sources. */
2594 for (int i
= 0; i
< inst
->sources
; i
++) {
2595 if (inst
->src
[i
].file
== VGRF
&&
2596 remap
[inst
->src
[i
].nr
] != -1 &&
2597 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2598 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2603 const int dst
= inst
->dst
.nr
;
2606 inst
->dst
.file
== VGRF
&&
2607 alloc
.sizes
[inst
->dst
.nr
] == inst
->regs_written
&&
2608 !inst
->is_partial_write()) {
2609 if (remap
[dst
] == -1) {
2612 remap
[dst
] = alloc
.allocate(inst
->regs_written
);
2613 inst
->dst
.nr
= remap
[dst
];
2616 } else if (inst
->dst
.file
== VGRF
&&
2618 remap
[dst
] != dst
) {
2619 inst
->dst
.nr
= remap
[dst
];
2625 invalidate_live_intervals();
2627 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2628 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2629 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2638 * Remove redundant or useless discard jumps.
2640 * For example, we can eliminate jumps in the following sequence:
2642 * discard-jump (redundant with the next jump)
2643 * discard-jump (useless; jumps to the next instruction)
2647 fs_visitor::opt_redundant_discard_jumps()
2649 bool progress
= false;
2651 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2653 fs_inst
*placeholder_halt
= NULL
;
2654 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2655 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2656 placeholder_halt
= inst
;
2661 if (!placeholder_halt
)
2664 /* Delete any HALTs immediately before the placeholder halt. */
2665 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2666 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2667 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2668 prev
->remove(last_bblock
);
2673 invalidate_live_intervals();
2679 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2680 * from \p r which overlaps the region starting at \p r and spanning \p n GRF
2683 static inline unsigned
2684 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned n
)
2686 const int rel_offset
= (reg_offset(s
) - reg_offset(r
)) / REG_SIZE
;
2687 assert(reg_space(r
) == reg_space(s
) &&
2688 rel_offset
>= 0 && rel_offset
< int(8 * sizeof(unsigned)));
2689 return ((1 << n
) - 1) << rel_offset
;
2693 fs_visitor::compute_to_mrf()
2695 bool progress
= false;
2698 /* No MRFs on Gen >= 7. */
2699 if (devinfo
->gen
>= 7)
2702 calculate_live_intervals();
2704 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2708 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2709 inst
->is_partial_write() ||
2710 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2711 inst
->dst
.type
!= inst
->src
[0].type
||
2712 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2713 !inst
->src
[0].is_contiguous() ||
2714 inst
->src
[0].subreg_offset
)
2717 /* Can't compute-to-MRF this GRF if someone else was going to
2720 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2723 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
2724 * things that computed the value of all GRFs of the source region. The
2725 * regs_left bitset keeps track of the registers we haven't yet found a
2726 * generating instruction for.
2728 unsigned regs_left
= (1 << inst
->regs_read(0)) - 1;
2730 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2731 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2732 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2733 /* Found the last thing to write our reg we want to turn
2734 * into a compute-to-MRF.
2737 /* If this one instruction didn't populate all the
2738 * channels, bail. We might be able to rewrite everything
2739 * that writes that reg, but it would require smarter
2742 if (scan_inst
->is_partial_write())
2745 /* Handling things not fully contained in the source of the copy
2746 * would need us to understand coalescing out more than one MOV at
2749 if (scan_inst
->dst
.reg_offset
< inst
->src
[0].reg_offset
||
2750 scan_inst
->dst
.reg_offset
+ scan_inst
->regs_written
>
2751 inst
->src
[0].reg_offset
+ inst
->regs_read(0))
2754 /* SEND instructions can't have MRF as a destination. */
2755 if (scan_inst
->mlen
)
2758 if (devinfo
->gen
== 6) {
2759 /* gen6 math instructions must have the destination be
2760 * GRF, so no compute-to-MRF for them.
2762 if (scan_inst
->is_math()) {
2767 /* Clear the bits for any registers this instruction overwrites. */
2768 regs_left
&= ~mask_relative_to(
2769 inst
->src
[0], scan_inst
->dst
, scan_inst
->regs_written
);
2774 /* We don't handle control flow here. Most computation of
2775 * values that end up in MRFs are shortly before the MRF
2778 if (block
->start() == scan_inst
)
2781 /* You can't read from an MRF, so if someone else reads our
2782 * MRF's source GRF that we wanted to rewrite, that stops us.
2784 bool interfered
= false;
2785 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2786 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->regs_read(i
) * REG_SIZE
,
2787 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2794 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2795 inst
->dst
, inst
->regs_written
* REG_SIZE
)) {
2796 /* If somebody else writes our MRF here, we can't
2797 * compute-to-MRF before that.
2802 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
2803 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
2804 inst
->dst
, inst
->regs_written
* REG_SIZE
)) {
2805 /* Found a SEND instruction, which means that there are
2806 * live values in MRFs from base_mrf to base_mrf +
2807 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2817 /* Found all generating instructions of our MRF's source value, so it
2818 * should be safe to rewrite them to point to the MRF directly.
2820 regs_left
= (1 << inst
->regs_read(0)) - 1;
2822 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2823 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2824 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2825 /* Clear the bits for any registers this instruction overwrites. */
2826 regs_left
&= ~mask_relative_to(
2827 inst
->src
[0], scan_inst
->dst
, scan_inst
->regs_written
);
2829 const unsigned rel_offset
= (reg_offset(scan_inst
->dst
) -
2830 reg_offset(inst
->src
[0])) / REG_SIZE
;
2832 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2833 /* Apply the same address transformation done by the hardware
2834 * for COMPR4 MRF writes.
2836 assert(rel_offset
< 2);
2837 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
* 4;
2839 /* Clear the COMPR4 bit if the generating instruction is not
2842 if (scan_inst
->regs_written
< 2)
2843 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
2846 /* Calculate the MRF number the result of this instruction is
2847 * ultimately written to.
2849 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
;
2852 scan_inst
->dst
.file
= MRF
;
2853 scan_inst
->dst
.reg_offset
= 0;
2854 scan_inst
->saturate
|= inst
->saturate
;
2861 inst
->remove(block
);
2866 invalidate_live_intervals();
2872 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2873 * flow. We could probably do better here with some form of divergence
2877 fs_visitor::eliminate_find_live_channel()
2879 bool progress
= false;
2882 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2883 switch (inst
->opcode
) {
2889 case BRW_OPCODE_ENDIF
:
2890 case BRW_OPCODE_WHILE
:
2894 case FS_OPCODE_DISCARD_JUMP
:
2895 /* This can potentially make control flow non-uniform until the end
2900 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2902 inst
->opcode
= BRW_OPCODE_MOV
;
2903 inst
->src
[0] = brw_imm_ud(0u);
2905 inst
->force_writemask_all
= true;
2919 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2920 * instructions to FS_OPCODE_REP_FB_WRITE.
2923 fs_visitor::emit_repclear_shader()
2925 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2927 int color_mrf
= base_mrf
+ 2;
2931 mov
= bld
.exec_all().group(4, 0)
2932 .MOV(brw_message_reg(color_mrf
),
2933 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2935 struct brw_reg reg
=
2936 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2937 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
2938 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2940 mov
= bld
.exec_all().group(4, 0)
2941 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
2945 if (key
->nr_color_regions
== 1) {
2946 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2947 write
->saturate
= key
->clamp_fragment_color
;
2948 write
->base_mrf
= color_mrf
;
2950 write
->header_size
= 0;
2953 assume(key
->nr_color_regions
> 0);
2954 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2955 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2956 write
->saturate
= key
->clamp_fragment_color
;
2957 write
->base_mrf
= base_mrf
;
2959 write
->header_size
= 2;
2967 assign_constant_locations();
2968 assign_curb_setup();
2970 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2972 assert(mov
->src
[0].file
== FIXED_GRF
);
2973 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2978 * Walks through basic blocks, looking for repeated MRF writes and
2979 * removing the later ones.
2982 fs_visitor::remove_duplicate_mrf_writes()
2984 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2985 bool progress
= false;
2987 /* Need to update the MRF tracking for compressed instructions. */
2988 if (dispatch_width
>= 16)
2991 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2993 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2994 if (inst
->is_control_flow()) {
2995 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2998 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2999 inst
->dst
.file
== MRF
) {
3000 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3001 if (prev_inst
&& inst
->equals(prev_inst
)) {
3002 inst
->remove(block
);
3008 /* Clear out the last-write records for MRFs that were overwritten. */
3009 if (inst
->dst
.file
== MRF
) {
3010 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3013 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3014 /* Found a SEND instruction, which will include two or fewer
3015 * implied MRF writes. We could do better here.
3017 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3018 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3022 /* Clear out any MRF move records whose sources got overwritten. */
3023 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3024 if (last_mrf_move
[i
] &&
3025 regions_overlap(inst
->dst
, inst
->regs_written
* REG_SIZE
,
3026 last_mrf_move
[i
]->src
[0],
3027 last_mrf_move
[i
]->regs_read(0) * REG_SIZE
)) {
3028 last_mrf_move
[i
] = NULL
;
3032 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3033 inst
->dst
.file
== MRF
&&
3034 inst
->src
[0].file
!= ARF
&&
3035 !inst
->is_partial_write()) {
3036 last_mrf_move
[inst
->dst
.nr
] = inst
;
3041 invalidate_live_intervals();
3047 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3049 /* Clear the flag for registers that actually got read (as expected). */
3050 for (int i
= 0; i
< inst
->sources
; i
++) {
3052 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3053 grf
= inst
->src
[i
].nr
;
3058 if (grf
>= first_grf
&&
3059 grf
< first_grf
+ grf_len
) {
3060 deps
[grf
- first_grf
] = false;
3061 if (inst
->exec_size
== 16)
3062 deps
[grf
- first_grf
+ 1] = false;
3068 * Implements this workaround for the original 965:
3070 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3071 * check for post destination dependencies on this instruction, software
3072 * must ensure that there is no destination hazard for the case of ‘write
3073 * followed by a posted write’ shown in the following example.
3076 * 2. send r3.xy <rest of send instruction>
3079 * Due to no post-destination dependency check on the ‘send’, the above
3080 * code sequence could have two instructions (1 and 2) in flight at the
3081 * same time that both consider ‘r3’ as the target of their final writes.
3084 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3087 int write_len
= inst
->regs_written
;
3088 int first_write_grf
= inst
->dst
.nr
;
3089 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3090 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3092 memset(needs_dep
, false, sizeof(needs_dep
));
3093 memset(needs_dep
, true, write_len
);
3095 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3097 /* Walk backwards looking for writes to registers we're writing which
3098 * aren't read since being written. If we hit the start of the program,
3099 * we assume that there are no outstanding dependencies on entry to the
3102 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3103 /* If we hit control flow, assume that there *are* outstanding
3104 * dependencies, and force their cleanup before our instruction.
3106 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3107 for (int i
= 0; i
< write_len
; i
++) {
3109 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3110 first_write_grf
+ i
);
3115 /* We insert our reads as late as possible on the assumption that any
3116 * instruction but a MOV that might have left us an outstanding
3117 * dependency has more latency than a MOV.
3119 if (scan_inst
->dst
.file
== VGRF
) {
3120 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
3121 int reg
= scan_inst
->dst
.nr
+ i
;
3123 if (reg
>= first_write_grf
&&
3124 reg
< first_write_grf
+ write_len
&&
3125 needs_dep
[reg
- first_write_grf
]) {
3126 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3127 needs_dep
[reg
- first_write_grf
] = false;
3128 if (scan_inst
->exec_size
== 16)
3129 needs_dep
[reg
- first_write_grf
+ 1] = false;
3134 /* Clear the flag for registers that actually got read (as expected). */
3135 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3137 /* Continue the loop only if we haven't resolved all the dependencies */
3139 for (i
= 0; i
< write_len
; i
++) {
3149 * Implements this workaround for the original 965:
3151 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3152 * used as a destination register until after it has been sourced by an
3153 * instruction with a different destination register.
3156 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3158 int write_len
= inst
->regs_written
;
3159 int first_write_grf
= inst
->dst
.nr
;
3160 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3161 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3163 memset(needs_dep
, false, sizeof(needs_dep
));
3164 memset(needs_dep
, true, write_len
);
3165 /* Walk forwards looking for writes to registers we're writing which aren't
3166 * read before being written.
3168 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3169 /* If we hit control flow, force resolve all remaining dependencies. */
3170 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3171 for (int i
= 0; i
< write_len
; i
++) {
3173 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3174 first_write_grf
+ i
);
3179 /* Clear the flag for registers that actually got read (as expected). */
3180 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3182 /* We insert our reads as late as possible since they're reading the
3183 * result of a SEND, which has massive latency.
3185 if (scan_inst
->dst
.file
== VGRF
&&
3186 scan_inst
->dst
.nr
>= first_write_grf
&&
3187 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3188 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3189 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3191 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3194 /* Continue the loop only if we haven't resolved all the dependencies */
3196 for (i
= 0; i
< write_len
; i
++) {
3206 fs_visitor::insert_gen4_send_dependency_workarounds()
3208 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3211 bool progress
= false;
3213 /* Note that we're done with register allocation, so GRF fs_regs always
3214 * have a .reg_offset of 0.
3217 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3218 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3219 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3220 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3226 invalidate_live_intervals();
3230 * Turns the generic expression-style uniform pull constant load instruction
3231 * into a hardware-specific series of instructions for loading a pull
3234 * The expression style allows the CSE pass before this to optimize out
3235 * repeated loads from the same offset, and gives the pre-register-allocation
3236 * scheduling full flexibility, while the conversion to native instructions
3237 * allows the post-register-allocation scheduler the best information
3240 * Note that execution masking for setting up pull constant loads is special:
3241 * the channels that need to be written are unrelated to the current execution
3242 * mask, since a later instruction will use one of the result channels as a
3243 * source operand for all 8 or 16 of its channels.
3246 fs_visitor::lower_uniform_pull_constant_loads()
3248 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3249 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3252 if (devinfo
->gen
>= 7) {
3253 /* The offset arg is a vec4-aligned immediate byte offset. */
3254 fs_reg const_offset_reg
= inst
->src
[1];
3255 assert(const_offset_reg
.file
== IMM
&&
3256 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3257 assert(const_offset_reg
.ud
% 16 == 0);
3259 fs_reg payload
, offset
;
3260 if (devinfo
->gen
>= 9) {
3261 /* We have to use a message header on Skylake to get SIMD4x2
3262 * mode. Reserve space for the register.
3264 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3265 offset
.reg_offset
++;
3268 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3272 /* This is actually going to be a MOV, but since only the first dword
3273 * is accessed, we have a special opcode to do just that one. Note
3274 * that this needs to be an operation that will be considered a def
3275 * by live variable analysis, or register allocation will explode.
3277 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3278 8, offset
, const_offset_reg
);
3279 setup
->force_writemask_all
= true;
3281 setup
->ir
= inst
->ir
;
3282 setup
->annotation
= inst
->annotation
;
3283 inst
->insert_before(block
, setup
);
3285 /* Similarly, this will only populate the first 4 channels of the
3286 * result register (since we only use smear values from 0-3), but we
3287 * don't tell the optimizer.
3289 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3290 inst
->src
[1] = payload
;
3292 invalidate_live_intervals();
3294 /* Before register allocation, we didn't tell the scheduler about the
3295 * MRF we use. We know it's safe to use this MRF because nothing
3296 * else does except for register spill/unspill, which generates and
3297 * uses its MRF within a single IR instruction.
3299 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3306 fs_visitor::lower_load_payload()
3308 bool progress
= false;
3310 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3311 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3314 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3315 assert(inst
->saturate
== false);
3316 fs_reg dst
= inst
->dst
;
3318 /* Get rid of COMPR4. We'll add it back in if we need it */
3319 if (dst
.file
== MRF
)
3320 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3322 const fs_builder
ibld(this, block
, inst
);
3323 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3325 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3326 if (inst
->src
[i
].file
!= BAD_FILE
) {
3327 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3328 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3329 hbld
.MOV(mov_dst
, mov_src
);
3331 dst
= offset(dst
, hbld
, 1);
3334 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3335 inst
->exec_size
> 8) {
3336 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3337 * a straightforward copy. Instead, the result of the
3338 * LOAD_PAYLOAD is treated as interleaved and the first four
3339 * non-header sources are unpacked as:
3350 * This is used for gen <= 5 fb writes.
3352 assert(inst
->exec_size
== 16);
3353 assert(inst
->header_size
+ 4 <= inst
->sources
);
3354 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3355 if (inst
->src
[i
].file
!= BAD_FILE
) {
3356 if (devinfo
->has_compr4
) {
3357 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3358 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3359 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3361 /* Platform doesn't have COMPR4. We have to fake it */
3362 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3363 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3365 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3372 /* The loop above only ever incremented us through the first set
3373 * of 4 registers. However, thanks to the magic of COMPR4, we
3374 * actually wrote to the first 8 registers, so we need to take
3375 * that into account now.
3379 /* The COMPR4 code took care of the first 4 sources. We'll let
3380 * the regular path handle any remaining sources. Yes, we are
3381 * modifying the instruction but we're about to delete it so
3382 * this really doesn't hurt anything.
3384 inst
->header_size
+= 4;
3387 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3388 if (inst
->src
[i
].file
!= BAD_FILE
)
3389 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3390 dst
= offset(dst
, ibld
, 1);
3393 inst
->remove(block
);
3398 invalidate_live_intervals();
3404 fs_visitor::lower_integer_multiplication()
3406 bool progress
= false;
3408 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3409 const fs_builder
ibld(this, block
, inst
);
3411 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3412 if (inst
->dst
.is_accumulator() ||
3413 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3414 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3417 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3418 * operation directly, but CHV/BXT cannot.
3420 if (devinfo
->gen
>= 8 &&
3421 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3424 if (inst
->src
[1].file
== IMM
&&
3425 inst
->src
[1].ud
< (1 << 16)) {
3426 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3427 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3430 * If multiplying by an immediate value that fits in 16-bits, do a
3431 * single MUL instruction with that value in the proper location.
3433 if (devinfo
->gen
< 7) {
3434 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3436 ibld
.MOV(imm
, inst
->src
[1]);
3437 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3439 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3440 ibld
.MUL(inst
->dst
, inst
->src
[0],
3441 ud
? brw_imm_uw(inst
->src
[1].ud
)
3442 : brw_imm_w(inst
->src
[1].d
));
3445 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3446 * do 32-bit integer multiplication in one instruction, but instead
3447 * must do a sequence (which actually calculates a 64-bit result):
3449 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3450 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3451 * mov(8) g2<1>D acc0<8,8,1>D
3453 * But on Gen > 6, the ability to use second accumulator register
3454 * (acc1) for non-float data types was removed, preventing a simple
3455 * implementation in SIMD16. A 16-channel result can be calculated by
3456 * executing the three instructions twice in SIMD8, once with quarter
3457 * control of 1Q for the first eight channels and again with 2Q for
3458 * the second eight channels.
3460 * Which accumulator register is implicitly accessed (by AccWrEnable
3461 * for instance) is determined by the quarter control. Unfortunately
3462 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3463 * implicit accumulator access by an instruction with 2Q will access
3464 * acc1 regardless of whether the data type is usable in acc1.
3466 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3467 * integer data types.
3469 * Since we only want the low 32-bits of the result, we can do two
3470 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3471 * adjust the high result and add them (like the mach is doing):
3473 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3474 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3475 * shl(8) g9<1>D g8<8,8,1>D 16D
3476 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3478 * We avoid the shl instruction by realizing that we only want to add
3479 * the low 16-bits of the "high" result to the high 16-bits of the
3480 * "low" result and using proper regioning on the add:
3482 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3483 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3484 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3486 * Since it does not use the (single) accumulator register, we can
3487 * schedule multi-component multiplications much better.
3490 fs_reg orig_dst
= inst
->dst
;
3491 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3492 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3495 fs_reg low
= inst
->dst
;
3496 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3499 if (devinfo
->gen
>= 7) {
3500 fs_reg src1_0_w
= inst
->src
[1];
3501 fs_reg src1_1_w
= inst
->src
[1];
3503 if (inst
->src
[1].file
== IMM
) {
3504 src1_0_w
.ud
&= 0xffff;
3507 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3508 if (src1_0_w
.stride
!= 0) {
3509 assert(src1_0_w
.stride
== 1);
3510 src1_0_w
.stride
= 2;
3513 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3514 if (src1_1_w
.stride
!= 0) {
3515 assert(src1_1_w
.stride
== 1);
3516 src1_1_w
.stride
= 2;
3518 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3520 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3521 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3523 fs_reg src0_0_w
= inst
->src
[0];
3524 fs_reg src0_1_w
= inst
->src
[0];
3526 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3527 if (src0_0_w
.stride
!= 0) {
3528 assert(src0_0_w
.stride
== 1);
3529 src0_0_w
.stride
= 2;
3532 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3533 if (src0_1_w
.stride
!= 0) {
3534 assert(src0_1_w
.stride
== 1);
3535 src0_1_w
.stride
= 2;
3537 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3539 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3540 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3543 fs_reg dst
= inst
->dst
;
3544 dst
.type
= BRW_REGISTER_TYPE_UW
;
3545 dst
.subreg_offset
= 2;
3548 high
.type
= BRW_REGISTER_TYPE_UW
;
3551 low
.type
= BRW_REGISTER_TYPE_UW
;
3552 low
.subreg_offset
= 2;
3555 ibld
.ADD(dst
, low
, high
);
3557 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3558 set_condmod(inst
->conditional_mod
,
3559 ibld
.MOV(orig_dst
, inst
->dst
));
3563 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3564 /* Should have been lowered to 8-wide. */
3565 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
3566 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3568 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3569 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3571 if (devinfo
->gen
>= 8) {
3572 /* Until Gen8, integer multiplies read 32-bits from one source,
3573 * and 16-bits from the other, and relying on the MACH instruction
3574 * to generate the high bits of the result.
3576 * On Gen8, the multiply instruction does a full 32x32-bit
3577 * multiply, but in order to do a 64-bit multiply we can simulate
3578 * the previous behavior and then use a MACH instruction.
3580 * FINISHME: Don't use source modifiers on src1.
3582 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3583 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3584 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3585 mul
->src
[1].stride
*= 2;
3587 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3589 /* Among other things the quarter control bits influence which
3590 * accumulator register is used by the hardware for instructions
3591 * that access the accumulator implicitly (e.g. MACH). A
3592 * second-half instruction would normally map to acc1, which
3593 * doesn't exist on Gen7 and up (the hardware does emulate it for
3594 * floating-point instructions *only* by taking advantage of the
3595 * extra precision of acc0 not normally used for floating point
3598 * HSW and up are careful enough not to try to access an
3599 * accumulator register that doesn't exist, but on earlier Gen7
3600 * hardware we need to make sure that the quarter control bits are
3601 * zero to avoid non-deterministic behaviour and emit an extra MOV
3602 * to get the result masked correctly according to the current
3606 mach
->force_writemask_all
= true;
3607 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3608 ibld
.MOV(inst
->dst
, mach
->dst
);
3614 inst
->remove(block
);
3619 invalidate_live_intervals();
3625 fs_visitor::lower_minmax()
3627 assert(devinfo
->gen
< 6);
3629 bool progress
= false;
3631 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3632 const fs_builder
ibld(this, block
, inst
);
3634 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3635 inst
->predicate
== BRW_PREDICATE_NONE
) {
3636 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3637 * the original SEL.L/GE instruction
3639 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3640 inst
->conditional_mod
);
3641 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3642 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3649 invalidate_live_intervals();
3655 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3656 fs_reg
*dst
, fs_reg color
, unsigned components
)
3658 if (key
->clamp_fragment_color
) {
3659 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3660 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3662 for (unsigned i
= 0; i
< components
; i
++)
3664 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3669 for (unsigned i
= 0; i
< components
; i
++)
3670 dst
[i
] = offset(color
, bld
, i
);
3674 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3675 const brw_wm_prog_data
*prog_data
,
3676 const brw_wm_prog_key
*key
,
3677 const fs_visitor::thread_payload
&payload
)
3679 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3680 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3681 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3682 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3683 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3684 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3685 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3686 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3687 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3688 const unsigned components
=
3689 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3691 /* We can potentially have a message length of up to 15, so we have to set
3692 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3695 int header_size
= 2, payload_header_size
;
3696 unsigned length
= 0;
3698 /* From the Sandy Bridge PRM, volume 4, page 198:
3700 * "Dispatched Pixel Enables. One bit per pixel indicating
3701 * which pixels were originally enabled when the thread was
3702 * dispatched. This field is only required for the end-of-
3703 * thread message and on all dual-source messages."
3705 if (devinfo
->gen
>= 6 &&
3706 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3707 color1
.file
== BAD_FILE
&&
3708 key
->nr_color_regions
== 1) {
3712 if (header_size
!= 0) {
3713 assert(header_size
== 2);
3714 /* Allocate 2 registers for a header */
3718 if (payload
.aa_dest_stencil_reg
) {
3719 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3720 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3721 .MOV(sources
[length
],
3722 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3726 if (sample_mask
.file
!= BAD_FILE
) {
3727 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3728 BRW_REGISTER_TYPE_UD
);
3730 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3731 * relevant. Since it's unsigned single words one vgrf is always
3732 * 16-wide, but only the lower or higher 8 channels will be used by the
3733 * hardware when doing a SIMD8 write depending on whether we have
3734 * selected the subspans for the first or second half respectively.
3736 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3737 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3738 sample_mask
.stride
*= 2;
3740 bld
.exec_all().annotate("FB write oMask")
3741 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3747 payload_header_size
= length
;
3749 if (src0_alpha
.file
!= BAD_FILE
) {
3750 /* FIXME: This is being passed at the wrong location in the payload and
3751 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3752 * It's supposed to be immediately before oMask but there seems to be no
3753 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3754 * requires header sources to form a contiguous segment at the beginning
3755 * of the message and src0_alpha has per-channel semantics.
3757 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3761 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3764 if (color1
.file
!= BAD_FILE
) {
3765 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3769 if (src_depth
.file
!= BAD_FILE
) {
3770 sources
[length
] = src_depth
;
3774 if (dst_depth
.file
!= BAD_FILE
) {
3775 sources
[length
] = dst_depth
;
3779 if (src_stencil
.file
!= BAD_FILE
) {
3780 assert(devinfo
->gen
>= 9);
3781 assert(bld
.dispatch_width() != 16);
3783 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3784 * available on gen9+. As such it's impossible to have both enabled at the
3785 * same time and therefore length cannot overrun the array.
3787 assert(length
< 15);
3789 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3790 bld
.exec_all().annotate("FB write OS")
3791 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
3792 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
3797 if (devinfo
->gen
>= 7) {
3798 /* Send from the GRF */
3799 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3800 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3801 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3802 load
->dst
= payload
;
3804 inst
->src
[0] = payload
;
3805 inst
->resize_sources(1);
3807 /* Send from the MRF */
3808 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3809 sources
, length
, payload_header_size
);
3811 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3812 * will do this for us if we just give it a COMPR4 destination.
3814 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3815 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3817 inst
->resize_sources(0);
3821 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3822 inst
->mlen
= load
->regs_written
;
3823 inst
->header_size
= header_size
;
3827 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3828 const fs_reg
&coordinate
,
3829 const fs_reg
&shadow_c
,
3830 const fs_reg
&lod
, const fs_reg
&lod2
,
3831 const fs_reg
&surface
,
3832 const fs_reg
&sampler
,
3833 unsigned coord_components
,
3834 unsigned grad_components
)
3836 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3837 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3838 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3839 fs_reg msg_end
= msg_begin
;
3842 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3844 for (unsigned i
= 0; i
< coord_components
; i
++)
3845 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3846 offset(coordinate
, bld
, i
));
3848 msg_end
= offset(msg_end
, bld
, coord_components
);
3850 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3851 * require all three components to be present and zero if they are unused.
3853 if (coord_components
> 0 &&
3854 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3855 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3856 for (unsigned i
= coord_components
; i
< 3; i
++)
3857 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3859 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3862 if (op
== SHADER_OPCODE_TXD
) {
3863 /* TXD unsupported in SIMD16 mode. */
3864 assert(bld
.dispatch_width() == 8);
3866 /* the slots for u and v are always present, but r is optional */
3867 if (coord_components
< 2)
3868 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3871 * dPdx = dudx, dvdx, drdx
3872 * dPdy = dudy, dvdy, drdy
3874 * 1-arg: Does not exist.
3876 * 2-arg: dudx dvdx dudy dvdy
3877 * dPdx.x dPdx.y dPdy.x dPdy.y
3880 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3881 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3882 * m5 m6 m7 m8 m9 m10
3884 for (unsigned i
= 0; i
< grad_components
; i
++)
3885 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3887 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3889 for (unsigned i
= 0; i
< grad_components
; i
++)
3890 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3892 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3896 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3897 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3899 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3900 bld
.dispatch_width() == 16);
3902 const brw_reg_type type
=
3903 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3904 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3905 bld
.MOV(retype(msg_end
, type
), lod
);
3906 msg_end
= offset(msg_end
, bld
, 1);
3909 if (shadow_c
.file
!= BAD_FILE
) {
3910 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3911 /* There's no plain shadow compare message, so we use shadow
3912 * compare with a bias of 0.0.
3914 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3915 msg_end
= offset(msg_end
, bld
, 1);
3918 bld
.MOV(msg_end
, shadow_c
);
3919 msg_end
= offset(msg_end
, bld
, 1);
3923 inst
->src
[0] = reg_undef
;
3924 inst
->src
[1] = surface
;
3925 inst
->src
[2] = sampler
;
3926 inst
->resize_sources(3);
3927 inst
->base_mrf
= msg_begin
.nr
;
3928 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3929 inst
->header_size
= 1;
3933 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3934 const fs_reg
&coordinate
,
3935 const fs_reg
&shadow_c
,
3936 const fs_reg
&lod
, const fs_reg
&lod2
,
3937 const fs_reg
&sample_index
,
3938 const fs_reg
&surface
,
3939 const fs_reg
&sampler
,
3940 const fs_reg
&offset_value
,
3941 unsigned coord_components
,
3942 unsigned grad_components
)
3944 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3945 fs_reg msg_coords
= message
;
3946 unsigned header_size
= 0;
3948 if (offset_value
.file
!= BAD_FILE
) {
3949 /* The offsets set up by the visitor are in the m1 header, so we can't
3956 for (unsigned i
= 0; i
< coord_components
; i
++)
3957 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
3958 offset(coordinate
, bld
, i
));
3960 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3961 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3963 if (shadow_c
.file
!= BAD_FILE
) {
3964 fs_reg msg_shadow
= msg_lod
;
3965 bld
.MOV(msg_shadow
, shadow_c
);
3966 msg_lod
= offset(msg_shadow
, bld
, 1);
3971 case SHADER_OPCODE_TXL
:
3973 bld
.MOV(msg_lod
, lod
);
3974 msg_end
= offset(msg_lod
, bld
, 1);
3976 case SHADER_OPCODE_TXD
:
3979 * dPdx = dudx, dvdx, drdx
3980 * dPdy = dudy, dvdy, drdy
3982 * Load up these values:
3983 * - dudx dudy dvdx dvdy drdx drdy
3984 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3987 for (unsigned i
= 0; i
< grad_components
; i
++) {
3988 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
3989 msg_end
= offset(msg_end
, bld
, 1);
3991 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
3992 msg_end
= offset(msg_end
, bld
, 1);
3995 case SHADER_OPCODE_TXS
:
3996 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3997 bld
.MOV(msg_lod
, lod
);
3998 msg_end
= offset(msg_lod
, bld
, 1);
4000 case SHADER_OPCODE_TXF
:
4001 msg_lod
= offset(msg_coords
, bld
, 3);
4002 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4003 msg_end
= offset(msg_lod
, bld
, 1);
4005 case SHADER_OPCODE_TXF_CMS
:
4006 msg_lod
= offset(msg_coords
, bld
, 3);
4008 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4010 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4011 msg_end
= offset(msg_lod
, bld
, 2);
4018 inst
->src
[0] = reg_undef
;
4019 inst
->src
[1] = surface
;
4020 inst
->src
[2] = sampler
;
4021 inst
->resize_sources(3);
4022 inst
->base_mrf
= message
.nr
;
4023 inst
->mlen
= msg_end
.nr
- message
.nr
;
4024 inst
->header_size
= header_size
;
4026 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4027 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4031 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
4033 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4036 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4040 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4041 const fs_reg
&coordinate
,
4042 const fs_reg
&shadow_c
,
4043 fs_reg lod
, const fs_reg
&lod2
,
4044 const fs_reg
&sample_index
,
4046 const fs_reg
&surface
,
4047 const fs_reg
&sampler
,
4048 const fs_reg
&offset_value
,
4049 unsigned coord_components
,
4050 unsigned grad_components
)
4052 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4053 int reg_width
= bld
.dispatch_width() / 8;
4054 unsigned header_size
= 0, length
= 0;
4055 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4056 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4057 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4059 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4060 offset_value
.file
!= BAD_FILE
|| inst
->eot
||
4061 op
== SHADER_OPCODE_SAMPLEINFO
||
4062 is_high_sampler(devinfo
, sampler
)) {
4063 /* For general texture offsets (no txf workaround), we need a header to
4064 * put them in. Note that we're only reserving space for it in the
4065 * message payload as it will be initialized implicitly by the
4068 * TG4 needs to place its channel select in the header, for interaction
4069 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4070 * larger sampler numbers we need to offset the Sampler State Pointer in
4074 sources
[0] = fs_reg();
4077 /* If we're requesting fewer than four channels worth of response,
4078 * and we have an explicit header, we need to set up the sampler
4079 * writemask. It's reversed from normal: 1 means "don't write".
4081 if (!inst
->eot
&& inst
->regs_written
!= 4 * reg_width
) {
4082 assert((inst
->regs_written
% reg_width
) == 0);
4083 unsigned mask
= ~((1 << (inst
->regs_written
/ reg_width
)) - 1) & 0xf;
4084 inst
->offset
|= mask
<< 12;
4088 if (shadow_c
.file
!= BAD_FILE
) {
4089 bld
.MOV(sources
[length
], shadow_c
);
4093 bool coordinate_done
= false;
4095 /* Set up the LOD info */
4098 case SHADER_OPCODE_TXL
:
4099 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4100 op
= SHADER_OPCODE_TXL_LZ
;
4103 bld
.MOV(sources
[length
], lod
);
4106 case SHADER_OPCODE_TXD
:
4107 /* TXD should have been lowered in SIMD16 mode. */
4108 assert(bld
.dispatch_width() == 8);
4110 /* Load dPdx and the coordinate together:
4111 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4113 for (unsigned i
= 0; i
< coord_components
; i
++) {
4114 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4116 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4117 * only derivatives for (u, v, r).
4119 if (i
< grad_components
) {
4120 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4121 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4125 coordinate_done
= true;
4127 case SHADER_OPCODE_TXS
:
4128 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4131 case SHADER_OPCODE_TXF
:
4132 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4133 * On Gen9 they are u, v, lod, r
4135 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4137 if (devinfo
->gen
>= 9) {
4138 if (coord_components
>= 2) {
4139 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4140 offset(coordinate
, bld
, 1));
4142 sources
[length
] = brw_imm_d(0);
4147 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4148 op
= SHADER_OPCODE_TXF_LZ
;
4150 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4154 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4155 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4156 offset(coordinate
, bld
, i
));
4158 coordinate_done
= true;
4161 case SHADER_OPCODE_TXF_CMS
:
4162 case SHADER_OPCODE_TXF_CMS_W
:
4163 case SHADER_OPCODE_TXF_UMS
:
4164 case SHADER_OPCODE_TXF_MCS
:
4165 if (op
== SHADER_OPCODE_TXF_UMS
||
4166 op
== SHADER_OPCODE_TXF_CMS
||
4167 op
== SHADER_OPCODE_TXF_CMS_W
) {
4168 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4172 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4173 /* Data from the multisample control surface. */
4174 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4177 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4180 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4181 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4184 offset(mcs
, bld
, 1));
4189 /* There is no offsetting for this message; just copy in the integer
4190 * texture coordinates.
4192 for (unsigned i
= 0; i
< coord_components
; i
++)
4193 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4194 offset(coordinate
, bld
, i
));
4196 coordinate_done
= true;
4198 case SHADER_OPCODE_TG4_OFFSET
:
4199 /* More crazy intermixing */
4200 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4201 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4203 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4204 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4205 offset(offset_value
, bld
, i
));
4207 if (coord_components
== 3) /* r if present */
4208 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4210 coordinate_done
= true;
4216 /* Set up the coordinate (except for cases where it was done above) */
4217 if (!coordinate_done
) {
4218 for (unsigned i
= 0; i
< coord_components
; i
++)
4219 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4224 mlen
= length
* reg_width
- header_size
;
4226 mlen
= length
* reg_width
;
4228 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4229 BRW_REGISTER_TYPE_F
);
4230 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4232 /* Generate the SEND. */
4234 inst
->src
[0] = src_payload
;
4235 inst
->src
[1] = surface
;
4236 inst
->src
[2] = sampler
;
4237 inst
->resize_sources(3);
4239 inst
->header_size
= header_size
;
4241 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4242 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4246 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4248 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4249 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4250 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4251 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4252 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4253 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4254 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4255 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4256 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4257 const fs_reg
&offset_value
= inst
->src
[TEX_LOGICAL_SRC_OFFSET_VALUE
];
4258 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4259 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4260 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4261 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4263 if (devinfo
->gen
>= 7) {
4264 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4265 shadow_c
, lod
, lod2
, sample_index
,
4266 mcs
, surface
, sampler
, offset_value
,
4267 coord_components
, grad_components
);
4268 } else if (devinfo
->gen
>= 5) {
4269 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4270 shadow_c
, lod
, lod2
, sample_index
,
4271 surface
, sampler
, offset_value
,
4272 coord_components
, grad_components
);
4274 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4275 shadow_c
, lod
, lod2
,
4277 coord_components
, grad_components
);
4282 * Initialize the header present in some typed and untyped surface
4286 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4288 fs_builder ubld
= bld
.exec_all().group(8, 0);
4289 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4290 ubld
.MOV(dst
, brw_imm_d(0));
4291 ubld
.MOV(component(dst
, 7), sample_mask
);
4296 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4297 const fs_reg
&sample_mask
)
4299 /* Get the logical send arguments. */
4300 const fs_reg
&addr
= inst
->src
[0];
4301 const fs_reg
&src
= inst
->src
[1];
4302 const fs_reg
&surface
= inst
->src
[2];
4303 const UNUSED fs_reg
&dims
= inst
->src
[3];
4304 const fs_reg
&arg
= inst
->src
[4];
4306 /* Calculate the total number of components of the payload. */
4307 const unsigned addr_sz
= inst
->components_read(0);
4308 const unsigned src_sz
= inst
->components_read(1);
4309 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4310 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4312 /* Allocate space for the payload. */
4313 fs_reg
*const components
= new fs_reg
[sz
];
4314 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4317 /* Construct the payload. */
4319 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4321 for (unsigned i
= 0; i
< addr_sz
; i
++)
4322 components
[n
++] = offset(addr
, bld
, i
);
4324 for (unsigned i
= 0; i
< src_sz
; i
++)
4325 components
[n
++] = offset(src
, bld
, i
);
4327 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4329 /* Update the original instruction. */
4331 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4332 inst
->header_size
= header_sz
;
4334 inst
->src
[0] = payload
;
4335 inst
->src
[1] = surface
;
4337 inst
->resize_sources(3);
4339 delete[] components
;
4343 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4345 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4347 if (devinfo
->gen
>= 7) {
4348 /* We are switching the instruction from an ALU-like instruction to a
4349 * send-from-grf instruction. Since sends can't handle strides or
4350 * source modifiers, we have to make a copy of the offset source.
4352 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4353 bld
.MOV(tmp
, inst
->src
[1]);
4356 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4359 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4360 BRW_REGISTER_TYPE_UD
);
4362 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4364 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4365 inst
->resize_sources(1);
4366 inst
->base_mrf
= payload
.nr
;
4367 inst
->header_size
= 1;
4368 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4373 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4375 assert(bld
.shader
->devinfo
->gen
< 6);
4378 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4380 if (inst
->sources
> 1) {
4381 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4382 * "Message Payload":
4384 * "Operand0[7]. For the INT DIV functions, this operand is the
4387 * "Operand1[7]. For the INT DIV functions, this operand is the
4390 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4391 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4392 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4394 inst
->resize_sources(1);
4395 inst
->src
[0] = src0
;
4397 assert(inst
->exec_size
== 8);
4398 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4403 fs_visitor::lower_logical_sends()
4405 bool progress
= false;
4407 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4408 const fs_builder
ibld(this, block
, inst
);
4410 switch (inst
->opcode
) {
4411 case FS_OPCODE_FB_WRITE_LOGICAL
:
4412 assert(stage
== MESA_SHADER_FRAGMENT
);
4413 lower_fb_write_logical_send(ibld
, inst
,
4414 (const brw_wm_prog_data
*)prog_data
,
4415 (const brw_wm_prog_key
*)key
,
4419 case SHADER_OPCODE_TEX_LOGICAL
:
4420 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4423 case SHADER_OPCODE_TXD_LOGICAL
:
4424 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4427 case SHADER_OPCODE_TXF_LOGICAL
:
4428 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4431 case SHADER_OPCODE_TXL_LOGICAL
:
4432 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4435 case SHADER_OPCODE_TXS_LOGICAL
:
4436 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4439 case FS_OPCODE_TXB_LOGICAL
:
4440 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4443 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4444 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4447 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4448 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4451 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4452 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4455 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4456 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4459 case SHADER_OPCODE_LOD_LOGICAL
:
4460 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4463 case SHADER_OPCODE_TG4_LOGICAL
:
4464 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4467 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4468 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4471 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4472 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
4475 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4476 lower_surface_logical_send(ibld
, inst
,
4477 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4481 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4482 lower_surface_logical_send(ibld
, inst
,
4483 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4484 ibld
.sample_mask_reg());
4487 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4488 lower_surface_logical_send(ibld
, inst
,
4489 SHADER_OPCODE_UNTYPED_ATOMIC
,
4490 ibld
.sample_mask_reg());
4493 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4494 lower_surface_logical_send(ibld
, inst
,
4495 SHADER_OPCODE_TYPED_SURFACE_READ
,
4499 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4500 lower_surface_logical_send(ibld
, inst
,
4501 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4502 ibld
.sample_mask_reg());
4505 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4506 lower_surface_logical_send(ibld
, inst
,
4507 SHADER_OPCODE_TYPED_ATOMIC
,
4508 ibld
.sample_mask_reg());
4511 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4512 lower_varying_pull_constant_logical_send(ibld
, inst
);
4515 case SHADER_OPCODE_RCP
:
4516 case SHADER_OPCODE_RSQ
:
4517 case SHADER_OPCODE_SQRT
:
4518 case SHADER_OPCODE_EXP2
:
4519 case SHADER_OPCODE_LOG2
:
4520 case SHADER_OPCODE_SIN
:
4521 case SHADER_OPCODE_COS
:
4522 case SHADER_OPCODE_POW
:
4523 case SHADER_OPCODE_INT_QUOTIENT
:
4524 case SHADER_OPCODE_INT_REMAINDER
:
4525 /* The math opcodes are overloaded for the send-like and
4526 * expression-like instructions which seems kind of icky. Gen6+ has
4527 * a native (but rather quirky) MATH instruction so we don't need to
4528 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
4529 * logical instructions (which we can easily recognize because they
4530 * have mlen = 0) into send-like virtual instructions.
4532 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
4533 lower_math_logical_send(ibld
, inst
);
4548 invalidate_live_intervals();
4554 * Get the closest allowed SIMD width for instruction \p inst accounting for
4555 * some common regioning and execution control restrictions that apply to FPU
4556 * instructions. These restrictions don't necessarily have any relevance to
4557 * instructions not executed by the FPU pipeline like extended math, control
4558 * flow or send message instructions.
4560 * For virtual opcodes it's really up to the instruction -- In some cases
4561 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
4562 * instructions) it may simplify virtual instruction lowering if we can
4563 * enforce FPU-like regioning restrictions already on the virtual instruction,
4564 * in other cases (e.g. virtual send-like instructions) this may be
4565 * excessively restrictive.
4568 get_fpu_lowered_simd_width(const struct brw_device_info
*devinfo
,
4569 const fs_inst
*inst
)
4571 /* Maximum execution size representable in the instruction controls. */
4572 unsigned max_width
= MIN2(32, inst
->exec_size
);
4574 /* According to the PRMs:
4575 * "A. In Direct Addressing mode, a source cannot span more than 2
4576 * adjacent GRF registers.
4577 * B. A destination cannot span more than 2 adjacent GRF registers."
4579 * Look for the source or destination with the largest register region
4580 * which is the one that is going to limit the overall execution size of
4581 * the instruction due to this rule.
4583 unsigned reg_count
= inst
->regs_written
;
4585 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4586 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4588 /* Calculate the maximum execution size of the instruction based on the
4589 * factor by which it goes over the hardware limit of 2 GRFs.
4592 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
4594 /* According to the IVB PRMs:
4595 * "When destination spans two registers, the source MUST span two
4596 * registers. The exception to the above rule:
4598 * - When source is scalar, the source registers are not incremented.
4599 * - When source is packed integer Word and destination is packed
4600 * integer DWord, the source register is not incremented but the
4601 * source sub register is incremented."
4603 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
4604 * restrictions. The code below intentionally doesn't check whether the
4605 * destination type is integer because empirically the hardware doesn't
4606 * seem to care what the actual type is as long as it's dword-aligned.
4608 if (devinfo
->gen
< 8) {
4609 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
4610 if (inst
->regs_written
== 2 &&
4611 inst
->regs_read(i
) != 0 && inst
->regs_read(i
) != 2 &&
4612 !is_uniform(inst
->src
[i
]) &&
4613 !(type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
4614 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1))
4615 max_width
= MIN2(max_width
, inst
->exec_size
/
4616 inst
->regs_written
);
4620 /* From the IVB PRMs:
4621 * "When an instruction is SIMD32, the low 16 bits of the execution mask
4622 * are applied for both halves of the SIMD32 instruction. If different
4623 * execution mask channels are required, split the instruction into two
4624 * SIMD16 instructions."
4626 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
4627 * 32-wide control flow support in hardware and will behave similarly.
4629 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
4630 max_width
= MIN2(max_width
, 16);
4632 /* From the IVB PRMs (applies to HSW too):
4633 * "Instructions with condition modifiers must not use SIMD32."
4635 * From the BDW PRMs (applies to later hardware too):
4636 * "Ternary instruction with condition modifiers must not use SIMD32."
4638 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
4639 max_width
= MIN2(max_width
, 16);
4641 /* From the IVB PRMs (applies to other devices that don't have the
4642 * brw_device_info::supports_simd16_3src flag set):
4643 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
4644 * SIMD8 is not allowed for DF operations."
4646 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
4647 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4649 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
4650 * the 8-bit quarter of the execution mask signals specified in the
4651 * instruction control fields) for the second compressed half of any
4652 * single-precision instruction (for double-precision instructions
4653 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
4654 * the EU will apply the wrong execution controls for the second
4655 * sequential GRF write if the number of channels per GRF is not exactly
4656 * eight in single-precision mode (or four in double-float mode).
4658 * In this situation we calculate the maximum size of the split
4659 * instructions so they only ever write to a single register.
4661 if (devinfo
->gen
< 8 && inst
->regs_written
> 1 &&
4662 !inst
->force_writemask_all
) {
4663 const unsigned channels_per_grf
= inst
->exec_size
/ inst
->regs_written
;
4664 unsigned exec_type_size
= 0;
4665 for (int i
= 0; i
< inst
->sources
; i
++) {
4666 if (inst
->src
[i
].file
!= BAD_FILE
)
4667 exec_type_size
= MAX2(exec_type_size
, type_sz(inst
->src
[i
].type
));
4669 assert(exec_type_size
);
4671 /* The hardware shifts exactly 8 channels per compressed half of the
4672 * instruction in single-precision mode and exactly 4 in double-precision.
4674 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
4675 max_width
= MIN2(max_width
, channels_per_grf
);
4678 /* Only power-of-two execution sizes are representable in the instruction
4681 return 1 << _mesa_logbase2(max_width
);
4685 * Get the maximum allowed SIMD width for instruction \p inst accounting for
4686 * various payload size restrictions that apply to sampler message
4689 * This is only intended to provide a maximum theoretical bound for the
4690 * execution size of the message based on the number of argument components
4691 * alone, which in most cases will determine whether the SIMD8 or SIMD16
4692 * variant of the message can be used, though some messages may have
4693 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
4694 * the message length to determine the exact SIMD width and argument count,
4695 * which makes a number of sampler message combinations impossible to
4699 get_sampler_lowered_simd_width(const struct brw_device_info
*devinfo
,
4700 const fs_inst
*inst
)
4702 /* Calculate the number of coordinate components that have to be present
4703 * assuming that additional arguments follow the texel coordinates in the
4704 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
4705 * need to pad to four or three components depending on the message,
4706 * pre-ILK we need to pad to at most three components.
4708 const unsigned req_coord_components
=
4709 (devinfo
->gen
>= 7 ||
4710 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
4711 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
4712 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
4715 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
4716 * variant of the TXL or TXF message.
4718 const bool implicit_lod
= devinfo
->gen
>= 9 &&
4719 (inst
->opcode
== SHADER_OPCODE_TXL
||
4720 inst
->opcode
== SHADER_OPCODE_TXF
) &&
4721 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
4723 /* Calculate the total number of argument components that need to be passed
4724 * to the sampler unit.
4726 const unsigned num_payload_components
=
4727 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
4728 req_coord_components
) +
4729 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
4730 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
4731 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
4732 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
4733 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
4734 inst
->components_read(TEX_LOGICAL_SRC_OFFSET_VALUE
) : 0) +
4735 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
4737 /* SIMD16 messages with more than five arguments exceed the maximum message
4738 * size supported by the sampler, regardless of whether a header is
4741 return MIN2(inst
->exec_size
,
4742 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
4746 * Get the closest native SIMD width supported by the hardware for instruction
4747 * \p inst. The instruction will be left untouched by
4748 * fs_visitor::lower_simd_width() if the returned value is equal to the
4749 * original execution size.
4752 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4753 const fs_inst
*inst
)
4755 switch (inst
->opcode
) {
4756 case BRW_OPCODE_MOV
:
4757 case BRW_OPCODE_SEL
:
4758 case BRW_OPCODE_NOT
:
4759 case BRW_OPCODE_AND
:
4761 case BRW_OPCODE_XOR
:
4762 case BRW_OPCODE_SHR
:
4763 case BRW_OPCODE_SHL
:
4764 case BRW_OPCODE_ASR
:
4765 case BRW_OPCODE_CMPN
:
4766 case BRW_OPCODE_CSEL
:
4767 case BRW_OPCODE_F32TO16
:
4768 case BRW_OPCODE_F16TO32
:
4769 case BRW_OPCODE_BFREV
:
4770 case BRW_OPCODE_BFE
:
4771 case BRW_OPCODE_ADD
:
4772 case BRW_OPCODE_MUL
:
4773 case BRW_OPCODE_AVG
:
4774 case BRW_OPCODE_FRC
:
4775 case BRW_OPCODE_RNDU
:
4776 case BRW_OPCODE_RNDD
:
4777 case BRW_OPCODE_RNDE
:
4778 case BRW_OPCODE_RNDZ
:
4779 case BRW_OPCODE_LZD
:
4780 case BRW_OPCODE_FBH
:
4781 case BRW_OPCODE_FBL
:
4782 case BRW_OPCODE_CBIT
:
4783 case BRW_OPCODE_SAD2
:
4784 case BRW_OPCODE_MAD
:
4785 case BRW_OPCODE_LRP
:
4786 case FS_OPCODE_PACK
:
4787 return get_fpu_lowered_simd_width(devinfo
, inst
);
4789 case BRW_OPCODE_CMP
: {
4790 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
4791 * when the destination is a GRF the dependency-clear bit on the flag
4792 * register is cleared early.
4794 * Suggested workarounds are to disable coissuing CMP instructions
4795 * or to split CMP(16) instructions into two CMP(8) instructions.
4797 * We choose to split into CMP(8) instructions since disabling
4798 * coissuing would affect CMP instructions not otherwise affected by
4801 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4802 !inst
->dst
.is_null() ? 8 : ~0);
4803 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
4805 case BRW_OPCODE_BFI1
:
4806 case BRW_OPCODE_BFI2
:
4807 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
4809 * "Force BFI instructions to be executed always in SIMD8."
4811 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
4812 get_fpu_lowered_simd_width(devinfo
, inst
));
4815 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
4816 return inst
->exec_size
;
4818 case SHADER_OPCODE_RCP
:
4819 case SHADER_OPCODE_RSQ
:
4820 case SHADER_OPCODE_SQRT
:
4821 case SHADER_OPCODE_EXP2
:
4822 case SHADER_OPCODE_LOG2
:
4823 case SHADER_OPCODE_SIN
:
4824 case SHADER_OPCODE_COS
:
4825 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
4828 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4829 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
4830 MIN2(8, inst
->exec_size
));
4832 case SHADER_OPCODE_POW
:
4833 /* SIMD16 is only allowed on Gen7+. */
4834 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4835 MIN2(8, inst
->exec_size
));
4837 case SHADER_OPCODE_INT_QUOTIENT
:
4838 case SHADER_OPCODE_INT_REMAINDER
:
4839 /* Integer division is limited to SIMD8 on all generations. */
4840 return MIN2(8, inst
->exec_size
);
4842 case FS_OPCODE_LINTERP
:
4843 case FS_OPCODE_GET_BUFFER_SIZE
:
4844 case FS_OPCODE_DDX_COARSE
:
4845 case FS_OPCODE_DDX_FINE
:
4846 case FS_OPCODE_DDY_COARSE
:
4847 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
4848 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
4849 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
4850 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
4851 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
4852 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
4853 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
4854 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
4855 return MIN2(16, inst
->exec_size
);
4857 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4858 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
4859 * message used to implement varying pull constant loads, so expand it
4860 * to SIMD16. An alternative with longer message payload length but
4861 * shorter return payload would be to use the SIMD8 sampler message that
4862 * takes (header, u, v, r) as parameters instead of (header, u).
4864 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
4866 case FS_OPCODE_DDY_FINE
:
4867 /* The implementation of this virtual opcode may require emitting
4868 * compressed Align16 instructions, which are severely limited on some
4871 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
4872 * Region Restrictions):
4874 * "In Align16 access mode, SIMD16 is not allowed for DW operations
4875 * and SIMD8 is not allowed for DF operations."
4877 * In this context, "DW operations" means "operations acting on 32-bit
4878 * values", so it includes operations on floats.
4880 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
4881 * (Instruction Compression -> Rules and Restrictions):
4883 * "A compressed instruction must be in Align1 access mode. Align16
4884 * mode instructions cannot be compressed."
4886 * Similar text exists in the g45 PRM.
4888 * Empirically, compressed align16 instructions using odd register
4889 * numbers don't appear to work on Sandybridge either.
4891 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
4892 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
4893 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
4895 case SHADER_OPCODE_MULH
:
4896 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4897 * is 8-wide on Gen7+.
4899 return (devinfo
->gen
>= 7 ? 8 :
4900 get_fpu_lowered_simd_width(devinfo
, inst
));
4902 case FS_OPCODE_FB_WRITE_LOGICAL
:
4903 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4906 assert(devinfo
->gen
!= 6 ||
4907 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4908 inst
->exec_size
== 8);
4909 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4910 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4911 8 : MIN2(16, inst
->exec_size
));
4913 case SHADER_OPCODE_TEX_LOGICAL
:
4914 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4915 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4916 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4917 case SHADER_OPCODE_LOD_LOGICAL
:
4918 case SHADER_OPCODE_TG4_LOGICAL
:
4919 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4920 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4921 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4922 return get_sampler_lowered_simd_width(devinfo
, inst
);
4924 case SHADER_OPCODE_TXD_LOGICAL
:
4925 /* TXD is unsupported in SIMD16 mode. */
4928 case SHADER_OPCODE_TXL_LOGICAL
:
4929 case FS_OPCODE_TXB_LOGICAL
:
4930 /* Only one execution size is representable pre-ILK depending on whether
4931 * the shadow reference argument is present.
4933 if (devinfo
->gen
== 4)
4934 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
4936 return get_sampler_lowered_simd_width(devinfo
, inst
);
4938 case SHADER_OPCODE_TXF_LOGICAL
:
4939 case SHADER_OPCODE_TXS_LOGICAL
:
4940 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4941 * messages. Use SIMD16 instead.
4943 if (devinfo
->gen
== 4)
4946 return get_sampler_lowered_simd_width(devinfo
, inst
);
4948 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4949 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4950 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4953 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4954 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4955 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4956 return MIN2(16, inst
->exec_size
);
4958 case SHADER_OPCODE_URB_READ_SIMD8
:
4959 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
4960 case SHADER_OPCODE_URB_WRITE_SIMD8
:
4961 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
4962 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
4963 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
4964 return MIN2(8, inst
->exec_size
);
4966 case SHADER_OPCODE_MOV_INDIRECT
:
4967 /* Prior to Broadwell, we only have 8 address subregisters */
4968 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
4969 2 * REG_SIZE
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
4972 case SHADER_OPCODE_LOAD_PAYLOAD
: {
4973 const unsigned reg_count
=
4974 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
4976 if (reg_count
> 2) {
4977 /* Only LOAD_PAYLOAD instructions with per-channel destination region
4978 * can be easily lowered (which excludes headers and heterogeneous
4981 assert(!inst
->header_size
);
4982 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4983 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
4984 inst
->src
[i
].file
== BAD_FILE
);
4986 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4988 return inst
->exec_size
;
4992 return inst
->exec_size
;
4997 * Return true if splitting out the group of channels of instruction \p inst
4998 * given by lbld.group() requires allocating a temporary for the i-th source
4999 * of the lowered instruction.
5002 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
5004 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
5005 (inst
->components_read(i
) == 1 &&
5006 lbld
.dispatch_width() <= inst
->exec_size
));
5010 * Extract the data that would be consumed by the channel group given by
5011 * lbld.group() from the i-th source region of instruction \p inst and return
5012 * it as result in packed form. If any copy instructions are required they
5013 * will be emitted before the given \p inst in \p block.
5016 emit_unzip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
,
5019 /* Specified channel group from the source region. */
5020 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group());
5022 if (needs_src_copy(lbld
, inst
, i
)) {
5023 /* Builder of the right width to perform the copy avoiding uninitialized
5024 * data if the lowered execution size is greater than the original
5025 * execution size of the instruction.
5027 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5028 inst
->exec_size
), 0);
5029 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
5031 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
5032 cbld
.at(block
, inst
)
5033 .MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
5037 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
5038 /* The source is invariant for all dispatch_width-wide groups of the
5041 return inst
->src
[i
];
5044 /* We can just point the lowered instruction at the right channel group
5045 * from the original region.
5052 * Return true if splitting out the group of channels of instruction \p inst
5053 * given by lbld.group() requires allocating a temporary for the destination
5054 * of the lowered instruction and copying the data back to the original
5055 * destination region.
5058 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
5060 /* If the instruction writes more than one component we'll have to shuffle
5061 * the results of multiple lowered instructions in order to make sure that
5062 * they end up arranged correctly in the original destination region.
5064 if (inst
->regs_written
* REG_SIZE
>
5065 inst
->dst
.component_size(inst
->exec_size
))
5068 /* If the lowered execution size is larger than the original the result of
5069 * the instruction won't fit in the original destination, so we'll have to
5070 * allocate a temporary in any case.
5072 if (lbld
.dispatch_width() > inst
->exec_size
)
5075 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5076 /* If we already made a copy of the source for other reasons there won't
5077 * be any overlap with the destination.
5079 if (needs_src_copy(lbld
, inst
, i
))
5082 /* In order to keep the logic simple we emit a copy whenever the
5083 * destination region doesn't exactly match an overlapping source, which
5084 * may point at the source and destination not being aligned group by
5085 * group which could cause one of the lowered instructions to overwrite
5086 * the data read from the same source by other lowered instructions.
5088 if (regions_overlap(inst
->dst
, inst
->regs_written
* REG_SIZE
,
5089 inst
->src
[i
], inst
->regs_read(i
) * REG_SIZE
) &&
5090 !inst
->dst
.equals(inst
->src
[i
]))
5098 * Insert data from a packed temporary into the channel group given by
5099 * lbld.group() of the destination region of instruction \p inst and return
5100 * the temporary as result. If any copy instructions are required they will
5101 * be emitted around the given \p inst in \p block.
5104 emit_zip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
)
5106 /* Builder of the right width to perform the copy avoiding uninitialized
5107 * data if the lowered execution size is greater than the original
5108 * execution size of the instruction.
5110 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5111 inst
->exec_size
), 0);
5113 /* Specified channel group from the destination region. */
5114 const fs_reg dst
= horiz_offset(inst
->dst
, lbld
.group());
5115 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
5116 inst
->dst
.component_size(inst
->exec_size
);
5118 if (needs_dst_copy(lbld
, inst
)) {
5119 const fs_reg tmp
= lbld
.vgrf(inst
->dst
.type
, dst_size
);
5121 if (inst
->predicate
) {
5122 /* Handle predication by copying the original contents of
5123 * the destination into the temporary before emitting the
5124 * lowered instruction.
5126 for (unsigned k
= 0; k
< dst_size
; ++k
)
5127 cbld
.at(block
, inst
)
5128 .MOV(offset(tmp
, lbld
, k
), offset(dst
, inst
->exec_size
, k
));
5131 for (unsigned k
= 0; k
< dst_size
; ++k
)
5132 cbld
.at(block
, inst
->next
)
5133 .MOV(offset(dst
, inst
->exec_size
, k
), offset(tmp
, lbld
, k
));
5138 /* No need to allocate a temporary for the lowered instruction, just
5139 * take the right group of channels from the original region.
5146 fs_visitor::lower_simd_width()
5148 bool progress
= false;
5150 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5151 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5153 if (lower_width
!= inst
->exec_size
) {
5154 /* Builder matching the original instruction. We may also need to
5155 * emit an instruction of width larger than the original, set the
5156 * execution size of the builder to the highest of both for now so
5157 * we're sure that both cases can be handled.
5159 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5160 const fs_builder ibld
= bld
.at(block
, inst
)
5161 .exec_all(inst
->force_writemask_all
)
5162 .group(max_width
, inst
->group
/ max_width
);
5164 /* Split the copies in chunks of the execution width of either the
5165 * original or the lowered instruction, whichever is lower.
5167 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5168 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
5169 inst
->dst
.component_size(inst
->exec_size
);
5171 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5173 for (unsigned i
= 0; i
< n
; i
++) {
5174 /* Emit a copy of the original instruction with the lowered width.
5175 * If the EOT flag was set throw it away except for the last
5176 * instruction to avoid killing the thread prematurely.
5178 fs_inst split_inst
= *inst
;
5179 split_inst
.exec_size
= lower_width
;
5180 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
5182 /* Select the correct channel enables for the i-th group, then
5183 * transform the sources and destination and emit the lowered
5186 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5188 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5189 split_inst
.src
[j
] = emit_unzip(lbld
, block
, inst
, j
);
5191 split_inst
.dst
= emit_zip(lbld
, block
, inst
);
5192 split_inst
.regs_written
= DIV_ROUND_UP(
5193 split_inst
.dst
.component_size(lower_width
) * dst_size
,
5196 lbld
.emit(split_inst
);
5199 inst
->remove(block
);
5205 invalidate_live_intervals();
5211 fs_visitor::dump_instructions()
5213 dump_instructions(NULL
);
5217 fs_visitor::dump_instructions(const char *name
)
5219 FILE *file
= stderr
;
5220 if (name
&& geteuid() != 0) {
5221 file
= fopen(name
, "w");
5227 calculate_register_pressure();
5228 int ip
= 0, max_pressure
= 0;
5229 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5230 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5231 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5232 dump_instruction(inst
, file
);
5235 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5238 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5239 fprintf(file
, "%4d: ", ip
++);
5240 dump_instruction(inst
, file
);
5244 if (file
!= stderr
) {
5250 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5252 dump_instruction(be_inst
, stderr
);
5256 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5258 fs_inst
*inst
= (fs_inst
*)be_inst
;
5260 if (inst
->predicate
) {
5261 fprintf(file
, "(%cf0.%d) ",
5262 inst
->predicate_inverse
? '-' : '+',
5266 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5268 fprintf(file
, ".sat");
5269 if (inst
->conditional_mod
) {
5270 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5271 if (!inst
->predicate
&&
5272 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5273 inst
->opcode
!= BRW_OPCODE_IF
&&
5274 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5275 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
5278 fprintf(file
, "(%d) ", inst
->exec_size
);
5281 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5285 fprintf(file
, "(EOT) ");
5288 switch (inst
->dst
.file
) {
5290 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
5291 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
5292 inst
->dst
.subreg_offset
)
5293 fprintf(file
, "+%d.%d",
5294 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
5297 fprintf(file
, "g%d", inst
->dst
.nr
);
5300 fprintf(file
, "m%d", inst
->dst
.nr
);
5303 fprintf(file
, "(null)");
5306 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
5309 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
5312 switch (inst
->dst
.nr
) {
5314 fprintf(file
, "null");
5316 case BRW_ARF_ADDRESS
:
5317 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
5319 case BRW_ARF_ACCUMULATOR
:
5320 fprintf(file
, "acc%d", inst
->dst
.subnr
);
5323 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5326 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5329 if (inst
->dst
.subnr
)
5330 fprintf(file
, "+%d", inst
->dst
.subnr
);
5333 unreachable("not reached");
5335 if (inst
->dst
.stride
!= 1)
5336 fprintf(file
, "<%u>", inst
->dst
.stride
);
5337 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
5339 for (int i
= 0; i
< inst
->sources
; i
++) {
5340 if (inst
->src
[i
].negate
)
5342 if (inst
->src
[i
].abs
)
5344 switch (inst
->src
[i
].file
) {
5346 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
5347 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
5348 inst
->src
[i
].subreg_offset
)
5349 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
5350 inst
->src
[i
].subreg_offset
);
5353 fprintf(file
, "g%d", inst
->src
[i
].nr
);
5356 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
5359 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
5362 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
5363 if (inst
->src
[i
].subreg_offset
) {
5364 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
5365 inst
->src
[i
].subreg_offset
);
5369 fprintf(file
, "(null)");
5372 switch (inst
->src
[i
].type
) {
5373 case BRW_REGISTER_TYPE_F
:
5374 fprintf(file
, "%-gf", inst
->src
[i
].f
);
5376 case BRW_REGISTER_TYPE_DF
:
5377 fprintf(file
, "%fdf", inst
->src
[i
].df
);
5379 case BRW_REGISTER_TYPE_W
:
5380 case BRW_REGISTER_TYPE_D
:
5381 fprintf(file
, "%dd", inst
->src
[i
].d
);
5383 case BRW_REGISTER_TYPE_UW
:
5384 case BRW_REGISTER_TYPE_UD
:
5385 fprintf(file
, "%uu", inst
->src
[i
].ud
);
5387 case BRW_REGISTER_TYPE_VF
:
5388 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
5389 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
5390 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
5391 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
5392 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5395 fprintf(file
, "???");
5400 switch (inst
->src
[i
].nr
) {
5402 fprintf(file
, "null");
5404 case BRW_ARF_ADDRESS
:
5405 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5407 case BRW_ARF_ACCUMULATOR
:
5408 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5411 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5414 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5417 if (inst
->src
[i
].subnr
)
5418 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
5421 if (inst
->src
[i
].abs
)
5424 if (inst
->src
[i
].file
!= IMM
) {
5426 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5427 unsigned hstride
= inst
->src
[i
].hstride
;
5428 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5430 stride
= inst
->src
[i
].stride
;
5433 fprintf(file
, "<%u>", stride
);
5435 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
5438 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5439 fprintf(file
, ", ");
5444 if (inst
->force_writemask_all
)
5445 fprintf(file
, "NoMask ");
5447 if (inst
->exec_size
!= dispatch_width
)
5448 fprintf(file
, "group%d ", inst
->group
);
5450 fprintf(file
, "\n");
5454 * Possibly returns an instruction that set up @param reg.
5456 * Sometimes we want to take the result of some expression/variable
5457 * dereference tree and rewrite the instruction generating the result
5458 * of the tree. When processing the tree, we know that the
5459 * instructions generated are all writing temporaries that are dead
5460 * outside of this tree. So, if we have some instructions that write
5461 * a temporary, we're free to point that temp write somewhere else.
5463 * Note that this doesn't guarantee that the instruction generated
5464 * only reg -- it might be the size=4 destination of a texture instruction.
5467 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5472 end
->is_partial_write() ||
5473 !reg
.equals(end
->dst
)) {
5481 fs_visitor::setup_fs_payload_gen6()
5483 assert(stage
== MESA_SHADER_FRAGMENT
);
5484 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5486 unsigned barycentric_interp_modes
=
5487 (stage
== MESA_SHADER_FRAGMENT
) ?
5488 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
5490 assert(devinfo
->gen
>= 6);
5492 /* R0-1: masks, pixel X/Y coordinates. */
5493 payload
.num_regs
= 2;
5494 /* R2: only for 32-pixel dispatch.*/
5496 /* R3-26: barycentric interpolation coordinates. These appear in the
5497 * same order that they appear in the brw_barycentric_mode
5498 * enum. Each set of coordinates occupies 2 registers if dispatch width
5499 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5500 * appear if they were enabled using the "Barycentric Interpolation
5501 * Mode" bits in WM_STATE.
5503 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
5504 if (barycentric_interp_modes
& (1 << i
)) {
5505 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5506 payload
.num_regs
+= 2;
5507 if (dispatch_width
== 16) {
5508 payload
.num_regs
+= 2;
5513 /* R27: interpolated depth if uses source depth */
5514 prog_data
->uses_src_depth
=
5515 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5516 if (prog_data
->uses_src_depth
) {
5517 payload
.source_depth_reg
= payload
.num_regs
;
5519 if (dispatch_width
== 16) {
5520 /* R28: interpolated depth if not SIMD8. */
5525 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5526 prog_data
->uses_src_w
=
5527 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5528 if (prog_data
->uses_src_w
) {
5529 payload
.source_w_reg
= payload
.num_regs
;
5531 if (dispatch_width
== 16) {
5532 /* R30: interpolated W if not SIMD8. */
5537 /* R31: MSAA position offsets. */
5538 if (prog_data
->persample_dispatch
&&
5539 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
)) {
5540 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
5542 * "MSDISPMODE_PERSAMPLE is required in order to select
5545 * So we can only really get sample positions if we are doing real
5546 * per-sample dispatch. If we need gl_SamplePosition and we don't have
5547 * persample dispatch, we hard-code it to 0.5.
5549 prog_data
->uses_pos_offset
= true;
5550 payload
.sample_pos_reg
= payload
.num_regs
;
5554 /* R32: MSAA input coverage mask */
5555 prog_data
->uses_sample_mask
=
5556 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5557 if (prog_data
->uses_sample_mask
) {
5558 assert(devinfo
->gen
>= 7);
5559 payload
.sample_mask_in_reg
= payload
.num_regs
;
5561 if (dispatch_width
== 16) {
5562 /* R33: input coverage mask if not SIMD8. */
5567 /* R34-: bary for 32-pixel. */
5568 /* R58-59: interp W for 32-pixel. */
5570 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5571 source_depth_to_render_target
= true;
5576 fs_visitor::setup_vs_payload()
5578 /* R0: thread header, R1: urb handles */
5579 payload
.num_regs
= 2;
5583 fs_visitor::setup_gs_payload()
5585 assert(stage
== MESA_SHADER_GEOMETRY
);
5587 struct brw_gs_prog_data
*gs_prog_data
=
5588 (struct brw_gs_prog_data
*) prog_data
;
5589 struct brw_vue_prog_data
*vue_prog_data
=
5590 (struct brw_vue_prog_data
*) prog_data
;
5592 /* R0: thread header, R1: output URB handles */
5593 payload
.num_regs
= 2;
5595 if (gs_prog_data
->include_primitive_id
) {
5596 /* R2: Primitive ID 0..7 */
5600 /* Use a maximum of 24 registers for push-model inputs. */
5601 const unsigned max_push_components
= 24;
5603 /* If pushing our inputs would take too many registers, reduce the URB read
5604 * length (which is in HWords, or 8 registers), and resort to pulling.
5606 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5607 * have to multiply by VerticesIn to obtain the total storage requirement.
5609 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5610 max_push_components
|| gs_prog_data
->invocations
> 1) {
5611 gs_prog_data
->base
.include_vue_handles
= true;
5613 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5614 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5616 vue_prog_data
->urb_read_length
=
5617 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5622 fs_visitor::setup_cs_payload()
5624 assert(devinfo
->gen
>= 7);
5625 payload
.num_regs
= 1;
5629 fs_visitor::calculate_register_pressure()
5631 invalidate_live_intervals();
5632 calculate_live_intervals();
5634 unsigned num_instructions
= 0;
5635 foreach_block(block
, cfg
)
5636 num_instructions
+= block
->instructions
.length();
5638 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5640 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5641 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5642 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5647 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
5649 * The needs_unlit_centroid_workaround ends up producing one of these per
5650 * channel of centroid input, so it's good to clean them up.
5652 * An assumption here is that nothing ever modifies the dispatched pixels
5653 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
5654 * dictates that anyway.
5657 fs_visitor::opt_drop_redundant_mov_to_flags()
5659 bool flag_mov_found
[2] = {false};
5660 bool progress
= false;
5662 /* Instructions removed by this pass can only be added if this were true */
5663 if (!devinfo
->needs_unlit_centroid_workaround
)
5666 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5667 if (inst
->is_control_flow()) {
5668 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
5669 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
5670 if (!flag_mov_found
[inst
->flag_subreg
]) {
5671 flag_mov_found
[inst
->flag_subreg
] = true;
5673 inst
->remove(block
);
5676 } else if (inst
->flags_written()) {
5677 flag_mov_found
[inst
->flag_subreg
] = false;
5685 fs_visitor::optimize()
5687 /* Start by validating the shader we currently have. */
5690 /* bld is the common builder object pointing at the end of the program we
5691 * used to translate it into i965 IR. For the optimization and lowering
5692 * passes coming next, any code added after the end of the program without
5693 * having explicitly called fs_builder::at() clearly points at a mistake.
5694 * Ideally optimization passes wouldn't be part of the visitor so they
5695 * wouldn't have access to bld at all, but they do, so just in case some
5696 * pass forgets to ask for a location explicitly set it to NULL here to
5697 * make it trip. The dispatch width is initialized to a bogus value to
5698 * make sure that optimizations set the execution controls explicitly to
5699 * match the code they are manipulating instead of relying on the defaults.
5701 bld
= fs_builder(this, 64);
5703 assign_constant_locations();
5704 lower_constant_loads();
5708 split_virtual_grfs();
5711 #define OPT(pass, args...) ({ \
5713 bool this_progress = pass(args); \
5715 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5716 char filename[64]; \
5717 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5718 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5720 backend_shader::dump_instructions(filename); \
5725 progress = progress || this_progress; \
5729 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5731 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5732 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5734 backend_shader::dump_instructions(filename
);
5737 bool progress
= false;
5741 OPT(opt_drop_redundant_mov_to_flags
);
5748 OPT(remove_duplicate_mrf_writes
);
5752 OPT(opt_copy_propagate
);
5753 OPT(opt_predicated_break
, this);
5754 OPT(opt_cmod_propagation
);
5755 OPT(dead_code_eliminate
);
5756 OPT(opt_peephole_sel
);
5757 OPT(dead_control_flow_eliminate
, this);
5758 OPT(opt_register_renaming
);
5759 OPT(opt_saturate_propagation
);
5760 OPT(register_coalesce
);
5761 OPT(compute_to_mrf
);
5762 OPT(eliminate_find_live_channel
);
5764 OPT(compact_virtual_grfs
);
5770 if (OPT(lower_pack
)) {
5771 OPT(register_coalesce
);
5772 OPT(dead_code_eliminate
);
5775 if (OPT(lower_d2x
)) {
5776 OPT(opt_copy_propagate
);
5777 OPT(dead_code_eliminate
);
5780 OPT(lower_simd_width
);
5782 /* After SIMD lowering just in case we had to unroll the EOT send. */
5783 OPT(opt_sampler_eot
);
5785 OPT(lower_logical_sends
);
5788 OPT(opt_copy_propagate
);
5789 /* Only run after logical send lowering because it's easier to implement
5790 * in terms of physical sends.
5792 if (OPT(opt_zero_samples
))
5793 OPT(opt_copy_propagate
);
5794 /* Run after logical send lowering to give it a chance to CSE the
5795 * LOAD_PAYLOAD instructions created to construct the payloads of
5796 * e.g. texturing messages in cases where it wasn't possible to CSE the
5797 * whole logical instruction.
5800 OPT(register_coalesce
);
5801 OPT(compute_to_mrf
);
5802 OPT(dead_code_eliminate
);
5803 OPT(remove_duplicate_mrf_writes
);
5804 OPT(opt_peephole_sel
);
5807 OPT(opt_redundant_discard_jumps
);
5809 if (OPT(lower_load_payload
)) {
5810 split_virtual_grfs();
5811 OPT(register_coalesce
);
5812 OPT(compute_to_mrf
);
5813 OPT(dead_code_eliminate
);
5816 OPT(opt_combine_constants
);
5817 OPT(lower_integer_multiplication
);
5819 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5820 OPT(opt_cmod_propagation
);
5822 OPT(opt_copy_propagate
);
5823 OPT(dead_code_eliminate
);
5826 lower_uniform_pull_constant_loads();
5832 * Three source instruction must have a GRF/MRF destination register.
5833 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5836 fs_visitor::fixup_3src_null_dest()
5838 bool progress
= false;
5840 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5841 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
5842 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5849 invalidate_live_intervals();
5853 fs_visitor::allocate_registers(bool allow_spilling
)
5855 bool allocated_without_spills
;
5857 static const enum instruction_scheduler_mode pre_modes
[] = {
5859 SCHEDULE_PRE_NON_LIFO
,
5863 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
5865 /* Try each scheduling heuristic to see if it can successfully register
5866 * allocate without spilling. They should be ordered by decreasing
5867 * performance but increasing likelihood of allocating.
5869 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5870 schedule_instructions(pre_modes
[i
]);
5873 assign_regs_trivial();
5874 allocated_without_spills
= true;
5876 allocated_without_spills
= assign_regs(false, spill_all
);
5878 if (allocated_without_spills
)
5882 if (!allocated_without_spills
) {
5883 /* We assume that any spilling is worse than just dropping back to
5884 * SIMD8. There's probably actually some intermediate point where
5885 * SIMD16 with a couple of spills is still better.
5887 if (dispatch_width
> min_dispatch_width
) {
5888 fail("Failure to register allocate. Reduce number of "
5889 "live scalar values to avoid this.");
5891 compiler
->shader_perf_log(log_data
,
5892 "%s shader triggered register spilling. "
5893 "Try reducing the number of live scalar "
5894 "values to improve performance.\n",
5898 /* Since we're out of heuristics, just go spill registers until we
5899 * get an allocation.
5901 while (!assign_regs(true, spill_all
)) {
5907 assert(last_scratch
== 0 || allow_spilling
);
5909 /* This must come after all optimization and register allocation, since
5910 * it inserts dead code that happens to have side effects, and it does
5911 * so based on the actual physical registers in use.
5913 insert_gen4_send_dependency_workarounds();
5918 schedule_instructions(SCHEDULE_POST
);
5920 if (last_scratch
> 0) {
5921 unsigned max_scratch_size
= 2 * 1024 * 1024;
5923 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5925 if (stage
== MESA_SHADER_COMPUTE
) {
5926 if (devinfo
->is_haswell
) {
5927 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5928 * field documentation, Haswell supports a minimum of 2kB of
5929 * scratch space for compute shaders, unlike every other stage
5932 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
5933 } else if (devinfo
->gen
<= 7) {
5934 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5935 * field documentation, platforms prior to Haswell measure scratch
5936 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
5938 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
5939 max_scratch_size
= 12 * 1024;
5943 /* We currently only support up to 2MB of scratch space. If we
5944 * need to support more eventually, the documentation suggests
5945 * that we could allocate a larger buffer, and partition it out
5946 * ourselves. We'd just have to undo the hardware's address
5947 * calculation by subtracting (FFTID * Per Thread Scratch Space)
5948 * and then add FFTID * (Larger Per Thread Scratch Space).
5950 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
5951 * Thread Group Tracking > Local Memory/Scratch Space.
5953 assert(prog_data
->total_scratch
< max_scratch_size
);
5958 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5960 assert(stage
== MESA_SHADER_VERTEX
);
5964 if (shader_time_index
>= 0)
5965 emit_shader_time_begin();
5972 compute_clip_distance(clip_planes
);
5976 if (shader_time_index
>= 0)
5977 emit_shader_time_end();
5983 assign_curb_setup();
5984 assign_vs_urb_setup();
5986 fixup_3src_null_dest();
5987 allocate_registers(true);
5993 fs_visitor::run_tcs_single_patch()
5995 assert(stage
== MESA_SHADER_TESS_CTRL
);
5997 struct brw_tcs_prog_data
*tcs_prog_data
=
5998 (struct brw_tcs_prog_data
*) prog_data
;
6000 /* r1-r4 contain the ICP handles. */
6001 payload
.num_regs
= 5;
6003 if (shader_time_index
>= 0)
6004 emit_shader_time_begin();
6006 /* Initialize gl_InvocationID */
6007 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
6008 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6009 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
6010 bld
.MOV(channels_ud
, channels_uw
);
6012 if (tcs_prog_data
->instances
== 1) {
6013 invocation_id
= channels_ud
;
6015 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6017 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
6018 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6019 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6020 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
6021 brw_imm_ud(INTEL_MASK(23, 17)));
6022 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
6024 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
6027 /* Fix the disptach mask */
6028 if (nir
->info
.tcs
.vertices_out
% 8) {
6029 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
6030 brw_imm_ud(nir
->info
.tcs
.vertices_out
), BRW_CONDITIONAL_L
);
6031 bld
.IF(BRW_PREDICATE_NORMAL
);
6036 if (nir
->info
.tcs
.vertices_out
% 8) {
6037 bld
.emit(BRW_OPCODE_ENDIF
);
6040 /* Emit EOT write; set TR DS Cache bit */
6042 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
6043 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
6044 fs_reg(brw_imm_ud(0)),
6046 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
6047 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
6049 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
6050 bld
.null_reg_ud(), payload
);
6054 if (shader_time_index
>= 0)
6055 emit_shader_time_end();
6064 assign_curb_setup();
6065 assign_tcs_single_patch_urb_setup();
6067 fixup_3src_null_dest();
6068 allocate_registers(true);
6074 fs_visitor::run_tes()
6076 assert(stage
== MESA_SHADER_TESS_EVAL
);
6078 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6079 payload
.num_regs
= 5;
6081 if (shader_time_index
>= 0)
6082 emit_shader_time_begin();
6091 if (shader_time_index
>= 0)
6092 emit_shader_time_end();
6098 assign_curb_setup();
6099 assign_tes_urb_setup();
6101 fixup_3src_null_dest();
6102 allocate_registers(true);
6108 fs_visitor::run_gs()
6110 assert(stage
== MESA_SHADER_GEOMETRY
);
6114 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6116 if (gs_compile
->control_data_header_size_bits
> 0) {
6117 /* Create a VGRF to store accumulated control data bits. */
6118 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6120 /* If we're outputting more than 32 control data bits, then EmitVertex()
6121 * will set control_data_bits to 0 after emitting the first vertex.
6122 * Otherwise, we need to initialize it to 0 here.
6124 if (gs_compile
->control_data_header_size_bits
<= 32) {
6125 const fs_builder abld
= bld
.annotate("initialize control data bits");
6126 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6130 if (shader_time_index
>= 0)
6131 emit_shader_time_begin();
6135 emit_gs_thread_end();
6137 if (shader_time_index
>= 0)
6138 emit_shader_time_end();
6147 assign_curb_setup();
6148 assign_gs_urb_setup();
6150 fixup_3src_null_dest();
6151 allocate_registers(true);
6157 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6159 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
6160 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6162 assert(stage
== MESA_SHADER_FRAGMENT
);
6164 if (devinfo
->gen
>= 6)
6165 setup_fs_payload_gen6();
6167 setup_fs_payload_gen4();
6171 } else if (do_rep_send
) {
6172 assert(dispatch_width
== 16);
6173 emit_repclear_shader();
6175 if (shader_time_index
>= 0)
6176 emit_shader_time_begin();
6178 calculate_urb_setup();
6179 if (nir
->info
.inputs_read
> 0) {
6180 if (devinfo
->gen
< 6)
6181 emit_interpolation_setup_gen4();
6183 emit_interpolation_setup_gen6();
6186 /* We handle discards by keeping track of the still-live pixels in f0.1.
6187 * Initialize it with the dispatched pixels.
6189 if (wm_prog_data
->uses_kill
) {
6190 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
6191 discard_init
->flag_subreg
= 1;
6194 /* Generate FS IR for main(). (the visitor only descends into
6195 * functions called "main").
6202 if (wm_prog_data
->uses_kill
)
6203 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6205 if (wm_key
->alpha_test_func
)
6210 if (shader_time_index
>= 0)
6211 emit_shader_time_end();
6217 assign_curb_setup();
6220 fixup_3src_null_dest();
6221 allocate_registers(allow_spilling
);
6231 fs_visitor::run_cs()
6233 assert(stage
== MESA_SHADER_COMPUTE
);
6237 if (shader_time_index
>= 0)
6238 emit_shader_time_begin();
6240 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6241 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6242 const fs_builder abld
= bld
.exec_all().group(1, 0);
6243 abld
.MOV(retype(suboffset(brw_sr0_reg(), 1), BRW_REGISTER_TYPE_UW
),
6244 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6252 emit_cs_terminate();
6254 if (shader_time_index
>= 0)
6255 emit_shader_time_end();
6261 assign_curb_setup();
6263 fixup_3src_null_dest();
6264 allocate_registers(true);
6273 * Return a bitfield where bit n is set if barycentric interpolation mode n
6274 * (see enum brw_barycentric_mode) is needed by the fragment shader.
6276 * We examine the load_barycentric intrinsics rather than looking at input
6277 * variables so that we catch interpolateAtCentroid() messages too, which
6278 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
6281 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
6282 const nir_shader
*shader
)
6284 unsigned barycentric_interp_modes
= 0;
6286 nir_foreach_function(f
, shader
) {
6290 nir_foreach_block(block
, f
->impl
) {
6291 nir_foreach_instr(instr
, block
) {
6292 if (instr
->type
!= nir_instr_type_intrinsic
)
6295 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6296 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6299 /* Ignore WPOS; it doesn't require interpolation. */
6300 if (nir_intrinsic_base(intrin
) == VARYING_SLOT_POS
)
6303 intrin
= nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6304 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
6305 nir_intrinsic_interp_mode(intrin
);
6306 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
6307 enum brw_barycentric_mode bary
=
6308 brw_barycentric_mode(interp
, bary_op
);
6310 barycentric_interp_modes
|= 1 << bary
;
6312 if (devinfo
->needs_unlit_centroid_workaround
&&
6313 bary_op
== nir_intrinsic_load_barycentric_centroid
)
6314 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
6319 return barycentric_interp_modes
;
6323 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
6324 const nir_shader
*shader
)
6326 prog_data
->flat_inputs
= 0;
6328 nir_foreach_variable(var
, &shader
->inputs
) {
6329 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
6331 if (input_index
< 0)
6335 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6336 prog_data
->flat_inputs
|= (1 << input_index
);
6341 computed_depth_mode(const nir_shader
*shader
)
6343 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6344 switch (shader
->info
.fs
.depth_layout
) {
6345 case FRAG_DEPTH_LAYOUT_NONE
:
6346 case FRAG_DEPTH_LAYOUT_ANY
:
6347 return BRW_PSCDEPTH_ON
;
6348 case FRAG_DEPTH_LAYOUT_GREATER
:
6349 return BRW_PSCDEPTH_ON_GE
;
6350 case FRAG_DEPTH_LAYOUT_LESS
:
6351 return BRW_PSCDEPTH_ON_LE
;
6352 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
6353 return BRW_PSCDEPTH_OFF
;
6356 return BRW_PSCDEPTH_OFF
;
6360 * Move load_interpolated_input with simple (payload-based) barycentric modes
6361 * to the top of the program so we don't emit multiple PLNs for the same input.
6363 * This works around CSE not being able to handle non-dominating cases
6369 * interpolate the same exact input
6372 * This should be replaced by global value numbering someday.
6375 move_interpolation_to_top(nir_shader
*nir
)
6377 nir_foreach_function(f
, nir
) {
6381 nir_block
*top
= nir_start_block(f
->impl
);
6382 exec_node
*cursor_node
= NULL
;
6384 nir_foreach_block(block
, f
->impl
) {
6388 nir_foreach_instr_safe(instr
, block
) {
6389 if (instr
->type
!= nir_instr_type_intrinsic
)
6392 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6393 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6395 nir_intrinsic_instr
*bary_intrinsic
=
6396 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6397 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
6399 /* Leave interpolateAtSample/Offset() where they are. */
6400 if (op
== nir_intrinsic_load_barycentric_at_sample
||
6401 op
== nir_intrinsic_load_barycentric_at_offset
)
6404 nir_instr
*move
[3] = {
6405 &bary_intrinsic
->instr
,
6406 intrin
->src
[1].ssa
->parent_instr
,
6410 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
6411 if (move
[i
]->block
!= top
) {
6412 move
[i
]->block
= top
;
6413 exec_node_remove(&move
[i
]->node
);
6415 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
6417 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
6419 cursor_node
= &move
[i
]->node
;
6424 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6425 ((unsigned) nir_metadata_block_index
|
6426 (unsigned) nir_metadata_dominance
));
6431 * Apply default interpolation settings to FS inputs which don't specify any.
6434 brw_nir_set_default_interpolation(const struct brw_device_info
*devinfo
,
6435 struct nir_shader
*nir
,
6436 bool api_flat_shade
,
6437 bool per_sample_interpolation
)
6439 assert(nir
->stage
== MESA_SHADER_FRAGMENT
);
6441 nir_foreach_variable(var
, &nir
->inputs
) {
6442 /* Apply default interpolation mode.
6444 * Everything defaults to smooth except for the legacy GL color
6445 * built-in variables, which might be flat depending on API state.
6447 if (var
->data
.interpolation
== INTERP_MODE_NONE
) {
6448 const bool flat
= api_flat_shade
&&
6449 (var
->data
.location
== VARYING_SLOT_COL0
||
6450 var
->data
.location
== VARYING_SLOT_COL1
);
6452 var
->data
.interpolation
= flat
? INTERP_MODE_FLAT
6453 : INTERP_MODE_SMOOTH
;
6456 /* Apply 'sample' if necessary for API state. */
6457 if (per_sample_interpolation
&&
6458 var
->data
.interpolation
!= INTERP_MODE_FLAT
) {
6459 var
->data
.centroid
= false;
6460 var
->data
.sample
= true;
6463 /* On Ironlake and below, there is only one interpolation mode.
6464 * Centroid interpolation doesn't mean anything on this hardware --
6465 * there is no multisampling.
6467 if (devinfo
->gen
< 6) {
6468 var
->data
.centroid
= false;
6469 var
->data
.sample
= false;
6475 * Demote per-sample barycentric intrinsics to centroid.
6477 * Useful when rendering to a non-multisampled buffer.
6480 demote_sample_qualifiers(nir_shader
*nir
)
6482 nir_foreach_function(f
, nir
) {
6487 nir_builder_init(&b
, f
->impl
);
6489 nir_foreach_block(block
, f
->impl
) {
6490 nir_foreach_instr_safe(instr
, block
) {
6491 if (instr
->type
!= nir_instr_type_intrinsic
)
6494 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6495 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
6496 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
6499 b
.cursor
= nir_before_instr(instr
);
6500 nir_ssa_def
*centroid
=
6501 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
6502 nir_intrinsic_interp_mode(intrin
));
6503 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
6504 nir_src_for_ssa(centroid
));
6505 nir_instr_remove(instr
);
6509 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6510 ((unsigned) nir_metadata_block_index
|
6511 (unsigned) nir_metadata_dominance
));
6516 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
6518 const struct brw_wm_prog_key
*key
,
6519 struct brw_wm_prog_data
*prog_data
,
6520 const nir_shader
*src_shader
,
6521 struct gl_program
*prog
,
6522 int shader_time_index8
, int shader_time_index16
,
6523 bool allow_spilling
,
6525 unsigned *final_assembly_size
,
6528 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6529 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6531 brw_nir_set_default_interpolation(compiler
->devinfo
, shader
,
6532 key
->flat_shade
, key
->persample_interp
);
6533 brw_nir_lower_fs_inputs(shader
);
6534 brw_nir_lower_fs_outputs(shader
);
6535 if (!key
->multisample_fbo
)
6536 NIR_PASS_V(shader
, demote_sample_qualifiers
);
6537 NIR_PASS_V(shader
, move_interpolation_to_top
);
6538 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6540 /* key->alpha_test_func means simulating alpha testing via discards,
6541 * so the shader definitely kills pixels.
6543 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
6544 prog_data
->uses_omask
= key
->multisample_fbo
&&
6545 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
6546 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
6547 prog_data
->computed_stencil
=
6548 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
6550 prog_data
->persample_dispatch
=
6551 key
->multisample_fbo
&&
6552 (key
->persample_interp
||
6553 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
6554 SYSTEM_BIT_SAMPLE_POS
)) ||
6555 shader
->info
.fs
.uses_sample_qualifier
);
6557 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
6559 prog_data
->barycentric_interp_modes
=
6560 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
6562 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
;
6563 uint8_t simd8_grf_start
= 0, simd16_grf_start
= 0;
6564 unsigned simd8_grf_used
= 0, simd16_grf_used
= 0;
6566 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
6567 &prog_data
->base
, prog
, shader
, 8,
6568 shader_time_index8
);
6569 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
6571 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
6574 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
6576 simd8_grf_start
= v8
.payload
.num_regs
;
6577 simd8_grf_used
= v8
.grf_used
;
6580 if (v8
.max_dispatch_width
>= 16 &&
6581 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
6582 /* Try a SIMD16 compile */
6583 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
6584 &prog_data
->base
, prog
, shader
, 16,
6585 shader_time_index16
);
6586 v16
.import_uniforms(&v8
);
6587 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
6588 compiler
->shader_perf_log(log_data
,
6589 "SIMD16 shader failed to compile: %s",
6592 simd16_cfg
= v16
.cfg
;
6593 simd16_grf_start
= v16
.payload
.num_regs
;
6594 simd16_grf_used
= v16
.grf_used
;
6598 /* When the caller requests a repclear shader, they want SIMD16-only */
6602 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
6603 * at the top to select the shader. We've never implemented that.
6604 * Instead, we just give them exactly one shader and we pick the widest one
6607 if (compiler
->devinfo
->gen
< 5 && simd16_cfg
)
6610 if (prog_data
->persample_dispatch
) {
6611 /* Starting with SandyBridge (where we first get MSAA), the different
6612 * pixel dispatch combinations are grouped into classifications A
6613 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
6614 * generations, the only configurations supporting persample dispatch
6615 * are are this in which only one dispatch width is enabled.
6617 * If computed depth is enabled, SNB only allows SIMD8 while IVB+
6618 * allow SIMD8 or SIMD16 so we choose SIMD16 if available.
6620 if (compiler
->devinfo
->gen
== 6 &&
6621 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
) {
6623 } else if (simd16_cfg
) {
6628 /* We have to compute the flat inputs after the visitor is finished running
6629 * because it relies on prog_data->urb_setup which is computed in
6630 * fs_visitor::calculate_urb_setup().
6632 brw_compute_flat_inputs(prog_data
, shader
);
6634 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
6635 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6636 MESA_SHADER_FRAGMENT
);
6638 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
6639 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
6640 shader
->info
.label
? shader
->info
.label
:
6642 shader
->info
.name
));
6646 prog_data
->dispatch_8
= true;
6647 g
.generate_code(simd8_cfg
, 8);
6648 prog_data
->base
.dispatch_grf_start_reg
= simd8_grf_start
;
6649 prog_data
->reg_blocks_0
= brw_register_blocks(simd8_grf_used
);
6652 prog_data
->dispatch_16
= true;
6653 prog_data
->prog_offset_2
= g
.generate_code(simd16_cfg
, 16);
6654 prog_data
->dispatch_grf_start_reg_2
= simd16_grf_start
;
6655 prog_data
->reg_blocks_2
= brw_register_blocks(simd16_grf_used
);
6657 } else if (simd16_cfg
) {
6658 prog_data
->dispatch_16
= true;
6659 g
.generate_code(simd16_cfg
, 16);
6660 prog_data
->base
.dispatch_grf_start_reg
= simd16_grf_start
;
6661 prog_data
->reg_blocks_0
= brw_register_blocks(simd16_grf_used
);
6664 return g
.get_assembly(final_assembly_size
);
6668 fs_visitor::emit_cs_work_group_id_setup()
6670 assert(stage
== MESA_SHADER_COMPUTE
);
6672 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6674 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
6675 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
6676 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
6678 bld
.MOV(*reg
, r0_1
);
6679 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
6680 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
6686 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
6688 block
->dwords
= dwords
;
6689 block
->regs
= DIV_ROUND_UP(dwords
, 8);
6690 block
->size
= block
->regs
* 32;
6694 cs_fill_push_const_info(const struct brw_device_info
*devinfo
,
6695 struct brw_cs_prog_data
*cs_prog_data
)
6697 const struct brw_stage_prog_data
*prog_data
=
6698 (struct brw_stage_prog_data
*) cs_prog_data
;
6699 bool fill_thread_id
=
6700 cs_prog_data
->thread_local_id_index
>= 0 &&
6701 cs_prog_data
->thread_local_id_index
< (int)prog_data
->nr_params
;
6702 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
6704 /* The thread ID should be stored in the last param dword */
6705 assert(prog_data
->nr_params
> 0 || !fill_thread_id
);
6706 assert(!fill_thread_id
||
6707 cs_prog_data
->thread_local_id_index
==
6708 (int)prog_data
->nr_params
- 1);
6710 unsigned cross_thread_dwords
, per_thread_dwords
;
6711 if (!cross_thread_supported
) {
6712 cross_thread_dwords
= 0u;
6713 per_thread_dwords
= prog_data
->nr_params
;
6714 } else if (fill_thread_id
) {
6715 /* Fill all but the last register with cross-thread payload */
6716 cross_thread_dwords
= 8 * (cs_prog_data
->thread_local_id_index
/ 8);
6717 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
6718 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
6720 /* Fill all data using cross-thread payload */
6721 cross_thread_dwords
= prog_data
->nr_params
;
6722 per_thread_dwords
= 0u;
6725 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
6726 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
6728 unsigned total_dwords
=
6729 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
6730 cs_prog_data
->push
.cross_thread
.size
) / 4;
6731 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
6733 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
6734 cs_prog_data
->push
.per_thread
.size
== 0);
6735 assert(cs_prog_data
->push
.cross_thread
.dwords
+
6736 cs_prog_data
->push
.per_thread
.dwords
==
6737 prog_data
->nr_params
);
6741 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
6743 cs_prog_data
->simd_size
= size
;
6744 unsigned group_size
= cs_prog_data
->local_size
[0] *
6745 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
6746 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
6750 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
6752 const struct brw_cs_prog_key
*key
,
6753 struct brw_cs_prog_data
*prog_data
,
6754 const nir_shader
*src_shader
,
6755 int shader_time_index
,
6756 unsigned *final_assembly_size
,
6759 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6760 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6762 brw_nir_lower_cs_shared(shader
);
6763 prog_data
->base
.total_shared
+= shader
->num_shared
;
6765 /* Now that we cloned the nir_shader, we can update num_uniforms based on
6766 * the thread_local_id_index.
6768 assert(prog_data
->thread_local_id_index
>= 0);
6769 shader
->num_uniforms
=
6770 MAX2(shader
->num_uniforms
,
6771 (unsigned)4 * (prog_data
->thread_local_id_index
+ 1));
6773 brw_nir_lower_intrinsics(shader
, &prog_data
->base
);
6774 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6776 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
6777 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
6778 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
6779 unsigned local_workgroup_size
=
6780 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
6781 shader
->info
.cs
.local_size
[2];
6783 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
6784 unsigned simd_required
= DIV_ROUND_UP(local_workgroup_size
, max_cs_threads
);
6787 const char *fail_msg
= NULL
;
6789 /* Now the main event: Visit the shader IR and generate our CS IR for it.
6791 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6792 NULL
, /* Never used in core profile */
6793 shader
, 8, shader_time_index
);
6794 if (simd_required
<= 8) {
6796 fail_msg
= v8
.fail_msg
;
6799 cs_set_simd_size(prog_data
, 8);
6800 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6801 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
6805 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6806 NULL
, /* Never used in core profile */
6807 shader
, 16, shader_time_index
);
6808 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
6809 !fail_msg
&& v8
.max_dispatch_width
>= 16 &&
6810 simd_required
<= 16) {
6811 /* Try a SIMD16 compile */
6812 if (simd_required
<= 8)
6813 v16
.import_uniforms(&v8
);
6814 if (!v16
.run_cs()) {
6815 compiler
->shader_perf_log(log_data
,
6816 "SIMD16 shader failed to compile: %s",
6820 "Couldn't generate SIMD16 program and not "
6821 "enough threads for SIMD8";
6825 cs_set_simd_size(prog_data
, 16);
6826 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6827 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
6831 fs_visitor
v32(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6832 NULL
, /* Never used in core profile */
6833 shader
, 32, shader_time_index
);
6834 if (!fail_msg
&& v8
.max_dispatch_width
>= 32 &&
6835 (simd_required
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
6836 /* Try a SIMD32 compile */
6837 if (simd_required
<= 8)
6838 v32
.import_uniforms(&v8
);
6839 else if (simd_required
<= 16)
6840 v32
.import_uniforms(&v16
);
6842 if (!v32
.run_cs()) {
6843 compiler
->shader_perf_log(log_data
,
6844 "SIMD32 shader failed to compile: %s",
6848 "Couldn't generate SIMD32 program and not "
6849 "enough threads for SIMD16";
6853 cs_set_simd_size(prog_data
, 32);
6854 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6858 if (unlikely(cfg
== NULL
)) {
6861 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
6866 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
6867 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6868 MESA_SHADER_COMPUTE
);
6869 if (INTEL_DEBUG
& DEBUG_CS
) {
6870 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
6871 shader
->info
.label
? shader
->info
.label
:
6874 g
.enable_debug(name
);
6877 g
.generate_code(cfg
, prog_data
->simd_size
);
6879 return g
.get_assembly(final_assembly_size
);