2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
33 #include <sys/types.h>
35 #include "main/hash_table.h"
36 #include "main/macros.h"
37 #include "main/shaderobj.h"
38 #include "main/fbobject.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/register_allocate.h"
42 #include "program/sampler.h"
43 #include "program/hash_table.h"
44 #include "brw_context.h"
49 #include "main/uniforms.h"
50 #include "glsl/glsl_types.h"
55 memset(this, 0, sizeof(*this));
56 this->opcode
= BRW_OPCODE_NOP
;
57 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
59 this->dst
= reg_undef
;
60 this->src
[0] = reg_undef
;
61 this->src
[1] = reg_undef
;
62 this->src
[2] = reg_undef
;
64 /* This will be the case for almost all instructions. */
65 this->regs_written
= 1;
73 fs_inst::fs_inst(enum opcode opcode
)
76 this->opcode
= opcode
;
79 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
)
82 this->opcode
= opcode
;
86 assert(dst
.reg_offset
>= 0);
89 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
)
92 this->opcode
= opcode
;
97 assert(dst
.reg_offset
>= 0);
98 if (src
[0].file
== GRF
)
99 assert(src
[0].reg_offset
>= 0);
102 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
105 this->opcode
= opcode
;
111 assert(dst
.reg_offset
>= 0);
112 if (src
[0].file
== GRF
)
113 assert(src
[0].reg_offset
>= 0);
114 if (src
[1].file
== GRF
)
115 assert(src
[1].reg_offset
>= 0);
118 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
,
119 fs_reg src0
, fs_reg src1
, fs_reg src2
)
122 this->opcode
= opcode
;
129 assert(dst
.reg_offset
>= 0);
130 if (src
[0].file
== GRF
)
131 assert(src
[0].reg_offset
>= 0);
132 if (src
[1].file
== GRF
)
133 assert(src
[1].reg_offset
>= 0);
134 if (src
[2].file
== GRF
)
135 assert(src
[2].reg_offset
>= 0);
140 fs_visitor::op(fs_reg dst, fs_reg src0) \
142 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0); \
147 fs_visitor::op(fs_reg dst, fs_reg src0, fs_reg src1) \
149 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1); \
154 fs_visitor::op(fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2) \
156 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1, src2);\
186 /** Gen4 predicated IF. */
188 fs_visitor::IF(uint32_t predicate
)
190 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
);
191 inst
->predicate
= predicate
;
195 /** Gen6+ IF with embedded comparison. */
197 fs_visitor::IF(fs_reg src0
, fs_reg src1
, uint32_t condition
)
199 assert(brw
->gen
>= 6);
200 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
,
201 reg_null_d
, src0
, src1
);
202 inst
->conditional_mod
= condition
;
207 * CMP: Sets the low bit of the destination channels with the result
208 * of the comparison, while the upper bits are undefined, and updates
209 * the flag register with the packed 16 bits of the result.
212 fs_visitor::CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
, uint32_t condition
)
216 /* Take the instruction:
218 * CMP null<d> src0<f> src1<f>
220 * Original gen4 does type conversion to the destination type before
221 * comparison, producing garbage results for floating point comparisons.
222 * gen5 does the comparison on the execution type (resolved source types),
223 * so dst type doesn't matter. gen6 does comparison and then uses the
224 * result as if it was the dst type with no conversion, which happens to
225 * mostly work out for float-interpreted-as-int since our comparisons are
229 dst
.type
= src0
.type
;
230 if (dst
.file
== HW_REG
)
231 dst
.fixed_hw_reg
.type
= dst
.type
;
234 resolve_ud_negate(&src0
);
235 resolve_ud_negate(&src1
);
237 inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_CMP
, dst
, src0
, src1
);
238 inst
->conditional_mod
= condition
;
244 fs_visitor::VARYING_PULL_CONSTANT_LOAD(fs_reg dst
, fs_reg surf_index
,
245 fs_reg varying_offset
,
246 uint32_t const_offset
)
248 exec_list instructions
;
251 /* We have our constant surface use a pitch of 4 bytes, so our index can
252 * be any component of a vector, and then we load 4 contiguous
253 * components starting from that.
255 * We break down the const_offset to a portion added to the variable
256 * offset and a portion done using reg_offset, which means that if you
257 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
258 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
259 * CSE can later notice that those loads are all the same and eliminate
260 * the redundant ones.
262 fs_reg vec4_offset
= fs_reg(this, glsl_type::int_type
);
263 instructions
.push_tail(ADD(vec4_offset
,
264 varying_offset
, const_offset
& ~3));
267 if (brw
->gen
== 4 && dispatch_width
== 8) {
268 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
269 * u, v, r) as parameters, or we can just use the SIMD16 message
270 * consisting of (header, u). We choose the second, at the cost of a
271 * longer return length.
278 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
280 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
281 fs_reg vec4_result
= fs_reg(GRF
, virtual_grf_alloc(4 * scale
), dst
.type
);
282 inst
= new(mem_ctx
) fs_inst(op
, vec4_result
, surf_index
, vec4_offset
);
283 inst
->regs_written
= 4 * scale
;
284 instructions
.push_tail(inst
);
288 inst
->header_present
= true;
292 inst
->mlen
= 1 + dispatch_width
/ 8;
295 vec4_result
.reg_offset
+= (const_offset
& 3) * scale
;
296 instructions
.push_tail(MOV(dst
, vec4_result
));
302 * A helper for MOV generation for fixing up broken hardware SEND dependency
306 fs_visitor::DEP_RESOLVE_MOV(int grf
)
308 fs_inst
*inst
= MOV(brw_null_reg(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
311 inst
->annotation
= "send dependency resolve";
313 /* The caller always wants uncompressed to emit the minimal extra
314 * dependencies, and to avoid having to deal with aligning its regs to 2.
316 inst
->force_uncompressed
= true;
322 fs_inst::equals(fs_inst
*inst
)
324 return (opcode
== inst
->opcode
&&
325 dst
.equals(inst
->dst
) &&
326 src
[0].equals(inst
->src
[0]) &&
327 src
[1].equals(inst
->src
[1]) &&
328 src
[2].equals(inst
->src
[2]) &&
329 saturate
== inst
->saturate
&&
330 predicate
== inst
->predicate
&&
331 conditional_mod
== inst
->conditional_mod
&&
332 mlen
== inst
->mlen
&&
333 base_mrf
== inst
->base_mrf
&&
334 sampler
== inst
->sampler
&&
335 target
== inst
->target
&&
337 header_present
== inst
->header_present
&&
338 shadow_compare
== inst
->shadow_compare
&&
339 offset
== inst
->offset
);
343 fs_inst::overwrites_reg(const fs_reg
®
)
345 return (reg
.file
== dst
.file
&&
346 reg
.reg
== dst
.reg
&&
347 reg
.reg_offset
>= dst
.reg_offset
&&
348 reg
.reg_offset
< dst
.reg_offset
+ regs_written
);
352 fs_inst::is_send_from_grf()
354 return (opcode
== FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
||
355 opcode
== SHADER_OPCODE_SHADER_TIME_ADD
||
356 (opcode
== FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
&&
357 src
[1].file
== GRF
));
361 fs_visitor::can_do_source_mods(fs_inst
*inst
)
363 if (brw
->gen
== 6 && inst
->is_math())
366 if (inst
->is_send_from_grf())
375 memset(this, 0, sizeof(*this));
379 /** Generic unset register constructor. */
383 this->file
= BAD_FILE
;
386 /** Immediate value constructor. */
387 fs_reg::fs_reg(float f
)
391 this->type
= BRW_REGISTER_TYPE_F
;
395 /** Immediate value constructor. */
396 fs_reg::fs_reg(int32_t i
)
400 this->type
= BRW_REGISTER_TYPE_D
;
404 /** Immediate value constructor. */
405 fs_reg::fs_reg(uint32_t u
)
409 this->type
= BRW_REGISTER_TYPE_UD
;
413 /** Fixed brw_reg Immediate value constructor. */
414 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
418 this->fixed_hw_reg
= fixed_hw_reg
;
419 this->type
= fixed_hw_reg
.type
;
423 fs_reg::equals(const fs_reg
&r
) const
425 return (file
== r
.file
&&
427 reg_offset
== r
.reg_offset
&&
429 negate
== r
.negate
&&
431 !reladdr
&& !r
.reladdr
&&
432 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
433 sizeof(fixed_hw_reg
)) == 0 &&
439 fs_reg::is_zero() const
444 return type
== BRW_REGISTER_TYPE_F
? imm
.f
== 0.0 : imm
.i
== 0;
448 fs_reg::is_one() const
453 return type
== BRW_REGISTER_TYPE_F
? imm
.f
== 1.0 : imm
.i
== 1;
457 fs_reg::is_valid_3src() const
459 return file
== GRF
|| file
== UNIFORM
;
463 fs_visitor::type_size(const struct glsl_type
*type
)
465 unsigned int size
, i
;
467 switch (type
->base_type
) {
470 case GLSL_TYPE_FLOAT
:
472 return type
->components();
473 case GLSL_TYPE_ARRAY
:
474 return type_size(type
->fields
.array
) * type
->length
;
475 case GLSL_TYPE_STRUCT
:
477 for (i
= 0; i
< type
->length
; i
++) {
478 size
+= type_size(type
->fields
.structure
[i
].type
);
481 case GLSL_TYPE_SAMPLER
:
482 /* Samplers take up no register space, since they're baked in at
487 case GLSL_TYPE_ERROR
:
488 case GLSL_TYPE_INTERFACE
:
489 assert(!"not reached");
497 fs_visitor::get_timestamp()
499 assert(brw
->gen
>= 7);
501 fs_reg ts
= fs_reg(retype(brw_vec1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
504 BRW_REGISTER_TYPE_UD
));
506 fs_reg dst
= fs_reg(this, glsl_type::uint_type
);
508 fs_inst
*mov
= emit(MOV(dst
, ts
));
509 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
510 * even if it's not enabled in the dispatch.
512 mov
->force_writemask_all
= true;
513 mov
->force_uncompressed
= true;
515 /* The caller wants the low 32 bits of the timestamp. Since it's running
516 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
517 * which is plenty of time for our purposes. It is identical across the
518 * EUs, but since it's tracking GPU core speed it will increment at a
519 * varying rate as render P-states change.
521 * The caller could also check if render P-states have changed (or anything
522 * else that might disrupt timing) by setting smear to 2 and checking if
523 * that field is != 0.
531 fs_visitor::emit_shader_time_begin()
533 current_annotation
= "shader time start";
534 shader_start_time
= get_timestamp();
538 fs_visitor::emit_shader_time_end()
540 current_annotation
= "shader time end";
542 enum shader_time_shader_type type
, written_type
, reset_type
;
543 if (dispatch_width
== 8) {
545 written_type
= ST_FS8_WRITTEN
;
546 reset_type
= ST_FS8_RESET
;
548 assert(dispatch_width
== 16);
550 written_type
= ST_FS16_WRITTEN
;
551 reset_type
= ST_FS16_RESET
;
554 fs_reg shader_end_time
= get_timestamp();
556 /* Check that there weren't any timestamp reset events (assuming these
557 * were the only two timestamp reads that happened).
559 fs_reg reset
= shader_end_time
;
561 fs_inst
*test
= emit(AND(reg_null_d
, reset
, fs_reg(1u)));
562 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
563 emit(IF(BRW_PREDICATE_NORMAL
));
565 push_force_uncompressed();
566 fs_reg start
= shader_start_time
;
568 fs_reg diff
= fs_reg(this, glsl_type::uint_type
);
569 emit(ADD(diff
, start
, shader_end_time
));
571 /* If there were no instructions between the two timestamp gets, the diff
572 * is 2 cycles. Remove that overhead, so I can forget about that when
573 * trying to determine the time taken for single instructions.
575 emit(ADD(diff
, diff
, fs_reg(-2u)));
577 emit_shader_time_write(type
, diff
);
578 emit_shader_time_write(written_type
, fs_reg(1u));
579 emit(BRW_OPCODE_ELSE
);
580 emit_shader_time_write(reset_type
, fs_reg(1u));
581 emit(BRW_OPCODE_ENDIF
);
583 pop_force_uncompressed();
587 fs_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
590 int shader_time_index
=
591 brw_get_shader_time_index(brw
, shader_prog
, &fp
->Base
, type
);
592 fs_reg offset
= fs_reg(shader_time_index
* SHADER_TIME_STRIDE
);
595 if (dispatch_width
== 8)
596 payload
= fs_reg(this, glsl_type::uvec2_type
);
598 payload
= fs_reg(this, glsl_type::uint_type
);
600 emit(fs_inst(SHADER_OPCODE_SHADER_TIME_ADD
,
601 fs_reg(), payload
, offset
, value
));
605 fs_visitor::fail(const char *format
, ...)
615 va_start(va
, format
);
616 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
618 msg
= ralloc_asprintf(mem_ctx
, "FS compile failed: %s\n", msg
);
620 this->fail_msg
= msg
;
622 if (INTEL_DEBUG
& DEBUG_WM
) {
623 fprintf(stderr
, "%s", msg
);
628 fs_visitor::emit(enum opcode opcode
)
630 return emit(fs_inst(opcode
));
634 fs_visitor::emit(enum opcode opcode
, fs_reg dst
)
636 return emit(fs_inst(opcode
, dst
));
640 fs_visitor::emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
)
642 return emit(fs_inst(opcode
, dst
, src0
));
646 fs_visitor::emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
648 return emit(fs_inst(opcode
, dst
, src0
, src1
));
652 fs_visitor::emit(enum opcode opcode
, fs_reg dst
,
653 fs_reg src0
, fs_reg src1
, fs_reg src2
)
655 return emit(fs_inst(opcode
, dst
, src0
, src1
, src2
));
659 fs_visitor::push_force_uncompressed()
661 force_uncompressed_stack
++;
665 fs_visitor::pop_force_uncompressed()
667 force_uncompressed_stack
--;
668 assert(force_uncompressed_stack
>= 0);
672 fs_visitor::push_force_sechalf()
674 force_sechalf_stack
++;
678 fs_visitor::pop_force_sechalf()
680 force_sechalf_stack
--;
681 assert(force_sechalf_stack
>= 0);
685 * Returns true if the instruction has a flag that means it won't
686 * update an entire destination register.
688 * For example, dead code elimination and live variable analysis want to know
689 * when a write to a variable screens off any preceding values that were in
693 fs_inst::is_partial_write()
695 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
696 this->force_uncompressed
||
697 this->force_sechalf
);
701 * Returns how many MRFs an FS opcode will write over.
703 * Note that this is not the 0 or 1 implied writes in an actual gen
704 * instruction -- the FS opcodes often generate MOVs in addition.
707 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
712 switch (inst
->opcode
) {
713 case SHADER_OPCODE_RCP
:
714 case SHADER_OPCODE_RSQ
:
715 case SHADER_OPCODE_SQRT
:
716 case SHADER_OPCODE_EXP2
:
717 case SHADER_OPCODE_LOG2
:
718 case SHADER_OPCODE_SIN
:
719 case SHADER_OPCODE_COS
:
720 return 1 * dispatch_width
/ 8;
721 case SHADER_OPCODE_POW
:
722 case SHADER_OPCODE_INT_QUOTIENT
:
723 case SHADER_OPCODE_INT_REMAINDER
:
724 return 2 * dispatch_width
/ 8;
725 case SHADER_OPCODE_TEX
:
727 case SHADER_OPCODE_TXD
:
728 case SHADER_OPCODE_TXF
:
729 case SHADER_OPCODE_TXF_MS
:
730 case SHADER_OPCODE_TG4
:
731 case SHADER_OPCODE_TXL
:
732 case SHADER_OPCODE_TXS
:
733 case SHADER_OPCODE_LOD
:
735 case FS_OPCODE_FB_WRITE
:
737 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
738 case FS_OPCODE_UNSPILL
:
740 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
742 case FS_OPCODE_SPILL
:
745 assert(!"not reached");
751 fs_visitor::virtual_grf_alloc(int size
)
753 if (virtual_grf_array_size
<= virtual_grf_count
) {
754 if (virtual_grf_array_size
== 0)
755 virtual_grf_array_size
= 16;
757 virtual_grf_array_size
*= 2;
758 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
759 virtual_grf_array_size
);
761 virtual_grf_sizes
[virtual_grf_count
] = size
;
762 return virtual_grf_count
++;
765 /** Fixed HW reg constructor. */
766 fs_reg::fs_reg(enum register_file file
, int reg
)
771 this->type
= BRW_REGISTER_TYPE_F
;
774 /** Fixed HW reg constructor. */
775 fs_reg::fs_reg(enum register_file file
, int reg
, uint32_t type
)
783 /** Automatic reg constructor. */
784 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
789 this->reg
= v
->virtual_grf_alloc(v
->type_size(type
));
790 this->reg_offset
= 0;
791 this->type
= brw_type_for_base_type(type
);
795 fs_visitor::variable_storage(ir_variable
*var
)
797 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
801 import_uniforms_callback(const void *key
,
805 struct hash_table
*dst_ht
= (struct hash_table
*)closure
;
806 const fs_reg
*reg
= (const fs_reg
*)data
;
808 if (reg
->file
!= UNIFORM
)
811 hash_table_insert(dst_ht
, data
, key
);
814 /* For 16-wide, we need to follow from the uniform setup of 8-wide dispatch.
815 * This brings in those uniform definitions
818 fs_visitor::import_uniforms(fs_visitor
*v
)
820 hash_table_call_foreach(v
->variable_ht
,
821 import_uniforms_callback
,
823 this->params_remap
= v
->params_remap
;
824 this->nr_params_remap
= v
->nr_params_remap
;
827 /* Our support for uniforms is piggy-backed on the struct
828 * gl_fragment_program, because that's where the values actually
829 * get stored, rather than in some global gl_shader_program uniform
833 fs_visitor::setup_uniform_values(ir_variable
*ir
)
835 int namelen
= strlen(ir
->name
);
837 /* The data for our (non-builtin) uniforms is stored in a series of
838 * gl_uniform_driver_storage structs for each subcomponent that
839 * glGetUniformLocation() could name. We know it's been set up in the same
840 * order we'd walk the type, so walk the list of storage and find anything
841 * with our name, or the prefix of a component that starts with our name.
843 unsigned params_before
= c
->prog_data
.nr_params
;
844 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
845 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
847 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
848 (storage
->name
[namelen
] != 0 &&
849 storage
->name
[namelen
] != '.' &&
850 storage
->name
[namelen
] != '[')) {
854 unsigned slots
= storage
->type
->component_slots();
855 if (storage
->array_elements
)
856 slots
*= storage
->array_elements
;
858 for (unsigned i
= 0; i
< slots
; i
++) {
859 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
860 &storage
->storage
[i
].f
;
864 /* Make sure we actually initialized the right amount of stuff here. */
865 assert(params_before
+ ir
->type
->component_slots() ==
866 c
->prog_data
.nr_params
);
871 /* Our support for builtin uniforms is even scarier than non-builtin.
872 * It sits on top of the PROG_STATE_VAR parameters that are
873 * automatically updated from GL context state.
876 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
878 const ir_state_slot
*const slots
= ir
->state_slots
;
879 assert(ir
->state_slots
!= NULL
);
881 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
882 /* This state reference has already been setup by ir_to_mesa, but we'll
883 * get the same index back here.
885 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
886 (gl_state_index
*)slots
[i
].tokens
);
888 /* Add each of the unique swizzles of the element as a parameter.
889 * This'll end up matching the expected layout of the
890 * array/matrix/structure we're trying to fill in.
893 for (unsigned int j
= 0; j
< 4; j
++) {
894 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
895 if (swiz
== last_swiz
)
899 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
900 &fp
->Base
.Parameters
->ParameterValues
[index
][swiz
].f
;
906 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
908 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
910 bool flip
= !ir
->origin_upper_left
^ c
->key
.render_to_fbo
;
913 if (ir
->pixel_center_integer
) {
914 emit(MOV(wpos
, this->pixel_x
));
916 emit(ADD(wpos
, this->pixel_x
, fs_reg(0.5f
)));
921 if (!flip
&& ir
->pixel_center_integer
) {
922 emit(MOV(wpos
, this->pixel_y
));
924 fs_reg pixel_y
= this->pixel_y
;
925 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
928 pixel_y
.negate
= true;
929 offset
+= c
->key
.drawable_height
- 1.0;
932 emit(ADD(wpos
, pixel_y
, fs_reg(offset
)));
938 emit(MOV(wpos
, fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
940 emit(FS_OPCODE_LINTERP
, wpos
,
941 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
942 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
943 interp_reg(VARYING_SLOT_POS
, 2));
947 /* gl_FragCoord.w: Already set up in emit_interpolation */
948 emit(BRW_OPCODE_MOV
, wpos
, this->wpos_w
);
954 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
955 glsl_interp_qualifier interpolation_mode
,
958 brw_wm_barycentric_interp_mode barycoord_mode
;
961 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
962 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
964 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
966 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
967 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
969 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
972 /* On Ironlake and below, there is only one interpolation mode.
973 * Centroid interpolation doesn't mean anything on this hardware --
974 * there is no multisampling.
976 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
978 return emit(FS_OPCODE_LINTERP
, attr
,
979 this->delta_x
[barycoord_mode
],
980 this->delta_y
[barycoord_mode
], interp
);
984 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
986 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
987 reg
->type
= brw_type_for_base_type(ir
->type
->get_scalar_type());
990 unsigned int array_elements
;
991 const glsl_type
*type
;
993 if (ir
->type
->is_array()) {
994 array_elements
= ir
->type
->length
;
995 if (array_elements
== 0) {
996 fail("dereferenced array '%s' has length 0\n", ir
->name
);
998 type
= ir
->type
->fields
.array
;
1004 glsl_interp_qualifier interpolation_mode
=
1005 ir
->determine_interpolation_mode(c
->key
.flat_shade
);
1007 int location
= ir
->location
;
1008 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1009 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1010 if (c
->prog_data
.urb_setup
[location
] == -1) {
1011 /* If there's no incoming setup data for this slot, don't
1012 * emit interpolation for it.
1014 attr
.reg_offset
+= type
->vector_elements
;
1019 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1020 /* Constant interpolation (flat shading) case. The SF has
1021 * handed us defined values in only the constant offset
1022 * field of the setup reg.
1024 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1025 struct brw_reg interp
= interp_reg(location
, k
);
1026 interp
= suboffset(interp
, 3);
1027 interp
.type
= reg
->type
;
1028 emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1032 /* Smooth/noperspective interpolation case. */
1033 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1034 /* FINISHME: At some point we probably want to push
1035 * this farther by giving similar treatment to the
1036 * other potentially constant components of the
1037 * attribute, as well as making brw_vs_constval.c
1038 * handle varyings other than gl_TexCoord.
1040 struct brw_reg interp
= interp_reg(location
, k
);
1041 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1043 if (brw
->needs_unlit_centroid_workaround
&& ir
->centroid
) {
1044 /* Get the pixel/sample mask into f0 so that we know
1045 * which pixels are lit. Then, for each channel that is
1046 * unlit, replace the centroid data with non-centroid
1049 emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1050 fs_inst
*inst
= emit_linterp(attr
, fs_reg(interp
),
1051 interpolation_mode
, false);
1052 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1053 inst
->predicate_inverse
= true;
1055 if (brw
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1056 emit(BRW_OPCODE_MUL
, attr
, attr
, this->pixel_w
);
1070 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
1072 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1074 /* The frontfacing comes in as a bit in the thread payload. */
1075 if (brw
->gen
>= 6) {
1076 emit(BRW_OPCODE_ASR
, *reg
,
1077 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1079 emit(BRW_OPCODE_NOT
, *reg
, *reg
);
1080 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1));
1082 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
1083 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
1086 emit(CMP(*reg
, fs_reg(r1_6ud
), fs_reg(1u << 31), BRW_CONDITIONAL_L
));
1087 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u));
1094 fs_visitor::fix_math_operand(fs_reg src
)
1096 /* Can't do hstride == 0 args on gen6 math, so expand it out. We
1097 * might be able to do better by doing execsize = 1 math and then
1098 * expanding that result out, but we would need to be careful with
1101 * The hardware ignores source modifiers (negate and abs) on math
1102 * instructions, so we also move to a temp to set those up.
1104 if (brw
->gen
== 6 && src
.file
!= UNIFORM
&& src
.file
!= IMM
&&
1105 !src
.abs
&& !src
.negate
)
1108 /* Gen7 relaxes most of the above restrictions, but still can't use IMM
1111 if (brw
->gen
>= 7 && src
.file
!= IMM
)
1114 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
1115 expanded
.type
= src
.type
;
1116 emit(BRW_OPCODE_MOV
, expanded
, src
);
1121 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src
)
1124 case SHADER_OPCODE_RCP
:
1125 case SHADER_OPCODE_RSQ
:
1126 case SHADER_OPCODE_SQRT
:
1127 case SHADER_OPCODE_EXP2
:
1128 case SHADER_OPCODE_LOG2
:
1129 case SHADER_OPCODE_SIN
:
1130 case SHADER_OPCODE_COS
:
1133 assert(!"not reached: bad math opcode");
1137 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
1138 * might be able to do better by doing execsize = 1 math and then
1139 * expanding that result out, but we would need to be careful with
1142 * Gen 6 hardware ignores source modifiers (negate and abs) on math
1143 * instructions, so we also move to a temp to set those up.
1146 src
= fix_math_operand(src
);
1148 fs_inst
*inst
= emit(opcode
, dst
, src
);
1152 inst
->mlen
= dispatch_width
/ 8;
1159 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
1165 case SHADER_OPCODE_INT_QUOTIENT
:
1166 case SHADER_OPCODE_INT_REMAINDER
:
1167 if (brw
->gen
>= 7 && dispatch_width
== 16)
1168 fail("16-wide INTDIV unsupported\n");
1170 case SHADER_OPCODE_POW
:
1173 assert(!"not reached: unsupported binary math opcode.");
1177 if (brw
->gen
>= 6) {
1178 src0
= fix_math_operand(src0
);
1179 src1
= fix_math_operand(src1
);
1181 inst
= emit(opcode
, dst
, src0
, src1
);
1183 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
1184 * "Message Payload":
1186 * "Operand0[7]. For the INT DIV functions, this operand is the
1189 * "Operand1[7]. For the INT DIV functions, this operand is the
1192 bool is_int_div
= opcode
!= SHADER_OPCODE_POW
;
1193 fs_reg
&op0
= is_int_div
? src1
: src0
;
1194 fs_reg
&op1
= is_int_div
? src0
: src1
;
1196 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1, op1
.type
), op1
);
1197 inst
= emit(opcode
, dst
, op0
, reg_null_f
);
1199 inst
->base_mrf
= base_mrf
;
1200 inst
->mlen
= 2 * dispatch_width
/ 8;
1206 fs_visitor::assign_curb_setup()
1208 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
1209 if (dispatch_width
== 8) {
1210 c
->prog_data
.first_curbe_grf
= c
->nr_payload_regs
;
1212 c
->prog_data
.first_curbe_grf_16
= c
->nr_payload_regs
;
1215 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1216 foreach_list(node
, &this->instructions
) {
1217 fs_inst
*inst
= (fs_inst
*)node
;
1219 for (unsigned int i
= 0; i
< 3; i
++) {
1220 if (inst
->src
[i
].file
== UNIFORM
) {
1221 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1222 struct brw_reg brw_reg
= brw_vec1_grf(c
->nr_payload_regs
+
1226 inst
->src
[i
].file
= HW_REG
;
1227 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
1234 fs_visitor::calculate_urb_setup()
1236 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1237 c
->prog_data
.urb_setup
[i
] = -1;
1241 /* Figure out where each of the incoming setup attributes lands. */
1242 if (brw
->gen
>= 6) {
1243 if (_mesa_bitcount_64(fp
->Base
.InputsRead
&
1244 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1245 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1246 * first 16 varying inputs, so we can put them wherever we want.
1247 * Just put them in order.
1249 * This is useful because it means that (a) inputs not used by the
1250 * fragment shader won't take up valuable register space, and (b) we
1251 * won't have to recompile the fragment shader if it gets paired with
1252 * a different vertex (or geometry) shader.
1254 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1255 if (fp
->Base
.InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1256 BITFIELD64_BIT(i
)) {
1257 c
->prog_data
.urb_setup
[i
] = urb_next
++;
1261 /* We have enough input varyings that the SF/SBE pipeline stage can't
1262 * arbitrarily rearrange them to suit our whim; we have to put them
1263 * in an order that matches the output of the previous pipeline stage
1264 * (geometry or vertex shader).
1266 struct brw_vue_map prev_stage_vue_map
;
1267 brw_compute_vue_map(brw
, &prev_stage_vue_map
,
1268 c
->key
.input_slots_valid
);
1269 int first_slot
= 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1270 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1271 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1273 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1274 /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
1277 if (varying
!= BRW_VARYING_SLOT_COUNT
&&
1278 (fp
->Base
.InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1279 BITFIELD64_BIT(varying
))) {
1280 c
->prog_data
.urb_setup
[varying
] = slot
- first_slot
;
1283 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1286 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1287 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1288 /* Point size is packed into the header, not as a general attribute */
1289 if (i
== VARYING_SLOT_PSIZ
)
1292 if (c
->key
.input_slots_valid
& BITFIELD64_BIT(i
)) {
1293 /* The back color slot is skipped when the front color is
1294 * also written to. In addition, some slots can be
1295 * written in the vertex shader and not read in the
1296 * fragment shader. So the register number must always be
1297 * incremented, mapped or not.
1299 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1300 c
->prog_data
.urb_setup
[i
] = urb_next
;
1306 * It's a FS only attribute, and we did interpolation for this attribute
1307 * in SF thread. So, count it here, too.
1309 * See compile_sf_prog() for more info.
1311 if (fp
->Base
.InputsRead
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1312 c
->prog_data
.urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1315 c
->prog_data
.num_varying_inputs
= urb_next
;
1319 fs_visitor::assign_urb_setup()
1321 int urb_start
= c
->nr_payload_regs
+ c
->prog_data
.curb_read_length
;
1323 /* Offset all the urb_setup[] index by the actual position of the
1324 * setup regs, now that the location of the constants has been chosen.
1326 foreach_list(node
, &this->instructions
) {
1327 fs_inst
*inst
= (fs_inst
*)node
;
1329 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1330 assert(inst
->src
[2].file
== HW_REG
);
1331 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
1334 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1335 assert(inst
->src
[0].file
== HW_REG
);
1336 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1340 /* Each attribute is 4 setup channels, each of which is half a reg. */
1341 this->first_non_payload_grf
=
1342 urb_start
+ c
->prog_data
.num_varying_inputs
* 2;
1346 * Split large virtual GRFs into separate components if we can.
1348 * This is mostly duplicated with what brw_fs_vector_splitting does,
1349 * but that's really conservative because it's afraid of doing
1350 * splitting that doesn't result in real progress after the rest of
1351 * the optimization phases, which would cause infinite looping in
1352 * optimization. We can do it once here, safely. This also has the
1353 * opportunity to split interpolated values, or maybe even uniforms,
1354 * which we don't have at the IR level.
1356 * We want to split, because virtual GRFs are what we register
1357 * allocate and spill (due to contiguousness requirements for some
1358 * instructions), and they're what we naturally generate in the
1359 * codegen process, but most virtual GRFs don't actually need to be
1360 * contiguous sets of GRFs. If we split, we'll end up with reduced
1361 * live intervals and better dead code elimination and coalescing.
1364 fs_visitor::split_virtual_grfs()
1366 int num_vars
= this->virtual_grf_count
;
1367 bool split_grf
[num_vars
];
1368 int new_virtual_grf
[num_vars
];
1370 /* Try to split anything > 0 sized. */
1371 for (int i
= 0; i
< num_vars
; i
++) {
1372 if (this->virtual_grf_sizes
[i
] != 1)
1373 split_grf
[i
] = true;
1375 split_grf
[i
] = false;
1379 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].file
== GRF
) {
1380 /* PLN opcodes rely on the delta_xy being contiguous. We only have to
1381 * check this for BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because prior to
1382 * Gen6, that was the only supported interpolation mode, and since Gen6,
1383 * delta_x and delta_y are in fixed hardware registers.
1385 split_grf
[this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
] =
1389 foreach_list(node
, &this->instructions
) {
1390 fs_inst
*inst
= (fs_inst
*)node
;
1392 /* If there's a SEND message that requires contiguous destination
1393 * registers, no splitting is allowed.
1395 if (inst
->regs_written
> 1) {
1396 split_grf
[inst
->dst
.reg
] = false;
1399 /* If we're sending from a GRF, don't split it, on the assumption that
1400 * the send is reading the whole thing.
1402 if (inst
->is_send_from_grf()) {
1403 for (int i
= 0; i
< 3; i
++) {
1404 if (inst
->src
[i
].file
== GRF
) {
1405 split_grf
[inst
->src
[i
].reg
] = false;
1411 /* Allocate new space for split regs. Note that the virtual
1412 * numbers will be contiguous.
1414 for (int i
= 0; i
< num_vars
; i
++) {
1416 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1417 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1418 int reg
= virtual_grf_alloc(1);
1419 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1422 this->virtual_grf_sizes
[i
] = 1;
1426 foreach_list(node
, &this->instructions
) {
1427 fs_inst
*inst
= (fs_inst
*)node
;
1429 if (inst
->dst
.file
== GRF
&&
1430 split_grf
[inst
->dst
.reg
] &&
1431 inst
->dst
.reg_offset
!= 0) {
1432 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1433 inst
->dst
.reg_offset
- 1);
1434 inst
->dst
.reg_offset
= 0;
1436 for (int i
= 0; i
< 3; i
++) {
1437 if (inst
->src
[i
].file
== GRF
&&
1438 split_grf
[inst
->src
[i
].reg
] &&
1439 inst
->src
[i
].reg_offset
!= 0) {
1440 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1441 inst
->src
[i
].reg_offset
- 1);
1442 inst
->src
[i
].reg_offset
= 0;
1446 this->live_intervals_valid
= false;
1450 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1452 * During code generation, we create tons of temporary variables, many of
1453 * which get immediately killed and are never used again. Yet, in later
1454 * optimization and analysis passes, such as compute_live_intervals, we need
1455 * to loop over all the virtual GRFs. Compacting them can save a lot of
1459 fs_visitor::compact_virtual_grfs()
1461 /* Mark which virtual GRFs are used, and count how many. */
1462 int remap_table
[this->virtual_grf_count
];
1463 memset(remap_table
, -1, sizeof(remap_table
));
1465 foreach_list(node
, &this->instructions
) {
1466 const fs_inst
*inst
= (const fs_inst
*) node
;
1468 if (inst
->dst
.file
== GRF
)
1469 remap_table
[inst
->dst
.reg
] = 0;
1471 for (int i
= 0; i
< 3; i
++) {
1472 if (inst
->src
[i
].file
== GRF
)
1473 remap_table
[inst
->src
[i
].reg
] = 0;
1477 /* In addition to registers used in instructions, fs_visitor keeps
1478 * direct references to certain special values which must be patched:
1480 fs_reg
*special
[] = {
1481 &frag_depth
, &pixel_x
, &pixel_y
, &pixel_w
, &wpos_w
, &dual_src_output
,
1482 &outputs
[0], &outputs
[1], &outputs
[2], &outputs
[3],
1483 &outputs
[4], &outputs
[5], &outputs
[6], &outputs
[7],
1484 &delta_x
[0], &delta_x
[1], &delta_x
[2],
1485 &delta_x
[3], &delta_x
[4], &delta_x
[5],
1486 &delta_y
[0], &delta_y
[1], &delta_y
[2],
1487 &delta_y
[3], &delta_y
[4], &delta_y
[5],
1489 STATIC_ASSERT(BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
== 6);
1490 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
== 8);
1492 /* Treat all special values as used, to be conservative */
1493 for (unsigned i
= 0; i
< ARRAY_SIZE(special
); i
++) {
1494 if (special
[i
]->file
== GRF
)
1495 remap_table
[special
[i
]->reg
] = 0;
1498 /* Compact the GRF arrays. */
1500 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
1501 if (remap_table
[i
] != -1) {
1502 remap_table
[i
] = new_index
;
1503 virtual_grf_sizes
[new_index
] = virtual_grf_sizes
[i
];
1504 if (live_intervals_valid
) {
1505 virtual_grf_start
[new_index
] = virtual_grf_start
[i
];
1506 virtual_grf_end
[new_index
] = virtual_grf_end
[i
];
1512 this->virtual_grf_count
= new_index
;
1514 /* Patch all the instructions to use the newly renumbered registers */
1515 foreach_list(node
, &this->instructions
) {
1516 fs_inst
*inst
= (fs_inst
*) node
;
1518 if (inst
->dst
.file
== GRF
)
1519 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
1521 for (int i
= 0; i
< 3; i
++) {
1522 if (inst
->src
[i
].file
== GRF
)
1523 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
1527 /* Patch all the references to special values */
1528 for (unsigned i
= 0; i
< ARRAY_SIZE(special
); i
++) {
1529 if (special
[i
]->file
== GRF
&& remap_table
[special
[i
]->reg
] != -1)
1530 special
[i
]->reg
= remap_table
[special
[i
]->reg
];
1535 fs_visitor::remove_dead_constants()
1537 if (dispatch_width
== 8) {
1538 this->params_remap
= ralloc_array(mem_ctx
, int, c
->prog_data
.nr_params
);
1539 this->nr_params_remap
= c
->prog_data
.nr_params
;
1541 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++)
1542 this->params_remap
[i
] = -1;
1544 /* Find which params are still in use. */
1545 foreach_list(node
, &this->instructions
) {
1546 fs_inst
*inst
= (fs_inst
*)node
;
1548 for (int i
= 0; i
< 3; i
++) {
1549 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1551 if (inst
->src
[i
].file
!= UNIFORM
)
1554 /* Section 5.11 of the OpenGL 4.3 spec says:
1556 * "Out-of-bounds reads return undefined values, which include
1557 * values from other variables of the active program or zero."
1559 if (constant_nr
< 0 || constant_nr
>= (int)c
->prog_data
.nr_params
) {
1563 /* For now, set this to non-negative. We'll give it the
1564 * actual new number in a moment, in order to keep the
1565 * register numbers nicely ordered.
1567 this->params_remap
[constant_nr
] = 0;
1571 /* Figure out what the new numbers for the params will be. At some
1572 * point when we're doing uniform array access, we're going to want
1573 * to keep the distinction between .reg and .reg_offset, but for
1574 * now we don't care.
1576 unsigned int new_nr_params
= 0;
1577 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1578 if (this->params_remap
[i
] != -1) {
1579 this->params_remap
[i
] = new_nr_params
++;
1583 /* Update the list of params to be uploaded to match our new numbering. */
1584 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1585 int remapped
= this->params_remap
[i
];
1590 c
->prog_data
.param
[remapped
] = c
->prog_data
.param
[i
];
1593 c
->prog_data
.nr_params
= new_nr_params
;
1595 /* This should have been generated in the 8-wide pass already. */
1596 assert(this->params_remap
);
1599 /* Now do the renumbering of the shader to remove unused params. */
1600 foreach_list(node
, &this->instructions
) {
1601 fs_inst
*inst
= (fs_inst
*)node
;
1603 for (int i
= 0; i
< 3; i
++) {
1604 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1606 if (inst
->src
[i
].file
!= UNIFORM
)
1609 /* as above alias to 0 */
1610 if (constant_nr
< 0 || constant_nr
>= (int)this->nr_params_remap
) {
1613 assert(this->params_remap
[constant_nr
] != -1);
1614 inst
->src
[i
].reg
= this->params_remap
[constant_nr
];
1615 inst
->src
[i
].reg_offset
= 0;
1623 * Implements array access of uniforms by inserting a
1624 * PULL_CONSTANT_LOAD instruction.
1626 * Unlike temporary GRF array access (where we don't support it due to
1627 * the difficulty of doing relative addressing on instruction
1628 * destinations), we could potentially do array access of uniforms
1629 * that were loaded in GRF space as push constants. In real-world
1630 * usage we've seen, though, the arrays being used are always larger
1631 * than we could load as push constants, so just always move all
1632 * uniform array access out to a pull constant buffer.
1635 fs_visitor::move_uniform_array_access_to_pull_constants()
1637 int pull_constant_loc
[c
->prog_data
.nr_params
];
1639 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1640 pull_constant_loc
[i
] = -1;
1643 /* Walk through and find array access of uniforms. Put a copy of that
1644 * uniform in the pull constant buffer.
1646 * Note that we don't move constant-indexed accesses to arrays. No
1647 * testing has been done of the performance impact of this choice.
1649 foreach_list_safe(node
, &this->instructions
) {
1650 fs_inst
*inst
= (fs_inst
*)node
;
1652 for (int i
= 0 ; i
< 3; i
++) {
1653 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
1656 int uniform
= inst
->src
[i
].reg
;
1658 /* If this array isn't already present in the pull constant buffer,
1661 if (pull_constant_loc
[uniform
] == -1) {
1662 const float **values
= &c
->prog_data
.param
[uniform
];
1664 pull_constant_loc
[uniform
] = c
->prog_data
.nr_pull_params
;
1666 assert(param_size
[uniform
]);
1668 for (int j
= 0; j
< param_size
[uniform
]; j
++) {
1669 c
->prog_data
.pull_param
[c
->prog_data
.nr_pull_params
++] =
1674 /* Set up the annotation tracking for new generated instructions. */
1676 current_annotation
= inst
->annotation
;
1678 fs_reg surf_index
= fs_reg((unsigned)SURF_INDEX_FRAG_CONST_BUFFER
);
1679 fs_reg temp
= fs_reg(this, glsl_type::float_type
);
1680 exec_list list
= VARYING_PULL_CONSTANT_LOAD(temp
,
1682 *inst
->src
[i
].reladdr
,
1683 pull_constant_loc
[uniform
] +
1684 inst
->src
[i
].reg_offset
);
1685 inst
->insert_before(&list
);
1687 inst
->src
[i
].file
= temp
.file
;
1688 inst
->src
[i
].reg
= temp
.reg
;
1689 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
1690 inst
->src
[i
].reladdr
= NULL
;
1696 * Choose accesses from the UNIFORM file to demote to using the pull
1699 * We allow a fragment shader to have more than the specified minimum
1700 * maximum number of fragment shader uniform components (64). If
1701 * there are too many of these, they'd fill up all of register space.
1702 * So, this will push some of them out to the pull constant buffer and
1703 * update the program to load them.
1706 fs_visitor::setup_pull_constants()
1708 /* Only allow 16 registers (128 uniform components) as push constants. */
1709 unsigned int max_uniform_components
= 16 * 8;
1710 if (c
->prog_data
.nr_params
<= max_uniform_components
)
1713 if (dispatch_width
== 16) {
1714 fail("Pull constants not supported in 16-wide\n");
1718 /* Just demote the end of the list. We could probably do better
1719 * here, demoting things that are rarely used in the program first.
1721 unsigned int pull_uniform_base
= max_uniform_components
;
1723 int pull_constant_loc
[c
->prog_data
.nr_params
];
1724 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1725 if (i
< pull_uniform_base
) {
1726 pull_constant_loc
[i
] = -1;
1728 pull_constant_loc
[i
] = -1;
1729 /* If our constant is already being uploaded for reladdr purposes,
1732 for (unsigned int j
= 0; j
< c
->prog_data
.nr_pull_params
; j
++) {
1733 if (c
->prog_data
.pull_param
[j
] == c
->prog_data
.param
[i
]) {
1734 pull_constant_loc
[i
] = j
;
1738 if (pull_constant_loc
[i
] == -1) {
1739 int pull_index
= c
->prog_data
.nr_pull_params
++;
1740 c
->prog_data
.pull_param
[pull_index
] = c
->prog_data
.param
[i
];
1741 pull_constant_loc
[i
] = pull_index
;;
1745 c
->prog_data
.nr_params
= pull_uniform_base
;
1747 foreach_list(node
, &this->instructions
) {
1748 fs_inst
*inst
= (fs_inst
*)node
;
1750 for (int i
= 0; i
< 3; i
++) {
1751 if (inst
->src
[i
].file
!= UNIFORM
)
1754 int pull_index
= pull_constant_loc
[inst
->src
[i
].reg
+
1755 inst
->src
[i
].reg_offset
];
1756 if (pull_index
== -1)
1759 assert(!inst
->src
[i
].reladdr
);
1761 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
1762 fs_reg index
= fs_reg((unsigned)SURF_INDEX_FRAG_CONST_BUFFER
);
1763 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
1765 new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
1766 dst
, index
, offset
);
1767 pull
->ir
= inst
->ir
;
1768 pull
->annotation
= inst
->annotation
;
1770 inst
->insert_before(pull
);
1772 inst
->src
[i
].file
= GRF
;
1773 inst
->src
[i
].reg
= dst
.reg
;
1774 inst
->src
[i
].reg_offset
= 0;
1775 inst
->src
[i
].smear
= pull_index
& 3;
1781 fs_visitor::opt_algebraic()
1783 bool progress
= false;
1785 foreach_list(node
, &this->instructions
) {
1786 fs_inst
*inst
= (fs_inst
*)node
;
1788 switch (inst
->opcode
) {
1789 case BRW_OPCODE_MUL
:
1790 if (inst
->src
[1].file
!= IMM
)
1794 if (inst
->src
[1].is_one()) {
1795 inst
->opcode
= BRW_OPCODE_MOV
;
1796 inst
->src
[1] = reg_undef
;
1802 if (inst
->src
[1].is_zero()) {
1803 inst
->opcode
= BRW_OPCODE_MOV
;
1804 inst
->src
[0] = inst
->src
[1];
1805 inst
->src
[1] = reg_undef
;
1811 case BRW_OPCODE_ADD
:
1812 if (inst
->src
[1].file
!= IMM
)
1816 if (inst
->src
[1].is_zero()) {
1817 inst
->opcode
= BRW_OPCODE_MOV
;
1818 inst
->src
[1] = reg_undef
;
1832 * Removes any instructions writing a VGRF where that VGRF is not used by any
1833 * later instruction.
1836 fs_visitor::dead_code_eliminate()
1838 bool progress
= false;
1841 calculate_live_intervals();
1843 foreach_list_safe(node
, &this->instructions
) {
1844 fs_inst
*inst
= (fs_inst
*)node
;
1846 if (inst
->dst
.file
== GRF
) {
1847 assert(this->virtual_grf_end
[inst
->dst
.reg
] >= pc
);
1848 if (this->virtual_grf_end
[inst
->dst
.reg
] == pc
) {
1849 /* Don't dead code eliminate instructions that write to the
1850 * accumulator as a side-effect. Instead just set the destination
1851 * to the null register to free it.
1853 switch (inst
->opcode
) {
1854 case BRW_OPCODE_ADDC
:
1855 case BRW_OPCODE_SUBB
:
1856 case BRW_OPCODE_MACH
:
1857 inst
->dst
= fs_reg(retype(brw_null_reg(), inst
->dst
.type
));
1871 live_intervals_valid
= false;
1876 struct dead_code_hash_key
1883 dead_code_hash_compare(const void *a
, const void *b
)
1885 return memcmp(a
, b
, sizeof(struct dead_code_hash_key
)) == 0;
1889 clear_dead_code_hash(struct hash_table
*ht
)
1891 struct hash_entry
*entry
;
1893 hash_table_foreach(ht
, entry
) {
1894 _mesa_hash_table_remove(ht
, entry
);
1899 insert_dead_code_hash(struct hash_table
*ht
,
1900 int vgrf
, int reg_offset
, fs_inst
*inst
)
1902 /* We don't bother freeing keys, because they'll be GCed with the ht. */
1903 struct dead_code_hash_key
*key
= ralloc(ht
, struct dead_code_hash_key
);
1906 key
->reg_offset
= reg_offset
;
1908 _mesa_hash_table_insert(ht
, _mesa_hash_data(key
, sizeof(*key
)), key
, inst
);
1911 static struct hash_entry
*
1912 get_dead_code_hash_entry(struct hash_table
*ht
, int vgrf
, int reg_offset
)
1914 struct dead_code_hash_key key
;
1917 key
.reg_offset
= reg_offset
;
1919 return _mesa_hash_table_search(ht
, _mesa_hash_data(&key
, sizeof(key
)), &key
);
1923 remove_dead_code_hash(struct hash_table
*ht
,
1924 int vgrf
, int reg_offset
)
1926 struct hash_entry
*entry
= get_dead_code_hash_entry(ht
, vgrf
, reg_offset
);
1930 _mesa_hash_table_remove(ht
, entry
);
1934 * Walks basic blocks, removing any regs that are written but not read before
1937 * The dead_code_eliminate() function implements a global dead code
1938 * elimination, but it only handles the removing the last write to a register
1939 * if it's never read. This one can handle intermediate writes, but only
1940 * within a basic block.
1943 fs_visitor::dead_code_eliminate_local()
1945 struct hash_table
*ht
;
1946 bool progress
= false;
1948 ht
= _mesa_hash_table_create(mem_ctx
, dead_code_hash_compare
);
1950 foreach_list_safe(node
, &this->instructions
) {
1951 fs_inst
*inst
= (fs_inst
*)node
;
1953 /* At a basic block, empty the HT since we don't understand dataflow
1956 if (inst
->is_control_flow()) {
1957 clear_dead_code_hash(ht
);
1961 /* Clear the HT of any instructions that got read. */
1962 for (int i
= 0; i
< 3; i
++) {
1963 fs_reg src
= inst
->src
[i
];
1964 if (src
.file
!= GRF
)
1968 if (inst
->is_send_from_grf())
1969 read
= virtual_grf_sizes
[src
.reg
] - src
.reg_offset
;
1971 for (int reg_offset
= src
.reg_offset
;
1972 reg_offset
< src
.reg_offset
+ read
;
1974 remove_dead_code_hash(ht
, src
.reg
, reg_offset
);
1978 /* Add any update of a GRF to the HT, removing a previous write if it
1981 if (inst
->dst
.file
== GRF
) {
1982 if (inst
->regs_written
> 1) {
1983 /* We don't know how to trim channels from an instruction's
1984 * writes, so we can't incrementally remove unread channels from
1985 * it. Just remove whatever it overwrites from the table
1987 for (int i
= 0; i
< inst
->regs_written
; i
++) {
1988 remove_dead_code_hash(ht
,
1990 inst
->dst
.reg_offset
+ i
);
1993 struct hash_entry
*entry
=
1994 get_dead_code_hash_entry(ht
, inst
->dst
.reg
,
1995 inst
->dst
.reg_offset
);
1997 if (inst
->is_partial_write()) {
1998 /* For a partial write, we can't remove any previous dead code
1999 * candidate, since we're just modifying their result, but we can
2000 * be dead code eliminiated ourselves.
2005 insert_dead_code_hash(ht
, inst
->dst
.reg
, inst
->dst
.reg_offset
,
2010 /* We're completely updating a channel, and there was a
2011 * previous write to the channel that wasn't read. Kill it!
2013 fs_inst
*inst
= (fs_inst
*)entry
->data
;
2016 _mesa_hash_table_remove(ht
, entry
);
2019 insert_dead_code_hash(ht
, inst
->dst
.reg
, inst
->dst
.reg_offset
,
2026 _mesa_hash_table_destroy(ht
, NULL
);
2029 live_intervals_valid
= false;
2035 * Implements a second type of register coalescing: This one checks if
2036 * the two regs involved in a raw move don't interfere, in which case
2037 * they can both by stored in the same place and the MOV removed.
2040 fs_visitor::register_coalesce_2()
2042 bool progress
= false;
2044 calculate_live_intervals();
2046 foreach_list_safe(node
, &this->instructions
) {
2047 fs_inst
*inst
= (fs_inst
*)node
;
2049 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2050 inst
->is_partial_write() ||
2052 inst
->src
[0].file
!= GRF
||
2053 inst
->src
[0].negate
||
2055 inst
->src
[0].smear
!= -1 ||
2056 inst
->dst
.file
!= GRF
||
2057 inst
->dst
.type
!= inst
->src
[0].type
||
2058 virtual_grf_sizes
[inst
->src
[0].reg
] != 1 ||
2059 virtual_grf_interferes(inst
->dst
.reg
, inst
->src
[0].reg
)) {
2063 int reg_from
= inst
->src
[0].reg
;
2064 assert(inst
->src
[0].reg_offset
== 0);
2065 int reg_to
= inst
->dst
.reg
;
2066 int reg_to_offset
= inst
->dst
.reg_offset
;
2068 foreach_list(node
, &this->instructions
) {
2069 fs_inst
*scan_inst
= (fs_inst
*)node
;
2071 if (scan_inst
->dst
.file
== GRF
&&
2072 scan_inst
->dst
.reg
== reg_from
) {
2073 scan_inst
->dst
.reg
= reg_to
;
2074 scan_inst
->dst
.reg_offset
= reg_to_offset
;
2076 for (int i
= 0; i
< 3; i
++) {
2077 if (scan_inst
->src
[i
].file
== GRF
&&
2078 scan_inst
->src
[i
].reg
== reg_from
) {
2079 scan_inst
->src
[i
].reg
= reg_to
;
2080 scan_inst
->src
[i
].reg_offset
= reg_to_offset
;
2087 /* We don't need to recalculate live intervals inside the loop despite
2088 * flagging live_intervals_valid because we only use live intervals for
2089 * the interferes test, and we must have had a situation where the
2100 * Some register R that might get coalesced with one of these two could
2101 * only be referencing "to", otherwise "from"'s range would have been
2102 * longer. R's range could also only start at the end of "to" or later,
2103 * otherwise it will conflict with "to" when we try to coalesce "to"
2106 live_intervals_valid
= false;
2116 fs_visitor::register_coalesce()
2118 bool progress
= false;
2122 foreach_list_safe(node
, &this->instructions
) {
2123 fs_inst
*inst
= (fs_inst
*)node
;
2125 /* Make sure that we dominate the instructions we're going to
2126 * scan for interfering with our coalescing, or we won't have
2127 * scanned enough to see if anything interferes with our
2128 * coalescing. We don't dominate the following instructions if
2129 * we're in a loop or an if block.
2131 switch (inst
->opcode
) {
2135 case BRW_OPCODE_WHILE
:
2141 case BRW_OPCODE_ENDIF
:
2147 if (loop_depth
|| if_depth
)
2150 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2151 inst
->is_partial_write() ||
2153 inst
->dst
.file
!= GRF
|| (inst
->src
[0].file
!= GRF
&&
2154 inst
->src
[0].file
!= UNIFORM
)||
2155 inst
->dst
.type
!= inst
->src
[0].type
)
2158 bool has_source_modifiers
= (inst
->src
[0].abs
||
2159 inst
->src
[0].negate
||
2160 inst
->src
[0].smear
!= -1 ||
2161 inst
->src
[0].file
== UNIFORM
);
2163 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
2164 * them: check for no writes to either one until the exit of the
2167 bool interfered
= false;
2169 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->next
;
2170 !scan_inst
->is_tail_sentinel();
2171 scan_inst
= (fs_inst
*)scan_inst
->next
) {
2172 if (scan_inst
->dst
.file
== GRF
) {
2173 if (scan_inst
->overwrites_reg(inst
->dst
) ||
2174 scan_inst
->overwrites_reg(inst
->src
[0])) {
2180 if (has_source_modifiers
) {
2181 for (int i
= 0; i
< 3; i
++) {
2182 if (scan_inst
->src
[i
].file
== GRF
&&
2183 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
2184 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
&&
2185 inst
->dst
.type
!= scan_inst
->src
[i
].type
)
2194 /* The gen6 MATH instruction can't handle source modifiers or
2195 * unusual register regions, so avoid coalescing those for
2196 * now. We should do something more specific.
2198 if (has_source_modifiers
&& !can_do_source_mods(scan_inst
)) {
2203 /* The accumulator result appears to get used for the
2204 * conditional modifier generation. When negating a UD
2205 * value, there is a 33rd bit generated for the sign in the
2206 * accumulator value, so now you can't check, for example,
2207 * equality with a 32-bit value. See piglit fs-op-neg-uint.
2209 if (scan_inst
->conditional_mod
&&
2210 inst
->src
[0].negate
&&
2211 inst
->src
[0].type
== BRW_REGISTER_TYPE_UD
) {
2220 /* Rewrite the later usage to point at the source of the move to
2223 for (fs_inst
*scan_inst
= inst
;
2224 !scan_inst
->is_tail_sentinel();
2225 scan_inst
= (fs_inst
*)scan_inst
->next
) {
2226 for (int i
= 0; i
< 3; i
++) {
2227 if (scan_inst
->src
[i
].file
== GRF
&&
2228 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
2229 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
2230 fs_reg new_src
= inst
->src
[0];
2231 if (scan_inst
->src
[i
].abs
) {
2235 new_src
.negate
^= scan_inst
->src
[i
].negate
;
2236 scan_inst
->src
[i
] = new_src
;
2246 live_intervals_valid
= false;
2253 fs_visitor::compute_to_mrf()
2255 bool progress
= false;
2258 calculate_live_intervals();
2260 foreach_list_safe(node
, &this->instructions
) {
2261 fs_inst
*inst
= (fs_inst
*)node
;
2266 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2267 inst
->is_partial_write() ||
2268 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2269 inst
->dst
.type
!= inst
->src
[0].type
||
2270 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
2273 /* Work out which hardware MRF registers are written by this
2276 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2278 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2279 mrf_high
= mrf_low
+ 4;
2280 } else if (dispatch_width
== 16 &&
2281 (!inst
->force_uncompressed
&& !inst
->force_sechalf
)) {
2282 mrf_high
= mrf_low
+ 1;
2287 /* Can't compute-to-MRF this GRF if someone else was going to
2290 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2293 /* Found a move of a GRF to a MRF. Let's see if we can go
2294 * rewrite the thing that made this GRF to write into the MRF.
2297 for (scan_inst
= (fs_inst
*)inst
->prev
;
2298 scan_inst
->prev
!= NULL
;
2299 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2300 if (scan_inst
->dst
.file
== GRF
&&
2301 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2302 /* Found the last thing to write our reg we want to turn
2303 * into a compute-to-MRF.
2306 /* If this one instruction didn't populate all the
2307 * channels, bail. We might be able to rewrite everything
2308 * that writes that reg, but it would require smarter
2309 * tracking to delay the rewriting until complete success.
2311 if (scan_inst
->is_partial_write())
2314 /* Things returning more than one register would need us to
2315 * understand coalescing out more than one MOV at a time.
2317 if (scan_inst
->regs_written
> 1)
2320 /* SEND instructions can't have MRF as a destination. */
2321 if (scan_inst
->mlen
)
2324 if (brw
->gen
== 6) {
2325 /* gen6 math instructions must have the destination be
2326 * GRF, so no compute-to-MRF for them.
2328 if (scan_inst
->is_math()) {
2333 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2334 /* Found the creator of our MRF's source value. */
2335 scan_inst
->dst
.file
= MRF
;
2336 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2337 scan_inst
->saturate
|= inst
->saturate
;
2344 /* We don't handle control flow here. Most computation of
2345 * values that end up in MRFs are shortly before the MRF
2348 if (scan_inst
->is_control_flow() && scan_inst
->opcode
!= BRW_OPCODE_IF
)
2351 /* You can't read from an MRF, so if someone else reads our
2352 * MRF's source GRF that we wanted to rewrite, that stops us.
2354 bool interfered
= false;
2355 for (int i
= 0; i
< 3; i
++) {
2356 if (scan_inst
->src
[i
].file
== GRF
&&
2357 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2358 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2365 if (scan_inst
->dst
.file
== MRF
) {
2366 /* If somebody else writes our MRF here, we can't
2367 * compute-to-MRF before that.
2369 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2372 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2373 scan_mrf_high
= scan_mrf_low
+ 4;
2374 } else if (dispatch_width
== 16 &&
2375 (!scan_inst
->force_uncompressed
&&
2376 !scan_inst
->force_sechalf
)) {
2377 scan_mrf_high
= scan_mrf_low
+ 1;
2379 scan_mrf_high
= scan_mrf_low
;
2382 if (mrf_low
== scan_mrf_low
||
2383 mrf_low
== scan_mrf_high
||
2384 mrf_high
== scan_mrf_low
||
2385 mrf_high
== scan_mrf_high
) {
2390 if (scan_inst
->mlen
> 0) {
2391 /* Found a SEND instruction, which means that there are
2392 * live values in MRFs from base_mrf to base_mrf +
2393 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2396 if (mrf_low
>= scan_inst
->base_mrf
&&
2397 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2400 if (mrf_high
>= scan_inst
->base_mrf
&&
2401 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2409 live_intervals_valid
= false;
2415 * Walks through basic blocks, looking for repeated MRF writes and
2416 * removing the later ones.
2419 fs_visitor::remove_duplicate_mrf_writes()
2421 fs_inst
*last_mrf_move
[16];
2422 bool progress
= false;
2424 /* Need to update the MRF tracking for compressed instructions. */
2425 if (dispatch_width
== 16)
2428 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2430 foreach_list_safe(node
, &this->instructions
) {
2431 fs_inst
*inst
= (fs_inst
*)node
;
2433 if (inst
->is_control_flow()) {
2434 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2437 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2438 inst
->dst
.file
== MRF
) {
2439 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2440 if (prev_inst
&& inst
->equals(prev_inst
)) {
2447 /* Clear out the last-write records for MRFs that were overwritten. */
2448 if (inst
->dst
.file
== MRF
) {
2449 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2452 if (inst
->mlen
> 0) {
2453 /* Found a SEND instruction, which will include two or fewer
2454 * implied MRF writes. We could do better here.
2456 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2457 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2461 /* Clear out any MRF move records whose sources got overwritten. */
2462 if (inst
->dst
.file
== GRF
) {
2463 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
2464 if (last_mrf_move
[i
] &&
2465 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2466 last_mrf_move
[i
] = NULL
;
2471 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2472 inst
->dst
.file
== MRF
&&
2473 inst
->src
[0].file
== GRF
&&
2474 !inst
->is_partial_write()) {
2475 last_mrf_move
[inst
->dst
.reg
] = inst
;
2480 live_intervals_valid
= false;
2486 clear_deps_for_inst_src(fs_inst
*inst
, int dispatch_width
, bool *deps
,
2487 int first_grf
, int grf_len
)
2489 bool inst_16wide
= (dispatch_width
> 8 &&
2490 !inst
->force_uncompressed
&&
2491 !inst
->force_sechalf
);
2493 /* Clear the flag for registers that actually got read (as expected). */
2494 for (int i
= 0; i
< 3; i
++) {
2496 if (inst
->src
[i
].file
== GRF
) {
2497 grf
= inst
->src
[i
].reg
;
2498 } else if (inst
->src
[i
].file
== HW_REG
&&
2499 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
2500 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
2505 if (grf
>= first_grf
&&
2506 grf
< first_grf
+ grf_len
) {
2507 deps
[grf
- first_grf
] = false;
2509 deps
[grf
- first_grf
+ 1] = false;
2515 * Implements this workaround for the original 965:
2517 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2518 * check for post destination dependencies on this instruction, software
2519 * must ensure that there is no destination hazard for the case of ‘write
2520 * followed by a posted write’ shown in the following example.
2523 * 2. send r3.xy <rest of send instruction>
2526 * Due to no post-destination dependency check on the ‘send’, the above
2527 * code sequence could have two instructions (1 and 2) in flight at the
2528 * same time that both consider ‘r3’ as the target of their final writes.
2531 fs_visitor::insert_gen4_pre_send_dependency_workarounds(fs_inst
*inst
)
2533 int reg_size
= dispatch_width
/ 8;
2534 int write_len
= inst
->regs_written
* reg_size
;
2535 int first_write_grf
= inst
->dst
.reg
;
2536 bool needs_dep
[BRW_MAX_MRF
];
2537 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2539 memset(needs_dep
, false, sizeof(needs_dep
));
2540 memset(needs_dep
, true, write_len
);
2542 clear_deps_for_inst_src(inst
, dispatch_width
,
2543 needs_dep
, first_write_grf
, write_len
);
2545 /* Walk backwards looking for writes to registers we're writing which
2546 * aren't read since being written. If we hit the start of the program,
2547 * we assume that there are no outstanding dependencies on entry to the
2550 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->prev
;
2552 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2554 /* If we hit control flow, assume that there *are* outstanding
2555 * dependencies, and force their cleanup before our instruction.
2557 if (scan_inst
->is_control_flow()) {
2558 for (int i
= 0; i
< write_len
; i
++) {
2560 inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2566 bool scan_inst_16wide
= (dispatch_width
> 8 &&
2567 !scan_inst
->force_uncompressed
&&
2568 !scan_inst
->force_sechalf
);
2570 /* We insert our reads as late as possible on the assumption that any
2571 * instruction but a MOV that might have left us an outstanding
2572 * dependency has more latency than a MOV.
2574 if (scan_inst
->dst
.file
== GRF
) {
2575 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2576 int reg
= scan_inst
->dst
.reg
+ i
* reg_size
;
2578 if (reg
>= first_write_grf
&&
2579 reg
< first_write_grf
+ write_len
&&
2580 needs_dep
[reg
- first_write_grf
]) {
2581 inst
->insert_before(DEP_RESOLVE_MOV(reg
));
2582 needs_dep
[reg
- first_write_grf
] = false;
2583 if (scan_inst_16wide
)
2584 needs_dep
[reg
- first_write_grf
+ 1] = false;
2589 /* Clear the flag for registers that actually got read (as expected). */
2590 clear_deps_for_inst_src(scan_inst
, dispatch_width
,
2591 needs_dep
, first_write_grf
, write_len
);
2593 /* Continue the loop only if we haven't resolved all the dependencies */
2595 for (i
= 0; i
< write_len
; i
++) {
2605 * Implements this workaround for the original 965:
2607 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2608 * used as a destination register until after it has been sourced by an
2609 * instruction with a different destination register.
2612 fs_visitor::insert_gen4_post_send_dependency_workarounds(fs_inst
*inst
)
2614 int write_len
= inst
->regs_written
* dispatch_width
/ 8;
2615 int first_write_grf
= inst
->dst
.reg
;
2616 bool needs_dep
[BRW_MAX_MRF
];
2617 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2619 memset(needs_dep
, false, sizeof(needs_dep
));
2620 memset(needs_dep
, true, write_len
);
2621 /* Walk forwards looking for writes to registers we're writing which aren't
2622 * read before being written.
2624 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->next
;
2625 !scan_inst
->is_tail_sentinel();
2626 scan_inst
= (fs_inst
*)scan_inst
->next
) {
2627 /* If we hit control flow, force resolve all remaining dependencies. */
2628 if (scan_inst
->is_control_flow()) {
2629 for (int i
= 0; i
< write_len
; i
++) {
2631 scan_inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2636 /* Clear the flag for registers that actually got read (as expected). */
2637 clear_deps_for_inst_src(scan_inst
, dispatch_width
,
2638 needs_dep
, first_write_grf
, write_len
);
2640 /* We insert our reads as late as possible since they're reading the
2641 * result of a SEND, which has massive latency.
2643 if (scan_inst
->dst
.file
== GRF
&&
2644 scan_inst
->dst
.reg
>= first_write_grf
&&
2645 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
2646 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
2647 scan_inst
->insert_before(DEP_RESOLVE_MOV(scan_inst
->dst
.reg
));
2648 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
2651 /* Continue the loop only if we haven't resolved all the dependencies */
2653 for (i
= 0; i
< write_len
; i
++) {
2661 /* If we hit the end of the program, resolve all remaining dependencies out
2664 fs_inst
*last_inst
= (fs_inst
*)this->instructions
.get_tail();
2665 assert(last_inst
->eot
);
2666 for (int i
= 0; i
< write_len
; i
++) {
2668 last_inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2673 fs_visitor::insert_gen4_send_dependency_workarounds()
2675 if (brw
->gen
!= 4 || brw
->is_g4x
)
2678 /* Note that we're done with register allocation, so GRF fs_regs always
2679 * have a .reg_offset of 0.
2682 foreach_list_safe(node
, &this->instructions
) {
2683 fs_inst
*inst
= (fs_inst
*)node
;
2685 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
2686 insert_gen4_pre_send_dependency_workarounds(inst
);
2687 insert_gen4_post_send_dependency_workarounds(inst
);
2693 * Turns the generic expression-style uniform pull constant load instruction
2694 * into a hardware-specific series of instructions for loading a pull
2697 * The expression style allows the CSE pass before this to optimize out
2698 * repeated loads from the same offset, and gives the pre-register-allocation
2699 * scheduling full flexibility, while the conversion to native instructions
2700 * allows the post-register-allocation scheduler the best information
2703 * Note that execution masking for setting up pull constant loads is special:
2704 * the channels that need to be written are unrelated to the current execution
2705 * mask, since a later instruction will use one of the result channels as a
2706 * source operand for all 8 or 16 of its channels.
2709 fs_visitor::lower_uniform_pull_constant_loads()
2711 foreach_list(node
, &this->instructions
) {
2712 fs_inst
*inst
= (fs_inst
*)node
;
2714 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
2717 if (brw
->gen
>= 7) {
2718 /* The offset arg before was a vec4-aligned byte offset. We need to
2719 * turn it into a dword offset.
2721 fs_reg const_offset_reg
= inst
->src
[1];
2722 assert(const_offset_reg
.file
== IMM
&&
2723 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
2724 const_offset_reg
.imm
.u
/= 4;
2725 fs_reg payload
= fs_reg(this, glsl_type::uint_type
);
2727 /* This is actually going to be a MOV, but since only the first dword
2728 * is accessed, we have a special opcode to do just that one. Note
2729 * that this needs to be an operation that will be considered a def
2730 * by live variable analysis, or register allocation will explode.
2732 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
2733 payload
, const_offset_reg
);
2734 setup
->force_writemask_all
= true;
2736 setup
->ir
= inst
->ir
;
2737 setup
->annotation
= inst
->annotation
;
2738 inst
->insert_before(setup
);
2740 /* Similarly, this will only populate the first 4 channels of the
2741 * result register (since we only use smear values from 0-3), but we
2742 * don't tell the optimizer.
2744 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
2745 inst
->src
[1] = payload
;
2747 this->live_intervals_valid
= false;
2749 /* Before register allocation, we didn't tell the scheduler about the
2750 * MRF we use. We know it's safe to use this MRF because nothing
2751 * else does except for register spill/unspill, which generates and
2752 * uses its MRF within a single IR instruction.
2754 inst
->base_mrf
= 14;
2761 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
2763 fs_inst
*inst
= (fs_inst
*)be_inst
;
2765 if (inst
->predicate
) {
2766 printf("(%cf0.%d) ",
2767 inst
->predicate_inverse
? '-' : '+',
2771 printf("%s", brw_instruction_name(inst
->opcode
));
2774 if (inst
->conditional_mod
) {
2776 if (!inst
->predicate
&&
2777 (brw
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
2778 inst
->opcode
!= BRW_OPCODE_IF
&&
2779 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
2780 printf(".f0.%d", inst
->flag_subreg
);
2786 switch (inst
->dst
.file
) {
2788 printf("vgrf%d", inst
->dst
.reg
);
2789 if (inst
->dst
.reg_offset
)
2790 printf("+%d", inst
->dst
.reg_offset
);
2793 printf("m%d", inst
->dst
.reg
);
2799 printf("***u%d***", inst
->dst
.reg
);
2807 for (int i
= 0; i
< 3; i
++) {
2808 if (inst
->src
[i
].negate
)
2810 if (inst
->src
[i
].abs
)
2812 switch (inst
->src
[i
].file
) {
2814 printf("vgrf%d", inst
->src
[i
].reg
);
2815 if (inst
->src
[i
].reg_offset
)
2816 printf("+%d", inst
->src
[i
].reg_offset
);
2819 printf("***m%d***", inst
->src
[i
].reg
);
2822 printf("u%d", inst
->src
[i
].reg
);
2823 if (inst
->src
[i
].reg_offset
)
2824 printf(".%d", inst
->src
[i
].reg_offset
);
2830 switch (inst
->src
[i
].type
) {
2831 case BRW_REGISTER_TYPE_F
:
2832 printf("%ff", inst
->src
[i
].imm
.f
);
2834 case BRW_REGISTER_TYPE_D
:
2835 printf("%dd", inst
->src
[i
].imm
.i
);
2837 case BRW_REGISTER_TYPE_UD
:
2838 printf("%uu", inst
->src
[i
].imm
.u
);
2849 if (inst
->src
[i
].abs
)
2858 if (inst
->force_uncompressed
)
2861 if (inst
->force_sechalf
)
2868 * Possibly returns an instruction that set up @param reg.
2870 * Sometimes we want to take the result of some expression/variable
2871 * dereference tree and rewrite the instruction generating the result
2872 * of the tree. When processing the tree, we know that the
2873 * instructions generated are all writing temporaries that are dead
2874 * outside of this tree. So, if we have some instructions that write
2875 * a temporary, we're free to point that temp write somewhere else.
2877 * Note that this doesn't guarantee that the instruction generated
2878 * only reg -- it might be the size=4 destination of a texture instruction.
2881 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
2886 end
->is_partial_write() ||
2888 !reg
.equals(end
->dst
)) {
2896 fs_visitor::setup_payload_gen6()
2899 (fp
->Base
.InputsRead
& (1 << VARYING_SLOT_POS
)) != 0;
2900 unsigned barycentric_interp_modes
= c
->prog_data
.barycentric_interp_modes
;
2902 assert(brw
->gen
>= 6);
2904 /* R0-1: masks, pixel X/Y coordinates. */
2905 c
->nr_payload_regs
= 2;
2906 /* R2: only for 32-pixel dispatch.*/
2908 /* R3-26: barycentric interpolation coordinates. These appear in the
2909 * same order that they appear in the brw_wm_barycentric_interp_mode
2910 * enum. Each set of coordinates occupies 2 registers if dispatch width
2911 * == 8 and 4 registers if dispatch width == 16. Coordinates only
2912 * appear if they were enabled using the "Barycentric Interpolation
2913 * Mode" bits in WM_STATE.
2915 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
2916 if (barycentric_interp_modes
& (1 << i
)) {
2917 c
->barycentric_coord_reg
[i
] = c
->nr_payload_regs
;
2918 c
->nr_payload_regs
+= 2;
2919 if (dispatch_width
== 16) {
2920 c
->nr_payload_regs
+= 2;
2925 /* R27: interpolated depth if uses source depth */
2927 c
->source_depth_reg
= c
->nr_payload_regs
;
2928 c
->nr_payload_regs
++;
2929 if (dispatch_width
== 16) {
2930 /* R28: interpolated depth if not 8-wide. */
2931 c
->nr_payload_regs
++;
2934 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
2936 c
->source_w_reg
= c
->nr_payload_regs
;
2937 c
->nr_payload_regs
++;
2938 if (dispatch_width
== 16) {
2939 /* R30: interpolated W if not 8-wide. */
2940 c
->nr_payload_regs
++;
2943 /* R31: MSAA position offsets. */
2944 /* R32-: bary for 32-pixel. */
2945 /* R58-59: interp W for 32-pixel. */
2947 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
2948 c
->source_depth_to_render_target
= true;
2955 sanity_param_count
= fp
->Base
.Parameters
->NumParameters
;
2956 uint32_t orig_nr_params
= c
->prog_data
.nr_params
;
2959 setup_payload_gen6();
2961 setup_payload_gen4();
2966 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2967 emit_shader_time_begin();
2969 calculate_urb_setup();
2971 emit_interpolation_setup_gen4();
2973 emit_interpolation_setup_gen6();
2975 /* We handle discards by keeping track of the still-live pixels in f0.1.
2976 * Initialize it with the dispatched pixels.
2979 fs_inst
*discard_init
= emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
2980 discard_init
->flag_subreg
= 1;
2983 /* Generate FS IR for main(). (the visitor only descends into
2984 * functions called "main").
2987 foreach_list(node
, &*shader
->ir
) {
2988 ir_instruction
*ir
= (ir_instruction
*)node
;
2990 this->result
= reg_undef
;
2994 emit_fragment_program_code();
3000 emit(FS_OPCODE_PLACEHOLDER_HALT
);
3004 split_virtual_grfs();
3006 move_uniform_array_access_to_pull_constants();
3007 setup_pull_constants();
3013 compact_virtual_grfs();
3015 progress
= remove_duplicate_mrf_writes() || progress
;
3017 progress
= opt_algebraic() || progress
;
3018 progress
= opt_cse() || progress
;
3019 progress
= opt_copy_propagate() || progress
;
3020 progress
= dead_code_eliminate() || progress
;
3021 progress
= dead_code_eliminate_local() || progress
;
3022 progress
= register_coalesce() || progress
;
3023 progress
= register_coalesce_2() || progress
;
3024 progress
= compute_to_mrf() || progress
;
3027 remove_dead_constants();
3029 schedule_instructions(false);
3031 lower_uniform_pull_constant_loads();
3033 assign_curb_setup();
3037 /* Debug of register spilling: Go spill everything. */
3038 for (int i
= 0; i
< virtual_grf_count
; i
++) {
3044 assign_regs_trivial();
3046 while (!assign_regs()) {
3052 assert(force_uncompressed_stack
== 0);
3053 assert(force_sechalf_stack
== 0);
3055 /* This must come after all optimization and register allocation, since
3056 * it inserts dead code that happens to have side effects, and it does
3057 * so based on the actual physical registers in use.
3059 insert_gen4_send_dependency_workarounds();
3064 schedule_instructions(true);
3066 if (dispatch_width
== 8) {
3067 c
->prog_data
.reg_blocks
= brw_register_blocks(grf_used
);
3069 c
->prog_data
.reg_blocks_16
= brw_register_blocks(grf_used
);
3071 /* Make sure we didn't try to sneak in an extra uniform */
3072 assert(orig_nr_params
== c
->prog_data
.nr_params
);
3073 (void) orig_nr_params
;
3076 /* If any state parameters were appended, then ParameterValues could have
3077 * been realloced, in which case the driver uniform storage set up by
3078 * _mesa_associate_uniform_storage() would point to freed memory. Make
3079 * sure that didn't happen.
3081 assert(sanity_param_count
== fp
->Base
.Parameters
->NumParameters
);
3087 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
,
3088 struct gl_fragment_program
*fp
,
3089 struct gl_shader_program
*prog
,
3090 unsigned *final_assembly_size
)
3092 bool start_busy
= false;
3093 float start_time
= 0;
3095 if (unlikely(brw
->perf_debug
)) {
3096 start_busy
= (brw
->batch
.last_bo
&&
3097 drm_intel_bo_busy(brw
->batch
.last_bo
));
3098 start_time
= get_time();
3101 struct brw_shader
*shader
= NULL
;
3103 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3105 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3107 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3108 _mesa_print_ir(shader
->ir
, NULL
);
3111 printf("ARB_fragment_program %d ir for native fragment shader\n",
3113 _mesa_print_program(&fp
->Base
);
3117 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3119 fs_visitor
v(brw
, c
, prog
, fp
, 8);
3122 prog
->LinkStatus
= false;
3123 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
3126 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
3132 exec_list
*simd16_instructions
= NULL
;
3133 fs_visitor
v2(brw
, c
, prog
, fp
, 16);
3134 if (brw
->gen
>= 5 && likely(!(INTEL_DEBUG
& DEBUG_NO16
))) {
3135 if (c
->prog_data
.nr_pull_params
== 0) {
3136 /* Try a 16-wide compile */
3137 v2
.import_uniforms(&v
);
3139 perf_debug("16-wide shader failed to compile, falling back to "
3140 "8-wide at a 10-20%% performance cost: %s", v2
.fail_msg
);
3142 simd16_instructions
= &v2
.instructions
;
3145 perf_debug("Skipping 16-wide due to pull parameters.\n");
3149 c
->prog_data
.dispatch_width
= 8;
3151 fs_generator
g(brw
, c
, prog
, fp
, v
.dual_src_output
.file
!= BAD_FILE
);
3152 const unsigned *generated
= g
.generate_assembly(&v
.instructions
,
3153 simd16_instructions
,
3154 final_assembly_size
);
3156 if (unlikely(brw
->perf_debug
) && shader
) {
3157 if (shader
->compiled_once
)
3158 brw_wm_debug_recompile(brw
, prog
, &c
->key
);
3159 shader
->compiled_once
= true;
3161 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
3162 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
3163 (get_time() - start_time
) * 1000);
3171 brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
3173 struct brw_context
*brw
= brw_context(ctx
);
3174 struct brw_wm_prog_key key
;
3176 if (!prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
])
3179 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)
3180 prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
]->Program
;
3181 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
3182 bool program_uses_dfdy
= fp
->UsesDFdy
;
3184 memset(&key
, 0, sizeof(key
));
3188 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
3190 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
3191 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
3193 /* Just assume depth testing. */
3194 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
3195 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
3198 if (brw
->gen
< 6 || _mesa_bitcount_64(fp
->Base
.InputsRead
&
3199 BRW_FS_VARYING_INPUT_MASK
) > 16)
3200 key
.input_slots_valid
= fp
->Base
.InputsRead
| VARYING_BIT_POS
;
3202 key
.clamp_fragment_color
= ctx
->API
== API_OPENGL_COMPAT
;
3204 unsigned sampler_count
= _mesa_fls(fp
->Base
.SamplersUsed
);
3205 for (unsigned i
= 0; i
< sampler_count
; i
++) {
3206 if (fp
->Base
.ShadowSamplers
& (1 << i
)) {
3207 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
3208 key
.tex
.swizzles
[i
] =
3209 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
3211 /* Color sampler: assume no swizzling. */
3212 key
.tex
.swizzles
[i
] = SWIZZLE_XYZW
;
3216 if (fp
->Base
.InputsRead
& VARYING_BIT_POS
) {
3217 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
3220 if ((fp
->Base
.InputsRead
& VARYING_BIT_POS
) || program_uses_dfdy
) {
3221 key
.render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3224 key
.nr_color_regions
= 1;
3226 /* GL_FRAGMENT_SHADER_DERIVATIVE_HINT is almost always GL_DONT_CARE. The
3227 * quality of the derivatives is likely to be determined by the driconf
3230 key
.high_quality_derivatives
= brw
->disable_derivative_optimization
;
3232 key
.program_string_id
= bfp
->id
;
3234 uint32_t old_prog_offset
= brw
->wm
.base
.prog_offset
;
3235 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
3237 bool success
= do_wm_prog(brw
, prog
, bfp
, &key
);
3239 brw
->wm
.base
.prog_offset
= old_prog_offset
;
3240 brw
->wm
.prog_data
= old_prog_data
;