2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
33 #include <sys/types.h>
35 #include "main/hash_table.h"
36 #include "main/macros.h"
37 #include "main/shaderobj.h"
38 #include "main/fbobject.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/register_allocate.h"
42 #include "program/sampler.h"
43 #include "program/hash_table.h"
44 #include "brw_context.h"
49 #include "brw_dead_control_flow.h"
50 #include "main/uniforms.h"
51 #include "brw_fs_live_variables.h"
52 #include "glsl/glsl_types.h"
55 fs_inst::init(enum opcode opcode
, const fs_reg
&dst
, fs_reg
*src
, int sources
)
57 memset(this, 0, sizeof(*this));
59 this->opcode
= opcode
;
62 this->sources
= sources
;
64 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
66 /* This will be the case for almost all instructions. */
67 this->regs_written
= 1;
69 this->writes_accumulator
= false;
72 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
)
74 fs_reg
*src
= ralloc_array(this, fs_reg
, 3);
75 init(opcode
, dst
, src
, 0);
78 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
)
80 fs_reg
*src
= ralloc_array(this, fs_reg
, 3);
82 init(opcode
, dst
, src
, 1);
85 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
88 fs_reg
*src
= ralloc_array(this, fs_reg
, 3);
91 init(opcode
, dst
, src
, 2);
94 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
95 const fs_reg
&src1
, const fs_reg
&src2
)
97 fs_reg
*src
= ralloc_array(this, fs_reg
, 3);
101 init(opcode
, dst
, src
, 3);
104 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, fs_reg src
[], int sources
)
106 init(opcode
, dst
, src
, sources
);
109 fs_inst::fs_inst(const fs_inst
&that
)
111 memcpy(this, &that
, sizeof(that
));
113 this->src
= ralloc_array(this, fs_reg
, that
.sources
);
115 for (int i
= 0; i
< that
.sources
; i
++)
116 this->src
[i
] = that
.src
[i
];
120 fs_inst::resize_sources(uint8_t num_sources
)
122 if (this->sources
!= num_sources
) {
123 this->src
= reralloc(this, this->src
, fs_reg
, num_sources
);
124 this->sources
= num_sources
;
130 fs_visitor::op(fs_reg dst, fs_reg src0) \
132 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0); \
137 fs_visitor::op(fs_reg dst, fs_reg src0, fs_reg src1) \
139 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1); \
142 #define ALU2_ACC(op) \
144 fs_visitor::op(fs_reg dst, fs_reg src0, fs_reg src1) \
146 fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1);\
147 inst->writes_accumulator = true; \
153 fs_visitor::op(fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2) \
155 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1, src2);\
187 /** Gen4 predicated IF. */
189 fs_visitor::IF(uint32_t predicate
)
191 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
);
192 inst
->predicate
= predicate
;
196 /** Gen6 IF with embedded comparison. */
198 fs_visitor::IF(fs_reg src0
, fs_reg src1
, uint32_t condition
)
200 assert(brw
->gen
== 6);
201 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
,
202 reg_null_d
, src0
, src1
);
203 inst
->conditional_mod
= condition
;
208 * CMP: Sets the low bit of the destination channels with the result
209 * of the comparison, while the upper bits are undefined, and updates
210 * the flag register with the packed 16 bits of the result.
213 fs_visitor::CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
, uint32_t condition
)
217 /* Take the instruction:
219 * CMP null<d> src0<f> src1<f>
221 * Original gen4 does type conversion to the destination type before
222 * comparison, producing garbage results for floating point comparisons.
223 * gen5 does the comparison on the execution type (resolved source types),
224 * so dst type doesn't matter. gen6 does comparison and then uses the
225 * result as if it was the dst type with no conversion, which happens to
226 * mostly work out for float-interpreted-as-int since our comparisons are
230 dst
.type
= src0
.type
;
231 if (dst
.file
== HW_REG
)
232 dst
.fixed_hw_reg
.type
= dst
.type
;
235 resolve_ud_negate(&src0
);
236 resolve_ud_negate(&src1
);
238 inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_CMP
, dst
, src0
, src1
);
239 inst
->conditional_mod
= condition
;
245 fs_visitor::LOAD_PAYLOAD(const fs_reg
&dst
, fs_reg
*src
, int sources
)
247 fs_inst
*inst
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
, dst
, src
,
249 inst
->regs_written
= sources
;
255 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_reg
&dst
,
256 const fs_reg
&surf_index
,
257 const fs_reg
&varying_offset
,
258 uint32_t const_offset
)
260 exec_list instructions
;
263 /* We have our constant surface use a pitch of 4 bytes, so our index can
264 * be any component of a vector, and then we load 4 contiguous
265 * components starting from that.
267 * We break down the const_offset to a portion added to the variable
268 * offset and a portion done using reg_offset, which means that if you
269 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
270 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
271 * CSE can later notice that those loads are all the same and eliminate
272 * the redundant ones.
274 fs_reg vec4_offset
= fs_reg(this, glsl_type::int_type
);
275 instructions
.push_tail(ADD(vec4_offset
,
276 varying_offset
, const_offset
& ~3));
279 if (brw
->gen
== 4 && dispatch_width
== 8) {
280 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
281 * u, v, r) as parameters, or we can just use the SIMD16 message
282 * consisting of (header, u). We choose the second, at the cost of a
283 * longer return length.
290 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
292 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
293 fs_reg vec4_result
= fs_reg(GRF
, virtual_grf_alloc(4 * scale
), dst
.type
);
294 inst
= new(mem_ctx
) fs_inst(op
, vec4_result
, surf_index
, vec4_offset
);
295 inst
->regs_written
= 4 * scale
;
296 instructions
.push_tail(inst
);
300 inst
->header_present
= true;
304 inst
->mlen
= 1 + dispatch_width
/ 8;
307 vec4_result
.reg_offset
+= (const_offset
& 3) * scale
;
308 instructions
.push_tail(MOV(dst
, vec4_result
));
314 * A helper for MOV generation for fixing up broken hardware SEND dependency
318 fs_visitor::DEP_RESOLVE_MOV(int grf
)
320 fs_inst
*inst
= MOV(brw_null_reg(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
323 inst
->annotation
= "send dependency resolve";
325 /* The caller always wants uncompressed to emit the minimal extra
326 * dependencies, and to avoid having to deal with aligning its regs to 2.
328 inst
->force_uncompressed
= true;
334 fs_inst::equals(fs_inst
*inst
) const
336 return (opcode
== inst
->opcode
&&
337 dst
.equals(inst
->dst
) &&
338 src
[0].equals(inst
->src
[0]) &&
339 src
[1].equals(inst
->src
[1]) &&
340 src
[2].equals(inst
->src
[2]) &&
341 saturate
== inst
->saturate
&&
342 predicate
== inst
->predicate
&&
343 conditional_mod
== inst
->conditional_mod
&&
344 mlen
== inst
->mlen
&&
345 base_mrf
== inst
->base_mrf
&&
346 sampler
== inst
->sampler
&&
347 target
== inst
->target
&&
349 header_present
== inst
->header_present
&&
350 shadow_compare
== inst
->shadow_compare
&&
351 offset
== inst
->offset
);
355 fs_inst::overwrites_reg(const fs_reg
®
) const
357 return (reg
.file
== dst
.file
&&
358 reg
.reg
== dst
.reg
&&
359 reg
.reg_offset
>= dst
.reg_offset
&&
360 reg
.reg_offset
< dst
.reg_offset
+ regs_written
);
364 fs_inst::is_send_from_grf() const
366 return (opcode
== FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
||
367 opcode
== SHADER_OPCODE_SHADER_TIME_ADD
||
368 (opcode
== FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
&&
369 src
[1].file
== GRF
) ||
370 (is_tex() && src
[0].file
== GRF
));
374 fs_visitor::can_do_source_mods(fs_inst
*inst
)
376 if (brw
->gen
== 6 && inst
->is_math())
379 if (inst
->is_send_from_grf())
382 if (!inst
->can_do_source_mods())
391 memset(this, 0, sizeof(*this));
395 /** Generic unset register constructor. */
399 this->file
= BAD_FILE
;
402 /** Immediate value constructor. */
403 fs_reg::fs_reg(float f
)
407 this->type
= BRW_REGISTER_TYPE_F
;
411 /** Immediate value constructor. */
412 fs_reg::fs_reg(int32_t i
)
416 this->type
= BRW_REGISTER_TYPE_D
;
420 /** Immediate value constructor. */
421 fs_reg::fs_reg(uint32_t u
)
425 this->type
= BRW_REGISTER_TYPE_UD
;
429 /** Fixed brw_reg. */
430 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
434 this->fixed_hw_reg
= fixed_hw_reg
;
435 this->type
= fixed_hw_reg
.type
;
439 fs_reg::equals(const fs_reg
&r
) const
441 return (file
== r
.file
&&
443 reg_offset
== r
.reg_offset
&&
444 subreg_offset
== r
.subreg_offset
&&
446 negate
== r
.negate
&&
448 !reladdr
&& !r
.reladdr
&&
449 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
450 sizeof(fixed_hw_reg
)) == 0 &&
451 stride
== r
.stride
&&
456 fs_reg::apply_stride(unsigned stride
)
458 assert((this->stride
* stride
) <= 4 &&
459 (is_power_of_two(stride
) || stride
== 0) &&
460 file
!= HW_REG
&& file
!= IMM
);
461 this->stride
*= stride
;
466 fs_reg::set_smear(unsigned subreg
)
468 assert(file
!= HW_REG
&& file
!= IMM
);
469 subreg_offset
= subreg
* type_sz(type
);
475 fs_reg::is_contiguous() const
481 fs_reg::is_zero() const
486 return type
== BRW_REGISTER_TYPE_F
? imm
.f
== 0.0 : imm
.i
== 0;
490 fs_reg::is_one() const
495 return type
== BRW_REGISTER_TYPE_F
? imm
.f
== 1.0 : imm
.i
== 1;
499 fs_reg::is_null() const
501 return file
== HW_REG
&&
502 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
503 fixed_hw_reg
.nr
== BRW_ARF_NULL
;
507 fs_reg::is_valid_3src() const
509 return file
== GRF
|| file
== UNIFORM
;
513 fs_reg::is_accumulator() const
515 return file
== HW_REG
&&
516 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
517 fixed_hw_reg
.nr
== BRW_ARF_ACCUMULATOR
;
521 fs_visitor::type_size(const struct glsl_type
*type
)
523 unsigned int size
, i
;
525 switch (type
->base_type
) {
528 case GLSL_TYPE_FLOAT
:
530 return type
->components();
531 case GLSL_TYPE_ARRAY
:
532 return type_size(type
->fields
.array
) * type
->length
;
533 case GLSL_TYPE_STRUCT
:
535 for (i
= 0; i
< type
->length
; i
++) {
536 size
+= type_size(type
->fields
.structure
[i
].type
);
539 case GLSL_TYPE_SAMPLER
:
540 /* Samplers take up no register space, since they're baked in at
544 case GLSL_TYPE_ATOMIC_UINT
:
546 case GLSL_TYPE_IMAGE
:
548 case GLSL_TYPE_ERROR
:
549 case GLSL_TYPE_INTERFACE
:
550 assert(!"not reached");
558 fs_visitor::get_timestamp()
560 assert(brw
->gen
>= 7);
562 fs_reg ts
= fs_reg(retype(brw_vec1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
565 BRW_REGISTER_TYPE_UD
));
567 fs_reg dst
= fs_reg(this, glsl_type::uint_type
);
569 fs_inst
*mov
= emit(MOV(dst
, ts
));
570 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
571 * even if it's not enabled in the dispatch.
573 mov
->force_writemask_all
= true;
574 mov
->force_uncompressed
= true;
576 /* The caller wants the low 32 bits of the timestamp. Since it's running
577 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
578 * which is plenty of time for our purposes. It is identical across the
579 * EUs, but since it's tracking GPU core speed it will increment at a
580 * varying rate as render P-states change.
582 * The caller could also check if render P-states have changed (or anything
583 * else that might disrupt timing) by setting smear to 2 and checking if
584 * that field is != 0.
592 fs_visitor::emit_shader_time_begin()
594 current_annotation
= "shader time start";
595 shader_start_time
= get_timestamp();
599 fs_visitor::emit_shader_time_end()
601 current_annotation
= "shader time end";
603 enum shader_time_shader_type type
, written_type
, reset_type
;
604 if (dispatch_width
== 8) {
606 written_type
= ST_FS8_WRITTEN
;
607 reset_type
= ST_FS8_RESET
;
609 assert(dispatch_width
== 16);
611 written_type
= ST_FS16_WRITTEN
;
612 reset_type
= ST_FS16_RESET
;
615 fs_reg shader_end_time
= get_timestamp();
617 /* Check that there weren't any timestamp reset events (assuming these
618 * were the only two timestamp reads that happened).
620 fs_reg reset
= shader_end_time
;
622 fs_inst
*test
= emit(AND(reg_null_d
, reset
, fs_reg(1u)));
623 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
624 emit(IF(BRW_PREDICATE_NORMAL
));
626 push_force_uncompressed();
627 fs_reg start
= shader_start_time
;
629 fs_reg diff
= fs_reg(this, glsl_type::uint_type
);
630 emit(ADD(diff
, start
, shader_end_time
));
632 /* If there were no instructions between the two timestamp gets, the diff
633 * is 2 cycles. Remove that overhead, so I can forget about that when
634 * trying to determine the time taken for single instructions.
636 emit(ADD(diff
, diff
, fs_reg(-2u)));
638 emit_shader_time_write(type
, diff
);
639 emit_shader_time_write(written_type
, fs_reg(1u));
640 emit(BRW_OPCODE_ELSE
);
641 emit_shader_time_write(reset_type
, fs_reg(1u));
642 emit(BRW_OPCODE_ENDIF
);
644 pop_force_uncompressed();
648 fs_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
651 int shader_time_index
=
652 brw_get_shader_time_index(brw
, shader_prog
, &fp
->Base
, type
);
653 fs_reg offset
= fs_reg(shader_time_index
* SHADER_TIME_STRIDE
);
656 if (dispatch_width
== 8)
657 payload
= fs_reg(this, glsl_type::uvec2_type
);
659 payload
= fs_reg(this, glsl_type::uint_type
);
661 emit(new(mem_ctx
) fs_inst(SHADER_OPCODE_SHADER_TIME_ADD
,
662 fs_reg(), payload
, offset
, value
));
666 fs_visitor::vfail(const char *format
, va_list va
)
675 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
676 msg
= ralloc_asprintf(mem_ctx
, "FS compile failed: %s\n", msg
);
678 this->fail_msg
= msg
;
680 if (INTEL_DEBUG
& DEBUG_WM
) {
681 fprintf(stderr
, "%s", msg
);
686 fs_visitor::fail(const char *format
, ...)
690 va_start(va
, format
);
696 * Mark this program as impossible to compile in SIMD16 mode.
698 * During the SIMD8 compile (which happens first), we can detect and flag
699 * things that are unsupported in SIMD16 mode, so the compiler can skip
700 * the SIMD16 compile altogether.
702 * During a SIMD16 compile (if one happens anyway), this just calls fail().
705 fs_visitor::no16(const char *format
, ...)
709 va_start(va
, format
);
711 if (dispatch_width
== 16) {
714 simd16_unsupported
= true;
716 if (brw
->perf_debug
) {
718 ralloc_vasprintf_append(&no16_msg
, format
, va
);
720 no16_msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
728 fs_visitor::emit(enum opcode opcode
)
730 return emit(new(mem_ctx
) fs_inst(opcode
));
734 fs_visitor::emit(enum opcode opcode
, fs_reg dst
)
736 return emit(new(mem_ctx
) fs_inst(opcode
, dst
));
740 fs_visitor::emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
)
742 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
));
746 fs_visitor::emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
748 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
, src1
));
752 fs_visitor::emit(enum opcode opcode
, fs_reg dst
,
753 fs_reg src0
, fs_reg src1
, fs_reg src2
)
755 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
, src1
, src2
));
759 fs_visitor::emit(enum opcode opcode
, fs_reg dst
,
760 fs_reg src
[], int sources
)
762 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src
, sources
));
766 fs_visitor::push_force_uncompressed()
768 force_uncompressed_stack
++;
772 fs_visitor::pop_force_uncompressed()
774 force_uncompressed_stack
--;
775 assert(force_uncompressed_stack
>= 0);
779 * Returns true if the instruction has a flag that means it won't
780 * update an entire destination register.
782 * For example, dead code elimination and live variable analysis want to know
783 * when a write to a variable screens off any preceding values that were in
787 fs_inst::is_partial_write() const
789 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
790 this->force_uncompressed
||
791 this->force_sechalf
|| !this->dst
.is_contiguous());
795 fs_inst::regs_read(fs_visitor
*v
, int arg
) const
797 if (is_tex() && arg
== 0 && src
[0].file
== GRF
) {
798 if (v
->dispatch_width
== 16)
799 return (mlen
+ 1) / 2;
807 fs_inst::reads_flag() const
813 fs_inst::writes_flag() const
815 return (conditional_mod
&& opcode
!= BRW_OPCODE_SEL
) ||
816 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
820 * Returns how many MRFs an FS opcode will write over.
822 * Note that this is not the 0 or 1 implied writes in an actual gen
823 * instruction -- the FS opcodes often generate MOVs in addition.
826 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
831 if (inst
->base_mrf
== -1)
834 switch (inst
->opcode
) {
835 case SHADER_OPCODE_RCP
:
836 case SHADER_OPCODE_RSQ
:
837 case SHADER_OPCODE_SQRT
:
838 case SHADER_OPCODE_EXP2
:
839 case SHADER_OPCODE_LOG2
:
840 case SHADER_OPCODE_SIN
:
841 case SHADER_OPCODE_COS
:
842 return 1 * dispatch_width
/ 8;
843 case SHADER_OPCODE_POW
:
844 case SHADER_OPCODE_INT_QUOTIENT
:
845 case SHADER_OPCODE_INT_REMAINDER
:
846 return 2 * dispatch_width
/ 8;
847 case SHADER_OPCODE_TEX
:
849 case SHADER_OPCODE_TXD
:
850 case SHADER_OPCODE_TXF
:
851 case SHADER_OPCODE_TXF_CMS
:
852 case SHADER_OPCODE_TXF_MCS
:
853 case SHADER_OPCODE_TG4
:
854 case SHADER_OPCODE_TG4_OFFSET
:
855 case SHADER_OPCODE_TXL
:
856 case SHADER_OPCODE_TXS
:
857 case SHADER_OPCODE_LOD
:
859 case FS_OPCODE_FB_WRITE
:
861 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
862 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
864 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
866 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
868 case SHADER_OPCODE_UNTYPED_ATOMIC
:
869 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
872 assert(!"not reached");
878 fs_visitor::virtual_grf_alloc(int size
)
880 if (virtual_grf_array_size
<= virtual_grf_count
) {
881 if (virtual_grf_array_size
== 0)
882 virtual_grf_array_size
= 16;
884 virtual_grf_array_size
*= 2;
885 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
886 virtual_grf_array_size
);
888 virtual_grf_sizes
[virtual_grf_count
] = size
;
889 return virtual_grf_count
++;
892 /** Fixed HW reg constructor. */
893 fs_reg::fs_reg(enum register_file file
, int reg
)
898 this->type
= BRW_REGISTER_TYPE_F
;
901 /** Fixed HW reg constructor. */
902 fs_reg::fs_reg(enum register_file file
, int reg
, uint32_t type
)
910 /** Automatic reg constructor. */
911 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
916 this->reg
= v
->virtual_grf_alloc(v
->type_size(type
));
917 this->reg_offset
= 0;
918 this->type
= brw_type_for_base_type(type
);
922 fs_visitor::variable_storage(ir_variable
*var
)
924 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
928 import_uniforms_callback(const void *key
,
932 struct hash_table
*dst_ht
= (struct hash_table
*)closure
;
933 const fs_reg
*reg
= (const fs_reg
*)data
;
935 if (reg
->file
!= UNIFORM
)
938 hash_table_insert(dst_ht
, data
, key
);
941 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
942 * This brings in those uniform definitions
945 fs_visitor::import_uniforms(fs_visitor
*v
)
947 hash_table_call_foreach(v
->variable_ht
,
948 import_uniforms_callback
,
950 this->push_constant_loc
= v
->push_constant_loc
;
951 this->pull_constant_loc
= v
->pull_constant_loc
;
952 this->uniforms
= v
->uniforms
;
953 this->param_size
= v
->param_size
;
956 /* Our support for uniforms is piggy-backed on the struct
957 * gl_fragment_program, because that's where the values actually
958 * get stored, rather than in some global gl_shader_program uniform
962 fs_visitor::setup_uniform_values(ir_variable
*ir
)
964 int namelen
= strlen(ir
->name
);
966 /* The data for our (non-builtin) uniforms is stored in a series of
967 * gl_uniform_driver_storage structs for each subcomponent that
968 * glGetUniformLocation() could name. We know it's been set up in the same
969 * order we'd walk the type, so walk the list of storage and find anything
970 * with our name, or the prefix of a component that starts with our name.
972 unsigned params_before
= uniforms
;
973 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
974 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
976 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
977 (storage
->name
[namelen
] != 0 &&
978 storage
->name
[namelen
] != '.' &&
979 storage
->name
[namelen
] != '[')) {
983 unsigned slots
= storage
->type
->component_slots();
984 if (storage
->array_elements
)
985 slots
*= storage
->array_elements
;
987 for (unsigned i
= 0; i
< slots
; i
++) {
988 stage_prog_data
->param
[uniforms
++] = &storage
->storage
[i
].f
;
992 /* Make sure we actually initialized the right amount of stuff here. */
993 assert(params_before
+ ir
->type
->component_slots() == uniforms
);
998 /* Our support for builtin uniforms is even scarier than non-builtin.
999 * It sits on top of the PROG_STATE_VAR parameters that are
1000 * automatically updated from GL context state.
1003 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
1005 const ir_state_slot
*const slots
= ir
->state_slots
;
1006 assert(ir
->state_slots
!= NULL
);
1008 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
1009 /* This state reference has already been setup by ir_to_mesa, but we'll
1010 * get the same index back here.
1012 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
1013 (gl_state_index
*)slots
[i
].tokens
);
1015 /* Add each of the unique swizzles of the element as a parameter.
1016 * This'll end up matching the expected layout of the
1017 * array/matrix/structure we're trying to fill in.
1020 for (unsigned int j
= 0; j
< 4; j
++) {
1021 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
1022 if (swiz
== last_swiz
)
1026 stage_prog_data
->param
[uniforms
++] =
1027 &fp
->Base
.Parameters
->ParameterValues
[index
][swiz
].f
;
1033 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
1035 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1037 bool flip
= !ir
->data
.origin_upper_left
^ key
->render_to_fbo
;
1039 /* gl_FragCoord.x */
1040 if (ir
->data
.pixel_center_integer
) {
1041 emit(MOV(wpos
, this->pixel_x
));
1043 emit(ADD(wpos
, this->pixel_x
, fs_reg(0.5f
)));
1047 /* gl_FragCoord.y */
1048 if (!flip
&& ir
->data
.pixel_center_integer
) {
1049 emit(MOV(wpos
, this->pixel_y
));
1051 fs_reg pixel_y
= this->pixel_y
;
1052 float offset
= (ir
->data
.pixel_center_integer
? 0.0 : 0.5);
1055 pixel_y
.negate
= true;
1056 offset
+= key
->drawable_height
- 1.0;
1059 emit(ADD(wpos
, pixel_y
, fs_reg(offset
)));
1063 /* gl_FragCoord.z */
1064 if (brw
->gen
>= 6) {
1065 emit(MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0))));
1067 emit(FS_OPCODE_LINTERP
, wpos
,
1068 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1069 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1070 interp_reg(VARYING_SLOT_POS
, 2));
1074 /* gl_FragCoord.w: Already set up in emit_interpolation */
1075 emit(BRW_OPCODE_MOV
, wpos
, this->wpos_w
);
1081 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1082 glsl_interp_qualifier interpolation_mode
,
1083 bool is_centroid
, bool is_sample
)
1085 brw_wm_barycentric_interp_mode barycoord_mode
;
1086 if (brw
->gen
>= 6) {
1088 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1089 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1091 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1092 } else if (is_sample
) {
1093 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1094 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1096 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1098 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1099 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1101 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1104 /* On Ironlake and below, there is only one interpolation mode.
1105 * Centroid interpolation doesn't mean anything on this hardware --
1106 * there is no multisampling.
1108 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1110 return emit(FS_OPCODE_LINTERP
, attr
,
1111 this->delta_x
[barycoord_mode
],
1112 this->delta_y
[barycoord_mode
], interp
);
1116 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
1118 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1119 reg
->type
= brw_type_for_base_type(ir
->type
->get_scalar_type());
1122 unsigned int array_elements
;
1123 const glsl_type
*type
;
1125 if (ir
->type
->is_array()) {
1126 array_elements
= ir
->type
->length
;
1127 if (array_elements
== 0) {
1128 fail("dereferenced array '%s' has length 0\n", ir
->name
);
1130 type
= ir
->type
->fields
.array
;
1136 glsl_interp_qualifier interpolation_mode
=
1137 ir
->determine_interpolation_mode(key
->flat_shade
);
1139 int location
= ir
->data
.location
;
1140 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1141 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1142 if (prog_data
->urb_setup
[location
] == -1) {
1143 /* If there's no incoming setup data for this slot, don't
1144 * emit interpolation for it.
1146 attr
.reg_offset
+= type
->vector_elements
;
1151 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1152 /* Constant interpolation (flat shading) case. The SF has
1153 * handed us defined values in only the constant offset
1154 * field of the setup reg.
1156 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1157 struct brw_reg interp
= interp_reg(location
, k
);
1158 interp
= suboffset(interp
, 3);
1159 interp
.type
= reg
->type
;
1160 emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1164 /* Smooth/noperspective interpolation case. */
1165 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1166 struct brw_reg interp
= interp_reg(location
, k
);
1167 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1168 ir
->data
.centroid
&& !key
->persample_shading
,
1169 ir
->data
.sample
|| key
->persample_shading
);
1170 if (brw
->needs_unlit_centroid_workaround
&& ir
->data
.centroid
) {
1171 /* Get the pixel/sample mask into f0 so that we know
1172 * which pixels are lit. Then, for each channel that is
1173 * unlit, replace the centroid data with non-centroid
1176 emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1177 fs_inst
*inst
= emit_linterp(attr
, fs_reg(interp
),
1180 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1181 inst
->predicate_inverse
= true;
1183 if (brw
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1184 emit(BRW_OPCODE_MUL
, attr
, attr
, this->pixel_w
);
1198 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
1200 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1202 /* The frontfacing comes in as a bit in the thread payload. */
1203 if (brw
->gen
>= 6) {
1204 emit(BRW_OPCODE_ASR
, *reg
,
1205 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1207 emit(BRW_OPCODE_NOT
, *reg
, *reg
);
1208 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1));
1210 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
1211 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
1214 emit(CMP(*reg
, fs_reg(r1_6ud
), fs_reg(1u << 31), BRW_CONDITIONAL_L
));
1215 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u));
1222 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1224 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1226 if (key
->compute_pos_offset
) {
1227 /* Convert int_sample_pos to floating point */
1228 emit(MOV(dst
, int_sample_pos
));
1229 /* Scale to the range [0, 1] */
1230 emit(MUL(dst
, dst
, fs_reg(1 / 16.0f
)));
1233 /* From ARB_sample_shading specification:
1234 * "When rendering to a non-multisample buffer, or if multisample
1235 * rasterization is disabled, gl_SamplePosition will always be
1238 emit(MOV(dst
, fs_reg(0.5f
)));
1243 fs_visitor::emit_samplepos_setup(ir_variable
*ir
)
1245 assert(brw
->gen
>= 6);
1246 assert(ir
->type
== glsl_type::vec2_type
);
1248 this->current_annotation
= "compute sample position";
1249 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1251 fs_reg int_sample_x
= fs_reg(this, glsl_type::int_type
);
1252 fs_reg int_sample_y
= fs_reg(this, glsl_type::int_type
);
1254 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1255 * mode will be enabled.
1257 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1258 * R31.1:0 Position Offset X/Y for Slot[3:0]
1259 * R31.3:2 Position Offset X/Y for Slot[7:4]
1262 * The X, Y sample positions come in as bytes in thread payload. So, read
1263 * the positions using vstride=16, width=8, hstride=2.
1265 struct brw_reg sample_pos_reg
=
1266 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1267 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1269 emit(MOV(int_sample_x
, fs_reg(sample_pos_reg
)));
1270 if (dispatch_width
== 16) {
1271 fs_inst
*inst
= emit(MOV(half(int_sample_x
, 1),
1272 fs_reg(suboffset(sample_pos_reg
, 16))));
1273 inst
->force_sechalf
= true;
1275 /* Compute gl_SamplePosition.x */
1276 compute_sample_position(pos
, int_sample_x
);
1278 emit(MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1))));
1279 if (dispatch_width
== 16) {
1280 fs_inst
*inst
= emit(MOV(half(int_sample_y
, 1),
1281 fs_reg(suboffset(sample_pos_reg
, 17))));
1282 inst
->force_sechalf
= true;
1284 /* Compute gl_SamplePosition.y */
1285 compute_sample_position(pos
, int_sample_y
);
1290 fs_visitor::emit_sampleid_setup(ir_variable
*ir
)
1292 assert(brw
->gen
>= 6);
1294 this->current_annotation
= "compute sample id";
1295 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1297 if (key
->compute_sample_id
) {
1298 fs_reg t1
= fs_reg(this, glsl_type::int_type
);
1299 fs_reg t2
= fs_reg(this, glsl_type::int_type
);
1300 t2
.type
= BRW_REGISTER_TYPE_UW
;
1302 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1303 * 8x multisampling, subspan 0 will represent sample N (where N
1304 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1305 * 7. We can find the value of N by looking at R0.0 bits 7:6
1306 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1307 * (since samples are always delivered in pairs). That is, we
1308 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1309 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1310 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1311 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1312 * populating a temporary variable with the sequence (0, 1, 2, 3),
1313 * and then reading from it using vstride=1, width=4, hstride=0.
1314 * These computations hold good for 4x multisampling as well.
1316 emit(BRW_OPCODE_AND
, t1
,
1317 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1319 emit(BRW_OPCODE_SHR
, t1
, t1
, fs_reg(5));
1320 /* This works for both SIMD8 and SIMD16 */
1321 emit(MOV(t2
, brw_imm_v(0x3210)));
1322 /* This special instruction takes care of setting vstride=1,
1323 * width=4, hstride=0 of t2 during an ADD instruction.
1325 emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1327 /* As per GL_ARB_sample_shading specification:
1328 * "When rendering to a non-multisample buffer, or if multisample
1329 * rasterization is disabled, gl_SampleID will always be zero."
1331 emit(BRW_OPCODE_MOV
, *reg
, fs_reg(0));
1338 fs_visitor::fix_math_operand(fs_reg src
)
1340 /* Can't do hstride == 0 args on gen6 math, so expand it out. We
1341 * might be able to do better by doing execsize = 1 math and then
1342 * expanding that result out, but we would need to be careful with
1345 * The hardware ignores source modifiers (negate and abs) on math
1346 * instructions, so we also move to a temp to set those up.
1348 if (brw
->gen
== 6 && src
.file
!= UNIFORM
&& src
.file
!= IMM
&&
1349 !src
.abs
&& !src
.negate
)
1352 /* Gen7 relaxes most of the above restrictions, but still can't use IMM
1355 if (brw
->gen
>= 7 && src
.file
!= IMM
)
1358 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
1359 expanded
.type
= src
.type
;
1360 emit(BRW_OPCODE_MOV
, expanded
, src
);
1365 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src
)
1368 case SHADER_OPCODE_RCP
:
1369 case SHADER_OPCODE_RSQ
:
1370 case SHADER_OPCODE_SQRT
:
1371 case SHADER_OPCODE_EXP2
:
1372 case SHADER_OPCODE_LOG2
:
1373 case SHADER_OPCODE_SIN
:
1374 case SHADER_OPCODE_COS
:
1377 assert(!"not reached: bad math opcode");
1381 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
1382 * might be able to do better by doing execsize = 1 math and then
1383 * expanding that result out, but we would need to be careful with
1386 * Gen 6 hardware ignores source modifiers (negate and abs) on math
1387 * instructions, so we also move to a temp to set those up.
1390 src
= fix_math_operand(src
);
1392 fs_inst
*inst
= emit(opcode
, dst
, src
);
1396 inst
->mlen
= dispatch_width
/ 8;
1403 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
1409 case SHADER_OPCODE_INT_QUOTIENT
:
1410 case SHADER_OPCODE_INT_REMAINDER
:
1412 no16("SIMD16 INTDIV unsupported\n");
1414 case SHADER_OPCODE_POW
:
1417 assert(!"not reached: unsupported binary math opcode.");
1421 if (brw
->gen
>= 6) {
1422 src0
= fix_math_operand(src0
);
1423 src1
= fix_math_operand(src1
);
1425 inst
= emit(opcode
, dst
, src0
, src1
);
1427 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
1428 * "Message Payload":
1430 * "Operand0[7]. For the INT DIV functions, this operand is the
1433 * "Operand1[7]. For the INT DIV functions, this operand is the
1436 bool is_int_div
= opcode
!= SHADER_OPCODE_POW
;
1437 fs_reg
&op0
= is_int_div
? src1
: src0
;
1438 fs_reg
&op1
= is_int_div
? src0
: src1
;
1440 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1, op1
.type
), op1
);
1441 inst
= emit(opcode
, dst
, op0
, reg_null_f
);
1443 inst
->base_mrf
= base_mrf
;
1444 inst
->mlen
= 2 * dispatch_width
/ 8;
1450 fs_visitor::assign_curb_setup()
1452 if (dispatch_width
== 8) {
1453 prog_data
->first_curbe_grf
= payload
.num_regs
;
1455 prog_data
->first_curbe_grf_16
= payload
.num_regs
;
1458 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1460 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1461 foreach_list(node
, &this->instructions
) {
1462 fs_inst
*inst
= (fs_inst
*)node
;
1464 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1465 if (inst
->src
[i
].file
== UNIFORM
) {
1466 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1468 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1469 constant_nr
= push_constant_loc
[uniform_nr
];
1471 /* Section 5.11 of the OpenGL 4.1 spec says:
1472 * "Out-of-bounds reads return undefined values, which include
1473 * values from other variables of the active program or zero."
1474 * Just return the first push constant.
1479 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1483 inst
->src
[i
].file
= HW_REG
;
1484 inst
->src
[i
].fixed_hw_reg
= byte_offset(
1485 retype(brw_reg
, inst
->src
[i
].type
),
1486 inst
->src
[i
].subreg_offset
);
1493 fs_visitor::calculate_urb_setup()
1495 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1496 prog_data
->urb_setup
[i
] = -1;
1500 /* Figure out where each of the incoming setup attributes lands. */
1501 if (brw
->gen
>= 6) {
1502 if (_mesa_bitcount_64(fp
->Base
.InputsRead
&
1503 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1504 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1505 * first 16 varying inputs, so we can put them wherever we want.
1506 * Just put them in order.
1508 * This is useful because it means that (a) inputs not used by the
1509 * fragment shader won't take up valuable register space, and (b) we
1510 * won't have to recompile the fragment shader if it gets paired with
1511 * a different vertex (or geometry) shader.
1513 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1514 if (fp
->Base
.InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1515 BITFIELD64_BIT(i
)) {
1516 prog_data
->urb_setup
[i
] = urb_next
++;
1520 /* We have enough input varyings that the SF/SBE pipeline stage can't
1521 * arbitrarily rearrange them to suit our whim; we have to put them
1522 * in an order that matches the output of the previous pipeline stage
1523 * (geometry or vertex shader).
1525 struct brw_vue_map prev_stage_vue_map
;
1526 brw_compute_vue_map(brw
, &prev_stage_vue_map
,
1527 key
->input_slots_valid
);
1528 int first_slot
= 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1529 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1530 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1532 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1533 /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
1536 if (varying
!= BRW_VARYING_SLOT_COUNT
&&
1537 (fp
->Base
.InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1538 BITFIELD64_BIT(varying
))) {
1539 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1542 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1545 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1546 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1547 /* Point size is packed into the header, not as a general attribute */
1548 if (i
== VARYING_SLOT_PSIZ
)
1551 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1552 /* The back color slot is skipped when the front color is
1553 * also written to. In addition, some slots can be
1554 * written in the vertex shader and not read in the
1555 * fragment shader. So the register number must always be
1556 * incremented, mapped or not.
1558 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1559 prog_data
->urb_setup
[i
] = urb_next
;
1565 * It's a FS only attribute, and we did interpolation for this attribute
1566 * in SF thread. So, count it here, too.
1568 * See compile_sf_prog() for more info.
1570 if (fp
->Base
.InputsRead
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1571 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1574 prog_data
->num_varying_inputs
= urb_next
;
1578 fs_visitor::assign_urb_setup()
1580 int urb_start
= payload
.num_regs
+ prog_data
->curb_read_length
;
1582 /* Offset all the urb_setup[] index by the actual position of the
1583 * setup regs, now that the location of the constants has been chosen.
1585 foreach_list(node
, &this->instructions
) {
1586 fs_inst
*inst
= (fs_inst
*)node
;
1588 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1589 assert(inst
->src
[2].file
== HW_REG
);
1590 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
1593 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1594 assert(inst
->src
[0].file
== HW_REG
);
1595 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1599 /* Each attribute is 4 setup channels, each of which is half a reg. */
1600 this->first_non_payload_grf
=
1601 urb_start
+ prog_data
->num_varying_inputs
* 2;
1605 * Split large virtual GRFs into separate components if we can.
1607 * This is mostly duplicated with what brw_fs_vector_splitting does,
1608 * but that's really conservative because it's afraid of doing
1609 * splitting that doesn't result in real progress after the rest of
1610 * the optimization phases, which would cause infinite looping in
1611 * optimization. We can do it once here, safely. This also has the
1612 * opportunity to split interpolated values, or maybe even uniforms,
1613 * which we don't have at the IR level.
1615 * We want to split, because virtual GRFs are what we register
1616 * allocate and spill (due to contiguousness requirements for some
1617 * instructions), and they're what we naturally generate in the
1618 * codegen process, but most virtual GRFs don't actually need to be
1619 * contiguous sets of GRFs. If we split, we'll end up with reduced
1620 * live intervals and better dead code elimination and coalescing.
1623 fs_visitor::split_virtual_grfs()
1625 int num_vars
= this->virtual_grf_count
;
1626 bool split_grf
[num_vars
];
1627 int new_virtual_grf
[num_vars
];
1629 /* Try to split anything > 0 sized. */
1630 for (int i
= 0; i
< num_vars
; i
++) {
1631 if (this->virtual_grf_sizes
[i
] != 1)
1632 split_grf
[i
] = true;
1634 split_grf
[i
] = false;
1638 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].file
== GRF
) {
1639 /* PLN opcodes rely on the delta_xy being contiguous. We only have to
1640 * check this for BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because prior to
1641 * Gen6, that was the only supported interpolation mode, and since Gen6,
1642 * delta_x and delta_y are in fixed hardware registers.
1644 split_grf
[this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
] =
1648 foreach_list(node
, &this->instructions
) {
1649 fs_inst
*inst
= (fs_inst
*)node
;
1651 /* If there's a SEND message that requires contiguous destination
1652 * registers, no splitting is allowed.
1654 if (inst
->regs_written
> 1) {
1655 split_grf
[inst
->dst
.reg
] = false;
1658 /* If we're sending from a GRF, don't split it, on the assumption that
1659 * the send is reading the whole thing.
1661 if (inst
->is_send_from_grf()) {
1662 for (int i
= 0; i
< inst
->sources
; i
++) {
1663 if (inst
->src
[i
].file
== GRF
) {
1664 split_grf
[inst
->src
[i
].reg
] = false;
1670 /* Allocate new space for split regs. Note that the virtual
1671 * numbers will be contiguous.
1673 for (int i
= 0; i
< num_vars
; i
++) {
1675 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1676 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1677 int reg
= virtual_grf_alloc(1);
1678 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1681 this->virtual_grf_sizes
[i
] = 1;
1685 foreach_list(node
, &this->instructions
) {
1686 fs_inst
*inst
= (fs_inst
*)node
;
1688 if (inst
->dst
.file
== GRF
&&
1689 split_grf
[inst
->dst
.reg
] &&
1690 inst
->dst
.reg_offset
!= 0) {
1691 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1692 inst
->dst
.reg_offset
- 1);
1693 inst
->dst
.reg_offset
= 0;
1695 for (int i
= 0; i
< inst
->sources
; i
++) {
1696 if (inst
->src
[i
].file
== GRF
&&
1697 split_grf
[inst
->src
[i
].reg
] &&
1698 inst
->src
[i
].reg_offset
!= 0) {
1699 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1700 inst
->src
[i
].reg_offset
- 1);
1701 inst
->src
[i
].reg_offset
= 0;
1705 invalidate_live_intervals();
1709 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1711 * During code generation, we create tons of temporary variables, many of
1712 * which get immediately killed and are never used again. Yet, in later
1713 * optimization and analysis passes, such as compute_live_intervals, we need
1714 * to loop over all the virtual GRFs. Compacting them can save a lot of
1718 fs_visitor::compact_virtual_grfs()
1720 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1723 /* Mark which virtual GRFs are used, and count how many. */
1724 int remap_table
[this->virtual_grf_count
];
1725 memset(remap_table
, -1, sizeof(remap_table
));
1727 foreach_list(node
, &this->instructions
) {
1728 const fs_inst
*inst
= (const fs_inst
*) node
;
1730 if (inst
->dst
.file
== GRF
)
1731 remap_table
[inst
->dst
.reg
] = 0;
1733 for (int i
= 0; i
< inst
->sources
; i
++) {
1734 if (inst
->src
[i
].file
== GRF
)
1735 remap_table
[inst
->src
[i
].reg
] = 0;
1739 /* Compact the GRF arrays. */
1741 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
1742 if (remap_table
[i
] != -1) {
1743 remap_table
[i
] = new_index
;
1744 virtual_grf_sizes
[new_index
] = virtual_grf_sizes
[i
];
1745 invalidate_live_intervals();
1750 this->virtual_grf_count
= new_index
;
1752 /* Patch all the instructions to use the newly renumbered registers */
1753 foreach_list(node
, &this->instructions
) {
1754 fs_inst
*inst
= (fs_inst
*) node
;
1756 if (inst
->dst
.file
== GRF
)
1757 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
1759 for (int i
= 0; i
< inst
->sources
; i
++) {
1760 if (inst
->src
[i
].file
== GRF
)
1761 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
1767 * Implements array access of uniforms by inserting a
1768 * PULL_CONSTANT_LOAD instruction.
1770 * Unlike temporary GRF array access (where we don't support it due to
1771 * the difficulty of doing relative addressing on instruction
1772 * destinations), we could potentially do array access of uniforms
1773 * that were loaded in GRF space as push constants. In real-world
1774 * usage we've seen, though, the arrays being used are always larger
1775 * than we could load as push constants, so just always move all
1776 * uniform array access out to a pull constant buffer.
1779 fs_visitor::move_uniform_array_access_to_pull_constants()
1781 if (dispatch_width
!= 8)
1784 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1786 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1787 pull_constant_loc
[i
] = -1;
1790 /* Walk through and find array access of uniforms. Put a copy of that
1791 * uniform in the pull constant buffer.
1793 * Note that we don't move constant-indexed accesses to arrays. No
1794 * testing has been done of the performance impact of this choice.
1796 foreach_list_safe(node
, &this->instructions
) {
1797 fs_inst
*inst
= (fs_inst
*)node
;
1799 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1800 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
1803 int uniform
= inst
->src
[i
].reg
;
1805 /* If this array isn't already present in the pull constant buffer,
1808 if (pull_constant_loc
[uniform
] == -1) {
1809 const float **values
= &stage_prog_data
->param
[uniform
];
1811 assert(param_size
[uniform
]);
1813 for (int j
= 0; j
< param_size
[uniform
]; j
++) {
1814 pull_constant_loc
[uniform
+ j
] = stage_prog_data
->nr_pull_params
;
1816 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
1825 * Assign UNIFORM file registers to either push constants or pull constants.
1827 * We allow a fragment shader to have more than the specified minimum
1828 * maximum number of fragment shader uniform components (64). If
1829 * there are too many of these, they'd fill up all of register space.
1830 * So, this will push some of them out to the pull constant buffer and
1831 * update the program to load them.
1834 fs_visitor::assign_constant_locations()
1836 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1837 if (dispatch_width
!= 8)
1840 /* Find which UNIFORM registers are still in use. */
1841 bool is_live
[uniforms
];
1842 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1846 foreach_list(node
, &this->instructions
) {
1847 fs_inst
*inst
= (fs_inst
*) node
;
1849 for (int i
= 0; i
< inst
->sources
; i
++) {
1850 if (inst
->src
[i
].file
!= UNIFORM
)
1853 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1854 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1855 is_live
[constant_nr
] = true;
1859 /* Only allow 16 registers (128 uniform components) as push constants.
1861 * Just demote the end of the list. We could probably do better
1862 * here, demoting things that are rarely used in the program first.
1864 unsigned int max_push_components
= 16 * 8;
1865 unsigned int num_push_constants
= 0;
1867 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1869 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1870 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1871 /* This UNIFORM register is either dead, or has already been demoted
1872 * to a pull const. Mark it as no longer living in the param[] array.
1874 push_constant_loc
[i
] = -1;
1878 if (num_push_constants
< max_push_components
) {
1879 /* Retain as a push constant. Record the location in the params[]
1882 push_constant_loc
[i
] = num_push_constants
++;
1884 /* Demote to a pull constant. */
1885 push_constant_loc
[i
] = -1;
1887 int pull_index
= stage_prog_data
->nr_pull_params
++;
1888 stage_prog_data
->pull_param
[pull_index
] = stage_prog_data
->param
[i
];
1889 pull_constant_loc
[i
] = pull_index
;
1893 stage_prog_data
->nr_params
= num_push_constants
;
1895 /* Up until now, the param[] array has been indexed by reg + reg_offset
1896 * of UNIFORM registers. Condense it to only contain the uniforms we
1897 * chose to upload as push constants.
1899 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1900 int remapped
= push_constant_loc
[i
];
1905 assert(remapped
<= (int)i
);
1906 stage_prog_data
->param
[remapped
] = stage_prog_data
->param
[i
];
1911 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
1912 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
1915 fs_visitor::demote_pull_constants()
1917 foreach_list(node
, &this->instructions
) {
1918 fs_inst
*inst
= (fs_inst
*)node
;
1920 for (int i
= 0; i
< inst
->sources
; i
++) {
1921 if (inst
->src
[i
].file
!= UNIFORM
)
1924 int pull_index
= pull_constant_loc
[inst
->src
[i
].reg
+
1925 inst
->src
[i
].reg_offset
];
1926 if (pull_index
== -1)
1929 /* Set up the annotation tracking for new generated instructions. */
1931 current_annotation
= inst
->annotation
;
1933 fs_reg
surf_index(stage_prog_data
->binding_table
.pull_constants_start
);
1934 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
1936 /* Generate a pull load into dst. */
1937 if (inst
->src
[i
].reladdr
) {
1938 exec_list list
= VARYING_PULL_CONSTANT_LOAD(dst
,
1940 *inst
->src
[i
].reladdr
,
1942 inst
->insert_before(&list
);
1943 inst
->src
[i
].reladdr
= NULL
;
1945 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
1947 new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
1948 dst
, surf_index
, offset
);
1949 inst
->insert_before(pull
);
1950 inst
->src
[i
].set_smear(pull_index
& 3);
1953 /* Rewrite the instruction to use the temporary VGRF. */
1954 inst
->src
[i
].file
= GRF
;
1955 inst
->src
[i
].reg
= dst
.reg
;
1956 inst
->src
[i
].reg_offset
= 0;
1959 invalidate_live_intervals();
1963 fs_visitor::opt_algebraic()
1965 bool progress
= false;
1967 foreach_list(node
, &this->instructions
) {
1968 fs_inst
*inst
= (fs_inst
*)node
;
1970 switch (inst
->opcode
) {
1971 case BRW_OPCODE_MUL
:
1972 if (inst
->src
[1].file
!= IMM
)
1976 if (inst
->src
[1].is_one()) {
1977 inst
->opcode
= BRW_OPCODE_MOV
;
1978 inst
->src
[1] = reg_undef
;
1984 if (inst
->src
[1].is_zero()) {
1985 inst
->opcode
= BRW_OPCODE_MOV
;
1986 inst
->src
[0] = inst
->src
[1];
1987 inst
->src
[1] = reg_undef
;
1993 case BRW_OPCODE_ADD
:
1994 if (inst
->src
[1].file
!= IMM
)
1998 if (inst
->src
[1].is_zero()) {
1999 inst
->opcode
= BRW_OPCODE_MOV
;
2000 inst
->src
[1] = reg_undef
;
2006 if (inst
->src
[0].equals(inst
->src
[1])) {
2007 inst
->opcode
= BRW_OPCODE_MOV
;
2008 inst
->src
[1] = reg_undef
;
2013 case BRW_OPCODE_LRP
:
2014 if (inst
->src
[1].equals(inst
->src
[2])) {
2015 inst
->opcode
= BRW_OPCODE_MOV
;
2016 inst
->src
[0] = inst
->src
[1];
2017 inst
->src
[1] = reg_undef
;
2018 inst
->src
[2] = reg_undef
;
2023 case BRW_OPCODE_SEL
:
2024 if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2025 switch (inst
->conditional_mod
) {
2026 case BRW_CONDITIONAL_LE
:
2027 case BRW_CONDITIONAL_L
:
2028 switch (inst
->src
[1].type
) {
2029 case BRW_REGISTER_TYPE_F
:
2030 if (inst
->src
[1].imm
.f
>= 1.0f
) {
2031 inst
->opcode
= BRW_OPCODE_MOV
;
2032 inst
->src
[1] = reg_undef
;
2040 case BRW_CONDITIONAL_GE
:
2041 case BRW_CONDITIONAL_G
:
2042 switch (inst
->src
[1].type
) {
2043 case BRW_REGISTER_TYPE_F
:
2044 if (inst
->src
[1].imm
.f
<= 0.0f
) {
2045 inst
->opcode
= BRW_OPCODE_MOV
;
2046 inst
->src
[1] = reg_undef
;
2047 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2068 fs_visitor::compute_to_mrf()
2070 bool progress
= false;
2073 calculate_live_intervals();
2075 foreach_list_safe(node
, &this->instructions
) {
2076 fs_inst
*inst
= (fs_inst
*)node
;
2081 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2082 inst
->is_partial_write() ||
2083 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2084 inst
->dst
.type
!= inst
->src
[0].type
||
2085 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2086 !inst
->src
[0].is_contiguous() ||
2087 inst
->src
[0].subreg_offset
)
2090 /* Work out which hardware MRF registers are written by this
2093 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2095 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2096 mrf_high
= mrf_low
+ 4;
2097 } else if (dispatch_width
== 16 &&
2098 (!inst
->force_uncompressed
&& !inst
->force_sechalf
)) {
2099 mrf_high
= mrf_low
+ 1;
2104 /* Can't compute-to-MRF this GRF if someone else was going to
2107 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2110 /* Found a move of a GRF to a MRF. Let's see if we can go
2111 * rewrite the thing that made this GRF to write into the MRF.
2114 for (scan_inst
= (fs_inst
*)inst
->prev
;
2115 scan_inst
->prev
!= NULL
;
2116 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2117 if (scan_inst
->dst
.file
== GRF
&&
2118 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2119 /* Found the last thing to write our reg we want to turn
2120 * into a compute-to-MRF.
2123 /* If this one instruction didn't populate all the
2124 * channels, bail. We might be able to rewrite everything
2125 * that writes that reg, but it would require smarter
2126 * tracking to delay the rewriting until complete success.
2128 if (scan_inst
->is_partial_write())
2131 /* Things returning more than one register would need us to
2132 * understand coalescing out more than one MOV at a time.
2134 if (scan_inst
->regs_written
> 1)
2137 /* SEND instructions can't have MRF as a destination. */
2138 if (scan_inst
->mlen
)
2141 if (brw
->gen
== 6) {
2142 /* gen6 math instructions must have the destination be
2143 * GRF, so no compute-to-MRF for them.
2145 if (scan_inst
->is_math()) {
2150 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2151 /* Found the creator of our MRF's source value. */
2152 scan_inst
->dst
.file
= MRF
;
2153 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2154 scan_inst
->saturate
|= inst
->saturate
;
2161 /* We don't handle control flow here. Most computation of
2162 * values that end up in MRFs are shortly before the MRF
2165 if (scan_inst
->is_control_flow() && scan_inst
->opcode
!= BRW_OPCODE_IF
)
2168 /* You can't read from an MRF, so if someone else reads our
2169 * MRF's source GRF that we wanted to rewrite, that stops us.
2171 bool interfered
= false;
2172 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2173 if (scan_inst
->src
[i
].file
== GRF
&&
2174 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2175 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2182 if (scan_inst
->dst
.file
== MRF
) {
2183 /* If somebody else writes our MRF here, we can't
2184 * compute-to-MRF before that.
2186 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2189 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2190 scan_mrf_high
= scan_mrf_low
+ 4;
2191 } else if (dispatch_width
== 16 &&
2192 (!scan_inst
->force_uncompressed
&&
2193 !scan_inst
->force_sechalf
)) {
2194 scan_mrf_high
= scan_mrf_low
+ 1;
2196 scan_mrf_high
= scan_mrf_low
;
2199 if (mrf_low
== scan_mrf_low
||
2200 mrf_low
== scan_mrf_high
||
2201 mrf_high
== scan_mrf_low
||
2202 mrf_high
== scan_mrf_high
) {
2207 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2208 /* Found a SEND instruction, which means that there are
2209 * live values in MRFs from base_mrf to base_mrf +
2210 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2213 if (mrf_low
>= scan_inst
->base_mrf
&&
2214 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2217 if (mrf_high
>= scan_inst
->base_mrf
&&
2218 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2226 invalidate_live_intervals();
2232 * Walks through basic blocks, looking for repeated MRF writes and
2233 * removing the later ones.
2236 fs_visitor::remove_duplicate_mrf_writes()
2238 fs_inst
*last_mrf_move
[16];
2239 bool progress
= false;
2241 /* Need to update the MRF tracking for compressed instructions. */
2242 if (dispatch_width
== 16)
2245 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2247 foreach_list_safe(node
, &this->instructions
) {
2248 fs_inst
*inst
= (fs_inst
*)node
;
2250 if (inst
->is_control_flow()) {
2251 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2254 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2255 inst
->dst
.file
== MRF
) {
2256 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2257 if (prev_inst
&& inst
->equals(prev_inst
)) {
2264 /* Clear out the last-write records for MRFs that were overwritten. */
2265 if (inst
->dst
.file
== MRF
) {
2266 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2269 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2270 /* Found a SEND instruction, which will include two or fewer
2271 * implied MRF writes. We could do better here.
2273 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2274 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2278 /* Clear out any MRF move records whose sources got overwritten. */
2279 if (inst
->dst
.file
== GRF
) {
2280 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
2281 if (last_mrf_move
[i
] &&
2282 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2283 last_mrf_move
[i
] = NULL
;
2288 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2289 inst
->dst
.file
== MRF
&&
2290 inst
->src
[0].file
== GRF
&&
2291 !inst
->is_partial_write()) {
2292 last_mrf_move
[inst
->dst
.reg
] = inst
;
2297 invalidate_live_intervals();
2303 clear_deps_for_inst_src(fs_inst
*inst
, int dispatch_width
, bool *deps
,
2304 int first_grf
, int grf_len
)
2306 bool inst_simd16
= (dispatch_width
> 8 &&
2307 !inst
->force_uncompressed
&&
2308 !inst
->force_sechalf
);
2310 /* Clear the flag for registers that actually got read (as expected). */
2311 for (int i
= 0; i
< inst
->sources
; i
++) {
2313 if (inst
->src
[i
].file
== GRF
) {
2314 grf
= inst
->src
[i
].reg
;
2315 } else if (inst
->src
[i
].file
== HW_REG
&&
2316 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
2317 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
2322 if (grf
>= first_grf
&&
2323 grf
< first_grf
+ grf_len
) {
2324 deps
[grf
- first_grf
] = false;
2326 deps
[grf
- first_grf
+ 1] = false;
2332 * Implements this workaround for the original 965:
2334 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2335 * check for post destination dependencies on this instruction, software
2336 * must ensure that there is no destination hazard for the case of ‘write
2337 * followed by a posted write’ shown in the following example.
2340 * 2. send r3.xy <rest of send instruction>
2343 * Due to no post-destination dependency check on the ‘send’, the above
2344 * code sequence could have two instructions (1 and 2) in flight at the
2345 * same time that both consider ‘r3’ as the target of their final writes.
2348 fs_visitor::insert_gen4_pre_send_dependency_workarounds(fs_inst
*inst
)
2350 int reg_size
= dispatch_width
/ 8;
2351 int write_len
= inst
->regs_written
* reg_size
;
2352 int first_write_grf
= inst
->dst
.reg
;
2353 bool needs_dep
[BRW_MAX_MRF
];
2354 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2356 memset(needs_dep
, false, sizeof(needs_dep
));
2357 memset(needs_dep
, true, write_len
);
2359 clear_deps_for_inst_src(inst
, dispatch_width
,
2360 needs_dep
, first_write_grf
, write_len
);
2362 /* Walk backwards looking for writes to registers we're writing which
2363 * aren't read since being written. If we hit the start of the program,
2364 * we assume that there are no outstanding dependencies on entry to the
2367 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->prev
;
2368 !scan_inst
->is_head_sentinel();
2369 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2371 /* If we hit control flow, assume that there *are* outstanding
2372 * dependencies, and force their cleanup before our instruction.
2374 if (scan_inst
->is_control_flow()) {
2375 for (int i
= 0; i
< write_len
; i
++) {
2377 inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2383 bool scan_inst_simd16
= (dispatch_width
> 8 &&
2384 !scan_inst
->force_uncompressed
&&
2385 !scan_inst
->force_sechalf
);
2387 /* We insert our reads as late as possible on the assumption that any
2388 * instruction but a MOV that might have left us an outstanding
2389 * dependency has more latency than a MOV.
2391 if (scan_inst
->dst
.file
== GRF
) {
2392 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2393 int reg
= scan_inst
->dst
.reg
+ i
* reg_size
;
2395 if (reg
>= first_write_grf
&&
2396 reg
< first_write_grf
+ write_len
&&
2397 needs_dep
[reg
- first_write_grf
]) {
2398 inst
->insert_before(DEP_RESOLVE_MOV(reg
));
2399 needs_dep
[reg
- first_write_grf
] = false;
2400 if (scan_inst_simd16
)
2401 needs_dep
[reg
- first_write_grf
+ 1] = false;
2406 /* Clear the flag for registers that actually got read (as expected). */
2407 clear_deps_for_inst_src(scan_inst
, dispatch_width
,
2408 needs_dep
, first_write_grf
, write_len
);
2410 /* Continue the loop only if we haven't resolved all the dependencies */
2412 for (i
= 0; i
< write_len
; i
++) {
2422 * Implements this workaround for the original 965:
2424 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2425 * used as a destination register until after it has been sourced by an
2426 * instruction with a different destination register.
2429 fs_visitor::insert_gen4_post_send_dependency_workarounds(fs_inst
*inst
)
2431 int write_len
= inst
->regs_written
* dispatch_width
/ 8;
2432 int first_write_grf
= inst
->dst
.reg
;
2433 bool needs_dep
[BRW_MAX_MRF
];
2434 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2436 memset(needs_dep
, false, sizeof(needs_dep
));
2437 memset(needs_dep
, true, write_len
);
2438 /* Walk forwards looking for writes to registers we're writing which aren't
2439 * read before being written.
2441 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->next
;
2442 !scan_inst
->is_tail_sentinel();
2443 scan_inst
= (fs_inst
*)scan_inst
->next
) {
2444 /* If we hit control flow, force resolve all remaining dependencies. */
2445 if (scan_inst
->is_control_flow()) {
2446 for (int i
= 0; i
< write_len
; i
++) {
2448 scan_inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2453 /* Clear the flag for registers that actually got read (as expected). */
2454 clear_deps_for_inst_src(scan_inst
, dispatch_width
,
2455 needs_dep
, first_write_grf
, write_len
);
2457 /* We insert our reads as late as possible since they're reading the
2458 * result of a SEND, which has massive latency.
2460 if (scan_inst
->dst
.file
== GRF
&&
2461 scan_inst
->dst
.reg
>= first_write_grf
&&
2462 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
2463 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
2464 scan_inst
->insert_before(DEP_RESOLVE_MOV(scan_inst
->dst
.reg
));
2465 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
2468 /* Continue the loop only if we haven't resolved all the dependencies */
2470 for (i
= 0; i
< write_len
; i
++) {
2478 /* If we hit the end of the program, resolve all remaining dependencies out
2481 fs_inst
*last_inst
= (fs_inst
*)this->instructions
.get_tail();
2482 assert(last_inst
->eot
);
2483 for (int i
= 0; i
< write_len
; i
++) {
2485 last_inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2490 fs_visitor::insert_gen4_send_dependency_workarounds()
2492 if (brw
->gen
!= 4 || brw
->is_g4x
)
2495 bool progress
= false;
2497 /* Note that we're done with register allocation, so GRF fs_regs always
2498 * have a .reg_offset of 0.
2501 foreach_list_safe(node
, &this->instructions
) {
2502 fs_inst
*inst
= (fs_inst
*)node
;
2504 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
2505 insert_gen4_pre_send_dependency_workarounds(inst
);
2506 insert_gen4_post_send_dependency_workarounds(inst
);
2512 invalidate_live_intervals();
2516 * Turns the generic expression-style uniform pull constant load instruction
2517 * into a hardware-specific series of instructions for loading a pull
2520 * The expression style allows the CSE pass before this to optimize out
2521 * repeated loads from the same offset, and gives the pre-register-allocation
2522 * scheduling full flexibility, while the conversion to native instructions
2523 * allows the post-register-allocation scheduler the best information
2526 * Note that execution masking for setting up pull constant loads is special:
2527 * the channels that need to be written are unrelated to the current execution
2528 * mask, since a later instruction will use one of the result channels as a
2529 * source operand for all 8 or 16 of its channels.
2532 fs_visitor::lower_uniform_pull_constant_loads()
2534 foreach_list(node
, &this->instructions
) {
2535 fs_inst
*inst
= (fs_inst
*)node
;
2537 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
2540 if (brw
->gen
>= 7) {
2541 /* The offset arg before was a vec4-aligned byte offset. We need to
2542 * turn it into a dword offset.
2544 fs_reg const_offset_reg
= inst
->src
[1];
2545 assert(const_offset_reg
.file
== IMM
&&
2546 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
2547 const_offset_reg
.imm
.u
/= 4;
2548 fs_reg payload
= fs_reg(this, glsl_type::uint_type
);
2550 /* This is actually going to be a MOV, but since only the first dword
2551 * is accessed, we have a special opcode to do just that one. Note
2552 * that this needs to be an operation that will be considered a def
2553 * by live variable analysis, or register allocation will explode.
2555 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
2556 payload
, const_offset_reg
);
2557 setup
->force_writemask_all
= true;
2559 setup
->ir
= inst
->ir
;
2560 setup
->annotation
= inst
->annotation
;
2561 inst
->insert_before(setup
);
2563 /* Similarly, this will only populate the first 4 channels of the
2564 * result register (since we only use smear values from 0-3), but we
2565 * don't tell the optimizer.
2567 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
2568 inst
->src
[1] = payload
;
2570 invalidate_live_intervals();
2572 /* Before register allocation, we didn't tell the scheduler about the
2573 * MRF we use. We know it's safe to use this MRF because nothing
2574 * else does except for register spill/unspill, which generates and
2575 * uses its MRF within a single IR instruction.
2577 inst
->base_mrf
= 14;
2584 fs_visitor::dump_instructions()
2586 dump_instructions(NULL
);
2590 fs_visitor::dump_instructions(const char *name
)
2592 calculate_register_pressure();
2593 FILE *file
= stderr
;
2594 if (name
&& geteuid() != 0) {
2595 file
= fopen(name
, "w");
2600 int ip
= 0, max_pressure
= 0;
2601 foreach_list(node
, &this->instructions
) {
2602 backend_instruction
*inst
= (backend_instruction
*)node
;
2603 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
2604 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
2605 dump_instruction(inst
, file
);
2608 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
2610 if (file
!= stderr
) {
2616 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
2618 dump_instruction(be_inst
, stderr
);
2622 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
2624 fs_inst
*inst
= (fs_inst
*)be_inst
;
2626 if (inst
->predicate
) {
2627 fprintf(file
, "(%cf0.%d) ",
2628 inst
->predicate_inverse
? '-' : '+',
2632 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
2634 fprintf(file
, ".sat");
2635 if (inst
->conditional_mod
) {
2636 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
2637 if (!inst
->predicate
&&
2638 (brw
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
2639 inst
->opcode
!= BRW_OPCODE_IF
&&
2640 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
2641 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
2647 switch (inst
->dst
.file
) {
2649 fprintf(file
, "vgrf%d", inst
->dst
.reg
);
2650 if (virtual_grf_sizes
[inst
->dst
.reg
] != 1 ||
2651 inst
->dst
.subreg_offset
)
2652 fprintf(file
, "+%d.%d",
2653 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
2656 fprintf(file
, "m%d", inst
->dst
.reg
);
2659 fprintf(file
, "(null)");
2662 fprintf(file
, "***u%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
2665 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
2666 switch (inst
->dst
.fixed_hw_reg
.nr
) {
2668 fprintf(file
, "null");
2670 case BRW_ARF_ADDRESS
:
2671 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
2673 case BRW_ARF_ACCUMULATOR
:
2674 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
2677 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
2678 inst
->dst
.fixed_hw_reg
.subnr
);
2681 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
2682 inst
->dst
.fixed_hw_reg
.subnr
);
2686 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
2688 if (inst
->dst
.fixed_hw_reg
.subnr
)
2689 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
2692 fprintf(file
, "???");
2695 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
2697 for (int i
= 0; i
< inst
->sources
&& inst
->src
[i
].file
!= BAD_FILE
; i
++) {
2698 if (inst
->src
[i
].negate
)
2700 if (inst
->src
[i
].abs
)
2702 switch (inst
->src
[i
].file
) {
2704 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
2705 if (virtual_grf_sizes
[inst
->src
[i
].reg
] != 1 ||
2706 inst
->src
[i
].subreg_offset
)
2707 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
2708 inst
->src
[i
].subreg_offset
);
2711 fprintf(file
, "***m%d***", inst
->src
[i
].reg
);
2714 fprintf(file
, "u%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
2715 if (inst
->src
[i
].reladdr
) {
2716 fprintf(file
, "+reladdr");
2717 } else if (virtual_grf_sizes
[inst
->src
[i
].reg
] != 1 ||
2718 inst
->src
[i
].subreg_offset
) {
2719 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
2720 inst
->src
[i
].subreg_offset
);
2724 fprintf(file
, "(null)");
2727 switch (inst
->src
[i
].type
) {
2728 case BRW_REGISTER_TYPE_F
:
2729 fprintf(file
, "%ff", inst
->src
[i
].imm
.f
);
2731 case BRW_REGISTER_TYPE_D
:
2732 fprintf(file
, "%dd", inst
->src
[i
].imm
.i
);
2734 case BRW_REGISTER_TYPE_UD
:
2735 fprintf(file
, "%uu", inst
->src
[i
].imm
.u
);
2738 fprintf(file
, "???");
2743 if (inst
->src
[i
].fixed_hw_reg
.negate
)
2745 if (inst
->src
[i
].fixed_hw_reg
.abs
)
2747 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
2748 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
2750 fprintf(file
, "null");
2752 case BRW_ARF_ADDRESS
:
2753 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
2755 case BRW_ARF_ACCUMULATOR
:
2756 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
2759 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
2760 inst
->src
[i
].fixed_hw_reg
.subnr
);
2763 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
2764 inst
->src
[i
].fixed_hw_reg
.subnr
);
2768 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
2770 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
2771 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
2772 if (inst
->src
[i
].fixed_hw_reg
.abs
)
2776 fprintf(file
, "???");
2779 if (inst
->src
[i
].abs
)
2782 if (inst
->src
[i
].file
!= IMM
) {
2783 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
2786 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
2787 fprintf(file
, ", ");
2792 if (inst
->force_uncompressed
)
2793 fprintf(file
, "1sthalf ");
2795 if (inst
->force_sechalf
)
2796 fprintf(file
, "2ndhalf ");
2798 fprintf(file
, "\n");
2802 * Possibly returns an instruction that set up @param reg.
2804 * Sometimes we want to take the result of some expression/variable
2805 * dereference tree and rewrite the instruction generating the result
2806 * of the tree. When processing the tree, we know that the
2807 * instructions generated are all writing temporaries that are dead
2808 * outside of this tree. So, if we have some instructions that write
2809 * a temporary, we're free to point that temp write somewhere else.
2811 * Note that this doesn't guarantee that the instruction generated
2812 * only reg -- it might be the size=4 destination of a texture instruction.
2815 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
2820 end
->is_partial_write() ||
2822 !reg
.equals(end
->dst
)) {
2830 fs_visitor::setup_payload_gen6()
2833 (fp
->Base
.InputsRead
& (1 << VARYING_SLOT_POS
)) != 0;
2834 unsigned barycentric_interp_modes
= prog_data
->barycentric_interp_modes
;
2836 assert(brw
->gen
>= 6);
2838 /* R0-1: masks, pixel X/Y coordinates. */
2839 payload
.num_regs
= 2;
2840 /* R2: only for 32-pixel dispatch.*/
2842 /* R3-26: barycentric interpolation coordinates. These appear in the
2843 * same order that they appear in the brw_wm_barycentric_interp_mode
2844 * enum. Each set of coordinates occupies 2 registers if dispatch width
2845 * == 8 and 4 registers if dispatch width == 16. Coordinates only
2846 * appear if they were enabled using the "Barycentric Interpolation
2847 * Mode" bits in WM_STATE.
2849 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
2850 if (barycentric_interp_modes
& (1 << i
)) {
2851 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
2852 payload
.num_regs
+= 2;
2853 if (dispatch_width
== 16) {
2854 payload
.num_regs
+= 2;
2859 /* R27: interpolated depth if uses source depth */
2861 payload
.source_depth_reg
= payload
.num_regs
;
2863 if (dispatch_width
== 16) {
2864 /* R28: interpolated depth if not SIMD8. */
2868 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
2870 payload
.source_w_reg
= payload
.num_regs
;
2872 if (dispatch_width
== 16) {
2873 /* R30: interpolated W if not SIMD8. */
2878 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
2879 /* R31: MSAA position offsets. */
2880 if (prog_data
->uses_pos_offset
) {
2881 payload
.sample_pos_reg
= payload
.num_regs
;
2885 /* R32: MSAA input coverage mask */
2886 if (fp
->Base
.SystemValuesRead
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
2887 assert(brw
->gen
>= 7);
2888 payload
.sample_mask_in_reg
= payload
.num_regs
;
2890 if (dispatch_width
== 16) {
2891 /* R33: input coverage mask if not SIMD8. */
2896 /* R34-: bary for 32-pixel. */
2897 /* R58-59: interp W for 32-pixel. */
2899 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
2900 source_depth_to_render_target
= true;
2905 fs_visitor::assign_binding_table_offsets()
2907 uint32_t next_binding_table_offset
= 0;
2909 /* If there are no color regions, we still perform an FB write to a null
2910 * renderbuffer, which we place at surface index 0.
2912 prog_data
->binding_table
.render_target_start
= next_binding_table_offset
;
2913 next_binding_table_offset
+= MAX2(key
->nr_color_regions
, 1);
2915 assign_common_binding_table_offsets(next_binding_table_offset
);
2919 fs_visitor::calculate_register_pressure()
2921 invalidate_live_intervals();
2922 calculate_live_intervals();
2924 int num_instructions
= 0;
2925 foreach_list(node
, &this->instructions
) {
2929 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
2931 for (int reg
= 0; reg
< virtual_grf_count
; reg
++) {
2932 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
2933 regs_live_at_ip
[ip
] += virtual_grf_sizes
[reg
];
2938 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
2940 * The needs_unlit_centroid_workaround ends up producing one of these per
2941 * channel of centroid input, so it's good to clean them up.
2943 * An assumption here is that nothing ever modifies the dispatched pixels
2944 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
2945 * dictates that anyway.
2948 fs_visitor::opt_drop_redundant_mov_to_flags()
2950 bool flag_mov_found
[2] = {false};
2952 foreach_list_safe(node
, &this->instructions
) {
2953 fs_inst
*inst
= (fs_inst
*)node
;
2955 if (inst
->is_control_flow()) {
2956 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
2957 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
2958 if (!flag_mov_found
[inst
->flag_subreg
])
2959 flag_mov_found
[inst
->flag_subreg
] = true;
2962 } else if (inst
->writes_flag()) {
2963 flag_mov_found
[inst
->flag_subreg
] = false;
2971 sanity_param_count
= fp
->Base
.Parameters
->NumParameters
;
2972 bool allocated_without_spills
;
2974 assign_binding_table_offsets();
2977 setup_payload_gen6();
2979 setup_payload_gen4();
2984 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2985 emit_shader_time_begin();
2987 calculate_urb_setup();
2988 if (fp
->Base
.InputsRead
> 0) {
2990 emit_interpolation_setup_gen4();
2992 emit_interpolation_setup_gen6();
2995 /* We handle discards by keeping track of the still-live pixels in f0.1.
2996 * Initialize it with the dispatched pixels.
2998 if (fp
->UsesKill
|| key
->alpha_test_func
) {
2999 fs_inst
*discard_init
= emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
3000 discard_init
->flag_subreg
= 1;
3003 /* Generate FS IR for main(). (the visitor only descends into
3004 * functions called "main").
3007 foreach_list(node
, &*shader
->base
.ir
) {
3008 ir_instruction
*ir
= (ir_instruction
*)node
;
3010 this->result
= reg_undef
;
3014 emit_fragment_program_code();
3020 emit(FS_OPCODE_PLACEHOLDER_HALT
);
3022 if (key
->alpha_test_func
)
3027 split_virtual_grfs();
3029 move_uniform_array_access_to_pull_constants();
3030 assign_constant_locations();
3031 demote_pull_constants();
3033 opt_drop_redundant_mov_to_flags();
3035 #define OPT(pass, args...) do { \
3037 bool this_progress = pass(args); \
3039 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
3040 char filename[64]; \
3041 snprintf(filename, 64, "fs%d-%04d-%02d-%02d-" #pass, \
3042 dispatch_width, shader_prog->Name, iteration, pass_num); \
3044 backend_visitor::dump_instructions(filename); \
3047 progress = progress || this_progress; \
3050 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
3052 snprintf(filename
, 64, "fs%d-%04d-00-start",
3053 dispatch_width
, shader_prog
->Name
);
3055 backend_visitor::dump_instructions(filename
);
3065 compact_virtual_grfs();
3067 OPT(remove_duplicate_mrf_writes
);
3071 OPT(opt_copy_propagate
);
3072 OPT(opt_peephole_predicated_break
);
3073 OPT(dead_code_eliminate
);
3074 OPT(opt_peephole_sel
);
3075 OPT(dead_control_flow_eliminate
, this);
3076 OPT(opt_saturate_propagation
);
3077 OPT(register_coalesce
);
3078 OPT(compute_to_mrf
);
3081 lower_uniform_pull_constant_loads();
3083 assign_curb_setup();
3086 static enum instruction_scheduler_mode pre_modes
[] = {
3088 SCHEDULE_PRE_NON_LIFO
,
3092 /* Try each scheduling heuristic to see if it can successfully register
3093 * allocate without spilling. They should be ordered by decreasing
3094 * performance but increasing likelihood of allocating.
3096 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
3097 schedule_instructions(pre_modes
[i
]);
3100 assign_regs_trivial();
3101 allocated_without_spills
= true;
3103 allocated_without_spills
= assign_regs(false);
3105 if (allocated_without_spills
)
3109 if (!allocated_without_spills
) {
3110 /* We assume that any spilling is worse than just dropping back to
3111 * SIMD8. There's probably actually some intermediate point where
3112 * SIMD16 with a couple of spills is still better.
3114 if (dispatch_width
== 16) {
3115 fail("Failure to register allocate. Reduce number of "
3116 "live scalar values to avoid this.");
3118 perf_debug("Fragment shader triggered register spilling. "
3119 "Try reducing the number of live scalar values to "
3120 "improve performance.\n");
3123 /* Since we're out of heuristics, just go spill registers until we
3124 * get an allocation.
3126 while (!assign_regs(true)) {
3132 assert(force_uncompressed_stack
== 0);
3134 /* This must come after all optimization and register allocation, since
3135 * it inserts dead code that happens to have side effects, and it does
3136 * so based on the actual physical registers in use.
3138 insert_gen4_send_dependency_workarounds();
3143 if (!allocated_without_spills
)
3144 schedule_instructions(SCHEDULE_POST
);
3146 if (last_scratch
> 0) {
3147 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
3150 if (dispatch_width
== 8)
3151 prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
3153 prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
3155 /* If any state parameters were appended, then ParameterValues could have
3156 * been realloced, in which case the driver uniform storage set up by
3157 * _mesa_associate_uniform_storage() would point to freed memory. Make
3158 * sure that didn't happen.
3160 assert(sanity_param_count
== fp
->Base
.Parameters
->NumParameters
);
3166 brw_wm_fs_emit(struct brw_context
*brw
,
3168 const struct brw_wm_prog_key
*key
,
3169 struct brw_wm_prog_data
*prog_data
,
3170 struct gl_fragment_program
*fp
,
3171 struct gl_shader_program
*prog
,
3172 unsigned *final_assembly_size
)
3174 bool start_busy
= false;
3175 double start_time
= 0;
3177 if (unlikely(brw
->perf_debug
)) {
3178 start_busy
= (brw
->batch
.last_bo
&&
3179 drm_intel_bo_busy(brw
->batch
.last_bo
));
3180 start_time
= get_time();
3183 struct brw_shader
*shader
= NULL
;
3185 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3187 if (unlikely(INTEL_DEBUG
& DEBUG_WM
))
3188 brw_dump_ir(brw
, "fragment", prog
, &shader
->base
, &fp
->Base
);
3190 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3192 fs_visitor
v(brw
, mem_ctx
, key
, prog_data
, prog
, fp
, 8);
3195 prog
->LinkStatus
= false;
3196 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
3199 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
3205 exec_list
*simd16_instructions
= NULL
;
3206 fs_visitor
v2(brw
, mem_ctx
, key
, prog_data
, prog
, fp
, 16);
3207 if (brw
->gen
>= 5 && likely(!(INTEL_DEBUG
& DEBUG_NO16
))) {
3208 if (!v
.simd16_unsupported
) {
3209 /* Try a SIMD16 compile */
3210 v2
.import_uniforms(&v
);
3212 perf_debug("SIMD16 shader failed to compile, falling back to "
3213 "SIMD8 at a 10-20%% performance cost: %s", v2
.fail_msg
);
3215 simd16_instructions
= &v2
.instructions
;
3218 perf_debug("SIMD16 shader unsupported, falling back to "
3219 "SIMD8 at a 10-20%% performance cost: %s", v
.no16_msg
);
3223 const unsigned *assembly
= NULL
;
3224 if (brw
->gen
>= 8) {
3225 gen8_fs_generator
g(brw
, mem_ctx
, key
, prog_data
, prog
, fp
, v
.do_dual_src
);
3226 assembly
= g
.generate_assembly(&v
.instructions
, simd16_instructions
,
3227 final_assembly_size
);
3229 fs_generator
g(brw
, mem_ctx
, key
, prog_data
, prog
, fp
, v
.do_dual_src
,
3230 v
.runtime_check_aads_emit
, INTEL_DEBUG
& DEBUG_WM
);
3231 assembly
= g
.generate_assembly(&v
.instructions
, simd16_instructions
,
3232 final_assembly_size
);
3235 if (unlikely(brw
->perf_debug
) && shader
) {
3236 if (shader
->compiled_once
)
3237 brw_wm_debug_recompile(brw
, prog
, key
);
3238 shader
->compiled_once
= true;
3240 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
3241 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
3242 (get_time() - start_time
) * 1000);
3250 brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
3252 struct brw_context
*brw
= brw_context(ctx
);
3253 struct brw_wm_prog_key key
;
3255 if (!prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
])
3258 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)
3259 prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
]->Program
;
3260 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
3261 bool program_uses_dfdy
= fp
->UsesDFdy
;
3263 memset(&key
, 0, sizeof(key
));
3267 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
3269 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
3270 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
3272 /* Just assume depth testing. */
3273 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
3274 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
3277 if (brw
->gen
< 6 || _mesa_bitcount_64(fp
->Base
.InputsRead
&
3278 BRW_FS_VARYING_INPUT_MASK
) > 16)
3279 key
.input_slots_valid
= fp
->Base
.InputsRead
| VARYING_BIT_POS
;
3281 unsigned sampler_count
= _mesa_fls(fp
->Base
.SamplersUsed
);
3282 for (unsigned i
= 0; i
< sampler_count
; i
++) {
3283 if (fp
->Base
.ShadowSamplers
& (1 << i
)) {
3284 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
3285 key
.tex
.swizzles
[i
] =
3286 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
3288 /* Color sampler: assume no swizzling. */
3289 key
.tex
.swizzles
[i
] = SWIZZLE_XYZW
;
3293 if (fp
->Base
.InputsRead
& VARYING_BIT_POS
) {
3294 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
3297 key
.nr_color_regions
= _mesa_bitcount_64(fp
->Base
.OutputsWritten
&
3298 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
3299 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
)));
3301 if ((fp
->Base
.InputsRead
& VARYING_BIT_POS
) || program_uses_dfdy
) {
3302 key
.render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
) ||
3303 key
.nr_color_regions
> 1;
3306 /* GL_FRAGMENT_SHADER_DERIVATIVE_HINT is almost always GL_DONT_CARE. The
3307 * quality of the derivatives is likely to be determined by the driconf
3310 key
.high_quality_derivatives
= brw
->disable_derivative_optimization
;
3312 key
.program_string_id
= bfp
->id
;
3314 uint32_t old_prog_offset
= brw
->wm
.base
.prog_offset
;
3315 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
3317 bool success
= do_wm_prog(brw
, prog
, bfp
, &key
);
3319 brw
->wm
.base
.prog_offset
= old_prog_offset
;
3320 brw
->wm
.prog_data
= old_prog_data
;