2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
32 #include "brw_context.h"
37 #include "brw_vec4_gs_visitor.h"
39 #include "brw_program.h"
40 #include "brw_dead_control_flow.h"
41 #include "compiler/glsl_types.h"
42 #include "compiler/nir/nir_builder.h"
43 #include "program/prog_parameter.h"
47 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
51 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
52 const fs_reg
*src
, unsigned sources
)
54 memset(this, 0, sizeof(*this));
56 this->src
= new fs_reg
[MAX2(sources
, 3)];
57 for (unsigned i
= 0; i
< sources
; i
++)
58 this->src
[i
] = src
[i
];
60 this->opcode
= opcode
;
62 this->sources
= sources
;
63 this->exec_size
= exec_size
;
66 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
68 assert(this->exec_size
!= 0);
70 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
72 /* This will be the case for almost all instructions. */
79 this->size_written
= dst
.component_size(exec_size
);
82 this->size_written
= 0;
86 unreachable("Invalid destination register file");
89 this->writes_accumulator
= false;
94 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
97 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
99 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
104 init(opcode
, exec_size
, dst
, NULL
, 0);
107 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
110 const fs_reg src
[1] = { src0
};
111 init(opcode
, exec_size
, dst
, src
, 1);
114 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
115 const fs_reg
&src0
, const fs_reg
&src1
)
117 const fs_reg src
[2] = { src0
, src1
};
118 init(opcode
, exec_size
, dst
, src
, 2);
121 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
122 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
124 const fs_reg src
[3] = { src0
, src1
, src2
};
125 init(opcode
, exec_size
, dst
, src
, 3);
128 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
129 const fs_reg src
[], unsigned sources
)
131 init(opcode
, exec_width
, dst
, src
, sources
);
134 fs_inst::fs_inst(const fs_inst
&that
)
136 memcpy(this, &that
, sizeof(that
));
138 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
140 for (unsigned i
= 0; i
< that
.sources
; i
++)
141 this->src
[i
] = that
.src
[i
];
150 fs_inst::resize_sources(uint8_t num_sources
)
152 if (this->sources
!= num_sources
) {
153 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
155 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
156 src
[i
] = this->src
[i
];
160 this->sources
= num_sources
;
165 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
167 const fs_reg
&surf_index
,
168 const fs_reg
&varying_offset
,
169 uint32_t const_offset
)
171 /* We have our constant surface use a pitch of 4 bytes, so our index can
172 * be any component of a vector, and then we load 4 contiguous
173 * components starting from that.
175 * We break down the const_offset to a portion added to the variable
176 * offset and a portion done using reg_offset, which means that if you
177 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
178 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
179 * CSE can later notice that those loads are all the same and eliminate
180 * the redundant ones.
182 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
183 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
185 /* The pull load message will load a vec4 (16 bytes). If we are loading
186 * a double this means we are only loading 2 elements worth of data.
187 * We also want to use a 32-bit data type for the dst of the load operation
188 * so other parts of the driver don't get confused about the size of the
191 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
192 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
193 vec4_result
, surf_index
, vec4_offset
);
194 inst
->size_written
= 4 * bld
.dispatch_width() / 8 * REG_SIZE
;
196 if (type_sz(dst
.type
) == 8) {
197 shuffle_32bit_load_result_to_64bit_data(
198 bld
, retype(vec4_result
, dst
.type
), vec4_result
, 2);
201 vec4_result
.type
= dst
.type
;
202 bld
.MOV(dst
, offset(vec4_result
, bld
,
203 (const_offset
& 0xf) / type_sz(vec4_result
.type
)));
207 * A helper for MOV generation for fixing up broken hardware SEND dependency
211 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
213 /* The caller always wants uncompressed to emit the minimal extra
214 * dependencies, and to avoid having to deal with aligning its regs to 2.
216 const fs_builder ubld
= bld
.annotate("send dependency resolve")
219 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
223 fs_inst::equals(fs_inst
*inst
) const
225 return (opcode
== inst
->opcode
&&
226 dst
.equals(inst
->dst
) &&
227 src
[0].equals(inst
->src
[0]) &&
228 src
[1].equals(inst
->src
[1]) &&
229 src
[2].equals(inst
->src
[2]) &&
230 saturate
== inst
->saturate
&&
231 predicate
== inst
->predicate
&&
232 conditional_mod
== inst
->conditional_mod
&&
233 mlen
== inst
->mlen
&&
234 base_mrf
== inst
->base_mrf
&&
235 target
== inst
->target
&&
237 header_size
== inst
->header_size
&&
238 shadow_compare
== inst
->shadow_compare
&&
239 exec_size
== inst
->exec_size
&&
240 offset
== inst
->offset
);
244 fs_inst::is_send_from_grf() const
247 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
248 case SHADER_OPCODE_SHADER_TIME_ADD
:
249 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
250 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
251 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
252 case SHADER_OPCODE_UNTYPED_ATOMIC
:
253 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
254 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
255 case SHADER_OPCODE_TYPED_ATOMIC
:
256 case SHADER_OPCODE_TYPED_SURFACE_READ
:
257 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
258 case SHADER_OPCODE_URB_WRITE_SIMD8
:
259 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
260 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
261 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
262 case SHADER_OPCODE_URB_READ_SIMD8
:
263 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
265 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
266 return src
[1].file
== VGRF
;
267 case FS_OPCODE_FB_WRITE
:
268 case FS_OPCODE_FB_READ
:
269 return src
[0].file
== VGRF
;
272 return src
[0].file
== VGRF
;
279 * Returns true if this instruction's sources and destinations cannot
280 * safely be the same register.
282 * In most cases, a register can be written over safely by the same
283 * instruction that is its last use. For a single instruction, the
284 * sources are dereferenced before writing of the destination starts
287 * However, there are a few cases where this can be problematic:
289 * - Virtual opcodes that translate to multiple instructions in the
290 * code generator: if src == dst and one instruction writes the
291 * destination before a later instruction reads the source, then
292 * src will have been clobbered.
294 * - SIMD16 compressed instructions with certain regioning (see below).
296 * The register allocator uses this information to set up conflicts between
297 * GRF sources and the destination.
300 fs_inst::has_source_and_destination_hazard() const
303 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
304 /* Multiple partial writes to the destination */
307 /* The SIMD16 compressed instruction
309 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
311 * is actually decoded in hardware as:
313 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
314 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
316 * Which is safe. However, if we have uniform accesses
317 * happening, we get into trouble:
319 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
320 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
322 * Now our destination for the first instruction overwrote the
323 * second instruction's src0, and we get garbage for those 8
324 * pixels. There's a similar issue for the pre-gen6
325 * pixel_x/pixel_y, which are registers of 16-bit values and thus
326 * would get stomped by the first decode as well.
328 if (exec_size
== 16) {
329 for (int i
= 0; i
< sources
; i
++) {
330 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
331 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
332 src
[i
].type
== BRW_REGISTER_TYPE_W
||
333 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
334 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
344 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
346 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
349 fs_reg reg
= this->src
[0];
350 if (reg
.file
!= VGRF
|| reg
.offset
!= 0 || reg
.stride
!= 1)
353 if (grf_alloc
.sizes
[reg
.nr
] * REG_SIZE
!= this->size_written
)
356 for (int i
= 0; i
< this->sources
; i
++) {
357 reg
.type
= this->src
[i
].type
;
358 if (!this->src
[i
].equals(reg
))
361 if (i
< this->header_size
) {
362 reg
.offset
+= REG_SIZE
;
364 reg
= horiz_offset(reg
, this->exec_size
);
372 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
)
374 if (devinfo
->gen
== 6 && is_math())
377 if (is_send_from_grf())
380 if (!backend_instruction::can_do_source_mods())
387 fs_inst::can_change_types() const
389 return dst
.type
== src
[0].type
&&
390 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
391 (opcode
== BRW_OPCODE_MOV
||
392 (opcode
== BRW_OPCODE_SEL
&&
393 dst
.type
== src
[1].type
&&
394 predicate
!= BRW_PREDICATE_NONE
&&
395 !src
[1].abs
&& !src
[1].negate
));
399 fs_inst::has_side_effects() const
401 return this->eot
|| backend_instruction::has_side_effects();
407 memset(this, 0, sizeof(*this));
411 /** Generic unset register constructor. */
415 this->file
= BAD_FILE
;
418 fs_reg::fs_reg(struct ::brw_reg reg
) :
423 if (this->file
== IMM
&&
424 (this->type
!= BRW_REGISTER_TYPE_V
&&
425 this->type
!= BRW_REGISTER_TYPE_UV
&&
426 this->type
!= BRW_REGISTER_TYPE_VF
)) {
432 fs_reg::equals(const fs_reg
&r
) const
434 return (this->backend_reg::equals(r
) &&
439 fs_reg::set_smear(unsigned subreg
)
441 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
442 offset
= ROUND_DOWN_TO(offset
, REG_SIZE
) + subreg
* type_sz(type
);
448 fs_reg::is_contiguous() const
454 fs_reg::component_size(unsigned width
) const
456 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
459 return MAX2(width
* stride
, 1) * type_sz(type
);
463 type_size_scalar(const struct glsl_type
*type
)
465 unsigned int size
, i
;
467 switch (type
->base_type
) {
470 case GLSL_TYPE_FLOAT
:
472 return type
->components();
473 case GLSL_TYPE_DOUBLE
:
474 return type
->components() * 2;
475 case GLSL_TYPE_ARRAY
:
476 return type_size_scalar(type
->fields
.array
) * type
->length
;
477 case GLSL_TYPE_STRUCT
:
479 for (i
= 0; i
< type
->length
; i
++) {
480 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
483 case GLSL_TYPE_SAMPLER
:
484 /* Samplers take up no register space, since they're baked in at
488 case GLSL_TYPE_ATOMIC_UINT
:
490 case GLSL_TYPE_SUBROUTINE
:
492 case GLSL_TYPE_IMAGE
:
493 return BRW_IMAGE_PARAM_SIZE
;
495 case GLSL_TYPE_ERROR
:
496 case GLSL_TYPE_INTERFACE
:
497 case GLSL_TYPE_FUNCTION
:
498 unreachable("not reached");
505 * Returns the number of scalar components needed to store type, assuming
506 * that vectors are padded out to vec4.
508 * This has the packing rules of type_size_vec4(), but counts components
509 * similar to type_size_scalar().
512 type_size_vec4_times_4(const struct glsl_type
*type
)
514 return 4 * type_size_vec4(type
);
517 /* Attribute arrays are loaded as one vec4 per element (or matrix column),
518 * except for double-precision types, which are loaded as one dvec4.
521 type_size_vs_input(const struct glsl_type
*type
)
523 if (type
->is_double()) {
524 return type_size_dvec4(type
);
526 return type_size_vec4(type
);
531 * Create a MOV to read the timestamp register.
533 * The caller is responsible for emitting the MOV. The return value is
534 * the destination of the MOV, with extra parameters set.
537 fs_visitor::get_timestamp(const fs_builder
&bld
)
539 assert(devinfo
->gen
>= 7);
541 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
544 BRW_REGISTER_TYPE_UD
));
546 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
548 /* We want to read the 3 fields we care about even if it's not enabled in
551 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
557 fs_visitor::emit_shader_time_begin()
559 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
561 /* We want only the low 32 bits of the timestamp. Since it's running
562 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
563 * which is plenty of time for our purposes. It is identical across the
564 * EUs, but since it's tracking GPU core speed it will increment at a
565 * varying rate as render P-states change.
567 shader_start_time
.set_smear(0);
571 fs_visitor::emit_shader_time_end()
573 /* Insert our code just before the final SEND with EOT. */
574 exec_node
*end
= this->instructions
.get_tail();
575 assert(end
&& ((fs_inst
*) end
)->eot
);
576 const fs_builder ibld
= bld
.annotate("shader time end")
577 .exec_all().at(NULL
, end
);
579 fs_reg shader_end_time
= get_timestamp(ibld
);
581 /* We only use the low 32 bits of the timestamp - see
582 * emit_shader_time_begin()).
584 * We could also check if render P-states have changed (or anything
585 * else that might disrupt timing) by setting smear to 2 and checking if
586 * that field is != 0.
588 shader_end_time
.set_smear(0);
590 /* Check that there weren't any timestamp reset events (assuming these
591 * were the only two timestamp reads that happened).
593 fs_reg reset
= shader_end_time
;
595 set_condmod(BRW_CONDITIONAL_Z
,
596 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
597 ibld
.IF(BRW_PREDICATE_NORMAL
);
599 fs_reg start
= shader_start_time
;
601 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
604 const fs_builder cbld
= ibld
.group(1, 0);
605 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
607 /* If there were no instructions between the two timestamp gets, the diff
608 * is 2 cycles. Remove that overhead, so I can forget about that when
609 * trying to determine the time taken for single instructions.
611 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
612 SHADER_TIME_ADD(cbld
, 0, diff
);
613 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
614 ibld
.emit(BRW_OPCODE_ELSE
);
615 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
616 ibld
.emit(BRW_OPCODE_ENDIF
);
620 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
621 int shader_time_subindex
,
624 int index
= shader_time_index
* 3 + shader_time_subindex
;
625 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
628 if (dispatch_width
== 8)
629 payload
= vgrf(glsl_type::uvec2_type
);
631 payload
= vgrf(glsl_type::uint_type
);
633 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
637 fs_visitor::vfail(const char *format
, va_list va
)
646 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
647 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
649 this->fail_msg
= msg
;
652 fprintf(stderr
, "%s", msg
);
657 fs_visitor::fail(const char *format
, ...)
661 va_start(va
, format
);
667 * Mark this program as impossible to compile with dispatch width greater
670 * During the SIMD8 compile (which happens first), we can detect and flag
671 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
672 * SIMD16+ compile altogether.
674 * During a compile of dispatch width greater than n (if one happens anyway),
675 * this just calls fail().
678 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
680 if (dispatch_width
> n
) {
683 max_dispatch_width
= n
;
684 compiler
->shader_perf_log(log_data
,
685 "Shader dispatch width limited to SIMD%d: %s",
691 * Returns true if the instruction has a flag that means it won't
692 * update an entire destination register.
694 * For example, dead code elimination and live variable analysis want to know
695 * when a write to a variable screens off any preceding values that were in
699 fs_inst::is_partial_write() const
701 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
702 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
703 !this->dst
.is_contiguous() ||
704 this->dst
.offset
% REG_SIZE
!= 0);
708 fs_inst::components_read(unsigned i
) const
710 /* Return zero if the source is not present. */
711 if (src
[i
].file
== BAD_FILE
)
715 case FS_OPCODE_LINTERP
:
721 case FS_OPCODE_PIXEL_X
:
722 case FS_OPCODE_PIXEL_Y
:
726 case FS_OPCODE_FB_WRITE_LOGICAL
:
727 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
728 /* First/second FB write color. */
730 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
734 case SHADER_OPCODE_TEX_LOGICAL
:
735 case SHADER_OPCODE_TXD_LOGICAL
:
736 case SHADER_OPCODE_TXF_LOGICAL
:
737 case SHADER_OPCODE_TXL_LOGICAL
:
738 case SHADER_OPCODE_TXS_LOGICAL
:
739 case FS_OPCODE_TXB_LOGICAL
:
740 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
741 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
742 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
743 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
744 case SHADER_OPCODE_LOD_LOGICAL
:
745 case SHADER_OPCODE_TG4_LOGICAL
:
746 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
747 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
748 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
749 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
750 /* Texture coordinates. */
751 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
752 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
753 /* Texture derivatives. */
754 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
755 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
756 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
757 /* Texture offset. */
758 else if (i
== TEX_LOGICAL_SRC_OFFSET_VALUE
)
761 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
766 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
767 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
768 assert(src
[3].file
== IMM
);
769 /* Surface coordinates. */
772 /* Surface operation source (ignored for reads). */
778 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
779 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
780 assert(src
[3].file
== IMM
&&
782 /* Surface coordinates. */
785 /* Surface operation source. */
791 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
792 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
793 assert(src
[3].file
== IMM
&&
795 const unsigned op
= src
[4].ud
;
796 /* Surface coordinates. */
799 /* Surface operation source. */
800 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
802 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
803 op
== BRW_AOP_PREDEC
))
815 fs_inst::size_read(int arg
) const
818 case FS_OPCODE_FB_WRITE
:
819 case FS_OPCODE_FB_READ
:
820 case SHADER_OPCODE_URB_WRITE_SIMD8
:
821 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
822 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
823 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
824 case SHADER_OPCODE_URB_READ_SIMD8
:
825 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
826 case SHADER_OPCODE_UNTYPED_ATOMIC
:
827 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
828 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
829 case SHADER_OPCODE_TYPED_ATOMIC
:
830 case SHADER_OPCODE_TYPED_SURFACE_READ
:
831 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
832 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
834 return mlen
* REG_SIZE
;
837 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
838 /* The payload is actually stored in src1 */
840 return mlen
* REG_SIZE
;
843 case FS_OPCODE_LINTERP
:
848 case SHADER_OPCODE_LOAD_PAYLOAD
:
849 if (arg
< this->header_size
)
853 case CS_OPCODE_CS_TERMINATE
:
854 case SHADER_OPCODE_BARRIER
:
857 case SHADER_OPCODE_MOV_INDIRECT
:
859 assert(src
[2].file
== IMM
);
865 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
866 return mlen
* REG_SIZE
;
870 switch (src
[arg
].file
) {
873 return components_read(arg
) * type_sz(src
[arg
].type
);
879 return components_read(arg
) * src
[arg
].component_size(exec_size
);
881 unreachable("MRF registers are not allowed as sources");
887 /* Return the subset of flag registers that an instruction could
888 * potentially read or write based on the execution controls and flag
889 * subregister number of the instruction.
892 flag_mask(const fs_inst
*inst
)
894 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
895 const unsigned end
= start
+ inst
->exec_size
;
896 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
901 fs_inst::flags_read(const gen_device_info
*devinfo
) const
903 /* XXX - This doesn't consider explicit uses of the flag register as source
906 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
907 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
908 /* The vertical predication modes combine corresponding bits from
909 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
911 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
912 return flag_mask(this) << shift
| flag_mask(this);
913 } else if (predicate
) {
914 return flag_mask(this);
921 fs_inst::flags_written() const
923 /* XXX - This doesn't consider explicit uses of the flag register as
924 * destination region.
926 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
927 opcode
!= BRW_OPCODE_IF
&&
928 opcode
!= BRW_OPCODE_WHILE
)) ||
929 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
930 return flag_mask(this);
937 * Returns how many MRFs an FS opcode will write over.
939 * Note that this is not the 0 or 1 implied writes in an actual gen
940 * instruction -- the FS opcodes often generate MOVs in addition.
943 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
948 if (inst
->base_mrf
== -1)
951 switch (inst
->opcode
) {
952 case SHADER_OPCODE_RCP
:
953 case SHADER_OPCODE_RSQ
:
954 case SHADER_OPCODE_SQRT
:
955 case SHADER_OPCODE_EXP2
:
956 case SHADER_OPCODE_LOG2
:
957 case SHADER_OPCODE_SIN
:
958 case SHADER_OPCODE_COS
:
959 return 1 * dispatch_width
/ 8;
960 case SHADER_OPCODE_POW
:
961 case SHADER_OPCODE_INT_QUOTIENT
:
962 case SHADER_OPCODE_INT_REMAINDER
:
963 return 2 * dispatch_width
/ 8;
964 case SHADER_OPCODE_TEX
:
966 case SHADER_OPCODE_TXD
:
967 case SHADER_OPCODE_TXF
:
968 case SHADER_OPCODE_TXF_CMS
:
969 case SHADER_OPCODE_TXF_MCS
:
970 case SHADER_OPCODE_TG4
:
971 case SHADER_OPCODE_TG4_OFFSET
:
972 case SHADER_OPCODE_TXL
:
973 case SHADER_OPCODE_TXS
:
974 case SHADER_OPCODE_LOD
:
975 case SHADER_OPCODE_SAMPLEINFO
:
977 case FS_OPCODE_FB_WRITE
:
979 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
980 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
982 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
984 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
987 unreachable("not reached");
992 fs_visitor::vgrf(const glsl_type
*const type
)
994 int reg_width
= dispatch_width
/ 8;
995 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
996 brw_type_for_base_type(type
));
999 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1004 this->type
= BRW_REGISTER_TYPE_F
;
1005 this->stride
= (file
== UNIFORM
? 0 : 1);
1008 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1014 this->stride
= (file
== UNIFORM
? 0 : 1);
1017 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1018 * This brings in those uniform definitions
1021 fs_visitor::import_uniforms(fs_visitor
*v
)
1023 this->push_constant_loc
= v
->push_constant_loc
;
1024 this->pull_constant_loc
= v
->pull_constant_loc
;
1025 this->uniforms
= v
->uniforms
;
1029 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1031 assert(stage
== MESA_SHADER_FRAGMENT
);
1033 /* gl_FragCoord.x */
1034 bld
.MOV(wpos
, this->pixel_x
);
1035 wpos
= offset(wpos
, bld
, 1);
1037 /* gl_FragCoord.y */
1038 bld
.MOV(wpos
, this->pixel_y
);
1039 wpos
= offset(wpos
, bld
, 1);
1041 /* gl_FragCoord.z */
1042 if (devinfo
->gen
>= 6) {
1043 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1045 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1046 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1047 interp_reg(VARYING_SLOT_POS
, 2));
1049 wpos
= offset(wpos
, bld
, 1);
1051 /* gl_FragCoord.w: Already set up in emit_interpolation */
1052 bld
.MOV(wpos
, this->wpos_w
);
1055 enum brw_barycentric_mode
1056 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1058 /* Barycentric modes don't make sense for flat inputs. */
1059 assert(mode
!= INTERP_MODE_FLAT
);
1063 case nir_intrinsic_load_barycentric_pixel
:
1064 case nir_intrinsic_load_barycentric_at_offset
:
1065 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1067 case nir_intrinsic_load_barycentric_centroid
:
1068 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1070 case nir_intrinsic_load_barycentric_sample
:
1071 case nir_intrinsic_load_barycentric_at_sample
:
1072 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1075 unreachable("invalid intrinsic");
1078 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1081 return (enum brw_barycentric_mode
) bary
;
1085 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1087 static enum brw_barycentric_mode
1088 centroid_to_pixel(enum brw_barycentric_mode bary
)
1090 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1091 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1092 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1096 fs_visitor::emit_frontfacing_interpolation()
1098 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1100 if (devinfo
->gen
>= 6) {
1101 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1102 * a boolean result from this (~0/true or 0/false).
1104 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1105 * this task in only one instruction:
1106 * - a negation source modifier will flip the bit; and
1107 * - a W -> D type conversion will sign extend the bit into the high
1108 * word of the destination.
1110 * An ASR 15 fills the low word of the destination.
1112 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1115 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1117 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1118 * a boolean result from this (1/true or 0/false).
1120 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1121 * the negation source modifier to flip it. Unfortunately the SHR
1122 * instruction only operates on UD (or D with an abs source modifier)
1123 * sources without negation.
1125 * Instead, use ASR (which will give ~0/true or 0/false).
1127 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1130 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1137 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1139 assert(stage
== MESA_SHADER_FRAGMENT
);
1140 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1141 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1143 if (wm_prog_data
->persample_dispatch
) {
1144 /* Convert int_sample_pos to floating point */
1145 bld
.MOV(dst
, int_sample_pos
);
1146 /* Scale to the range [0, 1] */
1147 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1150 /* From ARB_sample_shading specification:
1151 * "When rendering to a non-multisample buffer, or if multisample
1152 * rasterization is disabled, gl_SamplePosition will always be
1155 bld
.MOV(dst
, brw_imm_f(0.5f
));
1160 fs_visitor::emit_samplepos_setup()
1162 assert(devinfo
->gen
>= 6);
1164 const fs_builder abld
= bld
.annotate("compute sample position");
1165 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1167 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1168 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1170 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1171 * mode will be enabled.
1173 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1174 * R31.1:0 Position Offset X/Y for Slot[3:0]
1175 * R31.3:2 Position Offset X/Y for Slot[7:4]
1178 * The X, Y sample positions come in as bytes in thread payload. So, read
1179 * the positions using vstride=16, width=8, hstride=2.
1181 struct brw_reg sample_pos_reg
=
1182 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1183 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1185 if (dispatch_width
== 8) {
1186 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1188 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1189 abld
.half(1).MOV(half(int_sample_x
, 1),
1190 fs_reg(suboffset(sample_pos_reg
, 16)));
1192 /* Compute gl_SamplePosition.x */
1193 compute_sample_position(pos
, int_sample_x
);
1194 pos
= offset(pos
, abld
, 1);
1195 if (dispatch_width
== 8) {
1196 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1198 abld
.half(0).MOV(half(int_sample_y
, 0),
1199 fs_reg(suboffset(sample_pos_reg
, 1)));
1200 abld
.half(1).MOV(half(int_sample_y
, 1),
1201 fs_reg(suboffset(sample_pos_reg
, 17)));
1203 /* Compute gl_SamplePosition.y */
1204 compute_sample_position(pos
, int_sample_y
);
1209 fs_visitor::emit_sampleid_setup()
1211 assert(stage
== MESA_SHADER_FRAGMENT
);
1212 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1213 assert(devinfo
->gen
>= 6);
1215 const fs_builder abld
= bld
.annotate("compute sample id");
1216 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1218 if (!key
->multisample_fbo
) {
1219 /* As per GL_ARB_sample_shading specification:
1220 * "When rendering to a non-multisample buffer, or if multisample
1221 * rasterization is disabled, gl_SampleID will always be zero."
1223 abld
.MOV(*reg
, brw_imm_d(0));
1224 } else if (devinfo
->gen
>= 8) {
1225 /* Sample ID comes in as 4-bit numbers in g1.0:
1227 * 15:12 Slot 3 SampleID (only used in SIMD16)
1228 * 11:8 Slot 2 SampleID (only used in SIMD16)
1229 * 7:4 Slot 1 SampleID
1230 * 3:0 Slot 0 SampleID
1232 * Each slot corresponds to four channels, so we want to replicate each
1233 * half-byte value to 4 channels in a row:
1235 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1236 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1238 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1239 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1241 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1242 * channels to read the first byte (7:0), and the second group of 8
1243 * channels to read the second byte (15:8). Then, we shift right by
1244 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1245 * values into place. Finally, we AND with 0xf to keep the low nibble.
1247 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1248 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1250 * TODO: These payload bits exist on Gen7 too, but they appear to always
1251 * be zero, so this code fails to work. We should find out why.
1253 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1255 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1256 BRW_REGISTER_TYPE_B
), 1, 8, 0)),
1257 brw_imm_v(0x44440000));
1258 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1260 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1262 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1264 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1265 * 8x multisampling, subspan 0 will represent sample N (where N
1266 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1267 * 7. We can find the value of N by looking at R0.0 bits 7:6
1268 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1269 * (since samples are always delivered in pairs). That is, we
1270 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1271 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1272 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1273 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1274 * populating a temporary variable with the sequence (0, 1, 2, 3),
1275 * and then reading from it using vstride=1, width=4, hstride=0.
1276 * These computations hold good for 4x multisampling as well.
1278 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1279 * the first four slots are sample 0 of subspan 0; the next four
1280 * are sample 1 of subspan 0; the third group is sample 0 of
1281 * subspan 1, and finally sample 1 of subspan 1.
1284 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1285 * accomodate 16x MSAA.
1287 abld
.exec_all().group(1, 0)
1288 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1290 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1292 /* This works for both SIMD8 and SIMD16 */
1293 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1295 /* This special instruction takes care of setting vstride=1,
1296 * width=4, hstride=0 of t2 during an ADD instruction.
1298 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1305 fs_visitor::emit_samplemaskin_setup()
1307 assert(stage
== MESA_SHADER_FRAGMENT
);
1308 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1309 assert(devinfo
->gen
>= 6);
1311 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1313 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1314 BRW_REGISTER_TYPE_D
));
1316 if (wm_prog_data
->persample_dispatch
) {
1317 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1318 * and a mask representing which sample is being processed by the
1319 * current shader invocation.
1321 * From the OES_sample_variables specification:
1322 * "When per-sample shading is active due to the use of a fragment input
1323 * qualified by "sample" or due to the use of the gl_SampleID or
1324 * gl_SamplePosition variables, only the bit for the current sample is
1325 * set in gl_SampleMaskIn."
1327 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1329 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1330 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1332 fs_reg one
= vgrf(glsl_type::int_type
);
1333 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1334 abld
.MOV(one
, brw_imm_d(1));
1335 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1336 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1338 /* In per-pixel mode, the coverage mask is sufficient. */
1339 *reg
= coverage_mask
;
1345 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1347 if (!src
.abs
&& !src
.negate
)
1350 fs_reg temp
= bld
.vgrf(src
.type
);
1357 fs_visitor::emit_discard_jump()
1359 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1361 /* For performance, after a discard, jump to the end of the
1362 * shader if all relevant channels have been discarded.
1364 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1365 discard_jump
->flag_subreg
= 1;
1367 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1368 discard_jump
->predicate_inverse
= true;
1372 fs_visitor::emit_gs_thread_end()
1374 assert(stage
== MESA_SHADER_GEOMETRY
);
1376 struct brw_gs_prog_data
*gs_prog_data
=
1377 (struct brw_gs_prog_data
*) prog_data
;
1379 if (gs_compile
->control_data_header_size_bits
> 0) {
1380 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1383 const fs_builder abld
= bld
.annotate("thread end");
1386 if (gs_prog_data
->static_vertex_count
!= -1) {
1387 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1388 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1389 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1390 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1391 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1394 /* Delete now dead instructions. */
1395 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1401 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1405 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1406 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1407 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1410 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1411 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1412 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1413 sources
[1] = this->final_gs_vertex_count
;
1414 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1415 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1423 fs_visitor::assign_curb_setup()
1425 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1427 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1428 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1429 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1430 if (inst
->src
[i
].file
== UNIFORM
) {
1431 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1433 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1434 constant_nr
= push_constant_loc
[uniform_nr
];
1436 /* Section 5.11 of the OpenGL 4.1 spec says:
1437 * "Out-of-bounds reads return undefined values, which include
1438 * values from other variables of the active program or zero."
1439 * Just return the first push constant.
1444 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1447 brw_reg
.abs
= inst
->src
[i
].abs
;
1448 brw_reg
.negate
= inst
->src
[i
].negate
;
1450 assert(inst
->src
[i
].stride
== 0);
1451 inst
->src
[i
] = byte_offset(
1452 retype(brw_reg
, inst
->src
[i
].type
),
1453 inst
->src
[i
].offset
% 4);
1458 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1459 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1463 fs_visitor::calculate_urb_setup()
1465 assert(stage
== MESA_SHADER_FRAGMENT
);
1466 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1467 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1469 memset(prog_data
->urb_setup
, -1,
1470 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1473 /* Figure out where each of the incoming setup attributes lands. */
1474 if (devinfo
->gen
>= 6) {
1475 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1476 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1477 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1478 * first 16 varying inputs, so we can put them wherever we want.
1479 * Just put them in order.
1481 * This is useful because it means that (a) inputs not used by the
1482 * fragment shader won't take up valuable register space, and (b) we
1483 * won't have to recompile the fragment shader if it gets paired with
1484 * a different vertex (or geometry) shader.
1486 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1487 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1488 BITFIELD64_BIT(i
)) {
1489 prog_data
->urb_setup
[i
] = urb_next
++;
1493 bool include_vue_header
=
1494 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1496 /* We have enough input varyings that the SF/SBE pipeline stage can't
1497 * arbitrarily rearrange them to suit our whim; we have to put them
1498 * in an order that matches the output of the previous pipeline stage
1499 * (geometry or vertex shader).
1501 struct brw_vue_map prev_stage_vue_map
;
1502 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1503 key
->input_slots_valid
,
1504 nir
->info
.separate_shader
);
1506 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1508 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1509 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1511 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1512 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1513 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1514 BITFIELD64_BIT(varying
))) {
1515 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1518 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1521 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1522 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1523 /* Point size is packed into the header, not as a general attribute */
1524 if (i
== VARYING_SLOT_PSIZ
)
1527 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1528 /* The back color slot is skipped when the front color is
1529 * also written to. In addition, some slots can be
1530 * written in the vertex shader and not read in the
1531 * fragment shader. So the register number must always be
1532 * incremented, mapped or not.
1534 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1535 prog_data
->urb_setup
[i
] = urb_next
;
1541 * It's a FS only attribute, and we did interpolation for this attribute
1542 * in SF thread. So, count it here, too.
1544 * See compile_sf_prog() for more info.
1546 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1547 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1550 prog_data
->num_varying_inputs
= urb_next
;
1554 fs_visitor::assign_urb_setup()
1556 assert(stage
== MESA_SHADER_FRAGMENT
);
1557 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1559 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1561 /* Offset all the urb_setup[] index by the actual position of the
1562 * setup regs, now that the location of the constants has been chosen.
1564 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1565 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1566 assert(inst
->src
[1].file
== FIXED_GRF
);
1567 inst
->src
[1].nr
+= urb_start
;
1570 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1571 assert(inst
->src
[0].file
== FIXED_GRF
);
1572 inst
->src
[0].nr
+= urb_start
;
1576 /* Each attribute is 4 setup channels, each of which is half a reg. */
1577 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1581 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1583 for (int i
= 0; i
< inst
->sources
; i
++) {
1584 if (inst
->src
[i
].file
== ATTR
) {
1585 int grf
= payload
.num_regs
+
1586 prog_data
->curb_read_length
+
1588 inst
->src
[i
].offset
/ REG_SIZE
;
1590 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1592 * VertStride must be used to cross GRF register boundaries. This
1593 * rule implies that elements within a 'Width' cannot cross GRF
1596 * So, for registers that are large enough, we have to split the exec
1597 * size in two and trust the compression state to sort it out.
1599 unsigned total_size
= inst
->exec_size
*
1600 inst
->src
[i
].stride
*
1601 type_sz(inst
->src
[i
].type
);
1603 assert(total_size
<= 2 * REG_SIZE
);
1604 const unsigned exec_size
=
1605 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1607 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1608 struct brw_reg reg
=
1609 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1610 inst
->src
[i
].offset
% REG_SIZE
),
1611 exec_size
* inst
->src
[i
].stride
,
1612 width
, inst
->src
[i
].stride
);
1613 reg
.abs
= inst
->src
[i
].abs
;
1614 reg
.negate
= inst
->src
[i
].negate
;
1622 fs_visitor::assign_vs_urb_setup()
1624 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1626 assert(stage
== MESA_SHADER_VERTEX
);
1628 /* Each attribute is 4 regs. */
1629 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1631 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1633 /* Rewrite all ATTR file references to the hw grf that they land in. */
1634 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1635 convert_attr_sources_to_hw_regs(inst
);
1640 fs_visitor::assign_tcs_single_patch_urb_setup()
1642 assert(stage
== MESA_SHADER_TESS_CTRL
);
1644 /* Rewrite all ATTR file references to HW_REGs. */
1645 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1646 convert_attr_sources_to_hw_regs(inst
);
1651 fs_visitor::assign_tes_urb_setup()
1653 assert(stage
== MESA_SHADER_TESS_EVAL
);
1655 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1657 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1659 /* Rewrite all ATTR file references to HW_REGs. */
1660 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1661 convert_attr_sources_to_hw_regs(inst
);
1666 fs_visitor::assign_gs_urb_setup()
1668 assert(stage
== MESA_SHADER_GEOMETRY
);
1670 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1672 first_non_payload_grf
+=
1673 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1675 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1676 /* Rewrite all ATTR file references to GRFs. */
1677 convert_attr_sources_to_hw_regs(inst
);
1683 * Split large virtual GRFs into separate components if we can.
1685 * This is mostly duplicated with what brw_fs_vector_splitting does,
1686 * but that's really conservative because it's afraid of doing
1687 * splitting that doesn't result in real progress after the rest of
1688 * the optimization phases, which would cause infinite looping in
1689 * optimization. We can do it once here, safely. This also has the
1690 * opportunity to split interpolated values, or maybe even uniforms,
1691 * which we don't have at the IR level.
1693 * We want to split, because virtual GRFs are what we register
1694 * allocate and spill (due to contiguousness requirements for some
1695 * instructions), and they're what we naturally generate in the
1696 * codegen process, but most virtual GRFs don't actually need to be
1697 * contiguous sets of GRFs. If we split, we'll end up with reduced
1698 * live intervals and better dead code elimination and coalescing.
1701 fs_visitor::split_virtual_grfs()
1703 int num_vars
= this->alloc
.count
;
1705 /* Count the total number of registers */
1707 int vgrf_to_reg
[num_vars
];
1708 for (int i
= 0; i
< num_vars
; i
++) {
1709 vgrf_to_reg
[i
] = reg_count
;
1710 reg_count
+= alloc
.sizes
[i
];
1713 /* An array of "split points". For each register slot, this indicates
1714 * if this slot can be separated from the previous slot. Every time an
1715 * instruction uses multiple elements of a register (as a source or
1716 * destination), we mark the used slots as inseparable. Then we go
1717 * through and split the registers into the smallest pieces we can.
1719 bool split_points
[reg_count
];
1720 memset(split_points
, 0, sizeof(split_points
));
1722 /* Mark all used registers as fully splittable */
1723 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1724 if (inst
->dst
.file
== VGRF
) {
1725 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1726 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1727 split_points
[reg
+ j
] = true;
1730 for (int i
= 0; i
< inst
->sources
; i
++) {
1731 if (inst
->src
[i
].file
== VGRF
) {
1732 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1733 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1734 split_points
[reg
+ j
] = true;
1739 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1740 if (inst
->dst
.file
== VGRF
) {
1741 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1742 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1743 split_points
[reg
+ j
] = false;
1745 for (int i
= 0; i
< inst
->sources
; i
++) {
1746 if (inst
->src
[i
].file
== VGRF
) {
1747 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1748 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1749 split_points
[reg
+ j
] = false;
1754 int new_virtual_grf
[reg_count
];
1755 int new_reg_offset
[reg_count
];
1758 for (int i
= 0; i
< num_vars
; i
++) {
1759 /* The first one should always be 0 as a quick sanity check. */
1760 assert(split_points
[reg
] == false);
1763 new_reg_offset
[reg
] = 0;
1768 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1769 /* If this is a split point, reset the offset to 0 and allocate a
1770 * new virtual GRF for the previous offset many registers
1772 if (split_points
[reg
]) {
1773 assert(offset
<= MAX_VGRF_SIZE
);
1774 int grf
= alloc
.allocate(offset
);
1775 for (int k
= reg
- offset
; k
< reg
; k
++)
1776 new_virtual_grf
[k
] = grf
;
1779 new_reg_offset
[reg
] = offset
;
1784 /* The last one gets the original register number */
1785 assert(offset
<= MAX_VGRF_SIZE
);
1786 alloc
.sizes
[i
] = offset
;
1787 for (int k
= reg
- offset
; k
< reg
; k
++)
1788 new_virtual_grf
[k
] = i
;
1790 assert(reg
== reg_count
);
1792 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1793 if (inst
->dst
.file
== VGRF
) {
1794 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1795 inst
->dst
.nr
= new_virtual_grf
[reg
];
1796 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
1797 inst
->dst
.offset
% REG_SIZE
;
1798 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1800 for (int i
= 0; i
< inst
->sources
; i
++) {
1801 if (inst
->src
[i
].file
== VGRF
) {
1802 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1803 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1804 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
1805 inst
->src
[i
].offset
% REG_SIZE
;
1806 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1810 invalidate_live_intervals();
1814 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1816 * During code generation, we create tons of temporary variables, many of
1817 * which get immediately killed and are never used again. Yet, in later
1818 * optimization and analysis passes, such as compute_live_intervals, we need
1819 * to loop over all the virtual GRFs. Compacting them can save a lot of
1823 fs_visitor::compact_virtual_grfs()
1825 bool progress
= false;
1826 int remap_table
[this->alloc
.count
];
1827 memset(remap_table
, -1, sizeof(remap_table
));
1829 /* Mark which virtual GRFs are used. */
1830 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1831 if (inst
->dst
.file
== VGRF
)
1832 remap_table
[inst
->dst
.nr
] = 0;
1834 for (int i
= 0; i
< inst
->sources
; i
++) {
1835 if (inst
->src
[i
].file
== VGRF
)
1836 remap_table
[inst
->src
[i
].nr
] = 0;
1840 /* Compact the GRF arrays. */
1842 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1843 if (remap_table
[i
] == -1) {
1844 /* We just found an unused register. This means that we are
1845 * actually going to compact something.
1849 remap_table
[i
] = new_index
;
1850 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1851 invalidate_live_intervals();
1856 this->alloc
.count
= new_index
;
1858 /* Patch all the instructions to use the newly renumbered registers */
1859 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1860 if (inst
->dst
.file
== VGRF
)
1861 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1863 for (int i
= 0; i
< inst
->sources
; i
++) {
1864 if (inst
->src
[i
].file
== VGRF
)
1865 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1869 /* Patch all the references to delta_xy, since they're used in register
1870 * allocation. If they're unused, switch them to BAD_FILE so we don't
1871 * think some random VGRF is delta_xy.
1873 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1874 if (delta_xy
[i
].file
== VGRF
) {
1875 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1876 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1878 delta_xy
[i
].file
= BAD_FILE
;
1887 set_push_pull_constant_loc(unsigned uniform
, int *chunk_start
, bool contiguous
,
1888 int *push_constant_loc
, int *pull_constant_loc
,
1889 unsigned *num_push_constants
,
1890 unsigned *num_pull_constants
,
1891 const unsigned max_push_components
,
1892 const unsigned max_chunk_size
,
1893 struct brw_stage_prog_data
*stage_prog_data
)
1895 /* This is the first live uniform in the chunk */
1896 if (*chunk_start
< 0)
1897 *chunk_start
= uniform
;
1899 /* If this element does not need to be contiguous with the next, we
1900 * split at this point and everything between chunk_start and u forms a
1904 unsigned chunk_size
= uniform
- *chunk_start
+ 1;
1906 /* Decide whether we should push or pull this parameter. In the
1907 * Vulkan driver, push constants are explicitly exposed via the API
1908 * so we push everything. In GL, we only push small arrays.
1910 if (stage_prog_data
->pull_param
== NULL
||
1911 (*num_push_constants
+ chunk_size
<= max_push_components
&&
1912 chunk_size
<= max_chunk_size
)) {
1913 assert(*num_push_constants
+ chunk_size
<= max_push_components
);
1914 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1915 push_constant_loc
[j
] = (*num_push_constants
)++;
1917 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1918 pull_constant_loc
[j
] = (*num_pull_constants
)++;
1926 * Assign UNIFORM file registers to either push constants or pull constants.
1928 * We allow a fragment shader to have more than the specified minimum
1929 * maximum number of fragment shader uniform components (64). If
1930 * there are too many of these, they'd fill up all of register space.
1931 * So, this will push some of them out to the pull constant buffer and
1932 * update the program to load them.
1935 fs_visitor::assign_constant_locations()
1937 /* Only the first compile gets to decide on locations. */
1938 if (dispatch_width
!= min_dispatch_width
)
1941 bool is_live
[uniforms
];
1942 memset(is_live
, 0, sizeof(is_live
));
1943 bool is_live_64bit
[uniforms
];
1944 memset(is_live_64bit
, 0, sizeof(is_live_64bit
));
1946 /* For each uniform slot, a value of true indicates that the given slot and
1947 * the next slot must remain contiguous. This is used to keep us from
1948 * splitting arrays apart.
1950 bool contiguous
[uniforms
];
1951 memset(contiguous
, 0, sizeof(contiguous
));
1953 int thread_local_id_index
=
1954 (stage
== MESA_SHADER_COMPUTE
) ?
1955 ((brw_cs_prog_data
*)stage_prog_data
)->thread_local_id_index
: -1;
1957 /* First, we walk through the instructions and do two things:
1959 * 1) Figure out which uniforms are live.
1961 * 2) Mark any indirectly used ranges of registers as contiguous.
1963 * Note that we don't move constant-indexed accesses to arrays. No
1964 * testing has been done of the performance impact of this choice.
1966 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1967 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1968 if (inst
->src
[i
].file
!= UNIFORM
)
1971 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1973 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
1974 assert(inst
->src
[2].ud
% 4 == 0);
1975 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
1976 assert(last
< uniforms
);
1978 for (unsigned j
= constant_nr
; j
< last
; j
++) {
1980 contiguous
[j
] = true;
1981 if (type_sz(inst
->src
[i
].type
) == 8) {
1982 is_live_64bit
[j
] = true;
1985 is_live
[last
] = true;
1987 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
) {
1988 int regs_read
= inst
->components_read(i
) *
1989 type_sz(inst
->src
[i
].type
) / 4;
1990 for (int j
= 0; j
< regs_read
; j
++) {
1991 is_live
[constant_nr
+ j
] = true;
1992 if (type_sz(inst
->src
[i
].type
) == 8) {
1993 is_live_64bit
[constant_nr
+ j
] = true;
2001 if (thread_local_id_index
>= 0 && !is_live
[thread_local_id_index
])
2002 thread_local_id_index
= -1;
2004 /* Only allow 16 registers (128 uniform components) as push constants.
2006 * Just demote the end of the list. We could probably do better
2007 * here, demoting things that are rarely used in the program first.
2009 * If changing this value, note the limitation about total_regs in
2012 unsigned int max_push_components
= 16 * 8;
2013 if (thread_local_id_index
>= 0)
2014 max_push_components
--; /* Save a slot for the thread ID */
2016 /* We push small arrays, but no bigger than 16 floats. This is big enough
2017 * for a vec4 but hopefully not large enough to push out other stuff. We
2018 * should probably use a better heuristic at some point.
2020 const unsigned int max_chunk_size
= 16;
2022 unsigned int num_push_constants
= 0;
2023 unsigned int num_pull_constants
= 0;
2025 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2026 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2028 /* Default to -1 meaning no location */
2029 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2030 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2032 int chunk_start
= -1;
2034 /* First push 64-bit uniforms to ensure they are properly aligned */
2035 for (unsigned u
= 0; u
< uniforms
; u
++) {
2036 if (!is_live
[u
] || !is_live_64bit
[u
])
2039 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2040 push_constant_loc
, pull_constant_loc
,
2041 &num_push_constants
, &num_pull_constants
,
2042 max_push_components
, max_chunk_size
,
2047 /* Then push the rest of uniforms */
2048 for (unsigned u
= 0; u
< uniforms
; u
++) {
2049 if (!is_live
[u
] || is_live_64bit
[u
])
2052 /* Skip thread_local_id_index to put it in the last push register. */
2053 if (thread_local_id_index
== (int)u
)
2056 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2057 push_constant_loc
, pull_constant_loc
,
2058 &num_push_constants
, &num_pull_constants
,
2059 max_push_components
, max_chunk_size
,
2063 /* Add the CS local thread ID uniform at the end of the push constants */
2064 if (thread_local_id_index
>= 0)
2065 push_constant_loc
[thread_local_id_index
] = num_push_constants
++;
2067 /* As the uniforms are going to be reordered, take the data from a temporary
2068 * copy of the original param[].
2070 gl_constant_value
**param
= ralloc_array(NULL
, gl_constant_value
*,
2071 stage_prog_data
->nr_params
);
2072 memcpy(param
, stage_prog_data
->param
,
2073 sizeof(gl_constant_value
*) * stage_prog_data
->nr_params
);
2074 stage_prog_data
->nr_params
= num_push_constants
;
2075 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2077 /* Up until now, the param[] array has been indexed by reg + reg_offset
2078 * of UNIFORM registers. Move pull constants into pull_param[] and
2079 * condense param[] to only contain the uniforms we chose to push.
2081 * NOTE: Because we are condensing the params[] array, we know that
2082 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2083 * having to make a copy.
2085 int new_thread_local_id_index
= -1;
2086 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2087 const gl_constant_value
*value
= param
[i
];
2089 if (pull_constant_loc
[i
] != -1) {
2090 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2091 } else if (push_constant_loc
[i
] != -1) {
2092 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2093 if (thread_local_id_index
== (int)i
)
2094 new_thread_local_id_index
= push_constant_loc
[i
];
2099 if (stage
== MESA_SHADER_COMPUTE
)
2100 ((brw_cs_prog_data
*)stage_prog_data
)->thread_local_id_index
=
2101 new_thread_local_id_index
;
2105 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2106 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2109 fs_visitor::lower_constant_loads()
2111 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2113 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2114 /* Set up the annotation tracking for new generated instructions. */
2115 const fs_builder
ibld(this, block
, inst
);
2117 for (int i
= 0; i
< inst
->sources
; i
++) {
2118 if (inst
->src
[i
].file
!= UNIFORM
)
2121 /* We'll handle this case later */
2122 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2125 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
2126 if (location
>= uniforms
)
2127 continue; /* Out of bounds access */
2129 int pull_index
= pull_constant_loc
[location
];
2131 if (pull_index
== -1)
2134 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2137 if (type_sz(inst
->src
[i
].type
) <= 4)
2138 dst
= vgrf(glsl_type::float_type
);
2140 dst
= vgrf(glsl_type::double_type
);
2142 assert(inst
->src
[i
].stride
== 0);
2144 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2145 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2146 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2147 dst
, brw_imm_ud(index
), offset
);
2149 /* Rewrite the instruction to use the temporary VGRF. */
2150 inst
->src
[i
].file
= VGRF
;
2151 inst
->src
[i
].nr
= dst
.nr
;
2152 inst
->src
[i
].offset
%= 4;
2153 inst
->src
[i
].set_smear((pull_index
& 3) * 4 /
2154 type_sz(inst
->src
[i
].type
));
2156 brw_mark_surface_used(prog_data
, index
);
2159 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2160 inst
->src
[0].file
== UNIFORM
) {
2162 unsigned location
= inst
->src
[0].nr
+ inst
->src
[0].offset
/ 4;
2163 if (location
>= uniforms
)
2164 continue; /* Out of bounds access */
2166 int pull_index
= pull_constant_loc
[location
];
2168 if (pull_index
== -1)
2171 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2175 inst
->remove(block
);
2177 brw_mark_surface_used(prog_data
, index
);
2180 invalidate_live_intervals();
2184 fs_visitor::opt_algebraic()
2186 bool progress
= false;
2188 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2189 switch (inst
->opcode
) {
2190 case BRW_OPCODE_MOV
:
2191 if (inst
->src
[0].file
!= IMM
)
2194 if (inst
->saturate
) {
2195 if (inst
->dst
.type
!= inst
->src
[0].type
)
2196 assert(!"unimplemented: saturate mixed types");
2198 if (brw_saturate_immediate(inst
->dst
.type
,
2199 &inst
->src
[0].as_brw_reg())) {
2200 inst
->saturate
= false;
2206 case BRW_OPCODE_MUL
:
2207 if (inst
->src
[1].file
!= IMM
)
2211 if (inst
->src
[1].is_one()) {
2212 inst
->opcode
= BRW_OPCODE_MOV
;
2213 inst
->src
[1] = reg_undef
;
2219 if (inst
->src
[1].is_negative_one()) {
2220 inst
->opcode
= BRW_OPCODE_MOV
;
2221 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2222 inst
->src
[1] = reg_undef
;
2228 if (inst
->src
[1].is_zero()) {
2229 inst
->opcode
= BRW_OPCODE_MOV
;
2230 inst
->src
[0] = inst
->src
[1];
2231 inst
->src
[1] = reg_undef
;
2236 if (inst
->src
[0].file
== IMM
) {
2237 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2238 inst
->opcode
= BRW_OPCODE_MOV
;
2239 inst
->src
[0].f
*= inst
->src
[1].f
;
2240 inst
->src
[1] = reg_undef
;
2245 case BRW_OPCODE_ADD
:
2246 if (inst
->src
[1].file
!= IMM
)
2250 if (inst
->src
[1].is_zero()) {
2251 inst
->opcode
= BRW_OPCODE_MOV
;
2252 inst
->src
[1] = reg_undef
;
2257 if (inst
->src
[0].file
== IMM
) {
2258 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2259 inst
->opcode
= BRW_OPCODE_MOV
;
2260 inst
->src
[0].f
+= inst
->src
[1].f
;
2261 inst
->src
[1] = reg_undef
;
2267 if (inst
->src
[0].equals(inst
->src
[1])) {
2268 inst
->opcode
= BRW_OPCODE_MOV
;
2269 inst
->src
[1] = reg_undef
;
2274 case BRW_OPCODE_LRP
:
2275 if (inst
->src
[1].equals(inst
->src
[2])) {
2276 inst
->opcode
= BRW_OPCODE_MOV
;
2277 inst
->src
[0] = inst
->src
[1];
2278 inst
->src
[1] = reg_undef
;
2279 inst
->src
[2] = reg_undef
;
2284 case BRW_OPCODE_CMP
:
2285 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2287 inst
->src
[0].negate
&&
2288 inst
->src
[1].is_zero()) {
2289 inst
->src
[0].abs
= false;
2290 inst
->src
[0].negate
= false;
2291 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2296 case BRW_OPCODE_SEL
:
2297 if (inst
->src
[0].equals(inst
->src
[1])) {
2298 inst
->opcode
= BRW_OPCODE_MOV
;
2299 inst
->src
[1] = reg_undef
;
2300 inst
->predicate
= BRW_PREDICATE_NONE
;
2301 inst
->predicate_inverse
= false;
2303 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2304 switch (inst
->conditional_mod
) {
2305 case BRW_CONDITIONAL_LE
:
2306 case BRW_CONDITIONAL_L
:
2307 switch (inst
->src
[1].type
) {
2308 case BRW_REGISTER_TYPE_F
:
2309 if (inst
->src
[1].f
>= 1.0f
) {
2310 inst
->opcode
= BRW_OPCODE_MOV
;
2311 inst
->src
[1] = reg_undef
;
2312 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2320 case BRW_CONDITIONAL_GE
:
2321 case BRW_CONDITIONAL_G
:
2322 switch (inst
->src
[1].type
) {
2323 case BRW_REGISTER_TYPE_F
:
2324 if (inst
->src
[1].f
<= 0.0f
) {
2325 inst
->opcode
= BRW_OPCODE_MOV
;
2326 inst
->src
[1] = reg_undef
;
2327 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2339 case BRW_OPCODE_MAD
:
2340 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2341 inst
->opcode
= BRW_OPCODE_MOV
;
2342 inst
->src
[1] = reg_undef
;
2343 inst
->src
[2] = reg_undef
;
2345 } else if (inst
->src
[0].is_zero()) {
2346 inst
->opcode
= BRW_OPCODE_MUL
;
2347 inst
->src
[0] = inst
->src
[2];
2348 inst
->src
[2] = reg_undef
;
2350 } else if (inst
->src
[1].is_one()) {
2351 inst
->opcode
= BRW_OPCODE_ADD
;
2352 inst
->src
[1] = inst
->src
[2];
2353 inst
->src
[2] = reg_undef
;
2355 } else if (inst
->src
[2].is_one()) {
2356 inst
->opcode
= BRW_OPCODE_ADD
;
2357 inst
->src
[2] = reg_undef
;
2359 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2360 inst
->opcode
= BRW_OPCODE_ADD
;
2361 inst
->src
[1].f
*= inst
->src
[2].f
;
2362 inst
->src
[2] = reg_undef
;
2366 case SHADER_OPCODE_BROADCAST
:
2367 if (is_uniform(inst
->src
[0])) {
2368 inst
->opcode
= BRW_OPCODE_MOV
;
2370 inst
->force_writemask_all
= true;
2372 } else if (inst
->src
[1].file
== IMM
) {
2373 inst
->opcode
= BRW_OPCODE_MOV
;
2374 inst
->src
[0] = component(inst
->src
[0],
2377 inst
->force_writemask_all
= true;
2386 /* Swap if src[0] is immediate. */
2387 if (progress
&& inst
->is_commutative()) {
2388 if (inst
->src
[0].file
== IMM
) {
2389 fs_reg tmp
= inst
->src
[1];
2390 inst
->src
[1] = inst
->src
[0];
2399 * Optimize sample messages that have constant zero values for the trailing
2400 * texture coordinates. We can just reduce the message length for these
2401 * instructions instead of reserving a register for it. Trailing parameters
2402 * that aren't sent default to zero anyway. This will cause the dead code
2403 * eliminator to remove the MOV instruction that would otherwise be emitted to
2404 * set up the zero value.
2407 fs_visitor::opt_zero_samples()
2409 /* Gen4 infers the texturing opcode based on the message length so we can't
2412 if (devinfo
->gen
< 5)
2415 bool progress
= false;
2417 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2418 if (!inst
->is_tex())
2421 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2423 if (load_payload
->is_head_sentinel() ||
2424 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2427 /* We don't want to remove the message header or the first parameter.
2428 * Removing the first parameter is not allowed, see the Haswell PRM
2429 * volume 7, page 149:
2431 * "Parameter 0 is required except for the sampleinfo message, which
2432 * has no parameter 0"
2434 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2435 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2436 (inst
->exec_size
/ 8) +
2437 inst
->header_size
- 1].is_zero()) {
2438 inst
->mlen
-= inst
->exec_size
/ 8;
2444 invalidate_live_intervals();
2450 * Optimize sample messages which are followed by the final RT write.
2452 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2453 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2454 * final texturing results copied to the framebuffer write payload and modify
2455 * them to write to the framebuffer directly.
2458 fs_visitor::opt_sampler_eot()
2460 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2462 if (stage
!= MESA_SHADER_FRAGMENT
)
2465 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2468 /* FINISHME: It should be possible to implement this optimization when there
2469 * are multiple drawbuffers.
2471 if (key
->nr_color_regions
!= 1)
2474 /* Requires emitting a bunch of saturating MOV instructions during logical
2475 * send lowering to clamp the color payload, which the sampler unit isn't
2476 * going to do for us.
2478 if (key
->clamp_fragment_color
)
2481 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2482 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2483 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2484 assert(fb_write
->eot
);
2485 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2487 /* There wasn't one; nothing to do. */
2488 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2491 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2493 /* 3D Sampler » Messages » Message Format
2495 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2496 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2498 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2499 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2500 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2501 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2502 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2503 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2504 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2505 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2508 /* XXX - This shouldn't be necessary. */
2509 if (tex_inst
->prev
->is_head_sentinel())
2512 /* Check that the FB write sources are fully initialized by the single
2513 * texturing instruction.
2515 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2516 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2517 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2518 fb_write
->size_read(i
) != tex_inst
->size_written
)
2520 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2521 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2526 assert(!tex_inst
->eot
); /* We can't get here twice */
2527 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2529 const fs_builder
ibld(this, block
, tex_inst
);
2531 tex_inst
->offset
|= fb_write
->target
<< 24;
2532 tex_inst
->eot
= true;
2533 tex_inst
->dst
= ibld
.null_reg_ud();
2534 tex_inst
->size_written
= 0;
2535 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2537 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2538 * flag and submit a header together with the sampler message as required
2541 invalidate_live_intervals();
2546 fs_visitor::opt_register_renaming()
2548 bool progress
= false;
2551 int remap
[alloc
.count
];
2552 memset(remap
, -1, sizeof(int) * alloc
.count
);
2554 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2555 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2557 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2558 inst
->opcode
== BRW_OPCODE_WHILE
) {
2562 /* Rewrite instruction sources. */
2563 for (int i
= 0; i
< inst
->sources
; i
++) {
2564 if (inst
->src
[i
].file
== VGRF
&&
2565 remap
[inst
->src
[i
].nr
] != -1 &&
2566 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2567 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2572 const int dst
= inst
->dst
.nr
;
2575 inst
->dst
.file
== VGRF
&&
2576 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
2577 !inst
->is_partial_write()) {
2578 if (remap
[dst
] == -1) {
2581 remap
[dst
] = alloc
.allocate(regs_written(inst
));
2582 inst
->dst
.nr
= remap
[dst
];
2585 } else if (inst
->dst
.file
== VGRF
&&
2587 remap
[dst
] != dst
) {
2588 inst
->dst
.nr
= remap
[dst
];
2594 invalidate_live_intervals();
2596 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2597 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2598 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2607 * Remove redundant or useless discard jumps.
2609 * For example, we can eliminate jumps in the following sequence:
2611 * discard-jump (redundant with the next jump)
2612 * discard-jump (useless; jumps to the next instruction)
2616 fs_visitor::opt_redundant_discard_jumps()
2618 bool progress
= false;
2620 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2622 fs_inst
*placeholder_halt
= NULL
;
2623 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2624 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2625 placeholder_halt
= inst
;
2630 if (!placeholder_halt
)
2633 /* Delete any HALTs immediately before the placeholder halt. */
2634 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2635 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2636 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2637 prev
->remove(last_bblock
);
2642 invalidate_live_intervals();
2648 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2649 * from \p r.offset which overlaps the region starting at \p s.offset and
2650 * spanning \p ds bytes.
2652 static inline unsigned
2653 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
2655 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
2656 const int shift
= rel_offset
/ REG_SIZE
;
2657 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
2658 assert(reg_space(r
) == reg_space(s
) &&
2659 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
2660 return ((1 << n
) - 1) << shift
;
2664 fs_visitor::compute_to_mrf()
2666 bool progress
= false;
2669 /* No MRFs on Gen >= 7. */
2670 if (devinfo
->gen
>= 7)
2673 calculate_live_intervals();
2675 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2679 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2680 inst
->is_partial_write() ||
2681 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2682 inst
->dst
.type
!= inst
->src
[0].type
||
2683 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2684 !inst
->src
[0].is_contiguous() ||
2685 inst
->src
[0].offset
% REG_SIZE
!= 0)
2688 /* Can't compute-to-MRF this GRF if someone else was going to
2691 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2694 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
2695 * things that computed the value of all GRFs of the source region. The
2696 * regs_left bitset keeps track of the registers we haven't yet found a
2697 * generating instruction for.
2699 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
2701 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2702 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2703 inst
->src
[0], inst
->size_read(0))) {
2704 /* Found the last thing to write our reg we want to turn
2705 * into a compute-to-MRF.
2708 /* If this one instruction didn't populate all the
2709 * channels, bail. We might be able to rewrite everything
2710 * that writes that reg, but it would require smarter
2713 if (scan_inst
->is_partial_write())
2716 /* Handling things not fully contained in the source of the copy
2717 * would need us to understand coalescing out more than one MOV at
2720 if (scan_inst
->dst
.offset
/ REG_SIZE
< inst
->src
[0].offset
/ REG_SIZE
||
2721 scan_inst
->dst
.offset
/ REG_SIZE
+ DIV_ROUND_UP(scan_inst
->size_written
, REG_SIZE
) >
2722 inst
->src
[0].offset
/ REG_SIZE
+ DIV_ROUND_UP(inst
->size_read(0), REG_SIZE
))
2725 /* SEND instructions can't have MRF as a destination. */
2726 if (scan_inst
->mlen
)
2729 if (devinfo
->gen
== 6) {
2730 /* gen6 math instructions must have the destination be
2731 * GRF, so no compute-to-MRF for them.
2733 if (scan_inst
->is_math()) {
2738 /* Clear the bits for any registers this instruction overwrites. */
2739 regs_left
&= ~mask_relative_to(
2740 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
2745 /* We don't handle control flow here. Most computation of
2746 * values that end up in MRFs are shortly before the MRF
2749 if (block
->start() == scan_inst
)
2752 /* You can't read from an MRF, so if someone else reads our
2753 * MRF's source GRF that we wanted to rewrite, that stops us.
2755 bool interfered
= false;
2756 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2757 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
2758 inst
->src
[0], inst
->size_read(0))) {
2765 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2766 inst
->dst
, inst
->size_written
)) {
2767 /* If somebody else writes our MRF here, we can't
2768 * compute-to-MRF before that.
2773 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
2774 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
2775 inst
->dst
, inst
->size_written
)) {
2776 /* Found a SEND instruction, which means that there are
2777 * live values in MRFs from base_mrf to base_mrf +
2778 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2788 /* Found all generating instructions of our MRF's source value, so it
2789 * should be safe to rewrite them to point to the MRF directly.
2791 regs_left
= (1 << regs_read(inst
, 0)) - 1;
2793 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2794 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2795 inst
->src
[0], inst
->size_read(0))) {
2796 /* Clear the bits for any registers this instruction overwrites. */
2797 regs_left
&= ~mask_relative_to(
2798 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
2800 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
2801 reg_offset(inst
->src
[0]);
2803 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2804 /* Apply the same address transformation done by the hardware
2805 * for COMPR4 MRF writes.
2807 assert(rel_offset
< 2 * REG_SIZE
);
2808 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
2810 /* Clear the COMPR4 bit if the generating instruction is not
2813 if (scan_inst
->size_written
< 2 * REG_SIZE
)
2814 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
2817 /* Calculate the MRF number the result of this instruction is
2818 * ultimately written to.
2820 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
2823 scan_inst
->dst
.file
= MRF
;
2824 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
2825 scan_inst
->saturate
|= inst
->saturate
;
2832 inst
->remove(block
);
2837 invalidate_live_intervals();
2843 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2844 * flow. We could probably do better here with some form of divergence
2848 fs_visitor::eliminate_find_live_channel()
2850 bool progress
= false;
2853 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2854 switch (inst
->opcode
) {
2860 case BRW_OPCODE_ENDIF
:
2861 case BRW_OPCODE_WHILE
:
2865 case FS_OPCODE_DISCARD_JUMP
:
2866 /* This can potentially make control flow non-uniform until the end
2871 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2873 inst
->opcode
= BRW_OPCODE_MOV
;
2874 inst
->src
[0] = brw_imm_ud(0u);
2876 inst
->force_writemask_all
= true;
2890 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2891 * instructions to FS_OPCODE_REP_FB_WRITE.
2894 fs_visitor::emit_repclear_shader()
2896 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2898 int color_mrf
= base_mrf
+ 2;
2902 mov
= bld
.exec_all().group(4, 0)
2903 .MOV(brw_message_reg(color_mrf
),
2904 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2906 struct brw_reg reg
=
2907 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2908 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
2909 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2911 mov
= bld
.exec_all().group(4, 0)
2912 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
2916 if (key
->nr_color_regions
== 1) {
2917 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2918 write
->saturate
= key
->clamp_fragment_color
;
2919 write
->base_mrf
= color_mrf
;
2921 write
->header_size
= 0;
2924 assume(key
->nr_color_regions
> 0);
2925 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2926 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2927 write
->saturate
= key
->clamp_fragment_color
;
2928 write
->base_mrf
= base_mrf
;
2930 write
->header_size
= 2;
2938 assign_constant_locations();
2939 assign_curb_setup();
2941 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2943 assert(mov
->src
[0].file
== FIXED_GRF
);
2944 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2949 * Walks through basic blocks, looking for repeated MRF writes and
2950 * removing the later ones.
2953 fs_visitor::remove_duplicate_mrf_writes()
2955 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2956 bool progress
= false;
2958 /* Need to update the MRF tracking for compressed instructions. */
2959 if (dispatch_width
>= 16)
2962 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2964 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2965 if (inst
->is_control_flow()) {
2966 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2969 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2970 inst
->dst
.file
== MRF
) {
2971 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
2972 if (prev_inst
&& inst
->equals(prev_inst
)) {
2973 inst
->remove(block
);
2979 /* Clear out the last-write records for MRFs that were overwritten. */
2980 if (inst
->dst
.file
== MRF
) {
2981 last_mrf_move
[inst
->dst
.nr
] = NULL
;
2984 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2985 /* Found a SEND instruction, which will include two or fewer
2986 * implied MRF writes. We could do better here.
2988 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2989 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2993 /* Clear out any MRF move records whose sources got overwritten. */
2994 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2995 if (last_mrf_move
[i
] &&
2996 regions_overlap(inst
->dst
, inst
->size_written
,
2997 last_mrf_move
[i
]->src
[0],
2998 last_mrf_move
[i
]->size_read(0))) {
2999 last_mrf_move
[i
] = NULL
;
3003 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3004 inst
->dst
.file
== MRF
&&
3005 inst
->src
[0].file
!= ARF
&&
3006 !inst
->is_partial_write()) {
3007 last_mrf_move
[inst
->dst
.nr
] = inst
;
3012 invalidate_live_intervals();
3018 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3020 /* Clear the flag for registers that actually got read (as expected). */
3021 for (int i
= 0; i
< inst
->sources
; i
++) {
3023 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3024 grf
= inst
->src
[i
].nr
;
3029 if (grf
>= first_grf
&&
3030 grf
< first_grf
+ grf_len
) {
3031 deps
[grf
- first_grf
] = false;
3032 if (inst
->exec_size
== 16)
3033 deps
[grf
- first_grf
+ 1] = false;
3039 * Implements this workaround for the original 965:
3041 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3042 * check for post destination dependencies on this instruction, software
3043 * must ensure that there is no destination hazard for the case of ‘write
3044 * followed by a posted write’ shown in the following example.
3047 * 2. send r3.xy <rest of send instruction>
3050 * Due to no post-destination dependency check on the ‘send’, the above
3051 * code sequence could have two instructions (1 and 2) in flight at the
3052 * same time that both consider ‘r3’ as the target of their final writes.
3055 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3058 int write_len
= regs_written(inst
);
3059 int first_write_grf
= inst
->dst
.nr
;
3060 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3061 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3063 memset(needs_dep
, false, sizeof(needs_dep
));
3064 memset(needs_dep
, true, write_len
);
3066 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3068 /* Walk backwards looking for writes to registers we're writing which
3069 * aren't read since being written. If we hit the start of the program,
3070 * we assume that there are no outstanding dependencies on entry to the
3073 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3074 /* If we hit control flow, assume that there *are* outstanding
3075 * dependencies, and force their cleanup before our instruction.
3077 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3078 for (int i
= 0; i
< write_len
; i
++) {
3080 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3081 first_write_grf
+ i
);
3086 /* We insert our reads as late as possible on the assumption that any
3087 * instruction but a MOV that might have left us an outstanding
3088 * dependency has more latency than a MOV.
3090 if (scan_inst
->dst
.file
== VGRF
) {
3091 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3092 int reg
= scan_inst
->dst
.nr
+ i
;
3094 if (reg
>= first_write_grf
&&
3095 reg
< first_write_grf
+ write_len
&&
3096 needs_dep
[reg
- first_write_grf
]) {
3097 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3098 needs_dep
[reg
- first_write_grf
] = false;
3099 if (scan_inst
->exec_size
== 16)
3100 needs_dep
[reg
- first_write_grf
+ 1] = false;
3105 /* Clear the flag for registers that actually got read (as expected). */
3106 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3108 /* Continue the loop only if we haven't resolved all the dependencies */
3110 for (i
= 0; i
< write_len
; i
++) {
3120 * Implements this workaround for the original 965:
3122 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3123 * used as a destination register until after it has been sourced by an
3124 * instruction with a different destination register.
3127 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3129 int write_len
= regs_written(inst
);
3130 int first_write_grf
= inst
->dst
.nr
;
3131 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3132 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3134 memset(needs_dep
, false, sizeof(needs_dep
));
3135 memset(needs_dep
, true, write_len
);
3136 /* Walk forwards looking for writes to registers we're writing which aren't
3137 * read before being written.
3139 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3140 /* If we hit control flow, force resolve all remaining dependencies. */
3141 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3142 for (int i
= 0; i
< write_len
; i
++) {
3144 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3145 first_write_grf
+ i
);
3150 /* Clear the flag for registers that actually got read (as expected). */
3151 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3153 /* We insert our reads as late as possible since they're reading the
3154 * result of a SEND, which has massive latency.
3156 if (scan_inst
->dst
.file
== VGRF
&&
3157 scan_inst
->dst
.nr
>= first_write_grf
&&
3158 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3159 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3160 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3162 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3165 /* Continue the loop only if we haven't resolved all the dependencies */
3167 for (i
= 0; i
< write_len
; i
++) {
3177 fs_visitor::insert_gen4_send_dependency_workarounds()
3179 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3182 bool progress
= false;
3184 /* Note that we're done with register allocation, so GRF fs_regs always
3185 * have a .reg_offset of 0.
3188 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3189 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3190 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3191 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3197 invalidate_live_intervals();
3201 * Turns the generic expression-style uniform pull constant load instruction
3202 * into a hardware-specific series of instructions for loading a pull
3205 * The expression style allows the CSE pass before this to optimize out
3206 * repeated loads from the same offset, and gives the pre-register-allocation
3207 * scheduling full flexibility, while the conversion to native instructions
3208 * allows the post-register-allocation scheduler the best information
3211 * Note that execution masking for setting up pull constant loads is special:
3212 * the channels that need to be written are unrelated to the current execution
3213 * mask, since a later instruction will use one of the result channels as a
3214 * source operand for all 8 or 16 of its channels.
3217 fs_visitor::lower_uniform_pull_constant_loads()
3219 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3220 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3223 if (devinfo
->gen
>= 7) {
3224 /* The offset arg is a vec4-aligned immediate byte offset. */
3225 fs_reg const_offset_reg
= inst
->src
[1];
3226 assert(const_offset_reg
.file
== IMM
&&
3227 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3228 assert(const_offset_reg
.ud
% 16 == 0);
3230 fs_reg payload
, offset
;
3231 if (devinfo
->gen
>= 9) {
3232 /* We have to use a message header on Skylake to get SIMD4x2
3233 * mode. Reserve space for the register.
3235 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3236 offset
.offset
+= REG_SIZE
;
3239 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3243 /* This is actually going to be a MOV, but since only the first dword
3244 * is accessed, we have a special opcode to do just that one. Note
3245 * that this needs to be an operation that will be considered a def
3246 * by live variable analysis, or register allocation will explode.
3248 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3249 8, offset
, const_offset_reg
);
3250 setup
->force_writemask_all
= true;
3252 setup
->ir
= inst
->ir
;
3253 setup
->annotation
= inst
->annotation
;
3254 inst
->insert_before(block
, setup
);
3256 /* Similarly, this will only populate the first 4 channels of the
3257 * result register (since we only use smear values from 0-3), but we
3258 * don't tell the optimizer.
3260 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3261 inst
->src
[1] = payload
;
3263 invalidate_live_intervals();
3265 /* Before register allocation, we didn't tell the scheduler about the
3266 * MRF we use. We know it's safe to use this MRF because nothing
3267 * else does except for register spill/unspill, which generates and
3268 * uses its MRF within a single IR instruction.
3270 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3277 fs_visitor::lower_load_payload()
3279 bool progress
= false;
3281 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3282 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3285 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3286 assert(inst
->saturate
== false);
3287 fs_reg dst
= inst
->dst
;
3289 /* Get rid of COMPR4. We'll add it back in if we need it */
3290 if (dst
.file
== MRF
)
3291 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3293 const fs_builder
ibld(this, block
, inst
);
3294 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3296 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3297 if (inst
->src
[i
].file
!= BAD_FILE
) {
3298 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3299 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3300 hbld
.MOV(mov_dst
, mov_src
);
3302 dst
= offset(dst
, hbld
, 1);
3305 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3306 inst
->exec_size
> 8) {
3307 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3308 * a straightforward copy. Instead, the result of the
3309 * LOAD_PAYLOAD is treated as interleaved and the first four
3310 * non-header sources are unpacked as:
3321 * This is used for gen <= 5 fb writes.
3323 assert(inst
->exec_size
== 16);
3324 assert(inst
->header_size
+ 4 <= inst
->sources
);
3325 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3326 if (inst
->src
[i
].file
!= BAD_FILE
) {
3327 if (devinfo
->has_compr4
) {
3328 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3329 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3330 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3332 /* Platform doesn't have COMPR4. We have to fake it */
3333 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3334 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3336 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3343 /* The loop above only ever incremented us through the first set
3344 * of 4 registers. However, thanks to the magic of COMPR4, we
3345 * actually wrote to the first 8 registers, so we need to take
3346 * that into account now.
3350 /* The COMPR4 code took care of the first 4 sources. We'll let
3351 * the regular path handle any remaining sources. Yes, we are
3352 * modifying the instruction but we're about to delete it so
3353 * this really doesn't hurt anything.
3355 inst
->header_size
+= 4;
3358 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3359 if (inst
->src
[i
].file
!= BAD_FILE
)
3360 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3361 dst
= offset(dst
, ibld
, 1);
3364 inst
->remove(block
);
3369 invalidate_live_intervals();
3375 fs_visitor::lower_integer_multiplication()
3377 bool progress
= false;
3379 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3380 const fs_builder
ibld(this, block
, inst
);
3382 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3383 if (inst
->dst
.is_accumulator() ||
3384 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3385 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3388 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3389 * operation directly, but CHV/BXT cannot.
3391 if (devinfo
->gen
>= 8 &&
3392 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3395 if (inst
->src
[1].file
== IMM
&&
3396 inst
->src
[1].ud
< (1 << 16)) {
3397 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3398 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3401 * If multiplying by an immediate value that fits in 16-bits, do a
3402 * single MUL instruction with that value in the proper location.
3404 if (devinfo
->gen
< 7) {
3405 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3407 ibld
.MOV(imm
, inst
->src
[1]);
3408 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3410 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3411 ibld
.MUL(inst
->dst
, inst
->src
[0],
3412 ud
? brw_imm_uw(inst
->src
[1].ud
)
3413 : brw_imm_w(inst
->src
[1].d
));
3416 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3417 * do 32-bit integer multiplication in one instruction, but instead
3418 * must do a sequence (which actually calculates a 64-bit result):
3420 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3421 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3422 * mov(8) g2<1>D acc0<8,8,1>D
3424 * But on Gen > 6, the ability to use second accumulator register
3425 * (acc1) for non-float data types was removed, preventing a simple
3426 * implementation in SIMD16. A 16-channel result can be calculated by
3427 * executing the three instructions twice in SIMD8, once with quarter
3428 * control of 1Q for the first eight channels and again with 2Q for
3429 * the second eight channels.
3431 * Which accumulator register is implicitly accessed (by AccWrEnable
3432 * for instance) is determined by the quarter control. Unfortunately
3433 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3434 * implicit accumulator access by an instruction with 2Q will access
3435 * acc1 regardless of whether the data type is usable in acc1.
3437 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3438 * integer data types.
3440 * Since we only want the low 32-bits of the result, we can do two
3441 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3442 * adjust the high result and add them (like the mach is doing):
3444 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3445 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3446 * shl(8) g9<1>D g8<8,8,1>D 16D
3447 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3449 * We avoid the shl instruction by realizing that we only want to add
3450 * the low 16-bits of the "high" result to the high 16-bits of the
3451 * "low" result and using proper regioning on the add:
3453 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3454 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3455 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3457 * Since it does not use the (single) accumulator register, we can
3458 * schedule multi-component multiplications much better.
3461 fs_reg orig_dst
= inst
->dst
;
3462 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3463 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3466 fs_reg low
= inst
->dst
;
3467 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3470 if (devinfo
->gen
>= 7) {
3471 fs_reg src1_0_w
= inst
->src
[1];
3472 fs_reg src1_1_w
= inst
->src
[1];
3474 if (inst
->src
[1].file
== IMM
) {
3475 src1_0_w
.ud
&= 0xffff;
3478 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3479 if (src1_0_w
.stride
!= 0) {
3480 assert(src1_0_w
.stride
== 1);
3481 src1_0_w
.stride
= 2;
3484 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3485 if (src1_1_w
.stride
!= 0) {
3486 assert(src1_1_w
.stride
== 1);
3487 src1_1_w
.stride
= 2;
3489 src1_1_w
.offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3491 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3492 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3494 fs_reg src0_0_w
= inst
->src
[0];
3495 fs_reg src0_1_w
= inst
->src
[0];
3497 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3498 if (src0_0_w
.stride
!= 0) {
3499 assert(src0_0_w
.stride
== 1);
3500 src0_0_w
.stride
= 2;
3503 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3504 if (src0_1_w
.stride
!= 0) {
3505 assert(src0_1_w
.stride
== 1);
3506 src0_1_w
.stride
= 2;
3508 src0_1_w
.offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3510 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3511 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3514 fs_reg dst
= inst
->dst
;
3515 dst
.type
= BRW_REGISTER_TYPE_UW
;
3516 dst
.offset
= ROUND_DOWN_TO(dst
.offset
, REG_SIZE
) + 2;
3519 high
.type
= BRW_REGISTER_TYPE_UW
;
3522 low
.type
= BRW_REGISTER_TYPE_UW
;
3523 low
.offset
= ROUND_DOWN_TO(low
.offset
, REG_SIZE
) + 2;
3526 ibld
.ADD(dst
, low
, high
);
3528 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3529 set_condmod(inst
->conditional_mod
,
3530 ibld
.MOV(orig_dst
, inst
->dst
));
3534 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3535 /* Should have been lowered to 8-wide. */
3536 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
3537 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3539 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3540 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3542 if (devinfo
->gen
>= 8) {
3543 /* Until Gen8, integer multiplies read 32-bits from one source,
3544 * and 16-bits from the other, and relying on the MACH instruction
3545 * to generate the high bits of the result.
3547 * On Gen8, the multiply instruction does a full 32x32-bit
3548 * multiply, but in order to do a 64-bit multiply we can simulate
3549 * the previous behavior and then use a MACH instruction.
3551 * FINISHME: Don't use source modifiers on src1.
3553 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3554 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3555 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3556 mul
->src
[1].stride
*= 2;
3558 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3560 /* Among other things the quarter control bits influence which
3561 * accumulator register is used by the hardware for instructions
3562 * that access the accumulator implicitly (e.g. MACH). A
3563 * second-half instruction would normally map to acc1, which
3564 * doesn't exist on Gen7 and up (the hardware does emulate it for
3565 * floating-point instructions *only* by taking advantage of the
3566 * extra precision of acc0 not normally used for floating point
3569 * HSW and up are careful enough not to try to access an
3570 * accumulator register that doesn't exist, but on earlier Gen7
3571 * hardware we need to make sure that the quarter control bits are
3572 * zero to avoid non-deterministic behaviour and emit an extra MOV
3573 * to get the result masked correctly according to the current
3577 mach
->force_writemask_all
= true;
3578 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3579 ibld
.MOV(inst
->dst
, mach
->dst
);
3585 inst
->remove(block
);
3590 invalidate_live_intervals();
3596 fs_visitor::lower_minmax()
3598 assert(devinfo
->gen
< 6);
3600 bool progress
= false;
3602 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3603 const fs_builder
ibld(this, block
, inst
);
3605 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3606 inst
->predicate
== BRW_PREDICATE_NONE
) {
3607 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3608 * the original SEL.L/GE instruction
3610 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3611 inst
->conditional_mod
);
3612 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3613 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3620 invalidate_live_intervals();
3626 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3627 fs_reg
*dst
, fs_reg color
, unsigned components
)
3629 if (key
->clamp_fragment_color
) {
3630 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3631 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3633 for (unsigned i
= 0; i
< components
; i
++)
3635 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3640 for (unsigned i
= 0; i
< components
; i
++)
3641 dst
[i
] = offset(color
, bld
, i
);
3645 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3646 const brw_wm_prog_data
*prog_data
,
3647 const brw_wm_prog_key
*key
,
3648 const fs_visitor::thread_payload
&payload
)
3650 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3651 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3652 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3653 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3654 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3655 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3656 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3657 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3658 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3659 const unsigned components
=
3660 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3662 /* We can potentially have a message length of up to 15, so we have to set
3663 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3666 int header_size
= 2, payload_header_size
;
3667 unsigned length
= 0;
3669 /* From the Sandy Bridge PRM, volume 4, page 198:
3671 * "Dispatched Pixel Enables. One bit per pixel indicating
3672 * which pixels were originally enabled when the thread was
3673 * dispatched. This field is only required for the end-of-
3674 * thread message and on all dual-source messages."
3676 if (devinfo
->gen
>= 6 &&
3677 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3678 color1
.file
== BAD_FILE
&&
3679 key
->nr_color_regions
== 1) {
3683 if (header_size
!= 0) {
3684 assert(header_size
== 2);
3685 /* Allocate 2 registers for a header */
3689 if (payload
.aa_dest_stencil_reg
) {
3690 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3691 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3692 .MOV(sources
[length
],
3693 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3697 if (sample_mask
.file
!= BAD_FILE
) {
3698 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3699 BRW_REGISTER_TYPE_UD
);
3701 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3702 * relevant. Since it's unsigned single words one vgrf is always
3703 * 16-wide, but only the lower or higher 8 channels will be used by the
3704 * hardware when doing a SIMD8 write depending on whether we have
3705 * selected the subspans for the first or second half respectively.
3707 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3708 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3709 sample_mask
.stride
*= 2;
3711 bld
.exec_all().annotate("FB write oMask")
3712 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3718 payload_header_size
= length
;
3720 if (src0_alpha
.file
!= BAD_FILE
) {
3721 /* FIXME: This is being passed at the wrong location in the payload and
3722 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3723 * It's supposed to be immediately before oMask but there seems to be no
3724 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3725 * requires header sources to form a contiguous segment at the beginning
3726 * of the message and src0_alpha has per-channel semantics.
3728 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3732 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3735 if (color1
.file
!= BAD_FILE
) {
3736 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3740 if (src_depth
.file
!= BAD_FILE
) {
3741 sources
[length
] = src_depth
;
3745 if (dst_depth
.file
!= BAD_FILE
) {
3746 sources
[length
] = dst_depth
;
3750 if (src_stencil
.file
!= BAD_FILE
) {
3751 assert(devinfo
->gen
>= 9);
3752 assert(bld
.dispatch_width() != 16);
3754 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3755 * available on gen9+. As such it's impossible to have both enabled at the
3756 * same time and therefore length cannot overrun the array.
3758 assert(length
< 15);
3760 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3761 bld
.exec_all().annotate("FB write OS")
3762 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
3763 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
3768 if (devinfo
->gen
>= 7) {
3769 /* Send from the GRF */
3770 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3771 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3772 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
3773 load
->dst
= payload
;
3775 inst
->src
[0] = payload
;
3776 inst
->resize_sources(1);
3778 /* Send from the MRF */
3779 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3780 sources
, length
, payload_header_size
);
3782 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3783 * will do this for us if we just give it a COMPR4 destination.
3785 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3786 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3788 inst
->resize_sources(0);
3792 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3793 inst
->mlen
= regs_written(load
);
3794 inst
->header_size
= header_size
;
3798 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
3800 const fs_builder
&ubld
= bld
.exec_all();
3801 const unsigned length
= 2;
3802 const fs_reg header
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
, length
);
3805 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3807 inst
->resize_sources(1);
3808 inst
->src
[0] = header
;
3809 inst
->opcode
= FS_OPCODE_FB_READ
;
3810 inst
->mlen
= length
;
3811 inst
->header_size
= length
;
3815 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3816 const fs_reg
&coordinate
,
3817 const fs_reg
&shadow_c
,
3818 const fs_reg
&lod
, const fs_reg
&lod2
,
3819 const fs_reg
&surface
,
3820 const fs_reg
&sampler
,
3821 unsigned coord_components
,
3822 unsigned grad_components
)
3824 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3825 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3826 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3827 fs_reg msg_end
= msg_begin
;
3830 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3832 for (unsigned i
= 0; i
< coord_components
; i
++)
3833 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3834 offset(coordinate
, bld
, i
));
3836 msg_end
= offset(msg_end
, bld
, coord_components
);
3838 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3839 * require all three components to be present and zero if they are unused.
3841 if (coord_components
> 0 &&
3842 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3843 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3844 for (unsigned i
= coord_components
; i
< 3; i
++)
3845 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3847 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3850 if (op
== SHADER_OPCODE_TXD
) {
3851 /* TXD unsupported in SIMD16 mode. */
3852 assert(bld
.dispatch_width() == 8);
3854 /* the slots for u and v are always present, but r is optional */
3855 if (coord_components
< 2)
3856 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3859 * dPdx = dudx, dvdx, drdx
3860 * dPdy = dudy, dvdy, drdy
3862 * 1-arg: Does not exist.
3864 * 2-arg: dudx dvdx dudy dvdy
3865 * dPdx.x dPdx.y dPdy.x dPdy.y
3868 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3869 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3870 * m5 m6 m7 m8 m9 m10
3872 for (unsigned i
= 0; i
< grad_components
; i
++)
3873 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3875 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3877 for (unsigned i
= 0; i
< grad_components
; i
++)
3878 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3880 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3884 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3885 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3887 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3888 bld
.dispatch_width() == 16);
3890 const brw_reg_type type
=
3891 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3892 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3893 bld
.MOV(retype(msg_end
, type
), lod
);
3894 msg_end
= offset(msg_end
, bld
, 1);
3897 if (shadow_c
.file
!= BAD_FILE
) {
3898 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3899 /* There's no plain shadow compare message, so we use shadow
3900 * compare with a bias of 0.0.
3902 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3903 msg_end
= offset(msg_end
, bld
, 1);
3906 bld
.MOV(msg_end
, shadow_c
);
3907 msg_end
= offset(msg_end
, bld
, 1);
3911 inst
->src
[0] = reg_undef
;
3912 inst
->src
[1] = surface
;
3913 inst
->src
[2] = sampler
;
3914 inst
->resize_sources(3);
3915 inst
->base_mrf
= msg_begin
.nr
;
3916 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3917 inst
->header_size
= 1;
3921 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3922 const fs_reg
&coordinate
,
3923 const fs_reg
&shadow_c
,
3924 const fs_reg
&lod
, const fs_reg
&lod2
,
3925 const fs_reg
&sample_index
,
3926 const fs_reg
&surface
,
3927 const fs_reg
&sampler
,
3928 const fs_reg
&offset_value
,
3929 unsigned coord_components
,
3930 unsigned grad_components
)
3932 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3933 fs_reg msg_coords
= message
;
3934 unsigned header_size
= 0;
3936 if (offset_value
.file
!= BAD_FILE
) {
3937 /* The offsets set up by the visitor are in the m1 header, so we can't
3944 for (unsigned i
= 0; i
< coord_components
; i
++)
3945 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
3946 offset(coordinate
, bld
, i
));
3948 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3949 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3951 if (shadow_c
.file
!= BAD_FILE
) {
3952 fs_reg msg_shadow
= msg_lod
;
3953 bld
.MOV(msg_shadow
, shadow_c
);
3954 msg_lod
= offset(msg_shadow
, bld
, 1);
3959 case SHADER_OPCODE_TXL
:
3961 bld
.MOV(msg_lod
, lod
);
3962 msg_end
= offset(msg_lod
, bld
, 1);
3964 case SHADER_OPCODE_TXD
:
3967 * dPdx = dudx, dvdx, drdx
3968 * dPdy = dudy, dvdy, drdy
3970 * Load up these values:
3971 * - dudx dudy dvdx dvdy drdx drdy
3972 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3975 for (unsigned i
= 0; i
< grad_components
; i
++) {
3976 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
3977 msg_end
= offset(msg_end
, bld
, 1);
3979 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
3980 msg_end
= offset(msg_end
, bld
, 1);
3983 case SHADER_OPCODE_TXS
:
3984 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3985 bld
.MOV(msg_lod
, lod
);
3986 msg_end
= offset(msg_lod
, bld
, 1);
3988 case SHADER_OPCODE_TXF
:
3989 msg_lod
= offset(msg_coords
, bld
, 3);
3990 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3991 msg_end
= offset(msg_lod
, bld
, 1);
3993 case SHADER_OPCODE_TXF_CMS
:
3994 msg_lod
= offset(msg_coords
, bld
, 3);
3996 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
3998 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3999 msg_end
= offset(msg_lod
, bld
, 2);
4006 inst
->src
[0] = reg_undef
;
4007 inst
->src
[1] = surface
;
4008 inst
->src
[2] = sampler
;
4009 inst
->resize_sources(3);
4010 inst
->base_mrf
= message
.nr
;
4011 inst
->mlen
= msg_end
.nr
- message
.nr
;
4012 inst
->header_size
= header_size
;
4014 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4015 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4019 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
4021 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4024 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4028 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4029 const fs_reg
&coordinate
,
4030 const fs_reg
&shadow_c
,
4031 fs_reg lod
, const fs_reg
&lod2
,
4032 const fs_reg
&sample_index
,
4034 const fs_reg
&surface
,
4035 const fs_reg
&sampler
,
4036 const fs_reg
&offset_value
,
4037 unsigned coord_components
,
4038 unsigned grad_components
)
4040 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4041 unsigned reg_width
= bld
.dispatch_width() / 8;
4042 unsigned header_size
= 0, length
= 0;
4043 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4044 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4045 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4047 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4048 offset_value
.file
!= BAD_FILE
|| inst
->eot
||
4049 op
== SHADER_OPCODE_SAMPLEINFO
||
4050 is_high_sampler(devinfo
, sampler
)) {
4051 /* For general texture offsets (no txf workaround), we need a header to
4052 * put them in. Note that we're only reserving space for it in the
4053 * message payload as it will be initialized implicitly by the
4056 * TG4 needs to place its channel select in the header, for interaction
4057 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4058 * larger sampler numbers we need to offset the Sampler State Pointer in
4062 sources
[0] = fs_reg();
4065 /* If we're requesting fewer than four channels worth of response,
4066 * and we have an explicit header, we need to set up the sampler
4067 * writemask. It's reversed from normal: 1 means "don't write".
4069 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4070 assert(regs_written(inst
) % reg_width
== 0);
4071 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4072 inst
->offset
|= mask
<< 12;
4076 if (shadow_c
.file
!= BAD_FILE
) {
4077 bld
.MOV(sources
[length
], shadow_c
);
4081 bool coordinate_done
= false;
4083 /* Set up the LOD info */
4086 case SHADER_OPCODE_TXL
:
4087 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4088 op
= SHADER_OPCODE_TXL_LZ
;
4091 bld
.MOV(sources
[length
], lod
);
4094 case SHADER_OPCODE_TXD
:
4095 /* TXD should have been lowered in SIMD16 mode. */
4096 assert(bld
.dispatch_width() == 8);
4098 /* Load dPdx and the coordinate together:
4099 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4101 for (unsigned i
= 0; i
< coord_components
; i
++) {
4102 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4104 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4105 * only derivatives for (u, v, r).
4107 if (i
< grad_components
) {
4108 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4109 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4113 coordinate_done
= true;
4115 case SHADER_OPCODE_TXS
:
4116 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4119 case SHADER_OPCODE_TXF
:
4120 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4121 * On Gen9 they are u, v, lod, r
4123 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4125 if (devinfo
->gen
>= 9) {
4126 if (coord_components
>= 2) {
4127 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4128 offset(coordinate
, bld
, 1));
4130 sources
[length
] = brw_imm_d(0);
4135 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4136 op
= SHADER_OPCODE_TXF_LZ
;
4138 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4142 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4143 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4144 offset(coordinate
, bld
, i
));
4146 coordinate_done
= true;
4149 case SHADER_OPCODE_TXF_CMS
:
4150 case SHADER_OPCODE_TXF_CMS_W
:
4151 case SHADER_OPCODE_TXF_UMS
:
4152 case SHADER_OPCODE_TXF_MCS
:
4153 if (op
== SHADER_OPCODE_TXF_UMS
||
4154 op
== SHADER_OPCODE_TXF_CMS
||
4155 op
== SHADER_OPCODE_TXF_CMS_W
) {
4156 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4160 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4161 /* Data from the multisample control surface. */
4162 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4165 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4168 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4169 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4172 offset(mcs
, bld
, 1));
4177 /* There is no offsetting for this message; just copy in the integer
4178 * texture coordinates.
4180 for (unsigned i
= 0; i
< coord_components
; i
++)
4181 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4182 offset(coordinate
, bld
, i
));
4184 coordinate_done
= true;
4186 case SHADER_OPCODE_TG4_OFFSET
:
4187 /* More crazy intermixing */
4188 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4189 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4191 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4192 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4193 offset(offset_value
, bld
, i
));
4195 if (coord_components
== 3) /* r if present */
4196 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4198 coordinate_done
= true;
4204 /* Set up the coordinate (except for cases where it was done above) */
4205 if (!coordinate_done
) {
4206 for (unsigned i
= 0; i
< coord_components
; i
++)
4207 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4212 mlen
= length
* reg_width
- header_size
;
4214 mlen
= length
* reg_width
;
4216 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4217 BRW_REGISTER_TYPE_F
);
4218 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4220 /* Generate the SEND. */
4222 inst
->src
[0] = src_payload
;
4223 inst
->src
[1] = surface
;
4224 inst
->src
[2] = sampler
;
4225 inst
->resize_sources(3);
4227 inst
->header_size
= header_size
;
4229 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4230 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4234 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4236 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4237 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4238 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4239 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4240 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4241 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4242 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4243 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4244 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4245 const fs_reg
&offset_value
= inst
->src
[TEX_LOGICAL_SRC_OFFSET_VALUE
];
4246 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4247 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4248 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4249 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4251 if (devinfo
->gen
>= 7) {
4252 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4253 shadow_c
, lod
, lod2
, sample_index
,
4254 mcs
, surface
, sampler
, offset_value
,
4255 coord_components
, grad_components
);
4256 } else if (devinfo
->gen
>= 5) {
4257 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4258 shadow_c
, lod
, lod2
, sample_index
,
4259 surface
, sampler
, offset_value
,
4260 coord_components
, grad_components
);
4262 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4263 shadow_c
, lod
, lod2
,
4265 coord_components
, grad_components
);
4270 * Initialize the header present in some typed and untyped surface
4274 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4276 fs_builder ubld
= bld
.exec_all().group(8, 0);
4277 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4278 ubld
.MOV(dst
, brw_imm_d(0));
4279 ubld
.MOV(component(dst
, 7), sample_mask
);
4284 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4285 const fs_reg
&sample_mask
)
4287 /* Get the logical send arguments. */
4288 const fs_reg
&addr
= inst
->src
[0];
4289 const fs_reg
&src
= inst
->src
[1];
4290 const fs_reg
&surface
= inst
->src
[2];
4291 const UNUSED fs_reg
&dims
= inst
->src
[3];
4292 const fs_reg
&arg
= inst
->src
[4];
4294 /* Calculate the total number of components of the payload. */
4295 const unsigned addr_sz
= inst
->components_read(0);
4296 const unsigned src_sz
= inst
->components_read(1);
4297 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4298 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4300 /* Allocate space for the payload. */
4301 fs_reg
*const components
= new fs_reg
[sz
];
4302 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4305 /* Construct the payload. */
4307 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4309 for (unsigned i
= 0; i
< addr_sz
; i
++)
4310 components
[n
++] = offset(addr
, bld
, i
);
4312 for (unsigned i
= 0; i
< src_sz
; i
++)
4313 components
[n
++] = offset(src
, bld
, i
);
4315 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4317 /* Update the original instruction. */
4319 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4320 inst
->header_size
= header_sz
;
4322 inst
->src
[0] = payload
;
4323 inst
->src
[1] = surface
;
4325 inst
->resize_sources(3);
4327 delete[] components
;
4331 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4333 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4335 if (devinfo
->gen
>= 7) {
4336 /* We are switching the instruction from an ALU-like instruction to a
4337 * send-from-grf instruction. Since sends can't handle strides or
4338 * source modifiers, we have to make a copy of the offset source.
4340 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4341 bld
.MOV(tmp
, inst
->src
[1]);
4344 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4347 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4348 BRW_REGISTER_TYPE_UD
);
4350 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4352 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4353 inst
->resize_sources(1);
4354 inst
->base_mrf
= payload
.nr
;
4355 inst
->header_size
= 1;
4356 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4361 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4363 assert(bld
.shader
->devinfo
->gen
< 6);
4366 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4368 if (inst
->sources
> 1) {
4369 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4370 * "Message Payload":
4372 * "Operand0[7]. For the INT DIV functions, this operand is the
4375 * "Operand1[7]. For the INT DIV functions, this operand is the
4378 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4379 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4380 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4382 inst
->resize_sources(1);
4383 inst
->src
[0] = src0
;
4385 assert(inst
->exec_size
== 8);
4386 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4391 fs_visitor::lower_logical_sends()
4393 bool progress
= false;
4395 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4396 const fs_builder
ibld(this, block
, inst
);
4398 switch (inst
->opcode
) {
4399 case FS_OPCODE_FB_WRITE_LOGICAL
:
4400 assert(stage
== MESA_SHADER_FRAGMENT
);
4401 lower_fb_write_logical_send(ibld
, inst
,
4402 (const brw_wm_prog_data
*)prog_data
,
4403 (const brw_wm_prog_key
*)key
,
4407 case FS_OPCODE_FB_READ_LOGICAL
:
4408 lower_fb_read_logical_send(ibld
, inst
);
4411 case SHADER_OPCODE_TEX_LOGICAL
:
4412 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4415 case SHADER_OPCODE_TXD_LOGICAL
:
4416 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4419 case SHADER_OPCODE_TXF_LOGICAL
:
4420 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4423 case SHADER_OPCODE_TXL_LOGICAL
:
4424 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4427 case SHADER_OPCODE_TXS_LOGICAL
:
4428 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4431 case FS_OPCODE_TXB_LOGICAL
:
4432 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4435 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4436 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4439 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4440 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4443 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4444 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4447 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4448 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4451 case SHADER_OPCODE_LOD_LOGICAL
:
4452 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4455 case SHADER_OPCODE_TG4_LOGICAL
:
4456 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4459 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4460 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4463 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4464 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
4467 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4468 lower_surface_logical_send(ibld
, inst
,
4469 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4473 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4474 lower_surface_logical_send(ibld
, inst
,
4475 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4476 ibld
.sample_mask_reg());
4479 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4480 lower_surface_logical_send(ibld
, inst
,
4481 SHADER_OPCODE_UNTYPED_ATOMIC
,
4482 ibld
.sample_mask_reg());
4485 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4486 lower_surface_logical_send(ibld
, inst
,
4487 SHADER_OPCODE_TYPED_SURFACE_READ
,
4491 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4492 lower_surface_logical_send(ibld
, inst
,
4493 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4494 ibld
.sample_mask_reg());
4497 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4498 lower_surface_logical_send(ibld
, inst
,
4499 SHADER_OPCODE_TYPED_ATOMIC
,
4500 ibld
.sample_mask_reg());
4503 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4504 lower_varying_pull_constant_logical_send(ibld
, inst
);
4507 case SHADER_OPCODE_RCP
:
4508 case SHADER_OPCODE_RSQ
:
4509 case SHADER_OPCODE_SQRT
:
4510 case SHADER_OPCODE_EXP2
:
4511 case SHADER_OPCODE_LOG2
:
4512 case SHADER_OPCODE_SIN
:
4513 case SHADER_OPCODE_COS
:
4514 case SHADER_OPCODE_POW
:
4515 case SHADER_OPCODE_INT_QUOTIENT
:
4516 case SHADER_OPCODE_INT_REMAINDER
:
4517 /* The math opcodes are overloaded for the send-like and
4518 * expression-like instructions which seems kind of icky. Gen6+ has
4519 * a native (but rather quirky) MATH instruction so we don't need to
4520 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
4521 * logical instructions (which we can easily recognize because they
4522 * have mlen = 0) into send-like virtual instructions.
4524 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
4525 lower_math_logical_send(ibld
, inst
);
4540 invalidate_live_intervals();
4546 * Get the closest allowed SIMD width for instruction \p inst accounting for
4547 * some common regioning and execution control restrictions that apply to FPU
4548 * instructions. These restrictions don't necessarily have any relevance to
4549 * instructions not executed by the FPU pipeline like extended math, control
4550 * flow or send message instructions.
4552 * For virtual opcodes it's really up to the instruction -- In some cases
4553 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
4554 * instructions) it may simplify virtual instruction lowering if we can
4555 * enforce FPU-like regioning restrictions already on the virtual instruction,
4556 * in other cases (e.g. virtual send-like instructions) this may be
4557 * excessively restrictive.
4560 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
4561 const fs_inst
*inst
)
4563 /* Maximum execution size representable in the instruction controls. */
4564 unsigned max_width
= MIN2(32, inst
->exec_size
);
4566 /* According to the PRMs:
4567 * "A. In Direct Addressing mode, a source cannot span more than 2
4568 * adjacent GRF registers.
4569 * B. A destination cannot span more than 2 adjacent GRF registers."
4571 * Look for the source or destination with the largest register region
4572 * which is the one that is going to limit the overall execution size of
4573 * the instruction due to this rule.
4575 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4577 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4578 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
4580 /* Calculate the maximum execution size of the instruction based on the
4581 * factor by which it goes over the hardware limit of 2 GRFs.
4584 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
4586 /* According to the IVB PRMs:
4587 * "When destination spans two registers, the source MUST span two
4588 * registers. The exception to the above rule:
4590 * - When source is scalar, the source registers are not incremented.
4591 * - When source is packed integer Word and destination is packed
4592 * integer DWord, the source register is not incremented but the
4593 * source sub register is incremented."
4595 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
4596 * restrictions. The code below intentionally doesn't check whether the
4597 * destination type is integer because empirically the hardware doesn't
4598 * seem to care what the actual type is as long as it's dword-aligned.
4600 if (devinfo
->gen
< 8) {
4601 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
4602 if (DIV_ROUND_UP(inst
->size_written
, REG_SIZE
) == 2 &&
4603 inst
->size_read(i
) != 0 && DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
) != 2 &&
4604 !is_uniform(inst
->src
[i
]) &&
4605 !(type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
4606 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1)) {
4607 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4608 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4613 /* From the IVB PRMs:
4614 * "When an instruction is SIMD32, the low 16 bits of the execution mask
4615 * are applied for both halves of the SIMD32 instruction. If different
4616 * execution mask channels are required, split the instruction into two
4617 * SIMD16 instructions."
4619 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
4620 * 32-wide control flow support in hardware and will behave similarly.
4622 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
4623 max_width
= MIN2(max_width
, 16);
4625 /* From the IVB PRMs (applies to HSW too):
4626 * "Instructions with condition modifiers must not use SIMD32."
4628 * From the BDW PRMs (applies to later hardware too):
4629 * "Ternary instruction with condition modifiers must not use SIMD32."
4631 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
4632 max_width
= MIN2(max_width
, 16);
4634 /* From the IVB PRMs (applies to other devices that don't have the
4635 * gen_device_info::supports_simd16_3src flag set):
4636 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
4637 * SIMD8 is not allowed for DF operations."
4639 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
4640 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4642 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
4643 * the 8-bit quarter of the execution mask signals specified in the
4644 * instruction control fields) for the second compressed half of any
4645 * single-precision instruction (for double-precision instructions
4646 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
4647 * the EU will apply the wrong execution controls for the second
4648 * sequential GRF write if the number of channels per GRF is not exactly
4649 * eight in single-precision mode (or four in double-float mode).
4651 * In this situation we calculate the maximum size of the split
4652 * instructions so they only ever write to a single register.
4654 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
4655 !inst
->force_writemask_all
) {
4656 const unsigned channels_per_grf
= inst
->exec_size
/
4657 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4658 unsigned exec_type_size
= 0;
4659 for (int i
= 0; i
< inst
->sources
; i
++) {
4660 if (inst
->src
[i
].file
!= BAD_FILE
)
4661 exec_type_size
= MAX2(exec_type_size
, type_sz(inst
->src
[i
].type
));
4663 assert(exec_type_size
);
4665 /* The hardware shifts exactly 8 channels per compressed half of the
4666 * instruction in single-precision mode and exactly 4 in double-precision.
4668 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
4669 max_width
= MIN2(max_width
, channels_per_grf
);
4672 /* Only power-of-two execution sizes are representable in the instruction
4675 return 1 << _mesa_logbase2(max_width
);
4679 * Get the maximum allowed SIMD width for instruction \p inst accounting for
4680 * various payload size restrictions that apply to sampler message
4683 * This is only intended to provide a maximum theoretical bound for the
4684 * execution size of the message based on the number of argument components
4685 * alone, which in most cases will determine whether the SIMD8 or SIMD16
4686 * variant of the message can be used, though some messages may have
4687 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
4688 * the message length to determine the exact SIMD width and argument count,
4689 * which makes a number of sampler message combinations impossible to
4693 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
4694 const fs_inst
*inst
)
4696 /* Calculate the number of coordinate components that have to be present
4697 * assuming that additional arguments follow the texel coordinates in the
4698 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
4699 * need to pad to four or three components depending on the message,
4700 * pre-ILK we need to pad to at most three components.
4702 const unsigned req_coord_components
=
4703 (devinfo
->gen
>= 7 ||
4704 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
4705 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
4706 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
4709 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
4710 * variant of the TXL or TXF message.
4712 const bool implicit_lod
= devinfo
->gen
>= 9 &&
4713 (inst
->opcode
== SHADER_OPCODE_TXL
||
4714 inst
->opcode
== SHADER_OPCODE_TXF
) &&
4715 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
4717 /* Calculate the total number of argument components that need to be passed
4718 * to the sampler unit.
4720 const unsigned num_payload_components
=
4721 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
4722 req_coord_components
) +
4723 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
4724 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
4725 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
4726 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
4727 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
4728 inst
->components_read(TEX_LOGICAL_SRC_OFFSET_VALUE
) : 0) +
4729 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
4731 /* SIMD16 messages with more than five arguments exceed the maximum message
4732 * size supported by the sampler, regardless of whether a header is
4735 return MIN2(inst
->exec_size
,
4736 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
4740 * Get the closest native SIMD width supported by the hardware for instruction
4741 * \p inst. The instruction will be left untouched by
4742 * fs_visitor::lower_simd_width() if the returned value is equal to the
4743 * original execution size.
4746 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
4747 const fs_inst
*inst
)
4749 switch (inst
->opcode
) {
4750 case BRW_OPCODE_MOV
:
4751 case BRW_OPCODE_SEL
:
4752 case BRW_OPCODE_NOT
:
4753 case BRW_OPCODE_AND
:
4755 case BRW_OPCODE_XOR
:
4756 case BRW_OPCODE_SHR
:
4757 case BRW_OPCODE_SHL
:
4758 case BRW_OPCODE_ASR
:
4759 case BRW_OPCODE_CMPN
:
4760 case BRW_OPCODE_CSEL
:
4761 case BRW_OPCODE_F32TO16
:
4762 case BRW_OPCODE_F16TO32
:
4763 case BRW_OPCODE_BFREV
:
4764 case BRW_OPCODE_BFE
:
4765 case BRW_OPCODE_ADD
:
4766 case BRW_OPCODE_MUL
:
4767 case BRW_OPCODE_AVG
:
4768 case BRW_OPCODE_FRC
:
4769 case BRW_OPCODE_RNDU
:
4770 case BRW_OPCODE_RNDD
:
4771 case BRW_OPCODE_RNDE
:
4772 case BRW_OPCODE_RNDZ
:
4773 case BRW_OPCODE_LZD
:
4774 case BRW_OPCODE_FBH
:
4775 case BRW_OPCODE_FBL
:
4776 case BRW_OPCODE_CBIT
:
4777 case BRW_OPCODE_SAD2
:
4778 case BRW_OPCODE_MAD
:
4779 case BRW_OPCODE_LRP
:
4780 case FS_OPCODE_PACK
:
4781 return get_fpu_lowered_simd_width(devinfo
, inst
);
4783 case BRW_OPCODE_CMP
: {
4784 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
4785 * when the destination is a GRF the dependency-clear bit on the flag
4786 * register is cleared early.
4788 * Suggested workarounds are to disable coissuing CMP instructions
4789 * or to split CMP(16) instructions into two CMP(8) instructions.
4791 * We choose to split into CMP(8) instructions since disabling
4792 * coissuing would affect CMP instructions not otherwise affected by
4795 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4796 !inst
->dst
.is_null() ? 8 : ~0);
4797 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
4799 case BRW_OPCODE_BFI1
:
4800 case BRW_OPCODE_BFI2
:
4801 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
4803 * "Force BFI instructions to be executed always in SIMD8."
4805 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
4806 get_fpu_lowered_simd_width(devinfo
, inst
));
4809 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
4810 return inst
->exec_size
;
4812 case SHADER_OPCODE_RCP
:
4813 case SHADER_OPCODE_RSQ
:
4814 case SHADER_OPCODE_SQRT
:
4815 case SHADER_OPCODE_EXP2
:
4816 case SHADER_OPCODE_LOG2
:
4817 case SHADER_OPCODE_SIN
:
4818 case SHADER_OPCODE_COS
:
4819 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
4822 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4823 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
4824 MIN2(8, inst
->exec_size
));
4826 case SHADER_OPCODE_POW
:
4827 /* SIMD16 is only allowed on Gen7+. */
4828 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4829 MIN2(8, inst
->exec_size
));
4831 case SHADER_OPCODE_INT_QUOTIENT
:
4832 case SHADER_OPCODE_INT_REMAINDER
:
4833 /* Integer division is limited to SIMD8 on all generations. */
4834 return MIN2(8, inst
->exec_size
);
4836 case FS_OPCODE_LINTERP
:
4837 case FS_OPCODE_GET_BUFFER_SIZE
:
4838 case FS_OPCODE_DDX_COARSE
:
4839 case FS_OPCODE_DDX_FINE
:
4840 case FS_OPCODE_DDY_COARSE
:
4841 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
4842 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
4843 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
4844 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
4845 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
4846 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
4847 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
4848 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
4849 return MIN2(16, inst
->exec_size
);
4851 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4852 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
4853 * message used to implement varying pull constant loads, so expand it
4854 * to SIMD16. An alternative with longer message payload length but
4855 * shorter return payload would be to use the SIMD8 sampler message that
4856 * takes (header, u, v, r) as parameters instead of (header, u).
4858 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
4860 case FS_OPCODE_DDY_FINE
:
4861 /* The implementation of this virtual opcode may require emitting
4862 * compressed Align16 instructions, which are severely limited on some
4865 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
4866 * Region Restrictions):
4868 * "In Align16 access mode, SIMD16 is not allowed for DW operations
4869 * and SIMD8 is not allowed for DF operations."
4871 * In this context, "DW operations" means "operations acting on 32-bit
4872 * values", so it includes operations on floats.
4874 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
4875 * (Instruction Compression -> Rules and Restrictions):
4877 * "A compressed instruction must be in Align1 access mode. Align16
4878 * mode instructions cannot be compressed."
4880 * Similar text exists in the g45 PRM.
4882 * Empirically, compressed align16 instructions using odd register
4883 * numbers don't appear to work on Sandybridge either.
4885 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
4886 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
4887 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
4889 case SHADER_OPCODE_MULH
:
4890 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4891 * is 8-wide on Gen7+.
4893 return (devinfo
->gen
>= 7 ? 8 :
4894 get_fpu_lowered_simd_width(devinfo
, inst
));
4896 case FS_OPCODE_FB_WRITE_LOGICAL
:
4897 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4900 assert(devinfo
->gen
!= 6 ||
4901 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4902 inst
->exec_size
== 8);
4903 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4904 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4905 8 : MIN2(16, inst
->exec_size
));
4907 case FS_OPCODE_FB_READ_LOGICAL
:
4908 return MIN2(16, inst
->exec_size
);
4910 case SHADER_OPCODE_TEX_LOGICAL
:
4911 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4912 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4913 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4914 case SHADER_OPCODE_LOD_LOGICAL
:
4915 case SHADER_OPCODE_TG4_LOGICAL
:
4916 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4917 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4918 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4919 return get_sampler_lowered_simd_width(devinfo
, inst
);
4921 case SHADER_OPCODE_TXD_LOGICAL
:
4922 /* TXD is unsupported in SIMD16 mode. */
4925 case SHADER_OPCODE_TXL_LOGICAL
:
4926 case FS_OPCODE_TXB_LOGICAL
:
4927 /* Only one execution size is representable pre-ILK depending on whether
4928 * the shadow reference argument is present.
4930 if (devinfo
->gen
== 4)
4931 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
4933 return get_sampler_lowered_simd_width(devinfo
, inst
);
4935 case SHADER_OPCODE_TXF_LOGICAL
:
4936 case SHADER_OPCODE_TXS_LOGICAL
:
4937 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4938 * messages. Use SIMD16 instead.
4940 if (devinfo
->gen
== 4)
4943 return get_sampler_lowered_simd_width(devinfo
, inst
);
4945 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4946 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4947 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4950 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4951 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4952 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4953 return MIN2(16, inst
->exec_size
);
4955 case SHADER_OPCODE_URB_READ_SIMD8
:
4956 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
4957 case SHADER_OPCODE_URB_WRITE_SIMD8
:
4958 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
4959 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
4960 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
4961 return MIN2(8, inst
->exec_size
);
4963 case SHADER_OPCODE_MOV_INDIRECT
:
4964 /* Prior to Broadwell, we only have 8 address subregisters */
4965 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
4966 2 * REG_SIZE
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
4969 case SHADER_OPCODE_LOAD_PAYLOAD
: {
4970 const unsigned reg_count
=
4971 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
4973 if (reg_count
> 2) {
4974 /* Only LOAD_PAYLOAD instructions with per-channel destination region
4975 * can be easily lowered (which excludes headers and heterogeneous
4978 assert(!inst
->header_size
);
4979 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4980 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
4981 inst
->src
[i
].file
== BAD_FILE
);
4983 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4985 return inst
->exec_size
;
4989 return inst
->exec_size
;
4994 * Return true if splitting out the group of channels of instruction \p inst
4995 * given by lbld.group() requires allocating a temporary for the i-th source
4996 * of the lowered instruction.
4999 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
5001 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
5002 (inst
->components_read(i
) == 1 &&
5003 lbld
.dispatch_width() <= inst
->exec_size
));
5007 * Extract the data that would be consumed by the channel group given by
5008 * lbld.group() from the i-th source region of instruction \p inst and return
5009 * it as result in packed form. If any copy instructions are required they
5010 * will be emitted before the given \p inst in \p block.
5013 emit_unzip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
,
5016 /* Specified channel group from the source region. */
5017 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group());
5019 if (needs_src_copy(lbld
, inst
, i
)) {
5020 /* Builder of the right width to perform the copy avoiding uninitialized
5021 * data if the lowered execution size is greater than the original
5022 * execution size of the instruction.
5024 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5025 inst
->exec_size
), 0);
5026 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
5028 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
5029 cbld
.at(block
, inst
)
5030 .MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
5034 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
5035 /* The source is invariant for all dispatch_width-wide groups of the
5038 return inst
->src
[i
];
5041 /* We can just point the lowered instruction at the right channel group
5042 * from the original region.
5049 * Return true if splitting out the group of channels of instruction \p inst
5050 * given by lbld.group() requires allocating a temporary for the destination
5051 * of the lowered instruction and copying the data back to the original
5052 * destination region.
5055 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
5057 /* If the instruction writes more than one component we'll have to shuffle
5058 * the results of multiple lowered instructions in order to make sure that
5059 * they end up arranged correctly in the original destination region.
5061 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
5064 /* If the lowered execution size is larger than the original the result of
5065 * the instruction won't fit in the original destination, so we'll have to
5066 * allocate a temporary in any case.
5068 if (lbld
.dispatch_width() > inst
->exec_size
)
5071 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5072 /* If we already made a copy of the source for other reasons there won't
5073 * be any overlap with the destination.
5075 if (needs_src_copy(lbld
, inst
, i
))
5078 /* In order to keep the logic simple we emit a copy whenever the
5079 * destination region doesn't exactly match an overlapping source, which
5080 * may point at the source and destination not being aligned group by
5081 * group which could cause one of the lowered instructions to overwrite
5082 * the data read from the same source by other lowered instructions.
5084 if (regions_overlap(inst
->dst
, inst
->size_written
,
5085 inst
->src
[i
], inst
->size_read(i
)) &&
5086 !inst
->dst
.equals(inst
->src
[i
]))
5094 * Insert data from a packed temporary into the channel group given by
5095 * lbld.group() of the destination region of instruction \p inst and return
5096 * the temporary as result. If any copy instructions are required they will
5097 * be emitted around the given \p inst in \p block.
5100 emit_zip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
)
5102 /* Builder of the right width to perform the copy avoiding uninitialized
5103 * data if the lowered execution size is greater than the original
5104 * execution size of the instruction.
5106 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5107 inst
->exec_size
), 0);
5109 /* Specified channel group from the destination region. */
5110 const fs_reg dst
= horiz_offset(inst
->dst
, lbld
.group());
5111 const unsigned dst_size
= inst
->size_written
/
5112 inst
->dst
.component_size(inst
->exec_size
);
5114 if (needs_dst_copy(lbld
, inst
)) {
5115 const fs_reg tmp
= lbld
.vgrf(inst
->dst
.type
, dst_size
);
5117 if (inst
->predicate
) {
5118 /* Handle predication by copying the original contents of
5119 * the destination into the temporary before emitting the
5120 * lowered instruction.
5122 for (unsigned k
= 0; k
< dst_size
; ++k
)
5123 cbld
.at(block
, inst
)
5124 .MOV(offset(tmp
, lbld
, k
), offset(dst
, inst
->exec_size
, k
));
5127 for (unsigned k
= 0; k
< dst_size
; ++k
)
5128 cbld
.at(block
, inst
->next
)
5129 .MOV(offset(dst
, inst
->exec_size
, k
), offset(tmp
, lbld
, k
));
5134 /* No need to allocate a temporary for the lowered instruction, just
5135 * take the right group of channels from the original region.
5142 fs_visitor::lower_simd_width()
5144 bool progress
= false;
5146 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5147 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5149 if (lower_width
!= inst
->exec_size
) {
5150 /* Builder matching the original instruction. We may also need to
5151 * emit an instruction of width larger than the original, set the
5152 * execution size of the builder to the highest of both for now so
5153 * we're sure that both cases can be handled.
5155 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5156 const fs_builder ibld
= bld
.at(block
, inst
)
5157 .exec_all(inst
->force_writemask_all
)
5158 .group(max_width
, inst
->group
/ max_width
);
5160 /* Split the copies in chunks of the execution width of either the
5161 * original or the lowered instruction, whichever is lower.
5163 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5164 const unsigned dst_size
= inst
->size_written
/
5165 inst
->dst
.component_size(inst
->exec_size
);
5167 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5169 for (unsigned i
= 0; i
< n
; i
++) {
5170 /* Emit a copy of the original instruction with the lowered width.
5171 * If the EOT flag was set throw it away except for the last
5172 * instruction to avoid killing the thread prematurely.
5174 fs_inst split_inst
= *inst
;
5175 split_inst
.exec_size
= lower_width
;
5176 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
5178 /* Select the correct channel enables for the i-th group, then
5179 * transform the sources and destination and emit the lowered
5182 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5184 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5185 split_inst
.src
[j
] = emit_unzip(lbld
, block
, inst
, j
);
5187 split_inst
.dst
= emit_zip(lbld
, block
, inst
);
5188 split_inst
.size_written
=
5189 split_inst
.dst
.component_size(lower_width
) * dst_size
;
5191 lbld
.emit(split_inst
);
5194 inst
->remove(block
);
5200 invalidate_live_intervals();
5206 fs_visitor::dump_instructions()
5208 dump_instructions(NULL
);
5212 fs_visitor::dump_instructions(const char *name
)
5214 FILE *file
= stderr
;
5215 if (name
&& geteuid() != 0) {
5216 file
= fopen(name
, "w");
5222 calculate_register_pressure();
5223 int ip
= 0, max_pressure
= 0;
5224 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5225 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5226 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5227 dump_instruction(inst
, file
);
5230 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5233 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5234 fprintf(file
, "%4d: ", ip
++);
5235 dump_instruction(inst
, file
);
5239 if (file
!= stderr
) {
5245 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5247 dump_instruction(be_inst
, stderr
);
5251 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5253 fs_inst
*inst
= (fs_inst
*)be_inst
;
5255 if (inst
->predicate
) {
5256 fprintf(file
, "(%cf0.%d) ",
5257 inst
->predicate_inverse
? '-' : '+',
5261 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5263 fprintf(file
, ".sat");
5264 if (inst
->conditional_mod
) {
5265 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5266 if (!inst
->predicate
&&
5267 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5268 inst
->opcode
!= BRW_OPCODE_IF
&&
5269 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5270 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
5273 fprintf(file
, "(%d) ", inst
->exec_size
);
5276 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5280 fprintf(file
, "(EOT) ");
5283 switch (inst
->dst
.file
) {
5285 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
5286 if (alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
||
5287 inst
->dst
.offset
% REG_SIZE
)
5288 fprintf(file
, "+%d.%d",
5289 inst
->dst
.offset
/ REG_SIZE
, inst
->dst
.offset
% REG_SIZE
);
5292 fprintf(file
, "g%d", inst
->dst
.nr
);
5295 fprintf(file
, "m%d", inst
->dst
.nr
);
5298 fprintf(file
, "(null)");
5301 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.offset
/ 4);
5304 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.offset
/ REG_SIZE
);
5307 switch (inst
->dst
.nr
) {
5309 fprintf(file
, "null");
5311 case BRW_ARF_ADDRESS
:
5312 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
5314 case BRW_ARF_ACCUMULATOR
:
5315 fprintf(file
, "acc%d", inst
->dst
.subnr
);
5318 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5321 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5324 if (inst
->dst
.subnr
)
5325 fprintf(file
, "+%d", inst
->dst
.subnr
);
5328 unreachable("not reached");
5330 if (inst
->dst
.stride
!= 1)
5331 fprintf(file
, "<%u>", inst
->dst
.stride
);
5332 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
5334 for (int i
= 0; i
< inst
->sources
; i
++) {
5335 if (inst
->src
[i
].negate
)
5337 if (inst
->src
[i
].abs
)
5339 switch (inst
->src
[i
].file
) {
5341 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
5342 if (alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
) ||
5343 inst
->src
[i
].offset
% REG_SIZE
!= 0)
5344 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ REG_SIZE
,
5345 inst
->src
[i
].offset
% REG_SIZE
);
5348 fprintf(file
, "g%d", inst
->src
[i
].nr
);
5351 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
5354 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].offset
/ REG_SIZE
);
5357 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4);
5358 if (inst
->src
[i
].offset
% 4 != 0) {
5359 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ 4,
5360 inst
->src
[i
].offset
% 4);
5364 fprintf(file
, "(null)");
5367 switch (inst
->src
[i
].type
) {
5368 case BRW_REGISTER_TYPE_F
:
5369 fprintf(file
, "%-gf", inst
->src
[i
].f
);
5371 case BRW_REGISTER_TYPE_DF
:
5372 fprintf(file
, "%fdf", inst
->src
[i
].df
);
5374 case BRW_REGISTER_TYPE_W
:
5375 case BRW_REGISTER_TYPE_D
:
5376 fprintf(file
, "%dd", inst
->src
[i
].d
);
5378 case BRW_REGISTER_TYPE_UW
:
5379 case BRW_REGISTER_TYPE_UD
:
5380 fprintf(file
, "%uu", inst
->src
[i
].ud
);
5382 case BRW_REGISTER_TYPE_VF
:
5383 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
5384 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
5385 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
5386 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
5387 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5390 fprintf(file
, "???");
5395 switch (inst
->src
[i
].nr
) {
5397 fprintf(file
, "null");
5399 case BRW_ARF_ADDRESS
:
5400 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5402 case BRW_ARF_ACCUMULATOR
:
5403 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5406 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5409 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5412 if (inst
->src
[i
].subnr
)
5413 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
5416 if (inst
->src
[i
].abs
)
5419 if (inst
->src
[i
].file
!= IMM
) {
5421 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5422 unsigned hstride
= inst
->src
[i
].hstride
;
5423 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5425 stride
= inst
->src
[i
].stride
;
5428 fprintf(file
, "<%u>", stride
);
5430 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
5433 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5434 fprintf(file
, ", ");
5439 if (inst
->force_writemask_all
)
5440 fprintf(file
, "NoMask ");
5442 if (inst
->exec_size
!= dispatch_width
)
5443 fprintf(file
, "group%d ", inst
->group
);
5445 fprintf(file
, "\n");
5449 * Possibly returns an instruction that set up @param reg.
5451 * Sometimes we want to take the result of some expression/variable
5452 * dereference tree and rewrite the instruction generating the result
5453 * of the tree. When processing the tree, we know that the
5454 * instructions generated are all writing temporaries that are dead
5455 * outside of this tree. So, if we have some instructions that write
5456 * a temporary, we're free to point that temp write somewhere else.
5458 * Note that this doesn't guarantee that the instruction generated
5459 * only reg -- it might be the size=4 destination of a texture instruction.
5462 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5467 end
->is_partial_write() ||
5468 !reg
.equals(end
->dst
)) {
5476 fs_visitor::setup_fs_payload_gen6()
5478 assert(stage
== MESA_SHADER_FRAGMENT
);
5479 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5481 unsigned barycentric_interp_modes
=
5482 (stage
== MESA_SHADER_FRAGMENT
) ?
5483 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
5485 assert(devinfo
->gen
>= 6);
5487 /* R0-1: masks, pixel X/Y coordinates. */
5488 payload
.num_regs
= 2;
5489 /* R2: only for 32-pixel dispatch.*/
5491 /* R3-26: barycentric interpolation coordinates. These appear in the
5492 * same order that they appear in the brw_barycentric_mode
5493 * enum. Each set of coordinates occupies 2 registers if dispatch width
5494 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5495 * appear if they were enabled using the "Barycentric Interpolation
5496 * Mode" bits in WM_STATE.
5498 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
5499 if (barycentric_interp_modes
& (1 << i
)) {
5500 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5501 payload
.num_regs
+= 2;
5502 if (dispatch_width
== 16) {
5503 payload
.num_regs
+= 2;
5508 /* R27: interpolated depth if uses source depth */
5509 prog_data
->uses_src_depth
=
5510 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5511 if (prog_data
->uses_src_depth
) {
5512 payload
.source_depth_reg
= payload
.num_regs
;
5514 if (dispatch_width
== 16) {
5515 /* R28: interpolated depth if not SIMD8. */
5520 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5521 prog_data
->uses_src_w
=
5522 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5523 if (prog_data
->uses_src_w
) {
5524 payload
.source_w_reg
= payload
.num_regs
;
5526 if (dispatch_width
== 16) {
5527 /* R30: interpolated W if not SIMD8. */
5532 /* R31: MSAA position offsets. */
5533 if (prog_data
->persample_dispatch
&&
5534 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
)) {
5535 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
5537 * "MSDISPMODE_PERSAMPLE is required in order to select
5540 * So we can only really get sample positions if we are doing real
5541 * per-sample dispatch. If we need gl_SamplePosition and we don't have
5542 * persample dispatch, we hard-code it to 0.5.
5544 prog_data
->uses_pos_offset
= true;
5545 payload
.sample_pos_reg
= payload
.num_regs
;
5549 /* R32: MSAA input coverage mask */
5550 prog_data
->uses_sample_mask
=
5551 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5552 if (prog_data
->uses_sample_mask
) {
5553 assert(devinfo
->gen
>= 7);
5554 payload
.sample_mask_in_reg
= payload
.num_regs
;
5556 if (dispatch_width
== 16) {
5557 /* R33: input coverage mask if not SIMD8. */
5562 /* R34-: bary for 32-pixel. */
5563 /* R58-59: interp W for 32-pixel. */
5565 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5566 source_depth_to_render_target
= true;
5571 fs_visitor::setup_vs_payload()
5573 /* R0: thread header, R1: urb handles */
5574 payload
.num_regs
= 2;
5578 fs_visitor::setup_gs_payload()
5580 assert(stage
== MESA_SHADER_GEOMETRY
);
5582 struct brw_gs_prog_data
*gs_prog_data
=
5583 (struct brw_gs_prog_data
*) prog_data
;
5584 struct brw_vue_prog_data
*vue_prog_data
=
5585 (struct brw_vue_prog_data
*) prog_data
;
5587 /* R0: thread header, R1: output URB handles */
5588 payload
.num_regs
= 2;
5590 if (gs_prog_data
->include_primitive_id
) {
5591 /* R2: Primitive ID 0..7 */
5595 /* Use a maximum of 24 registers for push-model inputs. */
5596 const unsigned max_push_components
= 24;
5598 /* If pushing our inputs would take too many registers, reduce the URB read
5599 * length (which is in HWords, or 8 registers), and resort to pulling.
5601 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5602 * have to multiply by VerticesIn to obtain the total storage requirement.
5604 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5605 max_push_components
|| gs_prog_data
->invocations
> 1) {
5606 gs_prog_data
->base
.include_vue_handles
= true;
5608 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5609 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5611 vue_prog_data
->urb_read_length
=
5612 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5617 fs_visitor::setup_cs_payload()
5619 assert(devinfo
->gen
>= 7);
5620 payload
.num_regs
= 1;
5624 fs_visitor::calculate_register_pressure()
5626 invalidate_live_intervals();
5627 calculate_live_intervals();
5629 unsigned num_instructions
= 0;
5630 foreach_block(block
, cfg
)
5631 num_instructions
+= block
->instructions
.length();
5633 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5635 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5636 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5637 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5642 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
5644 * The needs_unlit_centroid_workaround ends up producing one of these per
5645 * channel of centroid input, so it's good to clean them up.
5647 * An assumption here is that nothing ever modifies the dispatched pixels
5648 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
5649 * dictates that anyway.
5652 fs_visitor::opt_drop_redundant_mov_to_flags()
5654 bool flag_mov_found
[2] = {false};
5655 bool progress
= false;
5657 /* Instructions removed by this pass can only be added if this were true */
5658 if (!devinfo
->needs_unlit_centroid_workaround
)
5661 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5662 if (inst
->is_control_flow()) {
5663 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
5664 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
5665 if (!flag_mov_found
[inst
->flag_subreg
]) {
5666 flag_mov_found
[inst
->flag_subreg
] = true;
5668 inst
->remove(block
);
5671 } else if (inst
->flags_written()) {
5672 flag_mov_found
[inst
->flag_subreg
] = false;
5680 fs_visitor::optimize()
5682 /* Start by validating the shader we currently have. */
5685 /* bld is the common builder object pointing at the end of the program we
5686 * used to translate it into i965 IR. For the optimization and lowering
5687 * passes coming next, any code added after the end of the program without
5688 * having explicitly called fs_builder::at() clearly points at a mistake.
5689 * Ideally optimization passes wouldn't be part of the visitor so they
5690 * wouldn't have access to bld at all, but they do, so just in case some
5691 * pass forgets to ask for a location explicitly set it to NULL here to
5692 * make it trip. The dispatch width is initialized to a bogus value to
5693 * make sure that optimizations set the execution controls explicitly to
5694 * match the code they are manipulating instead of relying on the defaults.
5696 bld
= fs_builder(this, 64);
5698 assign_constant_locations();
5699 lower_constant_loads();
5703 split_virtual_grfs();
5706 #define OPT(pass, args...) ({ \
5708 bool this_progress = pass(args); \
5710 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5711 char filename[64]; \
5712 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5713 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5715 backend_shader::dump_instructions(filename); \
5720 progress = progress || this_progress; \
5724 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5726 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5727 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5729 backend_shader::dump_instructions(filename
);
5732 bool progress
= false;
5736 OPT(opt_drop_redundant_mov_to_flags
);
5743 OPT(remove_duplicate_mrf_writes
);
5747 OPT(opt_copy_propagate
);
5748 OPT(opt_predicated_break
, this);
5749 OPT(opt_cmod_propagation
);
5750 OPT(dead_code_eliminate
);
5751 OPT(opt_peephole_sel
);
5752 OPT(dead_control_flow_eliminate
, this);
5753 OPT(opt_register_renaming
);
5754 OPT(opt_saturate_propagation
);
5755 OPT(register_coalesce
);
5756 OPT(compute_to_mrf
);
5757 OPT(eliminate_find_live_channel
);
5759 OPT(compact_virtual_grfs
);
5765 if (OPT(lower_pack
)) {
5766 OPT(register_coalesce
);
5767 OPT(dead_code_eliminate
);
5770 if (OPT(lower_d2x
)) {
5771 OPT(opt_copy_propagate
);
5772 OPT(dead_code_eliminate
);
5775 OPT(lower_simd_width
);
5777 /* After SIMD lowering just in case we had to unroll the EOT send. */
5778 OPT(opt_sampler_eot
);
5780 OPT(lower_logical_sends
);
5783 OPT(opt_copy_propagate
);
5784 /* Only run after logical send lowering because it's easier to implement
5785 * in terms of physical sends.
5787 if (OPT(opt_zero_samples
))
5788 OPT(opt_copy_propagate
);
5789 /* Run after logical send lowering to give it a chance to CSE the
5790 * LOAD_PAYLOAD instructions created to construct the payloads of
5791 * e.g. texturing messages in cases where it wasn't possible to CSE the
5792 * whole logical instruction.
5795 OPT(register_coalesce
);
5796 OPT(compute_to_mrf
);
5797 OPT(dead_code_eliminate
);
5798 OPT(remove_duplicate_mrf_writes
);
5799 OPT(opt_peephole_sel
);
5802 OPT(opt_redundant_discard_jumps
);
5804 if (OPT(lower_load_payload
)) {
5805 split_virtual_grfs();
5806 OPT(register_coalesce
);
5807 OPT(compute_to_mrf
);
5808 OPT(dead_code_eliminate
);
5811 OPT(opt_combine_constants
);
5812 OPT(lower_integer_multiplication
);
5814 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5815 OPT(opt_cmod_propagation
);
5817 OPT(opt_copy_propagate
);
5818 OPT(dead_code_eliminate
);
5821 lower_uniform_pull_constant_loads();
5827 * Three source instruction must have a GRF/MRF destination register.
5828 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5831 fs_visitor::fixup_3src_null_dest()
5833 bool progress
= false;
5835 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5836 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
5837 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5844 invalidate_live_intervals();
5848 fs_visitor::allocate_registers(bool allow_spilling
)
5850 bool allocated_without_spills
;
5852 static const enum instruction_scheduler_mode pre_modes
[] = {
5854 SCHEDULE_PRE_NON_LIFO
,
5858 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
5860 /* Try each scheduling heuristic to see if it can successfully register
5861 * allocate without spilling. They should be ordered by decreasing
5862 * performance but increasing likelihood of allocating.
5864 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5865 schedule_instructions(pre_modes
[i
]);
5868 assign_regs_trivial();
5869 allocated_without_spills
= true;
5871 allocated_without_spills
= assign_regs(false, spill_all
);
5873 if (allocated_without_spills
)
5877 if (!allocated_without_spills
) {
5878 if (!allow_spilling
)
5879 fail("Failure to register allocate and spilling is not allowed.");
5881 /* We assume that any spilling is worse than just dropping back to
5882 * SIMD8. There's probably actually some intermediate point where
5883 * SIMD16 with a couple of spills is still better.
5885 if (dispatch_width
> min_dispatch_width
) {
5886 fail("Failure to register allocate. Reduce number of "
5887 "live scalar values to avoid this.");
5889 compiler
->shader_perf_log(log_data
,
5890 "%s shader triggered register spilling. "
5891 "Try reducing the number of live scalar "
5892 "values to improve performance.\n",
5896 /* Since we're out of heuristics, just go spill registers until we
5897 * get an allocation.
5899 while (!assign_regs(true, spill_all
)) {
5905 /* This must come after all optimization and register allocation, since
5906 * it inserts dead code that happens to have side effects, and it does
5907 * so based on the actual physical registers in use.
5909 insert_gen4_send_dependency_workarounds();
5914 schedule_instructions(SCHEDULE_POST
);
5916 if (last_scratch
> 0) {
5917 unsigned max_scratch_size
= 2 * 1024 * 1024;
5919 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5921 if (stage
== MESA_SHADER_COMPUTE
) {
5922 if (devinfo
->is_haswell
) {
5923 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5924 * field documentation, Haswell supports a minimum of 2kB of
5925 * scratch space for compute shaders, unlike every other stage
5928 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
5929 } else if (devinfo
->gen
<= 7) {
5930 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5931 * field documentation, platforms prior to Haswell measure scratch
5932 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
5934 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
5935 max_scratch_size
= 12 * 1024;
5939 /* We currently only support up to 2MB of scratch space. If we
5940 * need to support more eventually, the documentation suggests
5941 * that we could allocate a larger buffer, and partition it out
5942 * ourselves. We'd just have to undo the hardware's address
5943 * calculation by subtracting (FFTID * Per Thread Scratch Space)
5944 * and then add FFTID * (Larger Per Thread Scratch Space).
5946 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
5947 * Thread Group Tracking > Local Memory/Scratch Space.
5949 assert(prog_data
->total_scratch
< max_scratch_size
);
5954 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5956 assert(stage
== MESA_SHADER_VERTEX
);
5960 if (shader_time_index
>= 0)
5961 emit_shader_time_begin();
5968 compute_clip_distance(clip_planes
);
5972 if (shader_time_index
>= 0)
5973 emit_shader_time_end();
5979 assign_curb_setup();
5980 assign_vs_urb_setup();
5982 fixup_3src_null_dest();
5983 allocate_registers(true);
5989 fs_visitor::run_tcs_single_patch()
5991 assert(stage
== MESA_SHADER_TESS_CTRL
);
5993 struct brw_tcs_prog_data
*tcs_prog_data
=
5994 (struct brw_tcs_prog_data
*) prog_data
;
5996 /* r1-r4 contain the ICP handles. */
5997 payload
.num_regs
= 5;
5999 if (shader_time_index
>= 0)
6000 emit_shader_time_begin();
6002 /* Initialize gl_InvocationID */
6003 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
6004 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6005 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
6006 bld
.MOV(channels_ud
, channels_uw
);
6008 if (tcs_prog_data
->instances
== 1) {
6009 invocation_id
= channels_ud
;
6011 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6013 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
6014 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6015 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6016 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
6017 brw_imm_ud(INTEL_MASK(23, 17)));
6018 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
6020 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
6023 /* Fix the disptach mask */
6024 if (nir
->info
.tcs
.vertices_out
% 8) {
6025 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
6026 brw_imm_ud(nir
->info
.tcs
.vertices_out
), BRW_CONDITIONAL_L
);
6027 bld
.IF(BRW_PREDICATE_NORMAL
);
6032 if (nir
->info
.tcs
.vertices_out
% 8) {
6033 bld
.emit(BRW_OPCODE_ENDIF
);
6036 /* Emit EOT write; set TR DS Cache bit */
6038 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
6039 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
6040 fs_reg(brw_imm_ud(0)),
6042 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
6043 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
6045 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
6046 bld
.null_reg_ud(), payload
);
6050 if (shader_time_index
>= 0)
6051 emit_shader_time_end();
6060 assign_curb_setup();
6061 assign_tcs_single_patch_urb_setup();
6063 fixup_3src_null_dest();
6064 allocate_registers(true);
6070 fs_visitor::run_tes()
6072 assert(stage
== MESA_SHADER_TESS_EVAL
);
6074 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6075 payload
.num_regs
= 5;
6077 if (shader_time_index
>= 0)
6078 emit_shader_time_begin();
6087 if (shader_time_index
>= 0)
6088 emit_shader_time_end();
6094 assign_curb_setup();
6095 assign_tes_urb_setup();
6097 fixup_3src_null_dest();
6098 allocate_registers(true);
6104 fs_visitor::run_gs()
6106 assert(stage
== MESA_SHADER_GEOMETRY
);
6110 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6112 if (gs_compile
->control_data_header_size_bits
> 0) {
6113 /* Create a VGRF to store accumulated control data bits. */
6114 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6116 /* If we're outputting more than 32 control data bits, then EmitVertex()
6117 * will set control_data_bits to 0 after emitting the first vertex.
6118 * Otherwise, we need to initialize it to 0 here.
6120 if (gs_compile
->control_data_header_size_bits
<= 32) {
6121 const fs_builder abld
= bld
.annotate("initialize control data bits");
6122 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6126 if (shader_time_index
>= 0)
6127 emit_shader_time_begin();
6131 emit_gs_thread_end();
6133 if (shader_time_index
>= 0)
6134 emit_shader_time_end();
6143 assign_curb_setup();
6144 assign_gs_urb_setup();
6146 fixup_3src_null_dest();
6147 allocate_registers(true);
6153 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6155 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
6156 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6158 assert(stage
== MESA_SHADER_FRAGMENT
);
6160 if (devinfo
->gen
>= 6)
6161 setup_fs_payload_gen6();
6163 setup_fs_payload_gen4();
6167 } else if (do_rep_send
) {
6168 assert(dispatch_width
== 16);
6169 emit_repclear_shader();
6171 if (shader_time_index
>= 0)
6172 emit_shader_time_begin();
6174 calculate_urb_setup();
6175 if (nir
->info
.inputs_read
> 0 ||
6176 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
6177 if (devinfo
->gen
< 6)
6178 emit_interpolation_setup_gen4();
6180 emit_interpolation_setup_gen6();
6183 /* We handle discards by keeping track of the still-live pixels in f0.1.
6184 * Initialize it with the dispatched pixels.
6186 if (wm_prog_data
->uses_kill
) {
6187 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
6188 discard_init
->flag_subreg
= 1;
6191 /* Generate FS IR for main(). (the visitor only descends into
6192 * functions called "main").
6199 if (wm_prog_data
->uses_kill
)
6200 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6202 if (wm_key
->alpha_test_func
)
6207 if (shader_time_index
>= 0)
6208 emit_shader_time_end();
6214 assign_curb_setup();
6217 fixup_3src_null_dest();
6218 allocate_registers(allow_spilling
);
6228 fs_visitor::run_cs()
6230 assert(stage
== MESA_SHADER_COMPUTE
);
6234 if (shader_time_index
>= 0)
6235 emit_shader_time_begin();
6237 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6238 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6239 const fs_builder abld
= bld
.exec_all().group(1, 0);
6240 abld
.MOV(retype(suboffset(brw_sr0_reg(), 1), BRW_REGISTER_TYPE_UW
),
6241 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6249 emit_cs_terminate();
6251 if (shader_time_index
>= 0)
6252 emit_shader_time_end();
6258 assign_curb_setup();
6260 fixup_3src_null_dest();
6261 allocate_registers(true);
6270 * Return a bitfield where bit n is set if barycentric interpolation mode n
6271 * (see enum brw_barycentric_mode) is needed by the fragment shader.
6273 * We examine the load_barycentric intrinsics rather than looking at input
6274 * variables so that we catch interpolateAtCentroid() messages too, which
6275 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
6278 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
6279 const nir_shader
*shader
)
6281 unsigned barycentric_interp_modes
= 0;
6283 nir_foreach_function(f
, shader
) {
6287 nir_foreach_block(block
, f
->impl
) {
6288 nir_foreach_instr(instr
, block
) {
6289 if (instr
->type
!= nir_instr_type_intrinsic
)
6292 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6293 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6296 /* Ignore WPOS; it doesn't require interpolation. */
6297 if (nir_intrinsic_base(intrin
) == VARYING_SLOT_POS
)
6300 intrin
= nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6301 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
6302 nir_intrinsic_interp_mode(intrin
);
6303 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
6304 enum brw_barycentric_mode bary
=
6305 brw_barycentric_mode(interp
, bary_op
);
6307 barycentric_interp_modes
|= 1 << bary
;
6309 if (devinfo
->needs_unlit_centroid_workaround
&&
6310 bary_op
== nir_intrinsic_load_barycentric_centroid
)
6311 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
6316 return barycentric_interp_modes
;
6320 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
6321 const nir_shader
*shader
)
6323 prog_data
->flat_inputs
= 0;
6325 nir_foreach_variable(var
, &shader
->inputs
) {
6326 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
6328 if (input_index
< 0)
6332 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6333 prog_data
->flat_inputs
|= (1 << input_index
);
6338 computed_depth_mode(const nir_shader
*shader
)
6340 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6341 switch (shader
->info
.fs
.depth_layout
) {
6342 case FRAG_DEPTH_LAYOUT_NONE
:
6343 case FRAG_DEPTH_LAYOUT_ANY
:
6344 return BRW_PSCDEPTH_ON
;
6345 case FRAG_DEPTH_LAYOUT_GREATER
:
6346 return BRW_PSCDEPTH_ON_GE
;
6347 case FRAG_DEPTH_LAYOUT_LESS
:
6348 return BRW_PSCDEPTH_ON_LE
;
6349 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
6350 return BRW_PSCDEPTH_OFF
;
6353 return BRW_PSCDEPTH_OFF
;
6357 * Move load_interpolated_input with simple (payload-based) barycentric modes
6358 * to the top of the program so we don't emit multiple PLNs for the same input.
6360 * This works around CSE not being able to handle non-dominating cases
6366 * interpolate the same exact input
6369 * This should be replaced by global value numbering someday.
6372 move_interpolation_to_top(nir_shader
*nir
)
6374 nir_foreach_function(f
, nir
) {
6378 nir_block
*top
= nir_start_block(f
->impl
);
6379 exec_node
*cursor_node
= NULL
;
6381 nir_foreach_block(block
, f
->impl
) {
6385 nir_foreach_instr_safe(instr
, block
) {
6386 if (instr
->type
!= nir_instr_type_intrinsic
)
6389 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6390 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6392 nir_intrinsic_instr
*bary_intrinsic
=
6393 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6394 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
6396 /* Leave interpolateAtSample/Offset() where they are. */
6397 if (op
== nir_intrinsic_load_barycentric_at_sample
||
6398 op
== nir_intrinsic_load_barycentric_at_offset
)
6401 nir_instr
*move
[3] = {
6402 &bary_intrinsic
->instr
,
6403 intrin
->src
[1].ssa
->parent_instr
,
6407 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
6408 if (move
[i
]->block
!= top
) {
6409 move
[i
]->block
= top
;
6410 exec_node_remove(&move
[i
]->node
);
6412 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
6414 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
6416 cursor_node
= &move
[i
]->node
;
6421 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6422 ((unsigned) nir_metadata_block_index
|
6423 (unsigned) nir_metadata_dominance
));
6428 * Apply default interpolation settings to FS inputs which don't specify any.
6431 brw_nir_set_default_interpolation(const struct gen_device_info
*devinfo
,
6432 struct nir_shader
*nir
,
6433 bool api_flat_shade
,
6434 bool per_sample_interpolation
)
6436 assert(nir
->stage
== MESA_SHADER_FRAGMENT
);
6438 nir_foreach_variable(var
, &nir
->inputs
) {
6439 /* Apply default interpolation mode.
6441 * Everything defaults to smooth except for the legacy GL color
6442 * built-in variables, which might be flat depending on API state.
6444 if (var
->data
.interpolation
== INTERP_MODE_NONE
) {
6445 const bool flat
= api_flat_shade
&&
6446 (var
->data
.location
== VARYING_SLOT_COL0
||
6447 var
->data
.location
== VARYING_SLOT_COL1
);
6449 var
->data
.interpolation
= flat
? INTERP_MODE_FLAT
6450 : INTERP_MODE_SMOOTH
;
6453 /* Apply 'sample' if necessary for API state. */
6454 if (per_sample_interpolation
&&
6455 var
->data
.interpolation
!= INTERP_MODE_FLAT
) {
6456 var
->data
.centroid
= false;
6457 var
->data
.sample
= true;
6460 /* On Ironlake and below, there is only one interpolation mode.
6461 * Centroid interpolation doesn't mean anything on this hardware --
6462 * there is no multisampling.
6464 if (devinfo
->gen
< 6) {
6465 var
->data
.centroid
= false;
6466 var
->data
.sample
= false;
6472 * Demote per-sample barycentric intrinsics to centroid.
6474 * Useful when rendering to a non-multisampled buffer.
6477 demote_sample_qualifiers(nir_shader
*nir
)
6479 nir_foreach_function(f
, nir
) {
6484 nir_builder_init(&b
, f
->impl
);
6486 nir_foreach_block(block
, f
->impl
) {
6487 nir_foreach_instr_safe(instr
, block
) {
6488 if (instr
->type
!= nir_instr_type_intrinsic
)
6491 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6492 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
6493 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
6496 b
.cursor
= nir_before_instr(instr
);
6497 nir_ssa_def
*centroid
=
6498 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
6499 nir_intrinsic_interp_mode(intrin
));
6500 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
6501 nir_src_for_ssa(centroid
));
6502 nir_instr_remove(instr
);
6506 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6507 ((unsigned) nir_metadata_block_index
|
6508 (unsigned) nir_metadata_dominance
));
6513 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
6515 const struct brw_wm_prog_key
*key
,
6516 struct brw_wm_prog_data
*prog_data
,
6517 const nir_shader
*src_shader
,
6518 struct gl_program
*prog
,
6519 int shader_time_index8
, int shader_time_index16
,
6520 bool allow_spilling
,
6522 unsigned *final_assembly_size
,
6525 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6526 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6528 brw_nir_set_default_interpolation(compiler
->devinfo
, shader
,
6529 key
->flat_shade
, key
->persample_interp
);
6530 brw_nir_lower_fs_inputs(shader
);
6531 brw_nir_lower_fs_outputs(shader
);
6532 if (!key
->multisample_fbo
)
6533 NIR_PASS_V(shader
, demote_sample_qualifiers
);
6534 NIR_PASS_V(shader
, move_interpolation_to_top
);
6535 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6537 /* key->alpha_test_func means simulating alpha testing via discards,
6538 * so the shader definitely kills pixels.
6540 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
6541 prog_data
->uses_omask
= key
->multisample_fbo
&&
6542 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
6543 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
6544 prog_data
->computed_stencil
=
6545 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
6547 prog_data
->persample_dispatch
=
6548 key
->multisample_fbo
&&
6549 (key
->persample_interp
||
6550 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
6551 SYSTEM_BIT_SAMPLE_POS
)) ||
6552 shader
->info
.fs
.uses_sample_qualifier
||
6553 shader
->info
.outputs_read
);
6555 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
6557 prog_data
->barycentric_interp_modes
=
6558 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
6560 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
;
6561 uint8_t simd8_grf_start
= 0, simd16_grf_start
= 0;
6562 unsigned simd8_grf_used
= 0, simd16_grf_used
= 0;
6564 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
6565 &prog_data
->base
, prog
, shader
, 8,
6566 shader_time_index8
);
6567 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
6569 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
6572 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
6574 simd8_grf_start
= v8
.payload
.num_regs
;
6575 simd8_grf_used
= v8
.grf_used
;
6578 if (v8
.max_dispatch_width
>= 16 &&
6579 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
6580 /* Try a SIMD16 compile */
6581 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
6582 &prog_data
->base
, prog
, shader
, 16,
6583 shader_time_index16
);
6584 v16
.import_uniforms(&v8
);
6585 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
6586 compiler
->shader_perf_log(log_data
,
6587 "SIMD16 shader failed to compile: %s",
6590 simd16_cfg
= v16
.cfg
;
6591 simd16_grf_start
= v16
.payload
.num_regs
;
6592 simd16_grf_used
= v16
.grf_used
;
6596 /* When the caller requests a repclear shader, they want SIMD16-only */
6600 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
6601 * at the top to select the shader. We've never implemented that.
6602 * Instead, we just give them exactly one shader and we pick the widest one
6605 if (compiler
->devinfo
->gen
< 5 && simd16_cfg
)
6608 if (prog_data
->persample_dispatch
) {
6609 /* Starting with SandyBridge (where we first get MSAA), the different
6610 * pixel dispatch combinations are grouped into classifications A
6611 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
6612 * generations, the only configurations supporting persample dispatch
6613 * are are this in which only one dispatch width is enabled.
6615 * If computed depth is enabled, SNB only allows SIMD8 while IVB+
6616 * allow SIMD8 or SIMD16 so we choose SIMD16 if available.
6618 if (compiler
->devinfo
->gen
== 6 &&
6619 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
) {
6621 } else if (simd16_cfg
) {
6626 /* We have to compute the flat inputs after the visitor is finished running
6627 * because it relies on prog_data->urb_setup which is computed in
6628 * fs_visitor::calculate_urb_setup().
6630 brw_compute_flat_inputs(prog_data
, shader
);
6632 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
6633 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6634 MESA_SHADER_FRAGMENT
);
6636 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
6637 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
6638 shader
->info
.label
? shader
->info
.label
:
6640 shader
->info
.name
));
6644 prog_data
->dispatch_8
= true;
6645 g
.generate_code(simd8_cfg
, 8);
6646 prog_data
->base
.dispatch_grf_start_reg
= simd8_grf_start
;
6647 prog_data
->reg_blocks_0
= brw_register_blocks(simd8_grf_used
);
6650 prog_data
->dispatch_16
= true;
6651 prog_data
->prog_offset_2
= g
.generate_code(simd16_cfg
, 16);
6652 prog_data
->dispatch_grf_start_reg_2
= simd16_grf_start
;
6653 prog_data
->reg_blocks_2
= brw_register_blocks(simd16_grf_used
);
6655 } else if (simd16_cfg
) {
6656 prog_data
->dispatch_16
= true;
6657 g
.generate_code(simd16_cfg
, 16);
6658 prog_data
->base
.dispatch_grf_start_reg
= simd16_grf_start
;
6659 prog_data
->reg_blocks_0
= brw_register_blocks(simd16_grf_used
);
6662 return g
.get_assembly(final_assembly_size
);
6666 fs_visitor::emit_cs_work_group_id_setup()
6668 assert(stage
== MESA_SHADER_COMPUTE
);
6670 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6672 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
6673 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
6674 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
6676 bld
.MOV(*reg
, r0_1
);
6677 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
6678 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
6684 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
6686 block
->dwords
= dwords
;
6687 block
->regs
= DIV_ROUND_UP(dwords
, 8);
6688 block
->size
= block
->regs
* 32;
6692 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
6693 struct brw_cs_prog_data
*cs_prog_data
)
6695 const struct brw_stage_prog_data
*prog_data
=
6696 (struct brw_stage_prog_data
*) cs_prog_data
;
6697 bool fill_thread_id
=
6698 cs_prog_data
->thread_local_id_index
>= 0 &&
6699 cs_prog_data
->thread_local_id_index
< (int)prog_data
->nr_params
;
6700 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
6702 /* The thread ID should be stored in the last param dword */
6703 assert(prog_data
->nr_params
> 0 || !fill_thread_id
);
6704 assert(!fill_thread_id
||
6705 cs_prog_data
->thread_local_id_index
==
6706 (int)prog_data
->nr_params
- 1);
6708 unsigned cross_thread_dwords
, per_thread_dwords
;
6709 if (!cross_thread_supported
) {
6710 cross_thread_dwords
= 0u;
6711 per_thread_dwords
= prog_data
->nr_params
;
6712 } else if (fill_thread_id
) {
6713 /* Fill all but the last register with cross-thread payload */
6714 cross_thread_dwords
= 8 * (cs_prog_data
->thread_local_id_index
/ 8);
6715 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
6716 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
6718 /* Fill all data using cross-thread payload */
6719 cross_thread_dwords
= prog_data
->nr_params
;
6720 per_thread_dwords
= 0u;
6723 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
6724 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
6726 unsigned total_dwords
=
6727 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
6728 cs_prog_data
->push
.cross_thread
.size
) / 4;
6729 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
6731 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
6732 cs_prog_data
->push
.per_thread
.size
== 0);
6733 assert(cs_prog_data
->push
.cross_thread
.dwords
+
6734 cs_prog_data
->push
.per_thread
.dwords
==
6735 prog_data
->nr_params
);
6739 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
6741 cs_prog_data
->simd_size
= size
;
6742 unsigned group_size
= cs_prog_data
->local_size
[0] *
6743 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
6744 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
6748 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
6750 const struct brw_cs_prog_key
*key
,
6751 struct brw_cs_prog_data
*prog_data
,
6752 const nir_shader
*src_shader
,
6753 int shader_time_index
,
6754 unsigned *final_assembly_size
,
6757 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6758 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6760 brw_nir_lower_cs_shared(shader
);
6761 prog_data
->base
.total_shared
+= shader
->num_shared
;
6763 /* Now that we cloned the nir_shader, we can update num_uniforms based on
6764 * the thread_local_id_index.
6766 assert(prog_data
->thread_local_id_index
>= 0);
6767 shader
->num_uniforms
=
6768 MAX2(shader
->num_uniforms
,
6769 (unsigned)4 * (prog_data
->thread_local_id_index
+ 1));
6771 brw_nir_lower_intrinsics(shader
, &prog_data
->base
);
6772 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6774 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
6775 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
6776 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
6777 unsigned local_workgroup_size
=
6778 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
6779 shader
->info
.cs
.local_size
[2];
6781 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
6782 unsigned simd_required
= DIV_ROUND_UP(local_workgroup_size
, max_cs_threads
);
6785 const char *fail_msg
= NULL
;
6787 /* Now the main event: Visit the shader IR and generate our CS IR for it.
6789 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6790 NULL
, /* Never used in core profile */
6791 shader
, 8, shader_time_index
);
6792 if (simd_required
<= 8) {
6794 fail_msg
= v8
.fail_msg
;
6797 cs_set_simd_size(prog_data
, 8);
6798 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6799 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
6803 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6804 NULL
, /* Never used in core profile */
6805 shader
, 16, shader_time_index
);
6806 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
6807 !fail_msg
&& v8
.max_dispatch_width
>= 16 &&
6808 simd_required
<= 16) {
6809 /* Try a SIMD16 compile */
6810 if (simd_required
<= 8)
6811 v16
.import_uniforms(&v8
);
6812 if (!v16
.run_cs()) {
6813 compiler
->shader_perf_log(log_data
,
6814 "SIMD16 shader failed to compile: %s",
6818 "Couldn't generate SIMD16 program and not "
6819 "enough threads for SIMD8";
6823 cs_set_simd_size(prog_data
, 16);
6824 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6825 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
6829 fs_visitor
v32(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6830 NULL
, /* Never used in core profile */
6831 shader
, 32, shader_time_index
);
6832 if (!fail_msg
&& v8
.max_dispatch_width
>= 32 &&
6833 (simd_required
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
6834 /* Try a SIMD32 compile */
6835 if (simd_required
<= 8)
6836 v32
.import_uniforms(&v8
);
6837 else if (simd_required
<= 16)
6838 v32
.import_uniforms(&v16
);
6840 if (!v32
.run_cs()) {
6841 compiler
->shader_perf_log(log_data
,
6842 "SIMD32 shader failed to compile: %s",
6846 "Couldn't generate SIMD32 program and not "
6847 "enough threads for SIMD16";
6851 cs_set_simd_size(prog_data
, 32);
6852 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6856 if (unlikely(cfg
== NULL
)) {
6859 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
6864 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
6865 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6866 MESA_SHADER_COMPUTE
);
6867 if (INTEL_DEBUG
& DEBUG_CS
) {
6868 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
6869 shader
->info
.label
? shader
->info
.label
:
6872 g
.enable_debug(name
);
6875 g
.generate_code(cfg
, prog_data
->simd_size
);
6877 return g
.get_assembly(final_assembly_size
);