2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
47 #include "brw_dead_control_flow.h"
48 #include "main/uniforms.h"
49 #include "brw_fs_live_variables.h"
50 #include "glsl/nir/glsl_types.h"
51 #include "program/sampler.h"
56 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
57 const fs_reg
*src
, unsigned sources
)
59 memset(this, 0, sizeof(*this));
61 this->src
= new fs_reg
[MAX2(sources
, 3)];
62 for (unsigned i
= 0; i
< sources
; i
++)
63 this->src
[i
] = src
[i
];
65 this->opcode
= opcode
;
67 this->sources
= sources
;
68 this->exec_size
= exec_size
;
70 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
72 assert(this->exec_size
!= 0);
74 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
76 /* This will be the case for almost all instructions. */
82 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
86 this->regs_written
= 0;
90 unreachable("Invalid destination register file");
92 unreachable("Invalid register file");
95 this->writes_accumulator
= false;
100 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
103 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
105 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
108 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
110 init(opcode
, exec_size
, dst
, NULL
, 0);
113 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
116 const fs_reg src
[1] = { src0
};
117 init(opcode
, exec_size
, dst
, src
, 1);
120 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
121 const fs_reg
&src0
, const fs_reg
&src1
)
123 const fs_reg src
[2] = { src0
, src1
};
124 init(opcode
, exec_size
, dst
, src
, 2);
127 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
128 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
130 const fs_reg src
[3] = { src0
, src1
, src2
};
131 init(opcode
, exec_size
, dst
, src
, 3);
134 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
135 const fs_reg src
[], unsigned sources
)
137 init(opcode
, exec_width
, dst
, src
, sources
);
140 fs_inst::fs_inst(const fs_inst
&that
)
142 memcpy(this, &that
, sizeof(that
));
144 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
146 for (unsigned i
= 0; i
< that
.sources
; i
++)
147 this->src
[i
] = that
.src
[i
];
156 fs_inst::resize_sources(uint8_t num_sources
)
158 if (this->sources
!= num_sources
) {
159 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
161 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
162 src
[i
] = this->src
[i
];
166 this->sources
= num_sources
;
171 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
173 const fs_reg
&surf_index
,
174 const fs_reg
&varying_offset
,
175 uint32_t const_offset
)
177 /* We have our constant surface use a pitch of 4 bytes, so our index can
178 * be any component of a vector, and then we load 4 contiguous
179 * components starting from that.
181 * We break down the const_offset to a portion added to the variable
182 * offset and a portion done using reg_offset, which means that if you
183 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
184 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
185 * CSE can later notice that those loads are all the same and eliminate
186 * the redundant ones.
188 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
189 bld
.ADD(vec4_offset
, varying_offset
, fs_reg(const_offset
& ~3));
192 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
193 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
194 * u, v, r) as parameters, or we can just use the SIMD16 message
195 * consisting of (header, u). We choose the second, at the cost of a
196 * longer return length.
202 if (devinfo
->gen
>= 7)
203 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
205 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
207 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
208 fs_reg vec4_result
= fs_reg(GRF
, alloc
.allocate(regs_written
), dst
.type
);
209 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
210 inst
->regs_written
= regs_written
;
212 if (devinfo
->gen
< 7) {
213 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
);
214 inst
->header_size
= 1;
215 if (devinfo
->gen
== 4)
218 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
221 bld
.MOV(dst
, offset(vec4_result
, bld
, (const_offset
& 3) * scale
));
225 * A helper for MOV generation for fixing up broken hardware SEND dependency
229 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
231 /* The caller always wants uncompressed to emit the minimal extra
232 * dependencies, and to avoid having to deal with aligning its regs to 2.
234 const fs_builder ubld
= bld
.annotate("send dependency resolve")
237 ubld
.MOV(ubld
.null_reg_f(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
241 fs_inst::equals(fs_inst
*inst
) const
243 return (opcode
== inst
->opcode
&&
244 dst
.equals(inst
->dst
) &&
245 src
[0].equals(inst
->src
[0]) &&
246 src
[1].equals(inst
->src
[1]) &&
247 src
[2].equals(inst
->src
[2]) &&
248 saturate
== inst
->saturate
&&
249 predicate
== inst
->predicate
&&
250 conditional_mod
== inst
->conditional_mod
&&
251 mlen
== inst
->mlen
&&
252 base_mrf
== inst
->base_mrf
&&
253 target
== inst
->target
&&
255 header_size
== inst
->header_size
&&
256 shadow_compare
== inst
->shadow_compare
&&
257 exec_size
== inst
->exec_size
&&
258 offset
== inst
->offset
);
262 fs_inst::overwrites_reg(const fs_reg
®
) const
264 return reg
.in_range(dst
, regs_written
);
268 fs_inst::is_send_from_grf() const
271 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
272 case SHADER_OPCODE_SHADER_TIME_ADD
:
273 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
274 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
275 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
276 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
277 case SHADER_OPCODE_UNTYPED_ATOMIC
:
278 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
279 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
280 case SHADER_OPCODE_TYPED_ATOMIC
:
281 case SHADER_OPCODE_TYPED_SURFACE_READ
:
282 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
283 case SHADER_OPCODE_URB_WRITE_SIMD8
:
284 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
285 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
286 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
288 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
289 return src
[1].file
== GRF
;
290 case FS_OPCODE_FB_WRITE
:
291 return src
[0].file
== GRF
;
294 return src
[0].file
== GRF
;
301 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
303 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
306 fs_reg reg
= this->src
[0];
307 if (reg
.file
!= GRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
310 if (grf_alloc
.sizes
[reg
.reg
] != this->regs_written
)
313 for (int i
= 0; i
< this->sources
; i
++) {
314 reg
.type
= this->src
[i
].type
;
315 if (!this->src
[i
].equals(reg
))
318 if (i
< this->header_size
) {
321 reg
.reg_offset
+= this->exec_size
/ 8;
329 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
331 if (devinfo
->gen
== 6 && is_math())
334 if (is_send_from_grf())
337 if (!backend_instruction::can_do_source_mods())
344 fs_inst::can_change_types() const
346 return dst
.type
== src
[0].type
&&
347 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
348 (opcode
== BRW_OPCODE_MOV
||
349 (opcode
== BRW_OPCODE_SEL
&&
350 dst
.type
== src
[1].type
&&
351 predicate
!= BRW_PREDICATE_NONE
&&
352 !src
[1].abs
&& !src
[1].negate
));
356 fs_inst::has_side_effects() const
358 return this->eot
|| backend_instruction::has_side_effects();
364 memset(this, 0, sizeof(*this));
368 /** Generic unset register constructor. */
372 this->file
= BAD_FILE
;
375 /** Immediate value constructor. */
376 fs_reg::fs_reg(float f
)
380 this->type
= BRW_REGISTER_TYPE_F
;
382 this->fixed_hw_reg
.dw1
.f
= f
;
385 /** Immediate value constructor. */
386 fs_reg::fs_reg(int32_t i
)
390 this->type
= BRW_REGISTER_TYPE_D
;
392 this->fixed_hw_reg
.dw1
.d
= i
;
395 /** Immediate value constructor. */
396 fs_reg::fs_reg(uint32_t u
)
400 this->type
= BRW_REGISTER_TYPE_UD
;
402 this->fixed_hw_reg
.dw1
.ud
= u
;
405 /** Vector float immediate value constructor. */
406 fs_reg::fs_reg(uint8_t vf
[4])
410 this->type
= BRW_REGISTER_TYPE_VF
;
411 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
414 /** Vector float immediate value constructor. */
415 fs_reg::fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
419 this->type
= BRW_REGISTER_TYPE_VF
;
420 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
426 /** Fixed brw_reg. */
427 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
431 this->fixed_hw_reg
= fixed_hw_reg
;
432 this->type
= fixed_hw_reg
.type
;
436 fs_reg::equals(const fs_reg
&r
) const
438 return (file
== r
.file
&&
440 reg_offset
== r
.reg_offset
&&
441 subreg_offset
== r
.subreg_offset
&&
443 negate
== r
.negate
&&
445 !reladdr
&& !r
.reladdr
&&
446 ((file
!= HW_REG
&& file
!= IMM
) ||
447 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
448 sizeof(fixed_hw_reg
)) == 0) &&
453 fs_reg::set_smear(unsigned subreg
)
455 assert(file
!= HW_REG
&& file
!= IMM
);
456 subreg_offset
= subreg
* type_sz(type
);
462 fs_reg::is_contiguous() const
468 fs_reg::component_size(unsigned width
) const
470 const unsigned stride
= (file
!= HW_REG
? this->stride
:
471 fixed_hw_reg
.hstride
== 0 ? 0 :
472 1 << (fixed_hw_reg
.hstride
- 1));
473 return MAX2(width
* stride
, 1) * type_sz(type
);
477 type_size_scalar(const struct glsl_type
*type
)
479 unsigned int size
, i
;
481 switch (type
->base_type
) {
484 case GLSL_TYPE_FLOAT
:
486 return type
->components();
487 case GLSL_TYPE_ARRAY
:
488 return type_size_scalar(type
->fields
.array
) * type
->length
;
489 case GLSL_TYPE_STRUCT
:
491 for (i
= 0; i
< type
->length
; i
++) {
492 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
495 case GLSL_TYPE_SAMPLER
:
496 /* Samplers take up no register space, since they're baked in at
500 case GLSL_TYPE_ATOMIC_UINT
:
502 case GLSL_TYPE_SUBROUTINE
:
504 case GLSL_TYPE_IMAGE
:
505 return BRW_IMAGE_PARAM_SIZE
;
507 case GLSL_TYPE_ERROR
:
508 case GLSL_TYPE_INTERFACE
:
509 case GLSL_TYPE_DOUBLE
:
510 unreachable("not reached");
517 * Create a MOV to read the timestamp register.
519 * The caller is responsible for emitting the MOV. The return value is
520 * the destination of the MOV, with extra parameters set.
523 fs_visitor::get_timestamp(const fs_builder
&bld
)
525 assert(devinfo
->gen
>= 7);
527 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
530 BRW_REGISTER_TYPE_UD
));
532 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
534 /* We want to read the 3 fields we care about even if it's not enabled in
537 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
539 /* The caller wants the low 32 bits of the timestamp. Since it's running
540 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
541 * which is plenty of time for our purposes. It is identical across the
542 * EUs, but since it's tracking GPU core speed it will increment at a
543 * varying rate as render P-states change.
545 * The caller could also check if render P-states have changed (or anything
546 * else that might disrupt timing) by setting smear to 2 and checking if
547 * that field is != 0.
555 fs_visitor::emit_shader_time_begin()
557 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
561 fs_visitor::emit_shader_time_end()
563 /* Insert our code just before the final SEND with EOT. */
564 exec_node
*end
= this->instructions
.get_tail();
565 assert(end
&& ((fs_inst
*) end
)->eot
);
566 const fs_builder ibld
= bld
.annotate("shader time end")
567 .exec_all().at(NULL
, end
);
569 fs_reg shader_end_time
= get_timestamp(ibld
);
571 /* Check that there weren't any timestamp reset events (assuming these
572 * were the only two timestamp reads that happened).
574 fs_reg reset
= shader_end_time
;
576 set_condmod(BRW_CONDITIONAL_Z
,
577 ibld
.AND(ibld
.null_reg_ud(), reset
, fs_reg(1u)));
578 ibld
.IF(BRW_PREDICATE_NORMAL
);
580 fs_reg start
= shader_start_time
;
582 fs_reg diff
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
585 const fs_builder cbld
= ibld
.group(1, 0);
586 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
588 /* If there were no instructions between the two timestamp gets, the diff
589 * is 2 cycles. Remove that overhead, so I can forget about that when
590 * trying to determine the time taken for single instructions.
592 cbld
.ADD(diff
, diff
, fs_reg(-2u));
593 SHADER_TIME_ADD(cbld
, 0, diff
);
594 SHADER_TIME_ADD(cbld
, 1, fs_reg(1u));
595 ibld
.emit(BRW_OPCODE_ELSE
);
596 SHADER_TIME_ADD(cbld
, 2, fs_reg(1u));
597 ibld
.emit(BRW_OPCODE_ENDIF
);
601 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
602 int shader_time_subindex
,
605 int index
= shader_time_index
* 3 + shader_time_subindex
;
606 fs_reg offset
= fs_reg(index
* SHADER_TIME_STRIDE
);
609 if (dispatch_width
== 8)
610 payload
= vgrf(glsl_type::uvec2_type
);
612 payload
= vgrf(glsl_type::uint_type
);
614 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
618 fs_visitor::vfail(const char *format
, va_list va
)
627 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
628 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
630 this->fail_msg
= msg
;
633 fprintf(stderr
, "%s", msg
);
638 fs_visitor::fail(const char *format
, ...)
642 va_start(va
, format
);
648 * Mark this program as impossible to compile in SIMD16 mode.
650 * During the SIMD8 compile (which happens first), we can detect and flag
651 * things that are unsupported in SIMD16 mode, so the compiler can skip
652 * the SIMD16 compile altogether.
654 * During a SIMD16 compile (if one happens anyway), this just calls fail().
657 fs_visitor::no16(const char *msg
)
659 if (dispatch_width
== 16) {
662 simd16_unsupported
= true;
664 compiler
->shader_perf_log(log_data
,
665 "SIMD16 shader failed to compile: %s", msg
);
670 * Returns true if the instruction has a flag that means it won't
671 * update an entire destination register.
673 * For example, dead code elimination and live variable analysis want to know
674 * when a write to a variable screens off any preceding values that were in
678 fs_inst::is_partial_write() const
680 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
681 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
682 !this->dst
.is_contiguous());
686 fs_inst::components_read(unsigned i
) const
689 case FS_OPCODE_LINTERP
:
695 case FS_OPCODE_PIXEL_X
:
696 case FS_OPCODE_PIXEL_Y
:
700 case FS_OPCODE_FB_WRITE_LOGICAL
:
701 assert(src
[6].file
== IMM
);
702 /* First/second FB write color. */
704 return src
[6].fixed_hw_reg
.dw1
.ud
;
708 case SHADER_OPCODE_TEX_LOGICAL
:
709 case SHADER_OPCODE_TXD_LOGICAL
:
710 case SHADER_OPCODE_TXF_LOGICAL
:
711 case SHADER_OPCODE_TXL_LOGICAL
:
712 case SHADER_OPCODE_TXS_LOGICAL
:
713 case FS_OPCODE_TXB_LOGICAL
:
714 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
715 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
716 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
717 case SHADER_OPCODE_LOD_LOGICAL
:
718 case SHADER_OPCODE_TG4_LOGICAL
:
719 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
720 assert(src
[8].file
== IMM
&& src
[9].file
== IMM
);
721 /* Texture coordinates. */
723 return src
[8].fixed_hw_reg
.dw1
.ud
;
724 /* Texture derivatives. */
725 else if ((i
== 2 || i
== 3) && opcode
== SHADER_OPCODE_TXD_LOGICAL
)
726 return src
[9].fixed_hw_reg
.dw1
.ud
;
727 /* Texture offset. */
733 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
734 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
735 assert(src
[3].file
== IMM
);
736 /* Surface coordinates. */
738 return src
[3].fixed_hw_reg
.dw1
.ud
;
739 /* Surface operation source (ignored for reads). */
745 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
746 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
747 assert(src
[3].file
== IMM
&&
749 /* Surface coordinates. */
751 return src
[3].fixed_hw_reg
.dw1
.ud
;
752 /* Surface operation source. */
754 return src
[4].fixed_hw_reg
.dw1
.ud
;
758 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
759 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
760 assert(src
[3].file
== IMM
&&
762 const unsigned op
= src
[4].fixed_hw_reg
.dw1
.ud
;
763 /* Surface coordinates. */
765 return src
[3].fixed_hw_reg
.dw1
.ud
;
766 /* Surface operation source. */
767 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
769 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
770 op
== BRW_AOP_PREDEC
))
782 fs_inst::regs_read(int arg
) const
785 case FS_OPCODE_FB_WRITE
:
786 case SHADER_OPCODE_URB_WRITE_SIMD8
:
787 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
788 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
789 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
790 case SHADER_OPCODE_UNTYPED_ATOMIC
:
791 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
792 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
793 case SHADER_OPCODE_TYPED_ATOMIC
:
794 case SHADER_OPCODE_TYPED_SURFACE_READ
:
795 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
796 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
801 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
802 /* The payload is actually stored in src1 */
807 case FS_OPCODE_LINTERP
:
812 case SHADER_OPCODE_LOAD_PAYLOAD
:
813 if (arg
< this->header_size
)
817 case CS_OPCODE_CS_TERMINATE
:
818 case SHADER_OPCODE_BARRIER
:
822 if (is_tex() && arg
== 0 && src
[0].file
== GRF
)
827 switch (src
[arg
].file
) {
836 return DIV_ROUND_UP(components_read(arg
) *
837 src
[arg
].component_size(exec_size
),
840 unreachable("MRF registers are not allowed as sources");
842 unreachable("Invalid register file");
847 fs_inst::reads_flag() const
853 fs_inst::writes_flag() const
855 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
856 opcode
!= BRW_OPCODE_IF
&&
857 opcode
!= BRW_OPCODE_WHILE
)) ||
858 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
862 * Returns how many MRFs an FS opcode will write over.
864 * Note that this is not the 0 or 1 implied writes in an actual gen
865 * instruction -- the FS opcodes often generate MOVs in addition.
868 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
873 if (inst
->base_mrf
== -1)
876 switch (inst
->opcode
) {
877 case SHADER_OPCODE_RCP
:
878 case SHADER_OPCODE_RSQ
:
879 case SHADER_OPCODE_SQRT
:
880 case SHADER_OPCODE_EXP2
:
881 case SHADER_OPCODE_LOG2
:
882 case SHADER_OPCODE_SIN
:
883 case SHADER_OPCODE_COS
:
884 return 1 * dispatch_width
/ 8;
885 case SHADER_OPCODE_POW
:
886 case SHADER_OPCODE_INT_QUOTIENT
:
887 case SHADER_OPCODE_INT_REMAINDER
:
888 return 2 * dispatch_width
/ 8;
889 case SHADER_OPCODE_TEX
:
891 case SHADER_OPCODE_TXD
:
892 case SHADER_OPCODE_TXF
:
893 case SHADER_OPCODE_TXF_CMS
:
894 case SHADER_OPCODE_TXF_MCS
:
895 case SHADER_OPCODE_TG4
:
896 case SHADER_OPCODE_TG4_OFFSET
:
897 case SHADER_OPCODE_TXL
:
898 case SHADER_OPCODE_TXS
:
899 case SHADER_OPCODE_LOD
:
900 case SHADER_OPCODE_SAMPLEINFO
:
902 case FS_OPCODE_FB_WRITE
:
904 case FS_OPCODE_GET_BUFFER_SIZE
:
905 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
906 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
908 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
910 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
912 case SHADER_OPCODE_UNTYPED_ATOMIC
:
913 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
914 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
915 case SHADER_OPCODE_TYPED_ATOMIC
:
916 case SHADER_OPCODE_TYPED_SURFACE_READ
:
917 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
918 case SHADER_OPCODE_URB_WRITE_SIMD8
:
919 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
920 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
921 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
922 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
923 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
924 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
925 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
928 unreachable("not reached");
933 fs_visitor::vgrf(const glsl_type
*const type
)
935 int reg_width
= dispatch_width
/ 8;
936 return fs_reg(GRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
937 brw_type_for_base_type(type
));
940 /** Fixed HW reg constructor. */
941 fs_reg::fs_reg(enum register_file file
, int reg
)
946 this->type
= BRW_REGISTER_TYPE_F
;
947 this->stride
= (file
== UNIFORM
? 0 : 1);
950 /** Fixed HW reg constructor. */
951 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
)
957 this->stride
= (file
== UNIFORM
? 0 : 1);
960 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
961 * This brings in those uniform definitions
964 fs_visitor::import_uniforms(fs_visitor
*v
)
966 this->push_constant_loc
= v
->push_constant_loc
;
967 this->pull_constant_loc
= v
->pull_constant_loc
;
968 this->uniforms
= v
->uniforms
;
969 this->param_size
= v
->param_size
;
973 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
974 bool origin_upper_left
)
976 assert(stage
== MESA_SHADER_FRAGMENT
);
977 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
978 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
980 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
983 if (pixel_center_integer
) {
984 bld
.MOV(wpos
, this->pixel_x
);
986 bld
.ADD(wpos
, this->pixel_x
, fs_reg(0.5f
));
988 wpos
= offset(wpos
, bld
, 1);
991 if (!flip
&& pixel_center_integer
) {
992 bld
.MOV(wpos
, this->pixel_y
);
994 fs_reg pixel_y
= this->pixel_y
;
995 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
998 pixel_y
.negate
= true;
999 offset
+= key
->drawable_height
- 1.0f
;
1002 bld
.ADD(wpos
, pixel_y
, fs_reg(offset
));
1004 wpos
= offset(wpos
, bld
, 1);
1006 /* gl_FragCoord.z */
1007 if (devinfo
->gen
>= 6) {
1008 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1010 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1011 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1012 interp_reg(VARYING_SLOT_POS
, 2));
1014 wpos
= offset(wpos
, bld
, 1);
1016 /* gl_FragCoord.w: Already set up in emit_interpolation */
1017 bld
.MOV(wpos
, this->wpos_w
);
1023 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1024 glsl_interp_qualifier interpolation_mode
,
1025 bool is_centroid
, bool is_sample
)
1027 brw_wm_barycentric_interp_mode barycoord_mode
;
1028 if (devinfo
->gen
>= 6) {
1030 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1031 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1033 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1034 } else if (is_sample
) {
1035 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1036 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1038 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1040 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1041 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1043 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1046 /* On Ironlake and below, there is only one interpolation mode.
1047 * Centroid interpolation doesn't mean anything on this hardware --
1048 * there is no multisampling.
1050 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1052 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1053 this->delta_xy
[barycoord_mode
], interp
);
1057 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
1058 const glsl_type
*type
,
1059 glsl_interp_qualifier interpolation_mode
,
1060 int location
, bool mod_centroid
,
1063 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
1065 assert(stage
== MESA_SHADER_FRAGMENT
);
1066 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1067 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1069 unsigned int array_elements
;
1071 if (type
->is_array()) {
1072 array_elements
= type
->arrays_of_arrays_size();
1073 if (array_elements
== 0) {
1074 fail("dereferenced array '%s' has length 0\n", name
);
1076 type
= type
->without_array();
1081 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1083 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1084 if (key
->flat_shade
&& is_gl_Color
) {
1085 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1087 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1091 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1092 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1093 if (prog_data
->urb_setup
[location
] == -1) {
1094 /* If there's no incoming setup data for this slot, don't
1095 * emit interpolation for it.
1097 attr
= offset(attr
, bld
, type
->vector_elements
);
1102 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1103 /* Constant interpolation (flat shading) case. The SF has
1104 * handed us defined values in only the constant offset
1105 * field of the setup reg.
1107 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1108 struct brw_reg interp
= interp_reg(location
, k
);
1109 interp
= suboffset(interp
, 3);
1110 interp
.type
= attr
.type
;
1111 bld
.emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1112 attr
= offset(attr
, bld
, 1);
1115 /* Smooth/noperspective interpolation case. */
1116 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1117 struct brw_reg interp
= interp_reg(location
, k
);
1118 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1119 /* Get the pixel/sample mask into f0 so that we know
1120 * which pixels are lit. Then, for each channel that is
1121 * unlit, replace the centroid data with non-centroid
1124 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1127 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1129 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1130 inst
->predicate_inverse
= true;
1131 if (devinfo
->has_pln
)
1132 inst
->no_dd_clear
= true;
1134 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1135 mod_centroid
&& !key
->persample_shading
,
1136 mod_sample
|| key
->persample_shading
);
1137 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1138 inst
->predicate_inverse
= false;
1139 if (devinfo
->has_pln
)
1140 inst
->no_dd_check
= true;
1143 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1144 mod_centroid
&& !key
->persample_shading
,
1145 mod_sample
|| key
->persample_shading
);
1147 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1148 bld
.MUL(attr
, attr
, this->pixel_w
);
1150 attr
= offset(attr
, bld
, 1);
1160 fs_visitor::emit_frontfacing_interpolation()
1162 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1164 if (devinfo
->gen
>= 6) {
1165 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1166 * a boolean result from this (~0/true or 0/false).
1168 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1169 * this task in only one instruction:
1170 * - a negation source modifier will flip the bit; and
1171 * - a W -> D type conversion will sign extend the bit into the high
1172 * word of the destination.
1174 * An ASR 15 fills the low word of the destination.
1176 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1179 bld
.ASR(*reg
, g0
, fs_reg(15));
1181 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1182 * a boolean result from this (1/true or 0/false).
1184 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1185 * the negation source modifier to flip it. Unfortunately the SHR
1186 * instruction only operates on UD (or D with an abs source modifier)
1187 * sources without negation.
1189 * Instead, use ASR (which will give ~0/true or 0/false).
1191 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1194 bld
.ASR(*reg
, g1_6
, fs_reg(31));
1201 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1203 assert(stage
== MESA_SHADER_FRAGMENT
);
1204 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1205 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1207 if (key
->compute_pos_offset
) {
1208 /* Convert int_sample_pos to floating point */
1209 bld
.MOV(dst
, int_sample_pos
);
1210 /* Scale to the range [0, 1] */
1211 bld
.MUL(dst
, dst
, fs_reg(1 / 16.0f
));
1214 /* From ARB_sample_shading specification:
1215 * "When rendering to a non-multisample buffer, or if multisample
1216 * rasterization is disabled, gl_SamplePosition will always be
1219 bld
.MOV(dst
, fs_reg(0.5f
));
1224 fs_visitor::emit_samplepos_setup()
1226 assert(devinfo
->gen
>= 6);
1228 const fs_builder abld
= bld
.annotate("compute sample position");
1229 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1231 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1232 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1234 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1235 * mode will be enabled.
1237 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1238 * R31.1:0 Position Offset X/Y for Slot[3:0]
1239 * R31.3:2 Position Offset X/Y for Slot[7:4]
1242 * The X, Y sample positions come in as bytes in thread payload. So, read
1243 * the positions using vstride=16, width=8, hstride=2.
1245 struct brw_reg sample_pos_reg
=
1246 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1247 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1249 if (dispatch_width
== 8) {
1250 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1252 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1253 abld
.half(1).MOV(half(int_sample_x
, 1),
1254 fs_reg(suboffset(sample_pos_reg
, 16)));
1256 /* Compute gl_SamplePosition.x */
1257 compute_sample_position(pos
, int_sample_x
);
1258 pos
= offset(pos
, abld
, 1);
1259 if (dispatch_width
== 8) {
1260 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1262 abld
.half(0).MOV(half(int_sample_y
, 0),
1263 fs_reg(suboffset(sample_pos_reg
, 1)));
1264 abld
.half(1).MOV(half(int_sample_y
, 1),
1265 fs_reg(suboffset(sample_pos_reg
, 17)));
1267 /* Compute gl_SamplePosition.y */
1268 compute_sample_position(pos
, int_sample_y
);
1273 fs_visitor::emit_sampleid_setup()
1275 assert(stage
== MESA_SHADER_FRAGMENT
);
1276 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1277 assert(devinfo
->gen
>= 6);
1279 const fs_builder abld
= bld
.annotate("compute sample id");
1280 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1282 if (key
->compute_sample_id
) {
1283 fs_reg t1
= vgrf(glsl_type::int_type
);
1284 fs_reg t2
= vgrf(glsl_type::int_type
);
1285 t2
.type
= BRW_REGISTER_TYPE_UW
;
1287 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1288 * 8x multisampling, subspan 0 will represent sample N (where N
1289 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1290 * 7. We can find the value of N by looking at R0.0 bits 7:6
1291 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1292 * (since samples are always delivered in pairs). That is, we
1293 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1294 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1295 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1296 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1297 * populating a temporary variable with the sequence (0, 1, 2, 3),
1298 * and then reading from it using vstride=1, width=4, hstride=0.
1299 * These computations hold good for 4x multisampling as well.
1301 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1302 * the first four slots are sample 0 of subspan 0; the next four
1303 * are sample 1 of subspan 0; the third group is sample 0 of
1304 * subspan 1, and finally sample 1 of subspan 1.
1307 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1309 abld
.exec_all().SHR(t1
, t1
, fs_reg(5));
1311 /* This works for both SIMD8 and SIMD16 */
1313 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1315 /* This special instruction takes care of setting vstride=1,
1316 * width=4, hstride=0 of t2 during an ADD instruction.
1318 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1320 /* As per GL_ARB_sample_shading specification:
1321 * "When rendering to a non-multisample buffer, or if multisample
1322 * rasterization is disabled, gl_SampleID will always be zero."
1324 abld
.MOV(*reg
, fs_reg(0));
1331 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1333 if (!src
.abs
&& !src
.negate
)
1336 fs_reg temp
= bld
.vgrf(src
.type
);
1343 fs_visitor::emit_discard_jump()
1345 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1347 /* For performance, after a discard, jump to the end of the
1348 * shader if all relevant channels have been discarded.
1350 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1351 discard_jump
->flag_subreg
= 1;
1353 discard_jump
->predicate
= (dispatch_width
== 8)
1354 ? BRW_PREDICATE_ALIGN1_ANY8H
1355 : BRW_PREDICATE_ALIGN1_ANY16H
;
1356 discard_jump
->predicate_inverse
= true;
1360 fs_visitor::assign_curb_setup()
1362 if (dispatch_width
== 8) {
1363 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1365 if (stage
== MESA_SHADER_FRAGMENT
) {
1366 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1367 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1368 } else if (stage
== MESA_SHADER_COMPUTE
) {
1369 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1370 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1372 unreachable("Unsupported shader type!");
1376 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1378 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1379 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1380 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1381 if (inst
->src
[i
].file
== UNIFORM
) {
1382 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1384 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1385 constant_nr
= push_constant_loc
[uniform_nr
];
1387 /* Section 5.11 of the OpenGL 4.1 spec says:
1388 * "Out-of-bounds reads return undefined values, which include
1389 * values from other variables of the active program or zero."
1390 * Just return the first push constant.
1395 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1399 assert(inst
->src
[i
].stride
== 0);
1400 inst
->src
[i
].file
= HW_REG
;
1401 inst
->src
[i
].fixed_hw_reg
= byte_offset(
1402 retype(brw_reg
, inst
->src
[i
].type
),
1403 inst
->src
[i
].subreg_offset
);
1408 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1409 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1413 fs_visitor::calculate_urb_setup()
1415 assert(stage
== MESA_SHADER_FRAGMENT
);
1416 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1417 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1419 memset(prog_data
->urb_setup
, -1,
1420 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1423 /* Figure out where each of the incoming setup attributes lands. */
1424 if (devinfo
->gen
>= 6) {
1425 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1426 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1427 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1428 * first 16 varying inputs, so we can put them wherever we want.
1429 * Just put them in order.
1431 * This is useful because it means that (a) inputs not used by the
1432 * fragment shader won't take up valuable register space, and (b) we
1433 * won't have to recompile the fragment shader if it gets paired with
1434 * a different vertex (or geometry) shader.
1436 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1437 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1438 BITFIELD64_BIT(i
)) {
1439 prog_data
->urb_setup
[i
] = urb_next
++;
1443 /* We have enough input varyings that the SF/SBE pipeline stage can't
1444 * arbitrarily rearrange them to suit our whim; we have to put them
1445 * in an order that matches the output of the previous pipeline stage
1446 * (geometry or vertex shader).
1448 struct brw_vue_map prev_stage_vue_map
;
1449 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1450 key
->input_slots_valid
,
1451 nir
->info
.separate_shader
);
1452 int first_slot
= 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1453 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1454 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1456 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1457 /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
1460 if (varying
!= BRW_VARYING_SLOT_COUNT
&&
1461 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1462 BITFIELD64_BIT(varying
))) {
1463 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1466 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1469 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1470 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1471 /* Point size is packed into the header, not as a general attribute */
1472 if (i
== VARYING_SLOT_PSIZ
)
1475 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1476 /* The back color slot is skipped when the front color is
1477 * also written to. In addition, some slots can be
1478 * written in the vertex shader and not read in the
1479 * fragment shader. So the register number must always be
1480 * incremented, mapped or not.
1482 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1483 prog_data
->urb_setup
[i
] = urb_next
;
1489 * It's a FS only attribute, and we did interpolation for this attribute
1490 * in SF thread. So, count it here, too.
1492 * See compile_sf_prog() for more info.
1494 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1495 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1498 prog_data
->num_varying_inputs
= urb_next
;
1502 fs_visitor::assign_urb_setup()
1504 assert(stage
== MESA_SHADER_FRAGMENT
);
1505 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1507 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1509 /* Offset all the urb_setup[] index by the actual position of the
1510 * setup regs, now that the location of the constants has been chosen.
1512 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1513 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1514 assert(inst
->src
[1].file
== HW_REG
);
1515 inst
->src
[1].fixed_hw_reg
.nr
+= urb_start
;
1518 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1519 assert(inst
->src
[0].file
== HW_REG
);
1520 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1524 /* Each attribute is 4 setup channels, each of which is half a reg. */
1525 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1529 fs_visitor::assign_vs_urb_setup()
1531 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1533 assert(stage
== MESA_SHADER_VERTEX
);
1534 int count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1535 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1538 /* Each attribute is 4 regs. */
1539 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attributes
;
1541 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1543 /* Rewrite all ATTR file references to the hw grf that they land in. */
1544 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1545 for (int i
= 0; i
< inst
->sources
; i
++) {
1546 if (inst
->src
[i
].file
== ATTR
) {
1547 int grf
= payload
.num_regs
+
1548 prog_data
->curb_read_length
+
1550 inst
->src
[i
].reg_offset
;
1552 inst
->src
[i
].file
= HW_REG
;
1553 inst
->src
[i
].fixed_hw_reg
=
1554 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1555 inst
->src
[i
].subreg_offset
),
1556 inst
->exec_size
* inst
->src
[i
].stride
,
1557 inst
->exec_size
, inst
->src
[i
].stride
);
1564 * Split large virtual GRFs into separate components if we can.
1566 * This is mostly duplicated with what brw_fs_vector_splitting does,
1567 * but that's really conservative because it's afraid of doing
1568 * splitting that doesn't result in real progress after the rest of
1569 * the optimization phases, which would cause infinite looping in
1570 * optimization. We can do it once here, safely. This also has the
1571 * opportunity to split interpolated values, or maybe even uniforms,
1572 * which we don't have at the IR level.
1574 * We want to split, because virtual GRFs are what we register
1575 * allocate and spill (due to contiguousness requirements for some
1576 * instructions), and they're what we naturally generate in the
1577 * codegen process, but most virtual GRFs don't actually need to be
1578 * contiguous sets of GRFs. If we split, we'll end up with reduced
1579 * live intervals and better dead code elimination and coalescing.
1582 fs_visitor::split_virtual_grfs()
1584 int num_vars
= this->alloc
.count
;
1586 /* Count the total number of registers */
1588 int vgrf_to_reg
[num_vars
];
1589 for (int i
= 0; i
< num_vars
; i
++) {
1590 vgrf_to_reg
[i
] = reg_count
;
1591 reg_count
+= alloc
.sizes
[i
];
1594 /* An array of "split points". For each register slot, this indicates
1595 * if this slot can be separated from the previous slot. Every time an
1596 * instruction uses multiple elements of a register (as a source or
1597 * destination), we mark the used slots as inseparable. Then we go
1598 * through and split the registers into the smallest pieces we can.
1600 bool split_points
[reg_count
];
1601 memset(split_points
, 0, sizeof(split_points
));
1603 /* Mark all used registers as fully splittable */
1604 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1605 if (inst
->dst
.file
== GRF
) {
1606 int reg
= vgrf_to_reg
[inst
->dst
.reg
];
1607 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.reg
]; j
++)
1608 split_points
[reg
+ j
] = true;
1611 for (int i
= 0; i
< inst
->sources
; i
++) {
1612 if (inst
->src
[i
].file
== GRF
) {
1613 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
];
1614 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].reg
]; j
++)
1615 split_points
[reg
+ j
] = true;
1620 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1621 if (inst
->dst
.file
== GRF
) {
1622 int reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1623 for (int j
= 1; j
< inst
->regs_written
; j
++)
1624 split_points
[reg
+ j
] = false;
1626 for (int i
= 0; i
< inst
->sources
; i
++) {
1627 if (inst
->src
[i
].file
== GRF
) {
1628 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1629 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1630 split_points
[reg
+ j
] = false;
1635 int new_virtual_grf
[reg_count
];
1636 int new_reg_offset
[reg_count
];
1639 for (int i
= 0; i
< num_vars
; i
++) {
1640 /* The first one should always be 0 as a quick sanity check. */
1641 assert(split_points
[reg
] == false);
1644 new_reg_offset
[reg
] = 0;
1649 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1650 /* If this is a split point, reset the offset to 0 and allocate a
1651 * new virtual GRF for the previous offset many registers
1653 if (split_points
[reg
]) {
1654 assert(offset
<= MAX_VGRF_SIZE
);
1655 int grf
= alloc
.allocate(offset
);
1656 for (int k
= reg
- offset
; k
< reg
; k
++)
1657 new_virtual_grf
[k
] = grf
;
1660 new_reg_offset
[reg
] = offset
;
1665 /* The last one gets the original register number */
1666 assert(offset
<= MAX_VGRF_SIZE
);
1667 alloc
.sizes
[i
] = offset
;
1668 for (int k
= reg
- offset
; k
< reg
; k
++)
1669 new_virtual_grf
[k
] = i
;
1671 assert(reg
== reg_count
);
1673 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1674 if (inst
->dst
.file
== GRF
) {
1675 reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1676 inst
->dst
.reg
= new_virtual_grf
[reg
];
1677 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1678 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1680 for (int i
= 0; i
< inst
->sources
; i
++) {
1681 if (inst
->src
[i
].file
== GRF
) {
1682 reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1683 inst
->src
[i
].reg
= new_virtual_grf
[reg
];
1684 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1685 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1689 invalidate_live_intervals();
1693 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1695 * During code generation, we create tons of temporary variables, many of
1696 * which get immediately killed and are never used again. Yet, in later
1697 * optimization and analysis passes, such as compute_live_intervals, we need
1698 * to loop over all the virtual GRFs. Compacting them can save a lot of
1702 fs_visitor::compact_virtual_grfs()
1704 bool progress
= false;
1705 int remap_table
[this->alloc
.count
];
1706 memset(remap_table
, -1, sizeof(remap_table
));
1708 /* Mark which virtual GRFs are used. */
1709 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1710 if (inst
->dst
.file
== GRF
)
1711 remap_table
[inst
->dst
.reg
] = 0;
1713 for (int i
= 0; i
< inst
->sources
; i
++) {
1714 if (inst
->src
[i
].file
== GRF
)
1715 remap_table
[inst
->src
[i
].reg
] = 0;
1719 /* Compact the GRF arrays. */
1721 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1722 if (remap_table
[i
] == -1) {
1723 /* We just found an unused register. This means that we are
1724 * actually going to compact something.
1728 remap_table
[i
] = new_index
;
1729 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1730 invalidate_live_intervals();
1735 this->alloc
.count
= new_index
;
1737 /* Patch all the instructions to use the newly renumbered registers */
1738 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1739 if (inst
->dst
.file
== GRF
)
1740 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
1742 for (int i
= 0; i
< inst
->sources
; i
++) {
1743 if (inst
->src
[i
].file
== GRF
)
1744 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
1748 /* Patch all the references to delta_xy, since they're used in register
1749 * allocation. If they're unused, switch them to BAD_FILE so we don't
1750 * think some random VGRF is delta_xy.
1752 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1753 if (delta_xy
[i
].file
== GRF
) {
1754 if (remap_table
[delta_xy
[i
].reg
] != -1) {
1755 delta_xy
[i
].reg
= remap_table
[delta_xy
[i
].reg
];
1757 delta_xy
[i
].file
= BAD_FILE
;
1766 * Assign UNIFORM file registers to either push constants or pull constants.
1768 * We allow a fragment shader to have more than the specified minimum
1769 * maximum number of fragment shader uniform components (64). If
1770 * there are too many of these, they'd fill up all of register space.
1771 * So, this will push some of them out to the pull constant buffer and
1772 * update the program to load them. We also use pull constants for all
1773 * indirect constant loads because we don't support indirect accesses in
1777 fs_visitor::assign_constant_locations()
1779 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1780 if (dispatch_width
!= 8)
1783 unsigned int num_pull_constants
= 0;
1785 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1786 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1788 bool is_live
[uniforms
];
1789 memset(is_live
, 0, sizeof(is_live
));
1791 /* First, we walk through the instructions and do two things:
1793 * 1) Figure out which uniforms are live.
1795 * 2) Find all indirect access of uniform arrays and flag them as needing
1796 * to go into the pull constant buffer.
1798 * Note that we don't move constant-indexed accesses to arrays. No
1799 * testing has been done of the performance impact of this choice.
1801 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1802 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1803 if (inst
->src
[i
].file
!= UNIFORM
)
1806 if (inst
->src
[i
].reladdr
) {
1807 int uniform
= inst
->src
[i
].reg
;
1809 /* If this array isn't already present in the pull constant buffer,
1812 if (pull_constant_loc
[uniform
] == -1) {
1813 assert(param_size
[uniform
]);
1814 for (int j
= 0; j
< param_size
[uniform
]; j
++)
1815 pull_constant_loc
[uniform
+ j
] = num_pull_constants
++;
1818 /* Mark the the one accessed uniform as live */
1819 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1820 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1821 is_live
[constant_nr
] = true;
1826 /* Only allow 16 registers (128 uniform components) as push constants.
1828 * Just demote the end of the list. We could probably do better
1829 * here, demoting things that are rarely used in the program first.
1831 * If changing this value, note the limitation about total_regs in
1834 unsigned int max_push_components
= 16 * 8;
1835 unsigned int num_push_constants
= 0;
1837 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1839 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1840 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1841 /* This UNIFORM register is either dead, or has already been demoted
1842 * to a pull const. Mark it as no longer living in the param[] array.
1844 push_constant_loc
[i
] = -1;
1848 if (num_push_constants
< max_push_components
) {
1849 /* Retain as a push constant. Record the location in the params[]
1852 push_constant_loc
[i
] = num_push_constants
++;
1854 /* Demote to a pull constant. */
1855 push_constant_loc
[i
] = -1;
1856 pull_constant_loc
[i
] = num_pull_constants
++;
1860 stage_prog_data
->nr_params
= num_push_constants
;
1861 stage_prog_data
->nr_pull_params
= num_pull_constants
;
1863 /* Up until now, the param[] array has been indexed by reg + reg_offset
1864 * of UNIFORM registers. Move pull constants into pull_param[] and
1865 * condense param[] to only contain the uniforms we chose to push.
1867 * NOTE: Because we are condensing the params[] array, we know that
1868 * push_constant_loc[i] <= i and we can do it in one smooth loop without
1869 * having to make a copy.
1871 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1872 const gl_constant_value
*value
= stage_prog_data
->param
[i
];
1874 if (pull_constant_loc
[i
] != -1) {
1875 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
1876 } else if (push_constant_loc
[i
] != -1) {
1877 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
1883 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
1884 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
1887 fs_visitor::demote_pull_constants()
1889 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1890 for (int i
= 0; i
< inst
->sources
; i
++) {
1891 if (inst
->src
[i
].file
!= UNIFORM
)
1895 unsigned location
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1896 if (location
>= uniforms
) /* Out of bounds access */
1899 pull_index
= pull_constant_loc
[location
];
1901 if (pull_index
== -1)
1904 /* Set up the annotation tracking for new generated instructions. */
1905 const fs_builder
ibld(this, block
, inst
);
1906 fs_reg
surf_index(stage_prog_data
->binding_table
.pull_constants_start
);
1907 fs_reg dst
= vgrf(glsl_type::float_type
);
1909 assert(inst
->src
[i
].stride
== 0);
1911 /* Generate a pull load into dst. */
1912 if (inst
->src
[i
].reladdr
) {
1913 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
1915 *inst
->src
[i
].reladdr
,
1917 inst
->src
[i
].reladdr
= NULL
;
1918 inst
->src
[i
].stride
= 1;
1920 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
1921 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
1922 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
1923 dst
, surf_index
, offset
);
1924 inst
->src
[i
].set_smear(pull_index
& 3);
1927 /* Rewrite the instruction to use the temporary VGRF. */
1928 inst
->src
[i
].file
= GRF
;
1929 inst
->src
[i
].reg
= dst
.reg
;
1930 inst
->src
[i
].reg_offset
= 0;
1933 invalidate_live_intervals();
1937 fs_visitor::opt_algebraic()
1939 bool progress
= false;
1941 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1942 switch (inst
->opcode
) {
1943 case BRW_OPCODE_MOV
:
1944 if (inst
->src
[0].file
!= IMM
)
1947 if (inst
->saturate
) {
1948 if (inst
->dst
.type
!= inst
->src
[0].type
)
1949 assert(!"unimplemented: saturate mixed types");
1951 if (brw_saturate_immediate(inst
->dst
.type
,
1952 &inst
->src
[0].fixed_hw_reg
)) {
1953 inst
->saturate
= false;
1959 case BRW_OPCODE_MUL
:
1960 if (inst
->src
[1].file
!= IMM
)
1964 if (inst
->src
[1].is_one()) {
1965 inst
->opcode
= BRW_OPCODE_MOV
;
1966 inst
->src
[1] = reg_undef
;
1972 if (inst
->src
[1].is_negative_one()) {
1973 inst
->opcode
= BRW_OPCODE_MOV
;
1974 inst
->src
[0].negate
= !inst
->src
[0].negate
;
1975 inst
->src
[1] = reg_undef
;
1981 if (inst
->src
[1].is_zero()) {
1982 inst
->opcode
= BRW_OPCODE_MOV
;
1983 inst
->src
[0] = inst
->src
[1];
1984 inst
->src
[1] = reg_undef
;
1989 if (inst
->src
[0].file
== IMM
) {
1990 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
1991 inst
->opcode
= BRW_OPCODE_MOV
;
1992 inst
->src
[0].fixed_hw_reg
.dw1
.f
*= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
1993 inst
->src
[1] = reg_undef
;
1998 case BRW_OPCODE_ADD
:
1999 if (inst
->src
[1].file
!= IMM
)
2003 if (inst
->src
[1].is_zero()) {
2004 inst
->opcode
= BRW_OPCODE_MOV
;
2005 inst
->src
[1] = reg_undef
;
2010 if (inst
->src
[0].file
== IMM
) {
2011 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2012 inst
->opcode
= BRW_OPCODE_MOV
;
2013 inst
->src
[0].fixed_hw_reg
.dw1
.f
+= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
2014 inst
->src
[1] = reg_undef
;
2020 if (inst
->src
[0].equals(inst
->src
[1])) {
2021 inst
->opcode
= BRW_OPCODE_MOV
;
2022 inst
->src
[1] = reg_undef
;
2027 case BRW_OPCODE_LRP
:
2028 if (inst
->src
[1].equals(inst
->src
[2])) {
2029 inst
->opcode
= BRW_OPCODE_MOV
;
2030 inst
->src
[0] = inst
->src
[1];
2031 inst
->src
[1] = reg_undef
;
2032 inst
->src
[2] = reg_undef
;
2037 case BRW_OPCODE_CMP
:
2038 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2040 inst
->src
[0].negate
&&
2041 inst
->src
[1].is_zero()) {
2042 inst
->src
[0].abs
= false;
2043 inst
->src
[0].negate
= false;
2044 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2049 case BRW_OPCODE_SEL
:
2050 if (inst
->src
[0].equals(inst
->src
[1])) {
2051 inst
->opcode
= BRW_OPCODE_MOV
;
2052 inst
->src
[1] = reg_undef
;
2053 inst
->predicate
= BRW_PREDICATE_NONE
;
2054 inst
->predicate_inverse
= false;
2056 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2057 switch (inst
->conditional_mod
) {
2058 case BRW_CONDITIONAL_LE
:
2059 case BRW_CONDITIONAL_L
:
2060 switch (inst
->src
[1].type
) {
2061 case BRW_REGISTER_TYPE_F
:
2062 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
>= 1.0f
) {
2063 inst
->opcode
= BRW_OPCODE_MOV
;
2064 inst
->src
[1] = reg_undef
;
2065 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2073 case BRW_CONDITIONAL_GE
:
2074 case BRW_CONDITIONAL_G
:
2075 switch (inst
->src
[1].type
) {
2076 case BRW_REGISTER_TYPE_F
:
2077 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
<= 0.0f
) {
2078 inst
->opcode
= BRW_OPCODE_MOV
;
2079 inst
->src
[1] = reg_undef
;
2080 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2092 case BRW_OPCODE_MAD
:
2093 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2094 inst
->opcode
= BRW_OPCODE_MOV
;
2095 inst
->src
[1] = reg_undef
;
2096 inst
->src
[2] = reg_undef
;
2098 } else if (inst
->src
[0].is_zero()) {
2099 inst
->opcode
= BRW_OPCODE_MUL
;
2100 inst
->src
[0] = inst
->src
[2];
2101 inst
->src
[2] = reg_undef
;
2103 } else if (inst
->src
[1].is_one()) {
2104 inst
->opcode
= BRW_OPCODE_ADD
;
2105 inst
->src
[1] = inst
->src
[2];
2106 inst
->src
[2] = reg_undef
;
2108 } else if (inst
->src
[2].is_one()) {
2109 inst
->opcode
= BRW_OPCODE_ADD
;
2110 inst
->src
[2] = reg_undef
;
2112 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2113 inst
->opcode
= BRW_OPCODE_ADD
;
2114 inst
->src
[1].fixed_hw_reg
.dw1
.f
*= inst
->src
[2].fixed_hw_reg
.dw1
.f
;
2115 inst
->src
[2] = reg_undef
;
2119 case SHADER_OPCODE_RCP
: {
2120 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2121 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2122 if (inst
->src
[0].equals(prev
->dst
)) {
2123 inst
->opcode
= SHADER_OPCODE_RSQ
;
2124 inst
->src
[0] = prev
->src
[0];
2130 case SHADER_OPCODE_BROADCAST
:
2131 if (is_uniform(inst
->src
[0])) {
2132 inst
->opcode
= BRW_OPCODE_MOV
;
2134 inst
->force_writemask_all
= true;
2136 } else if (inst
->src
[1].file
== IMM
) {
2137 inst
->opcode
= BRW_OPCODE_MOV
;
2138 inst
->src
[0] = component(inst
->src
[0],
2139 inst
->src
[1].fixed_hw_reg
.dw1
.ud
);
2141 inst
->force_writemask_all
= true;
2150 /* Swap if src[0] is immediate. */
2151 if (progress
&& inst
->is_commutative()) {
2152 if (inst
->src
[0].file
== IMM
) {
2153 fs_reg tmp
= inst
->src
[1];
2154 inst
->src
[1] = inst
->src
[0];
2163 * Optimize sample messages that have constant zero values for the trailing
2164 * texture coordinates. We can just reduce the message length for these
2165 * instructions instead of reserving a register for it. Trailing parameters
2166 * that aren't sent default to zero anyway. This will cause the dead code
2167 * eliminator to remove the MOV instruction that would otherwise be emitted to
2168 * set up the zero value.
2171 fs_visitor::opt_zero_samples()
2173 /* Gen4 infers the texturing opcode based on the message length so we can't
2176 if (devinfo
->gen
< 5)
2179 bool progress
= false;
2181 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2182 if (!inst
->is_tex())
2185 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2187 if (load_payload
->is_head_sentinel() ||
2188 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2191 /* We don't want to remove the message header or the first parameter.
2192 * Removing the first parameter is not allowed, see the Haswell PRM
2193 * volume 7, page 149:
2195 * "Parameter 0 is required except for the sampleinfo message, which
2196 * has no parameter 0"
2198 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2199 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2200 (inst
->exec_size
/ 8) +
2201 inst
->header_size
- 1].is_zero()) {
2202 inst
->mlen
-= inst
->exec_size
/ 8;
2208 invalidate_live_intervals();
2214 * Optimize sample messages which are followed by the final RT write.
2216 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2217 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2218 * final texturing results copied to the framebuffer write payload and modify
2219 * them to write to the framebuffer directly.
2222 fs_visitor::opt_sampler_eot()
2224 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2226 if (stage
!= MESA_SHADER_FRAGMENT
)
2229 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2232 /* FINISHME: It should be possible to implement this optimization when there
2233 * are multiple drawbuffers.
2235 if (key
->nr_color_regions
!= 1)
2238 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2239 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2240 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2241 assert(fb_write
->eot
);
2242 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2244 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2246 /* There wasn't one; nothing to do. */
2247 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2250 /* 3D Sampler » Messages » Message Format
2252 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2253 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2255 if (tex_inst
->opcode
== SHADER_OPCODE_TXS
||
2256 tex_inst
->opcode
== SHADER_OPCODE_SAMPLEINFO
||
2257 tex_inst
->opcode
== SHADER_OPCODE_LOD
||
2258 tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2259 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2262 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2263 * It's very likely to be the previous instruction.
2265 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2266 if (load_payload
->is_head_sentinel() ||
2267 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2270 assert(!tex_inst
->eot
); /* We can't get here twice */
2271 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2273 const fs_builder
ibld(this, block
, tex_inst
);
2275 tex_inst
->offset
|= fb_write
->target
<< 24;
2276 tex_inst
->eot
= true;
2277 tex_inst
->dst
= ibld
.null_reg_ud();
2278 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2280 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2281 * to create a new LOAD_PAYLOAD command with the same sources and a space
2282 * saved for the header. Using a new destination register not only makes sure
2283 * we have enough space, but it will make sure the dead code eliminator kills
2284 * the instruction that this will replace.
2286 if (tex_inst
->header_size
!= 0)
2289 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2290 load_payload
->sources
+ 1);
2291 fs_reg
*new_sources
=
2292 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2294 new_sources
[0] = fs_reg();
2295 for (int i
= 0; i
< load_payload
->sources
; i
++)
2296 new_sources
[i
+1] = load_payload
->src
[i
];
2298 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2299 * requires a lot of information about the sources to appropriately figure
2300 * out the number of registers needed to be used. Given this stage in our
2301 * optimization, we may not have the appropriate GRFs required by
2302 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2303 * manually emit the instruction.
2305 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2306 load_payload
->exec_size
,
2309 load_payload
->sources
+ 1);
2311 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2312 new_load_payload
->header_size
= 1;
2314 tex_inst
->header_size
= 1;
2315 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2316 tex_inst
->src
[0] = send_header
;
2322 fs_visitor::opt_register_renaming()
2324 bool progress
= false;
2327 int remap
[alloc
.count
];
2328 memset(remap
, -1, sizeof(int) * alloc
.count
);
2330 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2331 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2333 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2334 inst
->opcode
== BRW_OPCODE_WHILE
) {
2338 /* Rewrite instruction sources. */
2339 for (int i
= 0; i
< inst
->sources
; i
++) {
2340 if (inst
->src
[i
].file
== GRF
&&
2341 remap
[inst
->src
[i
].reg
] != -1 &&
2342 remap
[inst
->src
[i
].reg
] != inst
->src
[i
].reg
) {
2343 inst
->src
[i
].reg
= remap
[inst
->src
[i
].reg
];
2348 const int dst
= inst
->dst
.reg
;
2351 inst
->dst
.file
== GRF
&&
2352 alloc
.sizes
[inst
->dst
.reg
] == inst
->exec_size
/ 8 &&
2353 !inst
->is_partial_write()) {
2354 if (remap
[dst
] == -1) {
2357 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2358 inst
->dst
.reg
= remap
[dst
];
2361 } else if (inst
->dst
.file
== GRF
&&
2363 remap
[dst
] != dst
) {
2364 inst
->dst
.reg
= remap
[dst
];
2370 invalidate_live_intervals();
2372 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2373 if (delta_xy
[i
].file
== GRF
&& remap
[delta_xy
[i
].reg
] != -1) {
2374 delta_xy
[i
].reg
= remap
[delta_xy
[i
].reg
];
2383 * Remove redundant or useless discard jumps.
2385 * For example, we can eliminate jumps in the following sequence:
2387 * discard-jump (redundant with the next jump)
2388 * discard-jump (useless; jumps to the next instruction)
2392 fs_visitor::opt_redundant_discard_jumps()
2394 bool progress
= false;
2396 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2398 fs_inst
*placeholder_halt
= NULL
;
2399 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2400 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2401 placeholder_halt
= inst
;
2406 if (!placeholder_halt
)
2409 /* Delete any HALTs immediately before the placeholder halt. */
2410 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2411 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2412 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2413 prev
->remove(last_bblock
);
2418 invalidate_live_intervals();
2424 fs_visitor::compute_to_mrf()
2426 bool progress
= false;
2429 /* No MRFs on Gen >= 7. */
2430 if (devinfo
->gen
>= 7)
2433 calculate_live_intervals();
2435 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2439 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2440 inst
->is_partial_write() ||
2441 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2442 inst
->dst
.type
!= inst
->src
[0].type
||
2443 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2444 !inst
->src
[0].is_contiguous() ||
2445 inst
->src
[0].subreg_offset
)
2448 /* Work out which hardware MRF registers are written by this
2451 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2453 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2454 mrf_high
= mrf_low
+ 4;
2455 } else if (inst
->exec_size
== 16) {
2456 mrf_high
= mrf_low
+ 1;
2461 /* Can't compute-to-MRF this GRF if someone else was going to
2464 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2467 /* Found a move of a GRF to a MRF. Let's see if we can go
2468 * rewrite the thing that made this GRF to write into the MRF.
2470 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2471 if (scan_inst
->dst
.file
== GRF
&&
2472 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2473 /* Found the last thing to write our reg we want to turn
2474 * into a compute-to-MRF.
2477 /* If this one instruction didn't populate all the
2478 * channels, bail. We might be able to rewrite everything
2479 * that writes that reg, but it would require smarter
2480 * tracking to delay the rewriting until complete success.
2482 if (scan_inst
->is_partial_write())
2485 /* Things returning more than one register would need us to
2486 * understand coalescing out more than one MOV at a time.
2488 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2491 /* SEND instructions can't have MRF as a destination. */
2492 if (scan_inst
->mlen
)
2495 if (devinfo
->gen
== 6) {
2496 /* gen6 math instructions must have the destination be
2497 * GRF, so no compute-to-MRF for them.
2499 if (scan_inst
->is_math()) {
2504 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2505 /* Found the creator of our MRF's source value. */
2506 scan_inst
->dst
.file
= MRF
;
2507 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2508 scan_inst
->saturate
|= inst
->saturate
;
2509 inst
->remove(block
);
2515 /* We don't handle control flow here. Most computation of
2516 * values that end up in MRFs are shortly before the MRF
2519 if (block
->start() == scan_inst
)
2522 /* You can't read from an MRF, so if someone else reads our
2523 * MRF's source GRF that we wanted to rewrite, that stops us.
2525 bool interfered
= false;
2526 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2527 if (scan_inst
->src
[i
].file
== GRF
&&
2528 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2529 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2536 if (scan_inst
->dst
.file
== MRF
) {
2537 /* If somebody else writes our MRF here, we can't
2538 * compute-to-MRF before that.
2540 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2543 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2544 scan_mrf_high
= scan_mrf_low
+ 4;
2545 } else if (scan_inst
->exec_size
== 16) {
2546 scan_mrf_high
= scan_mrf_low
+ 1;
2548 scan_mrf_high
= scan_mrf_low
;
2551 if (mrf_low
== scan_mrf_low
||
2552 mrf_low
== scan_mrf_high
||
2553 mrf_high
== scan_mrf_low
||
2554 mrf_high
== scan_mrf_high
) {
2559 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2560 /* Found a SEND instruction, which means that there are
2561 * live values in MRFs from base_mrf to base_mrf +
2562 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2565 if (mrf_low
>= scan_inst
->base_mrf
&&
2566 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2569 if (mrf_high
>= scan_inst
->base_mrf
&&
2570 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2578 invalidate_live_intervals();
2584 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2585 * flow. We could probably do better here with some form of divergence
2589 fs_visitor::eliminate_find_live_channel()
2591 bool progress
= false;
2594 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2595 switch (inst
->opcode
) {
2601 case BRW_OPCODE_ENDIF
:
2602 case BRW_OPCODE_WHILE
:
2606 case FS_OPCODE_DISCARD_JUMP
:
2607 /* This can potentially make control flow non-uniform until the end
2612 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2614 inst
->opcode
= BRW_OPCODE_MOV
;
2615 inst
->src
[0] = fs_reg(0);
2617 inst
->force_writemask_all
= true;
2631 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2632 * instructions to FS_OPCODE_REP_FB_WRITE.
2635 fs_visitor::emit_repclear_shader()
2637 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2639 int color_mrf
= base_mrf
+ 2;
2641 fs_inst
*mov
= bld
.exec_all().MOV(vec4(brw_message_reg(color_mrf
)),
2642 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2645 if (key
->nr_color_regions
== 1) {
2646 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2647 write
->saturate
= key
->clamp_fragment_color
;
2648 write
->base_mrf
= color_mrf
;
2650 write
->header_size
= 0;
2653 assume(key
->nr_color_regions
> 0);
2654 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2655 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2656 write
->saturate
= key
->clamp_fragment_color
;
2657 write
->base_mrf
= base_mrf
;
2659 write
->header_size
= 2;
2667 assign_constant_locations();
2668 assign_curb_setup();
2670 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2671 assert(mov
->src
[0].file
== HW_REG
);
2672 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].fixed_hw_reg
.nr
, 0);
2676 * Walks through basic blocks, looking for repeated MRF writes and
2677 * removing the later ones.
2680 fs_visitor::remove_duplicate_mrf_writes()
2682 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2683 bool progress
= false;
2685 /* Need to update the MRF tracking for compressed instructions. */
2686 if (dispatch_width
== 16)
2689 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2691 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2692 if (inst
->is_control_flow()) {
2693 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2696 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2697 inst
->dst
.file
== MRF
) {
2698 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2699 if (prev_inst
&& inst
->equals(prev_inst
)) {
2700 inst
->remove(block
);
2706 /* Clear out the last-write records for MRFs that were overwritten. */
2707 if (inst
->dst
.file
== MRF
) {
2708 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2711 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2712 /* Found a SEND instruction, which will include two or fewer
2713 * implied MRF writes. We could do better here.
2715 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2716 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2720 /* Clear out any MRF move records whose sources got overwritten. */
2721 if (inst
->dst
.file
== GRF
) {
2722 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2723 if (last_mrf_move
[i
] &&
2724 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2725 last_mrf_move
[i
] = NULL
;
2730 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2731 inst
->dst
.file
== MRF
&&
2732 inst
->src
[0].file
== GRF
&&
2733 !inst
->is_partial_write()) {
2734 last_mrf_move
[inst
->dst
.reg
] = inst
;
2739 invalidate_live_intervals();
2745 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2747 /* Clear the flag for registers that actually got read (as expected). */
2748 for (int i
= 0; i
< inst
->sources
; i
++) {
2750 if (inst
->src
[i
].file
== GRF
) {
2751 grf
= inst
->src
[i
].reg
;
2752 } else if (inst
->src
[i
].file
== HW_REG
&&
2753 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
2754 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
2759 if (grf
>= first_grf
&&
2760 grf
< first_grf
+ grf_len
) {
2761 deps
[grf
- first_grf
] = false;
2762 if (inst
->exec_size
== 16)
2763 deps
[grf
- first_grf
+ 1] = false;
2769 * Implements this workaround for the original 965:
2771 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2772 * check for post destination dependencies on this instruction, software
2773 * must ensure that there is no destination hazard for the case of ‘write
2774 * followed by a posted write’ shown in the following example.
2777 * 2. send r3.xy <rest of send instruction>
2780 * Due to no post-destination dependency check on the ‘send’, the above
2781 * code sequence could have two instructions (1 and 2) in flight at the
2782 * same time that both consider ‘r3’ as the target of their final writes.
2785 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2788 int write_len
= inst
->regs_written
;
2789 int first_write_grf
= inst
->dst
.reg
;
2790 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2791 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2793 memset(needs_dep
, false, sizeof(needs_dep
));
2794 memset(needs_dep
, true, write_len
);
2796 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2798 /* Walk backwards looking for writes to registers we're writing which
2799 * aren't read since being written. If we hit the start of the program,
2800 * we assume that there are no outstanding dependencies on entry to the
2803 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2804 /* If we hit control flow, assume that there *are* outstanding
2805 * dependencies, and force their cleanup before our instruction.
2807 if (block
->start() == scan_inst
) {
2808 for (int i
= 0; i
< write_len
; i
++) {
2810 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
2811 first_write_grf
+ i
);
2816 /* We insert our reads as late as possible on the assumption that any
2817 * instruction but a MOV that might have left us an outstanding
2818 * dependency has more latency than a MOV.
2820 if (scan_inst
->dst
.file
== GRF
) {
2821 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2822 int reg
= scan_inst
->dst
.reg
+ i
;
2824 if (reg
>= first_write_grf
&&
2825 reg
< first_write_grf
+ write_len
&&
2826 needs_dep
[reg
- first_write_grf
]) {
2827 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
2828 needs_dep
[reg
- first_write_grf
] = false;
2829 if (scan_inst
->exec_size
== 16)
2830 needs_dep
[reg
- first_write_grf
+ 1] = false;
2835 /* Clear the flag for registers that actually got read (as expected). */
2836 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2838 /* Continue the loop only if we haven't resolved all the dependencies */
2840 for (i
= 0; i
< write_len
; i
++) {
2850 * Implements this workaround for the original 965:
2852 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2853 * used as a destination register until after it has been sourced by an
2854 * instruction with a different destination register.
2857 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
2859 int write_len
= inst
->regs_written
;
2860 int first_write_grf
= inst
->dst
.reg
;
2861 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2862 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2864 memset(needs_dep
, false, sizeof(needs_dep
));
2865 memset(needs_dep
, true, write_len
);
2866 /* Walk forwards looking for writes to registers we're writing which aren't
2867 * read before being written.
2869 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
2870 /* If we hit control flow, force resolve all remaining dependencies. */
2871 if (block
->end() == scan_inst
) {
2872 for (int i
= 0; i
< write_len
; i
++) {
2874 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
2875 first_write_grf
+ i
);
2880 /* Clear the flag for registers that actually got read (as expected). */
2881 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2883 /* We insert our reads as late as possible since they're reading the
2884 * result of a SEND, which has massive latency.
2886 if (scan_inst
->dst
.file
== GRF
&&
2887 scan_inst
->dst
.reg
>= first_write_grf
&&
2888 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
2889 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
2890 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
2891 scan_inst
->dst
.reg
);
2892 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
2895 /* Continue the loop only if we haven't resolved all the dependencies */
2897 for (i
= 0; i
< write_len
; i
++) {
2907 fs_visitor::insert_gen4_send_dependency_workarounds()
2909 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
2912 bool progress
= false;
2914 /* Note that we're done with register allocation, so GRF fs_regs always
2915 * have a .reg_offset of 0.
2918 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2919 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
2920 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
2921 insert_gen4_post_send_dependency_workarounds(block
, inst
);
2927 invalidate_live_intervals();
2931 * Turns the generic expression-style uniform pull constant load instruction
2932 * into a hardware-specific series of instructions for loading a pull
2935 * The expression style allows the CSE pass before this to optimize out
2936 * repeated loads from the same offset, and gives the pre-register-allocation
2937 * scheduling full flexibility, while the conversion to native instructions
2938 * allows the post-register-allocation scheduler the best information
2941 * Note that execution masking for setting up pull constant loads is special:
2942 * the channels that need to be written are unrelated to the current execution
2943 * mask, since a later instruction will use one of the result channels as a
2944 * source operand for all 8 or 16 of its channels.
2947 fs_visitor::lower_uniform_pull_constant_loads()
2949 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2950 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
2953 if (devinfo
->gen
>= 7) {
2954 /* The offset arg before was a vec4-aligned byte offset. We need to
2955 * turn it into a dword offset.
2957 fs_reg const_offset_reg
= inst
->src
[1];
2958 assert(const_offset_reg
.file
== IMM
&&
2959 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
2960 const_offset_reg
.fixed_hw_reg
.dw1
.ud
/= 4;
2962 fs_reg payload
, offset
;
2963 if (devinfo
->gen
>= 9) {
2964 /* We have to use a message header on Skylake to get SIMD4x2
2965 * mode. Reserve space for the register.
2967 offset
= payload
= fs_reg(GRF
, alloc
.allocate(2));
2968 offset
.reg_offset
++;
2971 offset
= payload
= fs_reg(GRF
, alloc
.allocate(1));
2975 /* This is actually going to be a MOV, but since only the first dword
2976 * is accessed, we have a special opcode to do just that one. Note
2977 * that this needs to be an operation that will be considered a def
2978 * by live variable analysis, or register allocation will explode.
2980 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
2981 8, offset
, const_offset_reg
);
2982 setup
->force_writemask_all
= true;
2984 setup
->ir
= inst
->ir
;
2985 setup
->annotation
= inst
->annotation
;
2986 inst
->insert_before(block
, setup
);
2988 /* Similarly, this will only populate the first 4 channels of the
2989 * result register (since we only use smear values from 0-3), but we
2990 * don't tell the optimizer.
2992 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
2993 inst
->src
[1] = payload
;
2994 inst
->base_mrf
= -1;
2996 invalidate_live_intervals();
2998 /* Before register allocation, we didn't tell the scheduler about the
2999 * MRF we use. We know it's safe to use this MRF because nothing
3000 * else does except for register spill/unspill, which generates and
3001 * uses its MRF within a single IR instruction.
3003 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3010 fs_visitor::lower_load_payload()
3012 bool progress
= false;
3014 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3015 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3018 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== GRF
);
3019 assert(inst
->saturate
== false);
3020 fs_reg dst
= inst
->dst
;
3022 /* Get rid of COMPR4. We'll add it back in if we need it */
3023 if (dst
.file
== MRF
)
3024 dst
.reg
= dst
.reg
& ~BRW_MRF_COMPR4
;
3026 const fs_builder
ibld(this, block
, inst
);
3027 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3029 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3030 if (inst
->src
[i
].file
!= BAD_FILE
) {
3031 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3032 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3033 hbld
.MOV(mov_dst
, mov_src
);
3035 dst
= offset(dst
, hbld
, 1);
3038 if (inst
->dst
.file
== MRF
&& (inst
->dst
.reg
& BRW_MRF_COMPR4
) &&
3039 inst
->exec_size
> 8) {
3040 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3041 * a straightforward copy. Instead, the result of the
3042 * LOAD_PAYLOAD is treated as interleaved and the first four
3043 * non-header sources are unpacked as:
3054 * This is used for gen <= 5 fb writes.
3056 assert(inst
->exec_size
== 16);
3057 assert(inst
->header_size
+ 4 <= inst
->sources
);
3058 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3059 if (inst
->src
[i
].file
!= BAD_FILE
) {
3060 if (devinfo
->has_compr4
) {
3061 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3062 compr4_dst
.reg
|= BRW_MRF_COMPR4
;
3063 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3065 /* Platform doesn't have COMPR4. We have to fake it */
3066 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3067 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3069 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3076 /* The loop above only ever incremented us through the first set
3077 * of 4 registers. However, thanks to the magic of COMPR4, we
3078 * actually wrote to the first 8 registers, so we need to take
3079 * that into account now.
3083 /* The COMPR4 code took care of the first 4 sources. We'll let
3084 * the regular path handle any remaining sources. Yes, we are
3085 * modifying the instruction but we're about to delete it so
3086 * this really doesn't hurt anything.
3088 inst
->header_size
+= 4;
3091 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3092 if (inst
->src
[i
].file
!= BAD_FILE
)
3093 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3094 dst
= offset(dst
, ibld
, 1);
3097 inst
->remove(block
);
3102 invalidate_live_intervals();
3108 fs_visitor::lower_integer_multiplication()
3110 bool progress
= false;
3112 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3113 const fs_builder
ibld(this, block
, inst
);
3115 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3116 if (inst
->dst
.is_accumulator() ||
3117 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3118 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3121 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3122 * operation directly, but CHV/BXT cannot.
3124 if (devinfo
->gen
>= 8 &&
3125 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3128 if (inst
->src
[1].file
== IMM
&&
3129 inst
->src
[1].fixed_hw_reg
.dw1
.ud
< (1 << 16)) {
3130 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3131 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3134 * If multiplying by an immediate value that fits in 16-bits, do a
3135 * single MUL instruction with that value in the proper location.
3137 if (devinfo
->gen
< 7) {
3138 fs_reg
imm(GRF
, alloc
.allocate(dispatch_width
/ 8),
3140 ibld
.MOV(imm
, inst
->src
[1]);
3141 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3143 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3146 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3147 * do 32-bit integer multiplication in one instruction, but instead
3148 * must do a sequence (which actually calculates a 64-bit result):
3150 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3151 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3152 * mov(8) g2<1>D acc0<8,8,1>D
3154 * But on Gen > 6, the ability to use second accumulator register
3155 * (acc1) for non-float data types was removed, preventing a simple
3156 * implementation in SIMD16. A 16-channel result can be calculated by
3157 * executing the three instructions twice in SIMD8, once with quarter
3158 * control of 1Q for the first eight channels and again with 2Q for
3159 * the second eight channels.
3161 * Which accumulator register is implicitly accessed (by AccWrEnable
3162 * for instance) is determined by the quarter control. Unfortunately
3163 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3164 * implicit accumulator access by an instruction with 2Q will access
3165 * acc1 regardless of whether the data type is usable in acc1.
3167 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3168 * integer data types.
3170 * Since we only want the low 32-bits of the result, we can do two
3171 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3172 * adjust the high result and add them (like the mach is doing):
3174 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3175 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3176 * shl(8) g9<1>D g8<8,8,1>D 16D
3177 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3179 * We avoid the shl instruction by realizing that we only want to add
3180 * the low 16-bits of the "high" result to the high 16-bits of the
3181 * "low" result and using proper regioning on the add:
3183 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3184 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3185 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3187 * Since it does not use the (single) accumulator register, we can
3188 * schedule multi-component multiplications much better.
3191 fs_reg orig_dst
= inst
->dst
;
3192 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3193 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
3196 fs_reg low
= inst
->dst
;
3197 fs_reg
high(GRF
, alloc
.allocate(dispatch_width
/ 8),
3200 if (devinfo
->gen
>= 7) {
3201 fs_reg src1_0_w
= inst
->src
[1];
3202 fs_reg src1_1_w
= inst
->src
[1];
3204 if (inst
->src
[1].file
== IMM
) {
3205 src1_0_w
.fixed_hw_reg
.dw1
.ud
&= 0xffff;
3206 src1_1_w
.fixed_hw_reg
.dw1
.ud
>>= 16;
3208 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3209 if (src1_0_w
.stride
!= 0) {
3210 assert(src1_0_w
.stride
== 1);
3211 src1_0_w
.stride
= 2;
3214 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3215 if (src1_1_w
.stride
!= 0) {
3216 assert(src1_1_w
.stride
== 1);
3217 src1_1_w
.stride
= 2;
3219 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3221 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3222 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3224 fs_reg src0_0_w
= inst
->src
[0];
3225 fs_reg src0_1_w
= inst
->src
[0];
3227 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3228 if (src0_0_w
.stride
!= 0) {
3229 assert(src0_0_w
.stride
== 1);
3230 src0_0_w
.stride
= 2;
3233 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3234 if (src0_1_w
.stride
!= 0) {
3235 assert(src0_1_w
.stride
== 1);
3236 src0_1_w
.stride
= 2;
3238 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3240 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3241 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3244 fs_reg dst
= inst
->dst
;
3245 dst
.type
= BRW_REGISTER_TYPE_UW
;
3246 dst
.subreg_offset
= 2;
3249 high
.type
= BRW_REGISTER_TYPE_UW
;
3252 low
.type
= BRW_REGISTER_TYPE_UW
;
3253 low
.subreg_offset
= 2;
3256 ibld
.ADD(dst
, low
, high
);
3258 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3259 set_condmod(inst
->conditional_mod
,
3260 ibld
.MOV(orig_dst
, inst
->dst
));
3264 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3265 /* Should have been lowered to 8-wide. */
3266 assert(inst
->exec_size
<= 8);
3267 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3269 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3270 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3272 if (devinfo
->gen
>= 8) {
3273 /* Until Gen8, integer multiplies read 32-bits from one source,
3274 * and 16-bits from the other, and relying on the MACH instruction
3275 * to generate the high bits of the result.
3277 * On Gen8, the multiply instruction does a full 32x32-bit
3278 * multiply, but in order to do a 64-bit multiply we can simulate
3279 * the previous behavior and then use a MACH instruction.
3281 * FINISHME: Don't use source modifiers on src1.
3283 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3284 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3285 mul
->src
[1].type
= (type_is_signed(mul
->src
[1].type
) ?
3286 BRW_REGISTER_TYPE_W
: BRW_REGISTER_TYPE_UW
);
3287 mul
->src
[1].stride
*= 2;
3289 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3290 inst
->force_sechalf
) {
3291 /* Among other things the quarter control bits influence which
3292 * accumulator register is used by the hardware for instructions
3293 * that access the accumulator implicitly (e.g. MACH). A
3294 * second-half instruction would normally map to acc1, which
3295 * doesn't exist on Gen7 and up (the hardware does emulate it for
3296 * floating-point instructions *only* by taking advantage of the
3297 * extra precision of acc0 not normally used for floating point
3300 * HSW and up are careful enough not to try to access an
3301 * accumulator register that doesn't exist, but on earlier Gen7
3302 * hardware we need to make sure that the quarter control bits are
3303 * zero to avoid non-deterministic behaviour and emit an extra MOV
3304 * to get the result masked correctly according to the current
3307 mach
->force_sechalf
= false;
3308 mach
->force_writemask_all
= true;
3309 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3310 ibld
.MOV(inst
->dst
, mach
->dst
);
3316 inst
->remove(block
);
3321 invalidate_live_intervals();
3327 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3328 fs_reg
*dst
, fs_reg color
, unsigned components
)
3330 if (key
->clamp_fragment_color
) {
3331 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3332 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3334 for (unsigned i
= 0; i
< components
; i
++)
3336 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3341 for (unsigned i
= 0; i
< components
; i
++)
3342 dst
[i
] = offset(color
, bld
, i
);
3346 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3347 const brw_wm_prog_data
*prog_data
,
3348 const brw_wm_prog_key
*key
,
3349 const fs_visitor::thread_payload
&payload
)
3351 assert(inst
->src
[6].file
== IMM
);
3352 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3353 const fs_reg
&color0
= inst
->src
[0];
3354 const fs_reg
&color1
= inst
->src
[1];
3355 const fs_reg
&src0_alpha
= inst
->src
[2];
3356 const fs_reg
&src_depth
= inst
->src
[3];
3357 const fs_reg
&dst_depth
= inst
->src
[4];
3358 fs_reg sample_mask
= inst
->src
[5];
3359 const unsigned components
= inst
->src
[6].fixed_hw_reg
.dw1
.ud
;
3361 /* We can potentially have a message length of up to 15, so we have to set
3362 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3365 int header_size
= 2, payload_header_size
;
3366 unsigned length
= 0;
3368 /* From the Sandy Bridge PRM, volume 4, page 198:
3370 * "Dispatched Pixel Enables. One bit per pixel indicating
3371 * which pixels were originally enabled when the thread was
3372 * dispatched. This field is only required for the end-of-
3373 * thread message and on all dual-source messages."
3375 if (devinfo
->gen
>= 6 &&
3376 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3377 color1
.file
== BAD_FILE
&&
3378 key
->nr_color_regions
== 1) {
3382 if (header_size
!= 0) {
3383 assert(header_size
== 2);
3384 /* Allocate 2 registers for a header */
3388 if (payload
.aa_dest_stencil_reg
) {
3389 sources
[length
] = fs_reg(GRF
, bld
.shader
->alloc
.allocate(1));
3390 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3391 .MOV(sources
[length
],
3392 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3396 if (prog_data
->uses_omask
) {
3397 sources
[length
] = fs_reg(GRF
, bld
.shader
->alloc
.allocate(1),
3398 BRW_REGISTER_TYPE_UD
);
3400 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3401 * relevant. Since it's unsigned single words one vgrf is always
3402 * 16-wide, but only the lower or higher 8 channels will be used by the
3403 * hardware when doing a SIMD8 write depending on whether we have
3404 * selected the subspans for the first or second half respectively.
3406 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3407 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3408 sample_mask
.stride
*= 2;
3410 bld
.exec_all().annotate("FB write oMask")
3411 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3412 inst
->force_sechalf
),
3417 payload_header_size
= length
;
3419 if (src0_alpha
.file
!= BAD_FILE
) {
3420 /* FIXME: This is being passed at the wrong location in the payload and
3421 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3422 * It's supposed to be immediately before oMask but there seems to be no
3423 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3424 * requires header sources to form a contiguous segment at the beginning
3425 * of the message and src0_alpha has per-channel semantics.
3427 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3431 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3434 if (color1
.file
!= BAD_FILE
) {
3435 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3439 if (src_depth
.file
!= BAD_FILE
) {
3440 sources
[length
] = src_depth
;
3444 if (dst_depth
.file
!= BAD_FILE
) {
3445 sources
[length
] = dst_depth
;
3450 if (devinfo
->gen
>= 7) {
3451 /* Send from the GRF */
3452 fs_reg payload
= fs_reg(GRF
, -1, BRW_REGISTER_TYPE_F
);
3453 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3454 payload
.reg
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3455 load
->dst
= payload
;
3457 inst
->src
[0] = payload
;
3458 inst
->resize_sources(1);
3459 inst
->base_mrf
= -1;
3461 /* Send from the MRF */
3462 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3463 sources
, length
, payload_header_size
);
3465 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3466 * will do this for us if we just give it a COMPR4 destination.
3468 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3469 load
->dst
.reg
|= BRW_MRF_COMPR4
;
3471 inst
->resize_sources(0);
3475 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3476 inst
->mlen
= load
->regs_written
;
3477 inst
->header_size
= header_size
;
3481 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3482 const fs_reg
&coordinate
,
3483 const fs_reg
&shadow_c
,
3484 const fs_reg
&lod
, const fs_reg
&lod2
,
3485 const fs_reg
&sampler
,
3486 unsigned coord_components
,
3487 unsigned grad_components
)
3489 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3490 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3491 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3492 fs_reg msg_end
= msg_begin
;
3495 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3497 for (unsigned i
= 0; i
< coord_components
; i
++)
3498 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3499 offset(coordinate
, bld
, i
));
3501 msg_end
= offset(msg_end
, bld
, coord_components
);
3503 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3504 * require all three components to be present and zero if they are unused.
3506 if (coord_components
> 0 &&
3507 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3508 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3509 for (unsigned i
= coord_components
; i
< 3; i
++)
3510 bld
.MOV(offset(msg_end
, bld
, i
), fs_reg(0.0f
));
3512 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3515 if (op
== SHADER_OPCODE_TXD
) {
3516 /* TXD unsupported in SIMD16 mode. */
3517 assert(bld
.dispatch_width() == 8);
3519 /* the slots for u and v are always present, but r is optional */
3520 if (coord_components
< 2)
3521 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3524 * dPdx = dudx, dvdx, drdx
3525 * dPdy = dudy, dvdy, drdy
3527 * 1-arg: Does not exist.
3529 * 2-arg: dudx dvdx dudy dvdy
3530 * dPdx.x dPdx.y dPdy.x dPdy.y
3533 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3534 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3535 * m5 m6 m7 m8 m9 m10
3537 for (unsigned i
= 0; i
< grad_components
; i
++)
3538 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3540 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3542 for (unsigned i
= 0; i
< grad_components
; i
++)
3543 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3545 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3549 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3550 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3552 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3553 bld
.dispatch_width() == 16);
3555 const brw_reg_type type
=
3556 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3557 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3558 bld
.MOV(retype(msg_end
, type
), lod
);
3559 msg_end
= offset(msg_end
, bld
, 1);
3562 if (shadow_c
.file
!= BAD_FILE
) {
3563 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3564 /* There's no plain shadow compare message, so we use shadow
3565 * compare with a bias of 0.0.
3567 bld
.MOV(msg_end
, fs_reg(0.0f
));
3568 msg_end
= offset(msg_end
, bld
, 1);
3571 bld
.MOV(msg_end
, shadow_c
);
3572 msg_end
= offset(msg_end
, bld
, 1);
3576 inst
->src
[0] = reg_undef
;
3577 inst
->src
[1] = sampler
;
3578 inst
->resize_sources(2);
3579 inst
->base_mrf
= msg_begin
.reg
;
3580 inst
->mlen
= msg_end
.reg
- msg_begin
.reg
;
3581 inst
->header_size
= 1;
3585 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3587 const fs_reg
&shadow_c
,
3588 fs_reg lod
, fs_reg lod2
,
3589 const fs_reg
&sample_index
,
3590 const fs_reg
&sampler
,
3591 const fs_reg
&offset_value
,
3592 unsigned coord_components
,
3593 unsigned grad_components
)
3595 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3596 fs_reg msg_coords
= message
;
3597 unsigned header_size
= 0;
3599 if (offset_value
.file
!= BAD_FILE
) {
3600 /* The offsets set up by the visitor are in the m1 header, so we can't
3607 for (unsigned i
= 0; i
< coord_components
; i
++) {
3608 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3609 coordinate
= offset(coordinate
, bld
, 1);
3611 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3612 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3614 if (shadow_c
.file
!= BAD_FILE
) {
3615 fs_reg msg_shadow
= msg_lod
;
3616 bld
.MOV(msg_shadow
, shadow_c
);
3617 msg_lod
= offset(msg_shadow
, bld
, 1);
3622 case SHADER_OPCODE_TXL
:
3624 bld
.MOV(msg_lod
, lod
);
3625 msg_end
= offset(msg_lod
, bld
, 1);
3627 case SHADER_OPCODE_TXD
:
3630 * dPdx = dudx, dvdx, drdx
3631 * dPdy = dudy, dvdy, drdy
3633 * Load up these values:
3634 * - dudx dudy dvdx dvdy drdx drdy
3635 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3638 for (unsigned i
= 0; i
< grad_components
; i
++) {
3639 bld
.MOV(msg_end
, lod
);
3640 lod
= offset(lod
, bld
, 1);
3641 msg_end
= offset(msg_end
, bld
, 1);
3643 bld
.MOV(msg_end
, lod2
);
3644 lod2
= offset(lod2
, bld
, 1);
3645 msg_end
= offset(msg_end
, bld
, 1);
3648 case SHADER_OPCODE_TXS
:
3649 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3650 bld
.MOV(msg_lod
, lod
);
3651 msg_end
= offset(msg_lod
, bld
, 1);
3653 case SHADER_OPCODE_TXF
:
3654 msg_lod
= offset(msg_coords
, bld
, 3);
3655 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3656 msg_end
= offset(msg_lod
, bld
, 1);
3658 case SHADER_OPCODE_TXF_CMS
:
3659 msg_lod
= offset(msg_coords
, bld
, 3);
3661 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u));
3663 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3664 msg_end
= offset(msg_lod
, bld
, 2);
3671 inst
->src
[0] = reg_undef
;
3672 inst
->src
[1] = sampler
;
3673 inst
->resize_sources(2);
3674 inst
->base_mrf
= message
.reg
;
3675 inst
->mlen
= msg_end
.reg
- message
.reg
;
3676 inst
->header_size
= header_size
;
3678 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3679 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3683 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3685 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3688 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
3692 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3694 const fs_reg
&shadow_c
,
3695 fs_reg lod
, fs_reg lod2
,
3696 const fs_reg
&sample_index
,
3697 const fs_reg
&mcs
, const fs_reg
&sampler
,
3698 fs_reg offset_value
,
3699 unsigned coord_components
,
3700 unsigned grad_components
)
3702 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3703 int reg_width
= bld
.dispatch_width() / 8;
3704 unsigned header_size
= 0, length
= 0;
3705 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3706 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3707 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3709 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3710 offset_value
.file
!= BAD_FILE
||
3711 is_high_sampler(devinfo
, sampler
)) {
3712 /* For general texture offsets (no txf workaround), we need a header to
3713 * put them in. Note that we're only reserving space for it in the
3714 * message payload as it will be initialized implicitly by the
3717 * TG4 needs to place its channel select in the header, for interaction
3718 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3719 * larger sampler numbers we need to offset the Sampler State Pointer in
3723 sources
[0] = fs_reg();
3727 if (shadow_c
.file
!= BAD_FILE
) {
3728 bld
.MOV(sources
[length
], shadow_c
);
3732 bool coordinate_done
= false;
3734 /* The sampler can only meaningfully compute LOD for fragment shader
3735 * messages. For all other stages, we change the opcode to TXL and
3736 * hardcode the LOD to 0.
3738 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3739 op
== SHADER_OPCODE_TEX
) {
3740 op
= SHADER_OPCODE_TXL
;
3744 /* Set up the LOD info */
3747 case SHADER_OPCODE_TXL
:
3748 bld
.MOV(sources
[length
], lod
);
3751 case SHADER_OPCODE_TXD
:
3752 /* TXD should have been lowered in SIMD16 mode. */
3753 assert(bld
.dispatch_width() == 8);
3755 /* Load dPdx and the coordinate together:
3756 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3758 for (unsigned i
= 0; i
< coord_components
; i
++) {
3759 bld
.MOV(sources
[length
], coordinate
);
3760 coordinate
= offset(coordinate
, bld
, 1);
3763 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3764 * only derivatives for (u, v, r).
3766 if (i
< grad_components
) {
3767 bld
.MOV(sources
[length
], lod
);
3768 lod
= offset(lod
, bld
, 1);
3771 bld
.MOV(sources
[length
], lod2
);
3772 lod2
= offset(lod2
, bld
, 1);
3777 coordinate_done
= true;
3779 case SHADER_OPCODE_TXS
:
3780 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
3783 case SHADER_OPCODE_TXF
:
3784 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
3785 * On Gen9 they are u, v, lod, r
3787 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3788 coordinate
= offset(coordinate
, bld
, 1);
3791 if (devinfo
->gen
>= 9) {
3792 if (coord_components
>= 2) {
3793 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3794 coordinate
= offset(coordinate
, bld
, 1);
3799 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
3802 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
3803 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3804 coordinate
= offset(coordinate
, bld
, 1);
3808 coordinate_done
= true;
3810 case SHADER_OPCODE_TXF_CMS
:
3811 case SHADER_OPCODE_TXF_UMS
:
3812 case SHADER_OPCODE_TXF_MCS
:
3813 if (op
== SHADER_OPCODE_TXF_UMS
|| op
== SHADER_OPCODE_TXF_CMS
) {
3814 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
3818 if (op
== SHADER_OPCODE_TXF_CMS
) {
3819 /* Data from the multisample control surface. */
3820 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
3824 /* There is no offsetting for this message; just copy in the integer
3825 * texture coordinates.
3827 for (unsigned i
= 0; i
< coord_components
; i
++) {
3828 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3829 coordinate
= offset(coordinate
, bld
, 1);
3833 coordinate_done
= true;
3835 case SHADER_OPCODE_TG4_OFFSET
:
3836 /* gather4_po_c should have been lowered in SIMD16 mode. */
3837 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
3839 /* More crazy intermixing */
3840 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
3841 bld
.MOV(sources
[length
], coordinate
);
3842 coordinate
= offset(coordinate
, bld
, 1);
3846 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
3847 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
3848 offset_value
= offset(offset_value
, bld
, 1);
3852 if (coord_components
== 3) { /* r if present */
3853 bld
.MOV(sources
[length
], coordinate
);
3854 coordinate
= offset(coordinate
, bld
, 1);
3858 coordinate_done
= true;
3864 /* Set up the coordinate (except for cases where it was done above) */
3865 if (!coordinate_done
) {
3866 for (unsigned i
= 0; i
< coord_components
; i
++) {
3867 bld
.MOV(sources
[length
], coordinate
);
3868 coordinate
= offset(coordinate
, bld
, 1);
3875 mlen
= length
* reg_width
- header_size
;
3877 mlen
= length
* reg_width
;
3879 const fs_reg src_payload
= fs_reg(GRF
, bld
.shader
->alloc
.allocate(mlen
),
3880 BRW_REGISTER_TYPE_F
);
3881 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
3883 /* Generate the SEND. */
3885 inst
->src
[0] = src_payload
;
3886 inst
->src
[1] = sampler
;
3887 inst
->resize_sources(2);
3888 inst
->base_mrf
= -1;
3890 inst
->header_size
= header_size
;
3892 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3893 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3897 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
3899 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3900 const fs_reg
&coordinate
= inst
->src
[0];
3901 const fs_reg
&shadow_c
= inst
->src
[1];
3902 const fs_reg
&lod
= inst
->src
[2];
3903 const fs_reg
&lod2
= inst
->src
[3];
3904 const fs_reg
&sample_index
= inst
->src
[4];
3905 const fs_reg
&mcs
= inst
->src
[5];
3906 const fs_reg
&sampler
= inst
->src
[6];
3907 const fs_reg
&offset_value
= inst
->src
[7];
3908 assert(inst
->src
[8].file
== IMM
&& inst
->src
[9].file
== IMM
);
3909 const unsigned coord_components
= inst
->src
[8].fixed_hw_reg
.dw1
.ud
;
3910 const unsigned grad_components
= inst
->src
[9].fixed_hw_reg
.dw1
.ud
;
3912 if (devinfo
->gen
>= 7) {
3913 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
3914 shadow_c
, lod
, lod2
, sample_index
,
3915 mcs
, sampler
, offset_value
,
3916 coord_components
, grad_components
);
3917 } else if (devinfo
->gen
>= 5) {
3918 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
3919 shadow_c
, lod
, lod2
, sample_index
,
3920 sampler
, offset_value
,
3921 coord_components
, grad_components
);
3923 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
3924 shadow_c
, lod
, lod2
, sampler
,
3925 coord_components
, grad_components
);
3930 * Initialize the header present in some typed and untyped surface
3934 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
3936 fs_builder ubld
= bld
.exec_all().group(8, 0);
3937 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3938 ubld
.MOV(dst
, fs_reg(0));
3939 ubld
.MOV(component(dst
, 7), sample_mask
);
3944 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3945 const fs_reg
&sample_mask
)
3947 /* Get the logical send arguments. */
3948 const fs_reg
&addr
= inst
->src
[0];
3949 const fs_reg
&src
= inst
->src
[1];
3950 const fs_reg
&surface
= inst
->src
[2];
3951 const UNUSED fs_reg
&dims
= inst
->src
[3];
3952 const fs_reg
&arg
= inst
->src
[4];
3954 /* Calculate the total number of components of the payload. */
3955 const unsigned addr_sz
= inst
->components_read(0);
3956 const unsigned src_sz
= inst
->components_read(1);
3957 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
3958 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
3960 /* Allocate space for the payload. */
3961 fs_reg
*const components
= new fs_reg
[sz
];
3962 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
3965 /* Construct the payload. */
3967 components
[n
++] = emit_surface_header(bld
, sample_mask
);
3969 for (unsigned i
= 0; i
< addr_sz
; i
++)
3970 components
[n
++] = offset(addr
, bld
, i
);
3972 for (unsigned i
= 0; i
< src_sz
; i
++)
3973 components
[n
++] = offset(src
, bld
, i
);
3975 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
3977 /* Update the original instruction. */
3979 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
3980 inst
->header_size
= header_sz
;
3982 inst
->src
[0] = payload
;
3983 inst
->src
[1] = surface
;
3985 inst
->resize_sources(3);
3987 delete[] components
;
3991 fs_visitor::lower_logical_sends()
3993 bool progress
= false;
3995 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3996 const fs_builder
ibld(this, block
, inst
);
3998 switch (inst
->opcode
) {
3999 case FS_OPCODE_FB_WRITE_LOGICAL
:
4000 assert(stage
== MESA_SHADER_FRAGMENT
);
4001 lower_fb_write_logical_send(ibld
, inst
,
4002 (const brw_wm_prog_data
*)prog_data
,
4003 (const brw_wm_prog_key
*)key
,
4007 case SHADER_OPCODE_TEX_LOGICAL
:
4008 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4011 case SHADER_OPCODE_TXD_LOGICAL
:
4012 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4015 case SHADER_OPCODE_TXF_LOGICAL
:
4016 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4019 case SHADER_OPCODE_TXL_LOGICAL
:
4020 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4023 case SHADER_OPCODE_TXS_LOGICAL
:
4024 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4027 case FS_OPCODE_TXB_LOGICAL
:
4028 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4031 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4032 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4035 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4036 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4039 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4040 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4043 case SHADER_OPCODE_LOD_LOGICAL
:
4044 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4047 case SHADER_OPCODE_TG4_LOGICAL
:
4048 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4051 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4052 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4055 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4056 lower_surface_logical_send(ibld
, inst
,
4057 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4061 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4062 lower_surface_logical_send(ibld
, inst
,
4063 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4064 ibld
.sample_mask_reg());
4067 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4068 lower_surface_logical_send(ibld
, inst
,
4069 SHADER_OPCODE_UNTYPED_ATOMIC
,
4070 ibld
.sample_mask_reg());
4073 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4074 lower_surface_logical_send(ibld
, inst
,
4075 SHADER_OPCODE_TYPED_SURFACE_READ
,
4079 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4080 lower_surface_logical_send(ibld
, inst
,
4081 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4082 ibld
.sample_mask_reg());
4085 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4086 lower_surface_logical_send(ibld
, inst
,
4087 SHADER_OPCODE_TYPED_ATOMIC
,
4088 ibld
.sample_mask_reg());
4099 invalidate_live_intervals();
4105 * Get the closest native SIMD width supported by the hardware for instruction
4106 * \p inst. The instruction will be left untouched by
4107 * fs_visitor::lower_simd_width() if the returned value is equal to the
4108 * original execution size.
4111 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4112 const fs_inst
*inst
)
4114 switch (inst
->opcode
) {
4115 case BRW_OPCODE_MOV
:
4116 case BRW_OPCODE_SEL
:
4117 case BRW_OPCODE_NOT
:
4118 case BRW_OPCODE_AND
:
4120 case BRW_OPCODE_XOR
:
4121 case BRW_OPCODE_SHR
:
4122 case BRW_OPCODE_SHL
:
4123 case BRW_OPCODE_ASR
:
4124 case BRW_OPCODE_CMP
:
4125 case BRW_OPCODE_CMPN
:
4126 case BRW_OPCODE_CSEL
:
4127 case BRW_OPCODE_F32TO16
:
4128 case BRW_OPCODE_F16TO32
:
4129 case BRW_OPCODE_BFREV
:
4130 case BRW_OPCODE_BFE
:
4131 case BRW_OPCODE_BFI1
:
4132 case BRW_OPCODE_BFI2
:
4133 case BRW_OPCODE_ADD
:
4134 case BRW_OPCODE_MUL
:
4135 case BRW_OPCODE_AVG
:
4136 case BRW_OPCODE_FRC
:
4137 case BRW_OPCODE_RNDU
:
4138 case BRW_OPCODE_RNDD
:
4139 case BRW_OPCODE_RNDE
:
4140 case BRW_OPCODE_RNDZ
:
4141 case BRW_OPCODE_LZD
:
4142 case BRW_OPCODE_FBH
:
4143 case BRW_OPCODE_FBL
:
4144 case BRW_OPCODE_CBIT
:
4145 case BRW_OPCODE_SAD2
:
4146 case BRW_OPCODE_MAD
:
4147 case BRW_OPCODE_LRP
:
4148 case SHADER_OPCODE_RCP
:
4149 case SHADER_OPCODE_RSQ
:
4150 case SHADER_OPCODE_SQRT
:
4151 case SHADER_OPCODE_EXP2
:
4152 case SHADER_OPCODE_LOG2
:
4153 case SHADER_OPCODE_POW
:
4154 case SHADER_OPCODE_INT_QUOTIENT
:
4155 case SHADER_OPCODE_INT_REMAINDER
:
4156 case SHADER_OPCODE_SIN
:
4157 case SHADER_OPCODE_COS
: {
4158 /* According to the PRMs:
4159 * "A. In Direct Addressing mode, a source cannot span more than 2
4160 * adjacent GRF registers.
4161 * B. A destination cannot span more than 2 adjacent GRF registers."
4163 * Look for the source or destination with the largest register region
4164 * which is the one that is going to limit the overal execution size of
4165 * the instruction due to this rule.
4167 unsigned reg_count
= inst
->regs_written
;
4169 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4170 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4172 /* Calculate the maximum execution size of the instruction based on the
4173 * factor by which it goes over the hardware limit of 2 GRFs.
4175 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4177 case SHADER_OPCODE_MULH
:
4178 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4179 * is 8-wide on Gen7+.
4181 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4183 case FS_OPCODE_FB_WRITE_LOGICAL
:
4184 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4187 assert(devinfo
->gen
!= 6 || inst
->src
[3].file
== BAD_FILE
||
4188 inst
->exec_size
== 8);
4189 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4190 return (inst
->src
[1].file
!= BAD_FILE
? 8 : inst
->exec_size
);
4192 case SHADER_OPCODE_TXD_LOGICAL
:
4193 /* TXD is unsupported in SIMD16 mode. */
4196 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4197 /* gather4_po_c is unsupported in SIMD16 mode. */
4198 const fs_reg
&shadow_c
= inst
->src
[1];
4199 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4201 case SHADER_OPCODE_TXL_LOGICAL
:
4202 case FS_OPCODE_TXB_LOGICAL
: {
4203 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4204 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4205 * mode because the message exceeds the maximum length of 11.
4207 const fs_reg
&shadow_c
= inst
->src
[1];
4208 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4210 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4213 return inst
->exec_size
;
4215 case SHADER_OPCODE_TXF_LOGICAL
:
4216 case SHADER_OPCODE_TXS_LOGICAL
:
4217 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4218 * messages. Use SIMD16 instead.
4220 if (devinfo
->gen
== 4)
4223 return inst
->exec_size
;
4225 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4226 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4227 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4231 return inst
->exec_size
;
4236 * The \p rows array of registers represents a \p num_rows by \p num_columns
4237 * matrix in row-major order, write it in column-major order into the register
4238 * passed as destination. \p stride gives the separation between matrix
4239 * elements in the input in fs_builder::dispatch_width() units.
4242 emit_transpose(const fs_builder
&bld
,
4243 const fs_reg
&dst
, const fs_reg
*rows
,
4244 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4246 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4248 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4249 for (unsigned j
= 0; j
< num_rows
; ++j
)
4250 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4253 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4255 delete[] components
;
4259 fs_visitor::lower_simd_width()
4261 bool progress
= false;
4263 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4264 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4266 if (lower_width
!= inst
->exec_size
) {
4267 /* Builder matching the original instruction. We may also need to
4268 * emit an instruction of width larger than the original, set the
4269 * execution size of the builder to the highest of both for now so
4270 * we're sure that both cases can be handled.
4272 const fs_builder ibld
= bld
.at(block
, inst
)
4273 .exec_all(inst
->force_writemask_all
)
4274 .group(MAX2(inst
->exec_size
, lower_width
),
4275 inst
->force_sechalf
);
4277 /* Split the copies in chunks of the execution width of either the
4278 * original or the lowered instruction, whichever is lower.
4280 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4281 const unsigned n
= inst
->exec_size
/ copy_width
;
4282 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4283 inst
->dst
.component_size(inst
->exec_size
);
4286 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4287 !inst
->writes_accumulator
&& !inst
->mlen
);
4289 for (unsigned i
= 0; i
< n
; i
++) {
4290 /* Emit a copy of the original instruction with the lowered width.
4291 * If the EOT flag was set throw it away except for the last
4292 * instruction to avoid killing the thread prematurely.
4294 fs_inst split_inst
= *inst
;
4295 split_inst
.exec_size
= lower_width
;
4296 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4298 /* Select the correct channel enables for the i-th group, then
4299 * transform the sources and destination and emit the lowered
4302 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4304 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4305 if (inst
->src
[j
].file
!= BAD_FILE
&&
4306 !is_uniform(inst
->src
[j
])) {
4307 /* Get the i-th copy_width-wide chunk of the source. */
4308 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4309 const unsigned src_size
= inst
->components_read(j
);
4311 /* Use a trivial transposition to copy one every n
4312 * copy_width-wide components of the register into a
4313 * temporary passed as source to the lowered instruction.
4315 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4316 emit_transpose(lbld
.group(copy_width
, 0),
4317 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4321 if (inst
->regs_written
) {
4322 /* Allocate enough space to hold the result of the lowered
4323 * instruction and fix up the number of registers written.
4325 split_inst
.dst
= dsts
[i
] =
4326 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4327 split_inst
.regs_written
=
4328 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4332 lbld
.emit(split_inst
);
4335 if (inst
->regs_written
) {
4336 /* Distance between useful channels in the temporaries, skipping
4337 * garbage if the lowered instruction is wider than the original.
4339 const unsigned m
= lower_width
/ copy_width
;
4341 /* Interleave the components of the result from the lowered
4342 * instructions. We need to set exec_all() when copying more than
4343 * one half per component, because LOAD_PAYLOAD (in terms of which
4344 * emit_transpose is implemented) can only use the same channel
4345 * enable signals for all of its non-header sources.
4347 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4348 .group(copy_width
, 0),
4349 inst
->dst
, dsts
, n
, dst_size
, m
);
4352 inst
->remove(block
);
4358 invalidate_live_intervals();
4364 fs_visitor::dump_instructions()
4366 dump_instructions(NULL
);
4370 fs_visitor::dump_instructions(const char *name
)
4372 FILE *file
= stderr
;
4373 if (name
&& geteuid() != 0) {
4374 file
= fopen(name
, "w");
4380 calculate_register_pressure();
4381 int ip
= 0, max_pressure
= 0;
4382 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4383 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4384 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4385 dump_instruction(inst
, file
);
4388 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4391 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4392 fprintf(file
, "%4d: ", ip
++);
4393 dump_instruction(inst
, file
);
4397 if (file
!= stderr
) {
4403 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4405 dump_instruction(be_inst
, stderr
);
4409 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4411 fs_inst
*inst
= (fs_inst
*)be_inst
;
4413 if (inst
->predicate
) {
4414 fprintf(file
, "(%cf0.%d) ",
4415 inst
->predicate_inverse
? '-' : '+',
4419 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4421 fprintf(file
, ".sat");
4422 if (inst
->conditional_mod
) {
4423 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4424 if (!inst
->predicate
&&
4425 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4426 inst
->opcode
!= BRW_OPCODE_IF
&&
4427 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4428 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4431 fprintf(file
, "(%d) ", inst
->exec_size
);
4434 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4437 switch (inst
->dst
.file
) {
4439 fprintf(file
, "vgrf%d", inst
->dst
.reg
);
4440 if (alloc
.sizes
[inst
->dst
.reg
] != inst
->regs_written
||
4441 inst
->dst
.subreg_offset
)
4442 fprintf(file
, "+%d.%d",
4443 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4446 fprintf(file
, "m%d", inst
->dst
.reg
);
4449 fprintf(file
, "(null)");
4452 fprintf(file
, "***u%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
4455 fprintf(file
, "***attr%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
4458 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
4459 switch (inst
->dst
.fixed_hw_reg
.nr
) {
4461 fprintf(file
, "null");
4463 case BRW_ARF_ADDRESS
:
4464 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
4466 case BRW_ARF_ACCUMULATOR
:
4467 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
4470 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
4471 inst
->dst
.fixed_hw_reg
.subnr
);
4474 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
4475 inst
->dst
.fixed_hw_reg
.subnr
);
4479 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
4481 if (inst
->dst
.fixed_hw_reg
.subnr
)
4482 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
4485 fprintf(file
, "???");
4488 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4490 for (int i
= 0; i
< inst
->sources
; i
++) {
4491 if (inst
->src
[i
].negate
)
4493 if (inst
->src
[i
].abs
)
4495 switch (inst
->src
[i
].file
) {
4497 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
4498 if (alloc
.sizes
[inst
->src
[i
].reg
] != (unsigned)inst
->regs_read(i
) ||
4499 inst
->src
[i
].subreg_offset
)
4500 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4501 inst
->src
[i
].subreg_offset
);
4504 fprintf(file
, "***m%d***", inst
->src
[i
].reg
);
4507 fprintf(file
, "attr%d+%d", inst
->src
[i
].reg
, inst
->src
[i
].reg_offset
);
4510 fprintf(file
, "u%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
4511 if (inst
->src
[i
].reladdr
) {
4512 fprintf(file
, "+reladdr");
4513 } else if (inst
->src
[i
].subreg_offset
) {
4514 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4515 inst
->src
[i
].subreg_offset
);
4519 fprintf(file
, "(null)");
4522 switch (inst
->src
[i
].type
) {
4523 case BRW_REGISTER_TYPE_F
:
4524 fprintf(file
, "%ff", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
4526 case BRW_REGISTER_TYPE_W
:
4527 case BRW_REGISTER_TYPE_D
:
4528 fprintf(file
, "%dd", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
4530 case BRW_REGISTER_TYPE_UW
:
4531 case BRW_REGISTER_TYPE_UD
:
4532 fprintf(file
, "%uu", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
4534 case BRW_REGISTER_TYPE_VF
:
4535 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4536 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
4537 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
4538 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
4539 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
4542 fprintf(file
, "???");
4547 if (inst
->src
[i
].fixed_hw_reg
.negate
)
4549 if (inst
->src
[i
].fixed_hw_reg
.abs
)
4551 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
4552 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
4554 fprintf(file
, "null");
4556 case BRW_ARF_ADDRESS
:
4557 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4559 case BRW_ARF_ACCUMULATOR
:
4560 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4563 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
4564 inst
->src
[i
].fixed_hw_reg
.subnr
);
4567 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
4568 inst
->src
[i
].fixed_hw_reg
.subnr
);
4572 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
4574 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
4575 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4576 if (inst
->src
[i
].fixed_hw_reg
.abs
)
4580 fprintf(file
, "???");
4583 if (inst
->src
[i
].abs
)
4586 if (inst
->src
[i
].file
!= IMM
) {
4587 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4590 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4591 fprintf(file
, ", ");
4596 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4597 if (inst
->force_sechalf
)
4598 fprintf(file
, "2ndhalf ");
4600 fprintf(file
, "1sthalf ");
4603 fprintf(file
, "\n");
4607 * Possibly returns an instruction that set up @param reg.
4609 * Sometimes we want to take the result of some expression/variable
4610 * dereference tree and rewrite the instruction generating the result
4611 * of the tree. When processing the tree, we know that the
4612 * instructions generated are all writing temporaries that are dead
4613 * outside of this tree. So, if we have some instructions that write
4614 * a temporary, we're free to point that temp write somewhere else.
4616 * Note that this doesn't guarantee that the instruction generated
4617 * only reg -- it might be the size=4 destination of a texture instruction.
4620 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4625 end
->is_partial_write() ||
4627 !reg
.equals(end
->dst
)) {
4635 fs_visitor::setup_payload_gen6()
4638 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
4639 unsigned barycentric_interp_modes
=
4640 (stage
== MESA_SHADER_FRAGMENT
) ?
4641 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4643 assert(devinfo
->gen
>= 6);
4645 /* R0-1: masks, pixel X/Y coordinates. */
4646 payload
.num_regs
= 2;
4647 /* R2: only for 32-pixel dispatch.*/
4649 /* R3-26: barycentric interpolation coordinates. These appear in the
4650 * same order that they appear in the brw_wm_barycentric_interp_mode
4651 * enum. Each set of coordinates occupies 2 registers if dispatch width
4652 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4653 * appear if they were enabled using the "Barycentric Interpolation
4654 * Mode" bits in WM_STATE.
4656 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4657 if (barycentric_interp_modes
& (1 << i
)) {
4658 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4659 payload
.num_regs
+= 2;
4660 if (dispatch_width
== 16) {
4661 payload
.num_regs
+= 2;
4666 /* R27: interpolated depth if uses source depth */
4668 payload
.source_depth_reg
= payload
.num_regs
;
4670 if (dispatch_width
== 16) {
4671 /* R28: interpolated depth if not SIMD8. */
4675 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4677 payload
.source_w_reg
= payload
.num_regs
;
4679 if (dispatch_width
== 16) {
4680 /* R30: interpolated W if not SIMD8. */
4685 if (stage
== MESA_SHADER_FRAGMENT
) {
4686 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4687 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4688 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4689 /* R31: MSAA position offsets. */
4690 if (prog_data
->uses_pos_offset
) {
4691 payload
.sample_pos_reg
= payload
.num_regs
;
4696 /* R32: MSAA input coverage mask */
4697 if (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
4698 assert(devinfo
->gen
>= 7);
4699 payload
.sample_mask_in_reg
= payload
.num_regs
;
4701 if (dispatch_width
== 16) {
4702 /* R33: input coverage mask if not SIMD8. */
4707 /* R34-: bary for 32-pixel. */
4708 /* R58-59: interp W for 32-pixel. */
4710 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4711 source_depth_to_render_target
= true;
4716 fs_visitor::setup_vs_payload()
4718 /* R0: thread header, R1: urb handles */
4719 payload
.num_regs
= 2;
4723 * We are building the local ID push constant data using the simplest possible
4724 * method. We simply push the local IDs directly as they should appear in the
4725 * registers for the uvec3 gl_LocalInvocationID variable.
4727 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
4728 * registers worth of push constant space.
4730 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
4731 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
4734 * FINISHME: There are a few easy optimizations to consider.
4736 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
4737 * no need for using push constant space for that dimension.
4739 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
4740 * easily use 16-bit words rather than 32-bit dwords in the push constant
4743 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
4744 * conveying the data, and thereby reduce push constant usage.
4748 fs_visitor::setup_cs_payload()
4750 assert(devinfo
->gen
>= 7);
4751 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
4753 payload
.num_regs
= 1;
4755 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
4756 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
4757 payload
.local_invocation_id_reg
= payload
.num_regs
;
4758 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
4763 fs_visitor::calculate_register_pressure()
4765 invalidate_live_intervals();
4766 calculate_live_intervals();
4768 unsigned num_instructions
= 0;
4769 foreach_block(block
, cfg
)
4770 num_instructions
+= block
->instructions
.length();
4772 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
4774 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
4775 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
4776 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
4781 fs_visitor::optimize()
4783 /* Start by validating the shader we currently have. */
4786 /* bld is the common builder object pointing at the end of the program we
4787 * used to translate it into i965 IR. For the optimization and lowering
4788 * passes coming next, any code added after the end of the program without
4789 * having explicitly called fs_builder::at() clearly points at a mistake.
4790 * Ideally optimization passes wouldn't be part of the visitor so they
4791 * wouldn't have access to bld at all, but they do, so just in case some
4792 * pass forgets to ask for a location explicitly set it to NULL here to
4793 * make it trip. The dispatch width is initialized to a bogus value to
4794 * make sure that optimizations set the execution controls explicitly to
4795 * match the code they are manipulating instead of relying on the defaults.
4797 bld
= fs_builder(this, 64);
4799 assign_constant_locations();
4800 demote_pull_constants();
4804 split_virtual_grfs();
4807 #define OPT(pass, args...) ({ \
4809 bool this_progress = pass(args); \
4811 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
4812 char filename[64]; \
4813 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
4814 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
4816 backend_shader::dump_instructions(filename); \
4821 progress = progress || this_progress; \
4825 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
4827 snprintf(filename
, 64, "%s%d-%s-00-start",
4828 stage_abbrev
, dispatch_width
, nir
->info
.name
);
4830 backend_shader::dump_instructions(filename
);
4833 bool progress
= false;
4837 OPT(lower_simd_width
);
4838 OPT(lower_logical_sends
);
4845 OPT(remove_duplicate_mrf_writes
);
4849 OPT(opt_copy_propagate
);
4850 OPT(opt_predicated_break
, this);
4851 OPT(opt_cmod_propagation
);
4852 OPT(dead_code_eliminate
);
4853 OPT(opt_peephole_sel
);
4854 OPT(dead_control_flow_eliminate
, this);
4855 OPT(opt_register_renaming
);
4856 OPT(opt_redundant_discard_jumps
);
4857 OPT(opt_saturate_propagation
);
4858 OPT(opt_zero_samples
);
4859 OPT(register_coalesce
);
4860 OPT(compute_to_mrf
);
4861 OPT(eliminate_find_live_channel
);
4863 OPT(compact_virtual_grfs
);
4868 OPT(opt_sampler_eot
);
4870 if (OPT(lower_load_payload
)) {
4871 split_virtual_grfs();
4872 OPT(register_coalesce
);
4873 OPT(compute_to_mrf
);
4874 OPT(dead_code_eliminate
);
4877 OPT(opt_combine_constants
);
4878 OPT(lower_integer_multiplication
);
4880 lower_uniform_pull_constant_loads();
4886 * Three source instruction must have a GRF/MRF destination register.
4887 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
4890 fs_visitor::fixup_3src_null_dest()
4892 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
4893 if (inst
->is_3src() && inst
->dst
.is_null()) {
4894 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
4901 fs_visitor::allocate_registers()
4903 bool allocated_without_spills
;
4905 static const enum instruction_scheduler_mode pre_modes
[] = {
4907 SCHEDULE_PRE_NON_LIFO
,
4911 /* Try each scheduling heuristic to see if it can successfully register
4912 * allocate without spilling. They should be ordered by decreasing
4913 * performance but increasing likelihood of allocating.
4915 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
4916 schedule_instructions(pre_modes
[i
]);
4919 assign_regs_trivial();
4920 allocated_without_spills
= true;
4922 allocated_without_spills
= assign_regs(false);
4924 if (allocated_without_spills
)
4928 if (!allocated_without_spills
) {
4929 /* We assume that any spilling is worse than just dropping back to
4930 * SIMD8. There's probably actually some intermediate point where
4931 * SIMD16 with a couple of spills is still better.
4933 if (dispatch_width
== 16) {
4934 fail("Failure to register allocate. Reduce number of "
4935 "live scalar values to avoid this.");
4937 compiler
->shader_perf_log(log_data
,
4938 "%s shader triggered register spilling. "
4939 "Try reducing the number of live scalar "
4940 "values to improve performance.\n",
4944 /* Since we're out of heuristics, just go spill registers until we
4945 * get an allocation.
4947 while (!assign_regs(true)) {
4953 /* This must come after all optimization and register allocation, since
4954 * it inserts dead code that happens to have side effects, and it does
4955 * so based on the actual physical registers in use.
4957 insert_gen4_send_dependency_workarounds();
4962 if (!allocated_without_spills
)
4963 schedule_instructions(SCHEDULE_POST
);
4965 if (last_scratch
> 0)
4966 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
4970 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
4972 assert(stage
== MESA_SHADER_VERTEX
);
4976 if (shader_time_index
>= 0)
4977 emit_shader_time_begin();
4984 compute_clip_distance(clip_planes
);
4988 if (shader_time_index
>= 0)
4989 emit_shader_time_end();
4995 assign_curb_setup();
4996 assign_vs_urb_setup();
4998 fixup_3src_null_dest();
4999 allocate_registers();
5005 fs_visitor::run_fs(bool do_rep_send
)
5007 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5008 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
5010 assert(stage
== MESA_SHADER_FRAGMENT
);
5012 if (devinfo
->gen
>= 6)
5013 setup_payload_gen6();
5015 setup_payload_gen4();
5019 } else if (do_rep_send
) {
5020 assert(dispatch_width
== 16);
5021 emit_repclear_shader();
5023 if (shader_time_index
>= 0)
5024 emit_shader_time_begin();
5026 calculate_urb_setup();
5027 if (nir
->info
.inputs_read
> 0) {
5028 if (devinfo
->gen
< 6)
5029 emit_interpolation_setup_gen4();
5031 emit_interpolation_setup_gen6();
5034 /* We handle discards by keeping track of the still-live pixels in f0.1.
5035 * Initialize it with the dispatched pixels.
5037 if (wm_prog_data
->uses_kill
) {
5038 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5039 discard_init
->flag_subreg
= 1;
5042 /* Generate FS IR for main(). (the visitor only descends into
5043 * functions called "main").
5050 if (wm_prog_data
->uses_kill
)
5051 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5053 if (wm_key
->alpha_test_func
)
5058 if (shader_time_index
>= 0)
5059 emit_shader_time_end();
5065 assign_curb_setup();
5068 fixup_3src_null_dest();
5069 allocate_registers();
5075 if (dispatch_width
== 8)
5076 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5078 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5084 fs_visitor::run_cs()
5086 assert(stage
== MESA_SHADER_COMPUTE
);
5090 if (shader_time_index
>= 0)
5091 emit_shader_time_begin();
5098 emit_cs_terminate();
5100 if (shader_time_index
>= 0)
5101 emit_shader_time_end();
5107 assign_curb_setup();
5109 fixup_3src_null_dest();
5110 allocate_registers();
5119 * Return a bitfield where bit n is set if barycentric interpolation mode n
5120 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
5123 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
5124 bool shade_model_flat
,
5125 bool persample_shading
,
5126 const nir_shader
*shader
)
5128 unsigned barycentric_interp_modes
= 0;
5130 nir_foreach_variable(var
, &shader
->inputs
) {
5131 enum glsl_interp_qualifier interp_qualifier
=
5132 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5133 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
5134 bool is_sample
= var
->data
.sample
|| persample_shading
;
5135 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5136 (var
->data
.location
== VARYING_SLOT_COL1
);
5138 /* Ignore WPOS and FACE, because they don't require interpolation. */
5139 if (var
->data
.location
== VARYING_SLOT_POS
||
5140 var
->data
.location
== VARYING_SLOT_FACE
)
5143 /* Determine the set (or sets) of barycentric coordinates needed to
5144 * interpolate this variable. Note that when
5145 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
5146 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
5147 * for lit pixels, so we need both sets of barycentric coordinates.
5149 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
5151 barycentric_interp_modes
|=
5152 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
5153 } else if (is_sample
) {
5154 barycentric_interp_modes
|=
5155 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
5157 if ((!is_centroid
&& !is_sample
) ||
5158 devinfo
->needs_unlit_centroid_workaround
) {
5159 barycentric_interp_modes
|=
5160 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
5162 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
5163 (!(shade_model_flat
&& is_gl_Color
) &&
5164 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
5166 barycentric_interp_modes
|=
5167 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
5168 } else if (is_sample
) {
5169 barycentric_interp_modes
|=
5170 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
5172 if ((!is_centroid
&& !is_sample
) ||
5173 devinfo
->needs_unlit_centroid_workaround
) {
5174 barycentric_interp_modes
|=
5175 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
5180 return barycentric_interp_modes
;
5184 computed_depth_mode(const nir_shader
*shader
)
5186 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5187 switch (shader
->info
.fs
.depth_layout
) {
5188 case FRAG_DEPTH_LAYOUT_NONE
:
5189 case FRAG_DEPTH_LAYOUT_ANY
:
5190 return BRW_PSCDEPTH_ON
;
5191 case FRAG_DEPTH_LAYOUT_GREATER
:
5192 return BRW_PSCDEPTH_ON_GE
;
5193 case FRAG_DEPTH_LAYOUT_LESS
:
5194 return BRW_PSCDEPTH_ON_LE
;
5195 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
5196 return BRW_PSCDEPTH_OFF
;
5199 return BRW_PSCDEPTH_OFF
;
5203 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
5205 const struct brw_wm_prog_key
*key
,
5206 struct brw_wm_prog_data
*prog_data
,
5207 const nir_shader
*shader
,
5208 struct gl_program
*prog
,
5209 int shader_time_index8
, int shader_time_index16
,
5211 unsigned *final_assembly_size
,
5214 /* key->alpha_test_func means simulating alpha testing via discards,
5215 * so the shader definitely kills pixels.
5217 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
5218 prog_data
->uses_omask
=
5219 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
5220 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
5222 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
5224 prog_data
->barycentric_interp_modes
=
5225 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
5227 key
->persample_shading
,
5230 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
,
5231 &prog_data
->base
, prog
, shader
, 8,
5232 shader_time_index8
);
5233 if (!v
.run_fs(false /* do_rep_send */)) {
5235 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
5240 cfg_t
*simd16_cfg
= NULL
;
5241 fs_visitor
v2(compiler
, log_data
, mem_ctx
, key
,
5242 &prog_data
->base
, prog
, shader
, 16,
5243 shader_time_index16
);
5244 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
5245 if (!v
.simd16_unsupported
) {
5246 /* Try a SIMD16 compile */
5247 v2
.import_uniforms(&v
);
5248 if (!v2
.run_fs(use_rep_send
)) {
5249 compiler
->shader_perf_log(log_data
,
5250 "SIMD16 shader failed to compile: %s",
5253 simd16_cfg
= v2
.cfg
;
5259 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || use_rep_send
;
5260 if ((no_simd8
|| compiler
->devinfo
->gen
< 5) && simd16_cfg
) {
5262 prog_data
->no_8
= true;
5265 prog_data
->no_8
= false;
5268 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
5269 v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
5271 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5272 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
5273 shader
->info
.label
? shader
->info
.label
:
5275 shader
->info
.name
));
5279 g
.generate_code(simd8_cfg
, 8);
5281 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5283 return g
.get_assembly(final_assembly_size
);
5287 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*prog_data
,
5288 void *buffer
, uint32_t threads
, uint32_t stride
)
5290 if (prog_data
->local_invocation_id_regs
== 0)
5293 /* 'stride' should be an integer number of registers, that is, a multiple
5296 assert(stride
% 32 == 0);
5298 unsigned x
= 0, y
= 0, z
= 0;
5299 for (unsigned t
= 0; t
< threads
; t
++) {
5300 uint32_t *param
= (uint32_t *) buffer
+ stride
* t
/ 4;
5302 for (unsigned i
= 0; i
< prog_data
->simd_size
; i
++) {
5303 param
[0 * prog_data
->simd_size
+ i
] = x
;
5304 param
[1 * prog_data
->simd_size
+ i
] = y
;
5305 param
[2 * prog_data
->simd_size
+ i
] = z
;
5308 if (x
== prog_data
->local_size
[0]) {
5311 if (y
== prog_data
->local_size
[1]) {
5314 if (z
== prog_data
->local_size
[2])
5323 fs_visitor::emit_cs_local_invocation_id_setup()
5325 assert(stage
== MESA_SHADER_COMPUTE
);
5327 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5329 struct brw_reg src
=
5330 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
5331 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
5333 src
.nr
+= dispatch_width
/ 8;
5334 bld
.MOV(offset(*reg
, bld
, 1), src
);
5335 src
.nr
+= dispatch_width
/ 8;
5336 bld
.MOV(offset(*reg
, bld
, 2), src
);
5342 fs_visitor::emit_cs_work_group_id_setup()
5344 assert(stage
== MESA_SHADER_COMPUTE
);
5346 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5348 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
5349 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
5350 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
5352 bld
.MOV(*reg
, r0_1
);
5353 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
5354 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
5360 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
5362 const struct brw_cs_prog_key
*key
,
5363 struct brw_cs_prog_data
*prog_data
,
5364 const nir_shader
*shader
,
5365 int shader_time_index
,
5366 unsigned *final_assembly_size
,
5369 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
5370 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
5371 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
5372 unsigned local_workgroup_size
=
5373 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
5374 shader
->info
.cs
.local_size
[2];
5376 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
5379 const char *fail_msg
= NULL
;
5381 /* Now the main event: Visit the shader IR and generate our CS IR for it.
5383 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5384 NULL
, /* Never used in core profile */
5385 shader
, 8, shader_time_index
);
5387 fail_msg
= v8
.fail_msg
;
5388 } else if (local_workgroup_size
<= 8 * max_cs_threads
) {
5390 prog_data
->simd_size
= 8;
5393 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5394 NULL
, /* Never used in core profile */
5395 shader
, 16, shader_time_index
);
5396 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
5397 !fail_msg
&& !v8
.simd16_unsupported
&&
5398 local_workgroup_size
<= 16 * max_cs_threads
) {
5399 /* Try a SIMD16 compile */
5400 v16
.import_uniforms(&v8
);
5401 if (!v16
.run_cs()) {
5402 compiler
->shader_perf_log(log_data
,
5403 "SIMD16 shader failed to compile: %s",
5407 "Couldn't generate SIMD16 program and not "
5408 "enough threads for SIMD8";
5412 prog_data
->simd_size
= 16;
5416 if (unlikely(cfg
== NULL
)) {
5419 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
5424 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
5425 v8
.promoted_constants
, v8
.runtime_check_aads_emit
, "CS");
5426 if (INTEL_DEBUG
& DEBUG_CS
) {
5427 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
5428 shader
->info
.label
? shader
->info
.label
:
5431 g
.enable_debug(name
);
5434 g
.generate_code(cfg
, prog_data
->simd_size
);
5436 return g
.get_assembly(final_assembly_size
);