2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
32 #include "brw_context.h"
37 #include "brw_vec4_gs_visitor.h"
39 #include "brw_program.h"
40 #include "brw_dead_control_flow.h"
41 #include "compiler/glsl_types.h"
42 #include "compiler/nir/nir_builder.h"
43 #include "program/prog_parameter.h"
47 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
51 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
52 const fs_reg
*src
, unsigned sources
)
54 memset(this, 0, sizeof(*this));
56 this->src
= new fs_reg
[MAX2(sources
, 3)];
57 for (unsigned i
= 0; i
< sources
; i
++)
58 this->src
[i
] = src
[i
];
60 this->opcode
= opcode
;
62 this->sources
= sources
;
63 this->exec_size
= exec_size
;
66 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
68 assert(this->exec_size
!= 0);
70 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
72 /* This will be the case for almost all instructions. */
79 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
83 this->regs_written
= 0;
87 unreachable("Invalid destination register file");
90 this->writes_accumulator
= false;
95 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
98 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
100 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
103 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
105 init(opcode
, exec_size
, dst
, NULL
, 0);
108 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
111 const fs_reg src
[1] = { src0
};
112 init(opcode
, exec_size
, dst
, src
, 1);
115 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
116 const fs_reg
&src0
, const fs_reg
&src1
)
118 const fs_reg src
[2] = { src0
, src1
};
119 init(opcode
, exec_size
, dst
, src
, 2);
122 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
123 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
125 const fs_reg src
[3] = { src0
, src1
, src2
};
126 init(opcode
, exec_size
, dst
, src
, 3);
129 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
130 const fs_reg src
[], unsigned sources
)
132 init(opcode
, exec_width
, dst
, src
, sources
);
135 fs_inst::fs_inst(const fs_inst
&that
)
137 memcpy(this, &that
, sizeof(that
));
139 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
141 for (unsigned i
= 0; i
< that
.sources
; i
++)
142 this->src
[i
] = that
.src
[i
];
151 fs_inst::resize_sources(uint8_t num_sources
)
153 if (this->sources
!= num_sources
) {
154 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
156 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
157 src
[i
] = this->src
[i
];
161 this->sources
= num_sources
;
166 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
168 const fs_reg
&surf_index
,
169 const fs_reg
&varying_offset
,
170 uint32_t const_offset
)
172 /* We have our constant surface use a pitch of 4 bytes, so our index can
173 * be any component of a vector, and then we load 4 contiguous
174 * components starting from that.
176 * We break down the const_offset to a portion added to the variable
177 * offset and a portion done using reg_offset, which means that if you
178 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
179 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
180 * CSE can later notice that those loads are all the same and eliminate
181 * the redundant ones.
183 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
184 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
186 /* The pull load message will load a vec4 (16 bytes). If we are loading
187 * a double this means we are only loading 2 elements worth of data.
188 * We also want to use a 32-bit data type for the dst of the load operation
189 * so other parts of the driver don't get confused about the size of the
192 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
193 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
194 vec4_result
, surf_index
, vec4_offset
);
195 inst
->regs_written
= 4 * bld
.dispatch_width() / 8;
197 if (type_sz(dst
.type
) == 8) {
198 shuffle_32bit_load_result_to_64bit_data(
199 bld
, retype(vec4_result
, dst
.type
), vec4_result
, 2);
202 vec4_result
.type
= dst
.type
;
203 bld
.MOV(dst
, offset(vec4_result
, bld
,
204 (const_offset
& 0xf) / type_sz(vec4_result
.type
)));
208 * A helper for MOV generation for fixing up broken hardware SEND dependency
212 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
214 /* The caller always wants uncompressed to emit the minimal extra
215 * dependencies, and to avoid having to deal with aligning its regs to 2.
217 const fs_builder ubld
= bld
.annotate("send dependency resolve")
220 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
224 fs_inst::equals(fs_inst
*inst
) const
226 return (opcode
== inst
->opcode
&&
227 dst
.equals(inst
->dst
) &&
228 src
[0].equals(inst
->src
[0]) &&
229 src
[1].equals(inst
->src
[1]) &&
230 src
[2].equals(inst
->src
[2]) &&
231 saturate
== inst
->saturate
&&
232 predicate
== inst
->predicate
&&
233 conditional_mod
== inst
->conditional_mod
&&
234 mlen
== inst
->mlen
&&
235 base_mrf
== inst
->base_mrf
&&
236 target
== inst
->target
&&
238 header_size
== inst
->header_size
&&
239 shadow_compare
== inst
->shadow_compare
&&
240 exec_size
== inst
->exec_size
&&
241 offset
== inst
->offset
);
245 fs_inst::overwrites_reg(const fs_reg
®
) const
247 return reg
.in_range(dst
, regs_written
);
251 fs_inst::is_send_from_grf() const
254 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
255 case SHADER_OPCODE_SHADER_TIME_ADD
:
256 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
257 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
258 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
259 case SHADER_OPCODE_UNTYPED_ATOMIC
:
260 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
261 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
262 case SHADER_OPCODE_TYPED_ATOMIC
:
263 case SHADER_OPCODE_TYPED_SURFACE_READ
:
264 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
265 case SHADER_OPCODE_URB_WRITE_SIMD8
:
266 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
267 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
268 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
269 case SHADER_OPCODE_URB_READ_SIMD8
:
270 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
272 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
273 return src
[1].file
== VGRF
;
274 case FS_OPCODE_FB_WRITE
:
275 case FS_OPCODE_FB_READ
:
276 return src
[0].file
== VGRF
;
279 return src
[0].file
== VGRF
;
286 * Returns true if this instruction's sources and destinations cannot
287 * safely be the same register.
289 * In most cases, a register can be written over safely by the same
290 * instruction that is its last use. For a single instruction, the
291 * sources are dereferenced before writing of the destination starts
294 * However, there are a few cases where this can be problematic:
296 * - Virtual opcodes that translate to multiple instructions in the
297 * code generator: if src == dst and one instruction writes the
298 * destination before a later instruction reads the source, then
299 * src will have been clobbered.
301 * - SIMD16 compressed instructions with certain regioning (see below).
303 * The register allocator uses this information to set up conflicts between
304 * GRF sources and the destination.
307 fs_inst::has_source_and_destination_hazard() const
310 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
311 /* Multiple partial writes to the destination */
314 /* The SIMD16 compressed instruction
316 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
318 * is actually decoded in hardware as:
320 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
321 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
323 * Which is safe. However, if we have uniform accesses
324 * happening, we get into trouble:
326 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
327 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
329 * Now our destination for the first instruction overwrote the
330 * second instruction's src0, and we get garbage for those 8
331 * pixels. There's a similar issue for the pre-gen6
332 * pixel_x/pixel_y, which are registers of 16-bit values and thus
333 * would get stomped by the first decode as well.
335 if (exec_size
== 16) {
336 for (int i
= 0; i
< sources
; i
++) {
337 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
338 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
339 src
[i
].type
== BRW_REGISTER_TYPE_W
||
340 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
341 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
351 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
353 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
356 fs_reg reg
= this->src
[0];
357 if (reg
.file
!= VGRF
|| reg
.offset
/ REG_SIZE
!= 0 || reg
.stride
== 0)
360 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
363 for (int i
= 0; i
< this->sources
; i
++) {
364 reg
.type
= this->src
[i
].type
;
365 if (!this->src
[i
].equals(reg
))
368 if (i
< this->header_size
) {
369 reg
.offset
+= REG_SIZE
;
371 reg
= horiz_offset(reg
, this->exec_size
);
379 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
)
381 if (devinfo
->gen
== 6 && is_math())
384 if (is_send_from_grf())
387 if (!backend_instruction::can_do_source_mods())
394 fs_inst::can_change_types() const
396 return dst
.type
== src
[0].type
&&
397 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
398 (opcode
== BRW_OPCODE_MOV
||
399 (opcode
== BRW_OPCODE_SEL
&&
400 dst
.type
== src
[1].type
&&
401 predicate
!= BRW_PREDICATE_NONE
&&
402 !src
[1].abs
&& !src
[1].negate
));
406 fs_inst::has_side_effects() const
408 return this->eot
|| backend_instruction::has_side_effects();
414 memset(this, 0, sizeof(*this));
418 /** Generic unset register constructor. */
422 this->file
= BAD_FILE
;
425 fs_reg::fs_reg(struct ::brw_reg reg
) :
430 if (this->file
== IMM
&&
431 (this->type
!= BRW_REGISTER_TYPE_V
&&
432 this->type
!= BRW_REGISTER_TYPE_UV
&&
433 this->type
!= BRW_REGISTER_TYPE_VF
)) {
439 fs_reg::equals(const fs_reg
&r
) const
441 return (this->backend_reg::equals(r
) &&
446 fs_reg::set_smear(unsigned subreg
)
448 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
449 offset
= ROUND_DOWN_TO(offset
, REG_SIZE
) + subreg
* type_sz(type
);
455 fs_reg::is_contiguous() const
461 fs_reg::component_size(unsigned width
) const
463 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
466 return MAX2(width
* stride
, 1) * type_sz(type
);
470 type_size_scalar(const struct glsl_type
*type
)
472 unsigned int size
, i
;
474 switch (type
->base_type
) {
477 case GLSL_TYPE_FLOAT
:
479 return type
->components();
480 case GLSL_TYPE_DOUBLE
:
481 return type
->components() * 2;
482 case GLSL_TYPE_ARRAY
:
483 return type_size_scalar(type
->fields
.array
) * type
->length
;
484 case GLSL_TYPE_STRUCT
:
486 for (i
= 0; i
< type
->length
; i
++) {
487 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
490 case GLSL_TYPE_SAMPLER
:
491 /* Samplers take up no register space, since they're baked in at
495 case GLSL_TYPE_ATOMIC_UINT
:
497 case GLSL_TYPE_SUBROUTINE
:
499 case GLSL_TYPE_IMAGE
:
500 return BRW_IMAGE_PARAM_SIZE
;
502 case GLSL_TYPE_ERROR
:
503 case GLSL_TYPE_INTERFACE
:
504 case GLSL_TYPE_FUNCTION
:
505 unreachable("not reached");
512 * Returns the number of scalar components needed to store type, assuming
513 * that vectors are padded out to vec4.
515 * This has the packing rules of type_size_vec4(), but counts components
516 * similar to type_size_scalar().
519 type_size_vec4_times_4(const struct glsl_type
*type
)
521 return 4 * type_size_vec4(type
);
524 /* Attribute arrays are loaded as one vec4 per element (or matrix column),
525 * except for double-precision types, which are loaded as one dvec4.
528 type_size_vs_input(const struct glsl_type
*type
)
530 if (type
->is_double()) {
531 return type_size_dvec4(type
);
533 return type_size_vec4(type
);
538 * Create a MOV to read the timestamp register.
540 * The caller is responsible for emitting the MOV. The return value is
541 * the destination of the MOV, with extra parameters set.
544 fs_visitor::get_timestamp(const fs_builder
&bld
)
546 assert(devinfo
->gen
>= 7);
548 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
551 BRW_REGISTER_TYPE_UD
));
553 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
555 /* We want to read the 3 fields we care about even if it's not enabled in
558 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
564 fs_visitor::emit_shader_time_begin()
566 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
568 /* We want only the low 32 bits of the timestamp. Since it's running
569 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
570 * which is plenty of time for our purposes. It is identical across the
571 * EUs, but since it's tracking GPU core speed it will increment at a
572 * varying rate as render P-states change.
574 shader_start_time
.set_smear(0);
578 fs_visitor::emit_shader_time_end()
580 /* Insert our code just before the final SEND with EOT. */
581 exec_node
*end
= this->instructions
.get_tail();
582 assert(end
&& ((fs_inst
*) end
)->eot
);
583 const fs_builder ibld
= bld
.annotate("shader time end")
584 .exec_all().at(NULL
, end
);
586 fs_reg shader_end_time
= get_timestamp(ibld
);
588 /* We only use the low 32 bits of the timestamp - see
589 * emit_shader_time_begin()).
591 * We could also check if render P-states have changed (or anything
592 * else that might disrupt timing) by setting smear to 2 and checking if
593 * that field is != 0.
595 shader_end_time
.set_smear(0);
597 /* Check that there weren't any timestamp reset events (assuming these
598 * were the only two timestamp reads that happened).
600 fs_reg reset
= shader_end_time
;
602 set_condmod(BRW_CONDITIONAL_Z
,
603 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
604 ibld
.IF(BRW_PREDICATE_NORMAL
);
606 fs_reg start
= shader_start_time
;
608 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
611 const fs_builder cbld
= ibld
.group(1, 0);
612 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
614 /* If there were no instructions between the two timestamp gets, the diff
615 * is 2 cycles. Remove that overhead, so I can forget about that when
616 * trying to determine the time taken for single instructions.
618 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
619 SHADER_TIME_ADD(cbld
, 0, diff
);
620 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
621 ibld
.emit(BRW_OPCODE_ELSE
);
622 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
623 ibld
.emit(BRW_OPCODE_ENDIF
);
627 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
628 int shader_time_subindex
,
631 int index
= shader_time_index
* 3 + shader_time_subindex
;
632 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
635 if (dispatch_width
== 8)
636 payload
= vgrf(glsl_type::uvec2_type
);
638 payload
= vgrf(glsl_type::uint_type
);
640 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
644 fs_visitor::vfail(const char *format
, va_list va
)
653 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
654 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
656 this->fail_msg
= msg
;
659 fprintf(stderr
, "%s", msg
);
664 fs_visitor::fail(const char *format
, ...)
668 va_start(va
, format
);
674 * Mark this program as impossible to compile with dispatch width greater
677 * During the SIMD8 compile (which happens first), we can detect and flag
678 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
679 * SIMD16+ compile altogether.
681 * During a compile of dispatch width greater than n (if one happens anyway),
682 * this just calls fail().
685 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
687 if (dispatch_width
> n
) {
690 max_dispatch_width
= n
;
691 compiler
->shader_perf_log(log_data
,
692 "Shader dispatch width limited to SIMD%d: %s",
698 * Returns true if the instruction has a flag that means it won't
699 * update an entire destination register.
701 * For example, dead code elimination and live variable analysis want to know
702 * when a write to a variable screens off any preceding values that were in
706 fs_inst::is_partial_write() const
708 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
709 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
710 !this->dst
.is_contiguous() ||
711 this->dst
.offset
% REG_SIZE
!= 0);
715 fs_inst::components_read(unsigned i
) const
717 /* Return zero if the source is not present. */
718 if (src
[i
].file
== BAD_FILE
)
722 case FS_OPCODE_LINTERP
:
728 case FS_OPCODE_PIXEL_X
:
729 case FS_OPCODE_PIXEL_Y
:
733 case FS_OPCODE_FB_WRITE_LOGICAL
:
734 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
735 /* First/second FB write color. */
737 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
741 case SHADER_OPCODE_TEX_LOGICAL
:
742 case SHADER_OPCODE_TXD_LOGICAL
:
743 case SHADER_OPCODE_TXF_LOGICAL
:
744 case SHADER_OPCODE_TXL_LOGICAL
:
745 case SHADER_OPCODE_TXS_LOGICAL
:
746 case FS_OPCODE_TXB_LOGICAL
:
747 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
748 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
749 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
750 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
751 case SHADER_OPCODE_LOD_LOGICAL
:
752 case SHADER_OPCODE_TG4_LOGICAL
:
753 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
754 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
755 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
756 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
757 /* Texture coordinates. */
758 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
759 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
760 /* Texture derivatives. */
761 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
762 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
763 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
764 /* Texture offset. */
765 else if (i
== TEX_LOGICAL_SRC_OFFSET_VALUE
)
768 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
773 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
774 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
775 assert(src
[3].file
== IMM
);
776 /* Surface coordinates. */
779 /* Surface operation source (ignored for reads). */
785 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
786 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
787 assert(src
[3].file
== IMM
&&
789 /* Surface coordinates. */
792 /* Surface operation source. */
798 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
799 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
800 assert(src
[3].file
== IMM
&&
802 const unsigned op
= src
[4].ud
;
803 /* Surface coordinates. */
806 /* Surface operation source. */
807 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
809 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
810 op
== BRW_AOP_PREDEC
))
822 fs_inst::regs_read(int arg
) const
825 case FS_OPCODE_FB_WRITE
:
826 case FS_OPCODE_FB_READ
:
827 case SHADER_OPCODE_URB_WRITE_SIMD8
:
828 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
829 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
830 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
831 case SHADER_OPCODE_URB_READ_SIMD8
:
832 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
833 case SHADER_OPCODE_UNTYPED_ATOMIC
:
834 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
835 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
836 case SHADER_OPCODE_TYPED_ATOMIC
:
837 case SHADER_OPCODE_TYPED_SURFACE_READ
:
838 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
839 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
844 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
845 /* The payload is actually stored in src1 */
850 case FS_OPCODE_LINTERP
:
855 case SHADER_OPCODE_LOAD_PAYLOAD
:
856 if (arg
< this->header_size
)
860 case CS_OPCODE_CS_TERMINATE
:
861 case SHADER_OPCODE_BARRIER
:
864 case SHADER_OPCODE_MOV_INDIRECT
:
866 assert(src
[2].file
== IMM
);
867 unsigned region_length
= src
[2].ud
;
869 if (src
[0].file
== UNIFORM
) {
870 assert(region_length
% 4 == 0);
871 return region_length
/ 4;
872 } else if (src
[0].file
== FIXED_GRF
) {
873 /* If the start of the region is not register aligned, then
874 * there's some portion of the register that's technically
875 * unread at the beginning.
877 * However, the register allocator works in terms of whole
878 * registers, and does not use subnr. It assumes that the
879 * read starts at the beginning of the register, and extends
880 * regs_read() whole registers beyond that.
882 * To compensate, we extend the region length to include this
883 * unread portion at the beginning.
886 region_length
+= src
[0].subnr
;
888 return DIV_ROUND_UP(region_length
, REG_SIZE
);
890 assert(!"Invalid register file");
896 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
901 switch (src
[arg
].file
) {
910 return DIV_ROUND_UP(components_read(arg
) *
911 src
[arg
].component_size(exec_size
),
914 unreachable("MRF registers are not allowed as sources");
920 /* Return the subset of flag registers that an instruction could
921 * potentially read or write based on the execution controls and flag
922 * subregister number of the instruction.
925 flag_mask(const fs_inst
*inst
)
927 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
928 const unsigned end
= start
+ inst
->exec_size
;
929 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
934 fs_inst::flags_read(const gen_device_info
*devinfo
) const
936 /* XXX - This doesn't consider explicit uses of the flag register as source
939 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
940 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
941 /* The vertical predication modes combine corresponding bits from
942 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
944 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
945 return flag_mask(this) << shift
| flag_mask(this);
946 } else if (predicate
) {
947 return flag_mask(this);
954 fs_inst::flags_written() const
956 /* XXX - This doesn't consider explicit uses of the flag register as
957 * destination region.
959 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
960 opcode
!= BRW_OPCODE_IF
&&
961 opcode
!= BRW_OPCODE_WHILE
)) ||
962 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
963 return flag_mask(this);
970 * Returns how many MRFs an FS opcode will write over.
972 * Note that this is not the 0 or 1 implied writes in an actual gen
973 * instruction -- the FS opcodes often generate MOVs in addition.
976 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
981 if (inst
->base_mrf
== -1)
984 switch (inst
->opcode
) {
985 case SHADER_OPCODE_RCP
:
986 case SHADER_OPCODE_RSQ
:
987 case SHADER_OPCODE_SQRT
:
988 case SHADER_OPCODE_EXP2
:
989 case SHADER_OPCODE_LOG2
:
990 case SHADER_OPCODE_SIN
:
991 case SHADER_OPCODE_COS
:
992 return 1 * dispatch_width
/ 8;
993 case SHADER_OPCODE_POW
:
994 case SHADER_OPCODE_INT_QUOTIENT
:
995 case SHADER_OPCODE_INT_REMAINDER
:
996 return 2 * dispatch_width
/ 8;
997 case SHADER_OPCODE_TEX
:
999 case SHADER_OPCODE_TXD
:
1000 case SHADER_OPCODE_TXF
:
1001 case SHADER_OPCODE_TXF_CMS
:
1002 case SHADER_OPCODE_TXF_MCS
:
1003 case SHADER_OPCODE_TG4
:
1004 case SHADER_OPCODE_TG4_OFFSET
:
1005 case SHADER_OPCODE_TXL
:
1006 case SHADER_OPCODE_TXS
:
1007 case SHADER_OPCODE_LOD
:
1008 case SHADER_OPCODE_SAMPLEINFO
:
1010 case FS_OPCODE_FB_WRITE
:
1012 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1013 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1015 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
1017 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1020 unreachable("not reached");
1025 fs_visitor::vgrf(const glsl_type
*const type
)
1027 int reg_width
= dispatch_width
/ 8;
1028 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
1029 brw_type_for_base_type(type
));
1032 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1037 this->type
= BRW_REGISTER_TYPE_F
;
1038 this->stride
= (file
== UNIFORM
? 0 : 1);
1041 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1047 this->stride
= (file
== UNIFORM
? 0 : 1);
1050 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1051 * This brings in those uniform definitions
1054 fs_visitor::import_uniforms(fs_visitor
*v
)
1056 this->push_constant_loc
= v
->push_constant_loc
;
1057 this->pull_constant_loc
= v
->pull_constant_loc
;
1058 this->uniforms
= v
->uniforms
;
1062 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1064 assert(stage
== MESA_SHADER_FRAGMENT
);
1066 /* gl_FragCoord.x */
1067 bld
.MOV(wpos
, this->pixel_x
);
1068 wpos
= offset(wpos
, bld
, 1);
1070 /* gl_FragCoord.y */
1071 bld
.MOV(wpos
, this->pixel_y
);
1072 wpos
= offset(wpos
, bld
, 1);
1074 /* gl_FragCoord.z */
1075 if (devinfo
->gen
>= 6) {
1076 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1078 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1079 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1080 interp_reg(VARYING_SLOT_POS
, 2));
1082 wpos
= offset(wpos
, bld
, 1);
1084 /* gl_FragCoord.w: Already set up in emit_interpolation */
1085 bld
.MOV(wpos
, this->wpos_w
);
1088 enum brw_barycentric_mode
1089 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1091 /* Barycentric modes don't make sense for flat inputs. */
1092 assert(mode
!= INTERP_MODE_FLAT
);
1096 case nir_intrinsic_load_barycentric_pixel
:
1097 case nir_intrinsic_load_barycentric_at_offset
:
1098 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1100 case nir_intrinsic_load_barycentric_centroid
:
1101 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1103 case nir_intrinsic_load_barycentric_sample
:
1104 case nir_intrinsic_load_barycentric_at_sample
:
1105 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1108 unreachable("invalid intrinsic");
1111 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1114 return (enum brw_barycentric_mode
) bary
;
1118 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1120 static enum brw_barycentric_mode
1121 centroid_to_pixel(enum brw_barycentric_mode bary
)
1123 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1124 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1125 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1129 fs_visitor::emit_frontfacing_interpolation()
1131 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1133 if (devinfo
->gen
>= 6) {
1134 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1135 * a boolean result from this (~0/true or 0/false).
1137 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1138 * this task in only one instruction:
1139 * - a negation source modifier will flip the bit; and
1140 * - a W -> D type conversion will sign extend the bit into the high
1141 * word of the destination.
1143 * An ASR 15 fills the low word of the destination.
1145 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1148 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1150 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1151 * a boolean result from this (1/true or 0/false).
1153 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1154 * the negation source modifier to flip it. Unfortunately the SHR
1155 * instruction only operates on UD (or D with an abs source modifier)
1156 * sources without negation.
1158 * Instead, use ASR (which will give ~0/true or 0/false).
1160 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1163 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1170 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1172 assert(stage
== MESA_SHADER_FRAGMENT
);
1173 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1174 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1176 if (wm_prog_data
->persample_dispatch
) {
1177 /* Convert int_sample_pos to floating point */
1178 bld
.MOV(dst
, int_sample_pos
);
1179 /* Scale to the range [0, 1] */
1180 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1183 /* From ARB_sample_shading specification:
1184 * "When rendering to a non-multisample buffer, or if multisample
1185 * rasterization is disabled, gl_SamplePosition will always be
1188 bld
.MOV(dst
, brw_imm_f(0.5f
));
1193 fs_visitor::emit_samplepos_setup()
1195 assert(devinfo
->gen
>= 6);
1197 const fs_builder abld
= bld
.annotate("compute sample position");
1198 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1200 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1201 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1203 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1204 * mode will be enabled.
1206 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1207 * R31.1:0 Position Offset X/Y for Slot[3:0]
1208 * R31.3:2 Position Offset X/Y for Slot[7:4]
1211 * The X, Y sample positions come in as bytes in thread payload. So, read
1212 * the positions using vstride=16, width=8, hstride=2.
1214 struct brw_reg sample_pos_reg
=
1215 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1216 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1218 if (dispatch_width
== 8) {
1219 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1221 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1222 abld
.half(1).MOV(half(int_sample_x
, 1),
1223 fs_reg(suboffset(sample_pos_reg
, 16)));
1225 /* Compute gl_SamplePosition.x */
1226 compute_sample_position(pos
, int_sample_x
);
1227 pos
= offset(pos
, abld
, 1);
1228 if (dispatch_width
== 8) {
1229 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1231 abld
.half(0).MOV(half(int_sample_y
, 0),
1232 fs_reg(suboffset(sample_pos_reg
, 1)));
1233 abld
.half(1).MOV(half(int_sample_y
, 1),
1234 fs_reg(suboffset(sample_pos_reg
, 17)));
1236 /* Compute gl_SamplePosition.y */
1237 compute_sample_position(pos
, int_sample_y
);
1242 fs_visitor::emit_sampleid_setup()
1244 assert(stage
== MESA_SHADER_FRAGMENT
);
1245 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1246 assert(devinfo
->gen
>= 6);
1248 const fs_builder abld
= bld
.annotate("compute sample id");
1249 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1251 if (!key
->multisample_fbo
) {
1252 /* As per GL_ARB_sample_shading specification:
1253 * "When rendering to a non-multisample buffer, or if multisample
1254 * rasterization is disabled, gl_SampleID will always be zero."
1256 abld
.MOV(*reg
, brw_imm_d(0));
1257 } else if (devinfo
->gen
>= 8) {
1258 /* Sample ID comes in as 4-bit numbers in g1.0:
1260 * 15:12 Slot 3 SampleID (only used in SIMD16)
1261 * 11:8 Slot 2 SampleID (only used in SIMD16)
1262 * 7:4 Slot 1 SampleID
1263 * 3:0 Slot 0 SampleID
1265 * Each slot corresponds to four channels, so we want to replicate each
1266 * half-byte value to 4 channels in a row:
1268 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1269 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1271 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1272 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1274 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1275 * channels to read the first byte (7:0), and the second group of 8
1276 * channels to read the second byte (15:8). Then, we shift right by
1277 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1278 * values into place. Finally, we AND with 0xf to keep the low nibble.
1280 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1281 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1283 * TODO: These payload bits exist on Gen7 too, but they appear to always
1284 * be zero, so this code fails to work. We should find out why.
1286 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1288 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1289 BRW_REGISTER_TYPE_B
), 1, 8, 0)),
1290 brw_imm_v(0x44440000));
1291 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1293 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1295 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1297 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1298 * 8x multisampling, subspan 0 will represent sample N (where N
1299 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1300 * 7. We can find the value of N by looking at R0.0 bits 7:6
1301 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1302 * (since samples are always delivered in pairs). That is, we
1303 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1304 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1305 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1306 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1307 * populating a temporary variable with the sequence (0, 1, 2, 3),
1308 * and then reading from it using vstride=1, width=4, hstride=0.
1309 * These computations hold good for 4x multisampling as well.
1311 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1312 * the first four slots are sample 0 of subspan 0; the next four
1313 * are sample 1 of subspan 0; the third group is sample 0 of
1314 * subspan 1, and finally sample 1 of subspan 1.
1317 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1318 * accomodate 16x MSAA.
1320 abld
.exec_all().group(1, 0)
1321 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1323 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1325 /* This works for both SIMD8 and SIMD16 */
1326 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1328 /* This special instruction takes care of setting vstride=1,
1329 * width=4, hstride=0 of t2 during an ADD instruction.
1331 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1338 fs_visitor::emit_samplemaskin_setup()
1340 assert(stage
== MESA_SHADER_FRAGMENT
);
1341 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1342 assert(devinfo
->gen
>= 6);
1344 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1346 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1347 BRW_REGISTER_TYPE_D
));
1349 if (wm_prog_data
->persample_dispatch
) {
1350 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1351 * and a mask representing which sample is being processed by the
1352 * current shader invocation.
1354 * From the OES_sample_variables specification:
1355 * "When per-sample shading is active due to the use of a fragment input
1356 * qualified by "sample" or due to the use of the gl_SampleID or
1357 * gl_SamplePosition variables, only the bit for the current sample is
1358 * set in gl_SampleMaskIn."
1360 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1362 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1363 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1365 fs_reg one
= vgrf(glsl_type::int_type
);
1366 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1367 abld
.MOV(one
, brw_imm_d(1));
1368 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1369 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1371 /* In per-pixel mode, the coverage mask is sufficient. */
1372 *reg
= coverage_mask
;
1378 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1380 if (!src
.abs
&& !src
.negate
)
1383 fs_reg temp
= bld
.vgrf(src
.type
);
1390 fs_visitor::emit_discard_jump()
1392 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1394 /* For performance, after a discard, jump to the end of the
1395 * shader if all relevant channels have been discarded.
1397 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1398 discard_jump
->flag_subreg
= 1;
1400 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1401 discard_jump
->predicate_inverse
= true;
1405 fs_visitor::emit_gs_thread_end()
1407 assert(stage
== MESA_SHADER_GEOMETRY
);
1409 struct brw_gs_prog_data
*gs_prog_data
=
1410 (struct brw_gs_prog_data
*) prog_data
;
1412 if (gs_compile
->control_data_header_size_bits
> 0) {
1413 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1416 const fs_builder abld
= bld
.annotate("thread end");
1419 if (gs_prog_data
->static_vertex_count
!= -1) {
1420 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1421 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1422 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1423 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1424 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1427 /* Delete now dead instructions. */
1428 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1434 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1438 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1439 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1440 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1443 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1444 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1445 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1446 sources
[1] = this->final_gs_vertex_count
;
1447 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1448 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1456 fs_visitor::assign_curb_setup()
1458 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1460 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1461 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1462 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1463 if (inst
->src
[i
].file
== UNIFORM
) {
1464 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1466 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1467 constant_nr
= push_constant_loc
[uniform_nr
];
1469 /* Section 5.11 of the OpenGL 4.1 spec says:
1470 * "Out-of-bounds reads return undefined values, which include
1471 * values from other variables of the active program or zero."
1472 * Just return the first push constant.
1477 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1480 brw_reg
.abs
= inst
->src
[i
].abs
;
1481 brw_reg
.negate
= inst
->src
[i
].negate
;
1483 assert(inst
->src
[i
].stride
== 0);
1484 inst
->src
[i
] = byte_offset(
1485 retype(brw_reg
, inst
->src
[i
].type
),
1486 inst
->src
[i
].offset
% 4);
1491 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1492 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1496 fs_visitor::calculate_urb_setup()
1498 assert(stage
== MESA_SHADER_FRAGMENT
);
1499 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1500 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1502 memset(prog_data
->urb_setup
, -1,
1503 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1506 /* Figure out where each of the incoming setup attributes lands. */
1507 if (devinfo
->gen
>= 6) {
1508 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1509 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1510 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1511 * first 16 varying inputs, so we can put them wherever we want.
1512 * Just put them in order.
1514 * This is useful because it means that (a) inputs not used by the
1515 * fragment shader won't take up valuable register space, and (b) we
1516 * won't have to recompile the fragment shader if it gets paired with
1517 * a different vertex (or geometry) shader.
1519 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1520 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1521 BITFIELD64_BIT(i
)) {
1522 prog_data
->urb_setup
[i
] = urb_next
++;
1526 bool include_vue_header
=
1527 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1529 /* We have enough input varyings that the SF/SBE pipeline stage can't
1530 * arbitrarily rearrange them to suit our whim; we have to put them
1531 * in an order that matches the output of the previous pipeline stage
1532 * (geometry or vertex shader).
1534 struct brw_vue_map prev_stage_vue_map
;
1535 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1536 key
->input_slots_valid
,
1537 nir
->info
.separate_shader
);
1539 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1541 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1542 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1544 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1545 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1546 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1547 BITFIELD64_BIT(varying
))) {
1548 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1551 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1554 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1555 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1556 /* Point size is packed into the header, not as a general attribute */
1557 if (i
== VARYING_SLOT_PSIZ
)
1560 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1561 /* The back color slot is skipped when the front color is
1562 * also written to. In addition, some slots can be
1563 * written in the vertex shader and not read in the
1564 * fragment shader. So the register number must always be
1565 * incremented, mapped or not.
1567 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1568 prog_data
->urb_setup
[i
] = urb_next
;
1574 * It's a FS only attribute, and we did interpolation for this attribute
1575 * in SF thread. So, count it here, too.
1577 * See compile_sf_prog() for more info.
1579 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1580 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1583 prog_data
->num_varying_inputs
= urb_next
;
1587 fs_visitor::assign_urb_setup()
1589 assert(stage
== MESA_SHADER_FRAGMENT
);
1590 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1592 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1594 /* Offset all the urb_setup[] index by the actual position of the
1595 * setup regs, now that the location of the constants has been chosen.
1597 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1598 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1599 assert(inst
->src
[1].file
== FIXED_GRF
);
1600 inst
->src
[1].nr
+= urb_start
;
1603 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1604 assert(inst
->src
[0].file
== FIXED_GRF
);
1605 inst
->src
[0].nr
+= urb_start
;
1609 /* Each attribute is 4 setup channels, each of which is half a reg. */
1610 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1614 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1616 for (int i
= 0; i
< inst
->sources
; i
++) {
1617 if (inst
->src
[i
].file
== ATTR
) {
1618 int grf
= payload
.num_regs
+
1619 prog_data
->curb_read_length
+
1621 inst
->src
[i
].offset
/ REG_SIZE
;
1623 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1625 * VertStride must be used to cross GRF register boundaries. This
1626 * rule implies that elements within a 'Width' cannot cross GRF
1629 * So, for registers that are large enough, we have to split the exec
1630 * size in two and trust the compression state to sort it out.
1632 unsigned total_size
= inst
->exec_size
*
1633 inst
->src
[i
].stride
*
1634 type_sz(inst
->src
[i
].type
);
1636 assert(total_size
<= 2 * REG_SIZE
);
1637 const unsigned exec_size
=
1638 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1640 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1641 struct brw_reg reg
=
1642 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1643 inst
->src
[i
].offset
% REG_SIZE
),
1644 exec_size
* inst
->src
[i
].stride
,
1645 width
, inst
->src
[i
].stride
);
1646 reg
.abs
= inst
->src
[i
].abs
;
1647 reg
.negate
= inst
->src
[i
].negate
;
1655 fs_visitor::assign_vs_urb_setup()
1657 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1659 assert(stage
== MESA_SHADER_VERTEX
);
1661 /* Each attribute is 4 regs. */
1662 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1664 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1666 /* Rewrite all ATTR file references to the hw grf that they land in. */
1667 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1668 convert_attr_sources_to_hw_regs(inst
);
1673 fs_visitor::assign_tcs_single_patch_urb_setup()
1675 assert(stage
== MESA_SHADER_TESS_CTRL
);
1677 /* Rewrite all ATTR file references to HW_REGs. */
1678 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1679 convert_attr_sources_to_hw_regs(inst
);
1684 fs_visitor::assign_tes_urb_setup()
1686 assert(stage
== MESA_SHADER_TESS_EVAL
);
1688 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1690 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1692 /* Rewrite all ATTR file references to HW_REGs. */
1693 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1694 convert_attr_sources_to_hw_regs(inst
);
1699 fs_visitor::assign_gs_urb_setup()
1701 assert(stage
== MESA_SHADER_GEOMETRY
);
1703 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1705 first_non_payload_grf
+=
1706 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1708 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1709 /* Rewrite all ATTR file references to GRFs. */
1710 convert_attr_sources_to_hw_regs(inst
);
1716 * Split large virtual GRFs into separate components if we can.
1718 * This is mostly duplicated with what brw_fs_vector_splitting does,
1719 * but that's really conservative because it's afraid of doing
1720 * splitting that doesn't result in real progress after the rest of
1721 * the optimization phases, which would cause infinite looping in
1722 * optimization. We can do it once here, safely. This also has the
1723 * opportunity to split interpolated values, or maybe even uniforms,
1724 * which we don't have at the IR level.
1726 * We want to split, because virtual GRFs are what we register
1727 * allocate and spill (due to contiguousness requirements for some
1728 * instructions), and they're what we naturally generate in the
1729 * codegen process, but most virtual GRFs don't actually need to be
1730 * contiguous sets of GRFs. If we split, we'll end up with reduced
1731 * live intervals and better dead code elimination and coalescing.
1734 fs_visitor::split_virtual_grfs()
1736 int num_vars
= this->alloc
.count
;
1738 /* Count the total number of registers */
1740 int vgrf_to_reg
[num_vars
];
1741 for (int i
= 0; i
< num_vars
; i
++) {
1742 vgrf_to_reg
[i
] = reg_count
;
1743 reg_count
+= alloc
.sizes
[i
];
1746 /* An array of "split points". For each register slot, this indicates
1747 * if this slot can be separated from the previous slot. Every time an
1748 * instruction uses multiple elements of a register (as a source or
1749 * destination), we mark the used slots as inseparable. Then we go
1750 * through and split the registers into the smallest pieces we can.
1752 bool split_points
[reg_count
];
1753 memset(split_points
, 0, sizeof(split_points
));
1755 /* Mark all used registers as fully splittable */
1756 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1757 if (inst
->dst
.file
== VGRF
) {
1758 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1759 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1760 split_points
[reg
+ j
] = true;
1763 for (int i
= 0; i
< inst
->sources
; i
++) {
1764 if (inst
->src
[i
].file
== VGRF
) {
1765 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1766 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1767 split_points
[reg
+ j
] = true;
1772 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1773 if (inst
->dst
.file
== VGRF
) {
1774 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1775 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1776 split_points
[reg
+ j
] = false;
1778 for (int i
= 0; i
< inst
->sources
; i
++) {
1779 if (inst
->src
[i
].file
== VGRF
) {
1780 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1781 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1782 split_points
[reg
+ j
] = false;
1787 int new_virtual_grf
[reg_count
];
1788 int new_reg_offset
[reg_count
];
1791 for (int i
= 0; i
< num_vars
; i
++) {
1792 /* The first one should always be 0 as a quick sanity check. */
1793 assert(split_points
[reg
] == false);
1796 new_reg_offset
[reg
] = 0;
1801 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1802 /* If this is a split point, reset the offset to 0 and allocate a
1803 * new virtual GRF for the previous offset many registers
1805 if (split_points
[reg
]) {
1806 assert(offset
<= MAX_VGRF_SIZE
);
1807 int grf
= alloc
.allocate(offset
);
1808 for (int k
= reg
- offset
; k
< reg
; k
++)
1809 new_virtual_grf
[k
] = grf
;
1812 new_reg_offset
[reg
] = offset
;
1817 /* The last one gets the original register number */
1818 assert(offset
<= MAX_VGRF_SIZE
);
1819 alloc
.sizes
[i
] = offset
;
1820 for (int k
= reg
- offset
; k
< reg
; k
++)
1821 new_virtual_grf
[k
] = i
;
1823 assert(reg
== reg_count
);
1825 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1826 if (inst
->dst
.file
== VGRF
) {
1827 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1828 inst
->dst
.nr
= new_virtual_grf
[reg
];
1829 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
1830 inst
->dst
.offset
% REG_SIZE
;
1831 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1833 for (int i
= 0; i
< inst
->sources
; i
++) {
1834 if (inst
->src
[i
].file
== VGRF
) {
1835 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1836 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1837 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
1838 inst
->src
[i
].offset
% REG_SIZE
;
1839 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1843 invalidate_live_intervals();
1847 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1849 * During code generation, we create tons of temporary variables, many of
1850 * which get immediately killed and are never used again. Yet, in later
1851 * optimization and analysis passes, such as compute_live_intervals, we need
1852 * to loop over all the virtual GRFs. Compacting them can save a lot of
1856 fs_visitor::compact_virtual_grfs()
1858 bool progress
= false;
1859 int remap_table
[this->alloc
.count
];
1860 memset(remap_table
, -1, sizeof(remap_table
));
1862 /* Mark which virtual GRFs are used. */
1863 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1864 if (inst
->dst
.file
== VGRF
)
1865 remap_table
[inst
->dst
.nr
] = 0;
1867 for (int i
= 0; i
< inst
->sources
; i
++) {
1868 if (inst
->src
[i
].file
== VGRF
)
1869 remap_table
[inst
->src
[i
].nr
] = 0;
1873 /* Compact the GRF arrays. */
1875 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1876 if (remap_table
[i
] == -1) {
1877 /* We just found an unused register. This means that we are
1878 * actually going to compact something.
1882 remap_table
[i
] = new_index
;
1883 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1884 invalidate_live_intervals();
1889 this->alloc
.count
= new_index
;
1891 /* Patch all the instructions to use the newly renumbered registers */
1892 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1893 if (inst
->dst
.file
== VGRF
)
1894 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1896 for (int i
= 0; i
< inst
->sources
; i
++) {
1897 if (inst
->src
[i
].file
== VGRF
)
1898 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1902 /* Patch all the references to delta_xy, since they're used in register
1903 * allocation. If they're unused, switch them to BAD_FILE so we don't
1904 * think some random VGRF is delta_xy.
1906 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1907 if (delta_xy
[i
].file
== VGRF
) {
1908 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1909 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1911 delta_xy
[i
].file
= BAD_FILE
;
1920 set_push_pull_constant_loc(unsigned uniform
, int *chunk_start
, bool contiguous
,
1921 int *push_constant_loc
, int *pull_constant_loc
,
1922 unsigned *num_push_constants
,
1923 unsigned *num_pull_constants
,
1924 const unsigned max_push_components
,
1925 const unsigned max_chunk_size
,
1926 struct brw_stage_prog_data
*stage_prog_data
)
1928 /* This is the first live uniform in the chunk */
1929 if (*chunk_start
< 0)
1930 *chunk_start
= uniform
;
1932 /* If this element does not need to be contiguous with the next, we
1933 * split at this point and everything between chunk_start and u forms a
1937 unsigned chunk_size
= uniform
- *chunk_start
+ 1;
1939 /* Decide whether we should push or pull this parameter. In the
1940 * Vulkan driver, push constants are explicitly exposed via the API
1941 * so we push everything. In GL, we only push small arrays.
1943 if (stage_prog_data
->pull_param
== NULL
||
1944 (*num_push_constants
+ chunk_size
<= max_push_components
&&
1945 chunk_size
<= max_chunk_size
)) {
1946 assert(*num_push_constants
+ chunk_size
<= max_push_components
);
1947 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1948 push_constant_loc
[j
] = (*num_push_constants
)++;
1950 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1951 pull_constant_loc
[j
] = (*num_pull_constants
)++;
1959 * Assign UNIFORM file registers to either push constants or pull constants.
1961 * We allow a fragment shader to have more than the specified minimum
1962 * maximum number of fragment shader uniform components (64). If
1963 * there are too many of these, they'd fill up all of register space.
1964 * So, this will push some of them out to the pull constant buffer and
1965 * update the program to load them.
1968 fs_visitor::assign_constant_locations()
1970 /* Only the first compile gets to decide on locations. */
1971 if (dispatch_width
!= min_dispatch_width
)
1974 bool is_live
[uniforms
];
1975 memset(is_live
, 0, sizeof(is_live
));
1976 bool is_live_64bit
[uniforms
];
1977 memset(is_live_64bit
, 0, sizeof(is_live_64bit
));
1979 /* For each uniform slot, a value of true indicates that the given slot and
1980 * the next slot must remain contiguous. This is used to keep us from
1981 * splitting arrays apart.
1983 bool contiguous
[uniforms
];
1984 memset(contiguous
, 0, sizeof(contiguous
));
1986 int thread_local_id_index
=
1987 (stage
== MESA_SHADER_COMPUTE
) ?
1988 ((brw_cs_prog_data
*)stage_prog_data
)->thread_local_id_index
: -1;
1990 /* First, we walk through the instructions and do two things:
1992 * 1) Figure out which uniforms are live.
1994 * 2) Mark any indirectly used ranges of registers as contiguous.
1996 * Note that we don't move constant-indexed accesses to arrays. No
1997 * testing has been done of the performance impact of this choice.
1999 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2000 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2001 if (inst
->src
[i
].file
!= UNIFORM
)
2004 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
2006 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2007 assert(inst
->src
[2].ud
% 4 == 0);
2008 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
2009 assert(last
< uniforms
);
2011 for (unsigned j
= constant_nr
; j
< last
; j
++) {
2013 contiguous
[j
] = true;
2014 if (type_sz(inst
->src
[i
].type
) == 8) {
2015 is_live_64bit
[j
] = true;
2018 is_live
[last
] = true;
2020 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
) {
2021 int regs_read
= inst
->components_read(i
) *
2022 type_sz(inst
->src
[i
].type
) / 4;
2023 for (int j
= 0; j
< regs_read
; j
++) {
2024 is_live
[constant_nr
+ j
] = true;
2025 if (type_sz(inst
->src
[i
].type
) == 8) {
2026 is_live_64bit
[constant_nr
+ j
] = true;
2034 if (thread_local_id_index
>= 0 && !is_live
[thread_local_id_index
])
2035 thread_local_id_index
= -1;
2037 /* Only allow 16 registers (128 uniform components) as push constants.
2039 * Just demote the end of the list. We could probably do better
2040 * here, demoting things that are rarely used in the program first.
2042 * If changing this value, note the limitation about total_regs in
2045 unsigned int max_push_components
= 16 * 8;
2046 if (thread_local_id_index
>= 0)
2047 max_push_components
--; /* Save a slot for the thread ID */
2049 /* We push small arrays, but no bigger than 16 floats. This is big enough
2050 * for a vec4 but hopefully not large enough to push out other stuff. We
2051 * should probably use a better heuristic at some point.
2053 const unsigned int max_chunk_size
= 16;
2055 unsigned int num_push_constants
= 0;
2056 unsigned int num_pull_constants
= 0;
2058 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2059 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2061 /* Default to -1 meaning no location */
2062 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2063 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2065 int chunk_start
= -1;
2067 /* First push 64-bit uniforms to ensure they are properly aligned */
2068 for (unsigned u
= 0; u
< uniforms
; u
++) {
2069 if (!is_live
[u
] || !is_live_64bit
[u
])
2072 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2073 push_constant_loc
, pull_constant_loc
,
2074 &num_push_constants
, &num_pull_constants
,
2075 max_push_components
, max_chunk_size
,
2080 /* Then push the rest of uniforms */
2081 for (unsigned u
= 0; u
< uniforms
; u
++) {
2082 if (!is_live
[u
] || is_live_64bit
[u
])
2085 /* Skip thread_local_id_index to put it in the last push register. */
2086 if (thread_local_id_index
== (int)u
)
2089 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2090 push_constant_loc
, pull_constant_loc
,
2091 &num_push_constants
, &num_pull_constants
,
2092 max_push_components
, max_chunk_size
,
2096 /* Add the CS local thread ID uniform at the end of the push constants */
2097 if (thread_local_id_index
>= 0)
2098 push_constant_loc
[thread_local_id_index
] = num_push_constants
++;
2100 /* As the uniforms are going to be reordered, take the data from a temporary
2101 * copy of the original param[].
2103 gl_constant_value
**param
= ralloc_array(NULL
, gl_constant_value
*,
2104 stage_prog_data
->nr_params
);
2105 memcpy(param
, stage_prog_data
->param
,
2106 sizeof(gl_constant_value
*) * stage_prog_data
->nr_params
);
2107 stage_prog_data
->nr_params
= num_push_constants
;
2108 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2110 /* Up until now, the param[] array has been indexed by reg + reg_offset
2111 * of UNIFORM registers. Move pull constants into pull_param[] and
2112 * condense param[] to only contain the uniforms we chose to push.
2114 * NOTE: Because we are condensing the params[] array, we know that
2115 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2116 * having to make a copy.
2118 int new_thread_local_id_index
= -1;
2119 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2120 const gl_constant_value
*value
= param
[i
];
2122 if (pull_constant_loc
[i
] != -1) {
2123 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2124 } else if (push_constant_loc
[i
] != -1) {
2125 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2126 if (thread_local_id_index
== (int)i
)
2127 new_thread_local_id_index
= push_constant_loc
[i
];
2132 if (stage
== MESA_SHADER_COMPUTE
)
2133 ((brw_cs_prog_data
*)stage_prog_data
)->thread_local_id_index
=
2134 new_thread_local_id_index
;
2138 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2139 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2142 fs_visitor::lower_constant_loads()
2144 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2146 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2147 /* Set up the annotation tracking for new generated instructions. */
2148 const fs_builder
ibld(this, block
, inst
);
2150 for (int i
= 0; i
< inst
->sources
; i
++) {
2151 if (inst
->src
[i
].file
!= UNIFORM
)
2154 /* We'll handle this case later */
2155 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2158 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
2159 if (location
>= uniforms
)
2160 continue; /* Out of bounds access */
2162 int pull_index
= pull_constant_loc
[location
];
2164 if (pull_index
== -1)
2167 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2170 if (type_sz(inst
->src
[i
].type
) <= 4)
2171 dst
= vgrf(glsl_type::float_type
);
2173 dst
= vgrf(glsl_type::double_type
);
2175 assert(inst
->src
[i
].stride
== 0);
2177 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2178 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2179 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2180 dst
, brw_imm_ud(index
), offset
);
2182 /* Rewrite the instruction to use the temporary VGRF. */
2183 inst
->src
[i
].file
= VGRF
;
2184 inst
->src
[i
].nr
= dst
.nr
;
2185 inst
->src
[i
].offset
%= 4;
2186 inst
->src
[i
].set_smear((pull_index
& 3) * 4 /
2187 type_sz(inst
->src
[i
].type
));
2189 brw_mark_surface_used(prog_data
, index
);
2192 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2193 inst
->src
[0].file
== UNIFORM
) {
2195 unsigned location
= inst
->src
[0].nr
+ inst
->src
[0].offset
/ 4;
2196 if (location
>= uniforms
)
2197 continue; /* Out of bounds access */
2199 int pull_index
= pull_constant_loc
[location
];
2201 if (pull_index
== -1)
2204 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2208 inst
->remove(block
);
2210 brw_mark_surface_used(prog_data
, index
);
2213 invalidate_live_intervals();
2217 fs_visitor::opt_algebraic()
2219 bool progress
= false;
2221 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2222 switch (inst
->opcode
) {
2223 case BRW_OPCODE_MOV
:
2224 if (inst
->src
[0].file
!= IMM
)
2227 if (inst
->saturate
) {
2228 if (inst
->dst
.type
!= inst
->src
[0].type
)
2229 assert(!"unimplemented: saturate mixed types");
2231 if (brw_saturate_immediate(inst
->dst
.type
,
2232 &inst
->src
[0].as_brw_reg())) {
2233 inst
->saturate
= false;
2239 case BRW_OPCODE_MUL
:
2240 if (inst
->src
[1].file
!= IMM
)
2244 if (inst
->src
[1].is_one()) {
2245 inst
->opcode
= BRW_OPCODE_MOV
;
2246 inst
->src
[1] = reg_undef
;
2252 if (inst
->src
[1].is_negative_one()) {
2253 inst
->opcode
= BRW_OPCODE_MOV
;
2254 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2255 inst
->src
[1] = reg_undef
;
2261 if (inst
->src
[1].is_zero()) {
2262 inst
->opcode
= BRW_OPCODE_MOV
;
2263 inst
->src
[0] = inst
->src
[1];
2264 inst
->src
[1] = reg_undef
;
2269 if (inst
->src
[0].file
== IMM
) {
2270 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2271 inst
->opcode
= BRW_OPCODE_MOV
;
2272 inst
->src
[0].f
*= inst
->src
[1].f
;
2273 inst
->src
[1] = reg_undef
;
2278 case BRW_OPCODE_ADD
:
2279 if (inst
->src
[1].file
!= IMM
)
2283 if (inst
->src
[1].is_zero()) {
2284 inst
->opcode
= BRW_OPCODE_MOV
;
2285 inst
->src
[1] = reg_undef
;
2290 if (inst
->src
[0].file
== IMM
) {
2291 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2292 inst
->opcode
= BRW_OPCODE_MOV
;
2293 inst
->src
[0].f
+= inst
->src
[1].f
;
2294 inst
->src
[1] = reg_undef
;
2300 if (inst
->src
[0].equals(inst
->src
[1])) {
2301 inst
->opcode
= BRW_OPCODE_MOV
;
2302 inst
->src
[1] = reg_undef
;
2307 case BRW_OPCODE_LRP
:
2308 if (inst
->src
[1].equals(inst
->src
[2])) {
2309 inst
->opcode
= BRW_OPCODE_MOV
;
2310 inst
->src
[0] = inst
->src
[1];
2311 inst
->src
[1] = reg_undef
;
2312 inst
->src
[2] = reg_undef
;
2317 case BRW_OPCODE_CMP
:
2318 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2320 inst
->src
[0].negate
&&
2321 inst
->src
[1].is_zero()) {
2322 inst
->src
[0].abs
= false;
2323 inst
->src
[0].negate
= false;
2324 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2329 case BRW_OPCODE_SEL
:
2330 if (inst
->src
[0].equals(inst
->src
[1])) {
2331 inst
->opcode
= BRW_OPCODE_MOV
;
2332 inst
->src
[1] = reg_undef
;
2333 inst
->predicate
= BRW_PREDICATE_NONE
;
2334 inst
->predicate_inverse
= false;
2336 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2337 switch (inst
->conditional_mod
) {
2338 case BRW_CONDITIONAL_LE
:
2339 case BRW_CONDITIONAL_L
:
2340 switch (inst
->src
[1].type
) {
2341 case BRW_REGISTER_TYPE_F
:
2342 if (inst
->src
[1].f
>= 1.0f
) {
2343 inst
->opcode
= BRW_OPCODE_MOV
;
2344 inst
->src
[1] = reg_undef
;
2345 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2353 case BRW_CONDITIONAL_GE
:
2354 case BRW_CONDITIONAL_G
:
2355 switch (inst
->src
[1].type
) {
2356 case BRW_REGISTER_TYPE_F
:
2357 if (inst
->src
[1].f
<= 0.0f
) {
2358 inst
->opcode
= BRW_OPCODE_MOV
;
2359 inst
->src
[1] = reg_undef
;
2360 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2372 case BRW_OPCODE_MAD
:
2373 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2374 inst
->opcode
= BRW_OPCODE_MOV
;
2375 inst
->src
[1] = reg_undef
;
2376 inst
->src
[2] = reg_undef
;
2378 } else if (inst
->src
[0].is_zero()) {
2379 inst
->opcode
= BRW_OPCODE_MUL
;
2380 inst
->src
[0] = inst
->src
[2];
2381 inst
->src
[2] = reg_undef
;
2383 } else if (inst
->src
[1].is_one()) {
2384 inst
->opcode
= BRW_OPCODE_ADD
;
2385 inst
->src
[1] = inst
->src
[2];
2386 inst
->src
[2] = reg_undef
;
2388 } else if (inst
->src
[2].is_one()) {
2389 inst
->opcode
= BRW_OPCODE_ADD
;
2390 inst
->src
[2] = reg_undef
;
2392 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2393 inst
->opcode
= BRW_OPCODE_ADD
;
2394 inst
->src
[1].f
*= inst
->src
[2].f
;
2395 inst
->src
[2] = reg_undef
;
2399 case SHADER_OPCODE_BROADCAST
:
2400 if (is_uniform(inst
->src
[0])) {
2401 inst
->opcode
= BRW_OPCODE_MOV
;
2403 inst
->force_writemask_all
= true;
2405 } else if (inst
->src
[1].file
== IMM
) {
2406 inst
->opcode
= BRW_OPCODE_MOV
;
2407 inst
->src
[0] = component(inst
->src
[0],
2410 inst
->force_writemask_all
= true;
2419 /* Swap if src[0] is immediate. */
2420 if (progress
&& inst
->is_commutative()) {
2421 if (inst
->src
[0].file
== IMM
) {
2422 fs_reg tmp
= inst
->src
[1];
2423 inst
->src
[1] = inst
->src
[0];
2432 * Optimize sample messages that have constant zero values for the trailing
2433 * texture coordinates. We can just reduce the message length for these
2434 * instructions instead of reserving a register for it. Trailing parameters
2435 * that aren't sent default to zero anyway. This will cause the dead code
2436 * eliminator to remove the MOV instruction that would otherwise be emitted to
2437 * set up the zero value.
2440 fs_visitor::opt_zero_samples()
2442 /* Gen4 infers the texturing opcode based on the message length so we can't
2445 if (devinfo
->gen
< 5)
2448 bool progress
= false;
2450 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2451 if (!inst
->is_tex())
2454 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2456 if (load_payload
->is_head_sentinel() ||
2457 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2460 /* We don't want to remove the message header or the first parameter.
2461 * Removing the first parameter is not allowed, see the Haswell PRM
2462 * volume 7, page 149:
2464 * "Parameter 0 is required except for the sampleinfo message, which
2465 * has no parameter 0"
2467 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2468 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2469 (inst
->exec_size
/ 8) +
2470 inst
->header_size
- 1].is_zero()) {
2471 inst
->mlen
-= inst
->exec_size
/ 8;
2477 invalidate_live_intervals();
2483 * Optimize sample messages which are followed by the final RT write.
2485 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2486 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2487 * final texturing results copied to the framebuffer write payload and modify
2488 * them to write to the framebuffer directly.
2491 fs_visitor::opt_sampler_eot()
2493 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2495 if (stage
!= MESA_SHADER_FRAGMENT
)
2498 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2501 /* FINISHME: It should be possible to implement this optimization when there
2502 * are multiple drawbuffers.
2504 if (key
->nr_color_regions
!= 1)
2507 /* Requires emitting a bunch of saturating MOV instructions during logical
2508 * send lowering to clamp the color payload, which the sampler unit isn't
2509 * going to do for us.
2511 if (key
->clamp_fragment_color
)
2514 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2515 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2516 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2517 assert(fb_write
->eot
);
2518 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2520 /* There wasn't one; nothing to do. */
2521 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2524 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2526 /* 3D Sampler » Messages » Message Format
2528 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2529 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2531 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2532 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2533 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2534 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2535 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2536 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2537 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2538 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2541 /* XXX - This shouldn't be necessary. */
2542 if (tex_inst
->prev
->is_head_sentinel())
2545 /* Check that the FB write sources are fully initialized by the single
2546 * texturing instruction.
2548 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2549 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2550 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2551 fb_write
->regs_read(i
) != tex_inst
->regs_written
)
2553 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2554 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2559 assert(!tex_inst
->eot
); /* We can't get here twice */
2560 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2562 const fs_builder
ibld(this, block
, tex_inst
);
2564 tex_inst
->offset
|= fb_write
->target
<< 24;
2565 tex_inst
->eot
= true;
2566 tex_inst
->dst
= ibld
.null_reg_ud();
2567 tex_inst
->regs_written
= 0;
2568 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2570 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2571 * flag and submit a header together with the sampler message as required
2574 invalidate_live_intervals();
2579 fs_visitor::opt_register_renaming()
2581 bool progress
= false;
2584 int remap
[alloc
.count
];
2585 memset(remap
, -1, sizeof(int) * alloc
.count
);
2587 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2588 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2590 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2591 inst
->opcode
== BRW_OPCODE_WHILE
) {
2595 /* Rewrite instruction sources. */
2596 for (int i
= 0; i
< inst
->sources
; i
++) {
2597 if (inst
->src
[i
].file
== VGRF
&&
2598 remap
[inst
->src
[i
].nr
] != -1 &&
2599 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2600 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2605 const int dst
= inst
->dst
.nr
;
2608 inst
->dst
.file
== VGRF
&&
2609 alloc
.sizes
[inst
->dst
.nr
] == inst
->regs_written
&&
2610 !inst
->is_partial_write()) {
2611 if (remap
[dst
] == -1) {
2614 remap
[dst
] = alloc
.allocate(regs_written(inst
));
2615 inst
->dst
.nr
= remap
[dst
];
2618 } else if (inst
->dst
.file
== VGRF
&&
2620 remap
[dst
] != dst
) {
2621 inst
->dst
.nr
= remap
[dst
];
2627 invalidate_live_intervals();
2629 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2630 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2631 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2640 * Remove redundant or useless discard jumps.
2642 * For example, we can eliminate jumps in the following sequence:
2644 * discard-jump (redundant with the next jump)
2645 * discard-jump (useless; jumps to the next instruction)
2649 fs_visitor::opt_redundant_discard_jumps()
2651 bool progress
= false;
2653 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2655 fs_inst
*placeholder_halt
= NULL
;
2656 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2657 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2658 placeholder_halt
= inst
;
2663 if (!placeholder_halt
)
2666 /* Delete any HALTs immediately before the placeholder halt. */
2667 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2668 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2669 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2670 prev
->remove(last_bblock
);
2675 invalidate_live_intervals();
2681 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2682 * from \p r which overlaps the region starting at \p r and spanning \p n GRF
2685 static inline unsigned
2686 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned n
)
2688 const int rel_offset
= (reg_offset(s
) - reg_offset(r
)) / REG_SIZE
;
2689 assert(reg_space(r
) == reg_space(s
) &&
2690 rel_offset
>= 0 && rel_offset
< int(8 * sizeof(unsigned)));
2691 return ((1 << n
) - 1) << rel_offset
;
2695 fs_visitor::compute_to_mrf()
2697 bool progress
= false;
2700 /* No MRFs on Gen >= 7. */
2701 if (devinfo
->gen
>= 7)
2704 calculate_live_intervals();
2706 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2710 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2711 inst
->is_partial_write() ||
2712 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2713 inst
->dst
.type
!= inst
->src
[0].type
||
2714 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2715 !inst
->src
[0].is_contiguous() ||
2716 inst
->src
[0].offset
% REG_SIZE
!= 0)
2719 /* Can't compute-to-MRF this GRF if someone else was going to
2722 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2725 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
2726 * things that computed the value of all GRFs of the source region. The
2727 * regs_left bitset keeps track of the registers we haven't yet found a
2728 * generating instruction for.
2730 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
2732 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2733 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2734 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2735 /* Found the last thing to write our reg we want to turn
2736 * into a compute-to-MRF.
2739 /* If this one instruction didn't populate all the
2740 * channels, bail. We might be able to rewrite everything
2741 * that writes that reg, but it would require smarter
2744 if (scan_inst
->is_partial_write())
2747 /* Handling things not fully contained in the source of the copy
2748 * would need us to understand coalescing out more than one MOV at
2751 if (scan_inst
->dst
.offset
/ REG_SIZE
< inst
->src
[0].offset
/ REG_SIZE
||
2752 scan_inst
->dst
.offset
/ REG_SIZE
+ scan_inst
->regs_written
>
2753 inst
->src
[0].offset
/ REG_SIZE
+ inst
->regs_read(0))
2756 /* SEND instructions can't have MRF as a destination. */
2757 if (scan_inst
->mlen
)
2760 if (devinfo
->gen
== 6) {
2761 /* gen6 math instructions must have the destination be
2762 * GRF, so no compute-to-MRF for them.
2764 if (scan_inst
->is_math()) {
2769 /* Clear the bits for any registers this instruction overwrites. */
2770 regs_left
&= ~mask_relative_to(
2771 inst
->src
[0], scan_inst
->dst
, scan_inst
->regs_written
);
2776 /* We don't handle control flow here. Most computation of
2777 * values that end up in MRFs are shortly before the MRF
2780 if (block
->start() == scan_inst
)
2783 /* You can't read from an MRF, so if someone else reads our
2784 * MRF's source GRF that we wanted to rewrite, that stops us.
2786 bool interfered
= false;
2787 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2788 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->regs_read(i
) * REG_SIZE
,
2789 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2796 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2797 inst
->dst
, inst
->regs_written
* REG_SIZE
)) {
2798 /* If somebody else writes our MRF here, we can't
2799 * compute-to-MRF before that.
2804 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
2805 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
2806 inst
->dst
, inst
->regs_written
* REG_SIZE
)) {
2807 /* Found a SEND instruction, which means that there are
2808 * live values in MRFs from base_mrf to base_mrf +
2809 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2819 /* Found all generating instructions of our MRF's source value, so it
2820 * should be safe to rewrite them to point to the MRF directly.
2822 regs_left
= (1 << regs_read(inst
, 0)) - 1;
2824 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2825 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2826 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2827 /* Clear the bits for any registers this instruction overwrites. */
2828 regs_left
&= ~mask_relative_to(
2829 inst
->src
[0], scan_inst
->dst
, scan_inst
->regs_written
);
2831 const unsigned rel_offset
= (reg_offset(scan_inst
->dst
) -
2832 reg_offset(inst
->src
[0])) / REG_SIZE
;
2834 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2835 /* Apply the same address transformation done by the hardware
2836 * for COMPR4 MRF writes.
2838 assert(rel_offset
< 2);
2839 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
* 4;
2841 /* Clear the COMPR4 bit if the generating instruction is not
2844 if (scan_inst
->regs_written
< 2)
2845 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
2848 /* Calculate the MRF number the result of this instruction is
2849 * ultimately written to.
2851 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
;
2854 scan_inst
->dst
.file
= MRF
;
2855 scan_inst
->dst
.offset
%= REG_SIZE
;
2856 scan_inst
->saturate
|= inst
->saturate
;
2863 inst
->remove(block
);
2868 invalidate_live_intervals();
2874 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2875 * flow. We could probably do better here with some form of divergence
2879 fs_visitor::eliminate_find_live_channel()
2881 bool progress
= false;
2884 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2885 switch (inst
->opcode
) {
2891 case BRW_OPCODE_ENDIF
:
2892 case BRW_OPCODE_WHILE
:
2896 case FS_OPCODE_DISCARD_JUMP
:
2897 /* This can potentially make control flow non-uniform until the end
2902 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2904 inst
->opcode
= BRW_OPCODE_MOV
;
2905 inst
->src
[0] = brw_imm_ud(0u);
2907 inst
->force_writemask_all
= true;
2921 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2922 * instructions to FS_OPCODE_REP_FB_WRITE.
2925 fs_visitor::emit_repclear_shader()
2927 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2929 int color_mrf
= base_mrf
+ 2;
2933 mov
= bld
.exec_all().group(4, 0)
2934 .MOV(brw_message_reg(color_mrf
),
2935 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2937 struct brw_reg reg
=
2938 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2939 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
2940 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2942 mov
= bld
.exec_all().group(4, 0)
2943 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
2947 if (key
->nr_color_regions
== 1) {
2948 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2949 write
->saturate
= key
->clamp_fragment_color
;
2950 write
->base_mrf
= color_mrf
;
2952 write
->header_size
= 0;
2955 assume(key
->nr_color_regions
> 0);
2956 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2957 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2958 write
->saturate
= key
->clamp_fragment_color
;
2959 write
->base_mrf
= base_mrf
;
2961 write
->header_size
= 2;
2969 assign_constant_locations();
2970 assign_curb_setup();
2972 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2974 assert(mov
->src
[0].file
== FIXED_GRF
);
2975 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2980 * Walks through basic blocks, looking for repeated MRF writes and
2981 * removing the later ones.
2984 fs_visitor::remove_duplicate_mrf_writes()
2986 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2987 bool progress
= false;
2989 /* Need to update the MRF tracking for compressed instructions. */
2990 if (dispatch_width
>= 16)
2993 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2995 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2996 if (inst
->is_control_flow()) {
2997 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3000 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3001 inst
->dst
.file
== MRF
) {
3002 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3003 if (prev_inst
&& inst
->equals(prev_inst
)) {
3004 inst
->remove(block
);
3010 /* Clear out the last-write records for MRFs that were overwritten. */
3011 if (inst
->dst
.file
== MRF
) {
3012 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3015 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3016 /* Found a SEND instruction, which will include two or fewer
3017 * implied MRF writes. We could do better here.
3019 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3020 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3024 /* Clear out any MRF move records whose sources got overwritten. */
3025 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3026 if (last_mrf_move
[i
] &&
3027 regions_overlap(inst
->dst
, inst
->regs_written
* REG_SIZE
,
3028 last_mrf_move
[i
]->src
[0],
3029 last_mrf_move
[i
]->regs_read(0) * REG_SIZE
)) {
3030 last_mrf_move
[i
] = NULL
;
3034 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3035 inst
->dst
.file
== MRF
&&
3036 inst
->src
[0].file
!= ARF
&&
3037 !inst
->is_partial_write()) {
3038 last_mrf_move
[inst
->dst
.nr
] = inst
;
3043 invalidate_live_intervals();
3049 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3051 /* Clear the flag for registers that actually got read (as expected). */
3052 for (int i
= 0; i
< inst
->sources
; i
++) {
3054 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3055 grf
= inst
->src
[i
].nr
;
3060 if (grf
>= first_grf
&&
3061 grf
< first_grf
+ grf_len
) {
3062 deps
[grf
- first_grf
] = false;
3063 if (inst
->exec_size
== 16)
3064 deps
[grf
- first_grf
+ 1] = false;
3070 * Implements this workaround for the original 965:
3072 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3073 * check for post destination dependencies on this instruction, software
3074 * must ensure that there is no destination hazard for the case of ‘write
3075 * followed by a posted write’ shown in the following example.
3078 * 2. send r3.xy <rest of send instruction>
3081 * Due to no post-destination dependency check on the ‘send’, the above
3082 * code sequence could have two instructions (1 and 2) in flight at the
3083 * same time that both consider ‘r3’ as the target of their final writes.
3086 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3089 int write_len
= regs_written(inst
);
3090 int first_write_grf
= inst
->dst
.nr
;
3091 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3092 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3094 memset(needs_dep
, false, sizeof(needs_dep
));
3095 memset(needs_dep
, true, write_len
);
3097 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3099 /* Walk backwards looking for writes to registers we're writing which
3100 * aren't read since being written. If we hit the start of the program,
3101 * we assume that there are no outstanding dependencies on entry to the
3104 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3105 /* If we hit control flow, assume that there *are* outstanding
3106 * dependencies, and force their cleanup before our instruction.
3108 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3109 for (int i
= 0; i
< write_len
; i
++) {
3111 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3112 first_write_grf
+ i
);
3117 /* We insert our reads as late as possible on the assumption that any
3118 * instruction but a MOV that might have left us an outstanding
3119 * dependency has more latency than a MOV.
3121 if (scan_inst
->dst
.file
== VGRF
) {
3122 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3123 int reg
= scan_inst
->dst
.nr
+ i
;
3125 if (reg
>= first_write_grf
&&
3126 reg
< first_write_grf
+ write_len
&&
3127 needs_dep
[reg
- first_write_grf
]) {
3128 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3129 needs_dep
[reg
- first_write_grf
] = false;
3130 if (scan_inst
->exec_size
== 16)
3131 needs_dep
[reg
- first_write_grf
+ 1] = false;
3136 /* Clear the flag for registers that actually got read (as expected). */
3137 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3139 /* Continue the loop only if we haven't resolved all the dependencies */
3141 for (i
= 0; i
< write_len
; i
++) {
3151 * Implements this workaround for the original 965:
3153 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3154 * used as a destination register until after it has been sourced by an
3155 * instruction with a different destination register.
3158 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3160 int write_len
= regs_written(inst
);
3161 int first_write_grf
= inst
->dst
.nr
;
3162 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3163 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3165 memset(needs_dep
, false, sizeof(needs_dep
));
3166 memset(needs_dep
, true, write_len
);
3167 /* Walk forwards looking for writes to registers we're writing which aren't
3168 * read before being written.
3170 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3171 /* If we hit control flow, force resolve all remaining dependencies. */
3172 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3173 for (int i
= 0; i
< write_len
; i
++) {
3175 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3176 first_write_grf
+ i
);
3181 /* Clear the flag for registers that actually got read (as expected). */
3182 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3184 /* We insert our reads as late as possible since they're reading the
3185 * result of a SEND, which has massive latency.
3187 if (scan_inst
->dst
.file
== VGRF
&&
3188 scan_inst
->dst
.nr
>= first_write_grf
&&
3189 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3190 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3191 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3193 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3196 /* Continue the loop only if we haven't resolved all the dependencies */
3198 for (i
= 0; i
< write_len
; i
++) {
3208 fs_visitor::insert_gen4_send_dependency_workarounds()
3210 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3213 bool progress
= false;
3215 /* Note that we're done with register allocation, so GRF fs_regs always
3216 * have a .reg_offset of 0.
3219 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3220 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3221 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3222 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3228 invalidate_live_intervals();
3232 * Turns the generic expression-style uniform pull constant load instruction
3233 * into a hardware-specific series of instructions for loading a pull
3236 * The expression style allows the CSE pass before this to optimize out
3237 * repeated loads from the same offset, and gives the pre-register-allocation
3238 * scheduling full flexibility, while the conversion to native instructions
3239 * allows the post-register-allocation scheduler the best information
3242 * Note that execution masking for setting up pull constant loads is special:
3243 * the channels that need to be written are unrelated to the current execution
3244 * mask, since a later instruction will use one of the result channels as a
3245 * source operand for all 8 or 16 of its channels.
3248 fs_visitor::lower_uniform_pull_constant_loads()
3250 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3251 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3254 if (devinfo
->gen
>= 7) {
3255 /* The offset arg is a vec4-aligned immediate byte offset. */
3256 fs_reg const_offset_reg
= inst
->src
[1];
3257 assert(const_offset_reg
.file
== IMM
&&
3258 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3259 assert(const_offset_reg
.ud
% 16 == 0);
3261 fs_reg payload
, offset
;
3262 if (devinfo
->gen
>= 9) {
3263 /* We have to use a message header on Skylake to get SIMD4x2
3264 * mode. Reserve space for the register.
3266 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3267 offset
.offset
+= REG_SIZE
;
3270 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3274 /* This is actually going to be a MOV, but since only the first dword
3275 * is accessed, we have a special opcode to do just that one. Note
3276 * that this needs to be an operation that will be considered a def
3277 * by live variable analysis, or register allocation will explode.
3279 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3280 8, offset
, const_offset_reg
);
3281 setup
->force_writemask_all
= true;
3283 setup
->ir
= inst
->ir
;
3284 setup
->annotation
= inst
->annotation
;
3285 inst
->insert_before(block
, setup
);
3287 /* Similarly, this will only populate the first 4 channels of the
3288 * result register (since we only use smear values from 0-3), but we
3289 * don't tell the optimizer.
3291 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3292 inst
->src
[1] = payload
;
3294 invalidate_live_intervals();
3296 /* Before register allocation, we didn't tell the scheduler about the
3297 * MRF we use. We know it's safe to use this MRF because nothing
3298 * else does except for register spill/unspill, which generates and
3299 * uses its MRF within a single IR instruction.
3301 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3308 fs_visitor::lower_load_payload()
3310 bool progress
= false;
3312 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3313 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3316 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3317 assert(inst
->saturate
== false);
3318 fs_reg dst
= inst
->dst
;
3320 /* Get rid of COMPR4. We'll add it back in if we need it */
3321 if (dst
.file
== MRF
)
3322 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3324 const fs_builder
ibld(this, block
, inst
);
3325 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3327 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3328 if (inst
->src
[i
].file
!= BAD_FILE
) {
3329 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3330 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3331 hbld
.MOV(mov_dst
, mov_src
);
3333 dst
= offset(dst
, hbld
, 1);
3336 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3337 inst
->exec_size
> 8) {
3338 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3339 * a straightforward copy. Instead, the result of the
3340 * LOAD_PAYLOAD is treated as interleaved and the first four
3341 * non-header sources are unpacked as:
3352 * This is used for gen <= 5 fb writes.
3354 assert(inst
->exec_size
== 16);
3355 assert(inst
->header_size
+ 4 <= inst
->sources
);
3356 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3357 if (inst
->src
[i
].file
!= BAD_FILE
) {
3358 if (devinfo
->has_compr4
) {
3359 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3360 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3361 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3363 /* Platform doesn't have COMPR4. We have to fake it */
3364 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3365 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3367 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3374 /* The loop above only ever incremented us through the first set
3375 * of 4 registers. However, thanks to the magic of COMPR4, we
3376 * actually wrote to the first 8 registers, so we need to take
3377 * that into account now.
3381 /* The COMPR4 code took care of the first 4 sources. We'll let
3382 * the regular path handle any remaining sources. Yes, we are
3383 * modifying the instruction but we're about to delete it so
3384 * this really doesn't hurt anything.
3386 inst
->header_size
+= 4;
3389 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3390 if (inst
->src
[i
].file
!= BAD_FILE
)
3391 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3392 dst
= offset(dst
, ibld
, 1);
3395 inst
->remove(block
);
3400 invalidate_live_intervals();
3406 fs_visitor::lower_integer_multiplication()
3408 bool progress
= false;
3410 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3411 const fs_builder
ibld(this, block
, inst
);
3413 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3414 if (inst
->dst
.is_accumulator() ||
3415 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3416 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3419 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3420 * operation directly, but CHV/BXT cannot.
3422 if (devinfo
->gen
>= 8 &&
3423 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3426 if (inst
->src
[1].file
== IMM
&&
3427 inst
->src
[1].ud
< (1 << 16)) {
3428 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3429 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3432 * If multiplying by an immediate value that fits in 16-bits, do a
3433 * single MUL instruction with that value in the proper location.
3435 if (devinfo
->gen
< 7) {
3436 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3438 ibld
.MOV(imm
, inst
->src
[1]);
3439 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3441 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3442 ibld
.MUL(inst
->dst
, inst
->src
[0],
3443 ud
? brw_imm_uw(inst
->src
[1].ud
)
3444 : brw_imm_w(inst
->src
[1].d
));
3447 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3448 * do 32-bit integer multiplication in one instruction, but instead
3449 * must do a sequence (which actually calculates a 64-bit result):
3451 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3452 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3453 * mov(8) g2<1>D acc0<8,8,1>D
3455 * But on Gen > 6, the ability to use second accumulator register
3456 * (acc1) for non-float data types was removed, preventing a simple
3457 * implementation in SIMD16. A 16-channel result can be calculated by
3458 * executing the three instructions twice in SIMD8, once with quarter
3459 * control of 1Q for the first eight channels and again with 2Q for
3460 * the second eight channels.
3462 * Which accumulator register is implicitly accessed (by AccWrEnable
3463 * for instance) is determined by the quarter control. Unfortunately
3464 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3465 * implicit accumulator access by an instruction with 2Q will access
3466 * acc1 regardless of whether the data type is usable in acc1.
3468 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3469 * integer data types.
3471 * Since we only want the low 32-bits of the result, we can do two
3472 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3473 * adjust the high result and add them (like the mach is doing):
3475 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3476 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3477 * shl(8) g9<1>D g8<8,8,1>D 16D
3478 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3480 * We avoid the shl instruction by realizing that we only want to add
3481 * the low 16-bits of the "high" result to the high 16-bits of the
3482 * "low" result and using proper regioning on the add:
3484 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3485 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3486 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3488 * Since it does not use the (single) accumulator register, we can
3489 * schedule multi-component multiplications much better.
3492 fs_reg orig_dst
= inst
->dst
;
3493 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3494 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3497 fs_reg low
= inst
->dst
;
3498 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3501 if (devinfo
->gen
>= 7) {
3502 fs_reg src1_0_w
= inst
->src
[1];
3503 fs_reg src1_1_w
= inst
->src
[1];
3505 if (inst
->src
[1].file
== IMM
) {
3506 src1_0_w
.ud
&= 0xffff;
3509 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3510 if (src1_0_w
.stride
!= 0) {
3511 assert(src1_0_w
.stride
== 1);
3512 src1_0_w
.stride
= 2;
3515 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3516 if (src1_1_w
.stride
!= 0) {
3517 assert(src1_1_w
.stride
== 1);
3518 src1_1_w
.stride
= 2;
3520 src1_1_w
.offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3522 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3523 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3525 fs_reg src0_0_w
= inst
->src
[0];
3526 fs_reg src0_1_w
= inst
->src
[0];
3528 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3529 if (src0_0_w
.stride
!= 0) {
3530 assert(src0_0_w
.stride
== 1);
3531 src0_0_w
.stride
= 2;
3534 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3535 if (src0_1_w
.stride
!= 0) {
3536 assert(src0_1_w
.stride
== 1);
3537 src0_1_w
.stride
= 2;
3539 src0_1_w
.offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3541 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3542 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3545 fs_reg dst
= inst
->dst
;
3546 dst
.type
= BRW_REGISTER_TYPE_UW
;
3547 dst
.offset
= ROUND_DOWN_TO(dst
.offset
, REG_SIZE
) + 2;
3550 high
.type
= BRW_REGISTER_TYPE_UW
;
3553 low
.type
= BRW_REGISTER_TYPE_UW
;
3554 low
.offset
= ROUND_DOWN_TO(low
.offset
, REG_SIZE
) + 2;
3557 ibld
.ADD(dst
, low
, high
);
3559 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3560 set_condmod(inst
->conditional_mod
,
3561 ibld
.MOV(orig_dst
, inst
->dst
));
3565 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3566 /* Should have been lowered to 8-wide. */
3567 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
3568 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3570 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3571 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3573 if (devinfo
->gen
>= 8) {
3574 /* Until Gen8, integer multiplies read 32-bits from one source,
3575 * and 16-bits from the other, and relying on the MACH instruction
3576 * to generate the high bits of the result.
3578 * On Gen8, the multiply instruction does a full 32x32-bit
3579 * multiply, but in order to do a 64-bit multiply we can simulate
3580 * the previous behavior and then use a MACH instruction.
3582 * FINISHME: Don't use source modifiers on src1.
3584 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3585 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3586 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3587 mul
->src
[1].stride
*= 2;
3589 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3591 /* Among other things the quarter control bits influence which
3592 * accumulator register is used by the hardware for instructions
3593 * that access the accumulator implicitly (e.g. MACH). A
3594 * second-half instruction would normally map to acc1, which
3595 * doesn't exist on Gen7 and up (the hardware does emulate it for
3596 * floating-point instructions *only* by taking advantage of the
3597 * extra precision of acc0 not normally used for floating point
3600 * HSW and up are careful enough not to try to access an
3601 * accumulator register that doesn't exist, but on earlier Gen7
3602 * hardware we need to make sure that the quarter control bits are
3603 * zero to avoid non-deterministic behaviour and emit an extra MOV
3604 * to get the result masked correctly according to the current
3608 mach
->force_writemask_all
= true;
3609 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3610 ibld
.MOV(inst
->dst
, mach
->dst
);
3616 inst
->remove(block
);
3621 invalidate_live_intervals();
3627 fs_visitor::lower_minmax()
3629 assert(devinfo
->gen
< 6);
3631 bool progress
= false;
3633 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3634 const fs_builder
ibld(this, block
, inst
);
3636 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3637 inst
->predicate
== BRW_PREDICATE_NONE
) {
3638 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3639 * the original SEL.L/GE instruction
3641 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3642 inst
->conditional_mod
);
3643 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3644 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3651 invalidate_live_intervals();
3657 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3658 fs_reg
*dst
, fs_reg color
, unsigned components
)
3660 if (key
->clamp_fragment_color
) {
3661 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3662 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3664 for (unsigned i
= 0; i
< components
; i
++)
3666 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3671 for (unsigned i
= 0; i
< components
; i
++)
3672 dst
[i
] = offset(color
, bld
, i
);
3676 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3677 const brw_wm_prog_data
*prog_data
,
3678 const brw_wm_prog_key
*key
,
3679 const fs_visitor::thread_payload
&payload
)
3681 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3682 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3683 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3684 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3685 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3686 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3687 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3688 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3689 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3690 const unsigned components
=
3691 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3693 /* We can potentially have a message length of up to 15, so we have to set
3694 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3697 int header_size
= 2, payload_header_size
;
3698 unsigned length
= 0;
3700 /* From the Sandy Bridge PRM, volume 4, page 198:
3702 * "Dispatched Pixel Enables. One bit per pixel indicating
3703 * which pixels were originally enabled when the thread was
3704 * dispatched. This field is only required for the end-of-
3705 * thread message and on all dual-source messages."
3707 if (devinfo
->gen
>= 6 &&
3708 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3709 color1
.file
== BAD_FILE
&&
3710 key
->nr_color_regions
== 1) {
3714 if (header_size
!= 0) {
3715 assert(header_size
== 2);
3716 /* Allocate 2 registers for a header */
3720 if (payload
.aa_dest_stencil_reg
) {
3721 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3722 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3723 .MOV(sources
[length
],
3724 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3728 if (sample_mask
.file
!= BAD_FILE
) {
3729 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3730 BRW_REGISTER_TYPE_UD
);
3732 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3733 * relevant. Since it's unsigned single words one vgrf is always
3734 * 16-wide, but only the lower or higher 8 channels will be used by the
3735 * hardware when doing a SIMD8 write depending on whether we have
3736 * selected the subspans for the first or second half respectively.
3738 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3739 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3740 sample_mask
.stride
*= 2;
3742 bld
.exec_all().annotate("FB write oMask")
3743 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3749 payload_header_size
= length
;
3751 if (src0_alpha
.file
!= BAD_FILE
) {
3752 /* FIXME: This is being passed at the wrong location in the payload and
3753 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3754 * It's supposed to be immediately before oMask but there seems to be no
3755 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3756 * requires header sources to form a contiguous segment at the beginning
3757 * of the message and src0_alpha has per-channel semantics.
3759 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3763 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3766 if (color1
.file
!= BAD_FILE
) {
3767 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3771 if (src_depth
.file
!= BAD_FILE
) {
3772 sources
[length
] = src_depth
;
3776 if (dst_depth
.file
!= BAD_FILE
) {
3777 sources
[length
] = dst_depth
;
3781 if (src_stencil
.file
!= BAD_FILE
) {
3782 assert(devinfo
->gen
>= 9);
3783 assert(bld
.dispatch_width() != 16);
3785 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3786 * available on gen9+. As such it's impossible to have both enabled at the
3787 * same time and therefore length cannot overrun the array.
3789 assert(length
< 15);
3791 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3792 bld
.exec_all().annotate("FB write OS")
3793 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
3794 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
3799 if (devinfo
->gen
>= 7) {
3800 /* Send from the GRF */
3801 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3802 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3803 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
3804 load
->dst
= payload
;
3806 inst
->src
[0] = payload
;
3807 inst
->resize_sources(1);
3809 /* Send from the MRF */
3810 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3811 sources
, length
, payload_header_size
);
3813 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3814 * will do this for us if we just give it a COMPR4 destination.
3816 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3817 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3819 inst
->resize_sources(0);
3823 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3824 inst
->mlen
= regs_written(load
);
3825 inst
->header_size
= header_size
;
3829 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
3831 const fs_builder
&ubld
= bld
.exec_all();
3832 const unsigned length
= 2;
3833 const fs_reg header
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
, length
);
3836 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3838 inst
->resize_sources(1);
3839 inst
->src
[0] = header
;
3840 inst
->opcode
= FS_OPCODE_FB_READ
;
3841 inst
->mlen
= length
;
3842 inst
->header_size
= length
;
3846 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3847 const fs_reg
&coordinate
,
3848 const fs_reg
&shadow_c
,
3849 const fs_reg
&lod
, const fs_reg
&lod2
,
3850 const fs_reg
&surface
,
3851 const fs_reg
&sampler
,
3852 unsigned coord_components
,
3853 unsigned grad_components
)
3855 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3856 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3857 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3858 fs_reg msg_end
= msg_begin
;
3861 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3863 for (unsigned i
= 0; i
< coord_components
; i
++)
3864 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3865 offset(coordinate
, bld
, i
));
3867 msg_end
= offset(msg_end
, bld
, coord_components
);
3869 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3870 * require all three components to be present and zero if they are unused.
3872 if (coord_components
> 0 &&
3873 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3874 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3875 for (unsigned i
= coord_components
; i
< 3; i
++)
3876 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3878 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3881 if (op
== SHADER_OPCODE_TXD
) {
3882 /* TXD unsupported in SIMD16 mode. */
3883 assert(bld
.dispatch_width() == 8);
3885 /* the slots for u and v are always present, but r is optional */
3886 if (coord_components
< 2)
3887 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3890 * dPdx = dudx, dvdx, drdx
3891 * dPdy = dudy, dvdy, drdy
3893 * 1-arg: Does not exist.
3895 * 2-arg: dudx dvdx dudy dvdy
3896 * dPdx.x dPdx.y dPdy.x dPdy.y
3899 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3900 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3901 * m5 m6 m7 m8 m9 m10
3903 for (unsigned i
= 0; i
< grad_components
; i
++)
3904 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3906 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3908 for (unsigned i
= 0; i
< grad_components
; i
++)
3909 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3911 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3915 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3916 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3918 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3919 bld
.dispatch_width() == 16);
3921 const brw_reg_type type
=
3922 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3923 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3924 bld
.MOV(retype(msg_end
, type
), lod
);
3925 msg_end
= offset(msg_end
, bld
, 1);
3928 if (shadow_c
.file
!= BAD_FILE
) {
3929 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3930 /* There's no plain shadow compare message, so we use shadow
3931 * compare with a bias of 0.0.
3933 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3934 msg_end
= offset(msg_end
, bld
, 1);
3937 bld
.MOV(msg_end
, shadow_c
);
3938 msg_end
= offset(msg_end
, bld
, 1);
3942 inst
->src
[0] = reg_undef
;
3943 inst
->src
[1] = surface
;
3944 inst
->src
[2] = sampler
;
3945 inst
->resize_sources(3);
3946 inst
->base_mrf
= msg_begin
.nr
;
3947 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3948 inst
->header_size
= 1;
3952 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3953 const fs_reg
&coordinate
,
3954 const fs_reg
&shadow_c
,
3955 const fs_reg
&lod
, const fs_reg
&lod2
,
3956 const fs_reg
&sample_index
,
3957 const fs_reg
&surface
,
3958 const fs_reg
&sampler
,
3959 const fs_reg
&offset_value
,
3960 unsigned coord_components
,
3961 unsigned grad_components
)
3963 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3964 fs_reg msg_coords
= message
;
3965 unsigned header_size
= 0;
3967 if (offset_value
.file
!= BAD_FILE
) {
3968 /* The offsets set up by the visitor are in the m1 header, so we can't
3975 for (unsigned i
= 0; i
< coord_components
; i
++)
3976 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
3977 offset(coordinate
, bld
, i
));
3979 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3980 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3982 if (shadow_c
.file
!= BAD_FILE
) {
3983 fs_reg msg_shadow
= msg_lod
;
3984 bld
.MOV(msg_shadow
, shadow_c
);
3985 msg_lod
= offset(msg_shadow
, bld
, 1);
3990 case SHADER_OPCODE_TXL
:
3992 bld
.MOV(msg_lod
, lod
);
3993 msg_end
= offset(msg_lod
, bld
, 1);
3995 case SHADER_OPCODE_TXD
:
3998 * dPdx = dudx, dvdx, drdx
3999 * dPdy = dudy, dvdy, drdy
4001 * Load up these values:
4002 * - dudx dudy dvdx dvdy drdx drdy
4003 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
4006 for (unsigned i
= 0; i
< grad_components
; i
++) {
4007 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
4008 msg_end
= offset(msg_end
, bld
, 1);
4010 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
4011 msg_end
= offset(msg_end
, bld
, 1);
4014 case SHADER_OPCODE_TXS
:
4015 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4016 bld
.MOV(msg_lod
, lod
);
4017 msg_end
= offset(msg_lod
, bld
, 1);
4019 case SHADER_OPCODE_TXF
:
4020 msg_lod
= offset(msg_coords
, bld
, 3);
4021 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4022 msg_end
= offset(msg_lod
, bld
, 1);
4024 case SHADER_OPCODE_TXF_CMS
:
4025 msg_lod
= offset(msg_coords
, bld
, 3);
4027 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4029 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4030 msg_end
= offset(msg_lod
, bld
, 2);
4037 inst
->src
[0] = reg_undef
;
4038 inst
->src
[1] = surface
;
4039 inst
->src
[2] = sampler
;
4040 inst
->resize_sources(3);
4041 inst
->base_mrf
= message
.nr
;
4042 inst
->mlen
= msg_end
.nr
- message
.nr
;
4043 inst
->header_size
= header_size
;
4045 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4046 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4050 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
4052 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4055 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4059 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4060 const fs_reg
&coordinate
,
4061 const fs_reg
&shadow_c
,
4062 fs_reg lod
, const fs_reg
&lod2
,
4063 const fs_reg
&sample_index
,
4065 const fs_reg
&surface
,
4066 const fs_reg
&sampler
,
4067 const fs_reg
&offset_value
,
4068 unsigned coord_components
,
4069 unsigned grad_components
)
4071 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4072 unsigned reg_width
= bld
.dispatch_width() / 8;
4073 unsigned header_size
= 0, length
= 0;
4074 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4075 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4076 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4078 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4079 offset_value
.file
!= BAD_FILE
|| inst
->eot
||
4080 op
== SHADER_OPCODE_SAMPLEINFO
||
4081 is_high_sampler(devinfo
, sampler
)) {
4082 /* For general texture offsets (no txf workaround), we need a header to
4083 * put them in. Note that we're only reserving space for it in the
4084 * message payload as it will be initialized implicitly by the
4087 * TG4 needs to place its channel select in the header, for interaction
4088 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4089 * larger sampler numbers we need to offset the Sampler State Pointer in
4093 sources
[0] = fs_reg();
4096 /* If we're requesting fewer than four channels worth of response,
4097 * and we have an explicit header, we need to set up the sampler
4098 * writemask. It's reversed from normal: 1 means "don't write".
4100 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4101 assert(regs_written(inst
) % reg_width
== 0);
4102 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4103 inst
->offset
|= mask
<< 12;
4107 if (shadow_c
.file
!= BAD_FILE
) {
4108 bld
.MOV(sources
[length
], shadow_c
);
4112 bool coordinate_done
= false;
4114 /* Set up the LOD info */
4117 case SHADER_OPCODE_TXL
:
4118 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4119 op
= SHADER_OPCODE_TXL_LZ
;
4122 bld
.MOV(sources
[length
], lod
);
4125 case SHADER_OPCODE_TXD
:
4126 /* TXD should have been lowered in SIMD16 mode. */
4127 assert(bld
.dispatch_width() == 8);
4129 /* Load dPdx and the coordinate together:
4130 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4132 for (unsigned i
= 0; i
< coord_components
; i
++) {
4133 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4135 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4136 * only derivatives for (u, v, r).
4138 if (i
< grad_components
) {
4139 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4140 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4144 coordinate_done
= true;
4146 case SHADER_OPCODE_TXS
:
4147 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4150 case SHADER_OPCODE_TXF
:
4151 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4152 * On Gen9 they are u, v, lod, r
4154 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4156 if (devinfo
->gen
>= 9) {
4157 if (coord_components
>= 2) {
4158 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4159 offset(coordinate
, bld
, 1));
4161 sources
[length
] = brw_imm_d(0);
4166 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4167 op
= SHADER_OPCODE_TXF_LZ
;
4169 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4173 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4174 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4175 offset(coordinate
, bld
, i
));
4177 coordinate_done
= true;
4180 case SHADER_OPCODE_TXF_CMS
:
4181 case SHADER_OPCODE_TXF_CMS_W
:
4182 case SHADER_OPCODE_TXF_UMS
:
4183 case SHADER_OPCODE_TXF_MCS
:
4184 if (op
== SHADER_OPCODE_TXF_UMS
||
4185 op
== SHADER_OPCODE_TXF_CMS
||
4186 op
== SHADER_OPCODE_TXF_CMS_W
) {
4187 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4191 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4192 /* Data from the multisample control surface. */
4193 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4196 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4199 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4200 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4203 offset(mcs
, bld
, 1));
4208 /* There is no offsetting for this message; just copy in the integer
4209 * texture coordinates.
4211 for (unsigned i
= 0; i
< coord_components
; i
++)
4212 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4213 offset(coordinate
, bld
, i
));
4215 coordinate_done
= true;
4217 case SHADER_OPCODE_TG4_OFFSET
:
4218 /* More crazy intermixing */
4219 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4220 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4222 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4223 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4224 offset(offset_value
, bld
, i
));
4226 if (coord_components
== 3) /* r if present */
4227 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4229 coordinate_done
= true;
4235 /* Set up the coordinate (except for cases where it was done above) */
4236 if (!coordinate_done
) {
4237 for (unsigned i
= 0; i
< coord_components
; i
++)
4238 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4243 mlen
= length
* reg_width
- header_size
;
4245 mlen
= length
* reg_width
;
4247 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4248 BRW_REGISTER_TYPE_F
);
4249 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4251 /* Generate the SEND. */
4253 inst
->src
[0] = src_payload
;
4254 inst
->src
[1] = surface
;
4255 inst
->src
[2] = sampler
;
4256 inst
->resize_sources(3);
4258 inst
->header_size
= header_size
;
4260 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4261 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4265 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4267 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4268 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4269 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4270 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4271 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4272 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4273 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4274 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4275 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4276 const fs_reg
&offset_value
= inst
->src
[TEX_LOGICAL_SRC_OFFSET_VALUE
];
4277 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4278 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4279 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4280 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4282 if (devinfo
->gen
>= 7) {
4283 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4284 shadow_c
, lod
, lod2
, sample_index
,
4285 mcs
, surface
, sampler
, offset_value
,
4286 coord_components
, grad_components
);
4287 } else if (devinfo
->gen
>= 5) {
4288 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4289 shadow_c
, lod
, lod2
, sample_index
,
4290 surface
, sampler
, offset_value
,
4291 coord_components
, grad_components
);
4293 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4294 shadow_c
, lod
, lod2
,
4296 coord_components
, grad_components
);
4301 * Initialize the header present in some typed and untyped surface
4305 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4307 fs_builder ubld
= bld
.exec_all().group(8, 0);
4308 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4309 ubld
.MOV(dst
, brw_imm_d(0));
4310 ubld
.MOV(component(dst
, 7), sample_mask
);
4315 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4316 const fs_reg
&sample_mask
)
4318 /* Get the logical send arguments. */
4319 const fs_reg
&addr
= inst
->src
[0];
4320 const fs_reg
&src
= inst
->src
[1];
4321 const fs_reg
&surface
= inst
->src
[2];
4322 const UNUSED fs_reg
&dims
= inst
->src
[3];
4323 const fs_reg
&arg
= inst
->src
[4];
4325 /* Calculate the total number of components of the payload. */
4326 const unsigned addr_sz
= inst
->components_read(0);
4327 const unsigned src_sz
= inst
->components_read(1);
4328 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4329 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4331 /* Allocate space for the payload. */
4332 fs_reg
*const components
= new fs_reg
[sz
];
4333 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4336 /* Construct the payload. */
4338 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4340 for (unsigned i
= 0; i
< addr_sz
; i
++)
4341 components
[n
++] = offset(addr
, bld
, i
);
4343 for (unsigned i
= 0; i
< src_sz
; i
++)
4344 components
[n
++] = offset(src
, bld
, i
);
4346 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4348 /* Update the original instruction. */
4350 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4351 inst
->header_size
= header_sz
;
4353 inst
->src
[0] = payload
;
4354 inst
->src
[1] = surface
;
4356 inst
->resize_sources(3);
4358 delete[] components
;
4362 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4364 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4366 if (devinfo
->gen
>= 7) {
4367 /* We are switching the instruction from an ALU-like instruction to a
4368 * send-from-grf instruction. Since sends can't handle strides or
4369 * source modifiers, we have to make a copy of the offset source.
4371 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4372 bld
.MOV(tmp
, inst
->src
[1]);
4375 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4378 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4379 BRW_REGISTER_TYPE_UD
);
4381 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4383 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4384 inst
->resize_sources(1);
4385 inst
->base_mrf
= payload
.nr
;
4386 inst
->header_size
= 1;
4387 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4392 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4394 assert(bld
.shader
->devinfo
->gen
< 6);
4397 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4399 if (inst
->sources
> 1) {
4400 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4401 * "Message Payload":
4403 * "Operand0[7]. For the INT DIV functions, this operand is the
4406 * "Operand1[7]. For the INT DIV functions, this operand is the
4409 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4410 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4411 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4413 inst
->resize_sources(1);
4414 inst
->src
[0] = src0
;
4416 assert(inst
->exec_size
== 8);
4417 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4422 fs_visitor::lower_logical_sends()
4424 bool progress
= false;
4426 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4427 const fs_builder
ibld(this, block
, inst
);
4429 switch (inst
->opcode
) {
4430 case FS_OPCODE_FB_WRITE_LOGICAL
:
4431 assert(stage
== MESA_SHADER_FRAGMENT
);
4432 lower_fb_write_logical_send(ibld
, inst
,
4433 (const brw_wm_prog_data
*)prog_data
,
4434 (const brw_wm_prog_key
*)key
,
4438 case FS_OPCODE_FB_READ_LOGICAL
:
4439 lower_fb_read_logical_send(ibld
, inst
);
4442 case SHADER_OPCODE_TEX_LOGICAL
:
4443 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4446 case SHADER_OPCODE_TXD_LOGICAL
:
4447 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4450 case SHADER_OPCODE_TXF_LOGICAL
:
4451 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4454 case SHADER_OPCODE_TXL_LOGICAL
:
4455 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4458 case SHADER_OPCODE_TXS_LOGICAL
:
4459 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4462 case FS_OPCODE_TXB_LOGICAL
:
4463 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4466 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4467 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4470 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4471 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4474 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4475 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4478 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4479 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4482 case SHADER_OPCODE_LOD_LOGICAL
:
4483 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4486 case SHADER_OPCODE_TG4_LOGICAL
:
4487 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4490 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4491 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4494 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4495 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
4498 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4499 lower_surface_logical_send(ibld
, inst
,
4500 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4504 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4505 lower_surface_logical_send(ibld
, inst
,
4506 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4507 ibld
.sample_mask_reg());
4510 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4511 lower_surface_logical_send(ibld
, inst
,
4512 SHADER_OPCODE_UNTYPED_ATOMIC
,
4513 ibld
.sample_mask_reg());
4516 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4517 lower_surface_logical_send(ibld
, inst
,
4518 SHADER_OPCODE_TYPED_SURFACE_READ
,
4522 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4523 lower_surface_logical_send(ibld
, inst
,
4524 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4525 ibld
.sample_mask_reg());
4528 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4529 lower_surface_logical_send(ibld
, inst
,
4530 SHADER_OPCODE_TYPED_ATOMIC
,
4531 ibld
.sample_mask_reg());
4534 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4535 lower_varying_pull_constant_logical_send(ibld
, inst
);
4538 case SHADER_OPCODE_RCP
:
4539 case SHADER_OPCODE_RSQ
:
4540 case SHADER_OPCODE_SQRT
:
4541 case SHADER_OPCODE_EXP2
:
4542 case SHADER_OPCODE_LOG2
:
4543 case SHADER_OPCODE_SIN
:
4544 case SHADER_OPCODE_COS
:
4545 case SHADER_OPCODE_POW
:
4546 case SHADER_OPCODE_INT_QUOTIENT
:
4547 case SHADER_OPCODE_INT_REMAINDER
:
4548 /* The math opcodes are overloaded for the send-like and
4549 * expression-like instructions which seems kind of icky. Gen6+ has
4550 * a native (but rather quirky) MATH instruction so we don't need to
4551 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
4552 * logical instructions (which we can easily recognize because they
4553 * have mlen = 0) into send-like virtual instructions.
4555 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
4556 lower_math_logical_send(ibld
, inst
);
4571 invalidate_live_intervals();
4577 * Get the closest allowed SIMD width for instruction \p inst accounting for
4578 * some common regioning and execution control restrictions that apply to FPU
4579 * instructions. These restrictions don't necessarily have any relevance to
4580 * instructions not executed by the FPU pipeline like extended math, control
4581 * flow or send message instructions.
4583 * For virtual opcodes it's really up to the instruction -- In some cases
4584 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
4585 * instructions) it may simplify virtual instruction lowering if we can
4586 * enforce FPU-like regioning restrictions already on the virtual instruction,
4587 * in other cases (e.g. virtual send-like instructions) this may be
4588 * excessively restrictive.
4591 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
4592 const fs_inst
*inst
)
4594 /* Maximum execution size representable in the instruction controls. */
4595 unsigned max_width
= MIN2(32, inst
->exec_size
);
4597 /* According to the PRMs:
4598 * "A. In Direct Addressing mode, a source cannot span more than 2
4599 * adjacent GRF registers.
4600 * B. A destination cannot span more than 2 adjacent GRF registers."
4602 * Look for the source or destination with the largest register region
4603 * which is the one that is going to limit the overall execution size of
4604 * the instruction due to this rule.
4606 unsigned reg_count
= inst
->regs_written
;
4608 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4609 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4611 /* Calculate the maximum execution size of the instruction based on the
4612 * factor by which it goes over the hardware limit of 2 GRFs.
4615 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
4617 /* According to the IVB PRMs:
4618 * "When destination spans two registers, the source MUST span two
4619 * registers. The exception to the above rule:
4621 * - When source is scalar, the source registers are not incremented.
4622 * - When source is packed integer Word and destination is packed
4623 * integer DWord, the source register is not incremented but the
4624 * source sub register is incremented."
4626 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
4627 * restrictions. The code below intentionally doesn't check whether the
4628 * destination type is integer because empirically the hardware doesn't
4629 * seem to care what the actual type is as long as it's dword-aligned.
4631 if (devinfo
->gen
< 8) {
4632 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
4633 if (inst
->regs_written
== 2 &&
4634 inst
->regs_read(i
) != 0 && inst
->regs_read(i
) != 2 &&
4635 !is_uniform(inst
->src
[i
]) &&
4636 !(type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
4637 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1))
4638 max_width
= MIN2(max_width
, inst
->exec_size
/
4639 inst
->regs_written
);
4643 /* From the IVB PRMs:
4644 * "When an instruction is SIMD32, the low 16 bits of the execution mask
4645 * are applied for both halves of the SIMD32 instruction. If different
4646 * execution mask channels are required, split the instruction into two
4647 * SIMD16 instructions."
4649 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
4650 * 32-wide control flow support in hardware and will behave similarly.
4652 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
4653 max_width
= MIN2(max_width
, 16);
4655 /* From the IVB PRMs (applies to HSW too):
4656 * "Instructions with condition modifiers must not use SIMD32."
4658 * From the BDW PRMs (applies to later hardware too):
4659 * "Ternary instruction with condition modifiers must not use SIMD32."
4661 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
4662 max_width
= MIN2(max_width
, 16);
4664 /* From the IVB PRMs (applies to other devices that don't have the
4665 * gen_device_info::supports_simd16_3src flag set):
4666 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
4667 * SIMD8 is not allowed for DF operations."
4669 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
4670 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4672 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
4673 * the 8-bit quarter of the execution mask signals specified in the
4674 * instruction control fields) for the second compressed half of any
4675 * single-precision instruction (for double-precision instructions
4676 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
4677 * the EU will apply the wrong execution controls for the second
4678 * sequential GRF write if the number of channels per GRF is not exactly
4679 * eight in single-precision mode (or four in double-float mode).
4681 * In this situation we calculate the maximum size of the split
4682 * instructions so they only ever write to a single register.
4684 if (devinfo
->gen
< 8 && inst
->regs_written
> 1 &&
4685 !inst
->force_writemask_all
) {
4686 const unsigned channels_per_grf
= inst
->exec_size
/ inst
->regs_written
;
4687 unsigned exec_type_size
= 0;
4688 for (int i
= 0; i
< inst
->sources
; i
++) {
4689 if (inst
->src
[i
].file
!= BAD_FILE
)
4690 exec_type_size
= MAX2(exec_type_size
, type_sz(inst
->src
[i
].type
));
4692 assert(exec_type_size
);
4694 /* The hardware shifts exactly 8 channels per compressed half of the
4695 * instruction in single-precision mode and exactly 4 in double-precision.
4697 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
4698 max_width
= MIN2(max_width
, channels_per_grf
);
4701 /* Only power-of-two execution sizes are representable in the instruction
4704 return 1 << _mesa_logbase2(max_width
);
4708 * Get the maximum allowed SIMD width for instruction \p inst accounting for
4709 * various payload size restrictions that apply to sampler message
4712 * This is only intended to provide a maximum theoretical bound for the
4713 * execution size of the message based on the number of argument components
4714 * alone, which in most cases will determine whether the SIMD8 or SIMD16
4715 * variant of the message can be used, though some messages may have
4716 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
4717 * the message length to determine the exact SIMD width and argument count,
4718 * which makes a number of sampler message combinations impossible to
4722 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
4723 const fs_inst
*inst
)
4725 /* Calculate the number of coordinate components that have to be present
4726 * assuming that additional arguments follow the texel coordinates in the
4727 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
4728 * need to pad to four or three components depending on the message,
4729 * pre-ILK we need to pad to at most three components.
4731 const unsigned req_coord_components
=
4732 (devinfo
->gen
>= 7 ||
4733 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
4734 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
4735 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
4738 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
4739 * variant of the TXL or TXF message.
4741 const bool implicit_lod
= devinfo
->gen
>= 9 &&
4742 (inst
->opcode
== SHADER_OPCODE_TXL
||
4743 inst
->opcode
== SHADER_OPCODE_TXF
) &&
4744 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
4746 /* Calculate the total number of argument components that need to be passed
4747 * to the sampler unit.
4749 const unsigned num_payload_components
=
4750 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
4751 req_coord_components
) +
4752 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
4753 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
4754 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
4755 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
4756 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
4757 inst
->components_read(TEX_LOGICAL_SRC_OFFSET_VALUE
) : 0) +
4758 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
4760 /* SIMD16 messages with more than five arguments exceed the maximum message
4761 * size supported by the sampler, regardless of whether a header is
4764 return MIN2(inst
->exec_size
,
4765 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
4769 * Get the closest native SIMD width supported by the hardware for instruction
4770 * \p inst. The instruction will be left untouched by
4771 * fs_visitor::lower_simd_width() if the returned value is equal to the
4772 * original execution size.
4775 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
4776 const fs_inst
*inst
)
4778 switch (inst
->opcode
) {
4779 case BRW_OPCODE_MOV
:
4780 case BRW_OPCODE_SEL
:
4781 case BRW_OPCODE_NOT
:
4782 case BRW_OPCODE_AND
:
4784 case BRW_OPCODE_XOR
:
4785 case BRW_OPCODE_SHR
:
4786 case BRW_OPCODE_SHL
:
4787 case BRW_OPCODE_ASR
:
4788 case BRW_OPCODE_CMPN
:
4789 case BRW_OPCODE_CSEL
:
4790 case BRW_OPCODE_F32TO16
:
4791 case BRW_OPCODE_F16TO32
:
4792 case BRW_OPCODE_BFREV
:
4793 case BRW_OPCODE_BFE
:
4794 case BRW_OPCODE_ADD
:
4795 case BRW_OPCODE_MUL
:
4796 case BRW_OPCODE_AVG
:
4797 case BRW_OPCODE_FRC
:
4798 case BRW_OPCODE_RNDU
:
4799 case BRW_OPCODE_RNDD
:
4800 case BRW_OPCODE_RNDE
:
4801 case BRW_OPCODE_RNDZ
:
4802 case BRW_OPCODE_LZD
:
4803 case BRW_OPCODE_FBH
:
4804 case BRW_OPCODE_FBL
:
4805 case BRW_OPCODE_CBIT
:
4806 case BRW_OPCODE_SAD2
:
4807 case BRW_OPCODE_MAD
:
4808 case BRW_OPCODE_LRP
:
4809 case FS_OPCODE_PACK
:
4810 return get_fpu_lowered_simd_width(devinfo
, inst
);
4812 case BRW_OPCODE_CMP
: {
4813 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
4814 * when the destination is a GRF the dependency-clear bit on the flag
4815 * register is cleared early.
4817 * Suggested workarounds are to disable coissuing CMP instructions
4818 * or to split CMP(16) instructions into two CMP(8) instructions.
4820 * We choose to split into CMP(8) instructions since disabling
4821 * coissuing would affect CMP instructions not otherwise affected by
4824 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4825 !inst
->dst
.is_null() ? 8 : ~0);
4826 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
4828 case BRW_OPCODE_BFI1
:
4829 case BRW_OPCODE_BFI2
:
4830 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
4832 * "Force BFI instructions to be executed always in SIMD8."
4834 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
4835 get_fpu_lowered_simd_width(devinfo
, inst
));
4838 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
4839 return inst
->exec_size
;
4841 case SHADER_OPCODE_RCP
:
4842 case SHADER_OPCODE_RSQ
:
4843 case SHADER_OPCODE_SQRT
:
4844 case SHADER_OPCODE_EXP2
:
4845 case SHADER_OPCODE_LOG2
:
4846 case SHADER_OPCODE_SIN
:
4847 case SHADER_OPCODE_COS
:
4848 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
4851 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4852 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
4853 MIN2(8, inst
->exec_size
));
4855 case SHADER_OPCODE_POW
:
4856 /* SIMD16 is only allowed on Gen7+. */
4857 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4858 MIN2(8, inst
->exec_size
));
4860 case SHADER_OPCODE_INT_QUOTIENT
:
4861 case SHADER_OPCODE_INT_REMAINDER
:
4862 /* Integer division is limited to SIMD8 on all generations. */
4863 return MIN2(8, inst
->exec_size
);
4865 case FS_OPCODE_LINTERP
:
4866 case FS_OPCODE_GET_BUFFER_SIZE
:
4867 case FS_OPCODE_DDX_COARSE
:
4868 case FS_OPCODE_DDX_FINE
:
4869 case FS_OPCODE_DDY_COARSE
:
4870 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
4871 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
4872 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
4873 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
4874 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
4875 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
4876 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
4877 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
4878 return MIN2(16, inst
->exec_size
);
4880 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4881 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
4882 * message used to implement varying pull constant loads, so expand it
4883 * to SIMD16. An alternative with longer message payload length but
4884 * shorter return payload would be to use the SIMD8 sampler message that
4885 * takes (header, u, v, r) as parameters instead of (header, u).
4887 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
4889 case FS_OPCODE_DDY_FINE
:
4890 /* The implementation of this virtual opcode may require emitting
4891 * compressed Align16 instructions, which are severely limited on some
4894 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
4895 * Region Restrictions):
4897 * "In Align16 access mode, SIMD16 is not allowed for DW operations
4898 * and SIMD8 is not allowed for DF operations."
4900 * In this context, "DW operations" means "operations acting on 32-bit
4901 * values", so it includes operations on floats.
4903 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
4904 * (Instruction Compression -> Rules and Restrictions):
4906 * "A compressed instruction must be in Align1 access mode. Align16
4907 * mode instructions cannot be compressed."
4909 * Similar text exists in the g45 PRM.
4911 * Empirically, compressed align16 instructions using odd register
4912 * numbers don't appear to work on Sandybridge either.
4914 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
4915 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
4916 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
4918 case SHADER_OPCODE_MULH
:
4919 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4920 * is 8-wide on Gen7+.
4922 return (devinfo
->gen
>= 7 ? 8 :
4923 get_fpu_lowered_simd_width(devinfo
, inst
));
4925 case FS_OPCODE_FB_WRITE_LOGICAL
:
4926 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4929 assert(devinfo
->gen
!= 6 ||
4930 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4931 inst
->exec_size
== 8);
4932 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4933 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4934 8 : MIN2(16, inst
->exec_size
));
4936 case FS_OPCODE_FB_READ_LOGICAL
:
4937 return MIN2(16, inst
->exec_size
);
4939 case SHADER_OPCODE_TEX_LOGICAL
:
4940 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4941 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4942 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4943 case SHADER_OPCODE_LOD_LOGICAL
:
4944 case SHADER_OPCODE_TG4_LOGICAL
:
4945 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4946 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4947 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4948 return get_sampler_lowered_simd_width(devinfo
, inst
);
4950 case SHADER_OPCODE_TXD_LOGICAL
:
4951 /* TXD is unsupported in SIMD16 mode. */
4954 case SHADER_OPCODE_TXL_LOGICAL
:
4955 case FS_OPCODE_TXB_LOGICAL
:
4956 /* Only one execution size is representable pre-ILK depending on whether
4957 * the shadow reference argument is present.
4959 if (devinfo
->gen
== 4)
4960 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
4962 return get_sampler_lowered_simd_width(devinfo
, inst
);
4964 case SHADER_OPCODE_TXF_LOGICAL
:
4965 case SHADER_OPCODE_TXS_LOGICAL
:
4966 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4967 * messages. Use SIMD16 instead.
4969 if (devinfo
->gen
== 4)
4972 return get_sampler_lowered_simd_width(devinfo
, inst
);
4974 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4975 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4976 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4979 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4980 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4981 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4982 return MIN2(16, inst
->exec_size
);
4984 case SHADER_OPCODE_URB_READ_SIMD8
:
4985 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
4986 case SHADER_OPCODE_URB_WRITE_SIMD8
:
4987 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
4988 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
4989 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
4990 return MIN2(8, inst
->exec_size
);
4992 case SHADER_OPCODE_MOV_INDIRECT
:
4993 /* Prior to Broadwell, we only have 8 address subregisters */
4994 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
4995 2 * REG_SIZE
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
4998 case SHADER_OPCODE_LOAD_PAYLOAD
: {
4999 const unsigned reg_count
=
5000 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
5002 if (reg_count
> 2) {
5003 /* Only LOAD_PAYLOAD instructions with per-channel destination region
5004 * can be easily lowered (which excludes headers and heterogeneous
5007 assert(!inst
->header_size
);
5008 for (unsigned i
= 0; i
< inst
->sources
; i
++)
5009 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
5010 inst
->src
[i
].file
== BAD_FILE
);
5012 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
5014 return inst
->exec_size
;
5018 return inst
->exec_size
;
5023 * Return true if splitting out the group of channels of instruction \p inst
5024 * given by lbld.group() requires allocating a temporary for the i-th source
5025 * of the lowered instruction.
5028 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
5030 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
5031 (inst
->components_read(i
) == 1 &&
5032 lbld
.dispatch_width() <= inst
->exec_size
));
5036 * Extract the data that would be consumed by the channel group given by
5037 * lbld.group() from the i-th source region of instruction \p inst and return
5038 * it as result in packed form. If any copy instructions are required they
5039 * will be emitted before the given \p inst in \p block.
5042 emit_unzip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
,
5045 /* Specified channel group from the source region. */
5046 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group());
5048 if (needs_src_copy(lbld
, inst
, i
)) {
5049 /* Builder of the right width to perform the copy avoiding uninitialized
5050 * data if the lowered execution size is greater than the original
5051 * execution size of the instruction.
5053 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5054 inst
->exec_size
), 0);
5055 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
5057 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
5058 cbld
.at(block
, inst
)
5059 .MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
5063 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
5064 /* The source is invariant for all dispatch_width-wide groups of the
5067 return inst
->src
[i
];
5070 /* We can just point the lowered instruction at the right channel group
5071 * from the original region.
5078 * Return true if splitting out the group of channels of instruction \p inst
5079 * given by lbld.group() requires allocating a temporary for the destination
5080 * of the lowered instruction and copying the data back to the original
5081 * destination region.
5084 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
5086 /* If the instruction writes more than one component we'll have to shuffle
5087 * the results of multiple lowered instructions in order to make sure that
5088 * they end up arranged correctly in the original destination region.
5090 if (inst
->regs_written
* REG_SIZE
>
5091 inst
->dst
.component_size(inst
->exec_size
))
5094 /* If the lowered execution size is larger than the original the result of
5095 * the instruction won't fit in the original destination, so we'll have to
5096 * allocate a temporary in any case.
5098 if (lbld
.dispatch_width() > inst
->exec_size
)
5101 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5102 /* If we already made a copy of the source for other reasons there won't
5103 * be any overlap with the destination.
5105 if (needs_src_copy(lbld
, inst
, i
))
5108 /* In order to keep the logic simple we emit a copy whenever the
5109 * destination region doesn't exactly match an overlapping source, which
5110 * may point at the source and destination not being aligned group by
5111 * group which could cause one of the lowered instructions to overwrite
5112 * the data read from the same source by other lowered instructions.
5114 if (regions_overlap(inst
->dst
, inst
->regs_written
* REG_SIZE
,
5115 inst
->src
[i
], inst
->regs_read(i
) * REG_SIZE
) &&
5116 !inst
->dst
.equals(inst
->src
[i
]))
5124 * Insert data from a packed temporary into the channel group given by
5125 * lbld.group() of the destination region of instruction \p inst and return
5126 * the temporary as result. If any copy instructions are required they will
5127 * be emitted around the given \p inst in \p block.
5130 emit_zip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
)
5132 /* Builder of the right width to perform the copy avoiding uninitialized
5133 * data if the lowered execution size is greater than the original
5134 * execution size of the instruction.
5136 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5137 inst
->exec_size
), 0);
5139 /* Specified channel group from the destination region. */
5140 const fs_reg dst
= horiz_offset(inst
->dst
, lbld
.group());
5141 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
5142 inst
->dst
.component_size(inst
->exec_size
);
5144 if (needs_dst_copy(lbld
, inst
)) {
5145 const fs_reg tmp
= lbld
.vgrf(inst
->dst
.type
, dst_size
);
5147 if (inst
->predicate
) {
5148 /* Handle predication by copying the original contents of
5149 * the destination into the temporary before emitting the
5150 * lowered instruction.
5152 for (unsigned k
= 0; k
< dst_size
; ++k
)
5153 cbld
.at(block
, inst
)
5154 .MOV(offset(tmp
, lbld
, k
), offset(dst
, inst
->exec_size
, k
));
5157 for (unsigned k
= 0; k
< dst_size
; ++k
)
5158 cbld
.at(block
, inst
->next
)
5159 .MOV(offset(dst
, inst
->exec_size
, k
), offset(tmp
, lbld
, k
));
5164 /* No need to allocate a temporary for the lowered instruction, just
5165 * take the right group of channels from the original region.
5172 fs_visitor::lower_simd_width()
5174 bool progress
= false;
5176 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5177 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5179 if (lower_width
!= inst
->exec_size
) {
5180 /* Builder matching the original instruction. We may also need to
5181 * emit an instruction of width larger than the original, set the
5182 * execution size of the builder to the highest of both for now so
5183 * we're sure that both cases can be handled.
5185 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5186 const fs_builder ibld
= bld
.at(block
, inst
)
5187 .exec_all(inst
->force_writemask_all
)
5188 .group(max_width
, inst
->group
/ max_width
);
5190 /* Split the copies in chunks of the execution width of either the
5191 * original or the lowered instruction, whichever is lower.
5193 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5194 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
5195 inst
->dst
.component_size(inst
->exec_size
);
5197 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5199 for (unsigned i
= 0; i
< n
; i
++) {
5200 /* Emit a copy of the original instruction with the lowered width.
5201 * If the EOT flag was set throw it away except for the last
5202 * instruction to avoid killing the thread prematurely.
5204 fs_inst split_inst
= *inst
;
5205 split_inst
.exec_size
= lower_width
;
5206 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
5208 /* Select the correct channel enables for the i-th group, then
5209 * transform the sources and destination and emit the lowered
5212 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5214 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5215 split_inst
.src
[j
] = emit_unzip(lbld
, block
, inst
, j
);
5217 split_inst
.dst
= emit_zip(lbld
, block
, inst
);
5218 split_inst
.regs_written
= DIV_ROUND_UP(
5219 split_inst
.dst
.component_size(lower_width
) * dst_size
,
5222 lbld
.emit(split_inst
);
5225 inst
->remove(block
);
5231 invalidate_live_intervals();
5237 fs_visitor::dump_instructions()
5239 dump_instructions(NULL
);
5243 fs_visitor::dump_instructions(const char *name
)
5245 FILE *file
= stderr
;
5246 if (name
&& geteuid() != 0) {
5247 file
= fopen(name
, "w");
5253 calculate_register_pressure();
5254 int ip
= 0, max_pressure
= 0;
5255 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5256 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5257 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5258 dump_instruction(inst
, file
);
5261 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5264 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5265 fprintf(file
, "%4d: ", ip
++);
5266 dump_instruction(inst
, file
);
5270 if (file
!= stderr
) {
5276 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5278 dump_instruction(be_inst
, stderr
);
5282 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5284 fs_inst
*inst
= (fs_inst
*)be_inst
;
5286 if (inst
->predicate
) {
5287 fprintf(file
, "(%cf0.%d) ",
5288 inst
->predicate_inverse
? '-' : '+',
5292 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5294 fprintf(file
, ".sat");
5295 if (inst
->conditional_mod
) {
5296 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5297 if (!inst
->predicate
&&
5298 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5299 inst
->opcode
!= BRW_OPCODE_IF
&&
5300 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5301 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
5304 fprintf(file
, "(%d) ", inst
->exec_size
);
5307 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5311 fprintf(file
, "(EOT) ");
5314 switch (inst
->dst
.file
) {
5316 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
5317 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
5318 inst
->dst
.offset
% REG_SIZE
)
5319 fprintf(file
, "+%d.%d",
5320 inst
->dst
.offset
/ REG_SIZE
, inst
->dst
.offset
% REG_SIZE
);
5323 fprintf(file
, "g%d", inst
->dst
.nr
);
5326 fprintf(file
, "m%d", inst
->dst
.nr
);
5329 fprintf(file
, "(null)");
5332 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.offset
/ 4);
5335 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.offset
/ REG_SIZE
);
5338 switch (inst
->dst
.nr
) {
5340 fprintf(file
, "null");
5342 case BRW_ARF_ADDRESS
:
5343 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
5345 case BRW_ARF_ACCUMULATOR
:
5346 fprintf(file
, "acc%d", inst
->dst
.subnr
);
5349 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5352 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5355 if (inst
->dst
.subnr
)
5356 fprintf(file
, "+%d", inst
->dst
.subnr
);
5359 unreachable("not reached");
5361 if (inst
->dst
.stride
!= 1)
5362 fprintf(file
, "<%u>", inst
->dst
.stride
);
5363 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
5365 for (int i
= 0; i
< inst
->sources
; i
++) {
5366 if (inst
->src
[i
].negate
)
5368 if (inst
->src
[i
].abs
)
5370 switch (inst
->src
[i
].file
) {
5372 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
5373 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
5374 inst
->src
[i
].offset
% REG_SIZE
!= 0)
5375 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ REG_SIZE
,
5376 inst
->src
[i
].offset
% REG_SIZE
);
5379 fprintf(file
, "g%d", inst
->src
[i
].nr
);
5382 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
5385 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].offset
/ REG_SIZE
);
5388 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4);
5389 if (inst
->src
[i
].offset
% 4 != 0) {
5390 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ 4,
5391 inst
->src
[i
].offset
% 4);
5395 fprintf(file
, "(null)");
5398 switch (inst
->src
[i
].type
) {
5399 case BRW_REGISTER_TYPE_F
:
5400 fprintf(file
, "%-gf", inst
->src
[i
].f
);
5402 case BRW_REGISTER_TYPE_DF
:
5403 fprintf(file
, "%fdf", inst
->src
[i
].df
);
5405 case BRW_REGISTER_TYPE_W
:
5406 case BRW_REGISTER_TYPE_D
:
5407 fprintf(file
, "%dd", inst
->src
[i
].d
);
5409 case BRW_REGISTER_TYPE_UW
:
5410 case BRW_REGISTER_TYPE_UD
:
5411 fprintf(file
, "%uu", inst
->src
[i
].ud
);
5413 case BRW_REGISTER_TYPE_VF
:
5414 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
5415 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
5416 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
5417 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
5418 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5421 fprintf(file
, "???");
5426 switch (inst
->src
[i
].nr
) {
5428 fprintf(file
, "null");
5430 case BRW_ARF_ADDRESS
:
5431 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5433 case BRW_ARF_ACCUMULATOR
:
5434 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5437 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5440 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5443 if (inst
->src
[i
].subnr
)
5444 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
5447 if (inst
->src
[i
].abs
)
5450 if (inst
->src
[i
].file
!= IMM
) {
5452 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5453 unsigned hstride
= inst
->src
[i
].hstride
;
5454 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5456 stride
= inst
->src
[i
].stride
;
5459 fprintf(file
, "<%u>", stride
);
5461 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
5464 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5465 fprintf(file
, ", ");
5470 if (inst
->force_writemask_all
)
5471 fprintf(file
, "NoMask ");
5473 if (inst
->exec_size
!= dispatch_width
)
5474 fprintf(file
, "group%d ", inst
->group
);
5476 fprintf(file
, "\n");
5480 * Possibly returns an instruction that set up @param reg.
5482 * Sometimes we want to take the result of some expression/variable
5483 * dereference tree and rewrite the instruction generating the result
5484 * of the tree. When processing the tree, we know that the
5485 * instructions generated are all writing temporaries that are dead
5486 * outside of this tree. So, if we have some instructions that write
5487 * a temporary, we're free to point that temp write somewhere else.
5489 * Note that this doesn't guarantee that the instruction generated
5490 * only reg -- it might be the size=4 destination of a texture instruction.
5493 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5498 end
->is_partial_write() ||
5499 !reg
.equals(end
->dst
)) {
5507 fs_visitor::setup_fs_payload_gen6()
5509 assert(stage
== MESA_SHADER_FRAGMENT
);
5510 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5512 unsigned barycentric_interp_modes
=
5513 (stage
== MESA_SHADER_FRAGMENT
) ?
5514 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
5516 assert(devinfo
->gen
>= 6);
5518 /* R0-1: masks, pixel X/Y coordinates. */
5519 payload
.num_regs
= 2;
5520 /* R2: only for 32-pixel dispatch.*/
5522 /* R3-26: barycentric interpolation coordinates. These appear in the
5523 * same order that they appear in the brw_barycentric_mode
5524 * enum. Each set of coordinates occupies 2 registers if dispatch width
5525 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5526 * appear if they were enabled using the "Barycentric Interpolation
5527 * Mode" bits in WM_STATE.
5529 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
5530 if (barycentric_interp_modes
& (1 << i
)) {
5531 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5532 payload
.num_regs
+= 2;
5533 if (dispatch_width
== 16) {
5534 payload
.num_regs
+= 2;
5539 /* R27: interpolated depth if uses source depth */
5540 prog_data
->uses_src_depth
=
5541 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5542 if (prog_data
->uses_src_depth
) {
5543 payload
.source_depth_reg
= payload
.num_regs
;
5545 if (dispatch_width
== 16) {
5546 /* R28: interpolated depth if not SIMD8. */
5551 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5552 prog_data
->uses_src_w
=
5553 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5554 if (prog_data
->uses_src_w
) {
5555 payload
.source_w_reg
= payload
.num_regs
;
5557 if (dispatch_width
== 16) {
5558 /* R30: interpolated W if not SIMD8. */
5563 /* R31: MSAA position offsets. */
5564 if (prog_data
->persample_dispatch
&&
5565 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
)) {
5566 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
5568 * "MSDISPMODE_PERSAMPLE is required in order to select
5571 * So we can only really get sample positions if we are doing real
5572 * per-sample dispatch. If we need gl_SamplePosition and we don't have
5573 * persample dispatch, we hard-code it to 0.5.
5575 prog_data
->uses_pos_offset
= true;
5576 payload
.sample_pos_reg
= payload
.num_regs
;
5580 /* R32: MSAA input coverage mask */
5581 prog_data
->uses_sample_mask
=
5582 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5583 if (prog_data
->uses_sample_mask
) {
5584 assert(devinfo
->gen
>= 7);
5585 payload
.sample_mask_in_reg
= payload
.num_regs
;
5587 if (dispatch_width
== 16) {
5588 /* R33: input coverage mask if not SIMD8. */
5593 /* R34-: bary for 32-pixel. */
5594 /* R58-59: interp W for 32-pixel. */
5596 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5597 source_depth_to_render_target
= true;
5602 fs_visitor::setup_vs_payload()
5604 /* R0: thread header, R1: urb handles */
5605 payload
.num_regs
= 2;
5609 fs_visitor::setup_gs_payload()
5611 assert(stage
== MESA_SHADER_GEOMETRY
);
5613 struct brw_gs_prog_data
*gs_prog_data
=
5614 (struct brw_gs_prog_data
*) prog_data
;
5615 struct brw_vue_prog_data
*vue_prog_data
=
5616 (struct brw_vue_prog_data
*) prog_data
;
5618 /* R0: thread header, R1: output URB handles */
5619 payload
.num_regs
= 2;
5621 if (gs_prog_data
->include_primitive_id
) {
5622 /* R2: Primitive ID 0..7 */
5626 /* Use a maximum of 24 registers for push-model inputs. */
5627 const unsigned max_push_components
= 24;
5629 /* If pushing our inputs would take too many registers, reduce the URB read
5630 * length (which is in HWords, or 8 registers), and resort to pulling.
5632 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5633 * have to multiply by VerticesIn to obtain the total storage requirement.
5635 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5636 max_push_components
|| gs_prog_data
->invocations
> 1) {
5637 gs_prog_data
->base
.include_vue_handles
= true;
5639 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5640 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5642 vue_prog_data
->urb_read_length
=
5643 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5648 fs_visitor::setup_cs_payload()
5650 assert(devinfo
->gen
>= 7);
5651 payload
.num_regs
= 1;
5655 fs_visitor::calculate_register_pressure()
5657 invalidate_live_intervals();
5658 calculate_live_intervals();
5660 unsigned num_instructions
= 0;
5661 foreach_block(block
, cfg
)
5662 num_instructions
+= block
->instructions
.length();
5664 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5666 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5667 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5668 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5673 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
5675 * The needs_unlit_centroid_workaround ends up producing one of these per
5676 * channel of centroid input, so it's good to clean them up.
5678 * An assumption here is that nothing ever modifies the dispatched pixels
5679 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
5680 * dictates that anyway.
5683 fs_visitor::opt_drop_redundant_mov_to_flags()
5685 bool flag_mov_found
[2] = {false};
5686 bool progress
= false;
5688 /* Instructions removed by this pass can only be added if this were true */
5689 if (!devinfo
->needs_unlit_centroid_workaround
)
5692 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5693 if (inst
->is_control_flow()) {
5694 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
5695 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
5696 if (!flag_mov_found
[inst
->flag_subreg
]) {
5697 flag_mov_found
[inst
->flag_subreg
] = true;
5699 inst
->remove(block
);
5702 } else if (inst
->flags_written()) {
5703 flag_mov_found
[inst
->flag_subreg
] = false;
5711 fs_visitor::optimize()
5713 /* Start by validating the shader we currently have. */
5716 /* bld is the common builder object pointing at the end of the program we
5717 * used to translate it into i965 IR. For the optimization and lowering
5718 * passes coming next, any code added after the end of the program without
5719 * having explicitly called fs_builder::at() clearly points at a mistake.
5720 * Ideally optimization passes wouldn't be part of the visitor so they
5721 * wouldn't have access to bld at all, but they do, so just in case some
5722 * pass forgets to ask for a location explicitly set it to NULL here to
5723 * make it trip. The dispatch width is initialized to a bogus value to
5724 * make sure that optimizations set the execution controls explicitly to
5725 * match the code they are manipulating instead of relying on the defaults.
5727 bld
= fs_builder(this, 64);
5729 assign_constant_locations();
5730 lower_constant_loads();
5734 split_virtual_grfs();
5737 #define OPT(pass, args...) ({ \
5739 bool this_progress = pass(args); \
5741 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5742 char filename[64]; \
5743 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5744 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5746 backend_shader::dump_instructions(filename); \
5751 progress = progress || this_progress; \
5755 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5757 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5758 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5760 backend_shader::dump_instructions(filename
);
5763 bool progress
= false;
5767 OPT(opt_drop_redundant_mov_to_flags
);
5774 OPT(remove_duplicate_mrf_writes
);
5778 OPT(opt_copy_propagate
);
5779 OPT(opt_predicated_break
, this);
5780 OPT(opt_cmod_propagation
);
5781 OPT(dead_code_eliminate
);
5782 OPT(opt_peephole_sel
);
5783 OPT(dead_control_flow_eliminate
, this);
5784 OPT(opt_register_renaming
);
5785 OPT(opt_saturate_propagation
);
5786 OPT(register_coalesce
);
5787 OPT(compute_to_mrf
);
5788 OPT(eliminate_find_live_channel
);
5790 OPT(compact_virtual_grfs
);
5796 if (OPT(lower_pack
)) {
5797 OPT(register_coalesce
);
5798 OPT(dead_code_eliminate
);
5801 if (OPT(lower_d2x
)) {
5802 OPT(opt_copy_propagate
);
5803 OPT(dead_code_eliminate
);
5806 OPT(lower_simd_width
);
5808 /* After SIMD lowering just in case we had to unroll the EOT send. */
5809 OPT(opt_sampler_eot
);
5811 OPT(lower_logical_sends
);
5814 OPT(opt_copy_propagate
);
5815 /* Only run after logical send lowering because it's easier to implement
5816 * in terms of physical sends.
5818 if (OPT(opt_zero_samples
))
5819 OPT(opt_copy_propagate
);
5820 /* Run after logical send lowering to give it a chance to CSE the
5821 * LOAD_PAYLOAD instructions created to construct the payloads of
5822 * e.g. texturing messages in cases where it wasn't possible to CSE the
5823 * whole logical instruction.
5826 OPT(register_coalesce
);
5827 OPT(compute_to_mrf
);
5828 OPT(dead_code_eliminate
);
5829 OPT(remove_duplicate_mrf_writes
);
5830 OPT(opt_peephole_sel
);
5833 OPT(opt_redundant_discard_jumps
);
5835 if (OPT(lower_load_payload
)) {
5836 split_virtual_grfs();
5837 OPT(register_coalesce
);
5838 OPT(compute_to_mrf
);
5839 OPT(dead_code_eliminate
);
5842 OPT(opt_combine_constants
);
5843 OPT(lower_integer_multiplication
);
5845 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5846 OPT(opt_cmod_propagation
);
5848 OPT(opt_copy_propagate
);
5849 OPT(dead_code_eliminate
);
5852 lower_uniform_pull_constant_loads();
5858 * Three source instruction must have a GRF/MRF destination register.
5859 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5862 fs_visitor::fixup_3src_null_dest()
5864 bool progress
= false;
5866 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5867 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
5868 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5875 invalidate_live_intervals();
5879 fs_visitor::allocate_registers(bool allow_spilling
)
5881 bool allocated_without_spills
;
5883 static const enum instruction_scheduler_mode pre_modes
[] = {
5885 SCHEDULE_PRE_NON_LIFO
,
5889 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
5891 /* Try each scheduling heuristic to see if it can successfully register
5892 * allocate without spilling. They should be ordered by decreasing
5893 * performance but increasing likelihood of allocating.
5895 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5896 schedule_instructions(pre_modes
[i
]);
5899 assign_regs_trivial();
5900 allocated_without_spills
= true;
5902 allocated_without_spills
= assign_regs(false, spill_all
);
5904 if (allocated_without_spills
)
5908 if (!allocated_without_spills
) {
5909 if (!allow_spilling
)
5910 fail("Failure to register allocate and spilling is not allowed.");
5912 /* We assume that any spilling is worse than just dropping back to
5913 * SIMD8. There's probably actually some intermediate point where
5914 * SIMD16 with a couple of spills is still better.
5916 if (dispatch_width
> min_dispatch_width
) {
5917 fail("Failure to register allocate. Reduce number of "
5918 "live scalar values to avoid this.");
5920 compiler
->shader_perf_log(log_data
,
5921 "%s shader triggered register spilling. "
5922 "Try reducing the number of live scalar "
5923 "values to improve performance.\n",
5927 /* Since we're out of heuristics, just go spill registers until we
5928 * get an allocation.
5930 while (!assign_regs(true, spill_all
)) {
5936 /* This must come after all optimization and register allocation, since
5937 * it inserts dead code that happens to have side effects, and it does
5938 * so based on the actual physical registers in use.
5940 insert_gen4_send_dependency_workarounds();
5945 schedule_instructions(SCHEDULE_POST
);
5947 if (last_scratch
> 0) {
5948 unsigned max_scratch_size
= 2 * 1024 * 1024;
5950 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5952 if (stage
== MESA_SHADER_COMPUTE
) {
5953 if (devinfo
->is_haswell
) {
5954 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5955 * field documentation, Haswell supports a minimum of 2kB of
5956 * scratch space for compute shaders, unlike every other stage
5959 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
5960 } else if (devinfo
->gen
<= 7) {
5961 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5962 * field documentation, platforms prior to Haswell measure scratch
5963 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
5965 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
5966 max_scratch_size
= 12 * 1024;
5970 /* We currently only support up to 2MB of scratch space. If we
5971 * need to support more eventually, the documentation suggests
5972 * that we could allocate a larger buffer, and partition it out
5973 * ourselves. We'd just have to undo the hardware's address
5974 * calculation by subtracting (FFTID * Per Thread Scratch Space)
5975 * and then add FFTID * (Larger Per Thread Scratch Space).
5977 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
5978 * Thread Group Tracking > Local Memory/Scratch Space.
5980 assert(prog_data
->total_scratch
< max_scratch_size
);
5985 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5987 assert(stage
== MESA_SHADER_VERTEX
);
5991 if (shader_time_index
>= 0)
5992 emit_shader_time_begin();
5999 compute_clip_distance(clip_planes
);
6003 if (shader_time_index
>= 0)
6004 emit_shader_time_end();
6010 assign_curb_setup();
6011 assign_vs_urb_setup();
6013 fixup_3src_null_dest();
6014 allocate_registers(true);
6020 fs_visitor::run_tcs_single_patch()
6022 assert(stage
== MESA_SHADER_TESS_CTRL
);
6024 struct brw_tcs_prog_data
*tcs_prog_data
=
6025 (struct brw_tcs_prog_data
*) prog_data
;
6027 /* r1-r4 contain the ICP handles. */
6028 payload
.num_regs
= 5;
6030 if (shader_time_index
>= 0)
6031 emit_shader_time_begin();
6033 /* Initialize gl_InvocationID */
6034 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
6035 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6036 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
6037 bld
.MOV(channels_ud
, channels_uw
);
6039 if (tcs_prog_data
->instances
== 1) {
6040 invocation_id
= channels_ud
;
6042 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6044 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
6045 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6046 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6047 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
6048 brw_imm_ud(INTEL_MASK(23, 17)));
6049 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
6051 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
6054 /* Fix the disptach mask */
6055 if (nir
->info
.tcs
.vertices_out
% 8) {
6056 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
6057 brw_imm_ud(nir
->info
.tcs
.vertices_out
), BRW_CONDITIONAL_L
);
6058 bld
.IF(BRW_PREDICATE_NORMAL
);
6063 if (nir
->info
.tcs
.vertices_out
% 8) {
6064 bld
.emit(BRW_OPCODE_ENDIF
);
6067 /* Emit EOT write; set TR DS Cache bit */
6069 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
6070 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
6071 fs_reg(brw_imm_ud(0)),
6073 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
6074 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
6076 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
6077 bld
.null_reg_ud(), payload
);
6081 if (shader_time_index
>= 0)
6082 emit_shader_time_end();
6091 assign_curb_setup();
6092 assign_tcs_single_patch_urb_setup();
6094 fixup_3src_null_dest();
6095 allocate_registers(true);
6101 fs_visitor::run_tes()
6103 assert(stage
== MESA_SHADER_TESS_EVAL
);
6105 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6106 payload
.num_regs
= 5;
6108 if (shader_time_index
>= 0)
6109 emit_shader_time_begin();
6118 if (shader_time_index
>= 0)
6119 emit_shader_time_end();
6125 assign_curb_setup();
6126 assign_tes_urb_setup();
6128 fixup_3src_null_dest();
6129 allocate_registers(true);
6135 fs_visitor::run_gs()
6137 assert(stage
== MESA_SHADER_GEOMETRY
);
6141 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6143 if (gs_compile
->control_data_header_size_bits
> 0) {
6144 /* Create a VGRF to store accumulated control data bits. */
6145 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6147 /* If we're outputting more than 32 control data bits, then EmitVertex()
6148 * will set control_data_bits to 0 after emitting the first vertex.
6149 * Otherwise, we need to initialize it to 0 here.
6151 if (gs_compile
->control_data_header_size_bits
<= 32) {
6152 const fs_builder abld
= bld
.annotate("initialize control data bits");
6153 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6157 if (shader_time_index
>= 0)
6158 emit_shader_time_begin();
6162 emit_gs_thread_end();
6164 if (shader_time_index
>= 0)
6165 emit_shader_time_end();
6174 assign_curb_setup();
6175 assign_gs_urb_setup();
6177 fixup_3src_null_dest();
6178 allocate_registers(true);
6184 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6186 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
6187 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6189 assert(stage
== MESA_SHADER_FRAGMENT
);
6191 if (devinfo
->gen
>= 6)
6192 setup_fs_payload_gen6();
6194 setup_fs_payload_gen4();
6198 } else if (do_rep_send
) {
6199 assert(dispatch_width
== 16);
6200 emit_repclear_shader();
6202 if (shader_time_index
>= 0)
6203 emit_shader_time_begin();
6205 calculate_urb_setup();
6206 if (nir
->info
.inputs_read
> 0 ||
6207 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
6208 if (devinfo
->gen
< 6)
6209 emit_interpolation_setup_gen4();
6211 emit_interpolation_setup_gen6();
6214 /* We handle discards by keeping track of the still-live pixels in f0.1.
6215 * Initialize it with the dispatched pixels.
6217 if (wm_prog_data
->uses_kill
) {
6218 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
6219 discard_init
->flag_subreg
= 1;
6222 /* Generate FS IR for main(). (the visitor only descends into
6223 * functions called "main").
6230 if (wm_prog_data
->uses_kill
)
6231 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6233 if (wm_key
->alpha_test_func
)
6238 if (shader_time_index
>= 0)
6239 emit_shader_time_end();
6245 assign_curb_setup();
6248 fixup_3src_null_dest();
6249 allocate_registers(allow_spilling
);
6259 fs_visitor::run_cs()
6261 assert(stage
== MESA_SHADER_COMPUTE
);
6265 if (shader_time_index
>= 0)
6266 emit_shader_time_begin();
6268 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6269 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6270 const fs_builder abld
= bld
.exec_all().group(1, 0);
6271 abld
.MOV(retype(suboffset(brw_sr0_reg(), 1), BRW_REGISTER_TYPE_UW
),
6272 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6280 emit_cs_terminate();
6282 if (shader_time_index
>= 0)
6283 emit_shader_time_end();
6289 assign_curb_setup();
6291 fixup_3src_null_dest();
6292 allocate_registers(true);
6301 * Return a bitfield where bit n is set if barycentric interpolation mode n
6302 * (see enum brw_barycentric_mode) is needed by the fragment shader.
6304 * We examine the load_barycentric intrinsics rather than looking at input
6305 * variables so that we catch interpolateAtCentroid() messages too, which
6306 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
6309 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
6310 const nir_shader
*shader
)
6312 unsigned barycentric_interp_modes
= 0;
6314 nir_foreach_function(f
, shader
) {
6318 nir_foreach_block(block
, f
->impl
) {
6319 nir_foreach_instr(instr
, block
) {
6320 if (instr
->type
!= nir_instr_type_intrinsic
)
6323 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6324 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6327 /* Ignore WPOS; it doesn't require interpolation. */
6328 if (nir_intrinsic_base(intrin
) == VARYING_SLOT_POS
)
6331 intrin
= nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6332 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
6333 nir_intrinsic_interp_mode(intrin
);
6334 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
6335 enum brw_barycentric_mode bary
=
6336 brw_barycentric_mode(interp
, bary_op
);
6338 barycentric_interp_modes
|= 1 << bary
;
6340 if (devinfo
->needs_unlit_centroid_workaround
&&
6341 bary_op
== nir_intrinsic_load_barycentric_centroid
)
6342 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
6347 return barycentric_interp_modes
;
6351 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
6352 const nir_shader
*shader
)
6354 prog_data
->flat_inputs
= 0;
6356 nir_foreach_variable(var
, &shader
->inputs
) {
6357 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
6359 if (input_index
< 0)
6363 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6364 prog_data
->flat_inputs
|= (1 << input_index
);
6369 computed_depth_mode(const nir_shader
*shader
)
6371 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6372 switch (shader
->info
.fs
.depth_layout
) {
6373 case FRAG_DEPTH_LAYOUT_NONE
:
6374 case FRAG_DEPTH_LAYOUT_ANY
:
6375 return BRW_PSCDEPTH_ON
;
6376 case FRAG_DEPTH_LAYOUT_GREATER
:
6377 return BRW_PSCDEPTH_ON_GE
;
6378 case FRAG_DEPTH_LAYOUT_LESS
:
6379 return BRW_PSCDEPTH_ON_LE
;
6380 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
6381 return BRW_PSCDEPTH_OFF
;
6384 return BRW_PSCDEPTH_OFF
;
6388 * Move load_interpolated_input with simple (payload-based) barycentric modes
6389 * to the top of the program so we don't emit multiple PLNs for the same input.
6391 * This works around CSE not being able to handle non-dominating cases
6397 * interpolate the same exact input
6400 * This should be replaced by global value numbering someday.
6403 move_interpolation_to_top(nir_shader
*nir
)
6405 nir_foreach_function(f
, nir
) {
6409 nir_block
*top
= nir_start_block(f
->impl
);
6410 exec_node
*cursor_node
= NULL
;
6412 nir_foreach_block(block
, f
->impl
) {
6416 nir_foreach_instr_safe(instr
, block
) {
6417 if (instr
->type
!= nir_instr_type_intrinsic
)
6420 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6421 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6423 nir_intrinsic_instr
*bary_intrinsic
=
6424 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6425 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
6427 /* Leave interpolateAtSample/Offset() where they are. */
6428 if (op
== nir_intrinsic_load_barycentric_at_sample
||
6429 op
== nir_intrinsic_load_barycentric_at_offset
)
6432 nir_instr
*move
[3] = {
6433 &bary_intrinsic
->instr
,
6434 intrin
->src
[1].ssa
->parent_instr
,
6438 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
6439 if (move
[i
]->block
!= top
) {
6440 move
[i
]->block
= top
;
6441 exec_node_remove(&move
[i
]->node
);
6443 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
6445 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
6447 cursor_node
= &move
[i
]->node
;
6452 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6453 ((unsigned) nir_metadata_block_index
|
6454 (unsigned) nir_metadata_dominance
));
6459 * Apply default interpolation settings to FS inputs which don't specify any.
6462 brw_nir_set_default_interpolation(const struct gen_device_info
*devinfo
,
6463 struct nir_shader
*nir
,
6464 bool api_flat_shade
,
6465 bool per_sample_interpolation
)
6467 assert(nir
->stage
== MESA_SHADER_FRAGMENT
);
6469 nir_foreach_variable(var
, &nir
->inputs
) {
6470 /* Apply default interpolation mode.
6472 * Everything defaults to smooth except for the legacy GL color
6473 * built-in variables, which might be flat depending on API state.
6475 if (var
->data
.interpolation
== INTERP_MODE_NONE
) {
6476 const bool flat
= api_flat_shade
&&
6477 (var
->data
.location
== VARYING_SLOT_COL0
||
6478 var
->data
.location
== VARYING_SLOT_COL1
);
6480 var
->data
.interpolation
= flat
? INTERP_MODE_FLAT
6481 : INTERP_MODE_SMOOTH
;
6484 /* Apply 'sample' if necessary for API state. */
6485 if (per_sample_interpolation
&&
6486 var
->data
.interpolation
!= INTERP_MODE_FLAT
) {
6487 var
->data
.centroid
= false;
6488 var
->data
.sample
= true;
6491 /* On Ironlake and below, there is only one interpolation mode.
6492 * Centroid interpolation doesn't mean anything on this hardware --
6493 * there is no multisampling.
6495 if (devinfo
->gen
< 6) {
6496 var
->data
.centroid
= false;
6497 var
->data
.sample
= false;
6503 * Demote per-sample barycentric intrinsics to centroid.
6505 * Useful when rendering to a non-multisampled buffer.
6508 demote_sample_qualifiers(nir_shader
*nir
)
6510 nir_foreach_function(f
, nir
) {
6515 nir_builder_init(&b
, f
->impl
);
6517 nir_foreach_block(block
, f
->impl
) {
6518 nir_foreach_instr_safe(instr
, block
) {
6519 if (instr
->type
!= nir_instr_type_intrinsic
)
6522 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6523 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
6524 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
6527 b
.cursor
= nir_before_instr(instr
);
6528 nir_ssa_def
*centroid
=
6529 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
6530 nir_intrinsic_interp_mode(intrin
));
6531 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
6532 nir_src_for_ssa(centroid
));
6533 nir_instr_remove(instr
);
6537 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6538 ((unsigned) nir_metadata_block_index
|
6539 (unsigned) nir_metadata_dominance
));
6544 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
6546 const struct brw_wm_prog_key
*key
,
6547 struct brw_wm_prog_data
*prog_data
,
6548 const nir_shader
*src_shader
,
6549 struct gl_program
*prog
,
6550 int shader_time_index8
, int shader_time_index16
,
6551 bool allow_spilling
,
6553 unsigned *final_assembly_size
,
6556 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6557 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6559 brw_nir_set_default_interpolation(compiler
->devinfo
, shader
,
6560 key
->flat_shade
, key
->persample_interp
);
6561 brw_nir_lower_fs_inputs(shader
);
6562 brw_nir_lower_fs_outputs(shader
);
6563 if (!key
->multisample_fbo
)
6564 NIR_PASS_V(shader
, demote_sample_qualifiers
);
6565 NIR_PASS_V(shader
, move_interpolation_to_top
);
6566 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6568 /* key->alpha_test_func means simulating alpha testing via discards,
6569 * so the shader definitely kills pixels.
6571 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
6572 prog_data
->uses_omask
= key
->multisample_fbo
&&
6573 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
6574 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
6575 prog_data
->computed_stencil
=
6576 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
6578 prog_data
->persample_dispatch
=
6579 key
->multisample_fbo
&&
6580 (key
->persample_interp
||
6581 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
6582 SYSTEM_BIT_SAMPLE_POS
)) ||
6583 shader
->info
.fs
.uses_sample_qualifier
||
6584 shader
->info
.outputs_read
);
6586 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
6588 prog_data
->barycentric_interp_modes
=
6589 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
6591 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
;
6592 uint8_t simd8_grf_start
= 0, simd16_grf_start
= 0;
6593 unsigned simd8_grf_used
= 0, simd16_grf_used
= 0;
6595 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
6596 &prog_data
->base
, prog
, shader
, 8,
6597 shader_time_index8
);
6598 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
6600 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
6603 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
6605 simd8_grf_start
= v8
.payload
.num_regs
;
6606 simd8_grf_used
= v8
.grf_used
;
6609 if (v8
.max_dispatch_width
>= 16 &&
6610 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
6611 /* Try a SIMD16 compile */
6612 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
6613 &prog_data
->base
, prog
, shader
, 16,
6614 shader_time_index16
);
6615 v16
.import_uniforms(&v8
);
6616 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
6617 compiler
->shader_perf_log(log_data
,
6618 "SIMD16 shader failed to compile: %s",
6621 simd16_cfg
= v16
.cfg
;
6622 simd16_grf_start
= v16
.payload
.num_regs
;
6623 simd16_grf_used
= v16
.grf_used
;
6627 /* When the caller requests a repclear shader, they want SIMD16-only */
6631 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
6632 * at the top to select the shader. We've never implemented that.
6633 * Instead, we just give them exactly one shader and we pick the widest one
6636 if (compiler
->devinfo
->gen
< 5 && simd16_cfg
)
6639 if (prog_data
->persample_dispatch
) {
6640 /* Starting with SandyBridge (where we first get MSAA), the different
6641 * pixel dispatch combinations are grouped into classifications A
6642 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
6643 * generations, the only configurations supporting persample dispatch
6644 * are are this in which only one dispatch width is enabled.
6646 * If computed depth is enabled, SNB only allows SIMD8 while IVB+
6647 * allow SIMD8 or SIMD16 so we choose SIMD16 if available.
6649 if (compiler
->devinfo
->gen
== 6 &&
6650 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
) {
6652 } else if (simd16_cfg
) {
6657 /* We have to compute the flat inputs after the visitor is finished running
6658 * because it relies on prog_data->urb_setup which is computed in
6659 * fs_visitor::calculate_urb_setup().
6661 brw_compute_flat_inputs(prog_data
, shader
);
6663 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
6664 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6665 MESA_SHADER_FRAGMENT
);
6667 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
6668 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
6669 shader
->info
.label
? shader
->info
.label
:
6671 shader
->info
.name
));
6675 prog_data
->dispatch_8
= true;
6676 g
.generate_code(simd8_cfg
, 8);
6677 prog_data
->base
.dispatch_grf_start_reg
= simd8_grf_start
;
6678 prog_data
->reg_blocks_0
= brw_register_blocks(simd8_grf_used
);
6681 prog_data
->dispatch_16
= true;
6682 prog_data
->prog_offset_2
= g
.generate_code(simd16_cfg
, 16);
6683 prog_data
->dispatch_grf_start_reg_2
= simd16_grf_start
;
6684 prog_data
->reg_blocks_2
= brw_register_blocks(simd16_grf_used
);
6686 } else if (simd16_cfg
) {
6687 prog_data
->dispatch_16
= true;
6688 g
.generate_code(simd16_cfg
, 16);
6689 prog_data
->base
.dispatch_grf_start_reg
= simd16_grf_start
;
6690 prog_data
->reg_blocks_0
= brw_register_blocks(simd16_grf_used
);
6693 return g
.get_assembly(final_assembly_size
);
6697 fs_visitor::emit_cs_work_group_id_setup()
6699 assert(stage
== MESA_SHADER_COMPUTE
);
6701 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6703 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
6704 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
6705 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
6707 bld
.MOV(*reg
, r0_1
);
6708 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
6709 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
6715 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
6717 block
->dwords
= dwords
;
6718 block
->regs
= DIV_ROUND_UP(dwords
, 8);
6719 block
->size
= block
->regs
* 32;
6723 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
6724 struct brw_cs_prog_data
*cs_prog_data
)
6726 const struct brw_stage_prog_data
*prog_data
=
6727 (struct brw_stage_prog_data
*) cs_prog_data
;
6728 bool fill_thread_id
=
6729 cs_prog_data
->thread_local_id_index
>= 0 &&
6730 cs_prog_data
->thread_local_id_index
< (int)prog_data
->nr_params
;
6731 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
6733 /* The thread ID should be stored in the last param dword */
6734 assert(prog_data
->nr_params
> 0 || !fill_thread_id
);
6735 assert(!fill_thread_id
||
6736 cs_prog_data
->thread_local_id_index
==
6737 (int)prog_data
->nr_params
- 1);
6739 unsigned cross_thread_dwords
, per_thread_dwords
;
6740 if (!cross_thread_supported
) {
6741 cross_thread_dwords
= 0u;
6742 per_thread_dwords
= prog_data
->nr_params
;
6743 } else if (fill_thread_id
) {
6744 /* Fill all but the last register with cross-thread payload */
6745 cross_thread_dwords
= 8 * (cs_prog_data
->thread_local_id_index
/ 8);
6746 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
6747 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
6749 /* Fill all data using cross-thread payload */
6750 cross_thread_dwords
= prog_data
->nr_params
;
6751 per_thread_dwords
= 0u;
6754 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
6755 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
6757 unsigned total_dwords
=
6758 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
6759 cs_prog_data
->push
.cross_thread
.size
) / 4;
6760 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
6762 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
6763 cs_prog_data
->push
.per_thread
.size
== 0);
6764 assert(cs_prog_data
->push
.cross_thread
.dwords
+
6765 cs_prog_data
->push
.per_thread
.dwords
==
6766 prog_data
->nr_params
);
6770 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
6772 cs_prog_data
->simd_size
= size
;
6773 unsigned group_size
= cs_prog_data
->local_size
[0] *
6774 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
6775 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
6779 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
6781 const struct brw_cs_prog_key
*key
,
6782 struct brw_cs_prog_data
*prog_data
,
6783 const nir_shader
*src_shader
,
6784 int shader_time_index
,
6785 unsigned *final_assembly_size
,
6788 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6789 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6791 brw_nir_lower_cs_shared(shader
);
6792 prog_data
->base
.total_shared
+= shader
->num_shared
;
6794 /* Now that we cloned the nir_shader, we can update num_uniforms based on
6795 * the thread_local_id_index.
6797 assert(prog_data
->thread_local_id_index
>= 0);
6798 shader
->num_uniforms
=
6799 MAX2(shader
->num_uniforms
,
6800 (unsigned)4 * (prog_data
->thread_local_id_index
+ 1));
6802 brw_nir_lower_intrinsics(shader
, &prog_data
->base
);
6803 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6805 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
6806 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
6807 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
6808 unsigned local_workgroup_size
=
6809 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
6810 shader
->info
.cs
.local_size
[2];
6812 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
6813 unsigned simd_required
= DIV_ROUND_UP(local_workgroup_size
, max_cs_threads
);
6816 const char *fail_msg
= NULL
;
6818 /* Now the main event: Visit the shader IR and generate our CS IR for it.
6820 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6821 NULL
, /* Never used in core profile */
6822 shader
, 8, shader_time_index
);
6823 if (simd_required
<= 8) {
6825 fail_msg
= v8
.fail_msg
;
6828 cs_set_simd_size(prog_data
, 8);
6829 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6830 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
6834 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6835 NULL
, /* Never used in core profile */
6836 shader
, 16, shader_time_index
);
6837 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
6838 !fail_msg
&& v8
.max_dispatch_width
>= 16 &&
6839 simd_required
<= 16) {
6840 /* Try a SIMD16 compile */
6841 if (simd_required
<= 8)
6842 v16
.import_uniforms(&v8
);
6843 if (!v16
.run_cs()) {
6844 compiler
->shader_perf_log(log_data
,
6845 "SIMD16 shader failed to compile: %s",
6849 "Couldn't generate SIMD16 program and not "
6850 "enough threads for SIMD8";
6854 cs_set_simd_size(prog_data
, 16);
6855 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6856 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
6860 fs_visitor
v32(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6861 NULL
, /* Never used in core profile */
6862 shader
, 32, shader_time_index
);
6863 if (!fail_msg
&& v8
.max_dispatch_width
>= 32 &&
6864 (simd_required
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
6865 /* Try a SIMD32 compile */
6866 if (simd_required
<= 8)
6867 v32
.import_uniforms(&v8
);
6868 else if (simd_required
<= 16)
6869 v32
.import_uniforms(&v16
);
6871 if (!v32
.run_cs()) {
6872 compiler
->shader_perf_log(log_data
,
6873 "SIMD32 shader failed to compile: %s",
6877 "Couldn't generate SIMD32 program and not "
6878 "enough threads for SIMD16";
6882 cs_set_simd_size(prog_data
, 32);
6883 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6887 if (unlikely(cfg
== NULL
)) {
6890 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
6895 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
6896 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6897 MESA_SHADER_COMPUTE
);
6898 if (INTEL_DEBUG
& DEBUG_CS
) {
6899 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
6900 shader
->info
.label
? shader
->info
.label
:
6903 g
.enable_debug(name
);
6906 g
.generate_code(cfg
, prog_data
->simd_size
);
6908 return g
.get_assembly(final_assembly_size
);