2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "../glsl/glsl_types.h"
47 #include "../glsl/ir_optimization.h"
48 #include "../glsl/ir_print_visitor.h"
51 ARF
= BRW_ARCHITECTURE_REGISTER_FILE
,
52 GRF
= BRW_GENERAL_REGISTER_FILE
,
53 MRF
= BRW_MESSAGE_REGISTER_FILE
,
54 IMM
= BRW_IMMEDIATE_VALUE
,
55 FIXED_HW_REG
, /* a struct brw_reg */
56 UNIFORM
, /* prog_data->params[hw_reg] */
61 FS_OPCODE_FB_WRITE
= 256,
79 static int using_new_fs
= -1;
80 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
83 brw_new_shader(GLcontext
*ctx
, GLuint name
, GLuint type
)
85 struct brw_shader
*shader
;
87 shader
= talloc_zero(NULL
, struct brw_shader
);
89 shader
->base
.Type
= type
;
90 shader
->base
.Name
= name
;
91 _mesa_init_shader(ctx
, &shader
->base
);
97 struct gl_shader_program
*
98 brw_new_shader_program(GLcontext
*ctx
, GLuint name
)
100 struct brw_shader_program
*prog
;
101 prog
= talloc_zero(NULL
, struct brw_shader_program
);
103 prog
->base
.Name
= name
;
104 _mesa_init_shader_program(ctx
, &prog
->base
);
110 brw_compile_shader(GLcontext
*ctx
, struct gl_shader
*shader
)
112 if (!_mesa_ir_compile_shader(ctx
, shader
))
119 brw_link_shader(GLcontext
*ctx
, struct gl_shader_program
*prog
)
121 struct intel_context
*intel
= intel_context(ctx
);
122 if (using_new_fs
== -1)
123 using_new_fs
= getenv("INTEL_NEW_FS") != NULL
;
125 for (unsigned i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
126 struct brw_shader
*shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
128 if (using_new_fs
&& shader
->base
.Type
== GL_FRAGMENT_SHADER
) {
129 void *mem_ctx
= talloc_new(NULL
);
133 talloc_free(shader
->ir
);
134 shader
->ir
= new(shader
) exec_list
;
135 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
137 do_mat_op_to_vec(shader
->ir
);
138 do_mod_to_fract(shader
->ir
);
139 do_div_to_mul_rcp(shader
->ir
);
140 do_sub_to_add_neg(shader
->ir
);
141 do_explog_to_explog2(shader
->ir
);
142 do_lower_texture_projection(shader
->ir
);
143 brw_do_cubemap_normalize(shader
->ir
);
148 brw_do_channel_expressions(shader
->ir
);
149 brw_do_vector_splitting(shader
->ir
);
151 progress
= do_lower_jumps(shader
->ir
, true, true,
152 true, /* main return */
153 false, /* continue */
157 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
159 progress
= lower_noise(shader
->ir
) || progress
;
161 lower_variable_index_to_cond_assign(shader
->ir
,
163 GL_TRUE
, /* output */
165 GL_TRUE
/* uniform */
167 if (intel
->gen
== 6) {
168 progress
= do_if_to_cond_assign(shader
->ir
) || progress
;
172 validate_ir_tree(shader
->ir
);
174 reparent_ir(shader
->ir
, shader
->ir
);
175 talloc_free(mem_ctx
);
179 if (!_mesa_ir_link_shader(ctx
, prog
))
186 type_size(const struct glsl_type
*type
)
188 unsigned int size
, i
;
190 switch (type
->base_type
) {
193 case GLSL_TYPE_FLOAT
:
195 return type
->components();
196 case GLSL_TYPE_ARRAY
:
197 return type_size(type
->fields
.array
) * type
->length
;
198 case GLSL_TYPE_STRUCT
:
200 for (i
= 0; i
< type
->length
; i
++) {
201 size
+= type_size(type
->fields
.structure
[i
].type
);
204 case GLSL_TYPE_SAMPLER
:
205 /* Samplers take up no register space, since they're baked in at
210 assert(!"not reached");
217 /* Callers of this talloc-based new need not call delete. It's
218 * easier to just talloc_free 'ctx' (or any of its ancestors). */
219 static void* operator new(size_t size
, void *ctx
)
223 node
= talloc_size(ctx
, size
);
224 assert(node
!= NULL
);
232 this->reg_offset
= 0;
238 /** Generic unset register constructor. */
242 this->file
= BAD_FILE
;
245 /** Immediate value constructor. */
250 this->type
= BRW_REGISTER_TYPE_F
;
254 /** Immediate value constructor. */
259 this->type
= BRW_REGISTER_TYPE_D
;
263 /** Immediate value constructor. */
268 this->type
= BRW_REGISTER_TYPE_UD
;
272 /** Fixed brw_reg Immediate value constructor. */
273 fs_reg(struct brw_reg fixed_hw_reg
)
276 this->file
= FIXED_HW_REG
;
277 this->fixed_hw_reg
= fixed_hw_reg
;
278 this->type
= fixed_hw_reg
.type
;
281 fs_reg(enum register_file file
, int hw_reg
);
282 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
284 /** Register file: ARF, GRF, MRF, IMM. */
285 enum register_file file
;
286 /** virtual register number. 0 = fixed hw reg */
288 /** Offset within the virtual register. */
290 /** HW register number. Generally unset until register allocation. */
292 /** Register type. BRW_REGISTER_TYPE_* */
296 struct brw_reg fixed_hw_reg
;
298 /** Value for file == BRW_IMMMEDIATE_FILE */
306 static const fs_reg reg_undef
;
307 static const fs_reg
reg_null(ARF
, BRW_ARF_NULL
);
309 class fs_inst
: public exec_node
{
311 /* Callers of this talloc-based new need not call delete. It's
312 * easier to just talloc_free 'ctx' (or any of its ancestors). */
313 static void* operator new(size_t size
, void *ctx
)
317 node
= talloc_zero_size(ctx
, size
);
318 assert(node
!= NULL
);
325 this->opcode
= BRW_OPCODE_NOP
;
326 this->saturate
= false;
327 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
328 this->predicated
= false;
332 this->header_present
= false;
333 this->shadow_compare
= false;
344 this->opcode
= opcode
;
347 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
)
350 this->opcode
= opcode
;
355 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
358 this->opcode
= opcode
;
364 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg src2
)
367 this->opcode
= opcode
;
374 int opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
379 int conditional_mod
; /**< BRW_CONDITIONAL_* */
381 int mlen
; /**< SEND message length */
383 int target
; /**< MRT target. */
389 * Annotation for the generated IR. One of the two can be set.
392 const char *annotation
;
396 class fs_visitor
: public ir_visitor
400 fs_visitor(struct brw_wm_compile
*c
, struct brw_shader
*shader
)
405 this->fp
= brw
->fragment_program
;
406 this->intel
= &brw
->intel
;
407 this->ctx
= &intel
->ctx
;
408 this->mem_ctx
= talloc_new(NULL
);
409 this->shader
= shader
;
411 this->variable_ht
= hash_table_ctor(0,
412 hash_table_pointer_hash
,
413 hash_table_pointer_compare
);
415 this->frag_color
= NULL
;
416 this->frag_data
= NULL
;
417 this->frag_depth
= NULL
;
418 this->first_non_payload_grf
= 0;
420 this->current_annotation
= NULL
;
421 this->annotation_string
= NULL
;
422 this->annotation_ir
= NULL
;
423 this->base_ir
= NULL
;
425 this->virtual_grf_sizes
= NULL
;
426 this->virtual_grf_next
= 1;
427 this->virtual_grf_array_size
= 0;
428 this->virtual_grf_def
= NULL
;
429 this->virtual_grf_use
= NULL
;
431 this->kill_emitted
= false;
436 talloc_free(this->mem_ctx
);
437 hash_table_dtor(this->variable_ht
);
440 fs_reg
*variable_storage(ir_variable
*var
);
441 int virtual_grf_alloc(int size
);
443 void visit(ir_variable
*ir
);
444 void visit(ir_assignment
*ir
);
445 void visit(ir_dereference_variable
*ir
);
446 void visit(ir_dereference_record
*ir
);
447 void visit(ir_dereference_array
*ir
);
448 void visit(ir_expression
*ir
);
449 void visit(ir_texture
*ir
);
450 void visit(ir_if
*ir
);
451 void visit(ir_constant
*ir
);
452 void visit(ir_swizzle
*ir
);
453 void visit(ir_return
*ir
);
454 void visit(ir_loop
*ir
);
455 void visit(ir_loop_jump
*ir
);
456 void visit(ir_discard
*ir
);
457 void visit(ir_call
*ir
);
458 void visit(ir_function
*ir
);
459 void visit(ir_function_signature
*ir
);
461 fs_inst
*emit(fs_inst inst
);
462 void assign_curb_setup();
463 void calculate_urb_setup();
464 void assign_urb_setup();
466 void assign_regs_trivial();
467 void calculate_live_intervals();
468 bool propagate_constants();
469 bool register_coalesce();
470 bool dead_code_eliminate();
471 bool virtual_grf_interferes(int a
, int b
);
472 void generate_code();
473 void generate_fb_write(fs_inst
*inst
);
474 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
475 struct brw_reg
*src
);
476 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
477 void generate_math(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg
*src
);
478 void generate_discard(fs_inst
*inst
, struct brw_reg temp
);
479 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
480 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
482 void emit_dummy_fs();
483 fs_reg
*emit_fragcoord_interpolation(ir_variable
*ir
);
484 fs_reg
*emit_frontfacing_interpolation(ir_variable
*ir
);
485 fs_reg
*emit_general_interpolation(ir_variable
*ir
);
486 void emit_interpolation_setup_gen4();
487 void emit_interpolation_setup_gen6();
488 fs_inst
*emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
);
489 fs_inst
*emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
);
490 void emit_fb_writes();
491 void emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
492 const glsl_type
*type
, bool predicated
);
494 struct brw_reg
interp_reg(int location
, int channel
);
495 int setup_uniform_values(int loc
, const glsl_type
*type
);
496 void setup_builtin_uniform_values(ir_variable
*ir
);
498 struct brw_context
*brw
;
499 const struct gl_fragment_program
*fp
;
500 struct intel_context
*intel
;
502 struct brw_wm_compile
*c
;
503 struct brw_compile
*p
;
504 struct brw_shader
*shader
;
506 exec_list instructions
;
508 int *virtual_grf_sizes
;
509 int virtual_grf_next
;
510 int virtual_grf_array_size
;
511 int *virtual_grf_def
;
512 int *virtual_grf_use
;
514 struct hash_table
*variable_ht
;
515 ir_variable
*frag_color
, *frag_data
, *frag_depth
;
516 int first_non_payload_grf
;
517 int urb_setup
[FRAG_ATTRIB_MAX
];
520 /** @{ debug annotation info */
521 const char *current_annotation
;
522 ir_instruction
*base_ir
;
523 const char **annotation_string
;
524 ir_instruction
**annotation_ir
;
529 /* Result of last visit() method. */
544 fs_visitor::virtual_grf_alloc(int size
)
546 if (virtual_grf_array_size
<= virtual_grf_next
) {
547 if (virtual_grf_array_size
== 0)
548 virtual_grf_array_size
= 16;
550 virtual_grf_array_size
*= 2;
551 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
552 int, virtual_grf_array_size
);
554 /* This slot is always unused. */
555 virtual_grf_sizes
[0] = 0;
557 virtual_grf_sizes
[virtual_grf_next
] = size
;
558 return virtual_grf_next
++;
561 /** Fixed HW reg constructor. */
562 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
566 this->hw_reg
= hw_reg
;
567 this->type
= BRW_REGISTER_TYPE_F
;
571 brw_type_for_base_type(const struct glsl_type
*type
)
573 switch (type
->base_type
) {
574 case GLSL_TYPE_FLOAT
:
575 return BRW_REGISTER_TYPE_F
;
578 return BRW_REGISTER_TYPE_D
;
580 return BRW_REGISTER_TYPE_UD
;
581 case GLSL_TYPE_ARRAY
:
582 case GLSL_TYPE_STRUCT
:
583 /* These should be overridden with the type of the member when
584 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
585 * way to trip up if we don't.
587 return BRW_REGISTER_TYPE_UD
;
589 assert(!"not reached");
590 return BRW_REGISTER_TYPE_F
;
594 /** Automatic reg constructor. */
595 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
600 this->reg
= v
->virtual_grf_alloc(type_size(type
));
601 this->reg_offset
= 0;
602 this->type
= brw_type_for_base_type(type
);
606 fs_visitor::variable_storage(ir_variable
*var
)
608 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
611 /* Our support for uniforms is piggy-backed on the struct
612 * gl_fragment_program, because that's where the values actually
613 * get stored, rather than in some global gl_shader_program uniform
617 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
619 unsigned int offset
= 0;
622 if (type
->is_matrix()) {
623 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
624 type
->vector_elements
,
627 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
628 offset
+= setup_uniform_values(loc
+ offset
, column
);
634 switch (type
->base_type
) {
635 case GLSL_TYPE_FLOAT
:
639 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
640 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
641 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
645 case GLSL_TYPE_STRUCT
:
646 for (unsigned int i
= 0; i
< type
->length
; i
++) {
647 offset
+= setup_uniform_values(loc
+ offset
,
648 type
->fields
.structure
[i
].type
);
652 case GLSL_TYPE_ARRAY
:
653 for (unsigned int i
= 0; i
< type
->length
; i
++) {
654 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
658 case GLSL_TYPE_SAMPLER
:
659 /* The sampler takes up a slot, but we don't use any values from it. */
663 assert(!"not reached");
669 /* Our support for builtin uniforms is even scarier than non-builtin.
670 * It sits on top of the PROG_STATE_VAR parameters that are
671 * automatically updated from GL context state.
674 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
676 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
678 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
679 statevar
= &_mesa_builtin_uniform_desc
[i
];
680 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
684 if (!statevar
->name
) {
686 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
691 if (ir
->type
->is_array()) {
692 array_count
= ir
->type
->length
;
697 for (int a
= 0; a
< array_count
; a
++) {
698 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
699 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
700 int tokens
[STATE_LENGTH
];
702 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
703 if (ir
->type
->is_array()) {
707 /* This state reference has already been setup by ir_to_mesa,
708 * but we'll get the same index back here.
710 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
711 (gl_state_index
*)tokens
);
712 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
714 /* Add each of the unique swizzles of the element as a
715 * parameter. This'll end up matching the expected layout of
716 * the array/matrix/structure we're trying to fill in.
719 for (unsigned int i
= 0; i
< 4; i
++) {
720 int swiz
= GET_SWZ(element
->swizzle
, i
);
721 if (swiz
== last_swiz
)
725 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
732 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
734 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
736 fs_reg neg_y
= this->pixel_y
;
740 if (ir
->pixel_center_integer
) {
741 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
743 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
748 if (ir
->origin_upper_left
&& ir
->pixel_center_integer
) {
749 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
751 fs_reg pixel_y
= this->pixel_y
;
752 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
754 if (!ir
->origin_upper_left
) {
755 pixel_y
.negate
= true;
756 offset
+= c
->key
.drawable_height
- 1.0;
759 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
764 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
765 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
768 /* gl_FragCoord.w: Already set up in emit_interpolation */
769 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
775 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
777 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
778 /* Interpolation is always in floating point regs. */
779 reg
->type
= BRW_REGISTER_TYPE_F
;
782 unsigned int array_elements
;
783 const glsl_type
*type
;
785 if (ir
->type
->is_array()) {
786 array_elements
= ir
->type
->length
;
787 if (array_elements
== 0) {
790 type
= ir
->type
->fields
.array
;
796 int location
= ir
->location
;
797 for (unsigned int i
= 0; i
< array_elements
; i
++) {
798 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
799 if (urb_setup
[location
] == -1) {
800 /* If there's no incoming setup data for this slot, don't
801 * emit interpolation for it.
803 attr
.reg_offset
+= type
->vector_elements
;
808 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
809 struct brw_reg interp
= interp_reg(location
, c
);
810 emit(fs_inst(FS_OPCODE_LINTERP
,
818 if (intel
->gen
< 6) {
819 attr
.reg_offset
-= type
->vector_elements
;
820 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
821 emit(fs_inst(BRW_OPCODE_MUL
,
836 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
838 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
840 /* The frontfacing comes in as a bit in the thread payload. */
841 if (intel
->gen
>= 6) {
842 emit(fs_inst(BRW_OPCODE_ASR
,
844 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
846 emit(fs_inst(BRW_OPCODE_NOT
,
849 emit(fs_inst(BRW_OPCODE_AND
,
854 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
855 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
856 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
859 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
863 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
864 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
871 fs_visitor::visit(ir_variable
*ir
)
875 if (variable_storage(ir
))
878 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
879 this->frag_color
= ir
;
880 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
881 this->frag_data
= ir
;
882 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
883 this->frag_depth
= ir
;
886 if (ir
->mode
== ir_var_in
) {
887 if (!strcmp(ir
->name
, "gl_FragCoord")) {
888 reg
= emit_fragcoord_interpolation(ir
);
889 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
890 reg
= emit_frontfacing_interpolation(ir
);
892 reg
= emit_general_interpolation(ir
);
895 hash_table_insert(this->variable_ht
, reg
, ir
);
899 if (ir
->mode
== ir_var_uniform
) {
900 int param_index
= c
->prog_data
.nr_params
;
902 if (!strncmp(ir
->name
, "gl_", 3)) {
903 setup_builtin_uniform_values(ir
);
905 setup_uniform_values(ir
->location
, ir
->type
);
908 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
912 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
914 hash_table_insert(this->variable_ht
, reg
, ir
);
918 fs_visitor::visit(ir_dereference_variable
*ir
)
920 fs_reg
*reg
= variable_storage(ir
->var
);
925 fs_visitor::visit(ir_dereference_record
*ir
)
927 const glsl_type
*struct_type
= ir
->record
->type
;
929 ir
->record
->accept(this);
931 unsigned int offset
= 0;
932 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
933 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
935 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
937 this->result
.reg_offset
+= offset
;
938 this->result
.type
= brw_type_for_base_type(ir
->type
);
942 fs_visitor::visit(ir_dereference_array
*ir
)
947 ir
->array
->accept(this);
948 index
= ir
->array_index
->as_constant();
950 element_size
= type_size(ir
->type
);
951 this->result
.type
= brw_type_for_base_type(ir
->type
);
954 assert(this->result
.file
== UNIFORM
||
955 (this->result
.file
== GRF
&&
956 this->result
.reg
!= 0));
957 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
959 assert(!"FINISHME: non-constant array element");
964 fs_visitor::visit(ir_expression
*ir
)
966 unsigned int operand
;
971 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
972 ir
->operands
[operand
]->accept(this);
973 if (this->result
.file
== BAD_FILE
) {
975 printf("Failed to get tree for expression operand:\n");
976 ir
->operands
[operand
]->accept(&v
);
979 op
[operand
] = this->result
;
981 /* Matrix expression operands should have been broken down to vector
982 * operations already.
984 assert(!ir
->operands
[operand
]->type
->is_matrix());
985 /* And then those vector operands should have been broken down to scalar.
987 assert(!ir
->operands
[operand
]->type
->is_vector());
990 /* Storage for our result. If our result goes into an assignment, it will
991 * just get copy-propagated out, so no worries.
993 this->result
= fs_reg(this, ir
->type
);
995 switch (ir
->operation
) {
996 case ir_unop_logic_not
:
997 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], fs_reg(-1)));
1000 op
[0].negate
= !op
[0].negate
;
1001 this->result
= op
[0];
1005 this->result
= op
[0];
1008 temp
= fs_reg(this, ir
->type
);
1010 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
1012 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
1013 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1014 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
1015 inst
->predicated
= true;
1017 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
1018 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1019 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
1020 inst
->predicated
= true;
1024 emit(fs_inst(FS_OPCODE_RCP
, this->result
, op
[0]));
1028 emit(fs_inst(FS_OPCODE_EXP2
, this->result
, op
[0]));
1031 emit(fs_inst(FS_OPCODE_LOG2
, this->result
, op
[0]));
1035 assert(!"not reached: should be handled by ir_explog_to_explog2");
1038 emit(fs_inst(FS_OPCODE_SIN
, this->result
, op
[0]));
1041 emit(fs_inst(FS_OPCODE_COS
, this->result
, op
[0]));
1045 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
1048 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
1052 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
1055 assert(!"not reached: should be handled by ir_sub_to_add_neg");
1059 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
1062 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1065 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1069 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1070 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1071 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1073 case ir_binop_greater
:
1074 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1075 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1076 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1078 case ir_binop_lequal
:
1079 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1080 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1081 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1083 case ir_binop_gequal
:
1084 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1085 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1086 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1088 case ir_binop_equal
:
1089 case ir_binop_all_equal
: /* same as nequal for scalars */
1090 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1091 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1092 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1094 case ir_binop_nequal
:
1095 case ir_binop_any_nequal
: /* same as nequal for scalars */
1096 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1097 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1098 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1101 case ir_binop_logic_xor
:
1102 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
1105 case ir_binop_logic_or
:
1106 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
1109 case ir_binop_logic_and
:
1110 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
1114 case ir_binop_cross
:
1116 assert(!"not reached: should be handled by brw_fs_channel_expressions");
1120 assert(!"not reached: should be handled by lower_noise");
1124 emit(fs_inst(FS_OPCODE_SQRT
, this->result
, op
[0]));
1128 emit(fs_inst(FS_OPCODE_RSQ
, this->result
, op
[0]));
1134 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1137 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1141 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
1142 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1145 emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1148 op
[0].negate
= ~op
[0].negate
;
1149 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1150 this->result
.negate
= true;
1153 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1156 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
1160 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1161 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1163 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1164 inst
->predicated
= true;
1167 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1168 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1170 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1171 inst
->predicated
= true;
1175 inst
= emit(fs_inst(FS_OPCODE_POW
, this->result
, op
[0], op
[1]));
1178 case ir_unop_bit_not
:
1180 case ir_binop_lshift
:
1181 case ir_binop_rshift
:
1182 case ir_binop_bit_and
:
1183 case ir_binop_bit_xor
:
1184 case ir_binop_bit_or
:
1185 assert(!"GLSL 1.30 features unsupported");
1191 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1192 const glsl_type
*type
, bool predicated
)
1194 switch (type
->base_type
) {
1195 case GLSL_TYPE_FLOAT
:
1196 case GLSL_TYPE_UINT
:
1198 case GLSL_TYPE_BOOL
:
1199 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1200 l
.type
= brw_type_for_base_type(type
);
1201 r
.type
= brw_type_for_base_type(type
);
1203 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1204 inst
->predicated
= predicated
;
1210 case GLSL_TYPE_ARRAY
:
1211 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1212 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1215 case GLSL_TYPE_STRUCT
:
1216 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1217 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1222 case GLSL_TYPE_SAMPLER
:
1226 assert(!"not reached");
1232 fs_visitor::visit(ir_assignment
*ir
)
1237 /* FINISHME: arrays on the lhs */
1238 ir
->lhs
->accept(this);
1241 ir
->rhs
->accept(this);
1244 assert(l
.file
!= BAD_FILE
);
1245 assert(r
.file
!= BAD_FILE
);
1247 if (ir
->condition
) {
1248 /* Get the condition bool into the predicate. */
1249 ir
->condition
->accept(this);
1250 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, this->result
, fs_reg(0)));
1251 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1254 if (ir
->lhs
->type
->is_scalar() ||
1255 ir
->lhs
->type
->is_vector()) {
1256 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1257 if (ir
->write_mask
& (1 << i
)) {
1258 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1260 inst
->predicated
= true;
1266 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1271 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1275 bool simd16
= false;
1278 if (ir
->shadow_comparitor
) {
1279 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1280 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1282 coordinate
.reg_offset
++;
1284 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1287 if (ir
->op
== ir_tex
) {
1288 /* There's no plain shadow compare message, so we use shadow
1289 * compare with a bias of 0.0.
1291 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1294 } else if (ir
->op
== ir_txb
) {
1295 ir
->lod_info
.bias
->accept(this);
1296 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1300 assert(ir
->op
== ir_txl
);
1301 ir
->lod_info
.lod
->accept(this);
1302 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1307 ir
->shadow_comparitor
->accept(this);
1308 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1310 } else if (ir
->op
== ir_tex
) {
1311 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1312 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1314 coordinate
.reg_offset
++;
1316 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1319 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1320 * instructions. We'll need to do SIMD16 here.
1322 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1324 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
* 2;) {
1325 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1327 coordinate
.reg_offset
++;
1330 /* The unused upper half. */
1334 /* lod/bias appears after u/v/r. */
1337 if (ir
->op
== ir_txb
) {
1338 ir
->lod_info
.bias
->accept(this);
1339 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1343 ir
->lod_info
.lod
->accept(this);
1344 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1349 /* The unused upper half. */
1352 /* Now, since we're doing simd16, the return is 2 interleaved
1353 * vec4s where the odd-indexed ones are junk. We'll need to move
1354 * this weirdness around to the expected layout.
1358 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1360 dst
.type
= BRW_REGISTER_TYPE_F
;
1363 fs_inst
*inst
= NULL
;
1366 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
1369 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
, fs_reg(MRF
, base_mrf
)));
1372 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
, fs_reg(MRF
, base_mrf
)));
1376 assert(!"GLSL 1.30 features unsupported");
1382 for (int i
= 0; i
< 4; i
++) {
1383 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1384 orig_dst
.reg_offset
++;
1385 dst
.reg_offset
+= 2;
1393 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1395 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1396 * optional parameters like shadow comparitor or LOD bias. If
1397 * optional parameters aren't present, those base slots are
1398 * optional and don't need to be included in the message.
1400 * We don't fill in the unnecessary slots regardless, which may
1401 * look surprising in the disassembly.
1406 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1407 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1408 coordinate
.reg_offset
++;
1411 if (ir
->shadow_comparitor
) {
1412 mlen
= MAX2(mlen
, 4);
1414 ir
->shadow_comparitor
->accept(this);
1415 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1419 fs_inst
*inst
= NULL
;
1422 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
1425 ir
->lod_info
.bias
->accept(this);
1426 mlen
= MAX2(mlen
, 4);
1427 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1430 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
, fs_reg(MRF
, base_mrf
)));
1433 ir
->lod_info
.lod
->accept(this);
1434 mlen
= MAX2(mlen
, 4);
1435 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1438 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
, fs_reg(MRF
, base_mrf
)));
1442 assert(!"GLSL 1.30 features unsupported");
1451 fs_visitor::visit(ir_texture
*ir
)
1453 fs_inst
*inst
= NULL
;
1455 ir
->coordinate
->accept(this);
1456 fs_reg coordinate
= this->result
;
1458 /* Should be lowered by do_lower_texture_projection */
1459 assert(!ir
->projector
);
1461 /* Writemasking doesn't eliminate channels on SIMD8 texture
1462 * samples, so don't worry about them.
1464 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1466 if (intel
->gen
< 5) {
1467 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1469 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1473 _mesa_get_sampler_uniform_value(ir
->sampler
,
1474 ctx
->Shader
.CurrentProgram
,
1475 &brw
->fragment_program
->Base
);
1476 inst
->sampler
= c
->fp
->program
.Base
.SamplerUnits
[inst
->sampler
];
1480 if (ir
->shadow_comparitor
)
1481 inst
->shadow_compare
= true;
1483 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1484 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1486 for (int i
= 0; i
< 4; i
++) {
1487 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1488 fs_reg l
= swizzle_dst
;
1491 if (swiz
== SWIZZLE_ZERO
) {
1492 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1493 } else if (swiz
== SWIZZLE_ONE
) {
1494 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1497 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1498 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1501 this->result
= swizzle_dst
;
1506 fs_visitor::visit(ir_swizzle
*ir
)
1508 ir
->val
->accept(this);
1509 fs_reg val
= this->result
;
1511 if (ir
->type
->vector_elements
== 1) {
1512 this->result
.reg_offset
+= ir
->mask
.x
;
1516 fs_reg result
= fs_reg(this, ir
->type
);
1517 this->result
= result
;
1519 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1520 fs_reg channel
= val
;
1538 channel
.reg_offset
+= swiz
;
1539 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1540 result
.reg_offset
++;
1545 fs_visitor::visit(ir_discard
*ir
)
1547 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1549 assert(ir
->condition
== NULL
); /* FINISHME */
1551 emit(fs_inst(FS_OPCODE_DISCARD
, temp
, temp
));
1552 kill_emitted
= true;
1556 fs_visitor::visit(ir_constant
*ir
)
1558 fs_reg
reg(this, ir
->type
);
1561 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1562 switch (ir
->type
->base_type
) {
1563 case GLSL_TYPE_FLOAT
:
1564 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
1566 case GLSL_TYPE_UINT
:
1567 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1570 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1572 case GLSL_TYPE_BOOL
:
1573 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1576 assert(!"Non-float/uint/int/bool constant");
1583 fs_visitor::visit(ir_if
*ir
)
1587 /* Don't point the annotation at the if statement, because then it plus
1588 * the then and else blocks get printed.
1590 this->base_ir
= ir
->condition
;
1592 /* Generate the condition into the condition code. */
1593 ir
->condition
->accept(this);
1594 inst
= emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(brw_null_reg()), this->result
));
1595 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1597 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1598 inst
->predicated
= true;
1600 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1601 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1607 if (!ir
->else_instructions
.is_empty()) {
1608 emit(fs_inst(BRW_OPCODE_ELSE
));
1610 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1611 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1618 emit(fs_inst(BRW_OPCODE_ENDIF
));
1622 fs_visitor::visit(ir_loop
*ir
)
1624 fs_reg counter
= reg_undef
;
1627 this->base_ir
= ir
->counter
;
1628 ir
->counter
->accept(this);
1629 counter
= *(variable_storage(ir
->counter
));
1632 this->base_ir
= ir
->from
;
1633 ir
->from
->accept(this);
1635 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1639 emit(fs_inst(BRW_OPCODE_DO
));
1642 this->base_ir
= ir
->to
;
1643 ir
->to
->accept(this);
1645 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
,
1646 counter
, this->result
));
1648 case ir_binop_equal
:
1649 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1651 case ir_binop_nequal
:
1652 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1654 case ir_binop_gequal
:
1655 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1657 case ir_binop_lequal
:
1658 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1660 case ir_binop_greater
:
1661 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1664 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1667 assert(!"not reached: unknown loop condition");
1672 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1673 inst
->predicated
= true;
1676 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1677 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1683 if (ir
->increment
) {
1684 this->base_ir
= ir
->increment
;
1685 ir
->increment
->accept(this);
1686 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1689 emit(fs_inst(BRW_OPCODE_WHILE
));
1693 fs_visitor::visit(ir_loop_jump
*ir
)
1696 case ir_loop_jump::jump_break
:
1697 emit(fs_inst(BRW_OPCODE_BREAK
));
1699 case ir_loop_jump::jump_continue
:
1700 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1706 fs_visitor::visit(ir_call
*ir
)
1708 assert(!"FINISHME");
1712 fs_visitor::visit(ir_return
*ir
)
1714 assert(!"FINISHME");
1718 fs_visitor::visit(ir_function
*ir
)
1720 /* Ignore function bodies other than main() -- we shouldn't see calls to
1721 * them since they should all be inlined before we get to ir_to_mesa.
1723 if (strcmp(ir
->name
, "main") == 0) {
1724 const ir_function_signature
*sig
;
1727 sig
= ir
->matching_signature(&empty
);
1731 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1732 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1741 fs_visitor::visit(ir_function_signature
*ir
)
1743 assert(!"not reached");
1748 fs_visitor::emit(fs_inst inst
)
1750 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1753 list_inst
->annotation
= this->current_annotation
;
1754 list_inst
->ir
= this->base_ir
;
1756 this->instructions
.push_tail(list_inst
);
1761 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1763 fs_visitor::emit_dummy_fs()
1765 /* Everyone's favorite color. */
1766 emit(fs_inst(BRW_OPCODE_MOV
,
1769 emit(fs_inst(BRW_OPCODE_MOV
,
1772 emit(fs_inst(BRW_OPCODE_MOV
,
1775 emit(fs_inst(BRW_OPCODE_MOV
,
1780 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1785 /* The register location here is relative to the start of the URB
1786 * data. It will get adjusted to be a real location before
1787 * generate_code() time.
1790 fs_visitor::interp_reg(int location
, int channel
)
1792 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1793 int stride
= (channel
& 1) * 4;
1795 assert(urb_setup
[location
] != -1);
1797 return brw_vec1_grf(regnr
, stride
);
1800 /** Emits the interpolation for the varying inputs. */
1802 fs_visitor::emit_interpolation_setup_gen4()
1804 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1806 this->current_annotation
= "compute pixel centers";
1807 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1808 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1809 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1810 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1811 emit(fs_inst(BRW_OPCODE_ADD
,
1813 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1814 fs_reg(brw_imm_v(0x10101010))));
1815 emit(fs_inst(BRW_OPCODE_ADD
,
1817 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1818 fs_reg(brw_imm_v(0x11001100))));
1820 this->current_annotation
= "compute pixel deltas from v0";
1822 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1823 this->delta_y
= this->delta_x
;
1824 this->delta_y
.reg_offset
++;
1826 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1827 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1829 emit(fs_inst(BRW_OPCODE_ADD
,
1832 fs_reg(negate(brw_vec1_grf(1, 0)))));
1833 emit(fs_inst(BRW_OPCODE_ADD
,
1836 fs_reg(negate(brw_vec1_grf(1, 1)))));
1838 this->current_annotation
= "compute pos.w and 1/pos.w";
1839 /* Compute wpos.w. It's always in our setup, since it's needed to
1840 * interpolate the other attributes.
1842 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1843 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1844 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1845 /* Compute the pixel 1/W value from wpos.w. */
1846 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1847 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
));
1848 this->current_annotation
= NULL
;
1851 /** Emits the interpolation for the varying inputs. */
1853 fs_visitor::emit_interpolation_setup_gen6()
1855 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1857 /* If the pixel centers end up used, the setup is the same as for gen4. */
1858 this->current_annotation
= "compute pixel centers";
1859 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1860 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1861 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1862 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1863 emit(fs_inst(BRW_OPCODE_ADD
,
1865 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1866 fs_reg(brw_imm_v(0x10101010))));
1867 emit(fs_inst(BRW_OPCODE_ADD
,
1869 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1870 fs_reg(brw_imm_v(0x11001100))));
1872 this->current_annotation
= "compute 1/pos.w";
1873 this->wpos_w
= fs_reg(brw_vec8_grf(c
->key
.source_w_reg
, 0));
1874 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1875 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
));
1877 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1878 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1880 this->current_annotation
= NULL
;
1884 fs_visitor::emit_fb_writes()
1886 this->current_annotation
= "FB write header";
1887 GLboolean header_present
= GL_TRUE
;
1890 if (intel
->gen
>= 6 &&
1891 !this->kill_emitted
&&
1892 c
->key
.nr_color_regions
== 1) {
1893 header_present
= false;
1896 if (header_present
) {
1901 if (c
->key
.aa_dest_stencil_reg
) {
1902 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1903 fs_reg(brw_vec8_grf(c
->key
.aa_dest_stencil_reg
, 0))));
1906 /* Reserve space for color. It'll be filled in per MRT below. */
1910 if (c
->key
.source_depth_to_render_target
) {
1911 if (c
->key
.computes_depth
) {
1912 /* Hand over gl_FragDepth. */
1913 assert(this->frag_depth
);
1914 fs_reg depth
= *(variable_storage(this->frag_depth
));
1916 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
1918 /* Pass through the payload depth. */
1919 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1920 fs_reg(brw_vec8_grf(c
->key
.source_depth_reg
, 0))));
1924 if (c
->key
.dest_depth_reg
) {
1925 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1926 fs_reg(brw_vec8_grf(c
->key
.dest_depth_reg
, 0))));
1929 fs_reg color
= reg_undef
;
1930 if (this->frag_color
)
1931 color
= *(variable_storage(this->frag_color
));
1932 else if (this->frag_data
)
1933 color
= *(variable_storage(this->frag_data
));
1935 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1936 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1937 "FB write target %d",
1939 if (this->frag_color
|| this->frag_data
) {
1940 for (int i
= 0; i
< 4; i
++) {
1941 emit(fs_inst(BRW_OPCODE_MOV
,
1942 fs_reg(MRF
, color_mrf
+ i
),
1948 if (this->frag_color
)
1949 color
.reg_offset
-= 4;
1951 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1952 reg_undef
, reg_undef
));
1953 inst
->target
= target
;
1955 if (target
== c
->key
.nr_color_regions
- 1)
1957 inst
->header_present
= header_present
;
1960 if (c
->key
.nr_color_regions
== 0) {
1961 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1962 reg_undef
, reg_undef
));
1965 inst
->header_present
= header_present
;
1968 this->current_annotation
= NULL
;
1972 fs_visitor::generate_fb_write(fs_inst
*inst
)
1974 GLboolean eot
= inst
->eot
;
1975 struct brw_reg implied_header
;
1977 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1980 brw_push_insn_state(p
);
1981 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1982 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1984 if (inst
->header_present
) {
1985 if (intel
->gen
>= 6) {
1988 brw_vec8_grf(0, 0));
1989 implied_header
= brw_null_reg();
1991 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1996 brw_vec8_grf(1, 0));
1998 implied_header
= brw_null_reg();
2001 brw_pop_insn_state(p
);
2004 8, /* dispatch_width */
2005 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
2015 fs_visitor::generate_linterp(fs_inst
*inst
,
2016 struct brw_reg dst
, struct brw_reg
*src
)
2018 struct brw_reg delta_x
= src
[0];
2019 struct brw_reg delta_y
= src
[1];
2020 struct brw_reg interp
= src
[2];
2023 delta_y
.nr
== delta_x
.nr
+ 1 &&
2024 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
2025 brw_PLN(p
, dst
, interp
, delta_x
);
2027 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
2028 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
2033 fs_visitor::generate_math(fs_inst
*inst
,
2034 struct brw_reg dst
, struct brw_reg
*src
)
2038 switch (inst
->opcode
) {
2040 op
= BRW_MATH_FUNCTION_INV
;
2043 op
= BRW_MATH_FUNCTION_RSQ
;
2045 case FS_OPCODE_SQRT
:
2046 op
= BRW_MATH_FUNCTION_SQRT
;
2048 case FS_OPCODE_EXP2
:
2049 op
= BRW_MATH_FUNCTION_EXP
;
2051 case FS_OPCODE_LOG2
:
2052 op
= BRW_MATH_FUNCTION_LOG
;
2055 op
= BRW_MATH_FUNCTION_POW
;
2058 op
= BRW_MATH_FUNCTION_SIN
;
2061 op
= BRW_MATH_FUNCTION_COS
;
2064 assert(!"not reached: unknown math function");
2069 if (inst
->opcode
== FS_OPCODE_POW
) {
2070 brw_MOV(p
, brw_message_reg(3), src
[1]);
2075 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2076 BRW_MATH_SATURATE_NONE
,
2078 BRW_MATH_DATA_VECTOR
,
2079 BRW_MATH_PRECISION_FULL
);
2083 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2087 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2089 if (intel
->gen
>= 5) {
2090 switch (inst
->opcode
) {
2092 if (inst
->shadow_compare
) {
2093 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
2095 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
2099 if (inst
->shadow_compare
) {
2100 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
2102 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
2107 switch (inst
->opcode
) {
2109 /* Note that G45 and older determines shadow compare and dispatch width
2110 * from message length for most messages.
2112 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2113 if (inst
->shadow_compare
) {
2114 assert(inst
->mlen
== 5);
2116 assert(inst
->mlen
<= 6);
2120 if (inst
->shadow_compare
) {
2121 assert(inst
->mlen
== 5);
2122 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2124 assert(inst
->mlen
== 8);
2125 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2126 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2131 assert(msg_type
!= -1);
2133 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2142 retype(dst
, BRW_REGISTER_TYPE_UW
),
2144 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2145 SURF_INDEX_TEXTURE(inst
->sampler
),
2157 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2160 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2162 * and we're trying to produce:
2165 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2166 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2167 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2168 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2169 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2170 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2171 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2172 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2174 * and add another set of two more subspans if in 16-pixel dispatch mode.
2176 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2177 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2178 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2179 * between each other. We could probably do it like ddx and swizzle the right
2180 * order later, but bail for now and just produce
2181 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2184 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2186 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2187 BRW_REGISTER_TYPE_F
,
2188 BRW_VERTICAL_STRIDE_2
,
2190 BRW_HORIZONTAL_STRIDE_0
,
2191 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2192 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2193 BRW_REGISTER_TYPE_F
,
2194 BRW_VERTICAL_STRIDE_2
,
2196 BRW_HORIZONTAL_STRIDE_0
,
2197 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2198 brw_ADD(p
, dst
, src0
, negate(src1
));
2202 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2204 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2205 BRW_REGISTER_TYPE_F
,
2206 BRW_VERTICAL_STRIDE_4
,
2208 BRW_HORIZONTAL_STRIDE_0
,
2209 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2210 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2211 BRW_REGISTER_TYPE_F
,
2212 BRW_VERTICAL_STRIDE_4
,
2214 BRW_HORIZONTAL_STRIDE_0
,
2215 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2216 brw_ADD(p
, dst
, src0
, negate(src1
));
2220 fs_visitor::generate_discard(fs_inst
*inst
, struct brw_reg temp
)
2222 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2223 temp
= brw_uw1_reg(temp
.file
, temp
.nr
, 0);
2225 brw_push_insn_state(p
);
2226 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2227 brw_NOT(p
, temp
, brw_mask_reg(1)); /* IMASK */
2228 brw_AND(p
, g0
, temp
, g0
);
2229 brw_pop_insn_state(p
);
2233 fs_visitor::assign_curb_setup()
2235 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
2236 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2238 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2239 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2240 fs_inst
*inst
= (fs_inst
*)iter
.get();
2242 for (unsigned int i
= 0; i
< 3; i
++) {
2243 if (inst
->src
[i
].file
== UNIFORM
) {
2244 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2245 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2249 inst
->src
[i
].file
= FIXED_HW_REG
;
2250 inst
->src
[i
].fixed_hw_reg
= brw_reg
;
2257 fs_visitor::calculate_urb_setup()
2259 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2264 /* Figure out where each of the incoming setup attributes lands. */
2265 if (intel
->gen
>= 6) {
2266 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2267 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
2268 urb_setup
[i
] = urb_next
++;
2272 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2273 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2274 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2277 if (i
>= VERT_RESULT_VAR0
)
2278 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2279 else if (i
<= VERT_RESULT_TEX7
)
2285 urb_setup
[fp_index
] = urb_next
++;
2290 /* Each attribute is 4 setup channels, each of which is half a reg. */
2291 c
->prog_data
.urb_read_length
= urb_next
* 2;
2295 fs_visitor::assign_urb_setup()
2297 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2299 /* Offset all the urb_setup[] index by the actual position of the
2300 * setup regs, now that the location of the constants has been chosen.
2302 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2303 fs_inst
*inst
= (fs_inst
*)iter
.get();
2305 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
2308 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2310 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2313 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2317 assign_reg(int *reg_hw_locations
, fs_reg
*reg
)
2319 if (reg
->file
== GRF
&& reg
->reg
!= 0) {
2320 reg
->hw_reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
;
2326 fs_visitor::assign_regs_trivial()
2329 int hw_reg_mapping
[this->virtual_grf_next
];
2332 hw_reg_mapping
[0] = 0;
2333 hw_reg_mapping
[1] = this->first_non_payload_grf
;
2334 for (i
= 2; i
< this->virtual_grf_next
; i
++) {
2335 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
2336 this->virtual_grf_sizes
[i
- 1]);
2338 last_grf
= hw_reg_mapping
[i
- 1] + this->virtual_grf_sizes
[i
- 1];
2340 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2341 fs_inst
*inst
= (fs_inst
*)iter
.get();
2343 assign_reg(hw_reg_mapping
, &inst
->dst
);
2344 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2345 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2348 this->grf_used
= last_grf
+ 1;
2352 fs_visitor::assign_regs()
2355 int hw_reg_mapping
[this->virtual_grf_next
+ 1];
2356 int base_reg_count
= BRW_MAX_GRF
- this->first_non_payload_grf
;
2357 int class_sizes
[base_reg_count
];
2358 int class_count
= 0;
2359 int aligned_pair_class
= -1;
2361 /* Set up the register classes.
2363 * The base registers store a scalar value. For texture samples,
2364 * we get virtual GRFs composed of 4 contiguous hw register. For
2365 * structures and arrays, we store them as contiguous larger things
2366 * than that, though we should be able to do better most of the
2369 class_sizes
[class_count
++] = 1;
2370 if (brw
->has_pln
&& intel
->gen
< 6) {
2371 /* Always set up the (unaligned) pairs for gen5, so we can find
2372 * them for making the aligned pair class.
2374 class_sizes
[class_count
++] = 2;
2376 for (int r
= 1; r
< this->virtual_grf_next
; r
++) {
2379 for (i
= 0; i
< class_count
; i
++) {
2380 if (class_sizes
[i
] == this->virtual_grf_sizes
[r
])
2383 if (i
== class_count
) {
2384 if (this->virtual_grf_sizes
[r
] >= base_reg_count
) {
2385 fprintf(stderr
, "Object too large to register allocate.\n");
2389 class_sizes
[class_count
++] = this->virtual_grf_sizes
[r
];
2393 int ra_reg_count
= 0;
2394 int class_base_reg
[class_count
];
2395 int class_reg_count
[class_count
];
2396 int classes
[class_count
+ 1];
2398 for (int i
= 0; i
< class_count
; i
++) {
2399 class_base_reg
[i
] = ra_reg_count
;
2400 class_reg_count
[i
] = base_reg_count
- (class_sizes
[i
] - 1);
2401 ra_reg_count
+= class_reg_count
[i
];
2404 struct ra_regs
*regs
= ra_alloc_reg_set(ra_reg_count
);
2405 for (int i
= 0; i
< class_count
; i
++) {
2406 classes
[i
] = ra_alloc_reg_class(regs
);
2408 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2409 ra_class_add_reg(regs
, classes
[i
], class_base_reg
[i
] + i_r
);
2412 /* Add conflicts between our contiguous registers aliasing
2413 * base regs and other register classes' contiguous registers
2414 * that alias base regs, or the base regs themselves for classes[0].
2416 for (int c
= 0; c
<= i
; c
++) {
2417 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2418 for (int c_r
= MAX2(0, i_r
- (class_sizes
[c
] - 1));
2419 c_r
< MIN2(class_reg_count
[c
], i_r
+ class_sizes
[i
]);
2423 printf("%d/%d conflicts %d/%d\n",
2424 class_sizes
[i
], this->first_non_payload_grf
+ i_r
,
2425 class_sizes
[c
], this->first_non_payload_grf
+ c_r
);
2428 ra_add_reg_conflict(regs
,
2429 class_base_reg
[i
] + i_r
,
2430 class_base_reg
[c
] + c_r
);
2436 /* Add a special class for aligned pairs, which we'll put delta_x/y
2437 * in on gen5 so that we can do PLN.
2439 if (brw
->has_pln
&& intel
->gen
< 6) {
2440 int reg_count
= (base_reg_count
- 1) / 2;
2441 int unaligned_pair_class
= 1;
2442 assert(class_sizes
[unaligned_pair_class
] == 2);
2444 aligned_pair_class
= class_count
;
2445 classes
[aligned_pair_class
] = ra_alloc_reg_class(regs
);
2446 class_base_reg
[aligned_pair_class
] = 0;
2447 class_reg_count
[aligned_pair_class
] = 0;
2448 int start
= (this->first_non_payload_grf
& 1) ? 1 : 0;
2450 for (int i
= 0; i
< reg_count
; i
++) {
2451 ra_class_add_reg(regs
, classes
[aligned_pair_class
],
2452 class_base_reg
[unaligned_pair_class
] + i
* 2 + start
);
2457 ra_set_finalize(regs
);
2459 struct ra_graph
*g
= ra_alloc_interference_graph(regs
,
2460 this->virtual_grf_next
);
2461 /* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1
2464 ra_set_node_class(g
, 0, classes
[0]);
2466 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2467 for (int c
= 0; c
< class_count
; c
++) {
2468 if (class_sizes
[c
] == this->virtual_grf_sizes
[i
]) {
2469 if (aligned_pair_class
>= 0 &&
2470 this->delta_x
.reg
== i
) {
2471 ra_set_node_class(g
, i
, classes
[aligned_pair_class
]);
2473 ra_set_node_class(g
, i
, classes
[c
]);
2479 for (int j
= 1; j
< i
; j
++) {
2480 if (virtual_grf_interferes(i
, j
)) {
2481 ra_add_node_interference(g
, i
, j
);
2486 /* FINISHME: Handle spilling */
2487 if (!ra_allocate_no_spills(g
)) {
2488 fprintf(stderr
, "Failed to allocate registers.\n");
2493 /* Get the chosen virtual registers for each node, and map virtual
2494 * regs in the register classes back down to real hardware reg
2497 hw_reg_mapping
[0] = 0; /* unused */
2498 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2499 int reg
= ra_get_node_reg(g
, i
);
2502 for (int c
= 0; c
< class_count
; c
++) {
2503 if (reg
>= class_base_reg
[c
] &&
2504 reg
< class_base_reg
[c
] + class_reg_count
[c
]) {
2505 hw_reg
= reg
- class_base_reg
[c
];
2510 assert(hw_reg
!= -1);
2511 hw_reg_mapping
[i
] = this->first_non_payload_grf
+ hw_reg
;
2512 last_grf
= MAX2(last_grf
,
2513 hw_reg_mapping
[i
] + this->virtual_grf_sizes
[i
] - 1);
2516 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2517 fs_inst
*inst
= (fs_inst
*)iter
.get();
2519 assign_reg(hw_reg_mapping
, &inst
->dst
);
2520 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2521 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2524 this->grf_used
= last_grf
+ 1;
2531 fs_visitor::calculate_live_intervals()
2533 int num_vars
= this->virtual_grf_next
;
2534 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2535 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2539 for (int i
= 0; i
< num_vars
; i
++) {
2545 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2546 fs_inst
*inst
= (fs_inst
*)iter
.get();
2548 if (inst
->opcode
== BRW_OPCODE_DO
) {
2549 if (loop_depth
++ == 0)
2551 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2554 if (loop_depth
== 0) {
2557 * Patches up any vars marked for use within the loop as
2558 * live until the end. This is conservative, as there
2559 * will often be variables defined and used inside the
2560 * loop but dead at the end of the loop body.
2562 for (int i
= 0; i
< num_vars
; i
++) {
2563 if (use
[i
] == loop_start
) {
2574 for (unsigned int i
= 0; i
< 3; i
++) {
2575 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2576 use
[inst
->src
[i
].reg
] = MAX2(use
[inst
->src
[i
].reg
], eip
);
2579 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2580 def
[inst
->dst
.reg
] = MIN2(def
[inst
->dst
.reg
], eip
);
2587 talloc_free(this->virtual_grf_def
);
2588 talloc_free(this->virtual_grf_use
);
2589 this->virtual_grf_def
= def
;
2590 this->virtual_grf_use
= use
;
2594 * Attempts to move immediate constants into the immediate
2595 * constant slot of following instructions.
2597 * Immediate constants are a bit tricky -- they have to be in the last
2598 * operand slot, you can't do abs/negate on them,
2602 fs_visitor::propagate_constants()
2604 bool progress
= false;
2606 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2607 fs_inst
*inst
= (fs_inst
*)iter
.get();
2609 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2611 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2612 inst
->dst
.type
!= inst
->src
[0].type
)
2615 /* Don't bother with cases where we should have had the
2616 * operation on the constant folded in GLSL already.
2621 /* Found a move of a constant to a GRF. Find anything else using the GRF
2622 * before it's written, and replace it with the constant if we can.
2624 exec_list_iterator scan_iter
= iter
;
2626 for (; scan_iter
.has_next(); scan_iter
.next()) {
2627 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2629 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2630 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2631 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2632 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2636 for (int i
= 2; i
>= 0; i
--) {
2637 if (scan_inst
->src
[i
].file
!= GRF
||
2638 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2639 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2642 /* Don't bother with cases where we should have had the
2643 * operation on the constant folded in GLSL already.
2645 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2648 switch (scan_inst
->opcode
) {
2649 case BRW_OPCODE_MOV
:
2650 scan_inst
->src
[i
] = inst
->src
[0];
2654 case BRW_OPCODE_MUL
:
2655 case BRW_OPCODE_ADD
:
2657 scan_inst
->src
[i
] = inst
->src
[0];
2659 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2660 /* Fit this constant in by commuting the operands */
2661 scan_inst
->src
[0] = scan_inst
->src
[1];
2662 scan_inst
->src
[1] = inst
->src
[0];
2665 case BRW_OPCODE_CMP
:
2667 scan_inst
->src
[i
] = inst
->src
[0];
2673 if (scan_inst
->dst
.file
== GRF
&&
2674 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2675 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2676 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2685 * Must be called after calculate_live_intervales() to remove unused
2686 * writes to registers -- register allocation will fail otherwise
2687 * because something deffed but not used won't be considered to
2688 * interfere with other regs.
2691 fs_visitor::dead_code_eliminate()
2693 bool progress
= false;
2694 int num_vars
= this->virtual_grf_next
;
2695 bool dead
[num_vars
];
2697 for (int i
= 0; i
< num_vars
; i
++) {
2698 /* This would be ">=", but FS_OPCODE_DISCARD has a src == dst where
2699 * it writes dst then reads it as src.
2701 dead
[i
] = this->virtual_grf_def
[i
] > this->virtual_grf_use
[i
];
2704 /* Mark off its interval so it won't interfere with anything. */
2705 this->virtual_grf_def
[i
] = -1;
2706 this->virtual_grf_use
[i
] = -1;
2710 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2711 fs_inst
*inst
= (fs_inst
*)iter
.get();
2713 if (inst
->dst
.file
== GRF
&& dead
[inst
->dst
.reg
]) {
2723 fs_visitor::register_coalesce()
2725 bool progress
= false;
2727 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2728 fs_inst
*inst
= (fs_inst
*)iter
.get();
2730 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2733 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= GRF
||
2734 inst
->dst
.type
!= inst
->src
[0].type
)
2737 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
2738 * them: check for no writes to either one until the exit of the
2741 bool interfered
= false;
2742 exec_list_iterator scan_iter
= iter
;
2744 for (; scan_iter
.has_next(); scan_iter
.next()) {
2745 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2747 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2748 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2749 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2755 if (scan_inst
->dst
.file
== GRF
) {
2756 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2757 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2758 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2762 if (scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
2763 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
2764 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2774 /* Rewrite the later usage to point at the source of the move to
2777 for (exec_list_iterator scan_iter
= iter
; scan_iter
.has_next();
2779 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2781 for (int i
= 0; i
< 3; i
++) {
2782 if (scan_inst
->src
[i
].file
== GRF
&&
2783 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
2784 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
2785 scan_inst
->src
[i
].reg
= inst
->src
[0].reg
;
2786 scan_inst
->src
[i
].reg_offset
= inst
->src
[0].reg_offset
;
2787 scan_inst
->src
[i
].abs
|= inst
->src
[0].abs
;
2788 scan_inst
->src
[i
].negate
^= inst
->src
[0].negate
;
2801 fs_visitor::virtual_grf_interferes(int a
, int b
)
2803 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
2804 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
2806 /* For dead code, just check if the def interferes with the other range. */
2807 if (this->virtual_grf_use
[a
] == -1) {
2808 return (this->virtual_grf_def
[a
] >= this->virtual_grf_def
[b
] &&
2809 this->virtual_grf_def
[a
] < this->virtual_grf_use
[b
]);
2811 if (this->virtual_grf_use
[b
] == -1) {
2812 return (this->virtual_grf_def
[b
] >= this->virtual_grf_def
[a
] &&
2813 this->virtual_grf_def
[b
] < this->virtual_grf_use
[a
]);
2816 return start
<= end
;
2819 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
2821 struct brw_reg brw_reg
;
2823 switch (reg
->file
) {
2827 brw_reg
= brw_vec8_reg(reg
->file
,
2829 brw_reg
= retype(brw_reg
, reg
->type
);
2832 switch (reg
->type
) {
2833 case BRW_REGISTER_TYPE_F
:
2834 brw_reg
= brw_imm_f(reg
->imm
.f
);
2836 case BRW_REGISTER_TYPE_D
:
2837 brw_reg
= brw_imm_d(reg
->imm
.i
);
2839 case BRW_REGISTER_TYPE_UD
:
2840 brw_reg
= brw_imm_ud(reg
->imm
.u
);
2843 assert(!"not reached");
2848 brw_reg
= reg
->fixed_hw_reg
;
2851 /* Probably unused. */
2852 brw_reg
= brw_null_reg();
2855 assert(!"not reached");
2856 brw_reg
= brw_null_reg();
2860 brw_reg
= brw_abs(brw_reg
);
2862 brw_reg
= negate(brw_reg
);
2868 fs_visitor::generate_code()
2870 unsigned int annotation_len
= 0;
2871 int last_native_inst
= 0;
2872 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
2873 int if_stack_depth
= 0, loop_stack_depth
= 0;
2874 int if_depth_in_loop
[16];
2876 if_depth_in_loop
[loop_stack_depth
] = 0;
2878 memset(&if_stack
, 0, sizeof(if_stack
));
2879 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2880 fs_inst
*inst
= (fs_inst
*)iter
.get();
2881 struct brw_reg src
[3], dst
;
2883 for (unsigned int i
= 0; i
< 3; i
++) {
2884 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
2886 dst
= brw_reg_from_fs_reg(&inst
->dst
);
2888 brw_set_conditionalmod(p
, inst
->conditional_mod
);
2889 brw_set_predicate_control(p
, inst
->predicated
);
2891 switch (inst
->opcode
) {
2892 case BRW_OPCODE_MOV
:
2893 brw_MOV(p
, dst
, src
[0]);
2895 case BRW_OPCODE_ADD
:
2896 brw_ADD(p
, dst
, src
[0], src
[1]);
2898 case BRW_OPCODE_MUL
:
2899 brw_MUL(p
, dst
, src
[0], src
[1]);
2902 case BRW_OPCODE_FRC
:
2903 brw_FRC(p
, dst
, src
[0]);
2905 case BRW_OPCODE_RNDD
:
2906 brw_RNDD(p
, dst
, src
[0]);
2908 case BRW_OPCODE_RNDZ
:
2909 brw_RNDZ(p
, dst
, src
[0]);
2912 case BRW_OPCODE_AND
:
2913 brw_AND(p
, dst
, src
[0], src
[1]);
2916 brw_OR(p
, dst
, src
[0], src
[1]);
2918 case BRW_OPCODE_XOR
:
2919 brw_XOR(p
, dst
, src
[0], src
[1]);
2921 case BRW_OPCODE_NOT
:
2922 brw_NOT(p
, dst
, src
[0]);
2924 case BRW_OPCODE_ASR
:
2925 brw_ASR(p
, dst
, src
[0], src
[1]);
2927 case BRW_OPCODE_SHR
:
2928 brw_SHR(p
, dst
, src
[0], src
[1]);
2930 case BRW_OPCODE_SHL
:
2931 brw_SHL(p
, dst
, src
[0], src
[1]);
2934 case BRW_OPCODE_CMP
:
2935 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
2937 case BRW_OPCODE_SEL
:
2938 brw_SEL(p
, dst
, src
[0], src
[1]);
2942 assert(if_stack_depth
< 16);
2943 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
2944 if_depth_in_loop
[loop_stack_depth
]++;
2947 case BRW_OPCODE_ELSE
:
2948 if_stack
[if_stack_depth
- 1] =
2949 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
2951 case BRW_OPCODE_ENDIF
:
2953 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
2954 if_depth_in_loop
[loop_stack_depth
]--;
2958 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
2959 if_depth_in_loop
[loop_stack_depth
] = 0;
2962 case BRW_OPCODE_BREAK
:
2963 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
2964 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2966 case BRW_OPCODE_CONTINUE
:
2967 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
2968 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2971 case BRW_OPCODE_WHILE
: {
2972 struct brw_instruction
*inst0
, *inst1
;
2975 if (intel
->gen
>= 5)
2978 assert(loop_stack_depth
> 0);
2980 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
2981 /* patch all the BREAK/CONT instructions from last BGNLOOP */
2982 while (inst0
> loop_stack
[loop_stack_depth
]) {
2984 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
2985 inst0
->bits3
.if_else
.jump_count
== 0) {
2986 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
2988 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
2989 inst0
->bits3
.if_else
.jump_count
== 0) {
2990 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
2998 case FS_OPCODE_SQRT
:
2999 case FS_OPCODE_EXP2
:
3000 case FS_OPCODE_LOG2
:
3004 generate_math(inst
, dst
, src
);
3006 case FS_OPCODE_LINTERP
:
3007 generate_linterp(inst
, dst
, src
);
3012 generate_tex(inst
, dst
, src
[0]);
3014 case FS_OPCODE_DISCARD
:
3015 generate_discard(inst
, dst
/* src0 == dst */);
3018 generate_ddx(inst
, dst
, src
[0]);
3021 generate_ddy(inst
, dst
, src
[0]);
3023 case FS_OPCODE_FB_WRITE
:
3024 generate_fb_write(inst
);
3027 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
3028 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
3029 brw_opcodes
[inst
->opcode
].name
);
3031 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
3036 if (annotation_len
< p
->nr_insn
) {
3037 annotation_len
*= 2;
3038 if (annotation_len
< 16)
3039 annotation_len
= 16;
3041 this->annotation_string
= talloc_realloc(this->mem_ctx
,
3045 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
3051 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
3052 this->annotation_string
[i
] = inst
->annotation
;
3053 this->annotation_ir
[i
] = inst
->ir
;
3055 last_native_inst
= p
->nr_insn
;
3060 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
3062 struct brw_compile
*p
= &c
->func
;
3063 struct intel_context
*intel
= &brw
->intel
;
3064 GLcontext
*ctx
= &intel
->ctx
;
3065 struct brw_shader
*shader
= NULL
;
3066 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
3074 for (unsigned int i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
3075 if (prog
->_LinkedShaders
[i
]->Type
== GL_FRAGMENT_SHADER
) {
3076 shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
3083 /* We always use 8-wide mode, at least for now. For one, flow
3084 * control only works in 8-wide. Also, when we're fragment shader
3085 * bound, we're almost always under register pressure as well, so
3086 * 8-wide would save us from the performance cliff of spilling
3089 c
->dispatch_width
= 8;
3091 if (INTEL_DEBUG
& DEBUG_WM
) {
3092 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3093 _mesa_print_ir(shader
->ir
, NULL
);
3097 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3099 fs_visitor
v(c
, shader
);
3104 v
.calculate_urb_setup();
3106 v
.emit_interpolation_setup_gen4();
3108 v
.emit_interpolation_setup_gen6();
3110 /* Generate FS IR for main(). (the visitor only descends into
3111 * functions called "main").
3113 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
3114 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
3120 v
.assign_curb_setup();
3121 v
.assign_urb_setup();
3127 v
.calculate_live_intervals();
3128 progress
= v
.propagate_constants() || progress
;
3129 progress
= v
.register_coalesce() || progress
;
3130 progress
= v
.dead_code_eliminate() || progress
;
3134 v
.assign_regs_trivial();
3142 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3147 if (INTEL_DEBUG
& DEBUG_WM
) {
3148 const char *last_annotation_string
= NULL
;
3149 ir_instruction
*last_annotation_ir
= NULL
;
3151 printf("Native code for fragment shader %d:\n", prog
->Name
);
3152 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
3153 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
3154 last_annotation_ir
= v
.annotation_ir
[i
];
3155 if (last_annotation_ir
) {
3157 last_annotation_ir
->print();
3161 if (last_annotation_string
!= v
.annotation_string
[i
]) {
3162 last_annotation_string
= v
.annotation_string
[i
];
3163 if (last_annotation_string
)
3164 printf(" %s\n", last_annotation_string
);
3166 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3171 c
->prog_data
.total_grf
= v
.grf_used
;
3172 c
->prog_data
.total_scratch
= 0;