2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
47 #include "../glsl/glsl_types.h"
48 #include "../glsl/ir_optimization.h"
49 #include "../glsl/ir_print_visitor.h"
51 static int using_new_fs
= -1;
52 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
55 brw_new_shader(GLcontext
*ctx
, GLuint name
, GLuint type
)
57 struct brw_shader
*shader
;
59 shader
= talloc_zero(NULL
, struct brw_shader
);
61 shader
->base
.Type
= type
;
62 shader
->base
.Name
= name
;
63 _mesa_init_shader(ctx
, &shader
->base
);
69 struct gl_shader_program
*
70 brw_new_shader_program(GLcontext
*ctx
, GLuint name
)
72 struct brw_shader_program
*prog
;
73 prog
= talloc_zero(NULL
, struct brw_shader_program
);
75 prog
->base
.Name
= name
;
76 _mesa_init_shader_program(ctx
, &prog
->base
);
82 brw_compile_shader(GLcontext
*ctx
, struct gl_shader
*shader
)
84 if (!_mesa_ir_compile_shader(ctx
, shader
))
91 brw_link_shader(GLcontext
*ctx
, struct gl_shader_program
*prog
)
93 struct intel_context
*intel
= intel_context(ctx
);
94 if (using_new_fs
== -1)
95 using_new_fs
= getenv("INTEL_NEW_FS") != NULL
;
97 for (unsigned i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
98 struct brw_shader
*shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
100 if (using_new_fs
&& shader
->base
.Type
== GL_FRAGMENT_SHADER
) {
101 void *mem_ctx
= talloc_new(NULL
);
105 talloc_free(shader
->ir
);
106 shader
->ir
= new(shader
) exec_list
;
107 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
109 do_mat_op_to_vec(shader
->ir
);
110 do_mod_to_fract(shader
->ir
);
111 do_div_to_mul_rcp(shader
->ir
);
112 do_sub_to_add_neg(shader
->ir
);
113 do_explog_to_explog2(shader
->ir
);
114 do_lower_texture_projection(shader
->ir
);
115 brw_do_cubemap_normalize(shader
->ir
);
120 brw_do_channel_expressions(shader
->ir
);
121 brw_do_vector_splitting(shader
->ir
);
123 progress
= do_lower_jumps(shader
->ir
, true, true,
124 true, /* main return */
125 false, /* continue */
129 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
131 progress
= lower_noise(shader
->ir
) || progress
;
133 lower_variable_index_to_cond_assign(shader
->ir
,
135 GL_TRUE
, /* output */
137 GL_TRUE
/* uniform */
139 if (intel
->gen
== 6) {
140 progress
= do_if_to_cond_assign(shader
->ir
) || progress
;
144 validate_ir_tree(shader
->ir
);
146 reparent_ir(shader
->ir
, shader
->ir
);
147 talloc_free(mem_ctx
);
151 if (!_mesa_ir_link_shader(ctx
, prog
))
158 type_size(const struct glsl_type
*type
)
160 unsigned int size
, i
;
162 switch (type
->base_type
) {
165 case GLSL_TYPE_FLOAT
:
167 return type
->components();
168 case GLSL_TYPE_ARRAY
:
169 return type_size(type
->fields
.array
) * type
->length
;
170 case GLSL_TYPE_STRUCT
:
172 for (i
= 0; i
< type
->length
; i
++) {
173 size
+= type_size(type
->fields
.structure
[i
].type
);
176 case GLSL_TYPE_SAMPLER
:
177 /* Samplers take up no register space, since they're baked in at
182 assert(!"not reached");
187 static const fs_reg reg_undef
;
188 static const fs_reg
reg_null(ARF
, BRW_ARF_NULL
);
191 fs_visitor::virtual_grf_alloc(int size
)
193 if (virtual_grf_array_size
<= virtual_grf_next
) {
194 if (virtual_grf_array_size
== 0)
195 virtual_grf_array_size
= 16;
197 virtual_grf_array_size
*= 2;
198 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
199 int, virtual_grf_array_size
);
201 /* This slot is always unused. */
202 virtual_grf_sizes
[0] = 0;
204 virtual_grf_sizes
[virtual_grf_next
] = size
;
205 return virtual_grf_next
++;
208 /** Fixed HW reg constructor. */
209 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
213 this->hw_reg
= hw_reg
;
214 this->type
= BRW_REGISTER_TYPE_F
;
218 brw_type_for_base_type(const struct glsl_type
*type
)
220 switch (type
->base_type
) {
221 case GLSL_TYPE_FLOAT
:
222 return BRW_REGISTER_TYPE_F
;
225 return BRW_REGISTER_TYPE_D
;
227 return BRW_REGISTER_TYPE_UD
;
228 case GLSL_TYPE_ARRAY
:
229 case GLSL_TYPE_STRUCT
:
230 /* These should be overridden with the type of the member when
231 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
232 * way to trip up if we don't.
234 return BRW_REGISTER_TYPE_UD
;
236 assert(!"not reached");
237 return BRW_REGISTER_TYPE_F
;
241 /** Automatic reg constructor. */
242 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
247 this->reg
= v
->virtual_grf_alloc(type_size(type
));
248 this->reg_offset
= 0;
249 this->type
= brw_type_for_base_type(type
);
253 fs_visitor::variable_storage(ir_variable
*var
)
255 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
258 /* Our support for uniforms is piggy-backed on the struct
259 * gl_fragment_program, because that's where the values actually
260 * get stored, rather than in some global gl_shader_program uniform
264 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
266 unsigned int offset
= 0;
269 if (type
->is_matrix()) {
270 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
271 type
->vector_elements
,
274 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
275 offset
+= setup_uniform_values(loc
+ offset
, column
);
281 switch (type
->base_type
) {
282 case GLSL_TYPE_FLOAT
:
286 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
287 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
288 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
292 case GLSL_TYPE_STRUCT
:
293 for (unsigned int i
= 0; i
< type
->length
; i
++) {
294 offset
+= setup_uniform_values(loc
+ offset
,
295 type
->fields
.structure
[i
].type
);
299 case GLSL_TYPE_ARRAY
:
300 for (unsigned int i
= 0; i
< type
->length
; i
++) {
301 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
305 case GLSL_TYPE_SAMPLER
:
306 /* The sampler takes up a slot, but we don't use any values from it. */
310 assert(!"not reached");
316 /* Our support for builtin uniforms is even scarier than non-builtin.
317 * It sits on top of the PROG_STATE_VAR parameters that are
318 * automatically updated from GL context state.
321 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
323 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
325 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
326 statevar
= &_mesa_builtin_uniform_desc
[i
];
327 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
331 if (!statevar
->name
) {
333 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
338 if (ir
->type
->is_array()) {
339 array_count
= ir
->type
->length
;
344 for (int a
= 0; a
< array_count
; a
++) {
345 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
346 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
347 int tokens
[STATE_LENGTH
];
349 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
350 if (ir
->type
->is_array()) {
354 /* This state reference has already been setup by ir_to_mesa,
355 * but we'll get the same index back here.
357 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
358 (gl_state_index
*)tokens
);
359 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
361 /* Add each of the unique swizzles of the element as a
362 * parameter. This'll end up matching the expected layout of
363 * the array/matrix/structure we're trying to fill in.
366 for (unsigned int i
= 0; i
< 4; i
++) {
367 int swiz
= GET_SWZ(element
->swizzle
, i
);
368 if (swiz
== last_swiz
)
372 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
379 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
381 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
383 fs_reg neg_y
= this->pixel_y
;
387 if (ir
->pixel_center_integer
) {
388 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
390 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
395 if (ir
->origin_upper_left
&& ir
->pixel_center_integer
) {
396 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
398 fs_reg pixel_y
= this->pixel_y
;
399 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
401 if (!ir
->origin_upper_left
) {
402 pixel_y
.negate
= true;
403 offset
+= c
->key
.drawable_height
- 1.0;
406 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
411 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
412 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
415 /* gl_FragCoord.w: Already set up in emit_interpolation */
416 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
422 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
424 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
425 /* Interpolation is always in floating point regs. */
426 reg
->type
= BRW_REGISTER_TYPE_F
;
429 unsigned int array_elements
;
430 const glsl_type
*type
;
432 if (ir
->type
->is_array()) {
433 array_elements
= ir
->type
->length
;
434 if (array_elements
== 0) {
437 type
= ir
->type
->fields
.array
;
443 int location
= ir
->location
;
444 for (unsigned int i
= 0; i
< array_elements
; i
++) {
445 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
446 if (urb_setup
[location
] == -1) {
447 /* If there's no incoming setup data for this slot, don't
448 * emit interpolation for it.
450 attr
.reg_offset
+= type
->vector_elements
;
455 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
456 struct brw_reg interp
= interp_reg(location
, c
);
457 emit(fs_inst(FS_OPCODE_LINTERP
,
465 if (intel
->gen
< 6) {
466 attr
.reg_offset
-= type
->vector_elements
;
467 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
468 emit(fs_inst(BRW_OPCODE_MUL
,
483 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
485 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
487 /* The frontfacing comes in as a bit in the thread payload. */
488 if (intel
->gen
>= 6) {
489 emit(fs_inst(BRW_OPCODE_ASR
,
491 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
493 emit(fs_inst(BRW_OPCODE_NOT
,
496 emit(fs_inst(BRW_OPCODE_AND
,
501 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
502 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
503 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
506 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
510 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
511 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
518 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src
)
530 assert(!"not reached: bad math opcode");
533 fs_inst
*inst
= emit(fs_inst(opcode
, dst
, src
));
542 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
544 assert(opcode
== FS_OPCODE_POW
);
546 fs_inst
*inst
= emit(fs_inst(opcode
, dst
, src0
, src1
));
555 fs_visitor::visit(ir_variable
*ir
)
559 if (variable_storage(ir
))
562 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
563 this->frag_color
= ir
;
564 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
565 this->frag_data
= ir
;
566 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
567 this->frag_depth
= ir
;
570 if (ir
->mode
== ir_var_in
) {
571 if (!strcmp(ir
->name
, "gl_FragCoord")) {
572 reg
= emit_fragcoord_interpolation(ir
);
573 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
574 reg
= emit_frontfacing_interpolation(ir
);
576 reg
= emit_general_interpolation(ir
);
579 hash_table_insert(this->variable_ht
, reg
, ir
);
583 if (ir
->mode
== ir_var_uniform
) {
584 int param_index
= c
->prog_data
.nr_params
;
586 if (!strncmp(ir
->name
, "gl_", 3)) {
587 setup_builtin_uniform_values(ir
);
589 setup_uniform_values(ir
->location
, ir
->type
);
592 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
596 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
598 hash_table_insert(this->variable_ht
, reg
, ir
);
602 fs_visitor::visit(ir_dereference_variable
*ir
)
604 fs_reg
*reg
= variable_storage(ir
->var
);
609 fs_visitor::visit(ir_dereference_record
*ir
)
611 const glsl_type
*struct_type
= ir
->record
->type
;
613 ir
->record
->accept(this);
615 unsigned int offset
= 0;
616 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
617 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
619 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
621 this->result
.reg_offset
+= offset
;
622 this->result
.type
= brw_type_for_base_type(ir
->type
);
626 fs_visitor::visit(ir_dereference_array
*ir
)
631 ir
->array
->accept(this);
632 index
= ir
->array_index
->as_constant();
634 element_size
= type_size(ir
->type
);
635 this->result
.type
= brw_type_for_base_type(ir
->type
);
638 assert(this->result
.file
== UNIFORM
||
639 (this->result
.file
== GRF
&&
640 this->result
.reg
!= 0));
641 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
643 assert(!"FINISHME: non-constant array element");
648 fs_visitor::visit(ir_expression
*ir
)
650 unsigned int operand
;
655 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
656 ir
->operands
[operand
]->accept(this);
657 if (this->result
.file
== BAD_FILE
) {
659 printf("Failed to get tree for expression operand:\n");
660 ir
->operands
[operand
]->accept(&v
);
663 op
[operand
] = this->result
;
665 /* Matrix expression operands should have been broken down to vector
666 * operations already.
668 assert(!ir
->operands
[operand
]->type
->is_matrix());
669 /* And then those vector operands should have been broken down to scalar.
671 assert(!ir
->operands
[operand
]->type
->is_vector());
674 /* Storage for our result. If our result goes into an assignment, it will
675 * just get copy-propagated out, so no worries.
677 this->result
= fs_reg(this, ir
->type
);
679 switch (ir
->operation
) {
680 case ir_unop_logic_not
:
681 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], fs_reg(-1)));
684 op
[0].negate
= !op
[0].negate
;
685 this->result
= op
[0];
689 this->result
= op
[0];
692 temp
= fs_reg(this, ir
->type
);
694 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
696 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
697 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
698 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
699 inst
->predicated
= true;
701 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
702 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
703 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
704 inst
->predicated
= true;
708 emit_math(FS_OPCODE_RCP
, this->result
, op
[0]);
712 emit_math(FS_OPCODE_EXP2
, this->result
, op
[0]);
715 emit_math(FS_OPCODE_LOG2
, this->result
, op
[0]);
719 assert(!"not reached: should be handled by ir_explog_to_explog2");
722 emit_math(FS_OPCODE_SIN
, this->result
, op
[0]);
725 emit_math(FS_OPCODE_COS
, this->result
, op
[0]);
729 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
732 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
736 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
739 assert(!"not reached: should be handled by ir_sub_to_add_neg");
743 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
746 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
749 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
753 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
754 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
755 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
757 case ir_binop_greater
:
758 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
759 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
760 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
762 case ir_binop_lequal
:
763 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
764 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
765 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
767 case ir_binop_gequal
:
768 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
769 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
770 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
773 case ir_binop_all_equal
: /* same as nequal for scalars */
774 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
775 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
776 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
778 case ir_binop_nequal
:
779 case ir_binop_any_nequal
: /* same as nequal for scalars */
780 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
781 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
782 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
785 case ir_binop_logic_xor
:
786 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
789 case ir_binop_logic_or
:
790 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
793 case ir_binop_logic_and
:
794 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
800 assert(!"not reached: should be handled by brw_fs_channel_expressions");
804 assert(!"not reached: should be handled by lower_noise");
808 emit_math(FS_OPCODE_SQRT
, this->result
, op
[0]);
812 emit_math(FS_OPCODE_RSQ
, this->result
, op
[0]);
818 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
821 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
825 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
826 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
829 emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
832 op
[0].negate
= ~op
[0].negate
;
833 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
834 this->result
.negate
= true;
837 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
840 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
844 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
845 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
847 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
848 inst
->predicated
= true;
851 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
852 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
854 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
855 inst
->predicated
= true;
859 emit_math(FS_OPCODE_POW
, this->result
, op
[0], op
[1]);
862 case ir_unop_bit_not
:
864 case ir_binop_lshift
:
865 case ir_binop_rshift
:
866 case ir_binop_bit_and
:
867 case ir_binop_bit_xor
:
868 case ir_binop_bit_or
:
869 assert(!"GLSL 1.30 features unsupported");
875 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
876 const glsl_type
*type
, bool predicated
)
878 switch (type
->base_type
) {
879 case GLSL_TYPE_FLOAT
:
883 for (unsigned int i
= 0; i
< type
->components(); i
++) {
884 l
.type
= brw_type_for_base_type(type
);
885 r
.type
= brw_type_for_base_type(type
);
887 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
888 inst
->predicated
= predicated
;
894 case GLSL_TYPE_ARRAY
:
895 for (unsigned int i
= 0; i
< type
->length
; i
++) {
896 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
899 case GLSL_TYPE_STRUCT
:
900 for (unsigned int i
= 0; i
< type
->length
; i
++) {
901 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
906 case GLSL_TYPE_SAMPLER
:
910 assert(!"not reached");
916 fs_visitor::visit(ir_assignment
*ir
)
921 /* FINISHME: arrays on the lhs */
922 ir
->lhs
->accept(this);
925 ir
->rhs
->accept(this);
928 assert(l
.file
!= BAD_FILE
);
929 assert(r
.file
!= BAD_FILE
);
932 /* Get the condition bool into the predicate. */
933 ir
->condition
->accept(this);
934 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, this->result
, fs_reg(0)));
935 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
938 if (ir
->lhs
->type
->is_scalar() ||
939 ir
->lhs
->type
->is_vector()) {
940 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
941 if (ir
->write_mask
& (1 << i
)) {
942 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
944 inst
->predicated
= true;
950 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
955 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
965 if (ir
->shadow_comparitor
) {
966 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
967 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
969 coordinate
.reg_offset
++;
971 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
974 if (ir
->op
== ir_tex
) {
975 /* There's no plain shadow compare message, so we use shadow
976 * compare with a bias of 0.0.
978 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
981 } else if (ir
->op
== ir_txb
) {
982 ir
->lod_info
.bias
->accept(this);
983 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
987 assert(ir
->op
== ir_txl
);
988 ir
->lod_info
.lod
->accept(this);
989 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
994 ir
->shadow_comparitor
->accept(this);
995 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
997 } else if (ir
->op
== ir_tex
) {
998 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
999 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1001 coordinate
.reg_offset
++;
1003 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1006 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1007 * instructions. We'll need to do SIMD16 here.
1009 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1011 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
* 2;) {
1012 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2),
1014 coordinate
.reg_offset
++;
1017 /* lod/bias appears after u/v/r. */
1020 if (ir
->op
== ir_txb
) {
1021 ir
->lod_info
.bias
->accept(this);
1022 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1026 ir
->lod_info
.lod
->accept(this);
1027 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1032 /* The unused upper half. */
1035 /* Now, since we're doing simd16, the return is 2 interleaved
1036 * vec4s where the odd-indexed ones are junk. We'll need to move
1037 * this weirdness around to the expected layout.
1041 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1043 dst
.type
= BRW_REGISTER_TYPE_F
;
1046 fs_inst
*inst
= NULL
;
1049 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1052 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1055 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1059 assert(!"GLSL 1.30 features unsupported");
1062 inst
->base_mrf
= base_mrf
;
1066 for (int i
= 0; i
< 4; i
++) {
1067 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1068 orig_dst
.reg_offset
++;
1069 dst
.reg_offset
+= 2;
1077 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1079 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1080 * optional parameters like shadow comparitor or LOD bias. If
1081 * optional parameters aren't present, those base slots are
1082 * optional and don't need to be included in the message.
1084 * We don't fill in the unnecessary slots regardless, which may
1085 * look surprising in the disassembly.
1087 int mlen
= 1; /* g0 header always present. */
1090 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1091 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1093 coordinate
.reg_offset
++;
1095 mlen
+= ir
->coordinate
->type
->vector_elements
;
1097 if (ir
->shadow_comparitor
) {
1098 mlen
= MAX2(mlen
, 5);
1100 ir
->shadow_comparitor
->accept(this);
1101 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1105 fs_inst
*inst
= NULL
;
1108 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1111 ir
->lod_info
.bias
->accept(this);
1112 mlen
= MAX2(mlen
, 5);
1113 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1116 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1119 ir
->lod_info
.lod
->accept(this);
1120 mlen
= MAX2(mlen
, 5);
1121 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1124 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1128 assert(!"GLSL 1.30 features unsupported");
1131 inst
->base_mrf
= base_mrf
;
1138 fs_visitor::visit(ir_texture
*ir
)
1140 fs_inst
*inst
= NULL
;
1142 ir
->coordinate
->accept(this);
1143 fs_reg coordinate
= this->result
;
1145 /* Should be lowered by do_lower_texture_projection */
1146 assert(!ir
->projector
);
1148 /* Writemasking doesn't eliminate channels on SIMD8 texture
1149 * samples, so don't worry about them.
1151 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1153 if (intel
->gen
< 5) {
1154 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1156 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1160 _mesa_get_sampler_uniform_value(ir
->sampler
,
1161 ctx
->Shader
.CurrentProgram
,
1162 &brw
->fragment_program
->Base
);
1163 inst
->sampler
= c
->fp
->program
.Base
.SamplerUnits
[inst
->sampler
];
1167 if (ir
->shadow_comparitor
)
1168 inst
->shadow_compare
= true;
1170 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1171 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1173 for (int i
= 0; i
< 4; i
++) {
1174 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1175 fs_reg l
= swizzle_dst
;
1178 if (swiz
== SWIZZLE_ZERO
) {
1179 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1180 } else if (swiz
== SWIZZLE_ONE
) {
1181 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1184 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1185 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1188 this->result
= swizzle_dst
;
1193 fs_visitor::visit(ir_swizzle
*ir
)
1195 ir
->val
->accept(this);
1196 fs_reg val
= this->result
;
1198 if (ir
->type
->vector_elements
== 1) {
1199 this->result
.reg_offset
+= ir
->mask
.x
;
1203 fs_reg result
= fs_reg(this, ir
->type
);
1204 this->result
= result
;
1206 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1207 fs_reg channel
= val
;
1225 channel
.reg_offset
+= swiz
;
1226 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1227 result
.reg_offset
++;
1232 fs_visitor::visit(ir_discard
*ir
)
1234 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1236 assert(ir
->condition
== NULL
); /* FINISHME */
1238 emit(fs_inst(FS_OPCODE_DISCARD_NOT
, temp
, reg_null
));
1239 emit(fs_inst(FS_OPCODE_DISCARD_AND
, reg_null
, temp
));
1240 kill_emitted
= true;
1244 fs_visitor::visit(ir_constant
*ir
)
1246 fs_reg
reg(this, ir
->type
);
1249 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1250 switch (ir
->type
->base_type
) {
1251 case GLSL_TYPE_FLOAT
:
1252 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
1254 case GLSL_TYPE_UINT
:
1255 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1258 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1260 case GLSL_TYPE_BOOL
:
1261 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1264 assert(!"Non-float/uint/int/bool constant");
1271 fs_visitor::visit(ir_if
*ir
)
1275 /* Don't point the annotation at the if statement, because then it plus
1276 * the then and else blocks get printed.
1278 this->base_ir
= ir
->condition
;
1280 /* Generate the condition into the condition code. */
1281 ir
->condition
->accept(this);
1282 inst
= emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(brw_null_reg()), this->result
));
1283 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1285 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1286 inst
->predicated
= true;
1288 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1289 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1295 if (!ir
->else_instructions
.is_empty()) {
1296 emit(fs_inst(BRW_OPCODE_ELSE
));
1298 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1299 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1306 emit(fs_inst(BRW_OPCODE_ENDIF
));
1310 fs_visitor::visit(ir_loop
*ir
)
1312 fs_reg counter
= reg_undef
;
1315 this->base_ir
= ir
->counter
;
1316 ir
->counter
->accept(this);
1317 counter
= *(variable_storage(ir
->counter
));
1320 this->base_ir
= ir
->from
;
1321 ir
->from
->accept(this);
1323 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1327 emit(fs_inst(BRW_OPCODE_DO
));
1330 this->base_ir
= ir
->to
;
1331 ir
->to
->accept(this);
1333 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
,
1334 counter
, this->result
));
1336 case ir_binop_equal
:
1337 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1339 case ir_binop_nequal
:
1340 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1342 case ir_binop_gequal
:
1343 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1345 case ir_binop_lequal
:
1346 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1348 case ir_binop_greater
:
1349 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1352 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1355 assert(!"not reached: unknown loop condition");
1360 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1361 inst
->predicated
= true;
1364 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1365 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1371 if (ir
->increment
) {
1372 this->base_ir
= ir
->increment
;
1373 ir
->increment
->accept(this);
1374 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1377 emit(fs_inst(BRW_OPCODE_WHILE
));
1381 fs_visitor::visit(ir_loop_jump
*ir
)
1384 case ir_loop_jump::jump_break
:
1385 emit(fs_inst(BRW_OPCODE_BREAK
));
1387 case ir_loop_jump::jump_continue
:
1388 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1394 fs_visitor::visit(ir_call
*ir
)
1396 assert(!"FINISHME");
1400 fs_visitor::visit(ir_return
*ir
)
1402 assert(!"FINISHME");
1406 fs_visitor::visit(ir_function
*ir
)
1408 /* Ignore function bodies other than main() -- we shouldn't see calls to
1409 * them since they should all be inlined before we get to ir_to_mesa.
1411 if (strcmp(ir
->name
, "main") == 0) {
1412 const ir_function_signature
*sig
;
1415 sig
= ir
->matching_signature(&empty
);
1419 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1420 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1429 fs_visitor::visit(ir_function_signature
*ir
)
1431 assert(!"not reached");
1436 fs_visitor::emit(fs_inst inst
)
1438 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1441 list_inst
->annotation
= this->current_annotation
;
1442 list_inst
->ir
= this->base_ir
;
1444 this->instructions
.push_tail(list_inst
);
1449 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1451 fs_visitor::emit_dummy_fs()
1453 /* Everyone's favorite color. */
1454 emit(fs_inst(BRW_OPCODE_MOV
,
1457 emit(fs_inst(BRW_OPCODE_MOV
,
1460 emit(fs_inst(BRW_OPCODE_MOV
,
1463 emit(fs_inst(BRW_OPCODE_MOV
,
1468 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1471 write
->base_mrf
= 0;
1474 /* The register location here is relative to the start of the URB
1475 * data. It will get adjusted to be a real location before
1476 * generate_code() time.
1479 fs_visitor::interp_reg(int location
, int channel
)
1481 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1482 int stride
= (channel
& 1) * 4;
1484 assert(urb_setup
[location
] != -1);
1486 return brw_vec1_grf(regnr
, stride
);
1489 /** Emits the interpolation for the varying inputs. */
1491 fs_visitor::emit_interpolation_setup_gen4()
1493 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1495 this->current_annotation
= "compute pixel centers";
1496 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1497 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1498 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1499 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1500 emit(fs_inst(BRW_OPCODE_ADD
,
1502 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1503 fs_reg(brw_imm_v(0x10101010))));
1504 emit(fs_inst(BRW_OPCODE_ADD
,
1506 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1507 fs_reg(brw_imm_v(0x11001100))));
1509 this->current_annotation
= "compute pixel deltas from v0";
1511 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1512 this->delta_y
= this->delta_x
;
1513 this->delta_y
.reg_offset
++;
1515 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1516 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1518 emit(fs_inst(BRW_OPCODE_ADD
,
1521 fs_reg(negate(brw_vec1_grf(1, 0)))));
1522 emit(fs_inst(BRW_OPCODE_ADD
,
1525 fs_reg(negate(brw_vec1_grf(1, 1)))));
1527 this->current_annotation
= "compute pos.w and 1/pos.w";
1528 /* Compute wpos.w. It's always in our setup, since it's needed to
1529 * interpolate the other attributes.
1531 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1532 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1533 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1534 /* Compute the pixel 1/W value from wpos.w. */
1535 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1536 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1537 this->current_annotation
= NULL
;
1540 /** Emits the interpolation for the varying inputs. */
1542 fs_visitor::emit_interpolation_setup_gen6()
1544 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1546 /* If the pixel centers end up used, the setup is the same as for gen4. */
1547 this->current_annotation
= "compute pixel centers";
1548 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1549 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1550 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1551 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1552 emit(fs_inst(BRW_OPCODE_ADD
,
1554 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1555 fs_reg(brw_imm_v(0x10101010))));
1556 emit(fs_inst(BRW_OPCODE_ADD
,
1558 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1559 fs_reg(brw_imm_v(0x11001100))));
1561 this->current_annotation
= "compute 1/pos.w";
1562 this->wpos_w
= fs_reg(brw_vec8_grf(c
->key
.source_w_reg
, 0));
1563 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1564 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1566 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1567 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1569 this->current_annotation
= NULL
;
1573 fs_visitor::emit_fb_writes()
1575 this->current_annotation
= "FB write header";
1576 GLboolean header_present
= GL_TRUE
;
1579 if (intel
->gen
>= 6 &&
1580 !this->kill_emitted
&&
1581 c
->key
.nr_color_regions
== 1) {
1582 header_present
= false;
1585 if (header_present
) {
1590 if (c
->key
.aa_dest_stencil_reg
) {
1591 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1592 fs_reg(brw_vec8_grf(c
->key
.aa_dest_stencil_reg
, 0))));
1595 /* Reserve space for color. It'll be filled in per MRT below. */
1599 if (c
->key
.source_depth_to_render_target
) {
1600 if (c
->key
.computes_depth
) {
1601 /* Hand over gl_FragDepth. */
1602 assert(this->frag_depth
);
1603 fs_reg depth
= *(variable_storage(this->frag_depth
));
1605 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
1607 /* Pass through the payload depth. */
1608 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1609 fs_reg(brw_vec8_grf(c
->key
.source_depth_reg
, 0))));
1613 if (c
->key
.dest_depth_reg
) {
1614 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1615 fs_reg(brw_vec8_grf(c
->key
.dest_depth_reg
, 0))));
1618 fs_reg color
= reg_undef
;
1619 if (this->frag_color
)
1620 color
= *(variable_storage(this->frag_color
));
1621 else if (this->frag_data
)
1622 color
= *(variable_storage(this->frag_data
));
1624 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1625 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1626 "FB write target %d",
1628 if (this->frag_color
|| this->frag_data
) {
1629 for (int i
= 0; i
< 4; i
++) {
1630 emit(fs_inst(BRW_OPCODE_MOV
,
1631 fs_reg(MRF
, color_mrf
+ i
),
1637 if (this->frag_color
)
1638 color
.reg_offset
-= 4;
1640 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1641 reg_undef
, reg_undef
));
1642 inst
->target
= target
;
1645 if (target
== c
->key
.nr_color_regions
- 1)
1647 inst
->header_present
= header_present
;
1650 if (c
->key
.nr_color_regions
== 0) {
1651 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1652 reg_undef
, reg_undef
));
1656 inst
->header_present
= header_present
;
1659 this->current_annotation
= NULL
;
1663 fs_visitor::generate_fb_write(fs_inst
*inst
)
1665 GLboolean eot
= inst
->eot
;
1666 struct brw_reg implied_header
;
1668 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1671 brw_push_insn_state(p
);
1672 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1673 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1675 if (inst
->header_present
) {
1676 if (intel
->gen
>= 6) {
1678 brw_message_reg(inst
->base_mrf
),
1679 brw_vec8_grf(0, 0));
1680 implied_header
= brw_null_reg();
1682 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1686 brw_message_reg(inst
->base_mrf
+ 1),
1687 brw_vec8_grf(1, 0));
1689 implied_header
= brw_null_reg();
1692 brw_pop_insn_state(p
);
1695 8, /* dispatch_width */
1696 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
1706 fs_visitor::generate_linterp(fs_inst
*inst
,
1707 struct brw_reg dst
, struct brw_reg
*src
)
1709 struct brw_reg delta_x
= src
[0];
1710 struct brw_reg delta_y
= src
[1];
1711 struct brw_reg interp
= src
[2];
1714 delta_y
.nr
== delta_x
.nr
+ 1 &&
1715 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
1716 brw_PLN(p
, dst
, interp
, delta_x
);
1718 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
1719 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
1724 fs_visitor::generate_math(fs_inst
*inst
,
1725 struct brw_reg dst
, struct brw_reg
*src
)
1729 switch (inst
->opcode
) {
1731 op
= BRW_MATH_FUNCTION_INV
;
1734 op
= BRW_MATH_FUNCTION_RSQ
;
1736 case FS_OPCODE_SQRT
:
1737 op
= BRW_MATH_FUNCTION_SQRT
;
1739 case FS_OPCODE_EXP2
:
1740 op
= BRW_MATH_FUNCTION_EXP
;
1742 case FS_OPCODE_LOG2
:
1743 op
= BRW_MATH_FUNCTION_LOG
;
1746 op
= BRW_MATH_FUNCTION_POW
;
1749 op
= BRW_MATH_FUNCTION_SIN
;
1752 op
= BRW_MATH_FUNCTION_COS
;
1755 assert(!"not reached: unknown math function");
1760 assert(inst
->mlen
>= 1);
1762 if (inst
->opcode
== FS_OPCODE_POW
) {
1763 brw_MOV(p
, brw_message_reg(inst
->base_mrf
+ 1), src
[1]);
1768 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
1769 BRW_MATH_SATURATE_NONE
,
1770 inst
->base_mrf
, src
[0],
1771 BRW_MATH_DATA_VECTOR
,
1772 BRW_MATH_PRECISION_FULL
);
1776 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
)
1780 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1782 if (intel
->gen
>= 5) {
1783 switch (inst
->opcode
) {
1785 if (inst
->shadow_compare
) {
1786 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
1788 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
1792 if (inst
->shadow_compare
) {
1793 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
1795 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
1800 switch (inst
->opcode
) {
1802 /* Note that G45 and older determines shadow compare and dispatch width
1803 * from message length for most messages.
1805 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
1806 if (inst
->shadow_compare
) {
1807 assert(inst
->mlen
== 5);
1809 assert(inst
->mlen
<= 6);
1813 if (inst
->shadow_compare
) {
1814 assert(inst
->mlen
== 5);
1815 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
1817 assert(inst
->mlen
== 8);
1818 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1819 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1824 assert(msg_type
!= -1);
1826 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
1832 retype(dst
, BRW_REGISTER_TYPE_UW
),
1834 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
1835 SURF_INDEX_TEXTURE(inst
->sampler
),
1847 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1850 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1852 * and we're trying to produce:
1855 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1856 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1857 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1858 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1859 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1860 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1861 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1862 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1864 * and add another set of two more subspans if in 16-pixel dispatch mode.
1866 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1867 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1868 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
1869 * between each other. We could probably do it like ddx and swizzle the right
1870 * order later, but bail for now and just produce
1871 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
1874 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
1876 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
1877 BRW_REGISTER_TYPE_F
,
1878 BRW_VERTICAL_STRIDE_2
,
1880 BRW_HORIZONTAL_STRIDE_0
,
1881 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1882 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
1883 BRW_REGISTER_TYPE_F
,
1884 BRW_VERTICAL_STRIDE_2
,
1886 BRW_HORIZONTAL_STRIDE_0
,
1887 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1888 brw_ADD(p
, dst
, src0
, negate(src1
));
1892 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
1894 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
1895 BRW_REGISTER_TYPE_F
,
1896 BRW_VERTICAL_STRIDE_4
,
1898 BRW_HORIZONTAL_STRIDE_0
,
1899 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1900 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
1901 BRW_REGISTER_TYPE_F
,
1902 BRW_VERTICAL_STRIDE_4
,
1904 BRW_HORIZONTAL_STRIDE_0
,
1905 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1906 brw_ADD(p
, dst
, src0
, negate(src1
));
1910 fs_visitor::generate_discard_not(fs_inst
*inst
, struct brw_reg mask
)
1912 brw_push_insn_state(p
);
1913 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1914 brw_NOT(p
, mask
, brw_mask_reg(1)); /* IMASK */
1915 brw_pop_insn_state(p
);
1919 fs_visitor::generate_discard_and(fs_inst
*inst
, struct brw_reg mask
)
1921 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1922 mask
= brw_uw1_reg(mask
.file
, mask
.nr
, 0);
1924 brw_push_insn_state(p
);
1925 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1926 brw_AND(p
, g0
, mask
, g0
);
1927 brw_pop_insn_state(p
);
1931 fs_visitor::assign_curb_setup()
1933 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
1934 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
1936 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1937 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1938 fs_inst
*inst
= (fs_inst
*)iter
.get();
1940 for (unsigned int i
= 0; i
< 3; i
++) {
1941 if (inst
->src
[i
].file
== UNIFORM
) {
1942 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
1943 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
1947 inst
->src
[i
].file
= FIXED_HW_REG
;
1948 inst
->src
[i
].fixed_hw_reg
= brw_reg
;
1955 fs_visitor::calculate_urb_setup()
1957 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
1962 /* Figure out where each of the incoming setup attributes lands. */
1963 if (intel
->gen
>= 6) {
1964 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
1965 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
1966 urb_setup
[i
] = urb_next
++;
1970 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1971 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
1972 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
1975 if (i
>= VERT_RESULT_VAR0
)
1976 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
1977 else if (i
<= VERT_RESULT_TEX7
)
1983 urb_setup
[fp_index
] = urb_next
++;
1988 /* Each attribute is 4 setup channels, each of which is half a reg. */
1989 c
->prog_data
.urb_read_length
= urb_next
* 2;
1993 fs_visitor::assign_urb_setup()
1995 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
1997 /* Offset all the urb_setup[] index by the actual position of the
1998 * setup regs, now that the location of the constants has been chosen.
2000 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2001 fs_inst
*inst
= (fs_inst
*)iter
.get();
2003 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
2006 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2008 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2011 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2015 assign_reg(int *reg_hw_locations
, fs_reg
*reg
)
2017 if (reg
->file
== GRF
&& reg
->reg
!= 0) {
2018 reg
->hw_reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
;
2024 fs_visitor::assign_regs_trivial()
2027 int hw_reg_mapping
[this->virtual_grf_next
];
2030 hw_reg_mapping
[0] = 0;
2031 hw_reg_mapping
[1] = this->first_non_payload_grf
;
2032 for (i
= 2; i
< this->virtual_grf_next
; i
++) {
2033 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
2034 this->virtual_grf_sizes
[i
- 1]);
2036 last_grf
= hw_reg_mapping
[i
- 1] + this->virtual_grf_sizes
[i
- 1];
2038 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2039 fs_inst
*inst
= (fs_inst
*)iter
.get();
2041 assign_reg(hw_reg_mapping
, &inst
->dst
);
2042 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2043 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2046 this->grf_used
= last_grf
+ 1;
2050 fs_visitor::assign_regs()
2053 int hw_reg_mapping
[this->virtual_grf_next
+ 1];
2054 int base_reg_count
= BRW_MAX_GRF
- this->first_non_payload_grf
;
2055 int class_sizes
[base_reg_count
];
2056 int class_count
= 0;
2057 int aligned_pair_class
= -1;
2059 /* Set up the register classes.
2061 * The base registers store a scalar value. For texture samples,
2062 * we get virtual GRFs composed of 4 contiguous hw register. For
2063 * structures and arrays, we store them as contiguous larger things
2064 * than that, though we should be able to do better most of the
2067 class_sizes
[class_count
++] = 1;
2068 if (brw
->has_pln
&& intel
->gen
< 6) {
2069 /* Always set up the (unaligned) pairs for gen5, so we can find
2070 * them for making the aligned pair class.
2072 class_sizes
[class_count
++] = 2;
2074 for (int r
= 1; r
< this->virtual_grf_next
; r
++) {
2077 for (i
= 0; i
< class_count
; i
++) {
2078 if (class_sizes
[i
] == this->virtual_grf_sizes
[r
])
2081 if (i
== class_count
) {
2082 if (this->virtual_grf_sizes
[r
] >= base_reg_count
) {
2083 fprintf(stderr
, "Object too large to register allocate.\n");
2087 class_sizes
[class_count
++] = this->virtual_grf_sizes
[r
];
2091 int ra_reg_count
= 0;
2092 int class_base_reg
[class_count
];
2093 int class_reg_count
[class_count
];
2094 int classes
[class_count
+ 1];
2096 for (int i
= 0; i
< class_count
; i
++) {
2097 class_base_reg
[i
] = ra_reg_count
;
2098 class_reg_count
[i
] = base_reg_count
- (class_sizes
[i
] - 1);
2099 ra_reg_count
+= class_reg_count
[i
];
2102 struct ra_regs
*regs
= ra_alloc_reg_set(ra_reg_count
);
2103 for (int i
= 0; i
< class_count
; i
++) {
2104 classes
[i
] = ra_alloc_reg_class(regs
);
2106 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2107 ra_class_add_reg(regs
, classes
[i
], class_base_reg
[i
] + i_r
);
2110 /* Add conflicts between our contiguous registers aliasing
2111 * base regs and other register classes' contiguous registers
2112 * that alias base regs, or the base regs themselves for classes[0].
2114 for (int c
= 0; c
<= i
; c
++) {
2115 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2116 for (int c_r
= MAX2(0, i_r
- (class_sizes
[c
] - 1));
2117 c_r
< MIN2(class_reg_count
[c
], i_r
+ class_sizes
[i
]);
2121 printf("%d/%d conflicts %d/%d\n",
2122 class_sizes
[i
], this->first_non_payload_grf
+ i_r
,
2123 class_sizes
[c
], this->first_non_payload_grf
+ c_r
);
2126 ra_add_reg_conflict(regs
,
2127 class_base_reg
[i
] + i_r
,
2128 class_base_reg
[c
] + c_r
);
2134 /* Add a special class for aligned pairs, which we'll put delta_x/y
2135 * in on gen5 so that we can do PLN.
2137 if (brw
->has_pln
&& intel
->gen
< 6) {
2138 int reg_count
= (base_reg_count
- 1) / 2;
2139 int unaligned_pair_class
= 1;
2140 assert(class_sizes
[unaligned_pair_class
] == 2);
2142 aligned_pair_class
= class_count
;
2143 classes
[aligned_pair_class
] = ra_alloc_reg_class(regs
);
2144 class_base_reg
[aligned_pair_class
] = 0;
2145 class_reg_count
[aligned_pair_class
] = 0;
2146 int start
= (this->first_non_payload_grf
& 1) ? 1 : 0;
2148 for (int i
= 0; i
< reg_count
; i
++) {
2149 ra_class_add_reg(regs
, classes
[aligned_pair_class
],
2150 class_base_reg
[unaligned_pair_class
] + i
* 2 + start
);
2155 ra_set_finalize(regs
);
2157 struct ra_graph
*g
= ra_alloc_interference_graph(regs
,
2158 this->virtual_grf_next
);
2159 /* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1
2162 ra_set_node_class(g
, 0, classes
[0]);
2164 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2165 for (int c
= 0; c
< class_count
; c
++) {
2166 if (class_sizes
[c
] == this->virtual_grf_sizes
[i
]) {
2167 if (aligned_pair_class
>= 0 &&
2168 this->delta_x
.reg
== i
) {
2169 ra_set_node_class(g
, i
, classes
[aligned_pair_class
]);
2171 ra_set_node_class(g
, i
, classes
[c
]);
2177 for (int j
= 1; j
< i
; j
++) {
2178 if (virtual_grf_interferes(i
, j
)) {
2179 ra_add_node_interference(g
, i
, j
);
2184 /* FINISHME: Handle spilling */
2185 if (!ra_allocate_no_spills(g
)) {
2186 fprintf(stderr
, "Failed to allocate registers.\n");
2191 /* Get the chosen virtual registers for each node, and map virtual
2192 * regs in the register classes back down to real hardware reg
2195 hw_reg_mapping
[0] = 0; /* unused */
2196 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2197 int reg
= ra_get_node_reg(g
, i
);
2200 for (int c
= 0; c
< class_count
; c
++) {
2201 if (reg
>= class_base_reg
[c
] &&
2202 reg
< class_base_reg
[c
] + class_reg_count
[c
]) {
2203 hw_reg
= reg
- class_base_reg
[c
];
2208 assert(hw_reg
!= -1);
2209 hw_reg_mapping
[i
] = this->first_non_payload_grf
+ hw_reg
;
2210 last_grf
= MAX2(last_grf
,
2211 hw_reg_mapping
[i
] + this->virtual_grf_sizes
[i
] - 1);
2214 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2215 fs_inst
*inst
= (fs_inst
*)iter
.get();
2217 assign_reg(hw_reg_mapping
, &inst
->dst
);
2218 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2219 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2222 this->grf_used
= last_grf
+ 1;
2229 fs_visitor::calculate_live_intervals()
2231 int num_vars
= this->virtual_grf_next
;
2232 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2233 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2237 for (int i
= 0; i
< num_vars
; i
++) {
2243 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2244 fs_inst
*inst
= (fs_inst
*)iter
.get();
2246 if (inst
->opcode
== BRW_OPCODE_DO
) {
2247 if (loop_depth
++ == 0)
2249 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2252 if (loop_depth
== 0) {
2255 * Patches up any vars marked for use within the loop as
2256 * live until the end. This is conservative, as there
2257 * will often be variables defined and used inside the
2258 * loop but dead at the end of the loop body.
2260 for (int i
= 0; i
< num_vars
; i
++) {
2261 if (use
[i
] == loop_start
) {
2272 for (unsigned int i
= 0; i
< 3; i
++) {
2273 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2274 use
[inst
->src
[i
].reg
] = MAX2(use
[inst
->src
[i
].reg
], eip
);
2277 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2278 def
[inst
->dst
.reg
] = MIN2(def
[inst
->dst
.reg
], eip
);
2285 talloc_free(this->virtual_grf_def
);
2286 talloc_free(this->virtual_grf_use
);
2287 this->virtual_grf_def
= def
;
2288 this->virtual_grf_use
= use
;
2292 * Attempts to move immediate constants into the immediate
2293 * constant slot of following instructions.
2295 * Immediate constants are a bit tricky -- they have to be in the last
2296 * operand slot, you can't do abs/negate on them,
2300 fs_visitor::propagate_constants()
2302 bool progress
= false;
2304 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2305 fs_inst
*inst
= (fs_inst
*)iter
.get();
2307 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2309 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2310 inst
->dst
.type
!= inst
->src
[0].type
)
2313 /* Don't bother with cases where we should have had the
2314 * operation on the constant folded in GLSL already.
2319 /* Found a move of a constant to a GRF. Find anything else using the GRF
2320 * before it's written, and replace it with the constant if we can.
2322 exec_list_iterator scan_iter
= iter
;
2324 for (; scan_iter
.has_next(); scan_iter
.next()) {
2325 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2327 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2328 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2329 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2330 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2334 for (int i
= 2; i
>= 0; i
--) {
2335 if (scan_inst
->src
[i
].file
!= GRF
||
2336 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2337 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2340 /* Don't bother with cases where we should have had the
2341 * operation on the constant folded in GLSL already.
2343 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2346 switch (scan_inst
->opcode
) {
2347 case BRW_OPCODE_MOV
:
2348 scan_inst
->src
[i
] = inst
->src
[0];
2352 case BRW_OPCODE_MUL
:
2353 case BRW_OPCODE_ADD
:
2355 scan_inst
->src
[i
] = inst
->src
[0];
2357 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2358 /* Fit this constant in by commuting the operands */
2359 scan_inst
->src
[0] = scan_inst
->src
[1];
2360 scan_inst
->src
[1] = inst
->src
[0];
2363 case BRW_OPCODE_CMP
:
2365 scan_inst
->src
[i
] = inst
->src
[0];
2371 if (scan_inst
->dst
.file
== GRF
&&
2372 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2373 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2374 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2383 * Must be called after calculate_live_intervales() to remove unused
2384 * writes to registers -- register allocation will fail otherwise
2385 * because something deffed but not used won't be considered to
2386 * interfere with other regs.
2389 fs_visitor::dead_code_eliminate()
2391 bool progress
= false;
2392 int num_vars
= this->virtual_grf_next
;
2393 bool dead
[num_vars
];
2395 for (int i
= 0; i
< num_vars
; i
++) {
2396 dead
[i
] = this->virtual_grf_def
[i
] >= this->virtual_grf_use
[i
];
2399 /* Mark off its interval so it won't interfere with anything. */
2400 this->virtual_grf_def
[i
] = -1;
2401 this->virtual_grf_use
[i
] = -1;
2405 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2406 fs_inst
*inst
= (fs_inst
*)iter
.get();
2408 if (inst
->dst
.file
== GRF
&& dead
[inst
->dst
.reg
]) {
2418 fs_visitor::register_coalesce()
2420 bool progress
= false;
2422 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2423 fs_inst
*inst
= (fs_inst
*)iter
.get();
2425 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2428 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= GRF
||
2429 inst
->dst
.type
!= inst
->src
[0].type
)
2432 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
2433 * them: check for no writes to either one until the exit of the
2436 bool interfered
= false;
2437 exec_list_iterator scan_iter
= iter
;
2439 for (; scan_iter
.has_next(); scan_iter
.next()) {
2440 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2442 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2443 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2444 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2450 if (scan_inst
->dst
.file
== GRF
) {
2451 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2452 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2453 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2457 if (scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
2458 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
2459 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2469 /* Rewrite the later usage to point at the source of the move to
2472 for (exec_list_iterator scan_iter
= iter
; scan_iter
.has_next();
2474 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2476 for (int i
= 0; i
< 3; i
++) {
2477 if (scan_inst
->src
[i
].file
== GRF
&&
2478 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
2479 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
2480 scan_inst
->src
[i
].reg
= inst
->src
[0].reg
;
2481 scan_inst
->src
[i
].reg_offset
= inst
->src
[0].reg_offset
;
2482 scan_inst
->src
[i
].abs
|= inst
->src
[0].abs
;
2483 scan_inst
->src
[i
].negate
^= inst
->src
[0].negate
;
2497 fs_visitor::compute_to_mrf()
2499 bool progress
= false;
2502 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2503 fs_inst
*inst
= (fs_inst
*)iter
.get();
2508 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2510 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2511 inst
->dst
.type
!= inst
->src
[0].type
||
2512 inst
->src
[0].abs
|| inst
->src
[0].negate
)
2515 /* Can't compute-to-MRF this GRF if someone else was going to
2518 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
2521 /* Found a move of a GRF to a MRF. Let's see if we can go
2522 * rewrite the thing that made this GRF to write into the MRF.
2526 for (scan_inst
= (fs_inst
*)inst
->prev
;
2527 scan_inst
->prev
!= NULL
;
2528 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2529 /* We don't handle flow control here. Most computation of
2530 * values that end up in MRFs are shortly before the MRF
2533 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2534 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2535 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2539 /* You can't read from an MRF, so if someone else reads our
2540 * MRF's source GRF that we wanted to rewrite, that stops us.
2542 bool interfered
= false;
2543 for (int i
= 0; i
< 3; i
++) {
2544 if (scan_inst
->src
[i
].file
== GRF
&&
2545 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2546 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2553 if (scan_inst
->dst
.file
== MRF
&&
2554 scan_inst
->dst
.hw_reg
== inst
->dst
.hw_reg
) {
2555 /* Somebody else wrote our MRF here, so we can't can't
2556 * compute-to-MRF before that.
2561 if (scan_inst
->mlen
> 0) {
2562 /* Found a SEND instruction, which will do some amount of
2563 * implied write that may overwrite our MRF that we were
2564 * hoping to compute-to-MRF somewhere above it. Nothing
2565 * we have implied-writes more than 2 MRFs from base_mrf,
2568 int implied_write_len
= MIN2(scan_inst
->mlen
, 2);
2569 if (inst
->dst
.hw_reg
>= scan_inst
->base_mrf
&&
2570 inst
->dst
.hw_reg
< scan_inst
->base_mrf
+ implied_write_len
) {
2575 if (scan_inst
->dst
.file
== GRF
&&
2576 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2577 /* Found the last thing to write our reg we want to turn
2578 * into a compute-to-MRF.
2581 if (scan_inst
->opcode
== FS_OPCODE_TEX
) {
2582 /* texturing writes several continuous regs, so we can't
2583 * compute-to-mrf that.
2588 /* If it's predicated, it (probably) didn't populate all
2591 if (scan_inst
->predicated
)
2594 /* SEND instructions can't have MRF as a destination. */
2595 if (scan_inst
->mlen
)
2598 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2599 /* Found the creator of our MRF's source value. */
2606 scan_inst
->dst
.file
= MRF
;
2607 scan_inst
->dst
.hw_reg
= inst
->dst
.hw_reg
;
2608 scan_inst
->saturate
|= inst
->saturate
;
2618 fs_visitor::virtual_grf_interferes(int a
, int b
)
2620 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
2621 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
2623 /* For dead code, just check if the def interferes with the other range. */
2624 if (this->virtual_grf_use
[a
] == -1) {
2625 return (this->virtual_grf_def
[a
] >= this->virtual_grf_def
[b
] &&
2626 this->virtual_grf_def
[a
] < this->virtual_grf_use
[b
]);
2628 if (this->virtual_grf_use
[b
] == -1) {
2629 return (this->virtual_grf_def
[b
] >= this->virtual_grf_def
[a
] &&
2630 this->virtual_grf_def
[b
] < this->virtual_grf_use
[a
]);
2636 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
2638 struct brw_reg brw_reg
;
2640 switch (reg
->file
) {
2644 brw_reg
= brw_vec8_reg(reg
->file
,
2646 brw_reg
= retype(brw_reg
, reg
->type
);
2649 switch (reg
->type
) {
2650 case BRW_REGISTER_TYPE_F
:
2651 brw_reg
= brw_imm_f(reg
->imm
.f
);
2653 case BRW_REGISTER_TYPE_D
:
2654 brw_reg
= brw_imm_d(reg
->imm
.i
);
2656 case BRW_REGISTER_TYPE_UD
:
2657 brw_reg
= brw_imm_ud(reg
->imm
.u
);
2660 assert(!"not reached");
2665 brw_reg
= reg
->fixed_hw_reg
;
2668 /* Probably unused. */
2669 brw_reg
= brw_null_reg();
2672 assert(!"not reached");
2673 brw_reg
= brw_null_reg();
2677 brw_reg
= brw_abs(brw_reg
);
2679 brw_reg
= negate(brw_reg
);
2685 fs_visitor::generate_code()
2687 unsigned int annotation_len
= 0;
2688 int last_native_inst
= 0;
2689 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
2690 int if_stack_depth
= 0, loop_stack_depth
= 0;
2691 int if_depth_in_loop
[16];
2693 if_depth_in_loop
[loop_stack_depth
] = 0;
2695 memset(&if_stack
, 0, sizeof(if_stack
));
2696 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2697 fs_inst
*inst
= (fs_inst
*)iter
.get();
2698 struct brw_reg src
[3], dst
;
2700 for (unsigned int i
= 0; i
< 3; i
++) {
2701 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
2703 dst
= brw_reg_from_fs_reg(&inst
->dst
);
2705 brw_set_conditionalmod(p
, inst
->conditional_mod
);
2706 brw_set_predicate_control(p
, inst
->predicated
);
2708 switch (inst
->opcode
) {
2709 case BRW_OPCODE_MOV
:
2710 brw_MOV(p
, dst
, src
[0]);
2712 case BRW_OPCODE_ADD
:
2713 brw_ADD(p
, dst
, src
[0], src
[1]);
2715 case BRW_OPCODE_MUL
:
2716 brw_MUL(p
, dst
, src
[0], src
[1]);
2719 case BRW_OPCODE_FRC
:
2720 brw_FRC(p
, dst
, src
[0]);
2722 case BRW_OPCODE_RNDD
:
2723 brw_RNDD(p
, dst
, src
[0]);
2725 case BRW_OPCODE_RNDZ
:
2726 brw_RNDZ(p
, dst
, src
[0]);
2729 case BRW_OPCODE_AND
:
2730 brw_AND(p
, dst
, src
[0], src
[1]);
2733 brw_OR(p
, dst
, src
[0], src
[1]);
2735 case BRW_OPCODE_XOR
:
2736 brw_XOR(p
, dst
, src
[0], src
[1]);
2738 case BRW_OPCODE_NOT
:
2739 brw_NOT(p
, dst
, src
[0]);
2741 case BRW_OPCODE_ASR
:
2742 brw_ASR(p
, dst
, src
[0], src
[1]);
2744 case BRW_OPCODE_SHR
:
2745 brw_SHR(p
, dst
, src
[0], src
[1]);
2747 case BRW_OPCODE_SHL
:
2748 brw_SHL(p
, dst
, src
[0], src
[1]);
2751 case BRW_OPCODE_CMP
:
2752 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
2754 case BRW_OPCODE_SEL
:
2755 brw_SEL(p
, dst
, src
[0], src
[1]);
2759 assert(if_stack_depth
< 16);
2760 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
2761 if_depth_in_loop
[loop_stack_depth
]++;
2764 case BRW_OPCODE_ELSE
:
2765 if_stack
[if_stack_depth
- 1] =
2766 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
2768 case BRW_OPCODE_ENDIF
:
2770 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
2771 if_depth_in_loop
[loop_stack_depth
]--;
2775 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
2776 if_depth_in_loop
[loop_stack_depth
] = 0;
2779 case BRW_OPCODE_BREAK
:
2780 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
2781 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2783 case BRW_OPCODE_CONTINUE
:
2784 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
2785 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2788 case BRW_OPCODE_WHILE
: {
2789 struct brw_instruction
*inst0
, *inst1
;
2792 if (intel
->gen
>= 5)
2795 assert(loop_stack_depth
> 0);
2797 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
2798 /* patch all the BREAK/CONT instructions from last BGNLOOP */
2799 while (inst0
> loop_stack
[loop_stack_depth
]) {
2801 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
2802 inst0
->bits3
.if_else
.jump_count
== 0) {
2803 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
2805 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
2806 inst0
->bits3
.if_else
.jump_count
== 0) {
2807 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
2815 case FS_OPCODE_SQRT
:
2816 case FS_OPCODE_EXP2
:
2817 case FS_OPCODE_LOG2
:
2821 generate_math(inst
, dst
, src
);
2823 case FS_OPCODE_LINTERP
:
2824 generate_linterp(inst
, dst
, src
);
2829 generate_tex(inst
, dst
);
2831 case FS_OPCODE_DISCARD_NOT
:
2832 generate_discard_not(inst
, dst
);
2834 case FS_OPCODE_DISCARD_AND
:
2835 generate_discard_and(inst
, src
[0]);
2838 generate_ddx(inst
, dst
, src
[0]);
2841 generate_ddy(inst
, dst
, src
[0]);
2843 case FS_OPCODE_FB_WRITE
:
2844 generate_fb_write(inst
);
2847 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
2848 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
2849 brw_opcodes
[inst
->opcode
].name
);
2851 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
2856 if (annotation_len
< p
->nr_insn
) {
2857 annotation_len
*= 2;
2858 if (annotation_len
< 16)
2859 annotation_len
= 16;
2861 this->annotation_string
= talloc_realloc(this->mem_ctx
,
2865 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
2871 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
2872 this->annotation_string
[i
] = inst
->annotation
;
2873 this->annotation_ir
[i
] = inst
->ir
;
2875 last_native_inst
= p
->nr_insn
;
2880 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
2882 struct brw_compile
*p
= &c
->func
;
2883 struct intel_context
*intel
= &brw
->intel
;
2884 GLcontext
*ctx
= &intel
->ctx
;
2885 struct brw_shader
*shader
= NULL
;
2886 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
2894 for (unsigned int i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
2895 if (prog
->_LinkedShaders
[i
]->Type
== GL_FRAGMENT_SHADER
) {
2896 shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
2903 /* We always use 8-wide mode, at least for now. For one, flow
2904 * control only works in 8-wide. Also, when we're fragment shader
2905 * bound, we're almost always under register pressure as well, so
2906 * 8-wide would save us from the performance cliff of spilling
2909 c
->dispatch_width
= 8;
2911 if (INTEL_DEBUG
& DEBUG_WM
) {
2912 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
2913 _mesa_print_ir(shader
->ir
, NULL
);
2917 /* Now the main event: Visit the shader IR and generate our FS IR for it.
2919 fs_visitor
v(c
, shader
);
2924 v
.calculate_urb_setup();
2926 v
.emit_interpolation_setup_gen4();
2928 v
.emit_interpolation_setup_gen6();
2930 /* Generate FS IR for main(). (the visitor only descends into
2931 * functions called "main").
2933 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
2934 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
2940 v
.assign_curb_setup();
2941 v
.assign_urb_setup();
2947 v
.calculate_live_intervals();
2948 progress
= v
.propagate_constants() || progress
;
2949 progress
= v
.register_coalesce() || progress
;
2950 progress
= v
.compute_to_mrf() || progress
;
2951 progress
= v
.dead_code_eliminate() || progress
;
2955 v
.assign_regs_trivial();
2963 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
2968 if (INTEL_DEBUG
& DEBUG_WM
) {
2969 const char *last_annotation_string
= NULL
;
2970 ir_instruction
*last_annotation_ir
= NULL
;
2972 printf("Native code for fragment shader %d:\n", prog
->Name
);
2973 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
2974 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
2975 last_annotation_ir
= v
.annotation_ir
[i
];
2976 if (last_annotation_ir
) {
2978 last_annotation_ir
->print();
2982 if (last_annotation_string
!= v
.annotation_string
[i
]) {
2983 last_annotation_string
= v
.annotation_string
[i
];
2984 if (last_annotation_string
)
2985 printf(" %s\n", last_annotation_string
);
2987 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
2992 c
->prog_data
.total_grf
= v
.grf_used
;
2993 c
->prog_data
.total_scratch
= 0;