2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "../glsl/glsl_types.h"
47 #include "../glsl/ir_optimization.h"
48 #include "../glsl/ir_print_visitor.h"
51 ARF
= BRW_ARCHITECTURE_REGISTER_FILE
,
52 GRF
= BRW_GENERAL_REGISTER_FILE
,
53 MRF
= BRW_MESSAGE_REGISTER_FILE
,
54 IMM
= BRW_IMMEDIATE_VALUE
,
55 FIXED_HW_REG
, /* a struct brw_reg */
56 UNIFORM
, /* prog_data->params[hw_reg] */
61 FS_OPCODE_FB_WRITE
= 256,
79 static int using_new_fs
= -1;
80 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
83 brw_new_shader(GLcontext
*ctx
, GLuint name
, GLuint type
)
85 struct brw_shader
*shader
;
87 shader
= talloc_zero(NULL
, struct brw_shader
);
89 shader
->base
.Type
= type
;
90 shader
->base
.Name
= name
;
91 _mesa_init_shader(ctx
, &shader
->base
);
97 struct gl_shader_program
*
98 brw_new_shader_program(GLcontext
*ctx
, GLuint name
)
100 struct brw_shader_program
*prog
;
101 prog
= talloc_zero(NULL
, struct brw_shader_program
);
103 prog
->base
.Name
= name
;
104 _mesa_init_shader_program(ctx
, &prog
->base
);
110 brw_compile_shader(GLcontext
*ctx
, struct gl_shader
*shader
)
112 if (!_mesa_ir_compile_shader(ctx
, shader
))
119 brw_link_shader(GLcontext
*ctx
, struct gl_shader_program
*prog
)
121 struct intel_context
*intel
= intel_context(ctx
);
122 if (using_new_fs
== -1)
123 using_new_fs
= getenv("INTEL_NEW_FS") != NULL
;
125 for (unsigned i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
126 struct brw_shader
*shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
128 if (using_new_fs
&& shader
->base
.Type
== GL_FRAGMENT_SHADER
) {
129 void *mem_ctx
= talloc_new(NULL
);
133 talloc_free(shader
->ir
);
134 shader
->ir
= new(shader
) exec_list
;
135 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
137 do_mat_op_to_vec(shader
->ir
);
138 do_mod_to_fract(shader
->ir
);
139 do_div_to_mul_rcp(shader
->ir
);
140 do_sub_to_add_neg(shader
->ir
);
141 do_explog_to_explog2(shader
->ir
);
142 do_lower_texture_projection(shader
->ir
);
143 brw_do_cubemap_normalize(shader
->ir
);
148 brw_do_channel_expressions(shader
->ir
);
149 brw_do_vector_splitting(shader
->ir
);
151 progress
= do_lower_jumps(shader
->ir
, true, true,
152 true, /* main return */
153 false, /* continue */
157 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
159 progress
= lower_noise(shader
->ir
) || progress
;
161 lower_variable_index_to_cond_assign(shader
->ir
,
163 GL_TRUE
, /* output */
165 GL_TRUE
/* uniform */
167 if (intel
->gen
== 6) {
168 progress
= do_if_to_cond_assign(shader
->ir
) || progress
;
172 validate_ir_tree(shader
->ir
);
174 reparent_ir(shader
->ir
, shader
->ir
);
175 talloc_free(mem_ctx
);
179 if (!_mesa_ir_link_shader(ctx
, prog
))
186 type_size(const struct glsl_type
*type
)
188 unsigned int size
, i
;
190 switch (type
->base_type
) {
193 case GLSL_TYPE_FLOAT
:
195 return type
->components();
196 case GLSL_TYPE_ARRAY
:
197 return type_size(type
->fields
.array
) * type
->length
;
198 case GLSL_TYPE_STRUCT
:
200 for (i
= 0; i
< type
->length
; i
++) {
201 size
+= type_size(type
->fields
.structure
[i
].type
);
204 case GLSL_TYPE_SAMPLER
:
205 /* Samplers take up no register space, since they're baked in at
210 assert(!"not reached");
217 /* Callers of this talloc-based new need not call delete. It's
218 * easier to just talloc_free 'ctx' (or any of its ancestors). */
219 static void* operator new(size_t size
, void *ctx
)
223 node
= talloc_size(ctx
, size
);
224 assert(node
!= NULL
);
232 this->reg_offset
= 0;
238 /** Generic unset register constructor. */
242 this->file
= BAD_FILE
;
245 /** Immediate value constructor. */
250 this->type
= BRW_REGISTER_TYPE_F
;
254 /** Immediate value constructor. */
259 this->type
= BRW_REGISTER_TYPE_D
;
263 /** Immediate value constructor. */
268 this->type
= BRW_REGISTER_TYPE_UD
;
272 /** Fixed brw_reg Immediate value constructor. */
273 fs_reg(struct brw_reg fixed_hw_reg
)
276 this->file
= FIXED_HW_REG
;
277 this->fixed_hw_reg
= fixed_hw_reg
;
278 this->type
= fixed_hw_reg
.type
;
281 fs_reg(enum register_file file
, int hw_reg
);
282 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
284 /** Register file: ARF, GRF, MRF, IMM. */
285 enum register_file file
;
286 /** virtual register number. 0 = fixed hw reg */
288 /** Offset within the virtual register. */
290 /** HW register number. Generally unset until register allocation. */
292 /** Register type. BRW_REGISTER_TYPE_* */
296 struct brw_reg fixed_hw_reg
;
298 /** Value for file == BRW_IMMMEDIATE_FILE */
306 static const fs_reg reg_undef
;
307 static const fs_reg
reg_null(ARF
, BRW_ARF_NULL
);
309 class fs_inst
: public exec_node
{
311 /* Callers of this talloc-based new need not call delete. It's
312 * easier to just talloc_free 'ctx' (or any of its ancestors). */
313 static void* operator new(size_t size
, void *ctx
)
317 node
= talloc_zero_size(ctx
, size
);
318 assert(node
!= NULL
);
325 this->opcode
= BRW_OPCODE_NOP
;
326 this->saturate
= false;
327 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
328 this->predicated
= false;
332 this->header_present
= false;
333 this->shadow_compare
= false;
344 this->opcode
= opcode
;
347 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
)
350 this->opcode
= opcode
;
355 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
358 this->opcode
= opcode
;
364 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg src2
)
367 this->opcode
= opcode
;
374 int opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
379 int conditional_mod
; /**< BRW_CONDITIONAL_* */
381 int mlen
; /**< SEND message length */
383 int target
; /**< MRT target. */
389 * Annotation for the generated IR. One of the two can be set.
392 const char *annotation
;
396 class fs_visitor
: public ir_visitor
400 fs_visitor(struct brw_wm_compile
*c
, struct brw_shader
*shader
)
405 this->fp
= brw
->fragment_program
;
406 this->intel
= &brw
->intel
;
407 this->ctx
= &intel
->ctx
;
408 this->mem_ctx
= talloc_new(NULL
);
409 this->shader
= shader
;
411 this->variable_ht
= hash_table_ctor(0,
412 hash_table_pointer_hash
,
413 hash_table_pointer_compare
);
415 this->frag_color
= NULL
;
416 this->frag_data
= NULL
;
417 this->frag_depth
= NULL
;
418 this->first_non_payload_grf
= 0;
420 this->current_annotation
= NULL
;
421 this->annotation_string
= NULL
;
422 this->annotation_ir
= NULL
;
423 this->base_ir
= NULL
;
425 this->virtual_grf_sizes
= NULL
;
426 this->virtual_grf_next
= 1;
427 this->virtual_grf_array_size
= 0;
428 this->virtual_grf_def
= NULL
;
429 this->virtual_grf_use
= NULL
;
431 this->kill_emitted
= false;
436 talloc_free(this->mem_ctx
);
437 hash_table_dtor(this->variable_ht
);
440 fs_reg
*variable_storage(ir_variable
*var
);
441 int virtual_grf_alloc(int size
);
443 void visit(ir_variable
*ir
);
444 void visit(ir_assignment
*ir
);
445 void visit(ir_dereference_variable
*ir
);
446 void visit(ir_dereference_record
*ir
);
447 void visit(ir_dereference_array
*ir
);
448 void visit(ir_expression
*ir
);
449 void visit(ir_texture
*ir
);
450 void visit(ir_if
*ir
);
451 void visit(ir_constant
*ir
);
452 void visit(ir_swizzle
*ir
);
453 void visit(ir_return
*ir
);
454 void visit(ir_loop
*ir
);
455 void visit(ir_loop_jump
*ir
);
456 void visit(ir_discard
*ir
);
457 void visit(ir_call
*ir
);
458 void visit(ir_function
*ir
);
459 void visit(ir_function_signature
*ir
);
461 fs_inst
*emit(fs_inst inst
);
462 void assign_curb_setup();
463 void calculate_urb_setup();
464 void assign_urb_setup();
466 void assign_regs_trivial();
467 void calculate_live_intervals();
468 bool propagate_constants();
469 bool dead_code_eliminate();
470 bool virtual_grf_interferes(int a
, int b
);
471 void generate_code();
472 void generate_fb_write(fs_inst
*inst
);
473 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
474 struct brw_reg
*src
);
475 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
476 void generate_math(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg
*src
);
477 void generate_discard(fs_inst
*inst
, struct brw_reg temp
);
478 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
479 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
481 void emit_dummy_fs();
482 fs_reg
*emit_fragcoord_interpolation(ir_variable
*ir
);
483 fs_reg
*emit_frontfacing_interpolation(ir_variable
*ir
);
484 fs_reg
*emit_general_interpolation(ir_variable
*ir
);
485 void emit_interpolation_setup_gen4();
486 void emit_interpolation_setup_gen6();
487 fs_inst
*emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
);
488 fs_inst
*emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
);
489 void emit_fb_writes();
490 void emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
491 const glsl_type
*type
, bool predicated
);
493 struct brw_reg
interp_reg(int location
, int channel
);
494 int setup_uniform_values(int loc
, const glsl_type
*type
);
495 void setup_builtin_uniform_values(ir_variable
*ir
);
497 struct brw_context
*brw
;
498 const struct gl_fragment_program
*fp
;
499 struct intel_context
*intel
;
501 struct brw_wm_compile
*c
;
502 struct brw_compile
*p
;
503 struct brw_shader
*shader
;
505 exec_list instructions
;
507 int *virtual_grf_sizes
;
508 int virtual_grf_next
;
509 int virtual_grf_array_size
;
510 int *virtual_grf_def
;
511 int *virtual_grf_use
;
513 struct hash_table
*variable_ht
;
514 ir_variable
*frag_color
, *frag_data
, *frag_depth
;
515 int first_non_payload_grf
;
516 int urb_setup
[FRAG_ATTRIB_MAX
];
519 /** @{ debug annotation info */
520 const char *current_annotation
;
521 ir_instruction
*base_ir
;
522 const char **annotation_string
;
523 ir_instruction
**annotation_ir
;
528 /* Result of last visit() method. */
543 fs_visitor::virtual_grf_alloc(int size
)
545 if (virtual_grf_array_size
<= virtual_grf_next
) {
546 if (virtual_grf_array_size
== 0)
547 virtual_grf_array_size
= 16;
549 virtual_grf_array_size
*= 2;
550 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
551 int, virtual_grf_array_size
);
553 /* This slot is always unused. */
554 virtual_grf_sizes
[0] = 0;
556 virtual_grf_sizes
[virtual_grf_next
] = size
;
557 return virtual_grf_next
++;
560 /** Fixed HW reg constructor. */
561 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
565 this->hw_reg
= hw_reg
;
566 this->type
= BRW_REGISTER_TYPE_F
;
570 brw_type_for_base_type(const struct glsl_type
*type
)
572 switch (type
->base_type
) {
573 case GLSL_TYPE_FLOAT
:
574 return BRW_REGISTER_TYPE_F
;
577 return BRW_REGISTER_TYPE_D
;
579 return BRW_REGISTER_TYPE_UD
;
580 case GLSL_TYPE_ARRAY
:
581 case GLSL_TYPE_STRUCT
:
582 /* These should be overridden with the type of the member when
583 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
584 * way to trip up if we don't.
586 return BRW_REGISTER_TYPE_UD
;
588 assert(!"not reached");
589 return BRW_REGISTER_TYPE_F
;
593 /** Automatic reg constructor. */
594 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
599 this->reg
= v
->virtual_grf_alloc(type_size(type
));
600 this->reg_offset
= 0;
601 this->type
= brw_type_for_base_type(type
);
605 fs_visitor::variable_storage(ir_variable
*var
)
607 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
610 /* Our support for uniforms is piggy-backed on the struct
611 * gl_fragment_program, because that's where the values actually
612 * get stored, rather than in some global gl_shader_program uniform
616 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
618 unsigned int offset
= 0;
621 if (type
->is_matrix()) {
622 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
623 type
->vector_elements
,
626 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
627 offset
+= setup_uniform_values(loc
+ offset
, column
);
633 switch (type
->base_type
) {
634 case GLSL_TYPE_FLOAT
:
638 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
639 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
640 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
644 case GLSL_TYPE_STRUCT
:
645 for (unsigned int i
= 0; i
< type
->length
; i
++) {
646 offset
+= setup_uniform_values(loc
+ offset
,
647 type
->fields
.structure
[i
].type
);
651 case GLSL_TYPE_ARRAY
:
652 for (unsigned int i
= 0; i
< type
->length
; i
++) {
653 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
657 case GLSL_TYPE_SAMPLER
:
658 /* The sampler takes up a slot, but we don't use any values from it. */
662 assert(!"not reached");
668 /* Our support for builtin uniforms is even scarier than non-builtin.
669 * It sits on top of the PROG_STATE_VAR parameters that are
670 * automatically updated from GL context state.
673 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
675 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
677 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
678 statevar
= &_mesa_builtin_uniform_desc
[i
];
679 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
683 if (!statevar
->name
) {
685 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
690 if (ir
->type
->is_array()) {
691 array_count
= ir
->type
->length
;
696 for (int a
= 0; a
< array_count
; a
++) {
697 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
698 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
699 int tokens
[STATE_LENGTH
];
701 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
702 if (ir
->type
->is_array()) {
706 /* This state reference has already been setup by ir_to_mesa,
707 * but we'll get the same index back here.
709 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
710 (gl_state_index
*)tokens
);
711 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
713 /* Add each of the unique swizzles of the element as a
714 * parameter. This'll end up matching the expected layout of
715 * the array/matrix/structure we're trying to fill in.
718 for (unsigned int i
= 0; i
< 4; i
++) {
719 int swiz
= GET_SWZ(element
->swizzle
, i
);
720 if (swiz
== last_swiz
)
724 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
731 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
733 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
735 fs_reg neg_y
= this->pixel_y
;
739 if (ir
->pixel_center_integer
) {
740 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
742 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
747 if (ir
->origin_upper_left
&& ir
->pixel_center_integer
) {
748 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
750 fs_reg pixel_y
= this->pixel_y
;
751 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
753 if (!ir
->origin_upper_left
) {
754 pixel_y
.negate
= true;
755 offset
+= c
->key
.drawable_height
- 1.0;
758 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
763 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
764 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
767 /* gl_FragCoord.w: Already set up in emit_interpolation */
768 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
774 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
776 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
777 /* Interpolation is always in floating point regs. */
778 reg
->type
= BRW_REGISTER_TYPE_F
;
781 unsigned int array_elements
;
782 const glsl_type
*type
;
784 if (ir
->type
->is_array()) {
785 array_elements
= ir
->type
->length
;
786 if (array_elements
== 0) {
789 type
= ir
->type
->fields
.array
;
795 int location
= ir
->location
;
796 for (unsigned int i
= 0; i
< array_elements
; i
++) {
797 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
798 if (urb_setup
[location
] == -1) {
799 /* If there's no incoming setup data for this slot, don't
800 * emit interpolation for it.
802 attr
.reg_offset
+= type
->vector_elements
;
807 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
808 struct brw_reg interp
= interp_reg(location
, c
);
809 emit(fs_inst(FS_OPCODE_LINTERP
,
817 if (intel
->gen
< 6) {
818 attr
.reg_offset
-= type
->vector_elements
;
819 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
820 emit(fs_inst(BRW_OPCODE_MUL
,
835 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
837 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
839 /* The frontfacing comes in as a bit in the thread payload. */
840 if (intel
->gen
>= 6) {
841 emit(fs_inst(BRW_OPCODE_ASR
,
843 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
845 emit(fs_inst(BRW_OPCODE_NOT
,
848 emit(fs_inst(BRW_OPCODE_AND
,
853 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
854 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
855 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
858 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
862 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
863 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
870 fs_visitor::visit(ir_variable
*ir
)
874 if (variable_storage(ir
))
877 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
878 this->frag_color
= ir
;
879 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
880 this->frag_data
= ir
;
881 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
882 this->frag_depth
= ir
;
885 if (ir
->mode
== ir_var_in
) {
886 if (!strcmp(ir
->name
, "gl_FragCoord")) {
887 reg
= emit_fragcoord_interpolation(ir
);
888 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
889 reg
= emit_frontfacing_interpolation(ir
);
891 reg
= emit_general_interpolation(ir
);
894 hash_table_insert(this->variable_ht
, reg
, ir
);
898 if (ir
->mode
== ir_var_uniform
) {
899 int param_index
= c
->prog_data
.nr_params
;
901 if (!strncmp(ir
->name
, "gl_", 3)) {
902 setup_builtin_uniform_values(ir
);
904 setup_uniform_values(ir
->location
, ir
->type
);
907 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
911 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
913 hash_table_insert(this->variable_ht
, reg
, ir
);
917 fs_visitor::visit(ir_dereference_variable
*ir
)
919 fs_reg
*reg
= variable_storage(ir
->var
);
924 fs_visitor::visit(ir_dereference_record
*ir
)
926 const glsl_type
*struct_type
= ir
->record
->type
;
928 ir
->record
->accept(this);
930 unsigned int offset
= 0;
931 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
932 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
934 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
936 this->result
.reg_offset
+= offset
;
937 this->result
.type
= brw_type_for_base_type(ir
->type
);
941 fs_visitor::visit(ir_dereference_array
*ir
)
946 ir
->array
->accept(this);
947 index
= ir
->array_index
->as_constant();
949 element_size
= type_size(ir
->type
);
950 this->result
.type
= brw_type_for_base_type(ir
->type
);
953 assert(this->result
.file
== UNIFORM
||
954 (this->result
.file
== GRF
&&
955 this->result
.reg
!= 0));
956 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
958 assert(!"FINISHME: non-constant array element");
963 fs_visitor::visit(ir_expression
*ir
)
965 unsigned int operand
;
970 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
971 ir
->operands
[operand
]->accept(this);
972 if (this->result
.file
== BAD_FILE
) {
974 printf("Failed to get tree for expression operand:\n");
975 ir
->operands
[operand
]->accept(&v
);
978 op
[operand
] = this->result
;
980 /* Matrix expression operands should have been broken down to vector
981 * operations already.
983 assert(!ir
->operands
[operand
]->type
->is_matrix());
984 /* And then those vector operands should have been broken down to scalar.
986 assert(!ir
->operands
[operand
]->type
->is_vector());
989 /* Storage for our result. If our result goes into an assignment, it will
990 * just get copy-propagated out, so no worries.
992 this->result
= fs_reg(this, ir
->type
);
994 switch (ir
->operation
) {
995 case ir_unop_logic_not
:
996 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], fs_reg(-1)));
999 op
[0].negate
= !op
[0].negate
;
1000 this->result
= op
[0];
1004 this->result
= op
[0];
1007 temp
= fs_reg(this, ir
->type
);
1009 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
1011 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
1012 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1013 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
1014 inst
->predicated
= true;
1016 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
1017 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1018 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
1019 inst
->predicated
= true;
1023 emit(fs_inst(FS_OPCODE_RCP
, this->result
, op
[0]));
1027 emit(fs_inst(FS_OPCODE_EXP2
, this->result
, op
[0]));
1030 emit(fs_inst(FS_OPCODE_LOG2
, this->result
, op
[0]));
1034 assert(!"not reached: should be handled by ir_explog_to_explog2");
1037 emit(fs_inst(FS_OPCODE_SIN
, this->result
, op
[0]));
1040 emit(fs_inst(FS_OPCODE_COS
, this->result
, op
[0]));
1044 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
1047 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
1051 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
1054 assert(!"not reached: should be handled by ir_sub_to_add_neg");
1058 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
1061 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1064 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1068 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1069 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1070 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1072 case ir_binop_greater
:
1073 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1074 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1075 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1077 case ir_binop_lequal
:
1078 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1079 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1080 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1082 case ir_binop_gequal
:
1083 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1084 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1085 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1087 case ir_binop_equal
:
1088 case ir_binop_all_equal
: /* same as nequal for scalars */
1089 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1090 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1091 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1093 case ir_binop_nequal
:
1094 case ir_binop_any_nequal
: /* same as nequal for scalars */
1095 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1096 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1097 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1100 case ir_binop_logic_xor
:
1101 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
1104 case ir_binop_logic_or
:
1105 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
1108 case ir_binop_logic_and
:
1109 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
1113 case ir_binop_cross
:
1115 assert(!"not reached: should be handled by brw_fs_channel_expressions");
1119 assert(!"not reached: should be handled by lower_noise");
1123 emit(fs_inst(FS_OPCODE_SQRT
, this->result
, op
[0]));
1127 emit(fs_inst(FS_OPCODE_RSQ
, this->result
, op
[0]));
1133 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1136 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1140 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
1141 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1144 emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1147 op
[0].negate
= ~op
[0].negate
;
1148 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1149 this->result
.negate
= true;
1152 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1155 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
1159 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1160 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1162 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1163 inst
->predicated
= true;
1166 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1167 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1169 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1170 inst
->predicated
= true;
1174 inst
= emit(fs_inst(FS_OPCODE_POW
, this->result
, op
[0], op
[1]));
1177 case ir_unop_bit_not
:
1179 case ir_binop_lshift
:
1180 case ir_binop_rshift
:
1181 case ir_binop_bit_and
:
1182 case ir_binop_bit_xor
:
1183 case ir_binop_bit_or
:
1184 assert(!"GLSL 1.30 features unsupported");
1190 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1191 const glsl_type
*type
, bool predicated
)
1193 switch (type
->base_type
) {
1194 case GLSL_TYPE_FLOAT
:
1195 case GLSL_TYPE_UINT
:
1197 case GLSL_TYPE_BOOL
:
1198 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1199 l
.type
= brw_type_for_base_type(type
);
1200 r
.type
= brw_type_for_base_type(type
);
1202 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1203 inst
->predicated
= predicated
;
1209 case GLSL_TYPE_ARRAY
:
1210 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1211 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1214 case GLSL_TYPE_STRUCT
:
1215 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1216 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1221 case GLSL_TYPE_SAMPLER
:
1225 assert(!"not reached");
1231 fs_visitor::visit(ir_assignment
*ir
)
1236 /* FINISHME: arrays on the lhs */
1237 ir
->lhs
->accept(this);
1240 ir
->rhs
->accept(this);
1243 assert(l
.file
!= BAD_FILE
);
1244 assert(r
.file
!= BAD_FILE
);
1246 if (ir
->condition
) {
1247 /* Get the condition bool into the predicate. */
1248 ir
->condition
->accept(this);
1249 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, this->result
, fs_reg(0)));
1250 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1253 if (ir
->lhs
->type
->is_scalar() ||
1254 ir
->lhs
->type
->is_vector()) {
1255 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1256 if (ir
->write_mask
& (1 << i
)) {
1257 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1259 inst
->predicated
= true;
1265 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1270 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1274 bool simd16
= false;
1277 if (ir
->shadow_comparitor
) {
1278 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1279 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1281 coordinate
.reg_offset
++;
1283 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1286 if (ir
->op
== ir_tex
) {
1287 /* There's no plain shadow compare message, so we use shadow
1288 * compare with a bias of 0.0.
1290 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1293 } else if (ir
->op
== ir_txb
) {
1294 ir
->lod_info
.bias
->accept(this);
1295 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1299 assert(ir
->op
== ir_txl
);
1300 ir
->lod_info
.lod
->accept(this);
1301 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1306 ir
->shadow_comparitor
->accept(this);
1307 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1309 } else if (ir
->op
== ir_tex
) {
1310 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1311 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1313 coordinate
.reg_offset
++;
1315 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1318 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1319 * instructions. We'll need to do SIMD16 here.
1321 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1323 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
* 2;) {
1324 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1326 coordinate
.reg_offset
++;
1329 /* The unused upper half. */
1333 /* lod/bias appears after u/v/r. */
1336 if (ir
->op
== ir_txb
) {
1337 ir
->lod_info
.bias
->accept(this);
1338 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1342 ir
->lod_info
.lod
->accept(this);
1343 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1348 /* The unused upper half. */
1351 /* Now, since we're doing simd16, the return is 2 interleaved
1352 * vec4s where the odd-indexed ones are junk. We'll need to move
1353 * this weirdness around to the expected layout.
1357 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1359 dst
.type
= BRW_REGISTER_TYPE_F
;
1362 fs_inst
*inst
= NULL
;
1365 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
1368 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
, fs_reg(MRF
, base_mrf
)));
1371 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
, fs_reg(MRF
, base_mrf
)));
1375 assert(!"GLSL 1.30 features unsupported");
1381 for (int i
= 0; i
< 4; i
++) {
1382 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1383 orig_dst
.reg_offset
++;
1384 dst
.reg_offset
+= 2;
1392 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1394 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1395 * optional parameters like shadow comparitor or LOD bias. If
1396 * optional parameters aren't present, those base slots are
1397 * optional and don't need to be included in the message.
1399 * We don't fill in the unnecessary slots regardless, which may
1400 * look surprising in the disassembly.
1405 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1406 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1407 coordinate
.reg_offset
++;
1410 if (ir
->shadow_comparitor
) {
1411 mlen
= MAX2(mlen
, 4);
1413 ir
->shadow_comparitor
->accept(this);
1414 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1418 fs_inst
*inst
= NULL
;
1421 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
1424 ir
->lod_info
.bias
->accept(this);
1425 mlen
= MAX2(mlen
, 4);
1426 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1429 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
, fs_reg(MRF
, base_mrf
)));
1432 ir
->lod_info
.lod
->accept(this);
1433 mlen
= MAX2(mlen
, 4);
1434 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1437 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
, fs_reg(MRF
, base_mrf
)));
1441 assert(!"GLSL 1.30 features unsupported");
1450 fs_visitor::visit(ir_texture
*ir
)
1452 fs_inst
*inst
= NULL
;
1454 ir
->coordinate
->accept(this);
1455 fs_reg coordinate
= this->result
;
1457 /* Should be lowered by do_lower_texture_projection */
1458 assert(!ir
->projector
);
1460 /* Writemasking doesn't eliminate channels on SIMD8 texture
1461 * samples, so don't worry about them.
1463 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1465 if (intel
->gen
< 5) {
1466 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1468 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1472 _mesa_get_sampler_uniform_value(ir
->sampler
,
1473 ctx
->Shader
.CurrentProgram
,
1474 &brw
->fragment_program
->Base
);
1475 inst
->sampler
= c
->fp
->program
.Base
.SamplerUnits
[inst
->sampler
];
1479 if (ir
->shadow_comparitor
)
1480 inst
->shadow_compare
= true;
1482 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1483 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1485 for (int i
= 0; i
< 4; i
++) {
1486 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1487 fs_reg l
= swizzle_dst
;
1490 if (swiz
== SWIZZLE_ZERO
) {
1491 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1492 } else if (swiz
== SWIZZLE_ONE
) {
1493 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1496 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1497 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1500 this->result
= swizzle_dst
;
1505 fs_visitor::visit(ir_swizzle
*ir
)
1507 ir
->val
->accept(this);
1508 fs_reg val
= this->result
;
1510 if (ir
->type
->vector_elements
== 1) {
1511 this->result
.reg_offset
+= ir
->mask
.x
;
1515 fs_reg result
= fs_reg(this, ir
->type
);
1516 this->result
= result
;
1518 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1519 fs_reg channel
= val
;
1537 channel
.reg_offset
+= swiz
;
1538 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1539 result
.reg_offset
++;
1544 fs_visitor::visit(ir_discard
*ir
)
1546 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1548 assert(ir
->condition
== NULL
); /* FINISHME */
1550 emit(fs_inst(FS_OPCODE_DISCARD
, temp
, temp
));
1551 kill_emitted
= true;
1555 fs_visitor::visit(ir_constant
*ir
)
1557 fs_reg
reg(this, ir
->type
);
1560 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1561 switch (ir
->type
->base_type
) {
1562 case GLSL_TYPE_FLOAT
:
1563 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
1565 case GLSL_TYPE_UINT
:
1566 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1569 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1571 case GLSL_TYPE_BOOL
:
1572 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1575 assert(!"Non-float/uint/int/bool constant");
1582 fs_visitor::visit(ir_if
*ir
)
1586 /* Don't point the annotation at the if statement, because then it plus
1587 * the then and else blocks get printed.
1589 this->base_ir
= ir
->condition
;
1591 /* Generate the condition into the condition code. */
1592 ir
->condition
->accept(this);
1593 inst
= emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(brw_null_reg()), this->result
));
1594 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1596 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1597 inst
->predicated
= true;
1599 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1600 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1606 if (!ir
->else_instructions
.is_empty()) {
1607 emit(fs_inst(BRW_OPCODE_ELSE
));
1609 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1610 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1617 emit(fs_inst(BRW_OPCODE_ENDIF
));
1621 fs_visitor::visit(ir_loop
*ir
)
1623 fs_reg counter
= reg_undef
;
1626 this->base_ir
= ir
->counter
;
1627 ir
->counter
->accept(this);
1628 counter
= *(variable_storage(ir
->counter
));
1631 this->base_ir
= ir
->from
;
1632 ir
->from
->accept(this);
1634 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1638 emit(fs_inst(BRW_OPCODE_DO
));
1641 this->base_ir
= ir
->to
;
1642 ir
->to
->accept(this);
1644 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
,
1645 counter
, this->result
));
1647 case ir_binop_equal
:
1648 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1650 case ir_binop_nequal
:
1651 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1653 case ir_binop_gequal
:
1654 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1656 case ir_binop_lequal
:
1657 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1659 case ir_binop_greater
:
1660 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1663 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1666 assert(!"not reached: unknown loop condition");
1671 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1672 inst
->predicated
= true;
1675 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1676 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1682 if (ir
->increment
) {
1683 this->base_ir
= ir
->increment
;
1684 ir
->increment
->accept(this);
1685 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1688 emit(fs_inst(BRW_OPCODE_WHILE
));
1692 fs_visitor::visit(ir_loop_jump
*ir
)
1695 case ir_loop_jump::jump_break
:
1696 emit(fs_inst(BRW_OPCODE_BREAK
));
1698 case ir_loop_jump::jump_continue
:
1699 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1705 fs_visitor::visit(ir_call
*ir
)
1707 assert(!"FINISHME");
1711 fs_visitor::visit(ir_return
*ir
)
1713 assert(!"FINISHME");
1717 fs_visitor::visit(ir_function
*ir
)
1719 /* Ignore function bodies other than main() -- we shouldn't see calls to
1720 * them since they should all be inlined before we get to ir_to_mesa.
1722 if (strcmp(ir
->name
, "main") == 0) {
1723 const ir_function_signature
*sig
;
1726 sig
= ir
->matching_signature(&empty
);
1730 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1731 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1740 fs_visitor::visit(ir_function_signature
*ir
)
1742 assert(!"not reached");
1747 fs_visitor::emit(fs_inst inst
)
1749 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1752 list_inst
->annotation
= this->current_annotation
;
1753 list_inst
->ir
= this->base_ir
;
1755 this->instructions
.push_tail(list_inst
);
1760 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1762 fs_visitor::emit_dummy_fs()
1764 /* Everyone's favorite color. */
1765 emit(fs_inst(BRW_OPCODE_MOV
,
1768 emit(fs_inst(BRW_OPCODE_MOV
,
1771 emit(fs_inst(BRW_OPCODE_MOV
,
1774 emit(fs_inst(BRW_OPCODE_MOV
,
1779 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1784 /* The register location here is relative to the start of the URB
1785 * data. It will get adjusted to be a real location before
1786 * generate_code() time.
1789 fs_visitor::interp_reg(int location
, int channel
)
1791 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1792 int stride
= (channel
& 1) * 4;
1794 assert(urb_setup
[location
] != -1);
1796 return brw_vec1_grf(regnr
, stride
);
1799 /** Emits the interpolation for the varying inputs. */
1801 fs_visitor::emit_interpolation_setup_gen4()
1803 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1805 this->current_annotation
= "compute pixel centers";
1806 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1807 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1808 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1809 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1810 emit(fs_inst(BRW_OPCODE_ADD
,
1812 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1813 fs_reg(brw_imm_v(0x10101010))));
1814 emit(fs_inst(BRW_OPCODE_ADD
,
1816 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1817 fs_reg(brw_imm_v(0x11001100))));
1819 this->current_annotation
= "compute pixel deltas from v0";
1821 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1822 this->delta_y
= this->delta_x
;
1823 this->delta_y
.reg_offset
++;
1825 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1826 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1828 emit(fs_inst(BRW_OPCODE_ADD
,
1831 fs_reg(negate(brw_vec1_grf(1, 0)))));
1832 emit(fs_inst(BRW_OPCODE_ADD
,
1835 fs_reg(negate(brw_vec1_grf(1, 1)))));
1837 this->current_annotation
= "compute pos.w and 1/pos.w";
1838 /* Compute wpos.w. It's always in our setup, since it's needed to
1839 * interpolate the other attributes.
1841 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1842 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1843 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1844 /* Compute the pixel 1/W value from wpos.w. */
1845 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1846 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
));
1847 this->current_annotation
= NULL
;
1850 /** Emits the interpolation for the varying inputs. */
1852 fs_visitor::emit_interpolation_setup_gen6()
1854 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1856 /* If the pixel centers end up used, the setup is the same as for gen4. */
1857 this->current_annotation
= "compute pixel centers";
1858 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1859 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1860 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1861 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1862 emit(fs_inst(BRW_OPCODE_ADD
,
1864 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1865 fs_reg(brw_imm_v(0x10101010))));
1866 emit(fs_inst(BRW_OPCODE_ADD
,
1868 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1869 fs_reg(brw_imm_v(0x11001100))));
1871 this->current_annotation
= "compute 1/pos.w";
1872 this->wpos_w
= fs_reg(brw_vec8_grf(c
->key
.source_w_reg
, 0));
1873 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1874 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
));
1876 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1877 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1879 this->current_annotation
= NULL
;
1883 fs_visitor::emit_fb_writes()
1885 this->current_annotation
= "FB write header";
1886 GLboolean header_present
= GL_TRUE
;
1889 if (intel
->gen
>= 6 &&
1890 !this->kill_emitted
&&
1891 c
->key
.nr_color_regions
== 1) {
1892 header_present
= false;
1895 if (header_present
) {
1900 if (c
->key
.aa_dest_stencil_reg
) {
1901 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1902 fs_reg(brw_vec8_grf(c
->key
.aa_dest_stencil_reg
, 0))));
1905 /* Reserve space for color. It'll be filled in per MRT below. */
1909 if (c
->key
.source_depth_to_render_target
) {
1910 if (c
->key
.computes_depth
) {
1911 /* Hand over gl_FragDepth. */
1912 assert(this->frag_depth
);
1913 fs_reg depth
= *(variable_storage(this->frag_depth
));
1915 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
1917 /* Pass through the payload depth. */
1918 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1919 fs_reg(brw_vec8_grf(c
->key
.source_depth_reg
, 0))));
1923 if (c
->key
.dest_depth_reg
) {
1924 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1925 fs_reg(brw_vec8_grf(c
->key
.dest_depth_reg
, 0))));
1928 fs_reg color
= reg_undef
;
1929 if (this->frag_color
)
1930 color
= *(variable_storage(this->frag_color
));
1931 else if (this->frag_data
)
1932 color
= *(variable_storage(this->frag_data
));
1934 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1935 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1936 "FB write target %d",
1938 if (this->frag_color
|| this->frag_data
) {
1939 for (int i
= 0; i
< 4; i
++) {
1940 emit(fs_inst(BRW_OPCODE_MOV
,
1941 fs_reg(MRF
, color_mrf
+ i
),
1947 if (this->frag_color
)
1948 color
.reg_offset
-= 4;
1950 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1951 reg_undef
, reg_undef
));
1952 inst
->target
= target
;
1954 if (target
== c
->key
.nr_color_regions
- 1)
1956 inst
->header_present
= header_present
;
1959 if (c
->key
.nr_color_regions
== 0) {
1960 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1961 reg_undef
, reg_undef
));
1964 inst
->header_present
= header_present
;
1967 this->current_annotation
= NULL
;
1971 fs_visitor::generate_fb_write(fs_inst
*inst
)
1973 GLboolean eot
= inst
->eot
;
1974 struct brw_reg implied_header
;
1976 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1979 brw_push_insn_state(p
);
1980 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1981 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1983 if (inst
->header_present
) {
1984 if (intel
->gen
>= 6) {
1987 brw_vec8_grf(0, 0));
1988 implied_header
= brw_null_reg();
1990 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1995 brw_vec8_grf(1, 0));
1997 implied_header
= brw_null_reg();
2000 brw_pop_insn_state(p
);
2003 8, /* dispatch_width */
2004 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
2014 fs_visitor::generate_linterp(fs_inst
*inst
,
2015 struct brw_reg dst
, struct brw_reg
*src
)
2017 struct brw_reg delta_x
= src
[0];
2018 struct brw_reg delta_y
= src
[1];
2019 struct brw_reg interp
= src
[2];
2022 delta_y
.nr
== delta_x
.nr
+ 1 &&
2023 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
2024 brw_PLN(p
, dst
, interp
, delta_x
);
2026 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
2027 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
2032 fs_visitor::generate_math(fs_inst
*inst
,
2033 struct brw_reg dst
, struct brw_reg
*src
)
2037 switch (inst
->opcode
) {
2039 op
= BRW_MATH_FUNCTION_INV
;
2042 op
= BRW_MATH_FUNCTION_RSQ
;
2044 case FS_OPCODE_SQRT
:
2045 op
= BRW_MATH_FUNCTION_SQRT
;
2047 case FS_OPCODE_EXP2
:
2048 op
= BRW_MATH_FUNCTION_EXP
;
2050 case FS_OPCODE_LOG2
:
2051 op
= BRW_MATH_FUNCTION_LOG
;
2054 op
= BRW_MATH_FUNCTION_POW
;
2057 op
= BRW_MATH_FUNCTION_SIN
;
2060 op
= BRW_MATH_FUNCTION_COS
;
2063 assert(!"not reached: unknown math function");
2068 if (inst
->opcode
== FS_OPCODE_POW
) {
2069 brw_MOV(p
, brw_message_reg(3), src
[1]);
2074 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2075 BRW_MATH_SATURATE_NONE
,
2077 BRW_MATH_DATA_VECTOR
,
2078 BRW_MATH_PRECISION_FULL
);
2082 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2086 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2088 if (intel
->gen
>= 5) {
2089 switch (inst
->opcode
) {
2091 if (inst
->shadow_compare
) {
2092 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
2094 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
2098 if (inst
->shadow_compare
) {
2099 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
2101 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
2106 switch (inst
->opcode
) {
2108 /* Note that G45 and older determines shadow compare and dispatch width
2109 * from message length for most messages.
2111 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2112 if (inst
->shadow_compare
) {
2113 assert(inst
->mlen
== 5);
2115 assert(inst
->mlen
<= 6);
2119 if (inst
->shadow_compare
) {
2120 assert(inst
->mlen
== 5);
2121 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2123 assert(inst
->mlen
== 8);
2124 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2125 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2130 assert(msg_type
!= -1);
2132 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2141 retype(dst
, BRW_REGISTER_TYPE_UW
),
2143 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2144 SURF_INDEX_TEXTURE(inst
->sampler
),
2156 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2159 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2161 * and we're trying to produce:
2164 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2165 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2166 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2167 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2168 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2169 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2170 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2171 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2173 * and add another set of two more subspans if in 16-pixel dispatch mode.
2175 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2176 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2177 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2178 * between each other. We could probably do it like ddx and swizzle the right
2179 * order later, but bail for now and just produce
2180 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2183 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2185 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2186 BRW_REGISTER_TYPE_F
,
2187 BRW_VERTICAL_STRIDE_2
,
2189 BRW_HORIZONTAL_STRIDE_0
,
2190 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2191 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2192 BRW_REGISTER_TYPE_F
,
2193 BRW_VERTICAL_STRIDE_2
,
2195 BRW_HORIZONTAL_STRIDE_0
,
2196 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2197 brw_ADD(p
, dst
, src0
, negate(src1
));
2201 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2203 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2204 BRW_REGISTER_TYPE_F
,
2205 BRW_VERTICAL_STRIDE_4
,
2207 BRW_HORIZONTAL_STRIDE_0
,
2208 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2209 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2210 BRW_REGISTER_TYPE_F
,
2211 BRW_VERTICAL_STRIDE_4
,
2213 BRW_HORIZONTAL_STRIDE_0
,
2214 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2215 brw_ADD(p
, dst
, src0
, negate(src1
));
2219 fs_visitor::generate_discard(fs_inst
*inst
, struct brw_reg temp
)
2221 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2222 temp
= brw_uw1_reg(temp
.file
, temp
.nr
, 0);
2224 brw_push_insn_state(p
);
2225 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2226 brw_NOT(p
, temp
, brw_mask_reg(1)); /* IMASK */
2227 brw_AND(p
, g0
, temp
, g0
);
2228 brw_pop_insn_state(p
);
2232 fs_visitor::assign_curb_setup()
2234 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
2235 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2237 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2238 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2239 fs_inst
*inst
= (fs_inst
*)iter
.get();
2241 for (unsigned int i
= 0; i
< 3; i
++) {
2242 if (inst
->src
[i
].file
== UNIFORM
) {
2243 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2244 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2248 inst
->src
[i
].file
= FIXED_HW_REG
;
2249 inst
->src
[i
].fixed_hw_reg
= brw_reg
;
2256 fs_visitor::calculate_urb_setup()
2258 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2263 /* Figure out where each of the incoming setup attributes lands. */
2264 if (intel
->gen
>= 6) {
2265 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2266 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
2267 urb_setup
[i
] = urb_next
++;
2271 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2272 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2273 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2276 if (i
>= VERT_RESULT_VAR0
)
2277 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2278 else if (i
<= VERT_RESULT_TEX7
)
2284 urb_setup
[fp_index
] = urb_next
++;
2289 /* Each attribute is 4 setup channels, each of which is half a reg. */
2290 c
->prog_data
.urb_read_length
= urb_next
* 2;
2294 fs_visitor::assign_urb_setup()
2296 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2298 /* Offset all the urb_setup[] index by the actual position of the
2299 * setup regs, now that the location of the constants has been chosen.
2301 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2302 fs_inst
*inst
= (fs_inst
*)iter
.get();
2304 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
2307 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2309 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2312 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2316 assign_reg(int *reg_hw_locations
, fs_reg
*reg
)
2318 if (reg
->file
== GRF
&& reg
->reg
!= 0) {
2319 reg
->hw_reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
;
2325 fs_visitor::assign_regs_trivial()
2328 int hw_reg_mapping
[this->virtual_grf_next
];
2331 hw_reg_mapping
[0] = 0;
2332 hw_reg_mapping
[1] = this->first_non_payload_grf
;
2333 for (i
= 2; i
< this->virtual_grf_next
; i
++) {
2334 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
2335 this->virtual_grf_sizes
[i
- 1]);
2337 last_grf
= hw_reg_mapping
[i
- 1] + this->virtual_grf_sizes
[i
- 1];
2339 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2340 fs_inst
*inst
= (fs_inst
*)iter
.get();
2342 assign_reg(hw_reg_mapping
, &inst
->dst
);
2343 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2344 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2347 this->grf_used
= last_grf
+ 1;
2351 fs_visitor::assign_regs()
2354 int hw_reg_mapping
[this->virtual_grf_next
+ 1];
2355 int base_reg_count
= BRW_MAX_GRF
- this->first_non_payload_grf
;
2356 int class_sizes
[base_reg_count
];
2357 int class_count
= 0;
2358 int aligned_pair_class
= -1;
2360 /* Set up the register classes.
2362 * The base registers store a scalar value. For texture samples,
2363 * we get virtual GRFs composed of 4 contiguous hw register. For
2364 * structures and arrays, we store them as contiguous larger things
2365 * than that, though we should be able to do better most of the
2368 class_sizes
[class_count
++] = 1;
2369 if (brw
->has_pln
&& intel
->gen
< 6) {
2370 /* Always set up the (unaligned) pairs for gen5, so we can find
2371 * them for making the aligned pair class.
2373 class_sizes
[class_count
++] = 2;
2375 for (int r
= 1; r
< this->virtual_grf_next
; r
++) {
2378 for (i
= 0; i
< class_count
; i
++) {
2379 if (class_sizes
[i
] == this->virtual_grf_sizes
[r
])
2382 if (i
== class_count
) {
2383 if (this->virtual_grf_sizes
[r
] >= base_reg_count
) {
2384 fprintf(stderr
, "Object too large to register allocate.\n");
2388 class_sizes
[class_count
++] = this->virtual_grf_sizes
[r
];
2392 int ra_reg_count
= 0;
2393 int class_base_reg
[class_count
];
2394 int class_reg_count
[class_count
];
2395 int classes
[class_count
+ 1];
2397 for (int i
= 0; i
< class_count
; i
++) {
2398 class_base_reg
[i
] = ra_reg_count
;
2399 class_reg_count
[i
] = base_reg_count
- (class_sizes
[i
] - 1);
2400 ra_reg_count
+= class_reg_count
[i
];
2403 struct ra_regs
*regs
= ra_alloc_reg_set(ra_reg_count
);
2404 for (int i
= 0; i
< class_count
; i
++) {
2405 classes
[i
] = ra_alloc_reg_class(regs
);
2407 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2408 ra_class_add_reg(regs
, classes
[i
], class_base_reg
[i
] + i_r
);
2411 /* Add conflicts between our contiguous registers aliasing
2412 * base regs and other register classes' contiguous registers
2413 * that alias base regs, or the base regs themselves for classes[0].
2415 for (int c
= 0; c
<= i
; c
++) {
2416 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2417 for (int c_r
= MAX2(0, i_r
- (class_sizes
[c
] - 1));
2418 c_r
< MIN2(class_reg_count
[c
], i_r
+ class_sizes
[i
]);
2422 printf("%d/%d conflicts %d/%d\n",
2423 class_sizes
[i
], this->first_non_payload_grf
+ i_r
,
2424 class_sizes
[c
], this->first_non_payload_grf
+ c_r
);
2427 ra_add_reg_conflict(regs
,
2428 class_base_reg
[i
] + i_r
,
2429 class_base_reg
[c
] + c_r
);
2435 /* Add a special class for aligned pairs, which we'll put delta_x/y
2436 * in on gen5 so that we can do PLN.
2438 if (brw
->has_pln
&& intel
->gen
< 6) {
2439 int reg_count
= (base_reg_count
- 1) / 2;
2440 int unaligned_pair_class
= 1;
2441 assert(class_sizes
[unaligned_pair_class
] == 2);
2443 aligned_pair_class
= class_count
;
2444 classes
[aligned_pair_class
] = ra_alloc_reg_class(regs
);
2445 class_base_reg
[aligned_pair_class
] = 0;
2446 class_reg_count
[aligned_pair_class
] = 0;
2447 int start
= (this->first_non_payload_grf
& 1) ? 1 : 0;
2449 for (int i
= 0; i
< reg_count
; i
++) {
2450 ra_class_add_reg(regs
, classes
[aligned_pair_class
],
2451 class_base_reg
[unaligned_pair_class
] + i
* 2 + start
);
2456 ra_set_finalize(regs
);
2458 struct ra_graph
*g
= ra_alloc_interference_graph(regs
,
2459 this->virtual_grf_next
);
2460 /* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1
2463 ra_set_node_class(g
, 0, classes
[0]);
2465 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2466 for (int c
= 0; c
< class_count
; c
++) {
2467 if (class_sizes
[c
] == this->virtual_grf_sizes
[i
]) {
2468 if (aligned_pair_class
>= 0 &&
2469 this->delta_x
.reg
== i
) {
2470 ra_set_node_class(g
, i
, classes
[aligned_pair_class
]);
2472 ra_set_node_class(g
, i
, classes
[c
]);
2478 for (int j
= 1; j
< i
; j
++) {
2479 if (virtual_grf_interferes(i
, j
)) {
2480 ra_add_node_interference(g
, i
, j
);
2485 /* FINISHME: Handle spilling */
2486 if (!ra_allocate_no_spills(g
)) {
2487 fprintf(stderr
, "Failed to allocate registers.\n");
2492 /* Get the chosen virtual registers for each node, and map virtual
2493 * regs in the register classes back down to real hardware reg
2496 hw_reg_mapping
[0] = 0; /* unused */
2497 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2498 int reg
= ra_get_node_reg(g
, i
);
2501 for (int c
= 0; c
< class_count
; c
++) {
2502 if (reg
>= class_base_reg
[c
] &&
2503 reg
< class_base_reg
[c
] + class_reg_count
[c
]) {
2504 hw_reg
= reg
- class_base_reg
[c
];
2509 assert(hw_reg
!= -1);
2510 hw_reg_mapping
[i
] = this->first_non_payload_grf
+ hw_reg
;
2511 last_grf
= MAX2(last_grf
,
2512 hw_reg_mapping
[i
] + this->virtual_grf_sizes
[i
] - 1);
2515 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2516 fs_inst
*inst
= (fs_inst
*)iter
.get();
2518 assign_reg(hw_reg_mapping
, &inst
->dst
);
2519 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2520 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2523 this->grf_used
= last_grf
+ 1;
2530 fs_visitor::calculate_live_intervals()
2532 int num_vars
= this->virtual_grf_next
;
2533 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2534 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2538 for (int i
= 0; i
< num_vars
; i
++) {
2544 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2545 fs_inst
*inst
= (fs_inst
*)iter
.get();
2547 if (inst
->opcode
== BRW_OPCODE_DO
) {
2548 if (loop_depth
++ == 0)
2550 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2553 if (loop_depth
== 0) {
2556 * Patches up any vars marked for use within the loop as
2557 * live until the end. This is conservative, as there
2558 * will often be variables defined and used inside the
2559 * loop but dead at the end of the loop body.
2561 for (int i
= 0; i
< num_vars
; i
++) {
2562 if (use
[i
] == loop_start
) {
2573 for (unsigned int i
= 0; i
< 3; i
++) {
2574 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2575 use
[inst
->src
[i
].reg
] = MAX2(use
[inst
->src
[i
].reg
], eip
);
2578 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2579 def
[inst
->dst
.reg
] = MIN2(def
[inst
->dst
.reg
], eip
);
2586 talloc_free(this->virtual_grf_def
);
2587 talloc_free(this->virtual_grf_use
);
2588 this->virtual_grf_def
= def
;
2589 this->virtual_grf_use
= use
;
2593 * Attempts to move immediate constants into the immediate
2594 * constant slot of following instructions.
2596 * Immediate constants are a bit tricky -- they have to be in the last
2597 * operand slot, you can't do abs/negate on them,
2601 fs_visitor::propagate_constants()
2603 bool progress
= false;
2605 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2606 fs_inst
*inst
= (fs_inst
*)iter
.get();
2608 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2610 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2611 inst
->dst
.type
!= inst
->src
[0].type
)
2614 /* Don't bother with cases where we should have had the
2615 * operation on the constant folded in GLSL already.
2620 /* Found a move of a constant to a GRF. Find anything else using the GRF
2621 * before it's written, and replace it with the constant if we can.
2623 exec_list_iterator scan_iter
= iter
;
2625 for (; scan_iter
.has_next(); scan_iter
.next()) {
2626 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2628 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2629 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2630 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2631 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2635 for (int i
= 2; i
>= 0; i
--) {
2636 if (scan_inst
->src
[i
].file
!= GRF
||
2637 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2638 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2641 /* Don't bother with cases where we should have had the
2642 * operation on the constant folded in GLSL already.
2644 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2647 switch (scan_inst
->opcode
) {
2648 case BRW_OPCODE_MOV
:
2649 scan_inst
->src
[i
] = inst
->src
[0];
2653 case BRW_OPCODE_MUL
:
2654 case BRW_OPCODE_ADD
:
2656 scan_inst
->src
[i
] = inst
->src
[0];
2658 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2659 /* Fit this constant in by commuting the operands */
2660 scan_inst
->src
[0] = scan_inst
->src
[1];
2661 scan_inst
->src
[1] = inst
->src
[0];
2664 case BRW_OPCODE_CMP
:
2666 scan_inst
->src
[i
] = inst
->src
[0];
2672 if (scan_inst
->dst
.file
== GRF
&&
2673 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2674 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2675 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2684 * Must be called after calculate_live_intervales() to remove unused
2685 * writes to registers -- register allocation will fail otherwise
2686 * because something deffed but not used won't be considered to
2687 * interfere with other regs.
2690 fs_visitor::dead_code_eliminate()
2692 bool progress
= false;
2693 int num_vars
= this->virtual_grf_next
;
2694 bool dead
[num_vars
];
2696 for (int i
= 0; i
< num_vars
; i
++) {
2697 /* This would be ">=", but FS_OPCODE_DISCARD has a src == dst where
2698 * it writes dst then reads it as src.
2700 dead
[i
] = this->virtual_grf_def
[i
] > this->virtual_grf_use
[i
];
2703 /* Mark off its interval so it won't interfere with anything. */
2704 this->virtual_grf_def
[i
] = -1;
2705 this->virtual_grf_use
[i
] = -1;
2709 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2710 fs_inst
*inst
= (fs_inst
*)iter
.get();
2712 if (inst
->dst
.file
== GRF
&& dead
[inst
->dst
.reg
]) {
2722 fs_visitor::virtual_grf_interferes(int a
, int b
)
2724 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
2725 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
2727 /* For dead code, just check if the def interferes with the other range. */
2728 if (this->virtual_grf_use
[a
] == -1) {
2729 return (this->virtual_grf_def
[a
] >= this->virtual_grf_def
[b
] &&
2730 this->virtual_grf_def
[a
] < this->virtual_grf_use
[b
]);
2732 if (this->virtual_grf_use
[b
] == -1) {
2733 return (this->virtual_grf_def
[b
] >= this->virtual_grf_def
[a
] &&
2734 this->virtual_grf_def
[b
] < this->virtual_grf_use
[a
]);
2737 return start
<= end
;
2740 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
2742 struct brw_reg brw_reg
;
2744 switch (reg
->file
) {
2748 brw_reg
= brw_vec8_reg(reg
->file
,
2750 brw_reg
= retype(brw_reg
, reg
->type
);
2753 switch (reg
->type
) {
2754 case BRW_REGISTER_TYPE_F
:
2755 brw_reg
= brw_imm_f(reg
->imm
.f
);
2757 case BRW_REGISTER_TYPE_D
:
2758 brw_reg
= brw_imm_d(reg
->imm
.i
);
2760 case BRW_REGISTER_TYPE_UD
:
2761 brw_reg
= brw_imm_ud(reg
->imm
.u
);
2764 assert(!"not reached");
2769 brw_reg
= reg
->fixed_hw_reg
;
2772 /* Probably unused. */
2773 brw_reg
= brw_null_reg();
2776 assert(!"not reached");
2777 brw_reg
= brw_null_reg();
2781 brw_reg
= brw_abs(brw_reg
);
2783 brw_reg
= negate(brw_reg
);
2789 fs_visitor::generate_code()
2791 unsigned int annotation_len
= 0;
2792 int last_native_inst
= 0;
2793 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
2794 int if_stack_depth
= 0, loop_stack_depth
= 0;
2795 int if_depth_in_loop
[16];
2797 if_depth_in_loop
[loop_stack_depth
] = 0;
2799 memset(&if_stack
, 0, sizeof(if_stack
));
2800 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2801 fs_inst
*inst
= (fs_inst
*)iter
.get();
2802 struct brw_reg src
[3], dst
;
2804 for (unsigned int i
= 0; i
< 3; i
++) {
2805 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
2807 dst
= brw_reg_from_fs_reg(&inst
->dst
);
2809 brw_set_conditionalmod(p
, inst
->conditional_mod
);
2810 brw_set_predicate_control(p
, inst
->predicated
);
2812 switch (inst
->opcode
) {
2813 case BRW_OPCODE_MOV
:
2814 brw_MOV(p
, dst
, src
[0]);
2816 case BRW_OPCODE_ADD
:
2817 brw_ADD(p
, dst
, src
[0], src
[1]);
2819 case BRW_OPCODE_MUL
:
2820 brw_MUL(p
, dst
, src
[0], src
[1]);
2823 case BRW_OPCODE_FRC
:
2824 brw_FRC(p
, dst
, src
[0]);
2826 case BRW_OPCODE_RNDD
:
2827 brw_RNDD(p
, dst
, src
[0]);
2829 case BRW_OPCODE_RNDZ
:
2830 brw_RNDZ(p
, dst
, src
[0]);
2833 case BRW_OPCODE_AND
:
2834 brw_AND(p
, dst
, src
[0], src
[1]);
2837 brw_OR(p
, dst
, src
[0], src
[1]);
2839 case BRW_OPCODE_XOR
:
2840 brw_XOR(p
, dst
, src
[0], src
[1]);
2842 case BRW_OPCODE_NOT
:
2843 brw_NOT(p
, dst
, src
[0]);
2845 case BRW_OPCODE_ASR
:
2846 brw_ASR(p
, dst
, src
[0], src
[1]);
2848 case BRW_OPCODE_SHR
:
2849 brw_SHR(p
, dst
, src
[0], src
[1]);
2851 case BRW_OPCODE_SHL
:
2852 brw_SHL(p
, dst
, src
[0], src
[1]);
2855 case BRW_OPCODE_CMP
:
2856 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
2858 case BRW_OPCODE_SEL
:
2859 brw_SEL(p
, dst
, src
[0], src
[1]);
2863 assert(if_stack_depth
< 16);
2864 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
2865 if_depth_in_loop
[loop_stack_depth
]++;
2868 case BRW_OPCODE_ELSE
:
2869 if_stack
[if_stack_depth
- 1] =
2870 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
2872 case BRW_OPCODE_ENDIF
:
2874 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
2875 if_depth_in_loop
[loop_stack_depth
]--;
2879 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
2880 if_depth_in_loop
[loop_stack_depth
] = 0;
2883 case BRW_OPCODE_BREAK
:
2884 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
2885 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2887 case BRW_OPCODE_CONTINUE
:
2888 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
2889 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2892 case BRW_OPCODE_WHILE
: {
2893 struct brw_instruction
*inst0
, *inst1
;
2896 if (intel
->gen
>= 5)
2899 assert(loop_stack_depth
> 0);
2901 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
2902 /* patch all the BREAK/CONT instructions from last BGNLOOP */
2903 while (inst0
> loop_stack
[loop_stack_depth
]) {
2905 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
2906 inst0
->bits3
.if_else
.jump_count
== 0) {
2907 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
2909 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
2910 inst0
->bits3
.if_else
.jump_count
== 0) {
2911 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
2919 case FS_OPCODE_SQRT
:
2920 case FS_OPCODE_EXP2
:
2921 case FS_OPCODE_LOG2
:
2925 generate_math(inst
, dst
, src
);
2927 case FS_OPCODE_LINTERP
:
2928 generate_linterp(inst
, dst
, src
);
2933 generate_tex(inst
, dst
, src
[0]);
2935 case FS_OPCODE_DISCARD
:
2936 generate_discard(inst
, dst
/* src0 == dst */);
2939 generate_ddx(inst
, dst
, src
[0]);
2942 generate_ddy(inst
, dst
, src
[0]);
2944 case FS_OPCODE_FB_WRITE
:
2945 generate_fb_write(inst
);
2948 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
2949 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
2950 brw_opcodes
[inst
->opcode
].name
);
2952 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
2957 if (annotation_len
< p
->nr_insn
) {
2958 annotation_len
*= 2;
2959 if (annotation_len
< 16)
2960 annotation_len
= 16;
2962 this->annotation_string
= talloc_realloc(this->mem_ctx
,
2966 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
2972 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
2973 this->annotation_string
[i
] = inst
->annotation
;
2974 this->annotation_ir
[i
] = inst
->ir
;
2976 last_native_inst
= p
->nr_insn
;
2981 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
2983 struct brw_compile
*p
= &c
->func
;
2984 struct intel_context
*intel
= &brw
->intel
;
2985 GLcontext
*ctx
= &intel
->ctx
;
2986 struct brw_shader
*shader
= NULL
;
2987 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
2995 for (unsigned int i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
2996 if (prog
->_LinkedShaders
[i
]->Type
== GL_FRAGMENT_SHADER
) {
2997 shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
3004 /* We always use 8-wide mode, at least for now. For one, flow
3005 * control only works in 8-wide. Also, when we're fragment shader
3006 * bound, we're almost always under register pressure as well, so
3007 * 8-wide would save us from the performance cliff of spilling
3010 c
->dispatch_width
= 8;
3012 if (INTEL_DEBUG
& DEBUG_WM
) {
3013 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3014 _mesa_print_ir(shader
->ir
, NULL
);
3018 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3020 fs_visitor
v(c
, shader
);
3025 v
.calculate_urb_setup();
3027 v
.emit_interpolation_setup_gen4();
3029 v
.emit_interpolation_setup_gen6();
3031 /* Generate FS IR for main(). (the visitor only descends into
3032 * functions called "main").
3034 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
3035 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
3041 v
.assign_curb_setup();
3042 v
.assign_urb_setup();
3048 v
.calculate_live_intervals();
3049 progress
= v
.propagate_constants() || progress
;
3050 progress
= v
.dead_code_eliminate() || progress
;
3054 v
.assign_regs_trivial();
3062 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3067 if (INTEL_DEBUG
& DEBUG_WM
) {
3068 const char *last_annotation_string
= NULL
;
3069 ir_instruction
*last_annotation_ir
= NULL
;
3071 printf("Native code for fragment shader %d:\n", prog
->Name
);
3072 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
3073 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
3074 last_annotation_ir
= v
.annotation_ir
[i
];
3075 if (last_annotation_ir
) {
3077 last_annotation_ir
->print();
3081 if (last_annotation_string
!= v
.annotation_string
[i
]) {
3082 last_annotation_string
= v
.annotation_string
[i
];
3083 if (last_annotation_string
)
3084 printf(" %s\n", last_annotation_string
);
3086 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3091 c
->prog_data
.total_grf
= v
.grf_used
;
3092 c
->prog_data
.total_scratch
= 0;