2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
47 #include "../glsl/glsl_types.h"
48 #include "../glsl/ir_optimization.h"
49 #include "../glsl/ir_print_visitor.h"
51 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
54 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
56 struct brw_shader
*shader
;
58 shader
= talloc_zero(NULL
, struct brw_shader
);
60 shader
->base
.Type
= type
;
61 shader
->base
.Name
= name
;
62 _mesa_init_shader(ctx
, &shader
->base
);
68 struct gl_shader_program
*
69 brw_new_shader_program(struct gl_context
*ctx
, GLuint name
)
71 struct brw_shader_program
*prog
;
72 prog
= talloc_zero(NULL
, struct brw_shader_program
);
74 prog
->base
.Name
= name
;
75 _mesa_init_shader_program(ctx
, &prog
->base
);
81 brw_compile_shader(struct gl_context
*ctx
, struct gl_shader
*shader
)
83 if (!_mesa_ir_compile_shader(ctx
, shader
))
90 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
92 struct intel_context
*intel
= intel_context(ctx
);
94 struct brw_shader
*shader
=
95 (struct brw_shader
*)prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
97 void *mem_ctx
= talloc_new(NULL
);
101 talloc_free(shader
->ir
);
102 shader
->ir
= new(shader
) exec_list
;
103 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
105 do_mat_op_to_vec(shader
->ir
);
106 do_mod_to_fract(shader
->ir
);
107 do_div_to_mul_rcp(shader
->ir
);
108 do_sub_to_add_neg(shader
->ir
);
109 do_explog_to_explog2(shader
->ir
);
110 do_lower_texture_projection(shader
->ir
);
111 brw_do_cubemap_normalize(shader
->ir
);
116 brw_do_channel_expressions(shader
->ir
);
117 brw_do_vector_splitting(shader
->ir
);
119 progress
= do_lower_jumps(shader
->ir
, true, true,
120 true, /* main return */
121 false, /* continue */
125 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
127 progress
= lower_noise(shader
->ir
) || progress
;
129 lower_variable_index_to_cond_assign(shader
->ir
,
131 GL_TRUE
, /* output */
133 GL_TRUE
/* uniform */
135 if (intel
->gen
== 6) {
136 progress
= do_if_to_cond_assign(shader
->ir
) || progress
;
140 validate_ir_tree(shader
->ir
);
142 reparent_ir(shader
->ir
, shader
->ir
);
143 talloc_free(mem_ctx
);
146 if (!_mesa_ir_link_shader(ctx
, prog
))
153 type_size(const struct glsl_type
*type
)
155 unsigned int size
, i
;
157 switch (type
->base_type
) {
160 case GLSL_TYPE_FLOAT
:
162 return type
->components();
163 case GLSL_TYPE_ARRAY
:
164 return type_size(type
->fields
.array
) * type
->length
;
165 case GLSL_TYPE_STRUCT
:
167 for (i
= 0; i
< type
->length
; i
++) {
168 size
+= type_size(type
->fields
.structure
[i
].type
);
171 case GLSL_TYPE_SAMPLER
:
172 /* Samplers take up no register space, since they're baked in at
177 assert(!"not reached");
182 static const fs_reg reg_undef
;
183 static const fs_reg
reg_null_f(ARF
, BRW_ARF_NULL
, BRW_REGISTER_TYPE_F
);
184 static const fs_reg
reg_null_d(ARF
, BRW_ARF_NULL
, BRW_REGISTER_TYPE_D
);
187 fs_visitor::virtual_grf_alloc(int size
)
189 if (virtual_grf_array_size
<= virtual_grf_next
) {
190 if (virtual_grf_array_size
== 0)
191 virtual_grf_array_size
= 16;
193 virtual_grf_array_size
*= 2;
194 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
195 int, virtual_grf_array_size
);
197 /* This slot is always unused. */
198 virtual_grf_sizes
[0] = 0;
200 virtual_grf_sizes
[virtual_grf_next
] = size
;
201 return virtual_grf_next
++;
204 /** Fixed HW reg constructor. */
205 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
209 this->hw_reg
= hw_reg
;
210 this->type
= BRW_REGISTER_TYPE_F
;
213 /** Fixed HW reg constructor. */
214 fs_reg::fs_reg(enum register_file file
, int hw_reg
, uint32_t type
)
218 this->hw_reg
= hw_reg
;
223 brw_type_for_base_type(const struct glsl_type
*type
)
225 switch (type
->base_type
) {
226 case GLSL_TYPE_FLOAT
:
227 return BRW_REGISTER_TYPE_F
;
230 return BRW_REGISTER_TYPE_D
;
232 return BRW_REGISTER_TYPE_UD
;
233 case GLSL_TYPE_ARRAY
:
234 case GLSL_TYPE_STRUCT
:
235 /* These should be overridden with the type of the member when
236 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
237 * way to trip up if we don't.
239 return BRW_REGISTER_TYPE_UD
;
241 assert(!"not reached");
242 return BRW_REGISTER_TYPE_F
;
246 /** Automatic reg constructor. */
247 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
252 this->reg
= v
->virtual_grf_alloc(type_size(type
));
253 this->reg_offset
= 0;
254 this->type
= brw_type_for_base_type(type
);
258 fs_visitor::variable_storage(ir_variable
*var
)
260 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
263 /* Our support for uniforms is piggy-backed on the struct
264 * gl_fragment_program, because that's where the values actually
265 * get stored, rather than in some global gl_shader_program uniform
269 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
271 unsigned int offset
= 0;
274 if (type
->is_matrix()) {
275 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
276 type
->vector_elements
,
279 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
280 offset
+= setup_uniform_values(loc
+ offset
, column
);
286 switch (type
->base_type
) {
287 case GLSL_TYPE_FLOAT
:
291 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
292 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
293 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
297 case GLSL_TYPE_STRUCT
:
298 for (unsigned int i
= 0; i
< type
->length
; i
++) {
299 offset
+= setup_uniform_values(loc
+ offset
,
300 type
->fields
.structure
[i
].type
);
304 case GLSL_TYPE_ARRAY
:
305 for (unsigned int i
= 0; i
< type
->length
; i
++) {
306 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
310 case GLSL_TYPE_SAMPLER
:
311 /* The sampler takes up a slot, but we don't use any values from it. */
315 assert(!"not reached");
321 /* Our support for builtin uniforms is even scarier than non-builtin.
322 * It sits on top of the PROG_STATE_VAR parameters that are
323 * automatically updated from GL context state.
326 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
328 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
330 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
331 statevar
= &_mesa_builtin_uniform_desc
[i
];
332 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
336 if (!statevar
->name
) {
338 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
343 if (ir
->type
->is_array()) {
344 array_count
= ir
->type
->length
;
349 for (int a
= 0; a
< array_count
; a
++) {
350 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
351 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
352 int tokens
[STATE_LENGTH
];
354 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
355 if (ir
->type
->is_array()) {
359 /* This state reference has already been setup by ir_to_mesa,
360 * but we'll get the same index back here.
362 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
363 (gl_state_index
*)tokens
);
364 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
366 /* Add each of the unique swizzles of the element as a
367 * parameter. This'll end up matching the expected layout of
368 * the array/matrix/structure we're trying to fill in.
371 for (unsigned int i
= 0; i
< 4; i
++) {
372 int swiz
= GET_SWZ(element
->swizzle
, i
);
373 if (swiz
== last_swiz
)
377 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
384 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
386 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
388 fs_reg neg_y
= this->pixel_y
;
392 if (ir
->pixel_center_integer
) {
393 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
395 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
400 if (ir
->origin_upper_left
&& ir
->pixel_center_integer
) {
401 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
403 fs_reg pixel_y
= this->pixel_y
;
404 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
406 if (!ir
->origin_upper_left
) {
407 pixel_y
.negate
= true;
408 offset
+= c
->key
.drawable_height
- 1.0;
411 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
416 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
417 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
420 /* gl_FragCoord.w: Already set up in emit_interpolation */
421 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
427 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
429 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
430 /* Interpolation is always in floating point regs. */
431 reg
->type
= BRW_REGISTER_TYPE_F
;
434 unsigned int array_elements
;
435 const glsl_type
*type
;
437 if (ir
->type
->is_array()) {
438 array_elements
= ir
->type
->length
;
439 if (array_elements
== 0) {
442 type
= ir
->type
->fields
.array
;
448 int location
= ir
->location
;
449 for (unsigned int i
= 0; i
< array_elements
; i
++) {
450 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
451 if (urb_setup
[location
] == -1) {
452 /* If there's no incoming setup data for this slot, don't
453 * emit interpolation for it.
455 attr
.reg_offset
+= type
->vector_elements
;
460 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
461 struct brw_reg interp
= interp_reg(location
, c
);
462 emit(fs_inst(FS_OPCODE_LINTERP
,
470 if (intel
->gen
< 6) {
471 attr
.reg_offset
-= type
->vector_elements
;
472 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
473 emit(fs_inst(BRW_OPCODE_MUL
,
488 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
490 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
492 /* The frontfacing comes in as a bit in the thread payload. */
493 if (intel
->gen
>= 6) {
494 emit(fs_inst(BRW_OPCODE_ASR
,
496 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
498 emit(fs_inst(BRW_OPCODE_NOT
,
501 emit(fs_inst(BRW_OPCODE_AND
,
506 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
507 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
508 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
511 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
515 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
516 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
523 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src
)
535 assert(!"not reached: bad math opcode");
539 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
540 * might be able to do better by doing execsize = 1 math and then
541 * expanding that result out, but we would need to be careful with
544 if (intel
->gen
>= 6 && src
.file
== UNIFORM
) {
545 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
546 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src
));
550 fs_inst
*inst
= emit(fs_inst(opcode
, dst
, src
));
552 if (intel
->gen
< 6) {
561 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
566 assert(opcode
== FS_OPCODE_POW
);
568 if (intel
->gen
>= 6) {
569 /* Can't do hstride == 0 args to gen6 math, so expand it out. */
570 if (src0
.file
== UNIFORM
) {
571 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
572 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src0
));
576 if (src1
.file
== UNIFORM
) {
577 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
578 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src1
));
582 inst
= emit(fs_inst(opcode
, dst
, src0
, src1
));
584 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1), src1
));
585 inst
= emit(fs_inst(opcode
, dst
, src0
, reg_null_f
));
587 inst
->base_mrf
= base_mrf
;
594 fs_visitor::visit(ir_variable
*ir
)
598 if (variable_storage(ir
))
601 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
602 this->frag_color
= ir
;
603 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
604 this->frag_data
= ir
;
605 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
606 this->frag_depth
= ir
;
609 if (ir
->mode
== ir_var_in
) {
610 if (!strcmp(ir
->name
, "gl_FragCoord")) {
611 reg
= emit_fragcoord_interpolation(ir
);
612 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
613 reg
= emit_frontfacing_interpolation(ir
);
615 reg
= emit_general_interpolation(ir
);
618 hash_table_insert(this->variable_ht
, reg
, ir
);
622 if (ir
->mode
== ir_var_uniform
) {
623 int param_index
= c
->prog_data
.nr_params
;
625 if (!strncmp(ir
->name
, "gl_", 3)) {
626 setup_builtin_uniform_values(ir
);
628 setup_uniform_values(ir
->location
, ir
->type
);
631 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
635 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
637 hash_table_insert(this->variable_ht
, reg
, ir
);
641 fs_visitor::visit(ir_dereference_variable
*ir
)
643 fs_reg
*reg
= variable_storage(ir
->var
);
648 fs_visitor::visit(ir_dereference_record
*ir
)
650 const glsl_type
*struct_type
= ir
->record
->type
;
652 ir
->record
->accept(this);
654 unsigned int offset
= 0;
655 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
656 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
658 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
660 this->result
.reg_offset
+= offset
;
661 this->result
.type
= brw_type_for_base_type(ir
->type
);
665 fs_visitor::visit(ir_dereference_array
*ir
)
670 ir
->array
->accept(this);
671 index
= ir
->array_index
->as_constant();
673 element_size
= type_size(ir
->type
);
674 this->result
.type
= brw_type_for_base_type(ir
->type
);
677 assert(this->result
.file
== UNIFORM
||
678 (this->result
.file
== GRF
&&
679 this->result
.reg
!= 0));
680 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
682 assert(!"FINISHME: non-constant array element");
687 fs_visitor::visit(ir_expression
*ir
)
689 unsigned int operand
;
693 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
694 ir
->operands
[operand
]->accept(this);
695 if (this->result
.file
== BAD_FILE
) {
697 printf("Failed to get tree for expression operand:\n");
698 ir
->operands
[operand
]->accept(&v
);
701 op
[operand
] = this->result
;
703 /* Matrix expression operands should have been broken down to vector
704 * operations already.
706 assert(!ir
->operands
[operand
]->type
->is_matrix());
707 /* And then those vector operands should have been broken down to scalar.
709 assert(!ir
->operands
[operand
]->type
->is_vector());
712 /* Storage for our result. If our result goes into an assignment, it will
713 * just get copy-propagated out, so no worries.
715 this->result
= fs_reg(this, ir
->type
);
717 switch (ir
->operation
) {
718 case ir_unop_logic_not
:
719 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
720 * ones complement of the whole register, not just bit 0.
722 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1)));
725 op
[0].negate
= !op
[0].negate
;
726 this->result
= op
[0];
730 this->result
= op
[0];
733 temp
= fs_reg(this, ir
->type
);
735 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
737 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
738 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
739 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
740 inst
->predicated
= true;
742 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
743 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
744 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
745 inst
->predicated
= true;
749 emit_math(FS_OPCODE_RCP
, this->result
, op
[0]);
753 emit_math(FS_OPCODE_EXP2
, this->result
, op
[0]);
756 emit_math(FS_OPCODE_LOG2
, this->result
, op
[0]);
760 assert(!"not reached: should be handled by ir_explog_to_explog2");
763 emit_math(FS_OPCODE_SIN
, this->result
, op
[0]);
766 emit_math(FS_OPCODE_COS
, this->result
, op
[0]);
770 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
773 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
777 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
780 assert(!"not reached: should be handled by ir_sub_to_add_neg");
784 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
787 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
790 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
794 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
795 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
796 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
798 case ir_binop_greater
:
799 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
800 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
801 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
803 case ir_binop_lequal
:
804 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
805 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
806 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
808 case ir_binop_gequal
:
809 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
810 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
811 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
814 case ir_binop_all_equal
: /* same as nequal for scalars */
815 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
816 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
817 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
819 case ir_binop_nequal
:
820 case ir_binop_any_nequal
: /* same as nequal for scalars */
821 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
822 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
823 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
826 case ir_binop_logic_xor
:
827 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
830 case ir_binop_logic_or
:
831 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
834 case ir_binop_logic_and
:
835 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
841 assert(!"not reached: should be handled by brw_fs_channel_expressions");
845 assert(!"not reached: should be handled by lower_noise");
849 emit_math(FS_OPCODE_SQRT
, this->result
, op
[0]);
853 emit_math(FS_OPCODE_RSQ
, this->result
, op
[0]);
860 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
864 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
865 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
866 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
,
867 this->result
, fs_reg(1)));
871 emit(fs_inst(BRW_OPCODE_RNDZ
, this->result
, op
[0]));
874 op
[0].negate
= !op
[0].negate
;
875 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
876 this->result
.negate
= true;
879 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
882 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
884 case ir_unop_round_even
:
885 emit(fs_inst(BRW_OPCODE_RNDE
, this->result
, op
[0]));
889 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
890 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
892 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
893 inst
->predicated
= true;
896 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
897 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
899 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
900 inst
->predicated
= true;
904 emit_math(FS_OPCODE_POW
, this->result
, op
[0], op
[1]);
907 case ir_unop_bit_not
:
909 case ir_binop_lshift
:
910 case ir_binop_rshift
:
911 case ir_binop_bit_and
:
912 case ir_binop_bit_xor
:
913 case ir_binop_bit_or
:
914 assert(!"GLSL 1.30 features unsupported");
920 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
921 const glsl_type
*type
, bool predicated
)
923 switch (type
->base_type
) {
924 case GLSL_TYPE_FLOAT
:
928 for (unsigned int i
= 0; i
< type
->components(); i
++) {
929 l
.type
= brw_type_for_base_type(type
);
930 r
.type
= brw_type_for_base_type(type
);
932 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
933 inst
->predicated
= predicated
;
939 case GLSL_TYPE_ARRAY
:
940 for (unsigned int i
= 0; i
< type
->length
; i
++) {
941 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
945 case GLSL_TYPE_STRUCT
:
946 for (unsigned int i
= 0; i
< type
->length
; i
++) {
947 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
952 case GLSL_TYPE_SAMPLER
:
956 assert(!"not reached");
962 fs_visitor::visit(ir_assignment
*ir
)
967 /* FINISHME: arrays on the lhs */
968 ir
->lhs
->accept(this);
971 ir
->rhs
->accept(this);
974 assert(l
.file
!= BAD_FILE
);
975 assert(r
.file
!= BAD_FILE
);
978 emit_bool_to_cond_code(ir
->condition
);
981 if (ir
->lhs
->type
->is_scalar() ||
982 ir
->lhs
->type
->is_vector()) {
983 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
984 if (ir
->write_mask
& (1 << i
)) {
985 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
987 inst
->predicated
= true;
993 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
998 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1002 bool simd16
= false;
1008 if (ir
->shadow_comparitor
) {
1009 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1010 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1012 coordinate
.reg_offset
++;
1014 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1017 if (ir
->op
== ir_tex
) {
1018 /* There's no plain shadow compare message, so we use shadow
1019 * compare with a bias of 0.0.
1021 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1024 } else if (ir
->op
== ir_txb
) {
1025 ir
->lod_info
.bias
->accept(this);
1026 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1030 assert(ir
->op
== ir_txl
);
1031 ir
->lod_info
.lod
->accept(this);
1032 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1037 ir
->shadow_comparitor
->accept(this);
1038 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1040 } else if (ir
->op
== ir_tex
) {
1041 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1042 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1044 coordinate
.reg_offset
++;
1046 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1049 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1050 * instructions. We'll need to do SIMD16 here.
1052 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1054 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1055 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2),
1057 coordinate
.reg_offset
++;
1060 /* lod/bias appears after u/v/r. */
1063 if (ir
->op
== ir_txb
) {
1064 ir
->lod_info
.bias
->accept(this);
1065 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1069 ir
->lod_info
.lod
->accept(this);
1070 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1075 /* The unused upper half. */
1078 /* Now, since we're doing simd16, the return is 2 interleaved
1079 * vec4s where the odd-indexed ones are junk. We'll need to move
1080 * this weirdness around to the expected layout.
1084 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1086 dst
.type
= BRW_REGISTER_TYPE_F
;
1089 fs_inst
*inst
= NULL
;
1092 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1095 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1098 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1102 assert(!"GLSL 1.30 features unsupported");
1105 inst
->base_mrf
= base_mrf
;
1109 for (int i
= 0; i
< 4; i
++) {
1110 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1111 orig_dst
.reg_offset
++;
1112 dst
.reg_offset
+= 2;
1120 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1122 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1123 * optional parameters like shadow comparitor or LOD bias. If
1124 * optional parameters aren't present, those base slots are
1125 * optional and don't need to be included in the message.
1127 * We don't fill in the unnecessary slots regardless, which may
1128 * look surprising in the disassembly.
1130 int mlen
= 1; /* g0 header always present. */
1133 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1134 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1136 coordinate
.reg_offset
++;
1138 mlen
+= ir
->coordinate
->type
->vector_elements
;
1140 if (ir
->shadow_comparitor
) {
1141 mlen
= MAX2(mlen
, 5);
1143 ir
->shadow_comparitor
->accept(this);
1144 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1148 fs_inst
*inst
= NULL
;
1151 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1154 ir
->lod_info
.bias
->accept(this);
1155 mlen
= MAX2(mlen
, 5);
1156 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1159 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1162 ir
->lod_info
.lod
->accept(this);
1163 mlen
= MAX2(mlen
, 5);
1164 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1167 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1171 assert(!"GLSL 1.30 features unsupported");
1174 inst
->base_mrf
= base_mrf
;
1181 fs_visitor::visit(ir_texture
*ir
)
1184 fs_inst
*inst
= NULL
;
1186 ir
->coordinate
->accept(this);
1187 fs_reg coordinate
= this->result
;
1189 /* Should be lowered by do_lower_texture_projection */
1190 assert(!ir
->projector
);
1192 sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
1193 ctx
->Shader
.CurrentProgram
,
1194 &brw
->fragment_program
->Base
);
1195 sampler
= c
->fp
->program
.Base
.SamplerUnits
[sampler
];
1197 /* The 965 requires the EU to do the normalization of GL rectangle
1198 * texture coordinates. We use the program parameter state
1199 * tracking to get the scaling factor.
1201 if (ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1202 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1203 int tokens
[STATE_LENGTH
] = {
1205 STATE_TEXRECT_SCALE
,
1211 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1212 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1213 GLuint index
= _mesa_add_state_reference(params
,
1214 (gl_state_index
*)tokens
);
1215 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
1217 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[0];
1218 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[1];
1220 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1221 fs_reg src
= coordinate
;
1224 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_x
));
1227 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_y
));
1230 /* Writemasking doesn't eliminate channels on SIMD8 texture
1231 * samples, so don't worry about them.
1233 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1235 if (intel
->gen
< 5) {
1236 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1238 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1241 inst
->sampler
= sampler
;
1245 if (ir
->shadow_comparitor
)
1246 inst
->shadow_compare
= true;
1248 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1249 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1251 for (int i
= 0; i
< 4; i
++) {
1252 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1253 fs_reg l
= swizzle_dst
;
1256 if (swiz
== SWIZZLE_ZERO
) {
1257 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1258 } else if (swiz
== SWIZZLE_ONE
) {
1259 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1262 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1263 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1266 this->result
= swizzle_dst
;
1271 fs_visitor::visit(ir_swizzle
*ir
)
1273 ir
->val
->accept(this);
1274 fs_reg val
= this->result
;
1276 if (ir
->type
->vector_elements
== 1) {
1277 this->result
.reg_offset
+= ir
->mask
.x
;
1281 fs_reg result
= fs_reg(this, ir
->type
);
1282 this->result
= result
;
1284 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1285 fs_reg channel
= val
;
1303 channel
.reg_offset
+= swiz
;
1304 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1305 result
.reg_offset
++;
1310 fs_visitor::visit(ir_discard
*ir
)
1312 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1314 assert(ir
->condition
== NULL
); /* FINISHME */
1316 emit(fs_inst(FS_OPCODE_DISCARD_NOT
, temp
, reg_null_d
));
1317 emit(fs_inst(FS_OPCODE_DISCARD_AND
, reg_null_d
, temp
));
1318 kill_emitted
= true;
1322 fs_visitor::visit(ir_constant
*ir
)
1324 fs_reg
reg(this, ir
->type
);
1327 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1328 switch (ir
->type
->base_type
) {
1329 case GLSL_TYPE_FLOAT
:
1330 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
1332 case GLSL_TYPE_UINT
:
1333 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1336 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1338 case GLSL_TYPE_BOOL
:
1339 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1342 assert(!"Non-float/uint/int/bool constant");
1349 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1351 ir_expression
*expr
= ir
->as_expression();
1357 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1358 assert(expr
->operands
[i
]->type
->is_scalar());
1360 expr
->operands
[i
]->accept(this);
1361 op
[i
] = this->result
;
1364 switch (expr
->operation
) {
1365 case ir_unop_logic_not
:
1366 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1)));
1367 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1370 case ir_binop_logic_xor
:
1371 inst
= emit(fs_inst(BRW_OPCODE_XOR
, reg_null_d
, op
[0], op
[1]));
1372 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1375 case ir_binop_logic_or
:
1376 inst
= emit(fs_inst(BRW_OPCODE_OR
, reg_null_d
, op
[0], op
[1]));
1377 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1380 case ir_binop_logic_and
:
1381 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], op
[1]));
1382 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1386 if (intel
->gen
>= 6) {
1387 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
,
1388 op
[0], fs_reg(0.0f
)));
1390 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, op
[0]));
1392 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1396 if (intel
->gen
>= 6) {
1397 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0)));
1399 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, op
[0]));
1401 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1404 case ir_binop_greater
:
1405 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1406 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1408 case ir_binop_gequal
:
1409 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1410 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1413 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1414 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1416 case ir_binop_lequal
:
1417 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1418 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1420 case ir_binop_equal
:
1421 case ir_binop_all_equal
:
1422 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1423 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1425 case ir_binop_nequal
:
1426 case ir_binop_any_nequal
:
1427 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1428 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1431 assert(!"not reached");
1440 if (intel
->gen
>= 6) {
1441 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
,
1442 this->result
, fs_reg(1)));
1443 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1445 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, this->result
));
1446 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1451 * Emit a gen6 IF statement with the comparison folded into the IF
1455 fs_visitor::emit_if_gen6(ir_if
*ir
)
1457 ir_expression
*expr
= ir
->condition
->as_expression();
1464 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1465 assert(expr
->operands
[i
]->type
->is_scalar());
1467 expr
->operands
[i
]->accept(this);
1468 op
[i
] = this->result
;
1471 switch (expr
->operation
) {
1472 case ir_unop_logic_not
:
1473 inst
= emit(fs_inst(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(1)));
1474 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1477 case ir_binop_logic_xor
:
1478 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1479 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1482 case ir_binop_logic_or
:
1483 temp
= fs_reg(this, glsl_type::bool_type
);
1484 emit(fs_inst(BRW_OPCODE_OR
, temp
, op
[0], op
[1]));
1485 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1486 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1489 case ir_binop_logic_and
:
1490 temp
= fs_reg(this, glsl_type::bool_type
);
1491 emit(fs_inst(BRW_OPCODE_AND
, temp
, op
[0], op
[1]));
1492 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1493 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1497 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0)));
1498 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1502 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1503 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1506 case ir_binop_greater
:
1507 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1508 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1510 case ir_binop_gequal
:
1511 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1512 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1515 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1516 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1518 case ir_binop_lequal
:
1519 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1520 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1522 case ir_binop_equal
:
1523 case ir_binop_all_equal
:
1524 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1525 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1527 case ir_binop_nequal
:
1528 case ir_binop_any_nequal
:
1529 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1530 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1533 assert(!"not reached");
1534 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1535 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1542 ir
->condition
->accept(this);
1544 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0)));
1545 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1549 fs_visitor::visit(ir_if
*ir
)
1553 /* Don't point the annotation at the if statement, because then it plus
1554 * the then and else blocks get printed.
1556 this->base_ir
= ir
->condition
;
1558 if (intel
->gen
>= 6) {
1561 emit_bool_to_cond_code(ir
->condition
);
1563 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1564 inst
->predicated
= true;
1567 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1568 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1574 if (!ir
->else_instructions
.is_empty()) {
1575 emit(fs_inst(BRW_OPCODE_ELSE
));
1577 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1578 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1585 emit(fs_inst(BRW_OPCODE_ENDIF
));
1589 fs_visitor::visit(ir_loop
*ir
)
1591 fs_reg counter
= reg_undef
;
1594 this->base_ir
= ir
->counter
;
1595 ir
->counter
->accept(this);
1596 counter
= *(variable_storage(ir
->counter
));
1599 this->base_ir
= ir
->from
;
1600 ir
->from
->accept(this);
1602 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1606 emit(fs_inst(BRW_OPCODE_DO
));
1609 this->base_ir
= ir
->to
;
1610 ir
->to
->accept(this);
1612 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
,
1613 counter
, this->result
));
1615 case ir_binop_equal
:
1616 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1618 case ir_binop_nequal
:
1619 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1621 case ir_binop_gequal
:
1622 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1624 case ir_binop_lequal
:
1625 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1627 case ir_binop_greater
:
1628 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1631 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1634 assert(!"not reached: unknown loop condition");
1639 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1640 inst
->predicated
= true;
1643 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1644 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1650 if (ir
->increment
) {
1651 this->base_ir
= ir
->increment
;
1652 ir
->increment
->accept(this);
1653 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1656 emit(fs_inst(BRW_OPCODE_WHILE
));
1660 fs_visitor::visit(ir_loop_jump
*ir
)
1663 case ir_loop_jump::jump_break
:
1664 emit(fs_inst(BRW_OPCODE_BREAK
));
1666 case ir_loop_jump::jump_continue
:
1667 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1673 fs_visitor::visit(ir_call
*ir
)
1675 assert(!"FINISHME");
1679 fs_visitor::visit(ir_return
*ir
)
1681 assert(!"FINISHME");
1685 fs_visitor::visit(ir_function
*ir
)
1687 /* Ignore function bodies other than main() -- we shouldn't see calls to
1688 * them since they should all be inlined before we get to ir_to_mesa.
1690 if (strcmp(ir
->name
, "main") == 0) {
1691 const ir_function_signature
*sig
;
1694 sig
= ir
->matching_signature(&empty
);
1698 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1699 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1708 fs_visitor::visit(ir_function_signature
*ir
)
1710 assert(!"not reached");
1715 fs_visitor::emit(fs_inst inst
)
1717 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1720 list_inst
->annotation
= this->current_annotation
;
1721 list_inst
->ir
= this->base_ir
;
1723 this->instructions
.push_tail(list_inst
);
1728 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1730 fs_visitor::emit_dummy_fs()
1732 /* Everyone's favorite color. */
1733 emit(fs_inst(BRW_OPCODE_MOV
,
1736 emit(fs_inst(BRW_OPCODE_MOV
,
1739 emit(fs_inst(BRW_OPCODE_MOV
,
1742 emit(fs_inst(BRW_OPCODE_MOV
,
1747 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1750 write
->base_mrf
= 0;
1753 /* The register location here is relative to the start of the URB
1754 * data. It will get adjusted to be a real location before
1755 * generate_code() time.
1758 fs_visitor::interp_reg(int location
, int channel
)
1760 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1761 int stride
= (channel
& 1) * 4;
1763 assert(urb_setup
[location
] != -1);
1765 return brw_vec1_grf(regnr
, stride
);
1768 /** Emits the interpolation for the varying inputs. */
1770 fs_visitor::emit_interpolation_setup_gen4()
1772 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1774 this->current_annotation
= "compute pixel centers";
1775 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1776 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1777 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1778 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1779 emit(fs_inst(BRW_OPCODE_ADD
,
1781 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1782 fs_reg(brw_imm_v(0x10101010))));
1783 emit(fs_inst(BRW_OPCODE_ADD
,
1785 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1786 fs_reg(brw_imm_v(0x11001100))));
1788 this->current_annotation
= "compute pixel deltas from v0";
1790 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1791 this->delta_y
= this->delta_x
;
1792 this->delta_y
.reg_offset
++;
1794 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1795 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1797 emit(fs_inst(BRW_OPCODE_ADD
,
1800 fs_reg(negate(brw_vec1_grf(1, 0)))));
1801 emit(fs_inst(BRW_OPCODE_ADD
,
1804 fs_reg(negate(brw_vec1_grf(1, 1)))));
1806 this->current_annotation
= "compute pos.w and 1/pos.w";
1807 /* Compute wpos.w. It's always in our setup, since it's needed to
1808 * interpolate the other attributes.
1810 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1811 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1812 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1813 /* Compute the pixel 1/W value from wpos.w. */
1814 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1815 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1816 this->current_annotation
= NULL
;
1819 /** Emits the interpolation for the varying inputs. */
1821 fs_visitor::emit_interpolation_setup_gen6()
1823 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1825 /* If the pixel centers end up used, the setup is the same as for gen4. */
1826 this->current_annotation
= "compute pixel centers";
1827 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1828 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1829 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1830 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1831 emit(fs_inst(BRW_OPCODE_ADD
,
1833 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1834 fs_reg(brw_imm_v(0x10101010))));
1835 emit(fs_inst(BRW_OPCODE_ADD
,
1837 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1838 fs_reg(brw_imm_v(0x11001100))));
1840 /* As of gen6, we can no longer mix float and int sources. We have
1841 * to turn the integer pixel centers into floats for their actual
1844 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1845 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1846 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
));
1847 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
));
1849 this->current_annotation
= "compute 1/pos.w";
1850 this->wpos_w
= fs_reg(brw_vec8_grf(c
->key
.source_w_reg
, 0));
1851 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1852 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1854 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1855 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1857 this->current_annotation
= NULL
;
1861 fs_visitor::emit_fb_writes()
1863 this->current_annotation
= "FB write header";
1864 GLboolean header_present
= GL_TRUE
;
1867 if (intel
->gen
>= 6 &&
1868 !this->kill_emitted
&&
1869 c
->key
.nr_color_regions
== 1) {
1870 header_present
= false;
1873 if (header_present
) {
1878 if (c
->key
.aa_dest_stencil_reg
) {
1879 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1880 fs_reg(brw_vec8_grf(c
->key
.aa_dest_stencil_reg
, 0))));
1883 /* Reserve space for color. It'll be filled in per MRT below. */
1887 if (c
->key
.source_depth_to_render_target
) {
1888 if (c
->key
.computes_depth
) {
1889 /* Hand over gl_FragDepth. */
1890 assert(this->frag_depth
);
1891 fs_reg depth
= *(variable_storage(this->frag_depth
));
1893 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
1895 /* Pass through the payload depth. */
1896 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1897 fs_reg(brw_vec8_grf(c
->key
.source_depth_reg
, 0))));
1901 if (c
->key
.dest_depth_reg
) {
1902 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1903 fs_reg(brw_vec8_grf(c
->key
.dest_depth_reg
, 0))));
1906 fs_reg color
= reg_undef
;
1907 if (this->frag_color
)
1908 color
= *(variable_storage(this->frag_color
));
1909 else if (this->frag_data
)
1910 color
= *(variable_storage(this->frag_data
));
1912 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1913 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1914 "FB write target %d",
1916 if (this->frag_color
|| this->frag_data
) {
1917 for (int i
= 0; i
< 4; i
++) {
1918 emit(fs_inst(BRW_OPCODE_MOV
,
1919 fs_reg(MRF
, color_mrf
+ i
),
1925 if (this->frag_color
)
1926 color
.reg_offset
-= 4;
1928 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1929 reg_undef
, reg_undef
));
1930 inst
->target
= target
;
1933 if (target
== c
->key
.nr_color_regions
- 1)
1935 inst
->header_present
= header_present
;
1938 if (c
->key
.nr_color_regions
== 0) {
1939 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1940 reg_undef
, reg_undef
));
1944 inst
->header_present
= header_present
;
1947 this->current_annotation
= NULL
;
1951 fs_visitor::generate_fb_write(fs_inst
*inst
)
1953 GLboolean eot
= inst
->eot
;
1954 struct brw_reg implied_header
;
1956 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1959 brw_push_insn_state(p
);
1960 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1961 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1963 if (inst
->header_present
) {
1964 if (intel
->gen
>= 6) {
1966 brw_message_reg(inst
->base_mrf
),
1967 brw_vec8_grf(0, 0));
1968 implied_header
= brw_null_reg();
1970 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1974 brw_message_reg(inst
->base_mrf
+ 1),
1975 brw_vec8_grf(1, 0));
1977 implied_header
= brw_null_reg();
1980 brw_pop_insn_state(p
);
1983 8, /* dispatch_width */
1984 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
1994 fs_visitor::generate_linterp(fs_inst
*inst
,
1995 struct brw_reg dst
, struct brw_reg
*src
)
1997 struct brw_reg delta_x
= src
[0];
1998 struct brw_reg delta_y
= src
[1];
1999 struct brw_reg interp
= src
[2];
2002 delta_y
.nr
== delta_x
.nr
+ 1 &&
2003 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
2004 brw_PLN(p
, dst
, interp
, delta_x
);
2006 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
2007 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
2012 fs_visitor::generate_math(fs_inst
*inst
,
2013 struct brw_reg dst
, struct brw_reg
*src
)
2017 switch (inst
->opcode
) {
2019 op
= BRW_MATH_FUNCTION_INV
;
2022 op
= BRW_MATH_FUNCTION_RSQ
;
2024 case FS_OPCODE_SQRT
:
2025 op
= BRW_MATH_FUNCTION_SQRT
;
2027 case FS_OPCODE_EXP2
:
2028 op
= BRW_MATH_FUNCTION_EXP
;
2030 case FS_OPCODE_LOG2
:
2031 op
= BRW_MATH_FUNCTION_LOG
;
2034 op
= BRW_MATH_FUNCTION_POW
;
2037 op
= BRW_MATH_FUNCTION_SIN
;
2040 op
= BRW_MATH_FUNCTION_COS
;
2043 assert(!"not reached: unknown math function");
2048 if (intel
->gen
>= 6) {
2049 assert(inst
->mlen
== 0);
2051 if (inst
->opcode
== FS_OPCODE_POW
) {
2052 brw_math2(p
, dst
, op
, src
[0], src
[1]);
2056 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2057 BRW_MATH_SATURATE_NONE
,
2059 BRW_MATH_DATA_VECTOR
,
2060 BRW_MATH_PRECISION_FULL
);
2063 assert(inst
->mlen
>= 1);
2067 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2068 BRW_MATH_SATURATE_NONE
,
2069 inst
->base_mrf
, src
[0],
2070 BRW_MATH_DATA_VECTOR
,
2071 BRW_MATH_PRECISION_FULL
);
2076 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
)
2080 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2082 if (intel
->gen
>= 5) {
2083 switch (inst
->opcode
) {
2085 if (inst
->shadow_compare
) {
2086 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
2088 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
2092 if (inst
->shadow_compare
) {
2093 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
2095 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
2100 switch (inst
->opcode
) {
2102 /* Note that G45 and older determines shadow compare and dispatch width
2103 * from message length for most messages.
2105 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2106 if (inst
->shadow_compare
) {
2107 assert(inst
->mlen
== 6);
2109 assert(inst
->mlen
<= 4);
2113 if (inst
->shadow_compare
) {
2114 assert(inst
->mlen
== 6);
2115 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2117 assert(inst
->mlen
== 9);
2118 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2119 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2124 assert(msg_type
!= -1);
2126 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2132 retype(dst
, BRW_REGISTER_TYPE_UW
),
2134 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2135 SURF_INDEX_TEXTURE(inst
->sampler
),
2147 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2150 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2152 * and we're trying to produce:
2155 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2156 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2157 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2158 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2159 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2160 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2161 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2162 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2164 * and add another set of two more subspans if in 16-pixel dispatch mode.
2166 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2167 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2168 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2169 * between each other. We could probably do it like ddx and swizzle the right
2170 * order later, but bail for now and just produce
2171 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2174 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2176 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2177 BRW_REGISTER_TYPE_F
,
2178 BRW_VERTICAL_STRIDE_2
,
2180 BRW_HORIZONTAL_STRIDE_0
,
2181 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2182 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2183 BRW_REGISTER_TYPE_F
,
2184 BRW_VERTICAL_STRIDE_2
,
2186 BRW_HORIZONTAL_STRIDE_0
,
2187 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2188 brw_ADD(p
, dst
, src0
, negate(src1
));
2192 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2194 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2195 BRW_REGISTER_TYPE_F
,
2196 BRW_VERTICAL_STRIDE_4
,
2198 BRW_HORIZONTAL_STRIDE_0
,
2199 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2200 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2201 BRW_REGISTER_TYPE_F
,
2202 BRW_VERTICAL_STRIDE_4
,
2204 BRW_HORIZONTAL_STRIDE_0
,
2205 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2206 brw_ADD(p
, dst
, src0
, negate(src1
));
2210 fs_visitor::generate_discard_not(fs_inst
*inst
, struct brw_reg mask
)
2212 brw_push_insn_state(p
);
2213 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2214 brw_NOT(p
, mask
, brw_mask_reg(1)); /* IMASK */
2215 brw_pop_insn_state(p
);
2219 fs_visitor::generate_discard_and(fs_inst
*inst
, struct brw_reg mask
)
2221 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2222 mask
= brw_uw1_reg(mask
.file
, mask
.nr
, 0);
2224 brw_push_insn_state(p
);
2225 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2226 brw_AND(p
, g0
, mask
, g0
);
2227 brw_pop_insn_state(p
);
2231 fs_visitor::assign_curb_setup()
2233 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
2234 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2236 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2237 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2238 fs_inst
*inst
= (fs_inst
*)iter
.get();
2240 for (unsigned int i
= 0; i
< 3; i
++) {
2241 if (inst
->src
[i
].file
== UNIFORM
) {
2242 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2243 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2247 inst
->src
[i
].file
= FIXED_HW_REG
;
2248 inst
->src
[i
].fixed_hw_reg
= brw_reg
;
2255 fs_visitor::calculate_urb_setup()
2257 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2262 /* Figure out where each of the incoming setup attributes lands. */
2263 if (intel
->gen
>= 6) {
2264 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2265 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
2266 urb_setup
[i
] = urb_next
++;
2270 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2271 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2272 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2275 if (i
>= VERT_RESULT_VAR0
)
2276 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2277 else if (i
<= VERT_RESULT_TEX7
)
2283 urb_setup
[fp_index
] = urb_next
++;
2288 /* Each attribute is 4 setup channels, each of which is half a reg. */
2289 c
->prog_data
.urb_read_length
= urb_next
* 2;
2293 fs_visitor::assign_urb_setup()
2295 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2297 /* Offset all the urb_setup[] index by the actual position of the
2298 * setup regs, now that the location of the constants has been chosen.
2300 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2301 fs_inst
*inst
= (fs_inst
*)iter
.get();
2303 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
2306 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2308 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2311 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2315 assign_reg(int *reg_hw_locations
, fs_reg
*reg
)
2317 if (reg
->file
== GRF
&& reg
->reg
!= 0) {
2318 assert(reg
->reg_offset
>= 0);
2319 reg
->hw_reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
;
2325 fs_visitor::assign_regs_trivial()
2328 int hw_reg_mapping
[this->virtual_grf_next
];
2331 hw_reg_mapping
[0] = 0;
2332 hw_reg_mapping
[1] = this->first_non_payload_grf
;
2333 for (i
= 2; i
< this->virtual_grf_next
; i
++) {
2334 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
2335 this->virtual_grf_sizes
[i
- 1]);
2337 last_grf
= hw_reg_mapping
[i
- 1] + this->virtual_grf_sizes
[i
- 1];
2339 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2340 fs_inst
*inst
= (fs_inst
*)iter
.get();
2342 assign_reg(hw_reg_mapping
, &inst
->dst
);
2343 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2344 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2347 this->grf_used
= last_grf
+ 1;
2351 fs_visitor::assign_regs()
2354 int hw_reg_mapping
[this->virtual_grf_next
+ 1];
2355 int base_reg_count
= BRW_MAX_GRF
- this->first_non_payload_grf
;
2356 int class_sizes
[base_reg_count
];
2357 int class_count
= 0;
2358 int aligned_pair_class
= -1;
2360 /* Set up the register classes.
2362 * The base registers store a scalar value. For texture samples,
2363 * we get virtual GRFs composed of 4 contiguous hw register. For
2364 * structures and arrays, we store them as contiguous larger things
2365 * than that, though we should be able to do better most of the
2368 class_sizes
[class_count
++] = 1;
2369 if (brw
->has_pln
&& intel
->gen
< 6) {
2370 /* Always set up the (unaligned) pairs for gen5, so we can find
2371 * them for making the aligned pair class.
2373 class_sizes
[class_count
++] = 2;
2375 for (int r
= 1; r
< this->virtual_grf_next
; r
++) {
2378 for (i
= 0; i
< class_count
; i
++) {
2379 if (class_sizes
[i
] == this->virtual_grf_sizes
[r
])
2382 if (i
== class_count
) {
2383 if (this->virtual_grf_sizes
[r
] >= base_reg_count
) {
2384 fprintf(stderr
, "Object too large to register allocate.\n");
2388 class_sizes
[class_count
++] = this->virtual_grf_sizes
[r
];
2392 int ra_reg_count
= 0;
2393 int class_base_reg
[class_count
];
2394 int class_reg_count
[class_count
];
2395 int classes
[class_count
+ 1];
2397 for (int i
= 0; i
< class_count
; i
++) {
2398 class_base_reg
[i
] = ra_reg_count
;
2399 class_reg_count
[i
] = base_reg_count
- (class_sizes
[i
] - 1);
2400 ra_reg_count
+= class_reg_count
[i
];
2403 struct ra_regs
*regs
= ra_alloc_reg_set(ra_reg_count
);
2404 for (int i
= 0; i
< class_count
; i
++) {
2405 classes
[i
] = ra_alloc_reg_class(regs
);
2407 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2408 ra_class_add_reg(regs
, classes
[i
], class_base_reg
[i
] + i_r
);
2411 /* Add conflicts between our contiguous registers aliasing
2412 * base regs and other register classes' contiguous registers
2413 * that alias base regs, or the base regs themselves for classes[0].
2415 for (int c
= 0; c
<= i
; c
++) {
2416 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2417 for (int c_r
= MAX2(0, i_r
- (class_sizes
[c
] - 1));
2418 c_r
< MIN2(class_reg_count
[c
], i_r
+ class_sizes
[i
]);
2422 printf("%d/%d conflicts %d/%d\n",
2423 class_sizes
[i
], this->first_non_payload_grf
+ i_r
,
2424 class_sizes
[c
], this->first_non_payload_grf
+ c_r
);
2427 ra_add_reg_conflict(regs
,
2428 class_base_reg
[i
] + i_r
,
2429 class_base_reg
[c
] + c_r
);
2435 /* Add a special class for aligned pairs, which we'll put delta_x/y
2436 * in on gen5 so that we can do PLN.
2438 if (brw
->has_pln
&& intel
->gen
< 6) {
2439 int reg_count
= (base_reg_count
- 1) / 2;
2440 int unaligned_pair_class
= 1;
2441 assert(class_sizes
[unaligned_pair_class
] == 2);
2443 aligned_pair_class
= class_count
;
2444 classes
[aligned_pair_class
] = ra_alloc_reg_class(regs
);
2445 class_sizes
[aligned_pair_class
] = 2;
2446 class_base_reg
[aligned_pair_class
] = 0;
2447 class_reg_count
[aligned_pair_class
] = 0;
2448 int start
= (this->first_non_payload_grf
& 1) ? 1 : 0;
2450 for (int i
= 0; i
< reg_count
; i
++) {
2451 ra_class_add_reg(regs
, classes
[aligned_pair_class
],
2452 class_base_reg
[unaligned_pair_class
] + i
* 2 + start
);
2457 ra_set_finalize(regs
);
2459 struct ra_graph
*g
= ra_alloc_interference_graph(regs
,
2460 this->virtual_grf_next
);
2461 /* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1
2464 ra_set_node_class(g
, 0, classes
[0]);
2466 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2467 for (int c
= 0; c
< class_count
; c
++) {
2468 if (class_sizes
[c
] == this->virtual_grf_sizes
[i
]) {
2469 if (aligned_pair_class
>= 0 &&
2470 this->delta_x
.reg
== i
) {
2471 ra_set_node_class(g
, i
, classes
[aligned_pair_class
]);
2473 ra_set_node_class(g
, i
, classes
[c
]);
2479 for (int j
= 1; j
< i
; j
++) {
2480 if (virtual_grf_interferes(i
, j
)) {
2481 ra_add_node_interference(g
, i
, j
);
2486 /* FINISHME: Handle spilling */
2487 if (!ra_allocate_no_spills(g
)) {
2488 fprintf(stderr
, "Failed to allocate registers.\n");
2493 /* Get the chosen virtual registers for each node, and map virtual
2494 * regs in the register classes back down to real hardware reg
2497 hw_reg_mapping
[0] = 0; /* unused */
2498 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2499 int reg
= ra_get_node_reg(g
, i
);
2502 for (int c
= 0; c
< class_count
; c
++) {
2503 if (reg
>= class_base_reg
[c
] &&
2504 reg
< class_base_reg
[c
] + class_reg_count
[c
]) {
2505 hw_reg
= reg
- class_base_reg
[c
];
2510 assert(hw_reg
>= 0);
2511 hw_reg_mapping
[i
] = this->first_non_payload_grf
+ hw_reg
;
2512 last_grf
= MAX2(last_grf
,
2513 hw_reg_mapping
[i
] + this->virtual_grf_sizes
[i
] - 1);
2516 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2517 fs_inst
*inst
= (fs_inst
*)iter
.get();
2519 assign_reg(hw_reg_mapping
, &inst
->dst
);
2520 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2521 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2524 this->grf_used
= last_grf
+ 1;
2531 * Split large virtual GRFs into separate components if we can.
2533 * This is mostly duplicated with what brw_fs_vector_splitting does,
2534 * but that's really conservative because it's afraid of doing
2535 * splitting that doesn't result in real progress after the rest of
2536 * the optimization phases, which would cause infinite looping in
2537 * optimization. We can do it once here, safely. This also has the
2538 * opportunity to split interpolated values, or maybe even uniforms,
2539 * which we don't have at the IR level.
2541 * We want to split, because virtual GRFs are what we register
2542 * allocate and spill (due to contiguousness requirements for some
2543 * instructions), and they're what we naturally generate in the
2544 * codegen process, but most virtual GRFs don't actually need to be
2545 * contiguous sets of GRFs. If we split, we'll end up with reduced
2546 * live intervals and better dead code elimination and coalescing.
2549 fs_visitor::split_virtual_grfs()
2551 int num_vars
= this->virtual_grf_next
;
2552 bool split_grf
[num_vars
];
2553 int new_virtual_grf
[num_vars
];
2555 /* Try to split anything > 0 sized. */
2556 for (int i
= 0; i
< num_vars
; i
++) {
2557 if (this->virtual_grf_sizes
[i
] != 1)
2558 split_grf
[i
] = true;
2560 split_grf
[i
] = false;
2564 /* PLN opcodes rely on the delta_xy being contiguous. */
2565 split_grf
[this->delta_x
.reg
] = false;
2568 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2569 fs_inst
*inst
= (fs_inst
*)iter
.get();
2571 /* Texturing produces 4 contiguous registers, so no splitting. */
2572 if ((inst
->opcode
== FS_OPCODE_TEX
||
2573 inst
->opcode
== FS_OPCODE_TXB
||
2574 inst
->opcode
== FS_OPCODE_TXL
) &&
2575 inst
->dst
.file
== GRF
) {
2576 split_grf
[inst
->dst
.reg
] = false;
2580 /* Allocate new space for split regs. Note that the virtual
2581 * numbers will be contiguous.
2583 for (int i
= 0; i
< num_vars
; i
++) {
2585 new_virtual_grf
[i
] = virtual_grf_alloc(1);
2586 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
2587 int reg
= virtual_grf_alloc(1);
2588 assert(reg
== new_virtual_grf
[i
] + j
- 1);
2590 this->virtual_grf_sizes
[i
] = 1;
2594 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2595 fs_inst
*inst
= (fs_inst
*)iter
.get();
2597 if (inst
->dst
.file
== GRF
&&
2598 split_grf
[inst
->dst
.reg
] &&
2599 inst
->dst
.reg_offset
!= 0) {
2600 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
2601 inst
->dst
.reg_offset
- 1);
2602 inst
->dst
.reg_offset
= 0;
2604 for (int i
= 0; i
< 3; i
++) {
2605 if (inst
->src
[i
].file
== GRF
&&
2606 split_grf
[inst
->src
[i
].reg
] &&
2607 inst
->src
[i
].reg_offset
!= 0) {
2608 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
2609 inst
->src
[i
].reg_offset
- 1);
2610 inst
->src
[i
].reg_offset
= 0;
2617 fs_visitor::calculate_live_intervals()
2619 int num_vars
= this->virtual_grf_next
;
2620 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2621 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2625 for (int i
= 0; i
< num_vars
; i
++) {
2631 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2632 fs_inst
*inst
= (fs_inst
*)iter
.get();
2634 if (inst
->opcode
== BRW_OPCODE_DO
) {
2635 if (loop_depth
++ == 0)
2637 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2640 if (loop_depth
== 0) {
2643 * Patches up any vars marked for use within the loop as
2644 * live until the end. This is conservative, as there
2645 * will often be variables defined and used inside the
2646 * loop but dead at the end of the loop body.
2648 for (int i
= 0; i
< num_vars
; i
++) {
2649 if (use
[i
] == loop_start
) {
2660 for (unsigned int i
= 0; i
< 3; i
++) {
2661 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2662 use
[inst
->src
[i
].reg
] = MAX2(use
[inst
->src
[i
].reg
], eip
);
2665 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2666 def
[inst
->dst
.reg
] = MIN2(def
[inst
->dst
.reg
], eip
);
2673 talloc_free(this->virtual_grf_def
);
2674 talloc_free(this->virtual_grf_use
);
2675 this->virtual_grf_def
= def
;
2676 this->virtual_grf_use
= use
;
2680 * Attempts to move immediate constants into the immediate
2681 * constant slot of following instructions.
2683 * Immediate constants are a bit tricky -- they have to be in the last
2684 * operand slot, you can't do abs/negate on them,
2688 fs_visitor::propagate_constants()
2690 bool progress
= false;
2692 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2693 fs_inst
*inst
= (fs_inst
*)iter
.get();
2695 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2697 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2698 inst
->dst
.type
!= inst
->src
[0].type
)
2701 /* Don't bother with cases where we should have had the
2702 * operation on the constant folded in GLSL already.
2707 /* Found a move of a constant to a GRF. Find anything else using the GRF
2708 * before it's written, and replace it with the constant if we can.
2710 exec_list_iterator scan_iter
= iter
;
2712 for (; scan_iter
.has_next(); scan_iter
.next()) {
2713 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2715 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2716 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2717 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2718 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2722 for (int i
= 2; i
>= 0; i
--) {
2723 if (scan_inst
->src
[i
].file
!= GRF
||
2724 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2725 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2728 /* Don't bother with cases where we should have had the
2729 * operation on the constant folded in GLSL already.
2731 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2734 switch (scan_inst
->opcode
) {
2735 case BRW_OPCODE_MOV
:
2736 scan_inst
->src
[i
] = inst
->src
[0];
2740 case BRW_OPCODE_MUL
:
2741 case BRW_OPCODE_ADD
:
2743 scan_inst
->src
[i
] = inst
->src
[0];
2745 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2746 /* Fit this constant in by commuting the operands */
2747 scan_inst
->src
[0] = scan_inst
->src
[1];
2748 scan_inst
->src
[1] = inst
->src
[0];
2751 case BRW_OPCODE_CMP
:
2753 scan_inst
->src
[i
] = inst
->src
[0];
2759 if (scan_inst
->dst
.file
== GRF
&&
2760 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2761 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2762 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2771 * Must be called after calculate_live_intervales() to remove unused
2772 * writes to registers -- register allocation will fail otherwise
2773 * because something deffed but not used won't be considered to
2774 * interfere with other regs.
2777 fs_visitor::dead_code_eliminate()
2779 bool progress
= false;
2780 int num_vars
= this->virtual_grf_next
;
2781 bool dead
[num_vars
];
2783 for (int i
= 0; i
< num_vars
; i
++) {
2784 dead
[i
] = this->virtual_grf_def
[i
] >= this->virtual_grf_use
[i
];
2787 /* Mark off its interval so it won't interfere with anything. */
2788 this->virtual_grf_def
[i
] = -1;
2789 this->virtual_grf_use
[i
] = -1;
2793 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2794 fs_inst
*inst
= (fs_inst
*)iter
.get();
2796 if (inst
->dst
.file
== GRF
&& dead
[inst
->dst
.reg
]) {
2806 fs_visitor::register_coalesce()
2808 bool progress
= false;
2810 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2811 fs_inst
*inst
= (fs_inst
*)iter
.get();
2813 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2816 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= GRF
||
2817 inst
->dst
.type
!= inst
->src
[0].type
)
2820 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
2821 * them: check for no writes to either one until the exit of the
2824 bool interfered
= false;
2825 exec_list_iterator scan_iter
= iter
;
2827 for (; scan_iter
.has_next(); scan_iter
.next()) {
2828 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2830 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2831 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2832 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2838 if (scan_inst
->dst
.file
== GRF
) {
2839 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2840 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2841 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2845 if (scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
2846 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
2847 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2857 /* Update live interval so we don't have to recalculate. */
2858 this->virtual_grf_use
[inst
->src
[0].reg
] = MAX2(virtual_grf_use
[inst
->src
[0].reg
],
2859 virtual_grf_use
[inst
->dst
.reg
]);
2861 /* Rewrite the later usage to point at the source of the move to
2864 for (exec_list_iterator scan_iter
= iter
; scan_iter
.has_next();
2866 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2868 for (int i
= 0; i
< 3; i
++) {
2869 if (scan_inst
->src
[i
].file
== GRF
&&
2870 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
2871 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
2872 scan_inst
->src
[i
].reg
= inst
->src
[0].reg
;
2873 scan_inst
->src
[i
].reg_offset
= inst
->src
[0].reg_offset
;
2874 scan_inst
->src
[i
].abs
|= inst
->src
[0].abs
;
2875 scan_inst
->src
[i
].negate
^= inst
->src
[0].negate
;
2889 fs_visitor::compute_to_mrf()
2891 bool progress
= false;
2894 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2895 fs_inst
*inst
= (fs_inst
*)iter
.get();
2900 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2902 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2903 inst
->dst
.type
!= inst
->src
[0].type
||
2904 inst
->src
[0].abs
|| inst
->src
[0].negate
)
2907 /* Can't compute-to-MRF this GRF if someone else was going to
2910 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
2913 /* Found a move of a GRF to a MRF. Let's see if we can go
2914 * rewrite the thing that made this GRF to write into the MRF.
2918 for (scan_inst
= (fs_inst
*)inst
->prev
;
2919 scan_inst
->prev
!= NULL
;
2920 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2921 /* We don't handle flow control here. Most computation of
2922 * values that end up in MRFs are shortly before the MRF
2925 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2926 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2927 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2931 /* You can't read from an MRF, so if someone else reads our
2932 * MRF's source GRF that we wanted to rewrite, that stops us.
2934 bool interfered
= false;
2935 for (int i
= 0; i
< 3; i
++) {
2936 if (scan_inst
->src
[i
].file
== GRF
&&
2937 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2938 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2945 if (scan_inst
->dst
.file
== MRF
&&
2946 scan_inst
->dst
.hw_reg
== inst
->dst
.hw_reg
) {
2947 /* Somebody else wrote our MRF here, so we can't can't
2948 * compute-to-MRF before that.
2953 if (scan_inst
->mlen
> 0) {
2954 /* Found a SEND instruction, which will do some amount of
2955 * implied write that may overwrite our MRF that we were
2956 * hoping to compute-to-MRF somewhere above it. Nothing
2957 * we have implied-writes more than 2 MRFs from base_mrf,
2960 int implied_write_len
= MIN2(scan_inst
->mlen
, 2);
2961 if (inst
->dst
.hw_reg
>= scan_inst
->base_mrf
&&
2962 inst
->dst
.hw_reg
< scan_inst
->base_mrf
+ implied_write_len
) {
2967 if (scan_inst
->dst
.file
== GRF
&&
2968 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2969 /* Found the last thing to write our reg we want to turn
2970 * into a compute-to-MRF.
2973 if (scan_inst
->opcode
== FS_OPCODE_TEX
) {
2974 /* texturing writes several continuous regs, so we can't
2975 * compute-to-mrf that.
2980 /* If it's predicated, it (probably) didn't populate all
2983 if (scan_inst
->predicated
)
2986 /* SEND instructions can't have MRF as a destination. */
2987 if (scan_inst
->mlen
)
2990 if (intel
->gen
>= 6) {
2991 /* gen6 math instructions must have the destination be
2992 * GRF, so no compute-to-MRF for them.
2994 if (scan_inst
->opcode
== FS_OPCODE_RCP
||
2995 scan_inst
->opcode
== FS_OPCODE_RSQ
||
2996 scan_inst
->opcode
== FS_OPCODE_SQRT
||
2997 scan_inst
->opcode
== FS_OPCODE_EXP2
||
2998 scan_inst
->opcode
== FS_OPCODE_LOG2
||
2999 scan_inst
->opcode
== FS_OPCODE_SIN
||
3000 scan_inst
->opcode
== FS_OPCODE_COS
||
3001 scan_inst
->opcode
== FS_OPCODE_POW
) {
3006 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
3007 /* Found the creator of our MRF's source value. */
3014 scan_inst
->dst
.file
= MRF
;
3015 scan_inst
->dst
.hw_reg
= inst
->dst
.hw_reg
;
3016 scan_inst
->saturate
|= inst
->saturate
;
3026 fs_visitor::virtual_grf_interferes(int a
, int b
)
3028 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
3029 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
3031 /* For dead code, just check if the def interferes with the other range. */
3032 if (this->virtual_grf_use
[a
] == -1) {
3033 return (this->virtual_grf_def
[a
] >= this->virtual_grf_def
[b
] &&
3034 this->virtual_grf_def
[a
] < this->virtual_grf_use
[b
]);
3036 if (this->virtual_grf_use
[b
] == -1) {
3037 return (this->virtual_grf_def
[b
] >= this->virtual_grf_def
[a
] &&
3038 this->virtual_grf_def
[b
] < this->virtual_grf_use
[a
]);
3044 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
3046 struct brw_reg brw_reg
;
3048 switch (reg
->file
) {
3052 brw_reg
= brw_vec8_reg(reg
->file
,
3054 brw_reg
= retype(brw_reg
, reg
->type
);
3057 switch (reg
->type
) {
3058 case BRW_REGISTER_TYPE_F
:
3059 brw_reg
= brw_imm_f(reg
->imm
.f
);
3061 case BRW_REGISTER_TYPE_D
:
3062 brw_reg
= brw_imm_d(reg
->imm
.i
);
3064 case BRW_REGISTER_TYPE_UD
:
3065 brw_reg
= brw_imm_ud(reg
->imm
.u
);
3068 assert(!"not reached");
3073 brw_reg
= reg
->fixed_hw_reg
;
3076 /* Probably unused. */
3077 brw_reg
= brw_null_reg();
3080 assert(!"not reached");
3081 brw_reg
= brw_null_reg();
3085 brw_reg
= brw_abs(brw_reg
);
3087 brw_reg
= negate(brw_reg
);
3093 fs_visitor::generate_code()
3095 unsigned int annotation_len
= 0;
3096 int last_native_inst
= 0;
3097 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
3098 int if_stack_depth
= 0, loop_stack_depth
= 0;
3099 int if_depth_in_loop
[16];
3101 if_depth_in_loop
[loop_stack_depth
] = 0;
3103 memset(&if_stack
, 0, sizeof(if_stack
));
3104 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3105 fs_inst
*inst
= (fs_inst
*)iter
.get();
3106 struct brw_reg src
[3], dst
;
3108 for (unsigned int i
= 0; i
< 3; i
++) {
3109 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
3111 dst
= brw_reg_from_fs_reg(&inst
->dst
);
3113 brw_set_conditionalmod(p
, inst
->conditional_mod
);
3114 brw_set_predicate_control(p
, inst
->predicated
);
3116 switch (inst
->opcode
) {
3117 case BRW_OPCODE_MOV
:
3118 brw_MOV(p
, dst
, src
[0]);
3120 case BRW_OPCODE_ADD
:
3121 brw_ADD(p
, dst
, src
[0], src
[1]);
3123 case BRW_OPCODE_MUL
:
3124 brw_MUL(p
, dst
, src
[0], src
[1]);
3127 case BRW_OPCODE_FRC
:
3128 brw_FRC(p
, dst
, src
[0]);
3130 case BRW_OPCODE_RNDD
:
3131 brw_RNDD(p
, dst
, src
[0]);
3133 case BRW_OPCODE_RNDE
:
3134 brw_RNDE(p
, dst
, src
[0]);
3136 case BRW_OPCODE_RNDZ
:
3137 brw_RNDZ(p
, dst
, src
[0]);
3140 case BRW_OPCODE_AND
:
3141 brw_AND(p
, dst
, src
[0], src
[1]);
3144 brw_OR(p
, dst
, src
[0], src
[1]);
3146 case BRW_OPCODE_XOR
:
3147 brw_XOR(p
, dst
, src
[0], src
[1]);
3149 case BRW_OPCODE_NOT
:
3150 brw_NOT(p
, dst
, src
[0]);
3152 case BRW_OPCODE_ASR
:
3153 brw_ASR(p
, dst
, src
[0], src
[1]);
3155 case BRW_OPCODE_SHR
:
3156 brw_SHR(p
, dst
, src
[0], src
[1]);
3158 case BRW_OPCODE_SHL
:
3159 brw_SHL(p
, dst
, src
[0], src
[1]);
3162 case BRW_OPCODE_CMP
:
3163 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
3165 case BRW_OPCODE_SEL
:
3166 brw_SEL(p
, dst
, src
[0], src
[1]);
3170 assert(if_stack_depth
< 16);
3171 if (inst
->src
[0].file
!= BAD_FILE
) {
3172 assert(intel
->gen
>= 6);
3173 if_stack
[if_stack_depth
] = brw_IF_gen6(p
, inst
->conditional_mod
, src
[0], src
[1]);
3175 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
3177 if_depth_in_loop
[loop_stack_depth
]++;
3181 case BRW_OPCODE_ELSE
:
3182 if_stack
[if_stack_depth
- 1] =
3183 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
3185 case BRW_OPCODE_ENDIF
:
3187 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
3188 if_depth_in_loop
[loop_stack_depth
]--;
3192 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
3193 if_depth_in_loop
[loop_stack_depth
] = 0;
3196 case BRW_OPCODE_BREAK
:
3197 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
3198 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3200 case BRW_OPCODE_CONTINUE
:
3201 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
3202 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3205 case BRW_OPCODE_WHILE
: {
3206 struct brw_instruction
*inst0
, *inst1
;
3209 if (intel
->gen
>= 5)
3212 assert(loop_stack_depth
> 0);
3214 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
3215 /* patch all the BREAK/CONT instructions from last BGNLOOP */
3216 while (inst0
> loop_stack
[loop_stack_depth
]) {
3218 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
3219 inst0
->bits3
.if_else
.jump_count
== 0) {
3220 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
3222 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
3223 inst0
->bits3
.if_else
.jump_count
== 0) {
3224 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
3232 case FS_OPCODE_SQRT
:
3233 case FS_OPCODE_EXP2
:
3234 case FS_OPCODE_LOG2
:
3238 generate_math(inst
, dst
, src
);
3240 case FS_OPCODE_LINTERP
:
3241 generate_linterp(inst
, dst
, src
);
3246 generate_tex(inst
, dst
);
3248 case FS_OPCODE_DISCARD_NOT
:
3249 generate_discard_not(inst
, dst
);
3251 case FS_OPCODE_DISCARD_AND
:
3252 generate_discard_and(inst
, src
[0]);
3255 generate_ddx(inst
, dst
, src
[0]);
3258 generate_ddy(inst
, dst
, src
[0]);
3260 case FS_OPCODE_FB_WRITE
:
3261 generate_fb_write(inst
);
3264 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
3265 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
3266 brw_opcodes
[inst
->opcode
].name
);
3268 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
3273 if (annotation_len
< p
->nr_insn
) {
3274 annotation_len
*= 2;
3275 if (annotation_len
< 16)
3276 annotation_len
= 16;
3278 this->annotation_string
= talloc_realloc(this->mem_ctx
,
3282 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
3288 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
3289 this->annotation_string
[i
] = inst
->annotation
;
3290 this->annotation_ir
[i
] = inst
->ir
;
3292 last_native_inst
= p
->nr_insn
;
3297 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
3299 struct brw_compile
*p
= &c
->func
;
3300 struct intel_context
*intel
= &brw
->intel
;
3301 struct gl_context
*ctx
= &intel
->ctx
;
3302 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
3307 struct brw_shader
*shader
=
3308 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3312 /* We always use 8-wide mode, at least for now. For one, flow
3313 * control only works in 8-wide. Also, when we're fragment shader
3314 * bound, we're almost always under register pressure as well, so
3315 * 8-wide would save us from the performance cliff of spilling
3318 c
->dispatch_width
= 8;
3320 if (INTEL_DEBUG
& DEBUG_WM
) {
3321 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3322 _mesa_print_ir(shader
->ir
, NULL
);
3326 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3328 fs_visitor
v(c
, shader
);
3333 v
.calculate_urb_setup();
3335 v
.emit_interpolation_setup_gen4();
3337 v
.emit_interpolation_setup_gen6();
3339 /* Generate FS IR for main(). (the visitor only descends into
3340 * functions called "main").
3342 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
3343 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
3350 v
.split_virtual_grfs();
3352 v
.assign_curb_setup();
3353 v
.assign_urb_setup();
3358 v
.calculate_live_intervals();
3359 progress
= v
.propagate_constants() || progress
;
3360 progress
= v
.register_coalesce() || progress
;
3361 progress
= v
.compute_to_mrf() || progress
;
3362 progress
= v
.dead_code_eliminate() || progress
;
3366 v
.assign_regs_trivial();
3374 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3379 if (INTEL_DEBUG
& DEBUG_WM
) {
3380 const char *last_annotation_string
= NULL
;
3381 ir_instruction
*last_annotation_ir
= NULL
;
3383 printf("Native code for fragment shader %d:\n", prog
->Name
);
3384 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
3385 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
3386 last_annotation_ir
= v
.annotation_ir
[i
];
3387 if (last_annotation_ir
) {
3389 last_annotation_ir
->print();
3393 if (last_annotation_string
!= v
.annotation_string
[i
]) {
3394 last_annotation_string
= v
.annotation_string
[i
];
3395 if (last_annotation_string
)
3396 printf(" %s\n", last_annotation_string
);
3399 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3400 ((uint32_t *)&p
->store
[i
])[3],
3401 ((uint32_t *)&p
->store
[i
])[2],
3402 ((uint32_t *)&p
->store
[i
])[1],
3403 ((uint32_t *)&p
->store
[i
])[0]);
3405 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3410 c
->prog_data
.total_grf
= v
.grf_used
;
3411 c
->prog_data
.total_scratch
= 0;