2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
32 #include "brw_context.h"
37 #include "brw_vec4_gs_visitor.h"
39 #include "brw_program.h"
40 #include "brw_dead_control_flow.h"
41 #include "compiler/glsl_types.h"
42 #include "compiler/nir/nir_builder.h"
43 #include "program/prog_parameter.h"
47 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
51 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
52 const fs_reg
*src
, unsigned sources
)
54 memset(this, 0, sizeof(*this));
56 this->src
= new fs_reg
[MAX2(sources
, 3)];
57 for (unsigned i
= 0; i
< sources
; i
++)
58 this->src
[i
] = src
[i
];
60 this->opcode
= opcode
;
62 this->sources
= sources
;
63 this->exec_size
= exec_size
;
66 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
68 assert(this->exec_size
!= 0);
70 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
72 /* This will be the case for almost all instructions. */
79 this->size_written
= dst
.component_size(exec_size
);
82 this->size_written
= 0;
86 unreachable("Invalid destination register file");
89 this->writes_accumulator
= false;
94 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
97 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
99 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
104 init(opcode
, exec_size
, dst
, NULL
, 0);
107 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
110 const fs_reg src
[1] = { src0
};
111 init(opcode
, exec_size
, dst
, src
, 1);
114 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
115 const fs_reg
&src0
, const fs_reg
&src1
)
117 const fs_reg src
[2] = { src0
, src1
};
118 init(opcode
, exec_size
, dst
, src
, 2);
121 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
122 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
124 const fs_reg src
[3] = { src0
, src1
, src2
};
125 init(opcode
, exec_size
, dst
, src
, 3);
128 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
129 const fs_reg src
[], unsigned sources
)
131 init(opcode
, exec_width
, dst
, src
, sources
);
134 fs_inst::fs_inst(const fs_inst
&that
)
136 memcpy(this, &that
, sizeof(that
));
138 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
140 for (unsigned i
= 0; i
< that
.sources
; i
++)
141 this->src
[i
] = that
.src
[i
];
150 fs_inst::resize_sources(uint8_t num_sources
)
152 if (this->sources
!= num_sources
) {
153 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
155 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
156 src
[i
] = this->src
[i
];
160 this->sources
= num_sources
;
165 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
167 const fs_reg
&surf_index
,
168 const fs_reg
&varying_offset
,
169 uint32_t const_offset
)
171 /* We have our constant surface use a pitch of 4 bytes, so our index can
172 * be any component of a vector, and then we load 4 contiguous
173 * components starting from that.
175 * We break down the const_offset to a portion added to the variable offset
176 * and a portion done using fs_reg::offset, which means that if you have
177 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
178 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
179 * later notice that those loads are all the same and eliminate the
182 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
183 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
185 /* The pull load message will load a vec4 (16 bytes). If we are loading
186 * a double this means we are only loading 2 elements worth of data.
187 * We also want to use a 32-bit data type for the dst of the load operation
188 * so other parts of the driver don't get confused about the size of the
191 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
192 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
193 vec4_result
, surf_index
, vec4_offset
);
194 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
196 if (type_sz(dst
.type
) == 8) {
197 shuffle_32bit_load_result_to_64bit_data(
198 bld
, retype(vec4_result
, dst
.type
), vec4_result
, 2);
201 vec4_result
.type
= dst
.type
;
202 bld
.MOV(dst
, offset(vec4_result
, bld
,
203 (const_offset
& 0xf) / type_sz(vec4_result
.type
)));
207 * A helper for MOV generation for fixing up broken hardware SEND dependency
211 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
213 /* The caller always wants uncompressed to emit the minimal extra
214 * dependencies, and to avoid having to deal with aligning its regs to 2.
216 const fs_builder ubld
= bld
.annotate("send dependency resolve")
219 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
223 fs_inst::equals(fs_inst
*inst
) const
225 return (opcode
== inst
->opcode
&&
226 dst
.equals(inst
->dst
) &&
227 src
[0].equals(inst
->src
[0]) &&
228 src
[1].equals(inst
->src
[1]) &&
229 src
[2].equals(inst
->src
[2]) &&
230 saturate
== inst
->saturate
&&
231 predicate
== inst
->predicate
&&
232 conditional_mod
== inst
->conditional_mod
&&
233 mlen
== inst
->mlen
&&
234 base_mrf
== inst
->base_mrf
&&
235 target
== inst
->target
&&
237 header_size
== inst
->header_size
&&
238 shadow_compare
== inst
->shadow_compare
&&
239 exec_size
== inst
->exec_size
&&
240 offset
== inst
->offset
);
244 fs_inst::is_send_from_grf() const
247 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
248 case SHADER_OPCODE_SHADER_TIME_ADD
:
249 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
250 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
251 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
252 case SHADER_OPCODE_UNTYPED_ATOMIC
:
253 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
254 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
255 case SHADER_OPCODE_TYPED_ATOMIC
:
256 case SHADER_OPCODE_TYPED_SURFACE_READ
:
257 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
258 case SHADER_OPCODE_URB_WRITE_SIMD8
:
259 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
260 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
261 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
262 case SHADER_OPCODE_URB_READ_SIMD8
:
263 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
265 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
266 return src
[1].file
== VGRF
;
267 case FS_OPCODE_FB_WRITE
:
268 case FS_OPCODE_FB_READ
:
269 return src
[0].file
== VGRF
;
272 return src
[0].file
== VGRF
;
279 * Returns true if this instruction's sources and destinations cannot
280 * safely be the same register.
282 * In most cases, a register can be written over safely by the same
283 * instruction that is its last use. For a single instruction, the
284 * sources are dereferenced before writing of the destination starts
287 * However, there are a few cases where this can be problematic:
289 * - Virtual opcodes that translate to multiple instructions in the
290 * code generator: if src == dst and one instruction writes the
291 * destination before a later instruction reads the source, then
292 * src will have been clobbered.
294 * - SIMD16 compressed instructions with certain regioning (see below).
296 * The register allocator uses this information to set up conflicts between
297 * GRF sources and the destination.
300 fs_inst::has_source_and_destination_hazard() const
303 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
304 /* Multiple partial writes to the destination */
307 /* The SIMD16 compressed instruction
309 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
311 * is actually decoded in hardware as:
313 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
314 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
316 * Which is safe. However, if we have uniform accesses
317 * happening, we get into trouble:
319 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
320 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
322 * Now our destination for the first instruction overwrote the
323 * second instruction's src0, and we get garbage for those 8
324 * pixels. There's a similar issue for the pre-gen6
325 * pixel_x/pixel_y, which are registers of 16-bit values and thus
326 * would get stomped by the first decode as well.
328 if (exec_size
== 16) {
329 for (int i
= 0; i
< sources
; i
++) {
330 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
331 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
332 src
[i
].type
== BRW_REGISTER_TYPE_W
||
333 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
334 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
344 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
346 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
349 fs_reg reg
= this->src
[0];
350 if (reg
.file
!= VGRF
|| reg
.offset
!= 0 || reg
.stride
!= 1)
353 if (grf_alloc
.sizes
[reg
.nr
] * REG_SIZE
!= this->size_written
)
356 for (int i
= 0; i
< this->sources
; i
++) {
357 reg
.type
= this->src
[i
].type
;
358 if (!this->src
[i
].equals(reg
))
361 if (i
< this->header_size
) {
362 reg
.offset
+= REG_SIZE
;
364 reg
= horiz_offset(reg
, this->exec_size
);
372 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
)
374 if (devinfo
->gen
== 6 && is_math())
377 if (is_send_from_grf())
380 if (!backend_instruction::can_do_source_mods())
387 fs_inst::can_change_types() const
389 return dst
.type
== src
[0].type
&&
390 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
391 (opcode
== BRW_OPCODE_MOV
||
392 (opcode
== BRW_OPCODE_SEL
&&
393 dst
.type
== src
[1].type
&&
394 predicate
!= BRW_PREDICATE_NONE
&&
395 !src
[1].abs
&& !src
[1].negate
));
399 fs_inst::has_side_effects() const
401 return this->eot
|| backend_instruction::has_side_effects();
407 memset(this, 0, sizeof(*this));
411 /** Generic unset register constructor. */
415 this->file
= BAD_FILE
;
418 fs_reg::fs_reg(struct ::brw_reg reg
) :
423 if (this->file
== IMM
&&
424 (this->type
!= BRW_REGISTER_TYPE_V
&&
425 this->type
!= BRW_REGISTER_TYPE_UV
&&
426 this->type
!= BRW_REGISTER_TYPE_VF
)) {
432 fs_reg::equals(const fs_reg
&r
) const
434 return (this->backend_reg::equals(r
) &&
439 fs_reg::is_contiguous() const
445 fs_reg::component_size(unsigned width
) const
447 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
450 return MAX2(width
* stride
, 1) * type_sz(type
);
454 type_size_scalar(const struct glsl_type
*type
)
456 unsigned int size
, i
;
458 switch (type
->base_type
) {
461 case GLSL_TYPE_FLOAT
:
463 return type
->components();
464 case GLSL_TYPE_DOUBLE
:
465 return type
->components() * 2;
466 case GLSL_TYPE_ARRAY
:
467 return type_size_scalar(type
->fields
.array
) * type
->length
;
468 case GLSL_TYPE_STRUCT
:
470 for (i
= 0; i
< type
->length
; i
++) {
471 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
474 case GLSL_TYPE_SAMPLER
:
475 /* Samplers take up no register space, since they're baked in at
479 case GLSL_TYPE_ATOMIC_UINT
:
481 case GLSL_TYPE_SUBROUTINE
:
483 case GLSL_TYPE_IMAGE
:
484 return BRW_IMAGE_PARAM_SIZE
;
486 case GLSL_TYPE_ERROR
:
487 case GLSL_TYPE_INTERFACE
:
488 case GLSL_TYPE_FUNCTION
:
489 unreachable("not reached");
495 /* Attribute arrays are loaded as one vec4 per element (or matrix column),
496 * except for double-precision types, which are loaded as one dvec4.
499 type_size_vs_input(const struct glsl_type
*type
)
501 if (type
->is_double()) {
502 return type_size_dvec4(type
);
504 return type_size_vec4(type
);
509 * Create a MOV to read the timestamp register.
511 * The caller is responsible for emitting the MOV. The return value is
512 * the destination of the MOV, with extra parameters set.
515 fs_visitor::get_timestamp(const fs_builder
&bld
)
517 assert(devinfo
->gen
>= 7);
519 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
522 BRW_REGISTER_TYPE_UD
));
524 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
526 /* We want to read the 3 fields we care about even if it's not enabled in
529 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
535 fs_visitor::emit_shader_time_begin()
537 /* We want only the low 32 bits of the timestamp. Since it's running
538 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
539 * which is plenty of time for our purposes. It is identical across the
540 * EUs, but since it's tracking GPU core speed it will increment at a
541 * varying rate as render P-states change.
543 shader_start_time
= component(
544 get_timestamp(bld
.annotate("shader time start")), 0);
548 fs_visitor::emit_shader_time_end()
550 /* Insert our code just before the final SEND with EOT. */
551 exec_node
*end
= this->instructions
.get_tail();
552 assert(end
&& ((fs_inst
*) end
)->eot
);
553 const fs_builder ibld
= bld
.annotate("shader time end")
554 .exec_all().at(NULL
, end
);
555 const fs_reg timestamp
= get_timestamp(ibld
);
557 /* We only use the low 32 bits of the timestamp - see
558 * emit_shader_time_begin()).
560 * We could also check if render P-states have changed (or anything
561 * else that might disrupt timing) by setting smear to 2 and checking if
562 * that field is != 0.
564 const fs_reg shader_end_time
= component(timestamp
, 0);
566 /* Check that there weren't any timestamp reset events (assuming these
567 * were the only two timestamp reads that happened).
569 const fs_reg reset
= component(timestamp
, 2);
570 set_condmod(BRW_CONDITIONAL_Z
,
571 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
572 ibld
.IF(BRW_PREDICATE_NORMAL
);
574 fs_reg start
= shader_start_time
;
576 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
577 BRW_REGISTER_TYPE_UD
),
579 const fs_builder cbld
= ibld
.group(1, 0);
580 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
582 /* If there were no instructions between the two timestamp gets, the diff
583 * is 2 cycles. Remove that overhead, so I can forget about that when
584 * trying to determine the time taken for single instructions.
586 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
587 SHADER_TIME_ADD(cbld
, 0, diff
);
588 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
589 ibld
.emit(BRW_OPCODE_ELSE
);
590 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
591 ibld
.emit(BRW_OPCODE_ENDIF
);
595 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
596 int shader_time_subindex
,
599 int index
= shader_time_index
* 3 + shader_time_subindex
;
600 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
603 if (dispatch_width
== 8)
604 payload
= vgrf(glsl_type::uvec2_type
);
606 payload
= vgrf(glsl_type::uint_type
);
608 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
612 fs_visitor::vfail(const char *format
, va_list va
)
621 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
622 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
624 this->fail_msg
= msg
;
627 fprintf(stderr
, "%s", msg
);
632 fs_visitor::fail(const char *format
, ...)
636 va_start(va
, format
);
642 * Mark this program as impossible to compile with dispatch width greater
645 * During the SIMD8 compile (which happens first), we can detect and flag
646 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
647 * SIMD16+ compile altogether.
649 * During a compile of dispatch width greater than n (if one happens anyway),
650 * this just calls fail().
653 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
655 if (dispatch_width
> n
) {
658 max_dispatch_width
= n
;
659 compiler
->shader_perf_log(log_data
,
660 "Shader dispatch width limited to SIMD%d: %s",
666 * Returns true if the instruction has a flag that means it won't
667 * update an entire destination register.
669 * For example, dead code elimination and live variable analysis want to know
670 * when a write to a variable screens off any preceding values that were in
674 fs_inst::is_partial_write() const
676 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
677 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
678 !this->dst
.is_contiguous() ||
679 this->dst
.offset
% REG_SIZE
!= 0);
683 fs_inst::components_read(unsigned i
) const
685 /* Return zero if the source is not present. */
686 if (src
[i
].file
== BAD_FILE
)
690 case FS_OPCODE_LINTERP
:
696 case FS_OPCODE_PIXEL_X
:
697 case FS_OPCODE_PIXEL_Y
:
701 case FS_OPCODE_FB_WRITE_LOGICAL
:
702 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
703 /* First/second FB write color. */
705 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
709 case SHADER_OPCODE_TEX_LOGICAL
:
710 case SHADER_OPCODE_TXD_LOGICAL
:
711 case SHADER_OPCODE_TXF_LOGICAL
:
712 case SHADER_OPCODE_TXL_LOGICAL
:
713 case SHADER_OPCODE_TXS_LOGICAL
:
714 case FS_OPCODE_TXB_LOGICAL
:
715 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
716 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
717 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
718 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
719 case SHADER_OPCODE_LOD_LOGICAL
:
720 case SHADER_OPCODE_TG4_LOGICAL
:
721 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
722 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
723 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
724 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
725 /* Texture coordinates. */
726 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
727 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
728 /* Texture derivatives. */
729 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
730 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
731 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
732 /* Texture offset. */
733 else if (i
== TEX_LOGICAL_SRC_OFFSET_VALUE
)
736 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
741 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
742 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
743 assert(src
[3].file
== IMM
);
744 /* Surface coordinates. */
747 /* Surface operation source (ignored for reads). */
753 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
754 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
755 assert(src
[3].file
== IMM
&&
757 /* Surface coordinates. */
760 /* Surface operation source. */
766 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
767 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
768 assert(src
[3].file
== IMM
&&
770 const unsigned op
= src
[4].ud
;
771 /* Surface coordinates. */
774 /* Surface operation source. */
775 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
777 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
778 op
== BRW_AOP_PREDEC
))
790 fs_inst::size_read(int arg
) const
793 case FS_OPCODE_FB_WRITE
:
794 case FS_OPCODE_FB_READ
:
795 case SHADER_OPCODE_URB_WRITE_SIMD8
:
796 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
797 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
798 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
799 case SHADER_OPCODE_URB_READ_SIMD8
:
800 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
801 case SHADER_OPCODE_UNTYPED_ATOMIC
:
802 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
803 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
804 case SHADER_OPCODE_TYPED_ATOMIC
:
805 case SHADER_OPCODE_TYPED_SURFACE_READ
:
806 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
807 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
809 return mlen
* REG_SIZE
;
812 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
813 /* The payload is actually stored in src1 */
815 return mlen
* REG_SIZE
;
818 case FS_OPCODE_LINTERP
:
823 case SHADER_OPCODE_LOAD_PAYLOAD
:
824 if (arg
< this->header_size
)
828 case CS_OPCODE_CS_TERMINATE
:
829 case SHADER_OPCODE_BARRIER
:
832 case SHADER_OPCODE_MOV_INDIRECT
:
834 assert(src
[2].file
== IMM
);
840 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
841 return mlen
* REG_SIZE
;
845 switch (src
[arg
].file
) {
848 return components_read(arg
) * type_sz(src
[arg
].type
);
854 return components_read(arg
) * src
[arg
].component_size(exec_size
);
856 unreachable("MRF registers are not allowed as sources");
862 /* Return the subset of flag registers that an instruction could
863 * potentially read or write based on the execution controls and flag
864 * subregister number of the instruction.
867 flag_mask(const fs_inst
*inst
)
869 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
870 const unsigned end
= start
+ inst
->exec_size
;
871 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
876 fs_inst::flags_read(const gen_device_info
*devinfo
) const
878 /* XXX - This doesn't consider explicit uses of the flag register as source
881 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
882 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
883 /* The vertical predication modes combine corresponding bits from
884 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
886 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
887 return flag_mask(this) << shift
| flag_mask(this);
888 } else if (predicate
) {
889 return flag_mask(this);
896 fs_inst::flags_written() const
898 /* XXX - This doesn't consider explicit uses of the flag register as
899 * destination region.
901 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
902 opcode
!= BRW_OPCODE_IF
&&
903 opcode
!= BRW_OPCODE_WHILE
)) ||
904 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
905 return flag_mask(this);
912 * Returns how many MRFs an FS opcode will write over.
914 * Note that this is not the 0 or 1 implied writes in an actual gen
915 * instruction -- the FS opcodes often generate MOVs in addition.
918 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
923 if (inst
->base_mrf
== -1)
926 switch (inst
->opcode
) {
927 case SHADER_OPCODE_RCP
:
928 case SHADER_OPCODE_RSQ
:
929 case SHADER_OPCODE_SQRT
:
930 case SHADER_OPCODE_EXP2
:
931 case SHADER_OPCODE_LOG2
:
932 case SHADER_OPCODE_SIN
:
933 case SHADER_OPCODE_COS
:
934 return 1 * dispatch_width
/ 8;
935 case SHADER_OPCODE_POW
:
936 case SHADER_OPCODE_INT_QUOTIENT
:
937 case SHADER_OPCODE_INT_REMAINDER
:
938 return 2 * dispatch_width
/ 8;
939 case SHADER_OPCODE_TEX
:
941 case SHADER_OPCODE_TXD
:
942 case SHADER_OPCODE_TXF
:
943 case SHADER_OPCODE_TXF_CMS
:
944 case SHADER_OPCODE_TXF_MCS
:
945 case SHADER_OPCODE_TG4
:
946 case SHADER_OPCODE_TG4_OFFSET
:
947 case SHADER_OPCODE_TXL
:
948 case SHADER_OPCODE_TXS
:
949 case SHADER_OPCODE_LOD
:
950 case SHADER_OPCODE_SAMPLEINFO
:
952 case FS_OPCODE_FB_WRITE
:
954 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
955 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
957 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
959 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
962 unreachable("not reached");
967 fs_visitor::vgrf(const glsl_type
*const type
)
969 int reg_width
= dispatch_width
/ 8;
970 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
971 brw_type_for_base_type(type
));
974 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
979 this->type
= BRW_REGISTER_TYPE_F
;
980 this->stride
= (file
== UNIFORM
? 0 : 1);
983 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
989 this->stride
= (file
== UNIFORM
? 0 : 1);
992 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
993 * This brings in those uniform definitions
996 fs_visitor::import_uniforms(fs_visitor
*v
)
998 this->push_constant_loc
= v
->push_constant_loc
;
999 this->pull_constant_loc
= v
->pull_constant_loc
;
1000 this->uniforms
= v
->uniforms
;
1004 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1006 assert(stage
== MESA_SHADER_FRAGMENT
);
1008 /* gl_FragCoord.x */
1009 bld
.MOV(wpos
, this->pixel_x
);
1010 wpos
= offset(wpos
, bld
, 1);
1012 /* gl_FragCoord.y */
1013 bld
.MOV(wpos
, this->pixel_y
);
1014 wpos
= offset(wpos
, bld
, 1);
1016 /* gl_FragCoord.z */
1017 if (devinfo
->gen
>= 6) {
1018 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1020 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1021 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1022 interp_reg(VARYING_SLOT_POS
, 2));
1024 wpos
= offset(wpos
, bld
, 1);
1026 /* gl_FragCoord.w: Already set up in emit_interpolation */
1027 bld
.MOV(wpos
, this->wpos_w
);
1030 enum brw_barycentric_mode
1031 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1033 /* Barycentric modes don't make sense for flat inputs. */
1034 assert(mode
!= INTERP_MODE_FLAT
);
1038 case nir_intrinsic_load_barycentric_pixel
:
1039 case nir_intrinsic_load_barycentric_at_offset
:
1040 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1042 case nir_intrinsic_load_barycentric_centroid
:
1043 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1045 case nir_intrinsic_load_barycentric_sample
:
1046 case nir_intrinsic_load_barycentric_at_sample
:
1047 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1050 unreachable("invalid intrinsic");
1053 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1056 return (enum brw_barycentric_mode
) bary
;
1060 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1062 static enum brw_barycentric_mode
1063 centroid_to_pixel(enum brw_barycentric_mode bary
)
1065 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1066 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1067 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1071 fs_visitor::emit_frontfacing_interpolation()
1073 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1075 if (devinfo
->gen
>= 6) {
1076 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1077 * a boolean result from this (~0/true or 0/false).
1079 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1080 * this task in only one instruction:
1081 * - a negation source modifier will flip the bit; and
1082 * - a W -> D type conversion will sign extend the bit into the high
1083 * word of the destination.
1085 * An ASR 15 fills the low word of the destination.
1087 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1090 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1092 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1093 * a boolean result from this (1/true or 0/false).
1095 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1096 * the negation source modifier to flip it. Unfortunately the SHR
1097 * instruction only operates on UD (or D with an abs source modifier)
1098 * sources without negation.
1100 * Instead, use ASR (which will give ~0/true or 0/false).
1102 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1105 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1112 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1114 assert(stage
== MESA_SHADER_FRAGMENT
);
1115 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1116 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1118 if (wm_prog_data
->persample_dispatch
) {
1119 /* Convert int_sample_pos to floating point */
1120 bld
.MOV(dst
, int_sample_pos
);
1121 /* Scale to the range [0, 1] */
1122 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1125 /* From ARB_sample_shading specification:
1126 * "When rendering to a non-multisample buffer, or if multisample
1127 * rasterization is disabled, gl_SamplePosition will always be
1130 bld
.MOV(dst
, brw_imm_f(0.5f
));
1135 fs_visitor::emit_samplepos_setup()
1137 assert(devinfo
->gen
>= 6);
1139 const fs_builder abld
= bld
.annotate("compute sample position");
1140 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1142 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1143 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1145 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1146 * mode will be enabled.
1148 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1149 * R31.1:0 Position Offset X/Y for Slot[3:0]
1150 * R31.3:2 Position Offset X/Y for Slot[7:4]
1153 * The X, Y sample positions come in as bytes in thread payload. So, read
1154 * the positions using vstride=16, width=8, hstride=2.
1156 struct brw_reg sample_pos_reg
=
1157 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1158 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1160 if (dispatch_width
== 8) {
1161 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1163 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1164 abld
.half(1).MOV(half(int_sample_x
, 1),
1165 fs_reg(suboffset(sample_pos_reg
, 16)));
1167 /* Compute gl_SamplePosition.x */
1168 compute_sample_position(pos
, int_sample_x
);
1169 pos
= offset(pos
, abld
, 1);
1170 if (dispatch_width
== 8) {
1171 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1173 abld
.half(0).MOV(half(int_sample_y
, 0),
1174 fs_reg(suboffset(sample_pos_reg
, 1)));
1175 abld
.half(1).MOV(half(int_sample_y
, 1),
1176 fs_reg(suboffset(sample_pos_reg
, 17)));
1178 /* Compute gl_SamplePosition.y */
1179 compute_sample_position(pos
, int_sample_y
);
1184 fs_visitor::emit_sampleid_setup()
1186 assert(stage
== MESA_SHADER_FRAGMENT
);
1187 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1188 assert(devinfo
->gen
>= 6);
1190 const fs_builder abld
= bld
.annotate("compute sample id");
1191 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1193 if (!key
->multisample_fbo
) {
1194 /* As per GL_ARB_sample_shading specification:
1195 * "When rendering to a non-multisample buffer, or if multisample
1196 * rasterization is disabled, gl_SampleID will always be zero."
1198 abld
.MOV(*reg
, brw_imm_d(0));
1199 } else if (devinfo
->gen
>= 8) {
1200 /* Sample ID comes in as 4-bit numbers in g1.0:
1202 * 15:12 Slot 3 SampleID (only used in SIMD16)
1203 * 11:8 Slot 2 SampleID (only used in SIMD16)
1204 * 7:4 Slot 1 SampleID
1205 * 3:0 Slot 0 SampleID
1207 * Each slot corresponds to four channels, so we want to replicate each
1208 * half-byte value to 4 channels in a row:
1210 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1211 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1213 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1214 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1216 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1217 * channels to read the first byte (7:0), and the second group of 8
1218 * channels to read the second byte (15:8). Then, we shift right by
1219 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1220 * values into place. Finally, we AND with 0xf to keep the low nibble.
1222 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1223 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1225 * TODO: These payload bits exist on Gen7 too, but they appear to always
1226 * be zero, so this code fails to work. We should find out why.
1228 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1230 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1231 BRW_REGISTER_TYPE_B
), 1, 8, 0)),
1232 brw_imm_v(0x44440000));
1233 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1235 const fs_reg t1
= component(fs_reg(VGRF
, alloc
.allocate(1),
1236 BRW_REGISTER_TYPE_D
), 0);
1237 const fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1239 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1240 * 8x multisampling, subspan 0 will represent sample N (where N
1241 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1242 * 7. We can find the value of N by looking at R0.0 bits 7:6
1243 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1244 * (since samples are always delivered in pairs). That is, we
1245 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1246 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1247 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1248 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1249 * populating a temporary variable with the sequence (0, 1, 2, 3),
1250 * and then reading from it using vstride=1, width=4, hstride=0.
1251 * These computations hold good for 4x multisampling as well.
1253 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1254 * the first four slots are sample 0 of subspan 0; the next four
1255 * are sample 1 of subspan 0; the third group is sample 0 of
1256 * subspan 1, and finally sample 1 of subspan 1.
1259 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1260 * accomodate 16x MSAA.
1262 abld
.exec_all().group(1, 0)
1263 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1265 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1267 /* This works for both SIMD8 and SIMD16 */
1268 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1270 /* This special instruction takes care of setting vstride=1,
1271 * width=4, hstride=0 of t2 during an ADD instruction.
1273 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1280 fs_visitor::emit_samplemaskin_setup()
1282 assert(stage
== MESA_SHADER_FRAGMENT
);
1283 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1284 assert(devinfo
->gen
>= 6);
1286 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1288 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1289 BRW_REGISTER_TYPE_D
));
1291 if (wm_prog_data
->persample_dispatch
) {
1292 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1293 * and a mask representing which sample is being processed by the
1294 * current shader invocation.
1296 * From the OES_sample_variables specification:
1297 * "When per-sample shading is active due to the use of a fragment input
1298 * qualified by "sample" or due to the use of the gl_SampleID or
1299 * gl_SamplePosition variables, only the bit for the current sample is
1300 * set in gl_SampleMaskIn."
1302 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1304 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1305 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1307 fs_reg one
= vgrf(glsl_type::int_type
);
1308 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1309 abld
.MOV(one
, brw_imm_d(1));
1310 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1311 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1313 /* In per-pixel mode, the coverage mask is sufficient. */
1314 *reg
= coverage_mask
;
1320 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1322 if (!src
.abs
&& !src
.negate
)
1325 fs_reg temp
= bld
.vgrf(src
.type
);
1332 fs_visitor::emit_discard_jump()
1334 assert(brw_wm_prog_data(this->prog_data
)->uses_kill
);
1336 /* For performance, after a discard, jump to the end of the
1337 * shader if all relevant channels have been discarded.
1339 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1340 discard_jump
->flag_subreg
= 1;
1342 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1343 discard_jump
->predicate_inverse
= true;
1347 fs_visitor::emit_gs_thread_end()
1349 assert(stage
== MESA_SHADER_GEOMETRY
);
1351 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1353 if (gs_compile
->control_data_header_size_bits
> 0) {
1354 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1357 const fs_builder abld
= bld
.annotate("thread end");
1360 if (gs_prog_data
->static_vertex_count
!= -1) {
1361 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1362 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1363 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1364 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1365 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1368 /* Delete now dead instructions. */
1369 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1375 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1379 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1380 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1381 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1384 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1385 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1386 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1387 sources
[1] = this->final_gs_vertex_count
;
1388 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1389 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1397 fs_visitor::assign_curb_setup()
1399 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1401 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1402 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1403 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1404 if (inst
->src
[i
].file
== UNIFORM
) {
1405 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1407 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1408 constant_nr
= push_constant_loc
[uniform_nr
];
1410 /* Section 5.11 of the OpenGL 4.1 spec says:
1411 * "Out-of-bounds reads return undefined values, which include
1412 * values from other variables of the active program or zero."
1413 * Just return the first push constant.
1418 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1421 brw_reg
.abs
= inst
->src
[i
].abs
;
1422 brw_reg
.negate
= inst
->src
[i
].negate
;
1424 assert(inst
->src
[i
].stride
== 0);
1425 inst
->src
[i
] = byte_offset(
1426 retype(brw_reg
, inst
->src
[i
].type
),
1427 inst
->src
[i
].offset
% 4);
1432 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1433 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1437 fs_visitor::calculate_urb_setup()
1439 assert(stage
== MESA_SHADER_FRAGMENT
);
1440 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1441 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1443 memset(prog_data
->urb_setup
, -1,
1444 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1447 /* Figure out where each of the incoming setup attributes lands. */
1448 if (devinfo
->gen
>= 6) {
1449 if (_mesa_bitcount_64(nir
->info
->inputs_read
&
1450 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1451 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1452 * first 16 varying inputs, so we can put them wherever we want.
1453 * Just put them in order.
1455 * This is useful because it means that (a) inputs not used by the
1456 * fragment shader won't take up valuable register space, and (b) we
1457 * won't have to recompile the fragment shader if it gets paired with
1458 * a different vertex (or geometry) shader.
1460 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1461 if (nir
->info
->inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1462 BITFIELD64_BIT(i
)) {
1463 prog_data
->urb_setup
[i
] = urb_next
++;
1467 bool include_vue_header
=
1468 nir
->info
->inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1470 /* We have enough input varyings that the SF/SBE pipeline stage can't
1471 * arbitrarily rearrange them to suit our whim; we have to put them
1472 * in an order that matches the output of the previous pipeline stage
1473 * (geometry or vertex shader).
1475 struct brw_vue_map prev_stage_vue_map
;
1476 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1477 key
->input_slots_valid
,
1478 nir
->info
->separate_shader
);
1480 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1482 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1483 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1485 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1486 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1487 (nir
->info
->inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1488 BITFIELD64_BIT(varying
))) {
1489 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1492 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1495 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1496 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1497 /* Point size is packed into the header, not as a general attribute */
1498 if (i
== VARYING_SLOT_PSIZ
)
1501 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1502 /* The back color slot is skipped when the front color is
1503 * also written to. In addition, some slots can be
1504 * written in the vertex shader and not read in the
1505 * fragment shader. So the register number must always be
1506 * incremented, mapped or not.
1508 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1509 prog_data
->urb_setup
[i
] = urb_next
;
1515 * It's a FS only attribute, and we did interpolation for this attribute
1516 * in SF thread. So, count it here, too.
1518 * See compile_sf_prog() for more info.
1520 if (nir
->info
->inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1521 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1524 prog_data
->num_varying_inputs
= urb_next
;
1528 fs_visitor::assign_urb_setup()
1530 assert(stage
== MESA_SHADER_FRAGMENT
);
1531 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1533 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1535 /* Offset all the urb_setup[] index by the actual position of the
1536 * setup regs, now that the location of the constants has been chosen.
1538 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1539 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1540 assert(inst
->src
[1].file
== FIXED_GRF
);
1541 inst
->src
[1].nr
+= urb_start
;
1544 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1545 assert(inst
->src
[0].file
== FIXED_GRF
);
1546 inst
->src
[0].nr
+= urb_start
;
1550 /* Each attribute is 4 setup channels, each of which is half a reg. */
1551 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1555 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1557 for (int i
= 0; i
< inst
->sources
; i
++) {
1558 if (inst
->src
[i
].file
== ATTR
) {
1559 int grf
= payload
.num_regs
+
1560 prog_data
->curb_read_length
+
1562 inst
->src
[i
].offset
/ REG_SIZE
;
1564 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1566 * VertStride must be used to cross GRF register boundaries. This
1567 * rule implies that elements within a 'Width' cannot cross GRF
1570 * So, for registers that are large enough, we have to split the exec
1571 * size in two and trust the compression state to sort it out.
1573 unsigned total_size
= inst
->exec_size
*
1574 inst
->src
[i
].stride
*
1575 type_sz(inst
->src
[i
].type
);
1577 assert(total_size
<= 2 * REG_SIZE
);
1578 const unsigned exec_size
=
1579 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1581 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1582 struct brw_reg reg
=
1583 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1584 inst
->src
[i
].offset
% REG_SIZE
),
1585 exec_size
* inst
->src
[i
].stride
,
1586 width
, inst
->src
[i
].stride
);
1587 reg
.abs
= inst
->src
[i
].abs
;
1588 reg
.negate
= inst
->src
[i
].negate
;
1596 fs_visitor::assign_vs_urb_setup()
1598 struct brw_vs_prog_data
*vs_prog_data
= brw_vs_prog_data(prog_data
);
1600 assert(stage
== MESA_SHADER_VERTEX
);
1602 /* Each attribute is 4 regs. */
1603 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1605 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1607 /* Rewrite all ATTR file references to the hw grf that they land in. */
1608 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1609 convert_attr_sources_to_hw_regs(inst
);
1614 fs_visitor::assign_tcs_single_patch_urb_setup()
1616 assert(stage
== MESA_SHADER_TESS_CTRL
);
1618 /* Rewrite all ATTR file references to HW_REGs. */
1619 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1620 convert_attr_sources_to_hw_regs(inst
);
1625 fs_visitor::assign_tes_urb_setup()
1627 assert(stage
== MESA_SHADER_TESS_EVAL
);
1629 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1631 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1633 /* Rewrite all ATTR file references to HW_REGs. */
1634 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1635 convert_attr_sources_to_hw_regs(inst
);
1640 fs_visitor::assign_gs_urb_setup()
1642 assert(stage
== MESA_SHADER_GEOMETRY
);
1644 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1646 first_non_payload_grf
+=
1647 8 * vue_prog_data
->urb_read_length
* nir
->info
->gs
.vertices_in
;
1649 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1650 /* Rewrite all ATTR file references to GRFs. */
1651 convert_attr_sources_to_hw_regs(inst
);
1657 * Split large virtual GRFs into separate components if we can.
1659 * This is mostly duplicated with what brw_fs_vector_splitting does,
1660 * but that's really conservative because it's afraid of doing
1661 * splitting that doesn't result in real progress after the rest of
1662 * the optimization phases, which would cause infinite looping in
1663 * optimization. We can do it once here, safely. This also has the
1664 * opportunity to split interpolated values, or maybe even uniforms,
1665 * which we don't have at the IR level.
1667 * We want to split, because virtual GRFs are what we register
1668 * allocate and spill (due to contiguousness requirements for some
1669 * instructions), and they're what we naturally generate in the
1670 * codegen process, but most virtual GRFs don't actually need to be
1671 * contiguous sets of GRFs. If we split, we'll end up with reduced
1672 * live intervals and better dead code elimination and coalescing.
1675 fs_visitor::split_virtual_grfs()
1677 /* Compact the register file so we eliminate dead vgrfs. This
1678 * only defines split points for live registers, so if we have
1679 * too large dead registers they will hit assertions later.
1681 compact_virtual_grfs();
1683 int num_vars
= this->alloc
.count
;
1685 /* Count the total number of registers */
1687 int vgrf_to_reg
[num_vars
];
1688 for (int i
= 0; i
< num_vars
; i
++) {
1689 vgrf_to_reg
[i
] = reg_count
;
1690 reg_count
+= alloc
.sizes
[i
];
1693 /* An array of "split points". For each register slot, this indicates
1694 * if this slot can be separated from the previous slot. Every time an
1695 * instruction uses multiple elements of a register (as a source or
1696 * destination), we mark the used slots as inseparable. Then we go
1697 * through and split the registers into the smallest pieces we can.
1699 bool split_points
[reg_count
];
1700 memset(split_points
, 0, sizeof(split_points
));
1702 /* Mark all used registers as fully splittable */
1703 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1704 if (inst
->dst
.file
== VGRF
) {
1705 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1706 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1707 split_points
[reg
+ j
] = true;
1710 for (int i
= 0; i
< inst
->sources
; i
++) {
1711 if (inst
->src
[i
].file
== VGRF
) {
1712 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1713 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1714 split_points
[reg
+ j
] = true;
1719 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1720 if (inst
->dst
.file
== VGRF
) {
1721 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1722 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1723 split_points
[reg
+ j
] = false;
1725 for (int i
= 0; i
< inst
->sources
; i
++) {
1726 if (inst
->src
[i
].file
== VGRF
) {
1727 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1728 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1729 split_points
[reg
+ j
] = false;
1734 int new_virtual_grf
[reg_count
];
1735 int new_reg_offset
[reg_count
];
1738 for (int i
= 0; i
< num_vars
; i
++) {
1739 /* The first one should always be 0 as a quick sanity check. */
1740 assert(split_points
[reg
] == false);
1743 new_reg_offset
[reg
] = 0;
1748 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1749 /* If this is a split point, reset the offset to 0 and allocate a
1750 * new virtual GRF for the previous offset many registers
1752 if (split_points
[reg
]) {
1753 assert(offset
<= MAX_VGRF_SIZE
);
1754 int grf
= alloc
.allocate(offset
);
1755 for (int k
= reg
- offset
; k
< reg
; k
++)
1756 new_virtual_grf
[k
] = grf
;
1759 new_reg_offset
[reg
] = offset
;
1764 /* The last one gets the original register number */
1765 assert(offset
<= MAX_VGRF_SIZE
);
1766 alloc
.sizes
[i
] = offset
;
1767 for (int k
= reg
- offset
; k
< reg
; k
++)
1768 new_virtual_grf
[k
] = i
;
1770 assert(reg
== reg_count
);
1772 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1773 if (inst
->dst
.file
== VGRF
) {
1774 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1775 inst
->dst
.nr
= new_virtual_grf
[reg
];
1776 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
1777 inst
->dst
.offset
% REG_SIZE
;
1778 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1780 for (int i
= 0; i
< inst
->sources
; i
++) {
1781 if (inst
->src
[i
].file
== VGRF
) {
1782 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1783 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1784 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
1785 inst
->src
[i
].offset
% REG_SIZE
;
1786 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1790 invalidate_live_intervals();
1794 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1796 * During code generation, we create tons of temporary variables, many of
1797 * which get immediately killed and are never used again. Yet, in later
1798 * optimization and analysis passes, such as compute_live_intervals, we need
1799 * to loop over all the virtual GRFs. Compacting them can save a lot of
1803 fs_visitor::compact_virtual_grfs()
1805 bool progress
= false;
1806 int remap_table
[this->alloc
.count
];
1807 memset(remap_table
, -1, sizeof(remap_table
));
1809 /* Mark which virtual GRFs are used. */
1810 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1811 if (inst
->dst
.file
== VGRF
)
1812 remap_table
[inst
->dst
.nr
] = 0;
1814 for (int i
= 0; i
< inst
->sources
; i
++) {
1815 if (inst
->src
[i
].file
== VGRF
)
1816 remap_table
[inst
->src
[i
].nr
] = 0;
1820 /* Compact the GRF arrays. */
1822 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1823 if (remap_table
[i
] == -1) {
1824 /* We just found an unused register. This means that we are
1825 * actually going to compact something.
1829 remap_table
[i
] = new_index
;
1830 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1831 invalidate_live_intervals();
1836 this->alloc
.count
= new_index
;
1838 /* Patch all the instructions to use the newly renumbered registers */
1839 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1840 if (inst
->dst
.file
== VGRF
)
1841 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1843 for (int i
= 0; i
< inst
->sources
; i
++) {
1844 if (inst
->src
[i
].file
== VGRF
)
1845 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1849 /* Patch all the references to delta_xy, since they're used in register
1850 * allocation. If they're unused, switch them to BAD_FILE so we don't
1851 * think some random VGRF is delta_xy.
1853 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1854 if (delta_xy
[i
].file
== VGRF
) {
1855 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1856 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1858 delta_xy
[i
].file
= BAD_FILE
;
1867 set_push_pull_constant_loc(unsigned uniform
, int *chunk_start
, bool contiguous
,
1868 int *push_constant_loc
, int *pull_constant_loc
,
1869 unsigned *num_push_constants
,
1870 unsigned *num_pull_constants
,
1871 const unsigned max_push_components
,
1872 const unsigned max_chunk_size
,
1873 struct brw_stage_prog_data
*stage_prog_data
)
1875 /* This is the first live uniform in the chunk */
1876 if (*chunk_start
< 0)
1877 *chunk_start
= uniform
;
1879 /* If this element does not need to be contiguous with the next, we
1880 * split at this point and everything between chunk_start and u forms a
1884 unsigned chunk_size
= uniform
- *chunk_start
+ 1;
1886 /* Decide whether we should push or pull this parameter. In the
1887 * Vulkan driver, push constants are explicitly exposed via the API
1888 * so we push everything. In GL, we only push small arrays.
1890 if (stage_prog_data
->pull_param
== NULL
||
1891 (*num_push_constants
+ chunk_size
<= max_push_components
&&
1892 chunk_size
<= max_chunk_size
)) {
1893 assert(*num_push_constants
+ chunk_size
<= max_push_components
);
1894 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1895 push_constant_loc
[j
] = (*num_push_constants
)++;
1897 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1898 pull_constant_loc
[j
] = (*num_pull_constants
)++;
1906 * Assign UNIFORM file registers to either push constants or pull constants.
1908 * We allow a fragment shader to have more than the specified minimum
1909 * maximum number of fragment shader uniform components (64). If
1910 * there are too many of these, they'd fill up all of register space.
1911 * So, this will push some of them out to the pull constant buffer and
1912 * update the program to load them.
1915 fs_visitor::assign_constant_locations()
1917 /* Only the first compile gets to decide on locations. */
1918 if (dispatch_width
!= min_dispatch_width
)
1921 bool is_live
[uniforms
];
1922 memset(is_live
, 0, sizeof(is_live
));
1923 bool is_live_64bit
[uniforms
];
1924 memset(is_live_64bit
, 0, sizeof(is_live_64bit
));
1926 /* For each uniform slot, a value of true indicates that the given slot and
1927 * the next slot must remain contiguous. This is used to keep us from
1928 * splitting arrays apart.
1930 bool contiguous
[uniforms
];
1931 memset(contiguous
, 0, sizeof(contiguous
));
1933 int thread_local_id_index
=
1934 (stage
== MESA_SHADER_COMPUTE
) ?
1935 brw_cs_prog_data(stage_prog_data
)->thread_local_id_index
: -1;
1937 /* First, we walk through the instructions and do two things:
1939 * 1) Figure out which uniforms are live.
1941 * 2) Mark any indirectly used ranges of registers as contiguous.
1943 * Note that we don't move constant-indexed accesses to arrays. No
1944 * testing has been done of the performance impact of this choice.
1946 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1947 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1948 if (inst
->src
[i
].file
!= UNIFORM
)
1951 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1953 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
1954 assert(inst
->src
[2].ud
% 4 == 0);
1955 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
1956 assert(last
< uniforms
);
1958 for (unsigned j
= constant_nr
; j
< last
; j
++) {
1960 contiguous
[j
] = true;
1961 if (type_sz(inst
->src
[i
].type
) == 8) {
1962 is_live_64bit
[j
] = true;
1965 is_live
[last
] = true;
1967 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
) {
1968 int regs_read
= inst
->components_read(i
) *
1969 type_sz(inst
->src
[i
].type
) / 4;
1970 for (int j
= 0; j
< regs_read
; j
++) {
1971 is_live
[constant_nr
+ j
] = true;
1972 if (type_sz(inst
->src
[i
].type
) == 8) {
1973 is_live_64bit
[constant_nr
+ j
] = true;
1981 if (thread_local_id_index
>= 0 && !is_live
[thread_local_id_index
])
1982 thread_local_id_index
= -1;
1984 /* Only allow 16 registers (128 uniform components) as push constants.
1986 * Just demote the end of the list. We could probably do better
1987 * here, demoting things that are rarely used in the program first.
1989 * If changing this value, note the limitation about total_regs in
1992 unsigned int max_push_components
= 16 * 8;
1993 if (thread_local_id_index
>= 0)
1994 max_push_components
--; /* Save a slot for the thread ID */
1996 /* We push small arrays, but no bigger than 16 floats. This is big enough
1997 * for a vec4 but hopefully not large enough to push out other stuff. We
1998 * should probably use a better heuristic at some point.
2000 const unsigned int max_chunk_size
= 16;
2002 unsigned int num_push_constants
= 0;
2003 unsigned int num_pull_constants
= 0;
2005 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2006 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2008 /* Default to -1 meaning no location */
2009 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2010 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2012 int chunk_start
= -1;
2014 /* First push 64-bit uniforms to ensure they are properly aligned */
2015 for (unsigned u
= 0; u
< uniforms
; u
++) {
2016 if (!is_live
[u
] || !is_live_64bit
[u
])
2019 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2020 push_constant_loc
, pull_constant_loc
,
2021 &num_push_constants
, &num_pull_constants
,
2022 max_push_components
, max_chunk_size
,
2027 /* Then push the rest of uniforms */
2028 for (unsigned u
= 0; u
< uniforms
; u
++) {
2029 if (!is_live
[u
] || is_live_64bit
[u
])
2032 /* Skip thread_local_id_index to put it in the last push register. */
2033 if (thread_local_id_index
== (int)u
)
2036 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2037 push_constant_loc
, pull_constant_loc
,
2038 &num_push_constants
, &num_pull_constants
,
2039 max_push_components
, max_chunk_size
,
2043 /* Add the CS local thread ID uniform at the end of the push constants */
2044 if (thread_local_id_index
>= 0)
2045 push_constant_loc
[thread_local_id_index
] = num_push_constants
++;
2047 /* As the uniforms are going to be reordered, take the data from a temporary
2048 * copy of the original param[].
2050 gl_constant_value
**param
= ralloc_array(NULL
, gl_constant_value
*,
2051 stage_prog_data
->nr_params
);
2052 memcpy(param
, stage_prog_data
->param
,
2053 sizeof(gl_constant_value
*) * stage_prog_data
->nr_params
);
2054 stage_prog_data
->nr_params
= num_push_constants
;
2055 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2057 /* Up until now, the param[] array has been indexed by reg + offset
2058 * of UNIFORM registers. Move pull constants into pull_param[] and
2059 * condense param[] to only contain the uniforms we chose to push.
2061 * NOTE: Because we are condensing the params[] array, we know that
2062 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2063 * having to make a copy.
2065 int new_thread_local_id_index
= -1;
2066 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2067 const gl_constant_value
*value
= param
[i
];
2069 if (pull_constant_loc
[i
] != -1) {
2070 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2071 } else if (push_constant_loc
[i
] != -1) {
2072 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2073 if (thread_local_id_index
== (int)i
)
2074 new_thread_local_id_index
= push_constant_loc
[i
];
2079 if (stage
== MESA_SHADER_COMPUTE
)
2080 brw_cs_prog_data(stage_prog_data
)->thread_local_id_index
=
2081 new_thread_local_id_index
;
2085 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2086 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2089 fs_visitor::lower_constant_loads()
2091 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2093 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2094 /* Set up the annotation tracking for new generated instructions. */
2095 const fs_builder
ibld(this, block
, inst
);
2097 for (int i
= 0; i
< inst
->sources
; i
++) {
2098 if (inst
->src
[i
].file
!= UNIFORM
)
2101 /* We'll handle this case later */
2102 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2105 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
2106 if (location
>= uniforms
)
2107 continue; /* Out of bounds access */
2109 int pull_index
= pull_constant_loc
[location
];
2111 if (pull_index
== -1)
2114 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2117 if (type_sz(inst
->src
[i
].type
) <= 4)
2118 dst
= vgrf(glsl_type::float_type
);
2120 dst
= vgrf(glsl_type::double_type
);
2122 assert(inst
->src
[i
].stride
== 0);
2124 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2125 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2126 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2127 dst
, brw_imm_ud(index
), offset
);
2129 /* Rewrite the instruction to use the temporary VGRF. */
2130 inst
->src
[i
].file
= VGRF
;
2131 inst
->src
[i
].nr
= dst
.nr
;
2132 inst
->src
[i
].offset
= (pull_index
& 3) * 4 + inst
->src
[i
].offset
% 4;
2134 brw_mark_surface_used(prog_data
, index
);
2137 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2138 inst
->src
[0].file
== UNIFORM
) {
2140 unsigned location
= inst
->src
[0].nr
+ inst
->src
[0].offset
/ 4;
2141 if (location
>= uniforms
)
2142 continue; /* Out of bounds access */
2144 int pull_index
= pull_constant_loc
[location
];
2146 if (pull_index
== -1)
2149 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2153 inst
->remove(block
);
2155 brw_mark_surface_used(prog_data
, index
);
2158 invalidate_live_intervals();
2162 fs_visitor::opt_algebraic()
2164 bool progress
= false;
2166 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2167 switch (inst
->opcode
) {
2168 case BRW_OPCODE_MOV
:
2169 if (inst
->src
[0].file
!= IMM
)
2172 if (inst
->saturate
) {
2173 if (inst
->dst
.type
!= inst
->src
[0].type
)
2174 assert(!"unimplemented: saturate mixed types");
2176 if (brw_saturate_immediate(inst
->dst
.type
,
2177 &inst
->src
[0].as_brw_reg())) {
2178 inst
->saturate
= false;
2184 case BRW_OPCODE_MUL
:
2185 if (inst
->src
[1].file
!= IMM
)
2189 if (inst
->src
[1].is_one()) {
2190 inst
->opcode
= BRW_OPCODE_MOV
;
2191 inst
->src
[1] = reg_undef
;
2197 if (inst
->src
[1].is_negative_one()) {
2198 inst
->opcode
= BRW_OPCODE_MOV
;
2199 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2200 inst
->src
[1] = reg_undef
;
2206 if (inst
->src
[1].is_zero()) {
2207 inst
->opcode
= BRW_OPCODE_MOV
;
2208 inst
->src
[0] = inst
->src
[1];
2209 inst
->src
[1] = reg_undef
;
2214 if (inst
->src
[0].file
== IMM
) {
2215 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2216 inst
->opcode
= BRW_OPCODE_MOV
;
2217 inst
->src
[0].f
*= inst
->src
[1].f
;
2218 inst
->src
[1] = reg_undef
;
2223 case BRW_OPCODE_ADD
:
2224 if (inst
->src
[1].file
!= IMM
)
2228 if (inst
->src
[1].is_zero()) {
2229 inst
->opcode
= BRW_OPCODE_MOV
;
2230 inst
->src
[1] = reg_undef
;
2235 if (inst
->src
[0].file
== IMM
) {
2236 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2237 inst
->opcode
= BRW_OPCODE_MOV
;
2238 inst
->src
[0].f
+= inst
->src
[1].f
;
2239 inst
->src
[1] = reg_undef
;
2245 if (inst
->src
[0].equals(inst
->src
[1])) {
2246 inst
->opcode
= BRW_OPCODE_MOV
;
2247 inst
->src
[1] = reg_undef
;
2252 case BRW_OPCODE_LRP
:
2253 if (inst
->src
[1].equals(inst
->src
[2])) {
2254 inst
->opcode
= BRW_OPCODE_MOV
;
2255 inst
->src
[0] = inst
->src
[1];
2256 inst
->src
[1] = reg_undef
;
2257 inst
->src
[2] = reg_undef
;
2262 case BRW_OPCODE_CMP
:
2263 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2265 inst
->src
[0].negate
&&
2266 inst
->src
[1].is_zero()) {
2267 inst
->src
[0].abs
= false;
2268 inst
->src
[0].negate
= false;
2269 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2274 case BRW_OPCODE_SEL
:
2275 if (inst
->src
[0].equals(inst
->src
[1])) {
2276 inst
->opcode
= BRW_OPCODE_MOV
;
2277 inst
->src
[1] = reg_undef
;
2278 inst
->predicate
= BRW_PREDICATE_NONE
;
2279 inst
->predicate_inverse
= false;
2281 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2282 switch (inst
->conditional_mod
) {
2283 case BRW_CONDITIONAL_LE
:
2284 case BRW_CONDITIONAL_L
:
2285 switch (inst
->src
[1].type
) {
2286 case BRW_REGISTER_TYPE_F
:
2287 if (inst
->src
[1].f
>= 1.0f
) {
2288 inst
->opcode
= BRW_OPCODE_MOV
;
2289 inst
->src
[1] = reg_undef
;
2290 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2298 case BRW_CONDITIONAL_GE
:
2299 case BRW_CONDITIONAL_G
:
2300 switch (inst
->src
[1].type
) {
2301 case BRW_REGISTER_TYPE_F
:
2302 if (inst
->src
[1].f
<= 0.0f
) {
2303 inst
->opcode
= BRW_OPCODE_MOV
;
2304 inst
->src
[1] = reg_undef
;
2305 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2317 case BRW_OPCODE_MAD
:
2318 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2319 inst
->opcode
= BRW_OPCODE_MOV
;
2320 inst
->src
[1] = reg_undef
;
2321 inst
->src
[2] = reg_undef
;
2323 } else if (inst
->src
[0].is_zero()) {
2324 inst
->opcode
= BRW_OPCODE_MUL
;
2325 inst
->src
[0] = inst
->src
[2];
2326 inst
->src
[2] = reg_undef
;
2328 } else if (inst
->src
[1].is_one()) {
2329 inst
->opcode
= BRW_OPCODE_ADD
;
2330 inst
->src
[1] = inst
->src
[2];
2331 inst
->src
[2] = reg_undef
;
2333 } else if (inst
->src
[2].is_one()) {
2334 inst
->opcode
= BRW_OPCODE_ADD
;
2335 inst
->src
[2] = reg_undef
;
2337 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2338 inst
->opcode
= BRW_OPCODE_ADD
;
2339 inst
->src
[1].f
*= inst
->src
[2].f
;
2340 inst
->src
[2] = reg_undef
;
2344 case SHADER_OPCODE_BROADCAST
:
2345 if (is_uniform(inst
->src
[0])) {
2346 inst
->opcode
= BRW_OPCODE_MOV
;
2348 inst
->force_writemask_all
= true;
2350 } else if (inst
->src
[1].file
== IMM
) {
2351 inst
->opcode
= BRW_OPCODE_MOV
;
2352 inst
->src
[0] = component(inst
->src
[0],
2355 inst
->force_writemask_all
= true;
2364 /* Swap if src[0] is immediate. */
2365 if (progress
&& inst
->is_commutative()) {
2366 if (inst
->src
[0].file
== IMM
) {
2367 fs_reg tmp
= inst
->src
[1];
2368 inst
->src
[1] = inst
->src
[0];
2377 * Optimize sample messages that have constant zero values for the trailing
2378 * texture coordinates. We can just reduce the message length for these
2379 * instructions instead of reserving a register for it. Trailing parameters
2380 * that aren't sent default to zero anyway. This will cause the dead code
2381 * eliminator to remove the MOV instruction that would otherwise be emitted to
2382 * set up the zero value.
2385 fs_visitor::opt_zero_samples()
2387 /* Gen4 infers the texturing opcode based on the message length so we can't
2390 if (devinfo
->gen
< 5)
2393 bool progress
= false;
2395 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2396 if (!inst
->is_tex())
2399 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2401 if (load_payload
->is_head_sentinel() ||
2402 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2405 /* We don't want to remove the message header or the first parameter.
2406 * Removing the first parameter is not allowed, see the Haswell PRM
2407 * volume 7, page 149:
2409 * "Parameter 0 is required except for the sampleinfo message, which
2410 * has no parameter 0"
2412 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2413 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2414 (inst
->exec_size
/ 8) +
2415 inst
->header_size
- 1].is_zero()) {
2416 inst
->mlen
-= inst
->exec_size
/ 8;
2422 invalidate_live_intervals();
2428 * Optimize sample messages which are followed by the final RT write.
2430 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2431 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2432 * final texturing results copied to the framebuffer write payload and modify
2433 * them to write to the framebuffer directly.
2436 fs_visitor::opt_sampler_eot()
2438 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2440 if (stage
!= MESA_SHADER_FRAGMENT
)
2443 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2446 /* FINISHME: It should be possible to implement this optimization when there
2447 * are multiple drawbuffers.
2449 if (key
->nr_color_regions
!= 1)
2452 /* Requires emitting a bunch of saturating MOV instructions during logical
2453 * send lowering to clamp the color payload, which the sampler unit isn't
2454 * going to do for us.
2456 if (key
->clamp_fragment_color
)
2459 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2460 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2461 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2462 assert(fb_write
->eot
);
2463 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2465 /* There wasn't one; nothing to do. */
2466 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2469 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2471 /* 3D Sampler » Messages » Message Format
2473 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2474 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2476 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2477 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2478 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2479 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2480 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2481 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2482 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2483 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2486 /* XXX - This shouldn't be necessary. */
2487 if (tex_inst
->prev
->is_head_sentinel())
2490 /* Check that the FB write sources are fully initialized by the single
2491 * texturing instruction.
2493 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2494 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2495 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2496 fb_write
->size_read(i
) != tex_inst
->size_written
)
2498 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2499 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2504 assert(!tex_inst
->eot
); /* We can't get here twice */
2505 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2507 const fs_builder
ibld(this, block
, tex_inst
);
2509 tex_inst
->offset
|= fb_write
->target
<< 24;
2510 tex_inst
->eot
= true;
2511 tex_inst
->dst
= ibld
.null_reg_ud();
2512 tex_inst
->size_written
= 0;
2513 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2515 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2516 * flag and submit a header together with the sampler message as required
2519 invalidate_live_intervals();
2524 fs_visitor::opt_register_renaming()
2526 bool progress
= false;
2529 int remap
[alloc
.count
];
2530 memset(remap
, -1, sizeof(int) * alloc
.count
);
2532 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2533 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2535 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2536 inst
->opcode
== BRW_OPCODE_WHILE
) {
2540 /* Rewrite instruction sources. */
2541 for (int i
= 0; i
< inst
->sources
; i
++) {
2542 if (inst
->src
[i
].file
== VGRF
&&
2543 remap
[inst
->src
[i
].nr
] != -1 &&
2544 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2545 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2550 const int dst
= inst
->dst
.nr
;
2553 inst
->dst
.file
== VGRF
&&
2554 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
2555 !inst
->is_partial_write()) {
2556 if (remap
[dst
] == -1) {
2559 remap
[dst
] = alloc
.allocate(regs_written(inst
));
2560 inst
->dst
.nr
= remap
[dst
];
2563 } else if (inst
->dst
.file
== VGRF
&&
2565 remap
[dst
] != dst
) {
2566 inst
->dst
.nr
= remap
[dst
];
2572 invalidate_live_intervals();
2574 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2575 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2576 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2585 * Remove redundant or useless discard jumps.
2587 * For example, we can eliminate jumps in the following sequence:
2589 * discard-jump (redundant with the next jump)
2590 * discard-jump (useless; jumps to the next instruction)
2594 fs_visitor::opt_redundant_discard_jumps()
2596 bool progress
= false;
2598 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2600 fs_inst
*placeholder_halt
= NULL
;
2601 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2602 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2603 placeholder_halt
= inst
;
2608 if (!placeholder_halt
)
2611 /* Delete any HALTs immediately before the placeholder halt. */
2612 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2613 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2614 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2615 prev
->remove(last_bblock
);
2620 invalidate_live_intervals();
2626 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2627 * from \p r.offset which overlaps the region starting at \p s.offset and
2628 * spanning \p ds bytes.
2630 static inline unsigned
2631 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
2633 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
2634 const int shift
= rel_offset
/ REG_SIZE
;
2635 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
2636 assert(reg_space(r
) == reg_space(s
) &&
2637 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
2638 return ((1 << n
) - 1) << shift
;
2642 fs_visitor::compute_to_mrf()
2644 bool progress
= false;
2647 /* No MRFs on Gen >= 7. */
2648 if (devinfo
->gen
>= 7)
2651 calculate_live_intervals();
2653 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2657 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2658 inst
->is_partial_write() ||
2659 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2660 inst
->dst
.type
!= inst
->src
[0].type
||
2661 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2662 !inst
->src
[0].is_contiguous() ||
2663 inst
->src
[0].offset
% REG_SIZE
!= 0)
2666 /* Can't compute-to-MRF this GRF if someone else was going to
2669 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2672 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
2673 * things that computed the value of all GRFs of the source region. The
2674 * regs_left bitset keeps track of the registers we haven't yet found a
2675 * generating instruction for.
2677 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
2679 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2680 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2681 inst
->src
[0], inst
->size_read(0))) {
2682 /* Found the last thing to write our reg we want to turn
2683 * into a compute-to-MRF.
2686 /* If this one instruction didn't populate all the
2687 * channels, bail. We might be able to rewrite everything
2688 * that writes that reg, but it would require smarter
2691 if (scan_inst
->is_partial_write())
2694 /* Handling things not fully contained in the source of the copy
2695 * would need us to understand coalescing out more than one MOV at
2698 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
2699 inst
->src
[0], inst
->size_read(0)))
2702 /* SEND instructions can't have MRF as a destination. */
2703 if (scan_inst
->mlen
)
2706 if (devinfo
->gen
== 6) {
2707 /* gen6 math instructions must have the destination be
2708 * GRF, so no compute-to-MRF for them.
2710 if (scan_inst
->is_math()) {
2715 /* Clear the bits for any registers this instruction overwrites. */
2716 regs_left
&= ~mask_relative_to(
2717 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
2722 /* We don't handle control flow here. Most computation of
2723 * values that end up in MRFs are shortly before the MRF
2726 if (block
->start() == scan_inst
)
2729 /* You can't read from an MRF, so if someone else reads our
2730 * MRF's source GRF that we wanted to rewrite, that stops us.
2732 bool interfered
= false;
2733 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2734 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
2735 inst
->src
[0], inst
->size_read(0))) {
2742 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2743 inst
->dst
, inst
->size_written
)) {
2744 /* If somebody else writes our MRF here, we can't
2745 * compute-to-MRF before that.
2750 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
2751 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
2752 inst
->dst
, inst
->size_written
)) {
2753 /* Found a SEND instruction, which means that there are
2754 * live values in MRFs from base_mrf to base_mrf +
2755 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2765 /* Found all generating instructions of our MRF's source value, so it
2766 * should be safe to rewrite them to point to the MRF directly.
2768 regs_left
= (1 << regs_read(inst
, 0)) - 1;
2770 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2771 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2772 inst
->src
[0], inst
->size_read(0))) {
2773 /* Clear the bits for any registers this instruction overwrites. */
2774 regs_left
&= ~mask_relative_to(
2775 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
2777 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
2778 reg_offset(inst
->src
[0]);
2780 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2781 /* Apply the same address transformation done by the hardware
2782 * for COMPR4 MRF writes.
2784 assert(rel_offset
< 2 * REG_SIZE
);
2785 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
2787 /* Clear the COMPR4 bit if the generating instruction is not
2790 if (scan_inst
->size_written
< 2 * REG_SIZE
)
2791 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
2794 /* Calculate the MRF number the result of this instruction is
2795 * ultimately written to.
2797 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
2800 scan_inst
->dst
.file
= MRF
;
2801 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
2802 scan_inst
->saturate
|= inst
->saturate
;
2809 inst
->remove(block
);
2814 invalidate_live_intervals();
2820 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2821 * flow. We could probably do better here with some form of divergence
2825 fs_visitor::eliminate_find_live_channel()
2827 bool progress
= false;
2830 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
2831 /* The optimization below assumes that channel zero is live on thread
2832 * dispatch, which may not be the case if the fixed function dispatches
2838 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2839 switch (inst
->opcode
) {
2845 case BRW_OPCODE_ENDIF
:
2846 case BRW_OPCODE_WHILE
:
2850 case FS_OPCODE_DISCARD_JUMP
:
2851 /* This can potentially make control flow non-uniform until the end
2856 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2858 inst
->opcode
= BRW_OPCODE_MOV
;
2859 inst
->src
[0] = brw_imm_ud(0u);
2861 inst
->force_writemask_all
= true;
2875 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2876 * instructions to FS_OPCODE_REP_FB_WRITE.
2879 fs_visitor::emit_repclear_shader()
2881 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2883 int color_mrf
= base_mrf
+ 2;
2887 mov
= bld
.exec_all().group(4, 0)
2888 .MOV(brw_message_reg(color_mrf
),
2889 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2891 struct brw_reg reg
=
2892 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2893 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
2894 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2896 mov
= bld
.exec_all().group(4, 0)
2897 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
2901 if (key
->nr_color_regions
== 1) {
2902 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2903 write
->saturate
= key
->clamp_fragment_color
;
2904 write
->base_mrf
= color_mrf
;
2906 write
->header_size
= 0;
2909 assume(key
->nr_color_regions
> 0);
2910 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2911 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2912 write
->saturate
= key
->clamp_fragment_color
;
2913 write
->base_mrf
= base_mrf
;
2915 write
->header_size
= 2;
2923 assign_constant_locations();
2924 assign_curb_setup();
2926 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2928 assert(mov
->src
[0].file
== FIXED_GRF
);
2929 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2934 * Walks through basic blocks, looking for repeated MRF writes and
2935 * removing the later ones.
2938 fs_visitor::remove_duplicate_mrf_writes()
2940 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2941 bool progress
= false;
2943 /* Need to update the MRF tracking for compressed instructions. */
2944 if (dispatch_width
>= 16)
2947 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2949 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2950 if (inst
->is_control_flow()) {
2951 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2954 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2955 inst
->dst
.file
== MRF
) {
2956 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
2957 if (prev_inst
&& inst
->equals(prev_inst
)) {
2958 inst
->remove(block
);
2964 /* Clear out the last-write records for MRFs that were overwritten. */
2965 if (inst
->dst
.file
== MRF
) {
2966 last_mrf_move
[inst
->dst
.nr
] = NULL
;
2969 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2970 /* Found a SEND instruction, which will include two or fewer
2971 * implied MRF writes. We could do better here.
2973 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2974 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2978 /* Clear out any MRF move records whose sources got overwritten. */
2979 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2980 if (last_mrf_move
[i
] &&
2981 regions_overlap(inst
->dst
, inst
->size_written
,
2982 last_mrf_move
[i
]->src
[0],
2983 last_mrf_move
[i
]->size_read(0))) {
2984 last_mrf_move
[i
] = NULL
;
2988 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2989 inst
->dst
.file
== MRF
&&
2990 inst
->src
[0].file
!= ARF
&&
2991 !inst
->is_partial_write()) {
2992 last_mrf_move
[inst
->dst
.nr
] = inst
;
2997 invalidate_live_intervals();
3003 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3005 /* Clear the flag for registers that actually got read (as expected). */
3006 for (int i
= 0; i
< inst
->sources
; i
++) {
3008 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3009 grf
= inst
->src
[i
].nr
;
3014 if (grf
>= first_grf
&&
3015 grf
< first_grf
+ grf_len
) {
3016 deps
[grf
- first_grf
] = false;
3017 if (inst
->exec_size
== 16)
3018 deps
[grf
- first_grf
+ 1] = false;
3024 * Implements this workaround for the original 965:
3026 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3027 * check for post destination dependencies on this instruction, software
3028 * must ensure that there is no destination hazard for the case of ‘write
3029 * followed by a posted write’ shown in the following example.
3032 * 2. send r3.xy <rest of send instruction>
3035 * Due to no post-destination dependency check on the ‘send’, the above
3036 * code sequence could have two instructions (1 and 2) in flight at the
3037 * same time that both consider ‘r3’ as the target of their final writes.
3040 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3043 int write_len
= regs_written(inst
);
3044 int first_write_grf
= inst
->dst
.nr
;
3045 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3046 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3048 memset(needs_dep
, false, sizeof(needs_dep
));
3049 memset(needs_dep
, true, write_len
);
3051 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3053 /* Walk backwards looking for writes to registers we're writing which
3054 * aren't read since being written. If we hit the start of the program,
3055 * we assume that there are no outstanding dependencies on entry to the
3058 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3059 /* If we hit control flow, assume that there *are* outstanding
3060 * dependencies, and force their cleanup before our instruction.
3062 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3063 for (int i
= 0; i
< write_len
; i
++) {
3065 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3066 first_write_grf
+ i
);
3071 /* We insert our reads as late as possible on the assumption that any
3072 * instruction but a MOV that might have left us an outstanding
3073 * dependency has more latency than a MOV.
3075 if (scan_inst
->dst
.file
== VGRF
) {
3076 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3077 int reg
= scan_inst
->dst
.nr
+ i
;
3079 if (reg
>= first_write_grf
&&
3080 reg
< first_write_grf
+ write_len
&&
3081 needs_dep
[reg
- first_write_grf
]) {
3082 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3083 needs_dep
[reg
- first_write_grf
] = false;
3084 if (scan_inst
->exec_size
== 16)
3085 needs_dep
[reg
- first_write_grf
+ 1] = false;
3090 /* Clear the flag for registers that actually got read (as expected). */
3091 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3093 /* Continue the loop only if we haven't resolved all the dependencies */
3095 for (i
= 0; i
< write_len
; i
++) {
3105 * Implements this workaround for the original 965:
3107 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3108 * used as a destination register until after it has been sourced by an
3109 * instruction with a different destination register.
3112 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3114 int write_len
= regs_written(inst
);
3115 int first_write_grf
= inst
->dst
.nr
;
3116 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3117 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3119 memset(needs_dep
, false, sizeof(needs_dep
));
3120 memset(needs_dep
, true, write_len
);
3121 /* Walk forwards looking for writes to registers we're writing which aren't
3122 * read before being written.
3124 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3125 /* If we hit control flow, force resolve all remaining dependencies. */
3126 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3127 for (int i
= 0; i
< write_len
; i
++) {
3129 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3130 first_write_grf
+ i
);
3135 /* Clear the flag for registers that actually got read (as expected). */
3136 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3138 /* We insert our reads as late as possible since they're reading the
3139 * result of a SEND, which has massive latency.
3141 if (scan_inst
->dst
.file
== VGRF
&&
3142 scan_inst
->dst
.nr
>= first_write_grf
&&
3143 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3144 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3145 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3147 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3150 /* Continue the loop only if we haven't resolved all the dependencies */
3152 for (i
= 0; i
< write_len
; i
++) {
3162 fs_visitor::insert_gen4_send_dependency_workarounds()
3164 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3167 bool progress
= false;
3169 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3170 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3171 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3172 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3178 invalidate_live_intervals();
3182 * Turns the generic expression-style uniform pull constant load instruction
3183 * into a hardware-specific series of instructions for loading a pull
3186 * The expression style allows the CSE pass before this to optimize out
3187 * repeated loads from the same offset, and gives the pre-register-allocation
3188 * scheduling full flexibility, while the conversion to native instructions
3189 * allows the post-register-allocation scheduler the best information
3192 * Note that execution masking for setting up pull constant loads is special:
3193 * the channels that need to be written are unrelated to the current execution
3194 * mask, since a later instruction will use one of the result channels as a
3195 * source operand for all 8 or 16 of its channels.
3198 fs_visitor::lower_uniform_pull_constant_loads()
3200 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3201 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3204 if (devinfo
->gen
>= 7) {
3205 /* The offset arg is a vec4-aligned immediate byte offset. */
3206 fs_reg const_offset_reg
= inst
->src
[1];
3207 assert(const_offset_reg
.file
== IMM
&&
3208 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3209 assert(const_offset_reg
.ud
% 16 == 0);
3211 fs_reg payload
, offset
;
3212 if (devinfo
->gen
>= 9) {
3213 /* We have to use a message header on Skylake to get SIMD4x2
3214 * mode. Reserve space for the register.
3216 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3217 offset
.offset
+= REG_SIZE
;
3220 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3224 /* This is actually going to be a MOV, but since only the first dword
3225 * is accessed, we have a special opcode to do just that one. Note
3226 * that this needs to be an operation that will be considered a def
3227 * by live variable analysis, or register allocation will explode.
3229 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3230 8, offset
, const_offset_reg
);
3231 setup
->force_writemask_all
= true;
3233 setup
->ir
= inst
->ir
;
3234 setup
->annotation
= inst
->annotation
;
3235 inst
->insert_before(block
, setup
);
3237 /* Similarly, this will only populate the first 4 channels of the
3238 * result register (since we only use smear values from 0-3), but we
3239 * don't tell the optimizer.
3241 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3242 inst
->src
[1] = payload
;
3244 invalidate_live_intervals();
3246 /* Before register allocation, we didn't tell the scheduler about the
3247 * MRF we use. We know it's safe to use this MRF because nothing
3248 * else does except for register spill/unspill, which generates and
3249 * uses its MRF within a single IR instruction.
3251 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3258 fs_visitor::lower_load_payload()
3260 bool progress
= false;
3262 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3263 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3266 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3267 assert(inst
->saturate
== false);
3268 fs_reg dst
= inst
->dst
;
3270 /* Get rid of COMPR4. We'll add it back in if we need it */
3271 if (dst
.file
== MRF
)
3272 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3274 const fs_builder
ibld(this, block
, inst
);
3275 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3277 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3278 if (inst
->src
[i
].file
!= BAD_FILE
) {
3279 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3280 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3281 hbld
.MOV(mov_dst
, mov_src
);
3283 dst
= offset(dst
, hbld
, 1);
3286 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3287 inst
->exec_size
> 8) {
3288 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3289 * a straightforward copy. Instead, the result of the
3290 * LOAD_PAYLOAD is treated as interleaved and the first four
3291 * non-header sources are unpacked as:
3302 * This is used for gen <= 5 fb writes.
3304 assert(inst
->exec_size
== 16);
3305 assert(inst
->header_size
+ 4 <= inst
->sources
);
3306 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3307 if (inst
->src
[i
].file
!= BAD_FILE
) {
3308 if (devinfo
->has_compr4
) {
3309 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3310 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3311 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3313 /* Platform doesn't have COMPR4. We have to fake it */
3314 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3315 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3317 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3324 /* The loop above only ever incremented us through the first set
3325 * of 4 registers. However, thanks to the magic of COMPR4, we
3326 * actually wrote to the first 8 registers, so we need to take
3327 * that into account now.
3331 /* The COMPR4 code took care of the first 4 sources. We'll let
3332 * the regular path handle any remaining sources. Yes, we are
3333 * modifying the instruction but we're about to delete it so
3334 * this really doesn't hurt anything.
3336 inst
->header_size
+= 4;
3339 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3340 if (inst
->src
[i
].file
!= BAD_FILE
)
3341 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3342 dst
= offset(dst
, ibld
, 1);
3345 inst
->remove(block
);
3350 invalidate_live_intervals();
3356 fs_visitor::lower_integer_multiplication()
3358 bool progress
= false;
3360 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3361 const fs_builder
ibld(this, block
, inst
);
3363 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3364 if (inst
->dst
.is_accumulator() ||
3365 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3366 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3369 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3370 * operation directly, but CHV/BXT cannot.
3372 if (devinfo
->gen
>= 8 &&
3373 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3376 if (inst
->src
[1].file
== IMM
&&
3377 inst
->src
[1].ud
< (1 << 16)) {
3378 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3379 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3382 * If multiplying by an immediate value that fits in 16-bits, do a
3383 * single MUL instruction with that value in the proper location.
3385 if (devinfo
->gen
< 7) {
3386 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3388 ibld
.MOV(imm
, inst
->src
[1]);
3389 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3391 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3392 ibld
.MUL(inst
->dst
, inst
->src
[0],
3393 ud
? brw_imm_uw(inst
->src
[1].ud
)
3394 : brw_imm_w(inst
->src
[1].d
));
3397 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3398 * do 32-bit integer multiplication in one instruction, but instead
3399 * must do a sequence (which actually calculates a 64-bit result):
3401 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3402 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3403 * mov(8) g2<1>D acc0<8,8,1>D
3405 * But on Gen > 6, the ability to use second accumulator register
3406 * (acc1) for non-float data types was removed, preventing a simple
3407 * implementation in SIMD16. A 16-channel result can be calculated by
3408 * executing the three instructions twice in SIMD8, once with quarter
3409 * control of 1Q for the first eight channels and again with 2Q for
3410 * the second eight channels.
3412 * Which accumulator register is implicitly accessed (by AccWrEnable
3413 * for instance) is determined by the quarter control. Unfortunately
3414 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3415 * implicit accumulator access by an instruction with 2Q will access
3416 * acc1 regardless of whether the data type is usable in acc1.
3418 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3419 * integer data types.
3421 * Since we only want the low 32-bits of the result, we can do two
3422 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3423 * adjust the high result and add them (like the mach is doing):
3425 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3426 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3427 * shl(8) g9<1>D g8<8,8,1>D 16D
3428 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3430 * We avoid the shl instruction by realizing that we only want to add
3431 * the low 16-bits of the "high" result to the high 16-bits of the
3432 * "low" result and using proper regioning on the add:
3434 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3435 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3436 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3438 * Since it does not use the (single) accumulator register, we can
3439 * schedule multi-component multiplications much better.
3442 fs_reg orig_dst
= inst
->dst
;
3443 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3444 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3447 fs_reg low
= inst
->dst
;
3448 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3451 if (devinfo
->gen
>= 7) {
3452 if (inst
->src
[1].file
== IMM
) {
3453 ibld
.MUL(low
, inst
->src
[0],
3454 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
3455 ibld
.MUL(high
, inst
->src
[0],
3456 brw_imm_uw(inst
->src
[1].ud
>> 16));
3458 ibld
.MUL(low
, inst
->src
[0],
3459 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
3460 ibld
.MUL(high
, inst
->src
[0],
3461 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
3464 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
3466 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
3470 ibld
.ADD(subscript(inst
->dst
, BRW_REGISTER_TYPE_UW
, 1),
3471 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3472 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
3474 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3475 set_condmod(inst
->conditional_mod
,
3476 ibld
.MOV(orig_dst
, inst
->dst
));
3480 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3481 /* Should have been lowered to 8-wide. */
3482 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
3483 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3485 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3486 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3488 if (devinfo
->gen
>= 8) {
3489 /* Until Gen8, integer multiplies read 32-bits from one source,
3490 * and 16-bits from the other, and relying on the MACH instruction
3491 * to generate the high bits of the result.
3493 * On Gen8, the multiply instruction does a full 32x32-bit
3494 * multiply, but in order to do a 64-bit multiply we can simulate
3495 * the previous behavior and then use a MACH instruction.
3497 * FINISHME: Don't use source modifiers on src1.
3499 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3500 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3501 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3502 mul
->src
[1].stride
*= 2;
3504 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3506 /* Among other things the quarter control bits influence which
3507 * accumulator register is used by the hardware for instructions
3508 * that access the accumulator implicitly (e.g. MACH). A
3509 * second-half instruction would normally map to acc1, which
3510 * doesn't exist on Gen7 and up (the hardware does emulate it for
3511 * floating-point instructions *only* by taking advantage of the
3512 * extra precision of acc0 not normally used for floating point
3515 * HSW and up are careful enough not to try to access an
3516 * accumulator register that doesn't exist, but on earlier Gen7
3517 * hardware we need to make sure that the quarter control bits are
3518 * zero to avoid non-deterministic behaviour and emit an extra MOV
3519 * to get the result masked correctly according to the current
3523 mach
->force_writemask_all
= true;
3524 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3525 ibld
.MOV(inst
->dst
, mach
->dst
);
3531 inst
->remove(block
);
3536 invalidate_live_intervals();
3542 fs_visitor::lower_minmax()
3544 assert(devinfo
->gen
< 6);
3546 bool progress
= false;
3548 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3549 const fs_builder
ibld(this, block
, inst
);
3551 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3552 inst
->predicate
== BRW_PREDICATE_NONE
) {
3553 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3554 * the original SEL.L/GE instruction
3556 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3557 inst
->conditional_mod
);
3558 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3559 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3566 invalidate_live_intervals();
3572 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3573 fs_reg
*dst
, fs_reg color
, unsigned components
)
3575 if (key
->clamp_fragment_color
) {
3576 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3577 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3579 for (unsigned i
= 0; i
< components
; i
++)
3581 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3586 for (unsigned i
= 0; i
< components
; i
++)
3587 dst
[i
] = offset(color
, bld
, i
);
3591 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3592 const struct brw_wm_prog_data
*prog_data
,
3593 const brw_wm_prog_key
*key
,
3594 const fs_visitor::thread_payload
&payload
)
3596 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3597 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3598 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3599 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3600 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3601 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3602 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3603 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3604 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3605 const unsigned components
=
3606 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3608 /* We can potentially have a message length of up to 15, so we have to set
3609 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3612 int header_size
= 2, payload_header_size
;
3613 unsigned length
= 0;
3615 /* From the Sandy Bridge PRM, volume 4, page 198:
3617 * "Dispatched Pixel Enables. One bit per pixel indicating
3618 * which pixels were originally enabled when the thread was
3619 * dispatched. This field is only required for the end-of-
3620 * thread message and on all dual-source messages."
3622 if (devinfo
->gen
>= 6 &&
3623 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3624 color1
.file
== BAD_FILE
&&
3625 key
->nr_color_regions
== 1) {
3629 if (header_size
!= 0) {
3630 assert(header_size
== 2);
3631 /* Allocate 2 registers for a header */
3635 if (payload
.aa_dest_stencil_reg
) {
3636 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3637 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3638 .MOV(sources
[length
],
3639 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3643 if (sample_mask
.file
!= BAD_FILE
) {
3644 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3645 BRW_REGISTER_TYPE_UD
);
3647 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3648 * relevant. Since it's unsigned single words one vgrf is always
3649 * 16-wide, but only the lower or higher 8 channels will be used by the
3650 * hardware when doing a SIMD8 write depending on whether we have
3651 * selected the subspans for the first or second half respectively.
3653 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3654 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3655 sample_mask
.stride
*= 2;
3657 bld
.exec_all().annotate("FB write oMask")
3658 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3664 payload_header_size
= length
;
3666 if (src0_alpha
.file
!= BAD_FILE
) {
3667 /* FIXME: This is being passed at the wrong location in the payload and
3668 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3669 * It's supposed to be immediately before oMask but there seems to be no
3670 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3671 * requires header sources to form a contiguous segment at the beginning
3672 * of the message and src0_alpha has per-channel semantics.
3674 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3678 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3681 if (color1
.file
!= BAD_FILE
) {
3682 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3686 if (src_depth
.file
!= BAD_FILE
) {
3687 sources
[length
] = src_depth
;
3691 if (dst_depth
.file
!= BAD_FILE
) {
3692 sources
[length
] = dst_depth
;
3696 if (src_stencil
.file
!= BAD_FILE
) {
3697 assert(devinfo
->gen
>= 9);
3698 assert(bld
.dispatch_width() != 16);
3700 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3701 * available on gen9+. As such it's impossible to have both enabled at the
3702 * same time and therefore length cannot overrun the array.
3704 assert(length
< 15);
3706 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3707 bld
.exec_all().annotate("FB write OS")
3708 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
3709 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
3714 if (devinfo
->gen
>= 7) {
3715 /* Send from the GRF */
3716 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3717 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3718 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
3719 load
->dst
= payload
;
3721 inst
->src
[0] = payload
;
3722 inst
->resize_sources(1);
3724 /* Send from the MRF */
3725 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3726 sources
, length
, payload_header_size
);
3728 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3729 * will do this for us if we just give it a COMPR4 destination.
3731 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3732 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3734 inst
->resize_sources(0);
3738 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3739 inst
->mlen
= regs_written(load
);
3740 inst
->header_size
= header_size
;
3744 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
3746 const fs_builder
&ubld
= bld
.exec_all();
3747 const unsigned length
= 2;
3748 const fs_reg header
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
, length
);
3751 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3753 inst
->resize_sources(1);
3754 inst
->src
[0] = header
;
3755 inst
->opcode
= FS_OPCODE_FB_READ
;
3756 inst
->mlen
= length
;
3757 inst
->header_size
= length
;
3761 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3762 const fs_reg
&coordinate
,
3763 const fs_reg
&shadow_c
,
3764 const fs_reg
&lod
, const fs_reg
&lod2
,
3765 const fs_reg
&surface
,
3766 const fs_reg
&sampler
,
3767 unsigned coord_components
,
3768 unsigned grad_components
)
3770 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3771 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3772 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3773 fs_reg msg_end
= msg_begin
;
3776 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3778 for (unsigned i
= 0; i
< coord_components
; i
++)
3779 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3780 offset(coordinate
, bld
, i
));
3782 msg_end
= offset(msg_end
, bld
, coord_components
);
3784 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3785 * require all three components to be present and zero if they are unused.
3787 if (coord_components
> 0 &&
3788 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3789 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3790 for (unsigned i
= coord_components
; i
< 3; i
++)
3791 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3793 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3796 if (op
== SHADER_OPCODE_TXD
) {
3797 /* TXD unsupported in SIMD16 mode. */
3798 assert(bld
.dispatch_width() == 8);
3800 /* the slots for u and v are always present, but r is optional */
3801 if (coord_components
< 2)
3802 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3805 * dPdx = dudx, dvdx, drdx
3806 * dPdy = dudy, dvdy, drdy
3808 * 1-arg: Does not exist.
3810 * 2-arg: dudx dvdx dudy dvdy
3811 * dPdx.x dPdx.y dPdy.x dPdy.y
3814 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3815 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3816 * m5 m6 m7 m8 m9 m10
3818 for (unsigned i
= 0; i
< grad_components
; i
++)
3819 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3821 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3823 for (unsigned i
= 0; i
< grad_components
; i
++)
3824 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3826 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3830 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3831 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3833 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3834 bld
.dispatch_width() == 16);
3836 const brw_reg_type type
=
3837 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3838 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3839 bld
.MOV(retype(msg_end
, type
), lod
);
3840 msg_end
= offset(msg_end
, bld
, 1);
3843 if (shadow_c
.file
!= BAD_FILE
) {
3844 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3845 /* There's no plain shadow compare message, so we use shadow
3846 * compare with a bias of 0.0.
3848 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3849 msg_end
= offset(msg_end
, bld
, 1);
3852 bld
.MOV(msg_end
, shadow_c
);
3853 msg_end
= offset(msg_end
, bld
, 1);
3857 inst
->src
[0] = reg_undef
;
3858 inst
->src
[1] = surface
;
3859 inst
->src
[2] = sampler
;
3860 inst
->resize_sources(3);
3861 inst
->base_mrf
= msg_begin
.nr
;
3862 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3863 inst
->header_size
= 1;
3867 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3868 const fs_reg
&coordinate
,
3869 const fs_reg
&shadow_c
,
3870 const fs_reg
&lod
, const fs_reg
&lod2
,
3871 const fs_reg
&sample_index
,
3872 const fs_reg
&surface
,
3873 const fs_reg
&sampler
,
3874 const fs_reg
&offset_value
,
3875 unsigned coord_components
,
3876 unsigned grad_components
)
3878 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3879 fs_reg msg_coords
= message
;
3880 unsigned header_size
= 0;
3882 if (offset_value
.file
!= BAD_FILE
) {
3883 /* The offsets set up by the visitor are in the m1 header, so we can't
3890 for (unsigned i
= 0; i
< coord_components
; i
++)
3891 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
3892 offset(coordinate
, bld
, i
));
3894 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3895 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3897 if (shadow_c
.file
!= BAD_FILE
) {
3898 fs_reg msg_shadow
= msg_lod
;
3899 bld
.MOV(msg_shadow
, shadow_c
);
3900 msg_lod
= offset(msg_shadow
, bld
, 1);
3905 case SHADER_OPCODE_TXL
:
3907 bld
.MOV(msg_lod
, lod
);
3908 msg_end
= offset(msg_lod
, bld
, 1);
3910 case SHADER_OPCODE_TXD
:
3913 * dPdx = dudx, dvdx, drdx
3914 * dPdy = dudy, dvdy, drdy
3916 * Load up these values:
3917 * - dudx dudy dvdx dvdy drdx drdy
3918 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3921 for (unsigned i
= 0; i
< grad_components
; i
++) {
3922 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
3923 msg_end
= offset(msg_end
, bld
, 1);
3925 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
3926 msg_end
= offset(msg_end
, bld
, 1);
3929 case SHADER_OPCODE_TXS
:
3930 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3931 bld
.MOV(msg_lod
, lod
);
3932 msg_end
= offset(msg_lod
, bld
, 1);
3934 case SHADER_OPCODE_TXF
:
3935 msg_lod
= offset(msg_coords
, bld
, 3);
3936 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3937 msg_end
= offset(msg_lod
, bld
, 1);
3939 case SHADER_OPCODE_TXF_CMS
:
3940 msg_lod
= offset(msg_coords
, bld
, 3);
3942 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
3944 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3945 msg_end
= offset(msg_lod
, bld
, 2);
3952 inst
->src
[0] = reg_undef
;
3953 inst
->src
[1] = surface
;
3954 inst
->src
[2] = sampler
;
3955 inst
->resize_sources(3);
3956 inst
->base_mrf
= message
.nr
;
3957 inst
->mlen
= msg_end
.nr
- message
.nr
;
3958 inst
->header_size
= header_size
;
3960 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3961 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3965 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
3967 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3970 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
3974 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3975 const fs_reg
&coordinate
,
3976 const fs_reg
&shadow_c
,
3977 fs_reg lod
, const fs_reg
&lod2
,
3978 const fs_reg
&sample_index
,
3980 const fs_reg
&surface
,
3981 const fs_reg
&sampler
,
3982 const fs_reg
&offset_value
,
3983 unsigned coord_components
,
3984 unsigned grad_components
)
3986 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3987 unsigned reg_width
= bld
.dispatch_width() / 8;
3988 unsigned header_size
= 0, length
= 0;
3989 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3990 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3991 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3993 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3994 offset_value
.file
!= BAD_FILE
|| inst
->eot
||
3995 op
== SHADER_OPCODE_SAMPLEINFO
||
3996 is_high_sampler(devinfo
, sampler
)) {
3997 /* For general texture offsets (no txf workaround), we need a header to
3998 * put them in. Note that we're only reserving space for it in the
3999 * message payload as it will be initialized implicitly by the
4002 * TG4 needs to place its channel select in the header, for interaction
4003 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4004 * larger sampler numbers we need to offset the Sampler State Pointer in
4008 sources
[0] = fs_reg();
4011 /* If we're requesting fewer than four channels worth of response,
4012 * and we have an explicit header, we need to set up the sampler
4013 * writemask. It's reversed from normal: 1 means "don't write".
4015 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4016 assert(regs_written(inst
) % reg_width
== 0);
4017 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4018 inst
->offset
|= mask
<< 12;
4022 if (shadow_c
.file
!= BAD_FILE
) {
4023 bld
.MOV(sources
[length
], shadow_c
);
4027 bool coordinate_done
= false;
4029 /* Set up the LOD info */
4032 case SHADER_OPCODE_TXL
:
4033 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4034 op
= SHADER_OPCODE_TXL_LZ
;
4037 bld
.MOV(sources
[length
], lod
);
4040 case SHADER_OPCODE_TXD
:
4041 /* TXD should have been lowered in SIMD16 mode. */
4042 assert(bld
.dispatch_width() == 8);
4044 /* Load dPdx and the coordinate together:
4045 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4047 for (unsigned i
= 0; i
< coord_components
; i
++) {
4048 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4050 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4051 * only derivatives for (u, v, r).
4053 if (i
< grad_components
) {
4054 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4055 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4059 coordinate_done
= true;
4061 case SHADER_OPCODE_TXS
:
4062 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4065 case SHADER_OPCODE_TXF
:
4066 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4067 * On Gen9 they are u, v, lod, r
4069 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4071 if (devinfo
->gen
>= 9) {
4072 if (coord_components
>= 2) {
4073 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4074 offset(coordinate
, bld
, 1));
4076 sources
[length
] = brw_imm_d(0);
4081 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4082 op
= SHADER_OPCODE_TXF_LZ
;
4084 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4088 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4089 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4090 offset(coordinate
, bld
, i
));
4092 coordinate_done
= true;
4095 case SHADER_OPCODE_TXF_CMS
:
4096 case SHADER_OPCODE_TXF_CMS_W
:
4097 case SHADER_OPCODE_TXF_UMS
:
4098 case SHADER_OPCODE_TXF_MCS
:
4099 if (op
== SHADER_OPCODE_TXF_UMS
||
4100 op
== SHADER_OPCODE_TXF_CMS
||
4101 op
== SHADER_OPCODE_TXF_CMS_W
) {
4102 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4106 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4107 /* Data from the multisample control surface. */
4108 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4111 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4114 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4115 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4118 offset(mcs
, bld
, 1));
4123 /* There is no offsetting for this message; just copy in the integer
4124 * texture coordinates.
4126 for (unsigned i
= 0; i
< coord_components
; i
++)
4127 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4128 offset(coordinate
, bld
, i
));
4130 coordinate_done
= true;
4132 case SHADER_OPCODE_TG4_OFFSET
:
4133 /* More crazy intermixing */
4134 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4135 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4137 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4138 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4139 offset(offset_value
, bld
, i
));
4141 if (coord_components
== 3) /* r if present */
4142 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4144 coordinate_done
= true;
4150 /* Set up the coordinate (except for cases where it was done above) */
4151 if (!coordinate_done
) {
4152 for (unsigned i
= 0; i
< coord_components
; i
++)
4153 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4158 mlen
= length
* reg_width
- header_size
;
4160 mlen
= length
* reg_width
;
4162 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4163 BRW_REGISTER_TYPE_F
);
4164 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4166 /* Generate the SEND. */
4168 inst
->src
[0] = src_payload
;
4169 inst
->src
[1] = surface
;
4170 inst
->src
[2] = sampler
;
4171 inst
->resize_sources(3);
4173 inst
->header_size
= header_size
;
4175 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4176 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4180 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4182 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4183 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4184 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4185 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4186 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4187 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4188 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4189 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4190 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4191 const fs_reg
&offset_value
= inst
->src
[TEX_LOGICAL_SRC_OFFSET_VALUE
];
4192 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4193 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4194 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4195 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4197 if (devinfo
->gen
>= 7) {
4198 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4199 shadow_c
, lod
, lod2
, sample_index
,
4200 mcs
, surface
, sampler
, offset_value
,
4201 coord_components
, grad_components
);
4202 } else if (devinfo
->gen
>= 5) {
4203 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4204 shadow_c
, lod
, lod2
, sample_index
,
4205 surface
, sampler
, offset_value
,
4206 coord_components
, grad_components
);
4208 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4209 shadow_c
, lod
, lod2
,
4211 coord_components
, grad_components
);
4216 * Initialize the header present in some typed and untyped surface
4220 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4222 fs_builder ubld
= bld
.exec_all().group(8, 0);
4223 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4224 ubld
.MOV(dst
, brw_imm_d(0));
4225 ubld
.MOV(component(dst
, 7), sample_mask
);
4230 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4231 const fs_reg
&sample_mask
)
4233 /* Get the logical send arguments. */
4234 const fs_reg
&addr
= inst
->src
[0];
4235 const fs_reg
&src
= inst
->src
[1];
4236 const fs_reg
&surface
= inst
->src
[2];
4237 const UNUSED fs_reg
&dims
= inst
->src
[3];
4238 const fs_reg
&arg
= inst
->src
[4];
4240 /* Calculate the total number of components of the payload. */
4241 const unsigned addr_sz
= inst
->components_read(0);
4242 const unsigned src_sz
= inst
->components_read(1);
4243 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4244 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4246 /* Allocate space for the payload. */
4247 fs_reg
*const components
= new fs_reg
[sz
];
4248 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4251 /* Construct the payload. */
4253 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4255 for (unsigned i
= 0; i
< addr_sz
; i
++)
4256 components
[n
++] = offset(addr
, bld
, i
);
4258 for (unsigned i
= 0; i
< src_sz
; i
++)
4259 components
[n
++] = offset(src
, bld
, i
);
4261 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4263 /* Update the original instruction. */
4265 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4266 inst
->header_size
= header_sz
;
4268 inst
->src
[0] = payload
;
4269 inst
->src
[1] = surface
;
4271 inst
->resize_sources(3);
4273 delete[] components
;
4277 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4279 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4281 if (devinfo
->gen
>= 7) {
4282 /* We are switching the instruction from an ALU-like instruction to a
4283 * send-from-grf instruction. Since sends can't handle strides or
4284 * source modifiers, we have to make a copy of the offset source.
4286 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4287 bld
.MOV(tmp
, inst
->src
[1]);
4290 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4293 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4294 BRW_REGISTER_TYPE_UD
);
4296 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4298 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4299 inst
->resize_sources(1);
4300 inst
->base_mrf
= payload
.nr
;
4301 inst
->header_size
= 1;
4302 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4307 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4309 assert(bld
.shader
->devinfo
->gen
< 6);
4312 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4314 if (inst
->sources
> 1) {
4315 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4316 * "Message Payload":
4318 * "Operand0[7]. For the INT DIV functions, this operand is the
4321 * "Operand1[7]. For the INT DIV functions, this operand is the
4324 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4325 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4326 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4328 inst
->resize_sources(1);
4329 inst
->src
[0] = src0
;
4331 assert(inst
->exec_size
== 8);
4332 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4337 fs_visitor::lower_logical_sends()
4339 bool progress
= false;
4341 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4342 const fs_builder
ibld(this, block
, inst
);
4344 switch (inst
->opcode
) {
4345 case FS_OPCODE_FB_WRITE_LOGICAL
:
4346 assert(stage
== MESA_SHADER_FRAGMENT
);
4347 lower_fb_write_logical_send(ibld
, inst
,
4348 brw_wm_prog_data(prog_data
),
4349 (const brw_wm_prog_key
*)key
,
4353 case FS_OPCODE_FB_READ_LOGICAL
:
4354 lower_fb_read_logical_send(ibld
, inst
);
4357 case SHADER_OPCODE_TEX_LOGICAL
:
4358 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4361 case SHADER_OPCODE_TXD_LOGICAL
:
4362 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4365 case SHADER_OPCODE_TXF_LOGICAL
:
4366 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4369 case SHADER_OPCODE_TXL_LOGICAL
:
4370 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4373 case SHADER_OPCODE_TXS_LOGICAL
:
4374 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4377 case FS_OPCODE_TXB_LOGICAL
:
4378 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4381 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4382 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4385 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4386 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4389 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4390 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4393 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4394 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4397 case SHADER_OPCODE_LOD_LOGICAL
:
4398 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4401 case SHADER_OPCODE_TG4_LOGICAL
:
4402 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4405 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4406 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4409 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4410 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
4413 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4414 lower_surface_logical_send(ibld
, inst
,
4415 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4419 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4420 lower_surface_logical_send(ibld
, inst
,
4421 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4422 ibld
.sample_mask_reg());
4425 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4426 lower_surface_logical_send(ibld
, inst
,
4427 SHADER_OPCODE_UNTYPED_ATOMIC
,
4428 ibld
.sample_mask_reg());
4431 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4432 lower_surface_logical_send(ibld
, inst
,
4433 SHADER_OPCODE_TYPED_SURFACE_READ
,
4437 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4438 lower_surface_logical_send(ibld
, inst
,
4439 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4440 ibld
.sample_mask_reg());
4443 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4444 lower_surface_logical_send(ibld
, inst
,
4445 SHADER_OPCODE_TYPED_ATOMIC
,
4446 ibld
.sample_mask_reg());
4449 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4450 lower_varying_pull_constant_logical_send(ibld
, inst
);
4453 case SHADER_OPCODE_RCP
:
4454 case SHADER_OPCODE_RSQ
:
4455 case SHADER_OPCODE_SQRT
:
4456 case SHADER_OPCODE_EXP2
:
4457 case SHADER_OPCODE_LOG2
:
4458 case SHADER_OPCODE_SIN
:
4459 case SHADER_OPCODE_COS
:
4460 case SHADER_OPCODE_POW
:
4461 case SHADER_OPCODE_INT_QUOTIENT
:
4462 case SHADER_OPCODE_INT_REMAINDER
:
4463 /* The math opcodes are overloaded for the send-like and
4464 * expression-like instructions which seems kind of icky. Gen6+ has
4465 * a native (but rather quirky) MATH instruction so we don't need to
4466 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
4467 * logical instructions (which we can easily recognize because they
4468 * have mlen = 0) into send-like virtual instructions.
4470 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
4471 lower_math_logical_send(ibld
, inst
);
4486 invalidate_live_intervals();
4492 * Get the closest allowed SIMD width for instruction \p inst accounting for
4493 * some common regioning and execution control restrictions that apply to FPU
4494 * instructions. These restrictions don't necessarily have any relevance to
4495 * instructions not executed by the FPU pipeline like extended math, control
4496 * flow or send message instructions.
4498 * For virtual opcodes it's really up to the instruction -- In some cases
4499 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
4500 * instructions) it may simplify virtual instruction lowering if we can
4501 * enforce FPU-like regioning restrictions already on the virtual instruction,
4502 * in other cases (e.g. virtual send-like instructions) this may be
4503 * excessively restrictive.
4506 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
4507 const fs_inst
*inst
)
4509 /* Maximum execution size representable in the instruction controls. */
4510 unsigned max_width
= MIN2(32, inst
->exec_size
);
4512 /* According to the PRMs:
4513 * "A. In Direct Addressing mode, a source cannot span more than 2
4514 * adjacent GRF registers.
4515 * B. A destination cannot span more than 2 adjacent GRF registers."
4517 * Look for the source or destination with the largest register region
4518 * which is the one that is going to limit the overall execution size of
4519 * the instruction due to this rule.
4521 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4523 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4524 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
4526 /* Calculate the maximum execution size of the instruction based on the
4527 * factor by which it goes over the hardware limit of 2 GRFs.
4530 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
4532 /* According to the IVB PRMs:
4533 * "When destination spans two registers, the source MUST span two
4534 * registers. The exception to the above rule:
4536 * - When source is scalar, the source registers are not incremented.
4537 * - When source is packed integer Word and destination is packed
4538 * integer DWord, the source register is not incremented but the
4539 * source sub register is incremented."
4541 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
4542 * restrictions. The code below intentionally doesn't check whether the
4543 * destination type is integer because empirically the hardware doesn't
4544 * seem to care what the actual type is as long as it's dword-aligned.
4546 if (devinfo
->gen
< 8) {
4547 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
4548 if (inst
->size_written
> REG_SIZE
&&
4549 inst
->size_read(i
) != 0 && inst
->size_read(i
) <= REG_SIZE
&&
4550 !is_uniform(inst
->src
[i
]) &&
4551 !(type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
4552 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1)) {
4553 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4554 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4559 /* From the IVB PRMs:
4560 * "When an instruction is SIMD32, the low 16 bits of the execution mask
4561 * are applied for both halves of the SIMD32 instruction. If different
4562 * execution mask channels are required, split the instruction into two
4563 * SIMD16 instructions."
4565 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
4566 * 32-wide control flow support in hardware and will behave similarly.
4568 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
4569 max_width
= MIN2(max_width
, 16);
4571 /* From the IVB PRMs (applies to HSW too):
4572 * "Instructions with condition modifiers must not use SIMD32."
4574 * From the BDW PRMs (applies to later hardware too):
4575 * "Ternary instruction with condition modifiers must not use SIMD32."
4577 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
4578 max_width
= MIN2(max_width
, 16);
4580 /* From the IVB PRMs (applies to other devices that don't have the
4581 * gen_device_info::supports_simd16_3src flag set):
4582 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
4583 * SIMD8 is not allowed for DF operations."
4585 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
4586 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4588 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
4589 * the 8-bit quarter of the execution mask signals specified in the
4590 * instruction control fields) for the second compressed half of any
4591 * single-precision instruction (for double-precision instructions
4592 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
4593 * the EU will apply the wrong execution controls for the second
4594 * sequential GRF write if the number of channels per GRF is not exactly
4595 * eight in single-precision mode (or four in double-float mode).
4597 * In this situation we calculate the maximum size of the split
4598 * instructions so they only ever write to a single register.
4600 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
4601 !inst
->force_writemask_all
) {
4602 const unsigned channels_per_grf
= inst
->exec_size
/
4603 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4604 unsigned exec_type_size
= 0;
4605 for (int i
= 0; i
< inst
->sources
; i
++) {
4606 if (inst
->src
[i
].file
!= BAD_FILE
)
4607 exec_type_size
= MAX2(exec_type_size
, type_sz(inst
->src
[i
].type
));
4609 assert(exec_type_size
);
4611 /* The hardware shifts exactly 8 channels per compressed half of the
4612 * instruction in single-precision mode and exactly 4 in double-precision.
4614 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
4615 max_width
= MIN2(max_width
, channels_per_grf
);
4618 /* Only power-of-two execution sizes are representable in the instruction
4621 return 1 << _mesa_logbase2(max_width
);
4625 * Get the maximum allowed SIMD width for instruction \p inst accounting for
4626 * various payload size restrictions that apply to sampler message
4629 * This is only intended to provide a maximum theoretical bound for the
4630 * execution size of the message based on the number of argument components
4631 * alone, which in most cases will determine whether the SIMD8 or SIMD16
4632 * variant of the message can be used, though some messages may have
4633 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
4634 * the message length to determine the exact SIMD width and argument count,
4635 * which makes a number of sampler message combinations impossible to
4639 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
4640 const fs_inst
*inst
)
4642 /* Calculate the number of coordinate components that have to be present
4643 * assuming that additional arguments follow the texel coordinates in the
4644 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
4645 * need to pad to four or three components depending on the message,
4646 * pre-ILK we need to pad to at most three components.
4648 const unsigned req_coord_components
=
4649 (devinfo
->gen
>= 7 ||
4650 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
4651 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
4652 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
4655 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
4656 * variant of the TXL or TXF message.
4658 const bool implicit_lod
= devinfo
->gen
>= 9 &&
4659 (inst
->opcode
== SHADER_OPCODE_TXL
||
4660 inst
->opcode
== SHADER_OPCODE_TXF
) &&
4661 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
4663 /* Calculate the total number of argument components that need to be passed
4664 * to the sampler unit.
4666 const unsigned num_payload_components
=
4667 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
4668 req_coord_components
) +
4669 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
4670 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
4671 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
4672 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
4673 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
4674 inst
->components_read(TEX_LOGICAL_SRC_OFFSET_VALUE
) : 0) +
4675 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
4677 /* SIMD16 messages with more than five arguments exceed the maximum message
4678 * size supported by the sampler, regardless of whether a header is
4681 return MIN2(inst
->exec_size
,
4682 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
4686 * Get the closest native SIMD width supported by the hardware for instruction
4687 * \p inst. The instruction will be left untouched by
4688 * fs_visitor::lower_simd_width() if the returned value is equal to the
4689 * original execution size.
4692 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
4693 const fs_inst
*inst
)
4695 switch (inst
->opcode
) {
4696 case BRW_OPCODE_MOV
:
4697 case BRW_OPCODE_SEL
:
4698 case BRW_OPCODE_NOT
:
4699 case BRW_OPCODE_AND
:
4701 case BRW_OPCODE_XOR
:
4702 case BRW_OPCODE_SHR
:
4703 case BRW_OPCODE_SHL
:
4704 case BRW_OPCODE_ASR
:
4705 case BRW_OPCODE_CMPN
:
4706 case BRW_OPCODE_CSEL
:
4707 case BRW_OPCODE_F32TO16
:
4708 case BRW_OPCODE_F16TO32
:
4709 case BRW_OPCODE_BFREV
:
4710 case BRW_OPCODE_BFE
:
4711 case BRW_OPCODE_ADD
:
4712 case BRW_OPCODE_MUL
:
4713 case BRW_OPCODE_AVG
:
4714 case BRW_OPCODE_FRC
:
4715 case BRW_OPCODE_RNDU
:
4716 case BRW_OPCODE_RNDD
:
4717 case BRW_OPCODE_RNDE
:
4718 case BRW_OPCODE_RNDZ
:
4719 case BRW_OPCODE_LZD
:
4720 case BRW_OPCODE_FBH
:
4721 case BRW_OPCODE_FBL
:
4722 case BRW_OPCODE_CBIT
:
4723 case BRW_OPCODE_SAD2
:
4724 case BRW_OPCODE_MAD
:
4725 case BRW_OPCODE_LRP
:
4726 case FS_OPCODE_PACK
:
4727 return get_fpu_lowered_simd_width(devinfo
, inst
);
4729 case BRW_OPCODE_CMP
: {
4730 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
4731 * when the destination is a GRF the dependency-clear bit on the flag
4732 * register is cleared early.
4734 * Suggested workarounds are to disable coissuing CMP instructions
4735 * or to split CMP(16) instructions into two CMP(8) instructions.
4737 * We choose to split into CMP(8) instructions since disabling
4738 * coissuing would affect CMP instructions not otherwise affected by
4741 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4742 !inst
->dst
.is_null() ? 8 : ~0);
4743 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
4745 case BRW_OPCODE_BFI1
:
4746 case BRW_OPCODE_BFI2
:
4747 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
4749 * "Force BFI instructions to be executed always in SIMD8."
4751 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
4752 get_fpu_lowered_simd_width(devinfo
, inst
));
4755 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
4756 return inst
->exec_size
;
4758 case SHADER_OPCODE_RCP
:
4759 case SHADER_OPCODE_RSQ
:
4760 case SHADER_OPCODE_SQRT
:
4761 case SHADER_OPCODE_EXP2
:
4762 case SHADER_OPCODE_LOG2
:
4763 case SHADER_OPCODE_SIN
:
4764 case SHADER_OPCODE_COS
:
4765 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
4768 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4769 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
4770 MIN2(8, inst
->exec_size
));
4772 case SHADER_OPCODE_POW
:
4773 /* SIMD16 is only allowed on Gen7+. */
4774 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4775 MIN2(8, inst
->exec_size
));
4777 case SHADER_OPCODE_INT_QUOTIENT
:
4778 case SHADER_OPCODE_INT_REMAINDER
:
4779 /* Integer division is limited to SIMD8 on all generations. */
4780 return MIN2(8, inst
->exec_size
);
4782 case FS_OPCODE_LINTERP
:
4783 case FS_OPCODE_GET_BUFFER_SIZE
:
4784 case FS_OPCODE_DDX_COARSE
:
4785 case FS_OPCODE_DDX_FINE
:
4786 case FS_OPCODE_DDY_COARSE
:
4787 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
4788 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
4789 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
4790 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
4791 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
4792 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
4793 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
4794 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
4795 return MIN2(16, inst
->exec_size
);
4797 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4798 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
4799 * message used to implement varying pull constant loads, so expand it
4800 * to SIMD16. An alternative with longer message payload length but
4801 * shorter return payload would be to use the SIMD8 sampler message that
4802 * takes (header, u, v, r) as parameters instead of (header, u).
4804 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
4806 case FS_OPCODE_DDY_FINE
:
4807 /* The implementation of this virtual opcode may require emitting
4808 * compressed Align16 instructions, which are severely limited on some
4811 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
4812 * Region Restrictions):
4814 * "In Align16 access mode, SIMD16 is not allowed for DW operations
4815 * and SIMD8 is not allowed for DF operations."
4817 * In this context, "DW operations" means "operations acting on 32-bit
4818 * values", so it includes operations on floats.
4820 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
4821 * (Instruction Compression -> Rules and Restrictions):
4823 * "A compressed instruction must be in Align1 access mode. Align16
4824 * mode instructions cannot be compressed."
4826 * Similar text exists in the g45 PRM.
4828 * Empirically, compressed align16 instructions using odd register
4829 * numbers don't appear to work on Sandybridge either.
4831 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
4832 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
4833 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
4835 case SHADER_OPCODE_MULH
:
4836 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4837 * is 8-wide on Gen7+.
4839 return (devinfo
->gen
>= 7 ? 8 :
4840 get_fpu_lowered_simd_width(devinfo
, inst
));
4842 case FS_OPCODE_FB_WRITE_LOGICAL
:
4843 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4846 assert(devinfo
->gen
!= 6 ||
4847 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4848 inst
->exec_size
== 8);
4849 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4850 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4851 8 : MIN2(16, inst
->exec_size
));
4853 case FS_OPCODE_FB_READ_LOGICAL
:
4854 return MIN2(16, inst
->exec_size
);
4856 case SHADER_OPCODE_TEX_LOGICAL
:
4857 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4858 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4859 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4860 case SHADER_OPCODE_LOD_LOGICAL
:
4861 case SHADER_OPCODE_TG4_LOGICAL
:
4862 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4863 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4864 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4865 return get_sampler_lowered_simd_width(devinfo
, inst
);
4867 case SHADER_OPCODE_TXD_LOGICAL
:
4868 /* TXD is unsupported in SIMD16 mode. */
4871 case SHADER_OPCODE_TXL_LOGICAL
:
4872 case FS_OPCODE_TXB_LOGICAL
:
4873 /* Only one execution size is representable pre-ILK depending on whether
4874 * the shadow reference argument is present.
4876 if (devinfo
->gen
== 4)
4877 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
4879 return get_sampler_lowered_simd_width(devinfo
, inst
);
4881 case SHADER_OPCODE_TXF_LOGICAL
:
4882 case SHADER_OPCODE_TXS_LOGICAL
:
4883 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4884 * messages. Use SIMD16 instead.
4886 if (devinfo
->gen
== 4)
4889 return get_sampler_lowered_simd_width(devinfo
, inst
);
4891 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4892 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4893 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4896 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4897 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4898 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4899 return MIN2(16, inst
->exec_size
);
4901 case SHADER_OPCODE_URB_READ_SIMD8
:
4902 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
4903 case SHADER_OPCODE_URB_WRITE_SIMD8
:
4904 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
4905 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
4906 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
4907 return MIN2(8, inst
->exec_size
);
4909 case SHADER_OPCODE_MOV_INDIRECT
:
4910 /* Prior to Broadwell, we only have 8 address subregisters */
4911 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
4912 2 * REG_SIZE
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
4915 case SHADER_OPCODE_LOAD_PAYLOAD
: {
4916 const unsigned reg_count
=
4917 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
4919 if (reg_count
> 2) {
4920 /* Only LOAD_PAYLOAD instructions with per-channel destination region
4921 * can be easily lowered (which excludes headers and heterogeneous
4924 assert(!inst
->header_size
);
4925 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4926 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
4927 inst
->src
[i
].file
== BAD_FILE
);
4929 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4931 return inst
->exec_size
;
4935 return inst
->exec_size
;
4940 * Return true if splitting out the group of channels of instruction \p inst
4941 * given by lbld.group() requires allocating a temporary for the i-th source
4942 * of the lowered instruction.
4945 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
4947 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
4948 (inst
->components_read(i
) == 1 &&
4949 lbld
.dispatch_width() <= inst
->exec_size
));
4953 * Extract the data that would be consumed by the channel group given by
4954 * lbld.group() from the i-th source region of instruction \p inst and return
4955 * it as result in packed form. If any copy instructions are required they
4956 * will be emitted before the given \p inst in \p block.
4959 emit_unzip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
,
4962 /* Specified channel group from the source region. */
4963 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group());
4965 if (needs_src_copy(lbld
, inst
, i
)) {
4966 /* Builder of the right width to perform the copy avoiding uninitialized
4967 * data if the lowered execution size is greater than the original
4968 * execution size of the instruction.
4970 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
4971 inst
->exec_size
), 0);
4972 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
4974 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
4975 cbld
.at(block
, inst
)
4976 .MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
4980 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
4981 /* The source is invariant for all dispatch_width-wide groups of the
4984 return inst
->src
[i
];
4987 /* We can just point the lowered instruction at the right channel group
4988 * from the original region.
4995 * Return true if splitting out the group of channels of instruction \p inst
4996 * given by lbld.group() requires allocating a temporary for the destination
4997 * of the lowered instruction and copying the data back to the original
4998 * destination region.
5001 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
5003 /* If the instruction writes more than one component we'll have to shuffle
5004 * the results of multiple lowered instructions in order to make sure that
5005 * they end up arranged correctly in the original destination region.
5007 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
5010 /* If the lowered execution size is larger than the original the result of
5011 * the instruction won't fit in the original destination, so we'll have to
5012 * allocate a temporary in any case.
5014 if (lbld
.dispatch_width() > inst
->exec_size
)
5017 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5018 /* If we already made a copy of the source for other reasons there won't
5019 * be any overlap with the destination.
5021 if (needs_src_copy(lbld
, inst
, i
))
5024 /* In order to keep the logic simple we emit a copy whenever the
5025 * destination region doesn't exactly match an overlapping source, which
5026 * may point at the source and destination not being aligned group by
5027 * group which could cause one of the lowered instructions to overwrite
5028 * the data read from the same source by other lowered instructions.
5030 if (regions_overlap(inst
->dst
, inst
->size_written
,
5031 inst
->src
[i
], inst
->size_read(i
)) &&
5032 !inst
->dst
.equals(inst
->src
[i
]))
5040 * Insert data from a packed temporary into the channel group given by
5041 * lbld.group() of the destination region of instruction \p inst and return
5042 * the temporary as result. If any copy instructions are required they will
5043 * be emitted around the given \p inst in \p block.
5046 emit_zip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
)
5048 /* Builder of the right width to perform the copy avoiding uninitialized
5049 * data if the lowered execution size is greater than the original
5050 * execution size of the instruction.
5052 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5053 inst
->exec_size
), 0);
5055 /* Specified channel group from the destination region. */
5056 const fs_reg dst
= horiz_offset(inst
->dst
, lbld
.group());
5057 const unsigned dst_size
= inst
->size_written
/
5058 inst
->dst
.component_size(inst
->exec_size
);
5060 if (needs_dst_copy(lbld
, inst
)) {
5061 const fs_reg tmp
= lbld
.vgrf(inst
->dst
.type
, dst_size
);
5063 if (inst
->predicate
) {
5064 /* Handle predication by copying the original contents of
5065 * the destination into the temporary before emitting the
5066 * lowered instruction.
5068 for (unsigned k
= 0; k
< dst_size
; ++k
)
5069 cbld
.at(block
, inst
)
5070 .MOV(offset(tmp
, lbld
, k
), offset(dst
, inst
->exec_size
, k
));
5073 for (unsigned k
= 0; k
< dst_size
; ++k
)
5074 cbld
.at(block
, inst
->next
)
5075 .MOV(offset(dst
, inst
->exec_size
, k
), offset(tmp
, lbld
, k
));
5080 /* No need to allocate a temporary for the lowered instruction, just
5081 * take the right group of channels from the original region.
5088 fs_visitor::lower_simd_width()
5090 bool progress
= false;
5092 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5093 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5095 if (lower_width
!= inst
->exec_size
) {
5096 /* Builder matching the original instruction. We may also need to
5097 * emit an instruction of width larger than the original, set the
5098 * execution size of the builder to the highest of both for now so
5099 * we're sure that both cases can be handled.
5101 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5102 const fs_builder ibld
= bld
.at(block
, inst
)
5103 .exec_all(inst
->force_writemask_all
)
5104 .group(max_width
, inst
->group
/ max_width
);
5106 /* Split the copies in chunks of the execution width of either the
5107 * original or the lowered instruction, whichever is lower.
5109 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5110 const unsigned dst_size
= inst
->size_written
/
5111 inst
->dst
.component_size(inst
->exec_size
);
5113 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5115 for (unsigned i
= 0; i
< n
; i
++) {
5116 /* Emit a copy of the original instruction with the lowered width.
5117 * If the EOT flag was set throw it away except for the last
5118 * instruction to avoid killing the thread prematurely.
5120 fs_inst split_inst
= *inst
;
5121 split_inst
.exec_size
= lower_width
;
5122 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
5124 /* Select the correct channel enables for the i-th group, then
5125 * transform the sources and destination and emit the lowered
5128 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5130 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5131 split_inst
.src
[j
] = emit_unzip(lbld
, block
, inst
, j
);
5133 split_inst
.dst
= emit_zip(lbld
, block
, inst
);
5134 split_inst
.size_written
=
5135 split_inst
.dst
.component_size(lower_width
) * dst_size
;
5137 lbld
.emit(split_inst
);
5140 inst
->remove(block
);
5146 invalidate_live_intervals();
5152 fs_visitor::dump_instructions()
5154 dump_instructions(NULL
);
5158 fs_visitor::dump_instructions(const char *name
)
5160 FILE *file
= stderr
;
5161 if (name
&& geteuid() != 0) {
5162 file
= fopen(name
, "w");
5168 calculate_register_pressure();
5169 int ip
= 0, max_pressure
= 0;
5170 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5171 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5172 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5173 dump_instruction(inst
, file
);
5176 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5179 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5180 fprintf(file
, "%4d: ", ip
++);
5181 dump_instruction(inst
, file
);
5185 if (file
!= stderr
) {
5191 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5193 dump_instruction(be_inst
, stderr
);
5197 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5199 fs_inst
*inst
= (fs_inst
*)be_inst
;
5201 if (inst
->predicate
) {
5202 fprintf(file
, "(%cf0.%d) ",
5203 inst
->predicate_inverse
? '-' : '+',
5207 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5209 fprintf(file
, ".sat");
5210 if (inst
->conditional_mod
) {
5211 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5212 if (!inst
->predicate
&&
5213 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5214 inst
->opcode
!= BRW_OPCODE_IF
&&
5215 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5216 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
5219 fprintf(file
, "(%d) ", inst
->exec_size
);
5222 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5226 fprintf(file
, "(EOT) ");
5229 switch (inst
->dst
.file
) {
5231 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
5234 fprintf(file
, "g%d", inst
->dst
.nr
);
5237 fprintf(file
, "m%d", inst
->dst
.nr
);
5240 fprintf(file
, "(null)");
5243 fprintf(file
, "***u%d***", inst
->dst
.nr
);
5246 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
5249 switch (inst
->dst
.nr
) {
5251 fprintf(file
, "null");
5253 case BRW_ARF_ADDRESS
:
5254 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
5256 case BRW_ARF_ACCUMULATOR
:
5257 fprintf(file
, "acc%d", inst
->dst
.subnr
);
5260 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5263 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5268 unreachable("not reached");
5271 if (inst
->dst
.offset
||
5272 (inst
->dst
.file
== VGRF
&&
5273 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
5274 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
5275 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
5276 inst
->dst
.offset
% reg_size
);
5279 if (inst
->dst
.stride
!= 1)
5280 fprintf(file
, "<%u>", inst
->dst
.stride
);
5281 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
5283 for (int i
= 0; i
< inst
->sources
; i
++) {
5284 if (inst
->src
[i
].negate
)
5286 if (inst
->src
[i
].abs
)
5288 switch (inst
->src
[i
].file
) {
5290 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
5293 fprintf(file
, "g%d", inst
->src
[i
].nr
);
5296 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
5299 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
5302 fprintf(file
, "u%d", inst
->src
[i
].nr
);
5305 fprintf(file
, "(null)");
5308 switch (inst
->src
[i
].type
) {
5309 case BRW_REGISTER_TYPE_F
:
5310 fprintf(file
, "%-gf", inst
->src
[i
].f
);
5312 case BRW_REGISTER_TYPE_DF
:
5313 fprintf(file
, "%fdf", inst
->src
[i
].df
);
5315 case BRW_REGISTER_TYPE_W
:
5316 case BRW_REGISTER_TYPE_D
:
5317 fprintf(file
, "%dd", inst
->src
[i
].d
);
5319 case BRW_REGISTER_TYPE_UW
:
5320 case BRW_REGISTER_TYPE_UD
:
5321 fprintf(file
, "%uu", inst
->src
[i
].ud
);
5323 case BRW_REGISTER_TYPE_VF
:
5324 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
5325 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
5326 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
5327 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
5328 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5331 fprintf(file
, "???");
5336 switch (inst
->src
[i
].nr
) {
5338 fprintf(file
, "null");
5340 case BRW_ARF_ADDRESS
:
5341 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5343 case BRW_ARF_ACCUMULATOR
:
5344 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5347 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5350 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5356 if (inst
->src
[i
].offset
||
5357 (inst
->src
[i
].file
== VGRF
&&
5358 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
5359 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
5360 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
5361 inst
->src
[i
].offset
% reg_size
);
5364 if (inst
->src
[i
].abs
)
5367 if (inst
->src
[i
].file
!= IMM
) {
5369 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5370 unsigned hstride
= inst
->src
[i
].hstride
;
5371 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5373 stride
= inst
->src
[i
].stride
;
5376 fprintf(file
, "<%u>", stride
);
5378 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
5381 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5382 fprintf(file
, ", ");
5387 if (inst
->force_writemask_all
)
5388 fprintf(file
, "NoMask ");
5390 if (inst
->exec_size
!= dispatch_width
)
5391 fprintf(file
, "group%d ", inst
->group
);
5393 fprintf(file
, "\n");
5397 * Possibly returns an instruction that set up @param reg.
5399 * Sometimes we want to take the result of some expression/variable
5400 * dereference tree and rewrite the instruction generating the result
5401 * of the tree. When processing the tree, we know that the
5402 * instructions generated are all writing temporaries that are dead
5403 * outside of this tree. So, if we have some instructions that write
5404 * a temporary, we're free to point that temp write somewhere else.
5406 * Note that this doesn't guarantee that the instruction generated
5407 * only reg -- it might be the size=4 destination of a texture instruction.
5410 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5415 end
->is_partial_write() ||
5416 !reg
.equals(end
->dst
)) {
5424 fs_visitor::setup_fs_payload_gen6()
5426 assert(stage
== MESA_SHADER_FRAGMENT
);
5427 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
5429 assert(devinfo
->gen
>= 6);
5431 /* R0-1: masks, pixel X/Y coordinates. */
5432 payload
.num_regs
= 2;
5433 /* R2: only for 32-pixel dispatch.*/
5435 /* R3-26: barycentric interpolation coordinates. These appear in the
5436 * same order that they appear in the brw_barycentric_mode
5437 * enum. Each set of coordinates occupies 2 registers if dispatch width
5438 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5439 * appear if they were enabled using the "Barycentric Interpolation
5440 * Mode" bits in WM_STATE.
5442 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
5443 if (prog_data
->barycentric_interp_modes
& (1 << i
)) {
5444 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5445 payload
.num_regs
+= 2;
5446 if (dispatch_width
== 16) {
5447 payload
.num_regs
+= 2;
5452 /* R27: interpolated depth if uses source depth */
5453 prog_data
->uses_src_depth
=
5454 (nir
->info
->inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5455 if (prog_data
->uses_src_depth
) {
5456 payload
.source_depth_reg
= payload
.num_regs
;
5458 if (dispatch_width
== 16) {
5459 /* R28: interpolated depth if not SIMD8. */
5464 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5465 prog_data
->uses_src_w
=
5466 (nir
->info
->inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5467 if (prog_data
->uses_src_w
) {
5468 payload
.source_w_reg
= payload
.num_regs
;
5470 if (dispatch_width
== 16) {
5471 /* R30: interpolated W if not SIMD8. */
5476 /* R31: MSAA position offsets. */
5477 if (prog_data
->persample_dispatch
&&
5478 (nir
->info
->system_values_read
& SYSTEM_BIT_SAMPLE_POS
)) {
5479 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
5481 * "MSDISPMODE_PERSAMPLE is required in order to select
5484 * So we can only really get sample positions if we are doing real
5485 * per-sample dispatch. If we need gl_SamplePosition and we don't have
5486 * persample dispatch, we hard-code it to 0.5.
5488 prog_data
->uses_pos_offset
= true;
5489 payload
.sample_pos_reg
= payload
.num_regs
;
5493 /* R32: MSAA input coverage mask */
5494 prog_data
->uses_sample_mask
=
5495 (nir
->info
->system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5496 if (prog_data
->uses_sample_mask
) {
5497 assert(devinfo
->gen
>= 7);
5498 payload
.sample_mask_in_reg
= payload
.num_regs
;
5500 if (dispatch_width
== 16) {
5501 /* R33: input coverage mask if not SIMD8. */
5506 /* R34-: bary for 32-pixel. */
5507 /* R58-59: interp W for 32-pixel. */
5509 if (nir
->info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5510 source_depth_to_render_target
= true;
5515 fs_visitor::setup_vs_payload()
5517 /* R0: thread header, R1: urb handles */
5518 payload
.num_regs
= 2;
5522 fs_visitor::setup_gs_payload()
5524 assert(stage
== MESA_SHADER_GEOMETRY
);
5526 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
5527 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
5529 /* R0: thread header, R1: output URB handles */
5530 payload
.num_regs
= 2;
5532 if (gs_prog_data
->include_primitive_id
) {
5533 /* R2: Primitive ID 0..7 */
5537 /* Use a maximum of 24 registers for push-model inputs. */
5538 const unsigned max_push_components
= 24;
5540 /* If pushing our inputs would take too many registers, reduce the URB read
5541 * length (which is in HWords, or 8 registers), and resort to pulling.
5543 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5544 * have to multiply by VerticesIn to obtain the total storage requirement.
5546 if (8 * vue_prog_data
->urb_read_length
* nir
->info
->gs
.vertices_in
>
5547 max_push_components
|| gs_prog_data
->invocations
> 1) {
5548 gs_prog_data
->base
.include_vue_handles
= true;
5550 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5551 payload
.num_regs
+= nir
->info
->gs
.vertices_in
;
5553 vue_prog_data
->urb_read_length
=
5554 ROUND_DOWN_TO(max_push_components
/ nir
->info
->gs
.vertices_in
, 8) / 8;
5559 fs_visitor::setup_cs_payload()
5561 assert(devinfo
->gen
>= 7);
5562 payload
.num_regs
= 1;
5566 fs_visitor::calculate_register_pressure()
5568 invalidate_live_intervals();
5569 calculate_live_intervals();
5571 unsigned num_instructions
= 0;
5572 foreach_block(block
, cfg
)
5573 num_instructions
+= block
->instructions
.length();
5575 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5577 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5578 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5579 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5584 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
5586 * The needs_unlit_centroid_workaround ends up producing one of these per
5587 * channel of centroid input, so it's good to clean them up.
5589 * An assumption here is that nothing ever modifies the dispatched pixels
5590 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
5591 * dictates that anyway.
5594 fs_visitor::opt_drop_redundant_mov_to_flags()
5596 bool flag_mov_found
[2] = {false};
5597 bool progress
= false;
5599 /* Instructions removed by this pass can only be added if this were true */
5600 if (!devinfo
->needs_unlit_centroid_workaround
)
5603 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5604 if (inst
->is_control_flow()) {
5605 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
5606 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
5607 if (!flag_mov_found
[inst
->flag_subreg
]) {
5608 flag_mov_found
[inst
->flag_subreg
] = true;
5610 inst
->remove(block
);
5613 } else if (inst
->flags_written()) {
5614 flag_mov_found
[inst
->flag_subreg
] = false;
5622 fs_visitor::optimize()
5624 /* Start by validating the shader we currently have. */
5627 /* bld is the common builder object pointing at the end of the program we
5628 * used to translate it into i965 IR. For the optimization and lowering
5629 * passes coming next, any code added after the end of the program without
5630 * having explicitly called fs_builder::at() clearly points at a mistake.
5631 * Ideally optimization passes wouldn't be part of the visitor so they
5632 * wouldn't have access to bld at all, but they do, so just in case some
5633 * pass forgets to ask for a location explicitly set it to NULL here to
5634 * make it trip. The dispatch width is initialized to a bogus value to
5635 * make sure that optimizations set the execution controls explicitly to
5636 * match the code they are manipulating instead of relying on the defaults.
5638 bld
= fs_builder(this, 64);
5640 assign_constant_locations();
5641 lower_constant_loads();
5645 split_virtual_grfs();
5648 #define OPT(pass, args...) ({ \
5650 bool this_progress = pass(args); \
5652 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5653 char filename[64]; \
5654 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5655 stage_abbrev, dispatch_width, nir->info->name, iteration, pass_num); \
5657 backend_shader::dump_instructions(filename); \
5662 progress = progress || this_progress; \
5666 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5668 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5669 stage_abbrev
, dispatch_width
, nir
->info
->name
);
5671 backend_shader::dump_instructions(filename
);
5674 bool progress
= false;
5678 OPT(opt_drop_redundant_mov_to_flags
);
5685 OPT(remove_duplicate_mrf_writes
);
5689 OPT(opt_copy_propagate
);
5690 OPT(opt_predicated_break
, this);
5691 OPT(opt_cmod_propagation
);
5692 OPT(dead_code_eliminate
);
5693 OPT(opt_peephole_sel
);
5694 OPT(dead_control_flow_eliminate
, this);
5695 OPT(opt_register_renaming
);
5696 OPT(opt_saturate_propagation
);
5697 OPT(register_coalesce
);
5698 OPT(compute_to_mrf
);
5699 OPT(eliminate_find_live_channel
);
5701 OPT(compact_virtual_grfs
);
5707 if (OPT(lower_pack
)) {
5708 OPT(register_coalesce
);
5709 OPT(dead_code_eliminate
);
5712 if (OPT(lower_d2x
)) {
5713 OPT(opt_copy_propagate
);
5714 OPT(dead_code_eliminate
);
5717 OPT(lower_simd_width
);
5719 /* After SIMD lowering just in case we had to unroll the EOT send. */
5720 OPT(opt_sampler_eot
);
5722 OPT(lower_logical_sends
);
5725 OPT(opt_copy_propagate
);
5726 /* Only run after logical send lowering because it's easier to implement
5727 * in terms of physical sends.
5729 if (OPT(opt_zero_samples
))
5730 OPT(opt_copy_propagate
);
5731 /* Run after logical send lowering to give it a chance to CSE the
5732 * LOAD_PAYLOAD instructions created to construct the payloads of
5733 * e.g. texturing messages in cases where it wasn't possible to CSE the
5734 * whole logical instruction.
5737 OPT(register_coalesce
);
5738 OPT(compute_to_mrf
);
5739 OPT(dead_code_eliminate
);
5740 OPT(remove_duplicate_mrf_writes
);
5741 OPT(opt_peephole_sel
);
5744 OPT(opt_redundant_discard_jumps
);
5746 if (OPT(lower_load_payload
)) {
5747 split_virtual_grfs();
5748 OPT(register_coalesce
);
5749 OPT(compute_to_mrf
);
5750 OPT(dead_code_eliminate
);
5753 OPT(opt_combine_constants
);
5754 OPT(lower_integer_multiplication
);
5756 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5757 OPT(opt_cmod_propagation
);
5759 OPT(opt_copy_propagate
);
5760 OPT(dead_code_eliminate
);
5763 lower_uniform_pull_constant_loads();
5769 * Three source instruction must have a GRF/MRF destination register.
5770 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5773 fs_visitor::fixup_3src_null_dest()
5775 bool progress
= false;
5777 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5778 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
5779 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5786 invalidate_live_intervals();
5790 fs_visitor::allocate_registers(bool allow_spilling
)
5792 bool allocated_without_spills
;
5794 static const enum instruction_scheduler_mode pre_modes
[] = {
5796 SCHEDULE_PRE_NON_LIFO
,
5800 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
5802 /* Try each scheduling heuristic to see if it can successfully register
5803 * allocate without spilling. They should be ordered by decreasing
5804 * performance but increasing likelihood of allocating.
5806 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5807 schedule_instructions(pre_modes
[i
]);
5810 assign_regs_trivial();
5811 allocated_without_spills
= true;
5813 allocated_without_spills
= assign_regs(false, spill_all
);
5815 if (allocated_without_spills
)
5819 if (!allocated_without_spills
) {
5820 if (!allow_spilling
)
5821 fail("Failure to register allocate and spilling is not allowed.");
5823 /* We assume that any spilling is worse than just dropping back to
5824 * SIMD8. There's probably actually some intermediate point where
5825 * SIMD16 with a couple of spills is still better.
5827 if (dispatch_width
> min_dispatch_width
) {
5828 fail("Failure to register allocate. Reduce number of "
5829 "live scalar values to avoid this.");
5831 compiler
->shader_perf_log(log_data
,
5832 "%s shader triggered register spilling. "
5833 "Try reducing the number of live scalar "
5834 "values to improve performance.\n",
5838 /* Since we're out of heuristics, just go spill registers until we
5839 * get an allocation.
5841 while (!assign_regs(true, spill_all
)) {
5847 /* This must come after all optimization and register allocation, since
5848 * it inserts dead code that happens to have side effects, and it does
5849 * so based on the actual physical registers in use.
5851 insert_gen4_send_dependency_workarounds();
5856 schedule_instructions(SCHEDULE_POST
);
5858 if (last_scratch
> 0) {
5859 MAYBE_UNUSED
unsigned max_scratch_size
= 2 * 1024 * 1024;
5861 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5863 if (stage
== MESA_SHADER_COMPUTE
) {
5864 if (devinfo
->is_haswell
) {
5865 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5866 * field documentation, Haswell supports a minimum of 2kB of
5867 * scratch space for compute shaders, unlike every other stage
5870 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
5871 } else if (devinfo
->gen
<= 7) {
5872 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5873 * field documentation, platforms prior to Haswell measure scratch
5874 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
5876 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
5877 max_scratch_size
= 12 * 1024;
5881 /* We currently only support up to 2MB of scratch space. If we
5882 * need to support more eventually, the documentation suggests
5883 * that we could allocate a larger buffer, and partition it out
5884 * ourselves. We'd just have to undo the hardware's address
5885 * calculation by subtracting (FFTID * Per Thread Scratch Space)
5886 * and then add FFTID * (Larger Per Thread Scratch Space).
5888 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
5889 * Thread Group Tracking > Local Memory/Scratch Space.
5891 assert(prog_data
->total_scratch
< max_scratch_size
);
5896 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5898 assert(stage
== MESA_SHADER_VERTEX
);
5902 if (shader_time_index
>= 0)
5903 emit_shader_time_begin();
5910 compute_clip_distance(clip_planes
);
5914 if (shader_time_index
>= 0)
5915 emit_shader_time_end();
5921 assign_curb_setup();
5922 assign_vs_urb_setup();
5924 fixup_3src_null_dest();
5925 allocate_registers(true);
5931 fs_visitor::run_tcs_single_patch()
5933 assert(stage
== MESA_SHADER_TESS_CTRL
);
5935 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
5937 /* r1-r4 contain the ICP handles. */
5938 payload
.num_regs
= 5;
5940 if (shader_time_index
>= 0)
5941 emit_shader_time_begin();
5943 /* Initialize gl_InvocationID */
5944 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
5945 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5946 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
5947 bld
.MOV(channels_ud
, channels_uw
);
5949 if (tcs_prog_data
->instances
== 1) {
5950 invocation_id
= channels_ud
;
5952 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5954 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
5955 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5956 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5957 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
5958 brw_imm_ud(INTEL_MASK(23, 17)));
5959 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
5961 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
5964 /* Fix the disptach mask */
5965 if (nir
->info
->tcs
.vertices_out
% 8) {
5966 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
5967 brw_imm_ud(nir
->info
->tcs
.vertices_out
), BRW_CONDITIONAL_L
);
5968 bld
.IF(BRW_PREDICATE_NORMAL
);
5973 if (nir
->info
->tcs
.vertices_out
% 8) {
5974 bld
.emit(BRW_OPCODE_ENDIF
);
5977 /* Emit EOT write; set TR DS Cache bit */
5979 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
5980 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
5981 fs_reg(brw_imm_ud(0)),
5983 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
5984 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
5986 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
5987 bld
.null_reg_ud(), payload
);
5991 if (shader_time_index
>= 0)
5992 emit_shader_time_end();
6001 assign_curb_setup();
6002 assign_tcs_single_patch_urb_setup();
6004 fixup_3src_null_dest();
6005 allocate_registers(true);
6011 fs_visitor::run_tes()
6013 assert(stage
== MESA_SHADER_TESS_EVAL
);
6015 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6016 payload
.num_regs
= 5;
6018 if (shader_time_index
>= 0)
6019 emit_shader_time_begin();
6028 if (shader_time_index
>= 0)
6029 emit_shader_time_end();
6035 assign_curb_setup();
6036 assign_tes_urb_setup();
6038 fixup_3src_null_dest();
6039 allocate_registers(true);
6045 fs_visitor::run_gs()
6047 assert(stage
== MESA_SHADER_GEOMETRY
);
6051 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6053 if (gs_compile
->control_data_header_size_bits
> 0) {
6054 /* Create a VGRF to store accumulated control data bits. */
6055 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6057 /* If we're outputting more than 32 control data bits, then EmitVertex()
6058 * will set control_data_bits to 0 after emitting the first vertex.
6059 * Otherwise, we need to initialize it to 0 here.
6061 if (gs_compile
->control_data_header_size_bits
<= 32) {
6062 const fs_builder abld
= bld
.annotate("initialize control data bits");
6063 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6067 if (shader_time_index
>= 0)
6068 emit_shader_time_begin();
6072 emit_gs_thread_end();
6074 if (shader_time_index
>= 0)
6075 emit_shader_time_end();
6084 assign_curb_setup();
6085 assign_gs_urb_setup();
6087 fixup_3src_null_dest();
6088 allocate_registers(true);
6094 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6096 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
6097 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6099 assert(stage
== MESA_SHADER_FRAGMENT
);
6101 if (devinfo
->gen
>= 6)
6102 setup_fs_payload_gen6();
6104 setup_fs_payload_gen4();
6108 } else if (do_rep_send
) {
6109 assert(dispatch_width
== 16);
6110 emit_repclear_shader();
6112 if (shader_time_index
>= 0)
6113 emit_shader_time_begin();
6115 calculate_urb_setup();
6116 if (nir
->info
->inputs_read
> 0 ||
6117 (nir
->info
->outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
6118 if (devinfo
->gen
< 6)
6119 emit_interpolation_setup_gen4();
6121 emit_interpolation_setup_gen6();
6124 /* We handle discards by keeping track of the still-live pixels in f0.1.
6125 * Initialize it with the dispatched pixels.
6127 if (wm_prog_data
->uses_kill
) {
6128 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
6129 discard_init
->flag_subreg
= 1;
6132 /* Generate FS IR for main(). (the visitor only descends into
6133 * functions called "main").
6140 if (wm_prog_data
->uses_kill
)
6141 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6143 if (wm_key
->alpha_test_func
)
6148 if (shader_time_index
>= 0)
6149 emit_shader_time_end();
6155 assign_curb_setup();
6158 fixup_3src_null_dest();
6159 allocate_registers(allow_spilling
);
6169 fs_visitor::run_cs()
6171 assert(stage
== MESA_SHADER_COMPUTE
);
6175 if (shader_time_index
>= 0)
6176 emit_shader_time_begin();
6178 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6179 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6180 const fs_builder abld
= bld
.exec_all().group(1, 0);
6181 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
6182 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6190 emit_cs_terminate();
6192 if (shader_time_index
>= 0)
6193 emit_shader_time_end();
6199 assign_curb_setup();
6201 fixup_3src_null_dest();
6202 allocate_registers(true);
6211 * Return a bitfield where bit n is set if barycentric interpolation mode n
6212 * (see enum brw_barycentric_mode) is needed by the fragment shader.
6214 * We examine the load_barycentric intrinsics rather than looking at input
6215 * variables so that we catch interpolateAtCentroid() messages too, which
6216 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
6219 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
6220 const nir_shader
*shader
)
6222 unsigned barycentric_interp_modes
= 0;
6224 nir_foreach_function(f
, shader
) {
6228 nir_foreach_block(block
, f
->impl
) {
6229 nir_foreach_instr(instr
, block
) {
6230 if (instr
->type
!= nir_instr_type_intrinsic
)
6233 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6234 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6237 /* Ignore WPOS; it doesn't require interpolation. */
6238 if (nir_intrinsic_base(intrin
) == VARYING_SLOT_POS
)
6241 intrin
= nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6242 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
6243 nir_intrinsic_interp_mode(intrin
);
6244 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
6245 enum brw_barycentric_mode bary
=
6246 brw_barycentric_mode(interp
, bary_op
);
6248 barycentric_interp_modes
|= 1 << bary
;
6250 if (devinfo
->needs_unlit_centroid_workaround
&&
6251 bary_op
== nir_intrinsic_load_barycentric_centroid
)
6252 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
6257 return barycentric_interp_modes
;
6261 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
6262 const nir_shader
*shader
)
6264 prog_data
->flat_inputs
= 0;
6266 nir_foreach_variable(var
, &shader
->inputs
) {
6267 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
6269 if (input_index
< 0)
6273 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6274 prog_data
->flat_inputs
|= (1 << input_index
);
6279 computed_depth_mode(const nir_shader
*shader
)
6281 if (shader
->info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6282 switch (shader
->info
->fs
.depth_layout
) {
6283 case FRAG_DEPTH_LAYOUT_NONE
:
6284 case FRAG_DEPTH_LAYOUT_ANY
:
6285 return BRW_PSCDEPTH_ON
;
6286 case FRAG_DEPTH_LAYOUT_GREATER
:
6287 return BRW_PSCDEPTH_ON_GE
;
6288 case FRAG_DEPTH_LAYOUT_LESS
:
6289 return BRW_PSCDEPTH_ON_LE
;
6290 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
6291 return BRW_PSCDEPTH_OFF
;
6294 return BRW_PSCDEPTH_OFF
;
6298 * Move load_interpolated_input with simple (payload-based) barycentric modes
6299 * to the top of the program so we don't emit multiple PLNs for the same input.
6301 * This works around CSE not being able to handle non-dominating cases
6307 * interpolate the same exact input
6310 * This should be replaced by global value numbering someday.
6313 move_interpolation_to_top(nir_shader
*nir
)
6315 nir_foreach_function(f
, nir
) {
6319 nir_block
*top
= nir_start_block(f
->impl
);
6320 exec_node
*cursor_node
= NULL
;
6322 nir_foreach_block(block
, f
->impl
) {
6326 nir_foreach_instr_safe(instr
, block
) {
6327 if (instr
->type
!= nir_instr_type_intrinsic
)
6330 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6331 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6333 nir_intrinsic_instr
*bary_intrinsic
=
6334 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6335 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
6337 /* Leave interpolateAtSample/Offset() where they are. */
6338 if (op
== nir_intrinsic_load_barycentric_at_sample
||
6339 op
== nir_intrinsic_load_barycentric_at_offset
)
6342 nir_instr
*move
[3] = {
6343 &bary_intrinsic
->instr
,
6344 intrin
->src
[1].ssa
->parent_instr
,
6348 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
6349 if (move
[i
]->block
!= top
) {
6350 move
[i
]->block
= top
;
6351 exec_node_remove(&move
[i
]->node
);
6353 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
6355 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
6357 cursor_node
= &move
[i
]->node
;
6362 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6363 ((unsigned) nir_metadata_block_index
|
6364 (unsigned) nir_metadata_dominance
));
6369 * Demote per-sample barycentric intrinsics to centroid.
6371 * Useful when rendering to a non-multisampled buffer.
6374 demote_sample_qualifiers(nir_shader
*nir
)
6376 nir_foreach_function(f
, nir
) {
6381 nir_builder_init(&b
, f
->impl
);
6383 nir_foreach_block(block
, f
->impl
) {
6384 nir_foreach_instr_safe(instr
, block
) {
6385 if (instr
->type
!= nir_instr_type_intrinsic
)
6388 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6389 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
6390 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
6393 b
.cursor
= nir_before_instr(instr
);
6394 nir_ssa_def
*centroid
=
6395 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
6396 nir_intrinsic_interp_mode(intrin
));
6397 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
6398 nir_src_for_ssa(centroid
));
6399 nir_instr_remove(instr
);
6403 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6404 ((unsigned) nir_metadata_block_index
|
6405 (unsigned) nir_metadata_dominance
));
6410 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
6412 const struct brw_wm_prog_key
*key
,
6413 struct brw_wm_prog_data
*prog_data
,
6414 const nir_shader
*src_shader
,
6415 struct gl_program
*prog
,
6416 int shader_time_index8
, int shader_time_index16
,
6417 bool allow_spilling
,
6419 unsigned *final_assembly_size
,
6422 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6423 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6425 brw_nir_lower_fs_inputs(shader
, compiler
->devinfo
, key
);
6426 brw_nir_lower_fs_outputs(shader
);
6427 if (!key
->multisample_fbo
)
6428 NIR_PASS_V(shader
, demote_sample_qualifiers
);
6429 NIR_PASS_V(shader
, move_interpolation_to_top
);
6430 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6432 /* key->alpha_test_func means simulating alpha testing via discards,
6433 * so the shader definitely kills pixels.
6435 prog_data
->uses_kill
= shader
->info
->fs
.uses_discard
||
6436 key
->alpha_test_func
;
6437 prog_data
->uses_omask
= key
->multisample_fbo
&&
6438 shader
->info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
6439 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
6440 prog_data
->computed_stencil
=
6441 shader
->info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
6443 prog_data
->persample_dispatch
=
6444 key
->multisample_fbo
&&
6445 (key
->persample_interp
||
6446 (shader
->info
->system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
6447 SYSTEM_BIT_SAMPLE_POS
)) ||
6448 shader
->info
->fs
.uses_sample_qualifier
||
6449 shader
->info
->outputs_read
);
6451 prog_data
->early_fragment_tests
= shader
->info
->fs
.early_fragment_tests
;
6453 prog_data
->barycentric_interp_modes
=
6454 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
6456 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
;
6457 uint8_t simd8_grf_start
= 0, simd16_grf_start
= 0;
6458 unsigned simd8_grf_used
= 0, simd16_grf_used
= 0;
6460 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
6461 &prog_data
->base
, prog
, shader
, 8,
6462 shader_time_index8
);
6463 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
6465 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
6468 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
6470 simd8_grf_start
= v8
.payload
.num_regs
;
6471 simd8_grf_used
= v8
.grf_used
;
6474 if (v8
.max_dispatch_width
>= 16 &&
6475 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
6476 /* Try a SIMD16 compile */
6477 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
6478 &prog_data
->base
, prog
, shader
, 16,
6479 shader_time_index16
);
6480 v16
.import_uniforms(&v8
);
6481 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
6482 compiler
->shader_perf_log(log_data
,
6483 "SIMD16 shader failed to compile: %s",
6486 simd16_cfg
= v16
.cfg
;
6487 simd16_grf_start
= v16
.payload
.num_regs
;
6488 simd16_grf_used
= v16
.grf_used
;
6492 /* When the caller requests a repclear shader, they want SIMD16-only */
6496 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
6497 * at the top to select the shader. We've never implemented that.
6498 * Instead, we just give them exactly one shader and we pick the widest one
6501 if (compiler
->devinfo
->gen
< 5 && simd16_cfg
)
6504 if (prog_data
->persample_dispatch
) {
6505 /* Starting with SandyBridge (where we first get MSAA), the different
6506 * pixel dispatch combinations are grouped into classifications A
6507 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
6508 * generations, the only configurations supporting persample dispatch
6509 * are are this in which only one dispatch width is enabled.
6511 * If computed depth is enabled, SNB only allows SIMD8 while IVB+
6512 * allow SIMD8 or SIMD16 so we choose SIMD16 if available.
6514 if (compiler
->devinfo
->gen
== 6 &&
6515 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
) {
6517 } else if (simd16_cfg
) {
6522 /* We have to compute the flat inputs after the visitor is finished running
6523 * because it relies on prog_data->urb_setup which is computed in
6524 * fs_visitor::calculate_urb_setup().
6526 brw_compute_flat_inputs(prog_data
, shader
);
6528 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
6529 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6530 MESA_SHADER_FRAGMENT
);
6532 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
6533 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
6534 shader
->info
->label
?
6535 shader
->info
->label
: "unnamed",
6536 shader
->info
->name
));
6540 prog_data
->dispatch_8
= true;
6541 g
.generate_code(simd8_cfg
, 8);
6542 prog_data
->base
.dispatch_grf_start_reg
= simd8_grf_start
;
6543 prog_data
->reg_blocks_0
= brw_register_blocks(simd8_grf_used
);
6546 prog_data
->dispatch_16
= true;
6547 prog_data
->prog_offset_2
= g
.generate_code(simd16_cfg
, 16);
6548 prog_data
->dispatch_grf_start_reg_2
= simd16_grf_start
;
6549 prog_data
->reg_blocks_2
= brw_register_blocks(simd16_grf_used
);
6551 } else if (simd16_cfg
) {
6552 prog_data
->dispatch_16
= true;
6553 g
.generate_code(simd16_cfg
, 16);
6554 prog_data
->base
.dispatch_grf_start_reg
= simd16_grf_start
;
6555 prog_data
->reg_blocks_0
= brw_register_blocks(simd16_grf_used
);
6558 return g
.get_assembly(final_assembly_size
);
6562 fs_visitor::emit_cs_work_group_id_setup()
6564 assert(stage
== MESA_SHADER_COMPUTE
);
6566 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6568 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
6569 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
6570 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
6572 bld
.MOV(*reg
, r0_1
);
6573 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
6574 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
6580 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
6582 block
->dwords
= dwords
;
6583 block
->regs
= DIV_ROUND_UP(dwords
, 8);
6584 block
->size
= block
->regs
* 32;
6588 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
6589 struct brw_cs_prog_data
*cs_prog_data
)
6591 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
6592 bool fill_thread_id
=
6593 cs_prog_data
->thread_local_id_index
>= 0 &&
6594 cs_prog_data
->thread_local_id_index
< (int)prog_data
->nr_params
;
6595 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
6597 /* The thread ID should be stored in the last param dword */
6598 assert(prog_data
->nr_params
> 0 || !fill_thread_id
);
6599 assert(!fill_thread_id
||
6600 cs_prog_data
->thread_local_id_index
==
6601 (int)prog_data
->nr_params
- 1);
6603 unsigned cross_thread_dwords
, per_thread_dwords
;
6604 if (!cross_thread_supported
) {
6605 cross_thread_dwords
= 0u;
6606 per_thread_dwords
= prog_data
->nr_params
;
6607 } else if (fill_thread_id
) {
6608 /* Fill all but the last register with cross-thread payload */
6609 cross_thread_dwords
= 8 * (cs_prog_data
->thread_local_id_index
/ 8);
6610 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
6611 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
6613 /* Fill all data using cross-thread payload */
6614 cross_thread_dwords
= prog_data
->nr_params
;
6615 per_thread_dwords
= 0u;
6618 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
6619 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
6621 unsigned total_dwords
=
6622 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
6623 cs_prog_data
->push
.cross_thread
.size
) / 4;
6624 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
6626 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
6627 cs_prog_data
->push
.per_thread
.size
== 0);
6628 assert(cs_prog_data
->push
.cross_thread
.dwords
+
6629 cs_prog_data
->push
.per_thread
.dwords
==
6630 prog_data
->nr_params
);
6634 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
6636 cs_prog_data
->simd_size
= size
;
6637 unsigned group_size
= cs_prog_data
->local_size
[0] *
6638 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
6639 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
6643 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
6645 const struct brw_cs_prog_key
*key
,
6646 struct brw_cs_prog_data
*prog_data
,
6647 const nir_shader
*src_shader
,
6648 int shader_time_index
,
6649 unsigned *final_assembly_size
,
6652 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6653 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6655 brw_nir_lower_cs_shared(shader
);
6656 prog_data
->base
.total_shared
+= shader
->num_shared
;
6658 /* Now that we cloned the nir_shader, we can update num_uniforms based on
6659 * the thread_local_id_index.
6661 assert(prog_data
->thread_local_id_index
>= 0);
6662 shader
->num_uniforms
=
6663 MAX2(shader
->num_uniforms
,
6664 (unsigned)4 * (prog_data
->thread_local_id_index
+ 1));
6666 brw_nir_lower_intrinsics(shader
, &prog_data
->base
);
6667 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6669 prog_data
->local_size
[0] = shader
->info
->cs
.local_size
[0];
6670 prog_data
->local_size
[1] = shader
->info
->cs
.local_size
[1];
6671 prog_data
->local_size
[2] = shader
->info
->cs
.local_size
[2];
6672 unsigned local_workgroup_size
=
6673 shader
->info
->cs
.local_size
[0] * shader
->info
->cs
.local_size
[1] *
6674 shader
->info
->cs
.local_size
[2];
6676 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
6677 unsigned simd_required
= DIV_ROUND_UP(local_workgroup_size
, max_cs_threads
);
6680 const char *fail_msg
= NULL
;
6682 /* Now the main event: Visit the shader IR and generate our CS IR for it.
6684 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6685 NULL
, /* Never used in core profile */
6686 shader
, 8, shader_time_index
);
6687 if (simd_required
<= 8) {
6689 fail_msg
= v8
.fail_msg
;
6692 cs_set_simd_size(prog_data
, 8);
6693 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6694 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
6698 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6699 NULL
, /* Never used in core profile */
6700 shader
, 16, shader_time_index
);
6701 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
6702 !fail_msg
&& v8
.max_dispatch_width
>= 16 &&
6703 simd_required
<= 16) {
6704 /* Try a SIMD16 compile */
6705 if (simd_required
<= 8)
6706 v16
.import_uniforms(&v8
);
6707 if (!v16
.run_cs()) {
6708 compiler
->shader_perf_log(log_data
,
6709 "SIMD16 shader failed to compile: %s",
6713 "Couldn't generate SIMD16 program and not "
6714 "enough threads for SIMD8";
6718 cs_set_simd_size(prog_data
, 16);
6719 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6720 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
6724 fs_visitor
v32(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6725 NULL
, /* Never used in core profile */
6726 shader
, 32, shader_time_index
);
6727 if (!fail_msg
&& v8
.max_dispatch_width
>= 32 &&
6728 (simd_required
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
6729 /* Try a SIMD32 compile */
6730 if (simd_required
<= 8)
6731 v32
.import_uniforms(&v8
);
6732 else if (simd_required
<= 16)
6733 v32
.import_uniforms(&v16
);
6735 if (!v32
.run_cs()) {
6736 compiler
->shader_perf_log(log_data
,
6737 "SIMD32 shader failed to compile: %s",
6741 "Couldn't generate SIMD32 program and not "
6742 "enough threads for SIMD16";
6746 cs_set_simd_size(prog_data
, 32);
6747 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6751 if (unlikely(cfg
== NULL
)) {
6754 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
6759 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
6760 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6761 MESA_SHADER_COMPUTE
);
6762 if (INTEL_DEBUG
& DEBUG_CS
) {
6763 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
6764 shader
->info
->label
? shader
->info
->label
:
6766 shader
->info
->name
);
6767 g
.enable_debug(name
);
6770 g
.generate_code(cfg
, prog_data
->simd_size
);
6772 return g
.get_assembly(final_assembly_size
);
6776 * Test the dispatch mask packing assumptions of
6777 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
6778 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
6779 * executed with an unexpected dispatch mask.
6782 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
6784 const gl_shader_stage stage
= bld
.shader
->stage
;
6786 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
6787 bld
.shader
->stage_prog_data
)) {
6788 const fs_builder ubld
= bld
.exec_all().group(1, 0);
6789 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
6790 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
6793 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
6794 ubld
.AND(tmp
, mask
, tmp
);
6796 /* This will loop forever if the dispatch mask doesn't have the expected
6797 * form '2^n-1', in which case tmp will be non-zero.
6799 bld
.emit(BRW_OPCODE_DO
);
6800 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
6801 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));