2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "brw_dead_control_flow.h"
47 #include "main/uniforms.h"
48 #include "brw_fs_live_variables.h"
49 #include "glsl/glsl_types.h"
50 #include "program/sampler.h"
55 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
56 const fs_reg
*src
, unsigned sources
)
58 memset(this, 0, sizeof(*this));
60 this->src
= new fs_reg
[MAX2(sources
, 3)];
61 for (unsigned i
= 0; i
< sources
; i
++)
62 this->src
[i
] = src
[i
];
64 this->opcode
= opcode
;
66 this->sources
= sources
;
67 this->exec_size
= exec_size
;
69 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
71 /* If exec_size == 0, try to guess it from the registers. Since all
72 * manner of things may use hardware registers, we first try to guess
73 * based on GRF registers. If this fails, we will go ahead and take the
74 * width from the destination register.
76 if (this->exec_size
== 0) {
77 if (dst
.file
== GRF
) {
78 this->exec_size
= dst
.width
;
80 for (unsigned i
= 0; i
< sources
; ++i
) {
81 if (src
[i
].file
!= GRF
&& src
[i
].file
!= ATTR
)
84 if (this->exec_size
<= 1)
85 this->exec_size
= src
[i
].width
;
86 assert(src
[i
].width
== 1 || src
[i
].width
== this->exec_size
);
90 if (this->exec_size
== 0 && dst
.file
!= BAD_FILE
)
91 this->exec_size
= dst
.width
;
93 assert(this->exec_size
!= 0);
95 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
97 /* This will be the case for almost all instructions. */
104 DIV_ROUND_UP(MAX2(dst
.width
* dst
.stride
, 1) * type_sz(dst
.type
), 32);
107 this->regs_written
= 0;
111 unreachable("Invalid destination register file");
113 unreachable("Invalid register file");
116 this->writes_accumulator
= false;
121 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
124 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
126 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
129 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
)
131 init(opcode
, 0, dst
, NULL
, 0);
134 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
137 const fs_reg src
[1] = { src0
};
138 init(opcode
, exec_size
, dst
, src
, 1);
141 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
)
143 const fs_reg src
[1] = { src0
};
144 init(opcode
, 0, dst
, src
, 1);
147 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
148 const fs_reg
&src0
, const fs_reg
&src1
)
150 const fs_reg src
[2] = { src0
, src1
};
151 init(opcode
, exec_size
, dst
, src
, 2);
154 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
157 const fs_reg src
[2] = { src0
, src1
};
158 init(opcode
, 0, dst
, src
, 2);
161 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
162 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
164 const fs_reg src
[3] = { src0
, src1
, src2
};
165 init(opcode
, exec_size
, dst
, src
, 3);
168 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
169 const fs_reg
&src1
, const fs_reg
&src2
)
171 const fs_reg src
[3] = { src0
, src1
, src2
};
172 init(opcode
, 0, dst
, src
, 3);
175 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
,
176 const fs_reg src
[], unsigned sources
)
178 init(opcode
, 0, dst
, src
, sources
);
181 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
182 const fs_reg src
[], unsigned sources
)
184 init(opcode
, exec_width
, dst
, src
, sources
);
187 fs_inst::fs_inst(const fs_inst
&that
)
189 memcpy(this, &that
, sizeof(that
));
191 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
193 for (unsigned i
= 0; i
< that
.sources
; i
++)
194 this->src
[i
] = that
.src
[i
];
203 fs_inst::resize_sources(uint8_t num_sources
)
205 if (this->sources
!= num_sources
) {
206 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
208 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
209 src
[i
] = this->src
[i
];
213 this->sources
= num_sources
;
218 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
220 const fs_reg
&surf_index
,
221 const fs_reg
&varying_offset
,
222 uint32_t const_offset
)
224 /* We have our constant surface use a pitch of 4 bytes, so our index can
225 * be any component of a vector, and then we load 4 contiguous
226 * components starting from that.
228 * We break down the const_offset to a portion added to the variable
229 * offset and a portion done using reg_offset, which means that if you
230 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
231 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
232 * CSE can later notice that those loads are all the same and eliminate
233 * the redundant ones.
235 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
236 bld
.ADD(vec4_offset
, varying_offset
, fs_reg(const_offset
& ~3));
239 if (devinfo
->gen
== 4 && dst
.width
== 8) {
240 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
241 * u, v, r) as parameters, or we can just use the SIMD16 message
242 * consisting of (header, u). We choose the second, at the cost of a
243 * longer return length.
249 if (devinfo
->gen
>= 7)
250 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
252 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
254 assert(dst
.width
% 8 == 0);
255 int regs_written
= 4 * (dst
.width
/ 8) * scale
;
256 fs_reg vec4_result
= fs_reg(GRF
, alloc
.allocate(regs_written
),
257 dst
.type
, dst
.width
);
258 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
259 inst
->regs_written
= regs_written
;
261 if (devinfo
->gen
< 7) {
263 inst
->header_size
= 1;
264 if (devinfo
->gen
== 4)
267 inst
->mlen
= 1 + dispatch_width
/ 8;
270 bld
.MOV(dst
, offset(vec4_result
, (const_offset
& 3) * scale
));
274 * A helper for MOV generation for fixing up broken hardware SEND dependency
278 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
280 /* The caller always wants uncompressed to emit the minimal extra
281 * dependencies, and to avoid having to deal with aligning its regs to 2.
283 const fs_builder ubld
= bld
.annotate("send dependency resolve")
286 ubld
.MOV(ubld
.null_reg_f(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
290 fs_inst::equals(fs_inst
*inst
) const
292 return (opcode
== inst
->opcode
&&
293 dst
.equals(inst
->dst
) &&
294 src
[0].equals(inst
->src
[0]) &&
295 src
[1].equals(inst
->src
[1]) &&
296 src
[2].equals(inst
->src
[2]) &&
297 saturate
== inst
->saturate
&&
298 predicate
== inst
->predicate
&&
299 conditional_mod
== inst
->conditional_mod
&&
300 mlen
== inst
->mlen
&&
301 base_mrf
== inst
->base_mrf
&&
302 target
== inst
->target
&&
304 header_size
== inst
->header_size
&&
305 shadow_compare
== inst
->shadow_compare
&&
306 exec_size
== inst
->exec_size
&&
307 offset
== inst
->offset
);
311 fs_inst::overwrites_reg(const fs_reg
®
) const
313 return reg
.in_range(dst
, regs_written
);
317 fs_inst::is_send_from_grf() const
320 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
321 case SHADER_OPCODE_SHADER_TIME_ADD
:
322 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
323 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
324 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
325 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
326 case SHADER_OPCODE_UNTYPED_ATOMIC
:
327 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
328 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
329 case SHADER_OPCODE_TYPED_ATOMIC
:
330 case SHADER_OPCODE_TYPED_SURFACE_READ
:
331 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
332 case SHADER_OPCODE_URB_WRITE_SIMD8
:
334 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
335 return src
[1].file
== GRF
;
336 case FS_OPCODE_FB_WRITE
:
337 return src
[0].file
== GRF
;
340 return src
[0].file
== GRF
;
347 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
349 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
352 fs_reg reg
= this->src
[0];
353 if (reg
.file
!= GRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
356 if (grf_alloc
.sizes
[reg
.reg
] != this->regs_written
)
359 for (int i
= 0; i
< this->sources
; i
++) {
360 reg
.type
= this->src
[i
].type
;
361 reg
.width
= this->src
[i
].width
;
362 if (!this->src
[i
].equals(reg
))
364 reg
= ::offset(reg
, 1);
371 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
373 if (devinfo
->gen
== 6 && is_math())
376 if (is_send_from_grf())
379 if (!backend_instruction::can_do_source_mods())
386 fs_inst::has_side_effects() const
388 return this->eot
|| backend_instruction::has_side_effects();
394 memset(this, 0, sizeof(*this));
398 /** Generic unset register constructor. */
402 this->file
= BAD_FILE
;
405 /** Immediate value constructor. */
406 fs_reg::fs_reg(float f
)
410 this->type
= BRW_REGISTER_TYPE_F
;
411 this->fixed_hw_reg
.dw1
.f
= f
;
415 /** Immediate value constructor. */
416 fs_reg::fs_reg(int32_t i
)
420 this->type
= BRW_REGISTER_TYPE_D
;
421 this->fixed_hw_reg
.dw1
.d
= i
;
425 /** Immediate value constructor. */
426 fs_reg::fs_reg(uint32_t u
)
430 this->type
= BRW_REGISTER_TYPE_UD
;
431 this->fixed_hw_reg
.dw1
.ud
= u
;
435 /** Vector float immediate value constructor. */
436 fs_reg::fs_reg(uint8_t vf
[4])
440 this->type
= BRW_REGISTER_TYPE_VF
;
441 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
444 /** Vector float immediate value constructor. */
445 fs_reg::fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
449 this->type
= BRW_REGISTER_TYPE_VF
;
450 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
456 /** Fixed brw_reg. */
457 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
461 this->fixed_hw_reg
= fixed_hw_reg
;
462 this->type
= fixed_hw_reg
.type
;
463 this->width
= 1 << fixed_hw_reg
.width
;
467 fs_reg::equals(const fs_reg
&r
) const
469 return (file
== r
.file
&&
471 reg_offset
== r
.reg_offset
&&
472 subreg_offset
== r
.subreg_offset
&&
474 negate
== r
.negate
&&
476 !reladdr
&& !r
.reladdr
&&
477 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
, sizeof(fixed_hw_reg
)) == 0 &&
483 fs_reg::set_smear(unsigned subreg
)
485 assert(file
!= HW_REG
&& file
!= IMM
);
486 subreg_offset
= subreg
* type_sz(type
);
492 fs_reg::is_contiguous() const
498 fs_visitor::type_size(const struct glsl_type
*type
)
500 unsigned int size
, i
;
502 switch (type
->base_type
) {
505 case GLSL_TYPE_FLOAT
:
507 return type
->components();
508 case GLSL_TYPE_ARRAY
:
509 return type_size(type
->fields
.array
) * type
->length
;
510 case GLSL_TYPE_STRUCT
:
512 for (i
= 0; i
< type
->length
; i
++) {
513 size
+= type_size(type
->fields
.structure
[i
].type
);
516 case GLSL_TYPE_SAMPLER
:
517 /* Samplers take up no register space, since they're baked in at
521 case GLSL_TYPE_ATOMIC_UINT
:
523 case GLSL_TYPE_IMAGE
:
525 case GLSL_TYPE_ERROR
:
526 case GLSL_TYPE_INTERFACE
:
527 case GLSL_TYPE_DOUBLE
:
528 unreachable("not reached");
535 * Create a MOV to read the timestamp register.
537 * The caller is responsible for emitting the MOV. The return value is
538 * the destination of the MOV, with extra parameters set.
541 fs_visitor::get_timestamp(const fs_builder
&bld
)
543 assert(devinfo
->gen
>= 7);
545 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
548 BRW_REGISTER_TYPE_UD
));
550 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
, 4);
552 /* We want to read the 3 fields we care about even if it's not enabled in
555 bld
.exec_all().MOV(dst
, ts
);
557 /* The caller wants the low 32 bits of the timestamp. Since it's running
558 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
559 * which is plenty of time for our purposes. It is identical across the
560 * EUs, but since it's tracking GPU core speed it will increment at a
561 * varying rate as render P-states change.
563 * The caller could also check if render P-states have changed (or anything
564 * else that might disrupt timing) by setting smear to 2 and checking if
565 * that field is != 0.
573 fs_visitor::emit_shader_time_begin()
575 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
579 fs_visitor::emit_shader_time_end()
581 enum shader_time_shader_type type
, written_type
, reset_type
;
583 case MESA_SHADER_VERTEX
:
585 written_type
= ST_VS_WRITTEN
;
586 reset_type
= ST_VS_RESET
;
588 case MESA_SHADER_GEOMETRY
:
590 written_type
= ST_GS_WRITTEN
;
591 reset_type
= ST_GS_RESET
;
593 case MESA_SHADER_FRAGMENT
:
594 if (dispatch_width
== 8) {
596 written_type
= ST_FS8_WRITTEN
;
597 reset_type
= ST_FS8_RESET
;
599 assert(dispatch_width
== 16);
601 written_type
= ST_FS16_WRITTEN
;
602 reset_type
= ST_FS16_RESET
;
605 case MESA_SHADER_COMPUTE
:
607 written_type
= ST_CS_WRITTEN
;
608 reset_type
= ST_CS_RESET
;
611 unreachable("fs_visitor::emit_shader_time_end missing code");
614 /* Insert our code just before the final SEND with EOT. */
615 exec_node
*end
= this->instructions
.get_tail();
616 assert(end
&& ((fs_inst
*) end
)->eot
);
617 const fs_builder ibld
= bld
.annotate("shader time end")
618 .exec_all().at(NULL
, end
);
620 fs_reg shader_end_time
= get_timestamp(ibld
);
622 /* Check that there weren't any timestamp reset events (assuming these
623 * were the only two timestamp reads that happened).
625 fs_reg reset
= shader_end_time
;
627 set_condmod(BRW_CONDITIONAL_Z
,
628 ibld
.AND(ibld
.null_reg_ud(), reset
, fs_reg(1u)));
629 ibld
.IF(BRW_PREDICATE_NORMAL
);
631 fs_reg start
= shader_start_time
;
633 fs_reg diff
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
, 1);
635 ibld
.ADD(diff
, start
, shader_end_time
);
637 /* If there were no instructions between the two timestamp gets, the diff
638 * is 2 cycles. Remove that overhead, so I can forget about that when
639 * trying to determine the time taken for single instructions.
641 ibld
.ADD(diff
, diff
, fs_reg(-2u));
642 SHADER_TIME_ADD(ibld
, type
, diff
);
643 SHADER_TIME_ADD(ibld
, written_type
, fs_reg(1u));
644 ibld
.emit(BRW_OPCODE_ELSE
);
645 SHADER_TIME_ADD(ibld
, reset_type
, fs_reg(1u));
646 ibld
.emit(BRW_OPCODE_ENDIF
);
650 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
651 enum shader_time_shader_type type
, fs_reg value
)
653 int shader_time_index
=
654 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
655 fs_reg offset
= fs_reg(shader_time_index
* SHADER_TIME_STRIDE
);
658 if (dispatch_width
== 8)
659 payload
= vgrf(glsl_type::uvec2_type
);
661 payload
= vgrf(glsl_type::uint_type
);
663 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
667 fs_visitor::vfail(const char *format
, va_list va
)
676 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
677 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
679 this->fail_msg
= msg
;
682 fprintf(stderr
, "%s", msg
);
687 fs_visitor::fail(const char *format
, ...)
691 va_start(va
, format
);
697 * Mark this program as impossible to compile in SIMD16 mode.
699 * During the SIMD8 compile (which happens first), we can detect and flag
700 * things that are unsupported in SIMD16 mode, so the compiler can skip
701 * the SIMD16 compile altogether.
703 * During a SIMD16 compile (if one happens anyway), this just calls fail().
706 fs_visitor::no16(const char *format
, ...)
710 va_start(va
, format
);
712 if (dispatch_width
== 16) {
715 simd16_unsupported
= true;
717 if (brw
->perf_debug
) {
719 ralloc_vasprintf_append(&no16_msg
, format
, va
);
721 no16_msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
729 * Returns true if the instruction has a flag that means it won't
730 * update an entire destination register.
732 * For example, dead code elimination and live variable analysis want to know
733 * when a write to a variable screens off any preceding values that were in
737 fs_inst::is_partial_write() const
739 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
740 (this->dst
.width
* type_sz(this->dst
.type
)) < 32 ||
741 !this->dst
.is_contiguous());
745 fs_inst::regs_read(int arg
) const
747 if (is_tex() && arg
== 0 && src
[0].file
== GRF
) {
749 } else if (opcode
== FS_OPCODE_FB_WRITE
&& arg
== 0) {
751 } else if (opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
&& arg
== 0) {
753 } else if (opcode
== SHADER_OPCODE_UNTYPED_ATOMIC
&& arg
== 0) {
755 } else if (opcode
== SHADER_OPCODE_UNTYPED_SURFACE_READ
&& arg
== 0) {
757 } else if (opcode
== SHADER_OPCODE_UNTYPED_SURFACE_WRITE
&& arg
== 0) {
759 } else if (opcode
== SHADER_OPCODE_TYPED_ATOMIC
&& arg
== 0) {
761 } else if (opcode
== SHADER_OPCODE_TYPED_SURFACE_READ
&& arg
== 0) {
763 } else if (opcode
== SHADER_OPCODE_TYPED_SURFACE_WRITE
&& arg
== 0) {
765 } else if (opcode
== FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
&& arg
== 0) {
767 } else if (opcode
== FS_OPCODE_LINTERP
&& arg
== 0) {
768 return exec_size
/ 4;
771 switch (src
[arg
].file
) {
778 if (src
[arg
].stride
== 0) {
781 int size
= src
[arg
].width
* src
[arg
].stride
* type_sz(src
[arg
].type
);
782 return (size
+ 31) / 32;
785 unreachable("MRF registers are not allowed as sources");
787 unreachable("Invalid register file");
792 fs_inst::reads_flag() const
798 fs_inst::writes_flag() const
800 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
801 opcode
!= BRW_OPCODE_IF
&&
802 opcode
!= BRW_OPCODE_WHILE
)) ||
803 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
807 * Returns how many MRFs an FS opcode will write over.
809 * Note that this is not the 0 or 1 implied writes in an actual gen
810 * instruction -- the FS opcodes often generate MOVs in addition.
813 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
818 if (inst
->base_mrf
== -1)
821 switch (inst
->opcode
) {
822 case SHADER_OPCODE_RCP
:
823 case SHADER_OPCODE_RSQ
:
824 case SHADER_OPCODE_SQRT
:
825 case SHADER_OPCODE_EXP2
:
826 case SHADER_OPCODE_LOG2
:
827 case SHADER_OPCODE_SIN
:
828 case SHADER_OPCODE_COS
:
829 return 1 * dispatch_width
/ 8;
830 case SHADER_OPCODE_POW
:
831 case SHADER_OPCODE_INT_QUOTIENT
:
832 case SHADER_OPCODE_INT_REMAINDER
:
833 return 2 * dispatch_width
/ 8;
834 case SHADER_OPCODE_TEX
:
836 case SHADER_OPCODE_TXD
:
837 case SHADER_OPCODE_TXF
:
838 case SHADER_OPCODE_TXF_CMS
:
839 case SHADER_OPCODE_TXF_MCS
:
840 case SHADER_OPCODE_TG4
:
841 case SHADER_OPCODE_TG4_OFFSET
:
842 case SHADER_OPCODE_TXL
:
843 case SHADER_OPCODE_TXS
:
844 case SHADER_OPCODE_LOD
:
846 case FS_OPCODE_FB_WRITE
:
848 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
849 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
851 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
853 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
855 case SHADER_OPCODE_UNTYPED_ATOMIC
:
856 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
857 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
858 case SHADER_OPCODE_TYPED_ATOMIC
:
859 case SHADER_OPCODE_TYPED_SURFACE_READ
:
860 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
861 case SHADER_OPCODE_URB_WRITE_SIMD8
:
862 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
863 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
864 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
865 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
868 unreachable("not reached");
873 fs_visitor::vgrf(const glsl_type
*const type
)
875 int reg_width
= dispatch_width
/ 8;
876 return fs_reg(GRF
, alloc
.allocate(type_size(type
) * reg_width
),
877 brw_type_for_base_type(type
), dispatch_width
);
880 /** Fixed HW reg constructor. */
881 fs_reg::fs_reg(enum register_file file
, int reg
)
886 this->type
= BRW_REGISTER_TYPE_F
;
897 /** Fixed HW reg constructor. */
898 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
)
914 /** Fixed HW reg constructor. */
915 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
,
925 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
926 * This brings in those uniform definitions
929 fs_visitor::import_uniforms(fs_visitor
*v
)
931 this->push_constant_loc
= v
->push_constant_loc
;
932 this->pull_constant_loc
= v
->pull_constant_loc
;
933 this->uniforms
= v
->uniforms
;
934 this->param_size
= v
->param_size
;
938 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
939 bool origin_upper_left
)
941 assert(stage
== MESA_SHADER_FRAGMENT
);
942 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
943 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
945 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
948 if (pixel_center_integer
) {
949 bld
.MOV(wpos
, this->pixel_x
);
951 bld
.ADD(wpos
, this->pixel_x
, fs_reg(0.5f
));
953 wpos
= offset(wpos
, 1);
956 if (!flip
&& pixel_center_integer
) {
957 bld
.MOV(wpos
, this->pixel_y
);
959 fs_reg pixel_y
= this->pixel_y
;
960 float offset
= (pixel_center_integer
? 0.0 : 0.5);
963 pixel_y
.negate
= true;
964 offset
+= key
->drawable_height
- 1.0;
967 bld
.ADD(wpos
, pixel_y
, fs_reg(offset
));
969 wpos
= offset(wpos
, 1);
972 if (devinfo
->gen
>= 6) {
973 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
975 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
976 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
977 interp_reg(VARYING_SLOT_POS
, 2));
979 wpos
= offset(wpos
, 1);
981 /* gl_FragCoord.w: Already set up in emit_interpolation */
982 bld
.MOV(wpos
, this->wpos_w
);
988 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
989 glsl_interp_qualifier interpolation_mode
,
990 bool is_centroid
, bool is_sample
)
992 brw_wm_barycentric_interp_mode barycoord_mode
;
993 if (devinfo
->gen
>= 6) {
995 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
996 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
998 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
999 } else if (is_sample
) {
1000 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1001 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1003 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1005 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1006 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1008 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1011 /* On Ironlake and below, there is only one interpolation mode.
1012 * Centroid interpolation doesn't mean anything on this hardware --
1013 * there is no multisampling.
1015 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1017 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1018 this->delta_xy
[barycoord_mode
], interp
);
1022 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
1023 const glsl_type
*type
,
1024 glsl_interp_qualifier interpolation_mode
,
1025 int location
, bool mod_centroid
,
1028 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
1030 assert(stage
== MESA_SHADER_FRAGMENT
);
1031 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1032 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1034 unsigned int array_elements
;
1036 if (type
->is_array()) {
1037 array_elements
= type
->length
;
1038 if (array_elements
== 0) {
1039 fail("dereferenced array '%s' has length 0\n", name
);
1041 type
= type
->fields
.array
;
1046 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1048 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1049 if (key
->flat_shade
&& is_gl_Color
) {
1050 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1052 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1056 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1057 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1058 if (prog_data
->urb_setup
[location
] == -1) {
1059 /* If there's no incoming setup data for this slot, don't
1060 * emit interpolation for it.
1062 attr
= offset(attr
, type
->vector_elements
);
1067 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1068 /* Constant interpolation (flat shading) case. The SF has
1069 * handed us defined values in only the constant offset
1070 * field of the setup reg.
1072 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1073 struct brw_reg interp
= interp_reg(location
, k
);
1074 interp
= suboffset(interp
, 3);
1075 interp
.type
= attr
.type
;
1076 bld
.emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1077 attr
= offset(attr
, 1);
1080 /* Smooth/noperspective interpolation case. */
1081 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1082 struct brw_reg interp
= interp_reg(location
, k
);
1083 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1084 /* Get the pixel/sample mask into f0 so that we know
1085 * which pixels are lit. Then, for each channel that is
1086 * unlit, replace the centroid data with non-centroid
1089 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1092 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1094 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1095 inst
->predicate_inverse
= true;
1096 if (devinfo
->has_pln
)
1097 inst
->no_dd_clear
= true;
1099 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1100 mod_centroid
&& !key
->persample_shading
,
1101 mod_sample
|| key
->persample_shading
);
1102 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1103 inst
->predicate_inverse
= false;
1104 if (devinfo
->has_pln
)
1105 inst
->no_dd_check
= true;
1108 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1109 mod_centroid
&& !key
->persample_shading
,
1110 mod_sample
|| key
->persample_shading
);
1112 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1113 bld
.MUL(attr
, attr
, this->pixel_w
);
1115 attr
= offset(attr
, 1);
1125 fs_visitor::emit_frontfacing_interpolation()
1127 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1129 if (devinfo
->gen
>= 6) {
1130 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1131 * a boolean result from this (~0/true or 0/false).
1133 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1134 * this task in only one instruction:
1135 * - a negation source modifier will flip the bit; and
1136 * - a W -> D type conversion will sign extend the bit into the high
1137 * word of the destination.
1139 * An ASR 15 fills the low word of the destination.
1141 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1144 bld
.ASR(*reg
, g0
, fs_reg(15));
1146 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1147 * a boolean result from this (1/true or 0/false).
1149 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1150 * the negation source modifier to flip it. Unfortunately the SHR
1151 * instruction only operates on UD (or D with an abs source modifier)
1152 * sources without negation.
1154 * Instead, use ASR (which will give ~0/true or 0/false).
1156 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1159 bld
.ASR(*reg
, g1_6
, fs_reg(31));
1166 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1168 assert(stage
== MESA_SHADER_FRAGMENT
);
1169 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1170 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1172 if (key
->compute_pos_offset
) {
1173 /* Convert int_sample_pos to floating point */
1174 bld
.MOV(dst
, int_sample_pos
);
1175 /* Scale to the range [0, 1] */
1176 bld
.MUL(dst
, dst
, fs_reg(1 / 16.0f
));
1179 /* From ARB_sample_shading specification:
1180 * "When rendering to a non-multisample buffer, or if multisample
1181 * rasterization is disabled, gl_SamplePosition will always be
1184 bld
.MOV(dst
, fs_reg(0.5f
));
1189 fs_visitor::emit_samplepos_setup()
1191 assert(devinfo
->gen
>= 6);
1193 const fs_builder abld
= bld
.annotate("compute sample position");
1194 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1196 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1197 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1199 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1200 * mode will be enabled.
1202 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1203 * R31.1:0 Position Offset X/Y for Slot[3:0]
1204 * R31.3:2 Position Offset X/Y for Slot[7:4]
1207 * The X, Y sample positions come in as bytes in thread payload. So, read
1208 * the positions using vstride=16, width=8, hstride=2.
1210 struct brw_reg sample_pos_reg
=
1211 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1212 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1214 if (dispatch_width
== 8) {
1215 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1217 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1218 abld
.half(1).MOV(half(int_sample_x
, 1),
1219 fs_reg(suboffset(sample_pos_reg
, 16)));
1221 /* Compute gl_SamplePosition.x */
1222 compute_sample_position(pos
, int_sample_x
);
1223 pos
= offset(pos
, 1);
1224 if (dispatch_width
== 8) {
1225 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1227 abld
.half(0).MOV(half(int_sample_y
, 0),
1228 fs_reg(suboffset(sample_pos_reg
, 1)));
1229 abld
.half(1).MOV(half(int_sample_y
, 1),
1230 fs_reg(suboffset(sample_pos_reg
, 17)));
1232 /* Compute gl_SamplePosition.y */
1233 compute_sample_position(pos
, int_sample_y
);
1238 fs_visitor::emit_sampleid_setup()
1240 assert(stage
== MESA_SHADER_FRAGMENT
);
1241 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1242 assert(devinfo
->gen
>= 6);
1244 const fs_builder abld
= bld
.annotate("compute sample id");
1245 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1247 if (key
->compute_sample_id
) {
1248 fs_reg t1
= vgrf(glsl_type::int_type
);
1249 fs_reg t2
= vgrf(glsl_type::int_type
);
1250 t2
.type
= BRW_REGISTER_TYPE_UW
;
1252 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1253 * 8x multisampling, subspan 0 will represent sample N (where N
1254 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1255 * 7. We can find the value of N by looking at R0.0 bits 7:6
1256 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1257 * (since samples are always delivered in pairs). That is, we
1258 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1259 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1260 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1261 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1262 * populating a temporary variable with the sequence (0, 1, 2, 3),
1263 * and then reading from it using vstride=1, width=4, hstride=0.
1264 * These computations hold good for 4x multisampling as well.
1266 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1267 * the first four slots are sample 0 of subspan 0; the next four
1268 * are sample 1 of subspan 0; the third group is sample 0 of
1269 * subspan 1, and finally sample 1 of subspan 1.
1272 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1274 abld
.exec_all().SHR(t1
, t1
, fs_reg(5));
1276 /* This works for both SIMD8 and SIMD16 */
1278 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1280 /* This special instruction takes care of setting vstride=1,
1281 * width=4, hstride=0 of t2 during an ADD instruction.
1283 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1285 /* As per GL_ARB_sample_shading specification:
1286 * "When rendering to a non-multisample buffer, or if multisample
1287 * rasterization is disabled, gl_SampleID will always be zero."
1289 abld
.MOV(*reg
, fs_reg(0));
1296 fs_visitor::resolve_source_modifiers(fs_reg
*src
)
1298 if (!src
->abs
&& !src
->negate
)
1301 fs_reg temp
= bld
.vgrf(src
->type
);
1302 bld
.MOV(temp
, *src
);
1307 fs_visitor::emit_discard_jump()
1309 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1311 /* For performance, after a discard, jump to the end of the
1312 * shader if all relevant channels have been discarded.
1314 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1315 discard_jump
->flag_subreg
= 1;
1317 discard_jump
->predicate
= (dispatch_width
== 8)
1318 ? BRW_PREDICATE_ALIGN1_ANY8H
1319 : BRW_PREDICATE_ALIGN1_ANY16H
;
1320 discard_jump
->predicate_inverse
= true;
1324 fs_visitor::assign_curb_setup()
1326 if (dispatch_width
== 8) {
1327 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1329 if (stage
== MESA_SHADER_FRAGMENT
) {
1330 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1331 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1332 } else if (stage
== MESA_SHADER_COMPUTE
) {
1333 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1334 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1336 unreachable("Unsupported shader type!");
1340 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1342 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1343 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1344 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1345 if (inst
->src
[i
].file
== UNIFORM
) {
1346 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1348 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1349 constant_nr
= push_constant_loc
[uniform_nr
];
1351 /* Section 5.11 of the OpenGL 4.1 spec says:
1352 * "Out-of-bounds reads return undefined values, which include
1353 * values from other variables of the active program or zero."
1354 * Just return the first push constant.
1359 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1363 inst
->src
[i
].file
= HW_REG
;
1364 inst
->src
[i
].fixed_hw_reg
= byte_offset(
1365 retype(brw_reg
, inst
->src
[i
].type
),
1366 inst
->src
[i
].subreg_offset
);
1373 fs_visitor::calculate_urb_setup()
1375 assert(stage
== MESA_SHADER_FRAGMENT
);
1376 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1377 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1379 memset(prog_data
->urb_setup
, -1,
1380 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1383 /* Figure out where each of the incoming setup attributes lands. */
1384 if (devinfo
->gen
>= 6) {
1385 if (_mesa_bitcount_64(prog
->InputsRead
&
1386 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1387 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1388 * first 16 varying inputs, so we can put them wherever we want.
1389 * Just put them in order.
1391 * This is useful because it means that (a) inputs not used by the
1392 * fragment shader won't take up valuable register space, and (b) we
1393 * won't have to recompile the fragment shader if it gets paired with
1394 * a different vertex (or geometry) shader.
1396 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1397 if (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1398 BITFIELD64_BIT(i
)) {
1399 prog_data
->urb_setup
[i
] = urb_next
++;
1403 /* We have enough input varyings that the SF/SBE pipeline stage can't
1404 * arbitrarily rearrange them to suit our whim; we have to put them
1405 * in an order that matches the output of the previous pipeline stage
1406 * (geometry or vertex shader).
1408 struct brw_vue_map prev_stage_vue_map
;
1409 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1410 key
->input_slots_valid
);
1411 int first_slot
= 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1412 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1413 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1415 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1416 /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
1419 if (varying
!= BRW_VARYING_SLOT_COUNT
&&
1420 (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1421 BITFIELD64_BIT(varying
))) {
1422 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1425 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1428 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1429 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1430 /* Point size is packed into the header, not as a general attribute */
1431 if (i
== VARYING_SLOT_PSIZ
)
1434 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1435 /* The back color slot is skipped when the front color is
1436 * also written to. In addition, some slots can be
1437 * written in the vertex shader and not read in the
1438 * fragment shader. So the register number must always be
1439 * incremented, mapped or not.
1441 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1442 prog_data
->urb_setup
[i
] = urb_next
;
1448 * It's a FS only attribute, and we did interpolation for this attribute
1449 * in SF thread. So, count it here, too.
1451 * See compile_sf_prog() for more info.
1453 if (prog
->InputsRead
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1454 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1457 prog_data
->num_varying_inputs
= urb_next
;
1461 fs_visitor::assign_urb_setup()
1463 assert(stage
== MESA_SHADER_FRAGMENT
);
1464 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1466 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1468 /* Offset all the urb_setup[] index by the actual position of the
1469 * setup regs, now that the location of the constants has been chosen.
1471 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1472 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1473 assert(inst
->src
[1].file
== HW_REG
);
1474 inst
->src
[1].fixed_hw_reg
.nr
+= urb_start
;
1477 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1478 assert(inst
->src
[0].file
== HW_REG
);
1479 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1483 /* Each attribute is 4 setup channels, each of which is half a reg. */
1484 this->first_non_payload_grf
=
1485 urb_start
+ prog_data
->num_varying_inputs
* 2;
1489 fs_visitor::assign_vs_urb_setup()
1491 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1492 int grf
, count
, slot
, channel
, attr
;
1494 assert(stage
== MESA_SHADER_VERTEX
);
1495 count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1496 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1499 /* Each attribute is 4 regs. */
1500 this->first_non_payload_grf
=
1501 payload
.num_regs
+ prog_data
->curb_read_length
+ count
* 4;
1503 unsigned vue_entries
=
1504 MAX2(count
, vs_prog_data
->base
.vue_map
.num_slots
);
1506 vs_prog_data
->base
.urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1507 vs_prog_data
->base
.urb_read_length
= (count
+ 1) / 2;
1509 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1511 /* Rewrite all ATTR file references to the hw grf that they land in. */
1512 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1513 for (int i
= 0; i
< inst
->sources
; i
++) {
1514 if (inst
->src
[i
].file
== ATTR
) {
1516 if (inst
->src
[i
].reg
== VERT_ATTRIB_MAX
) {
1519 /* Attributes come in in a contiguous block, ordered by their
1520 * gl_vert_attrib value. That means we can compute the slot
1521 * number for an attribute by masking out the enabled
1522 * attributes before it and counting the bits.
1524 attr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
/ 4;
1525 slot
= _mesa_bitcount_64(vs_prog_data
->inputs_read
&
1526 BITFIELD64_MASK(attr
));
1529 channel
= inst
->src
[i
].reg_offset
& 3;
1531 grf
= payload
.num_regs
+
1532 prog_data
->curb_read_length
+
1535 inst
->src
[i
].file
= HW_REG
;
1536 inst
->src
[i
].fixed_hw_reg
=
1537 retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
);
1544 * Split large virtual GRFs into separate components if we can.
1546 * This is mostly duplicated with what brw_fs_vector_splitting does,
1547 * but that's really conservative because it's afraid of doing
1548 * splitting that doesn't result in real progress after the rest of
1549 * the optimization phases, which would cause infinite looping in
1550 * optimization. We can do it once here, safely. This also has the
1551 * opportunity to split interpolated values, or maybe even uniforms,
1552 * which we don't have at the IR level.
1554 * We want to split, because virtual GRFs are what we register
1555 * allocate and spill (due to contiguousness requirements for some
1556 * instructions), and they're what we naturally generate in the
1557 * codegen process, but most virtual GRFs don't actually need to be
1558 * contiguous sets of GRFs. If we split, we'll end up with reduced
1559 * live intervals and better dead code elimination and coalescing.
1562 fs_visitor::split_virtual_grfs()
1564 int num_vars
= this->alloc
.count
;
1566 /* Count the total number of registers */
1568 int vgrf_to_reg
[num_vars
];
1569 for (int i
= 0; i
< num_vars
; i
++) {
1570 vgrf_to_reg
[i
] = reg_count
;
1571 reg_count
+= alloc
.sizes
[i
];
1574 /* An array of "split points". For each register slot, this indicates
1575 * if this slot can be separated from the previous slot. Every time an
1576 * instruction uses multiple elements of a register (as a source or
1577 * destination), we mark the used slots as inseparable. Then we go
1578 * through and split the registers into the smallest pieces we can.
1580 bool split_points
[reg_count
];
1581 memset(split_points
, 0, sizeof(split_points
));
1583 /* Mark all used registers as fully splittable */
1584 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1585 if (inst
->dst
.file
== GRF
) {
1586 int reg
= vgrf_to_reg
[inst
->dst
.reg
];
1587 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.reg
]; j
++)
1588 split_points
[reg
+ j
] = true;
1591 for (int i
= 0; i
< inst
->sources
; i
++) {
1592 if (inst
->src
[i
].file
== GRF
) {
1593 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
];
1594 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].reg
]; j
++)
1595 split_points
[reg
+ j
] = true;
1600 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1601 if (inst
->dst
.file
== GRF
) {
1602 int reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1603 for (int j
= 1; j
< inst
->regs_written
; j
++)
1604 split_points
[reg
+ j
] = false;
1606 for (int i
= 0; i
< inst
->sources
; i
++) {
1607 if (inst
->src
[i
].file
== GRF
) {
1608 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1609 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1610 split_points
[reg
+ j
] = false;
1615 int new_virtual_grf
[reg_count
];
1616 int new_reg_offset
[reg_count
];
1619 for (int i
= 0; i
< num_vars
; i
++) {
1620 /* The first one should always be 0 as a quick sanity check. */
1621 assert(split_points
[reg
] == false);
1624 new_reg_offset
[reg
] = 0;
1629 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1630 /* If this is a split point, reset the offset to 0 and allocate a
1631 * new virtual GRF for the previous offset many registers
1633 if (split_points
[reg
]) {
1634 assert(offset
<= MAX_VGRF_SIZE
);
1635 int grf
= alloc
.allocate(offset
);
1636 for (int k
= reg
- offset
; k
< reg
; k
++)
1637 new_virtual_grf
[k
] = grf
;
1640 new_reg_offset
[reg
] = offset
;
1645 /* The last one gets the original register number */
1646 assert(offset
<= MAX_VGRF_SIZE
);
1647 alloc
.sizes
[i
] = offset
;
1648 for (int k
= reg
- offset
; k
< reg
; k
++)
1649 new_virtual_grf
[k
] = i
;
1651 assert(reg
== reg_count
);
1653 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1654 if (inst
->dst
.file
== GRF
) {
1655 reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1656 inst
->dst
.reg
= new_virtual_grf
[reg
];
1657 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1658 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1660 for (int i
= 0; i
< inst
->sources
; i
++) {
1661 if (inst
->src
[i
].file
== GRF
) {
1662 reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1663 inst
->src
[i
].reg
= new_virtual_grf
[reg
];
1664 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1665 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1669 invalidate_live_intervals();
1673 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1675 * During code generation, we create tons of temporary variables, many of
1676 * which get immediately killed and are never used again. Yet, in later
1677 * optimization and analysis passes, such as compute_live_intervals, we need
1678 * to loop over all the virtual GRFs. Compacting them can save a lot of
1682 fs_visitor::compact_virtual_grfs()
1684 bool progress
= false;
1685 int remap_table
[this->alloc
.count
];
1686 memset(remap_table
, -1, sizeof(remap_table
));
1688 /* Mark which virtual GRFs are used. */
1689 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1690 if (inst
->dst
.file
== GRF
)
1691 remap_table
[inst
->dst
.reg
] = 0;
1693 for (int i
= 0; i
< inst
->sources
; i
++) {
1694 if (inst
->src
[i
].file
== GRF
)
1695 remap_table
[inst
->src
[i
].reg
] = 0;
1699 /* Compact the GRF arrays. */
1701 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1702 if (remap_table
[i
] == -1) {
1703 /* We just found an unused register. This means that we are
1704 * actually going to compact something.
1708 remap_table
[i
] = new_index
;
1709 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1710 invalidate_live_intervals();
1715 this->alloc
.count
= new_index
;
1717 /* Patch all the instructions to use the newly renumbered registers */
1718 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1719 if (inst
->dst
.file
== GRF
)
1720 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
1722 for (int i
= 0; i
< inst
->sources
; i
++) {
1723 if (inst
->src
[i
].file
== GRF
)
1724 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
1728 /* Patch all the references to delta_xy, since they're used in register
1729 * allocation. If they're unused, switch them to BAD_FILE so we don't
1730 * think some random VGRF is delta_xy.
1732 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1733 if (delta_xy
[i
].file
== GRF
) {
1734 if (remap_table
[delta_xy
[i
].reg
] != -1) {
1735 delta_xy
[i
].reg
= remap_table
[delta_xy
[i
].reg
];
1737 delta_xy
[i
].file
= BAD_FILE
;
1746 * Implements array access of uniforms by inserting a
1747 * PULL_CONSTANT_LOAD instruction.
1749 * Unlike temporary GRF array access (where we don't support it due to
1750 * the difficulty of doing relative addressing on instruction
1751 * destinations), we could potentially do array access of uniforms
1752 * that were loaded in GRF space as push constants. In real-world
1753 * usage we've seen, though, the arrays being used are always larger
1754 * than we could load as push constants, so just always move all
1755 * uniform array access out to a pull constant buffer.
1758 fs_visitor::move_uniform_array_access_to_pull_constants()
1760 if (dispatch_width
!= 8)
1763 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1764 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1766 /* Walk through and find array access of uniforms. Put a copy of that
1767 * uniform in the pull constant buffer.
1769 * Note that we don't move constant-indexed accesses to arrays. No
1770 * testing has been done of the performance impact of this choice.
1772 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1773 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1774 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
1777 int uniform
= inst
->src
[i
].reg
;
1779 /* If this array isn't already present in the pull constant buffer,
1782 if (pull_constant_loc
[uniform
] == -1) {
1783 const gl_constant_value
**values
= &stage_prog_data
->param
[uniform
];
1785 assert(param_size
[uniform
]);
1787 for (int j
= 0; j
< param_size
[uniform
]; j
++) {
1788 pull_constant_loc
[uniform
+ j
] = stage_prog_data
->nr_pull_params
;
1790 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
1799 * Assign UNIFORM file registers to either push constants or pull constants.
1801 * We allow a fragment shader to have more than the specified minimum
1802 * maximum number of fragment shader uniform components (64). If
1803 * there are too many of these, they'd fill up all of register space.
1804 * So, this will push some of them out to the pull constant buffer and
1805 * update the program to load them.
1808 fs_visitor::assign_constant_locations()
1810 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1811 if (dispatch_width
!= 8)
1814 /* Find which UNIFORM registers are still in use. */
1815 bool is_live
[uniforms
];
1816 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1820 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1821 for (int i
= 0; i
< inst
->sources
; i
++) {
1822 if (inst
->src
[i
].file
!= UNIFORM
)
1825 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1826 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1827 is_live
[constant_nr
] = true;
1831 /* Only allow 16 registers (128 uniform components) as push constants.
1833 * Just demote the end of the list. We could probably do better
1834 * here, demoting things that are rarely used in the program first.
1836 * If changing this value, note the limitation about total_regs in
1839 unsigned int max_push_components
= 16 * 8;
1840 unsigned int num_push_constants
= 0;
1842 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1844 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1845 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1846 /* This UNIFORM register is either dead, or has already been demoted
1847 * to a pull const. Mark it as no longer living in the param[] array.
1849 push_constant_loc
[i
] = -1;
1853 if (num_push_constants
< max_push_components
) {
1854 /* Retain as a push constant. Record the location in the params[]
1857 push_constant_loc
[i
] = num_push_constants
++;
1859 /* Demote to a pull constant. */
1860 push_constant_loc
[i
] = -1;
1862 int pull_index
= stage_prog_data
->nr_pull_params
++;
1863 stage_prog_data
->pull_param
[pull_index
] = stage_prog_data
->param
[i
];
1864 pull_constant_loc
[i
] = pull_index
;
1868 stage_prog_data
->nr_params
= num_push_constants
;
1870 /* Up until now, the param[] array has been indexed by reg + reg_offset
1871 * of UNIFORM registers. Condense it to only contain the uniforms we
1872 * chose to upload as push constants.
1874 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1875 int remapped
= push_constant_loc
[i
];
1880 assert(remapped
<= (int)i
);
1881 stage_prog_data
->param
[remapped
] = stage_prog_data
->param
[i
];
1886 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
1887 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
1890 fs_visitor::demote_pull_constants()
1892 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1893 for (int i
= 0; i
< inst
->sources
; i
++) {
1894 if (inst
->src
[i
].file
!= UNIFORM
)
1898 unsigned location
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1899 if (location
>= uniforms
) /* Out of bounds access */
1902 pull_index
= pull_constant_loc
[location
];
1904 if (pull_index
== -1)
1907 /* Set up the annotation tracking for new generated instructions. */
1908 const fs_builder ibld
= bld
.annotate(inst
->annotation
, inst
->ir
)
1910 fs_reg
surf_index(stage_prog_data
->binding_table
.pull_constants_start
);
1911 fs_reg dst
= vgrf(glsl_type::float_type
);
1913 /* Generate a pull load into dst. */
1914 if (inst
->src
[i
].reladdr
) {
1915 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
1917 *inst
->src
[i
].reladdr
,
1919 inst
->src
[i
].reladdr
= NULL
;
1921 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
1922 ibld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
1923 dst
, surf_index
, offset
);
1924 inst
->src
[i
].set_smear(pull_index
& 3);
1927 /* Rewrite the instruction to use the temporary VGRF. */
1928 inst
->src
[i
].file
= GRF
;
1929 inst
->src
[i
].reg
= dst
.reg
;
1930 inst
->src
[i
].reg_offset
= 0;
1931 inst
->src
[i
].width
= dispatch_width
;
1934 invalidate_live_intervals();
1938 fs_visitor::opt_algebraic()
1940 bool progress
= false;
1942 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1943 switch (inst
->opcode
) {
1944 case BRW_OPCODE_MOV
:
1945 if (inst
->src
[0].file
!= IMM
)
1948 if (inst
->saturate
) {
1949 if (inst
->dst
.type
!= inst
->src
[0].type
)
1950 assert(!"unimplemented: saturate mixed types");
1952 if (brw_saturate_immediate(inst
->dst
.type
,
1953 &inst
->src
[0].fixed_hw_reg
)) {
1954 inst
->saturate
= false;
1960 case BRW_OPCODE_MUL
:
1961 if (inst
->src
[1].file
!= IMM
)
1965 if (inst
->src
[1].is_one()) {
1966 inst
->opcode
= BRW_OPCODE_MOV
;
1967 inst
->src
[1] = reg_undef
;
1973 if (inst
->src
[1].is_negative_one()) {
1974 inst
->opcode
= BRW_OPCODE_MOV
;
1975 inst
->src
[0].negate
= !inst
->src
[0].negate
;
1976 inst
->src
[1] = reg_undef
;
1982 if (inst
->src
[1].is_zero()) {
1983 inst
->opcode
= BRW_OPCODE_MOV
;
1984 inst
->src
[0] = inst
->src
[1];
1985 inst
->src
[1] = reg_undef
;
1990 if (inst
->src
[0].file
== IMM
) {
1991 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
1992 inst
->opcode
= BRW_OPCODE_MOV
;
1993 inst
->src
[0].fixed_hw_reg
.dw1
.f
*= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
1994 inst
->src
[1] = reg_undef
;
1999 case BRW_OPCODE_ADD
:
2000 if (inst
->src
[1].file
!= IMM
)
2004 if (inst
->src
[1].is_zero()) {
2005 inst
->opcode
= BRW_OPCODE_MOV
;
2006 inst
->src
[1] = reg_undef
;
2011 if (inst
->src
[0].file
== IMM
) {
2012 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2013 inst
->opcode
= BRW_OPCODE_MOV
;
2014 inst
->src
[0].fixed_hw_reg
.dw1
.f
+= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
2015 inst
->src
[1] = reg_undef
;
2021 if (inst
->src
[0].equals(inst
->src
[1])) {
2022 inst
->opcode
= BRW_OPCODE_MOV
;
2023 inst
->src
[1] = reg_undef
;
2028 case BRW_OPCODE_LRP
:
2029 if (inst
->src
[1].equals(inst
->src
[2])) {
2030 inst
->opcode
= BRW_OPCODE_MOV
;
2031 inst
->src
[0] = inst
->src
[1];
2032 inst
->src
[1] = reg_undef
;
2033 inst
->src
[2] = reg_undef
;
2038 case BRW_OPCODE_CMP
:
2039 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2041 inst
->src
[0].negate
&&
2042 inst
->src
[1].is_zero()) {
2043 inst
->src
[0].abs
= false;
2044 inst
->src
[0].negate
= false;
2045 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2050 case BRW_OPCODE_SEL
:
2051 if (inst
->src
[0].equals(inst
->src
[1])) {
2052 inst
->opcode
= BRW_OPCODE_MOV
;
2053 inst
->src
[1] = reg_undef
;
2054 inst
->predicate
= BRW_PREDICATE_NONE
;
2055 inst
->predicate_inverse
= false;
2057 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2058 switch (inst
->conditional_mod
) {
2059 case BRW_CONDITIONAL_LE
:
2060 case BRW_CONDITIONAL_L
:
2061 switch (inst
->src
[1].type
) {
2062 case BRW_REGISTER_TYPE_F
:
2063 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
>= 1.0f
) {
2064 inst
->opcode
= BRW_OPCODE_MOV
;
2065 inst
->src
[1] = reg_undef
;
2066 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2074 case BRW_CONDITIONAL_GE
:
2075 case BRW_CONDITIONAL_G
:
2076 switch (inst
->src
[1].type
) {
2077 case BRW_REGISTER_TYPE_F
:
2078 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
<= 0.0f
) {
2079 inst
->opcode
= BRW_OPCODE_MOV
;
2080 inst
->src
[1] = reg_undef
;
2081 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2093 case BRW_OPCODE_MAD
:
2094 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2095 inst
->opcode
= BRW_OPCODE_MOV
;
2096 inst
->src
[1] = reg_undef
;
2097 inst
->src
[2] = reg_undef
;
2099 } else if (inst
->src
[0].is_zero()) {
2100 inst
->opcode
= BRW_OPCODE_MUL
;
2101 inst
->src
[0] = inst
->src
[2];
2102 inst
->src
[2] = reg_undef
;
2104 } else if (inst
->src
[1].is_one()) {
2105 inst
->opcode
= BRW_OPCODE_ADD
;
2106 inst
->src
[1] = inst
->src
[2];
2107 inst
->src
[2] = reg_undef
;
2109 } else if (inst
->src
[2].is_one()) {
2110 inst
->opcode
= BRW_OPCODE_ADD
;
2111 inst
->src
[2] = reg_undef
;
2113 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2114 inst
->opcode
= BRW_OPCODE_ADD
;
2115 inst
->src
[1].fixed_hw_reg
.dw1
.f
*= inst
->src
[2].fixed_hw_reg
.dw1
.f
;
2116 inst
->src
[2] = reg_undef
;
2120 case SHADER_OPCODE_RCP
: {
2121 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2122 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2123 if (inst
->src
[0].equals(prev
->dst
)) {
2124 inst
->opcode
= SHADER_OPCODE_RSQ
;
2125 inst
->src
[0] = prev
->src
[0];
2131 case SHADER_OPCODE_BROADCAST
:
2132 if (is_uniform(inst
->src
[0])) {
2133 inst
->opcode
= BRW_OPCODE_MOV
;
2135 inst
->force_writemask_all
= true;
2137 } else if (inst
->src
[1].file
== IMM
) {
2138 inst
->opcode
= BRW_OPCODE_MOV
;
2139 inst
->src
[0] = component(inst
->src
[0],
2140 inst
->src
[1].fixed_hw_reg
.dw1
.ud
);
2142 inst
->force_writemask_all
= true;
2151 /* Swap if src[0] is immediate. */
2152 if (progress
&& inst
->is_commutative()) {
2153 if (inst
->src
[0].file
== IMM
) {
2154 fs_reg tmp
= inst
->src
[1];
2155 inst
->src
[1] = inst
->src
[0];
2164 * Optimize sample messages that have constant zero values for the trailing
2165 * texture coordinates. We can just reduce the message length for these
2166 * instructions instead of reserving a register for it. Trailing parameters
2167 * that aren't sent default to zero anyway. This will cause the dead code
2168 * eliminator to remove the MOV instruction that would otherwise be emitted to
2169 * set up the zero value.
2172 fs_visitor::opt_zero_samples()
2174 /* Gen4 infers the texturing opcode based on the message length so we can't
2177 if (devinfo
->gen
< 5)
2180 bool progress
= false;
2182 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2183 if (!inst
->is_tex())
2186 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2188 if (load_payload
->is_head_sentinel() ||
2189 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2192 /* We don't want to remove the message header or the first parameter.
2193 * Removing the first parameter is not allowed, see the Haswell PRM
2194 * volume 7, page 149:
2196 * "Parameter 0 is required except for the sampleinfo message, which
2197 * has no parameter 0"
2199 while (inst
->mlen
> inst
->header_size
+ dispatch_width
/ 8 &&
2200 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2201 (dispatch_width
/ 8) +
2202 inst
->header_size
- 1].is_zero()) {
2203 inst
->mlen
-= dispatch_width
/ 8;
2209 invalidate_live_intervals();
2215 * Optimize sample messages which are followed by the final RT write.
2217 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2218 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2219 * final texturing results copied to the framebuffer write payload and modify
2220 * them to write to the framebuffer directly.
2223 fs_visitor::opt_sampler_eot()
2225 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2227 if (stage
!= MESA_SHADER_FRAGMENT
)
2230 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2233 /* FINISHME: It should be possible to implement this optimization when there
2234 * are multiple drawbuffers.
2236 if (key
->nr_color_regions
!= 1)
2239 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2240 fs_inst
*fb_write
= (fs_inst
*) cfg
->blocks
[cfg
->num_blocks
- 1]->end();
2241 assert(fb_write
->eot
);
2242 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2244 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2246 /* There wasn't one; nothing to do. */
2247 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2250 /* This optimisation doesn't seem to work for textureGather for some
2251 * reason. I can't find any documentation or known workarounds to indicate
2252 * that this is expected, but considering that it is probably pretty
2253 * unlikely that a shader would directly write out the results from
2254 * textureGather we might as well just disable it.
2256 if (tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2257 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2260 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2261 * It's very likely to be the previous instruction.
2263 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2264 if (load_payload
->is_head_sentinel() ||
2265 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2268 assert(!tex_inst
->eot
); /* We can't get here twice */
2269 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2271 tex_inst
->offset
|= fb_write
->target
<< 24;
2272 tex_inst
->eot
= true;
2273 tex_inst
->dst
= bld
.null_reg_ud();
2274 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2276 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2277 * to create a new LOAD_PAYLOAD command with the same sources and a space
2278 * saved for the header. Using a new destination register not only makes sure
2279 * we have enough space, but it will make sure the dead code eliminator kills
2280 * the instruction that this will replace.
2282 if (tex_inst
->header_size
!= 0)
2285 fs_reg send_header
= bld
.vgrf(BRW_REGISTER_TYPE_F
,
2286 load_payload
->sources
+ 1);
2287 fs_reg
*new_sources
=
2288 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2290 new_sources
[0] = fs_reg();
2291 for (int i
= 0; i
< load_payload
->sources
; i
++)
2292 new_sources
[i
+1] = load_payload
->src
[i
];
2294 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2295 * requires a lot of information about the sources to appropriately figure
2296 * out the number of registers needed to be used. Given this stage in our
2297 * optimization, we may not have the appropriate GRFs required by
2298 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2299 * manually emit the instruction.
2301 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2302 load_payload
->exec_size
,
2305 load_payload
->sources
+ 1);
2307 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2308 new_load_payload
->header_size
= 1;
2310 tex_inst
->header_size
= 1;
2311 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2312 tex_inst
->src
[0] = send_header
;
2318 fs_visitor::opt_register_renaming()
2320 bool progress
= false;
2323 int remap
[alloc
.count
];
2324 memset(remap
, -1, sizeof(int) * alloc
.count
);
2326 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2327 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2329 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2330 inst
->opcode
== BRW_OPCODE_WHILE
) {
2334 /* Rewrite instruction sources. */
2335 for (int i
= 0; i
< inst
->sources
; i
++) {
2336 if (inst
->src
[i
].file
== GRF
&&
2337 remap
[inst
->src
[i
].reg
] != -1 &&
2338 remap
[inst
->src
[i
].reg
] != inst
->src
[i
].reg
) {
2339 inst
->src
[i
].reg
= remap
[inst
->src
[i
].reg
];
2344 const int dst
= inst
->dst
.reg
;
2347 inst
->dst
.file
== GRF
&&
2348 alloc
.sizes
[inst
->dst
.reg
] == inst
->dst
.width
/ 8 &&
2349 !inst
->is_partial_write()) {
2350 if (remap
[dst
] == -1) {
2353 remap
[dst
] = alloc
.allocate(inst
->dst
.width
/ 8);
2354 inst
->dst
.reg
= remap
[dst
];
2357 } else if (inst
->dst
.file
== GRF
&&
2359 remap
[dst
] != dst
) {
2360 inst
->dst
.reg
= remap
[dst
];
2366 invalidate_live_intervals();
2368 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2369 if (delta_xy
[i
].file
== GRF
&& remap
[delta_xy
[i
].reg
] != -1) {
2370 delta_xy
[i
].reg
= remap
[delta_xy
[i
].reg
];
2379 * Remove redundant or useless discard jumps.
2381 * For example, we can eliminate jumps in the following sequence:
2383 * discard-jump (redundant with the next jump)
2384 * discard-jump (useless; jumps to the next instruction)
2388 fs_visitor::opt_redundant_discard_jumps()
2390 bool progress
= false;
2392 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2394 fs_inst
*placeholder_halt
= NULL
;
2395 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2396 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2397 placeholder_halt
= inst
;
2402 if (!placeholder_halt
)
2405 /* Delete any HALTs immediately before the placeholder halt. */
2406 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2407 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2408 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2409 prev
->remove(last_bblock
);
2414 invalidate_live_intervals();
2420 fs_visitor::compute_to_mrf()
2422 bool progress
= false;
2425 /* No MRFs on Gen >= 7. */
2426 if (devinfo
->gen
>= 7)
2429 calculate_live_intervals();
2431 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2435 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2436 inst
->is_partial_write() ||
2437 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2438 inst
->dst
.type
!= inst
->src
[0].type
||
2439 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2440 !inst
->src
[0].is_contiguous() ||
2441 inst
->src
[0].subreg_offset
)
2444 /* Work out which hardware MRF registers are written by this
2447 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2449 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2450 mrf_high
= mrf_low
+ 4;
2451 } else if (inst
->exec_size
== 16) {
2452 mrf_high
= mrf_low
+ 1;
2457 /* Can't compute-to-MRF this GRF if someone else was going to
2460 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2463 /* Found a move of a GRF to a MRF. Let's see if we can go
2464 * rewrite the thing that made this GRF to write into the MRF.
2466 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2467 if (scan_inst
->dst
.file
== GRF
&&
2468 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2469 /* Found the last thing to write our reg we want to turn
2470 * into a compute-to-MRF.
2473 /* If this one instruction didn't populate all the
2474 * channels, bail. We might be able to rewrite everything
2475 * that writes that reg, but it would require smarter
2476 * tracking to delay the rewriting until complete success.
2478 if (scan_inst
->is_partial_write())
2481 /* Things returning more than one register would need us to
2482 * understand coalescing out more than one MOV at a time.
2484 if (scan_inst
->regs_written
> scan_inst
->dst
.width
/ 8)
2487 /* SEND instructions can't have MRF as a destination. */
2488 if (scan_inst
->mlen
)
2491 if (devinfo
->gen
== 6) {
2492 /* gen6 math instructions must have the destination be
2493 * GRF, so no compute-to-MRF for them.
2495 if (scan_inst
->is_math()) {
2500 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2501 /* Found the creator of our MRF's source value. */
2502 scan_inst
->dst
.file
= MRF
;
2503 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2504 scan_inst
->saturate
|= inst
->saturate
;
2505 inst
->remove(block
);
2511 /* We don't handle control flow here. Most computation of
2512 * values that end up in MRFs are shortly before the MRF
2515 if (block
->start() == scan_inst
)
2518 /* You can't read from an MRF, so if someone else reads our
2519 * MRF's source GRF that we wanted to rewrite, that stops us.
2521 bool interfered
= false;
2522 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2523 if (scan_inst
->src
[i
].file
== GRF
&&
2524 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2525 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2532 if (scan_inst
->dst
.file
== MRF
) {
2533 /* If somebody else writes our MRF here, we can't
2534 * compute-to-MRF before that.
2536 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2539 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2540 scan_mrf_high
= scan_mrf_low
+ 4;
2541 } else if (scan_inst
->exec_size
== 16) {
2542 scan_mrf_high
= scan_mrf_low
+ 1;
2544 scan_mrf_high
= scan_mrf_low
;
2547 if (mrf_low
== scan_mrf_low
||
2548 mrf_low
== scan_mrf_high
||
2549 mrf_high
== scan_mrf_low
||
2550 mrf_high
== scan_mrf_high
) {
2555 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2556 /* Found a SEND instruction, which means that there are
2557 * live values in MRFs from base_mrf to base_mrf +
2558 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2561 if (mrf_low
>= scan_inst
->base_mrf
&&
2562 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2565 if (mrf_high
>= scan_inst
->base_mrf
&&
2566 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2574 invalidate_live_intervals();
2580 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2581 * flow. We could probably do better here with some form of divergence
2585 fs_visitor::eliminate_find_live_channel()
2587 bool progress
= false;
2590 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2591 switch (inst
->opcode
) {
2597 case BRW_OPCODE_ENDIF
:
2598 case BRW_OPCODE_WHILE
:
2602 case FS_OPCODE_DISCARD_JUMP
:
2603 /* This can potentially make control flow non-uniform until the end
2608 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2610 inst
->opcode
= BRW_OPCODE_MOV
;
2611 inst
->src
[0] = fs_reg(0);
2613 inst
->force_writemask_all
= true;
2627 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2628 * instructions to FS_OPCODE_REP_FB_WRITE.
2631 fs_visitor::emit_repclear_shader()
2633 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2635 int color_mrf
= base_mrf
+ 2;
2637 fs_inst
*mov
= bld
.exec_all().MOV(vec4(brw_message_reg(color_mrf
)),
2638 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2641 if (key
->nr_color_regions
== 1) {
2642 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2643 write
->saturate
= key
->clamp_fragment_color
;
2644 write
->base_mrf
= color_mrf
;
2646 write
->header_size
= 0;
2649 assume(key
->nr_color_regions
> 0);
2650 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2651 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2652 write
->saturate
= key
->clamp_fragment_color
;
2653 write
->base_mrf
= base_mrf
;
2655 write
->header_size
= 2;
2663 assign_constant_locations();
2664 assign_curb_setup();
2666 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2667 assert(mov
->src
[0].file
== HW_REG
);
2668 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].fixed_hw_reg
.nr
, 0);
2672 * Walks through basic blocks, looking for repeated MRF writes and
2673 * removing the later ones.
2676 fs_visitor::remove_duplicate_mrf_writes()
2678 fs_inst
*last_mrf_move
[16];
2679 bool progress
= false;
2681 /* Need to update the MRF tracking for compressed instructions. */
2682 if (dispatch_width
== 16)
2685 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2687 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2688 if (inst
->is_control_flow()) {
2689 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2692 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2693 inst
->dst
.file
== MRF
) {
2694 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2695 if (prev_inst
&& inst
->equals(prev_inst
)) {
2696 inst
->remove(block
);
2702 /* Clear out the last-write records for MRFs that were overwritten. */
2703 if (inst
->dst
.file
== MRF
) {
2704 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2707 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2708 /* Found a SEND instruction, which will include two or fewer
2709 * implied MRF writes. We could do better here.
2711 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2712 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2716 /* Clear out any MRF move records whose sources got overwritten. */
2717 if (inst
->dst
.file
== GRF
) {
2718 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2719 if (last_mrf_move
[i
] &&
2720 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2721 last_mrf_move
[i
] = NULL
;
2726 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2727 inst
->dst
.file
== MRF
&&
2728 inst
->src
[0].file
== GRF
&&
2729 !inst
->is_partial_write()) {
2730 last_mrf_move
[inst
->dst
.reg
] = inst
;
2735 invalidate_live_intervals();
2741 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2743 /* Clear the flag for registers that actually got read (as expected). */
2744 for (int i
= 0; i
< inst
->sources
; i
++) {
2746 if (inst
->src
[i
].file
== GRF
) {
2747 grf
= inst
->src
[i
].reg
;
2748 } else if (inst
->src
[i
].file
== HW_REG
&&
2749 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
2750 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
2755 if (grf
>= first_grf
&&
2756 grf
< first_grf
+ grf_len
) {
2757 deps
[grf
- first_grf
] = false;
2758 if (inst
->exec_size
== 16)
2759 deps
[grf
- first_grf
+ 1] = false;
2765 * Implements this workaround for the original 965:
2767 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2768 * check for post destination dependencies on this instruction, software
2769 * must ensure that there is no destination hazard for the case of ‘write
2770 * followed by a posted write’ shown in the following example.
2773 * 2. send r3.xy <rest of send instruction>
2776 * Due to no post-destination dependency check on the ‘send’, the above
2777 * code sequence could have two instructions (1 and 2) in flight at the
2778 * same time that both consider ‘r3’ as the target of their final writes.
2781 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2784 int write_len
= inst
->regs_written
;
2785 int first_write_grf
= inst
->dst
.reg
;
2786 bool needs_dep
[BRW_MAX_MRF
];
2787 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2789 memset(needs_dep
, false, sizeof(needs_dep
));
2790 memset(needs_dep
, true, write_len
);
2792 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2794 /* Walk backwards looking for writes to registers we're writing which
2795 * aren't read since being written. If we hit the start of the program,
2796 * we assume that there are no outstanding dependencies on entry to the
2799 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2800 /* If we hit control flow, assume that there *are* outstanding
2801 * dependencies, and force their cleanup before our instruction.
2803 if (block
->start() == scan_inst
) {
2804 for (int i
= 0; i
< write_len
; i
++) {
2806 DEP_RESOLVE_MOV(bld
.at(block
, inst
), first_write_grf
+ i
);
2811 /* We insert our reads as late as possible on the assumption that any
2812 * instruction but a MOV that might have left us an outstanding
2813 * dependency has more latency than a MOV.
2815 if (scan_inst
->dst
.file
== GRF
) {
2816 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2817 int reg
= scan_inst
->dst
.reg
+ i
;
2819 if (reg
>= first_write_grf
&&
2820 reg
< first_write_grf
+ write_len
&&
2821 needs_dep
[reg
- first_write_grf
]) {
2822 DEP_RESOLVE_MOV(bld
.at(block
, inst
), reg
);
2823 needs_dep
[reg
- first_write_grf
] = false;
2824 if (scan_inst
->exec_size
== 16)
2825 needs_dep
[reg
- first_write_grf
+ 1] = false;
2830 /* Clear the flag for registers that actually got read (as expected). */
2831 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2833 /* Continue the loop only if we haven't resolved all the dependencies */
2835 for (i
= 0; i
< write_len
; i
++) {
2845 * Implements this workaround for the original 965:
2847 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2848 * used as a destination register until after it has been sourced by an
2849 * instruction with a different destination register.
2852 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
2854 int write_len
= inst
->regs_written
;
2855 int first_write_grf
= inst
->dst
.reg
;
2856 bool needs_dep
[BRW_MAX_MRF
];
2857 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2859 memset(needs_dep
, false, sizeof(needs_dep
));
2860 memset(needs_dep
, true, write_len
);
2861 /* Walk forwards looking for writes to registers we're writing which aren't
2862 * read before being written.
2864 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2865 /* If we hit control flow, force resolve all remaining dependencies. */
2866 if (block
->end() == scan_inst
) {
2867 for (int i
= 0; i
< write_len
; i
++) {
2869 DEP_RESOLVE_MOV(bld
.at(block
, scan_inst
), first_write_grf
+ i
);
2874 /* Clear the flag for registers that actually got read (as expected). */
2875 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2877 /* We insert our reads as late as possible since they're reading the
2878 * result of a SEND, which has massive latency.
2880 if (scan_inst
->dst
.file
== GRF
&&
2881 scan_inst
->dst
.reg
>= first_write_grf
&&
2882 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
2883 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
2884 DEP_RESOLVE_MOV(bld
.at(block
, scan_inst
), scan_inst
->dst
.reg
);
2885 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
2888 /* Continue the loop only if we haven't resolved all the dependencies */
2890 for (i
= 0; i
< write_len
; i
++) {
2900 fs_visitor::insert_gen4_send_dependency_workarounds()
2902 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
2905 bool progress
= false;
2907 /* Note that we're done with register allocation, so GRF fs_regs always
2908 * have a .reg_offset of 0.
2911 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2912 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
2913 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
2914 insert_gen4_post_send_dependency_workarounds(block
, inst
);
2920 invalidate_live_intervals();
2924 * Turns the generic expression-style uniform pull constant load instruction
2925 * into a hardware-specific series of instructions for loading a pull
2928 * The expression style allows the CSE pass before this to optimize out
2929 * repeated loads from the same offset, and gives the pre-register-allocation
2930 * scheduling full flexibility, while the conversion to native instructions
2931 * allows the post-register-allocation scheduler the best information
2934 * Note that execution masking for setting up pull constant loads is special:
2935 * the channels that need to be written are unrelated to the current execution
2936 * mask, since a later instruction will use one of the result channels as a
2937 * source operand for all 8 or 16 of its channels.
2940 fs_visitor::lower_uniform_pull_constant_loads()
2942 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2943 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
2946 if (devinfo
->gen
>= 7) {
2947 /* The offset arg before was a vec4-aligned byte offset. We need to
2948 * turn it into a dword offset.
2950 fs_reg const_offset_reg
= inst
->src
[1];
2951 assert(const_offset_reg
.file
== IMM
&&
2952 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
2953 const_offset_reg
.fixed_hw_reg
.dw1
.ud
/= 4;
2954 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1));
2956 /* We have to use a message header on Skylake to get SIMD4x2 mode.
2957 * Reserve space for the register.
2959 if (devinfo
->gen
>= 9) {
2960 payload
.reg_offset
++;
2961 alloc
.sizes
[payload
.reg
] = 2;
2964 /* This is actually going to be a MOV, but since only the first dword
2965 * is accessed, we have a special opcode to do just that one. Note
2966 * that this needs to be an operation that will be considered a def
2967 * by live variable analysis, or register allocation will explode.
2969 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
2970 8, payload
, const_offset_reg
);
2971 setup
->force_writemask_all
= true;
2973 setup
->ir
= inst
->ir
;
2974 setup
->annotation
= inst
->annotation
;
2975 inst
->insert_before(block
, setup
);
2977 /* Similarly, this will only populate the first 4 channels of the
2978 * result register (since we only use smear values from 0-3), but we
2979 * don't tell the optimizer.
2981 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
2982 inst
->src
[1] = payload
;
2984 invalidate_live_intervals();
2986 /* Before register allocation, we didn't tell the scheduler about the
2987 * MRF we use. We know it's safe to use this MRF because nothing
2988 * else does except for register spill/unspill, which generates and
2989 * uses its MRF within a single IR instruction.
2991 inst
->base_mrf
= 14;
2998 fs_visitor::lower_load_payload()
3000 bool progress
= false;
3002 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3003 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3006 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== GRF
);
3007 assert(inst
->saturate
== false);
3009 const fs_builder ibld
= bld
.group(inst
->exec_size
, inst
->force_sechalf
)
3010 .exec_all(inst
->force_writemask_all
)
3012 fs_reg dst
= inst
->dst
;
3014 /* Get rid of COMPR4. We'll add it back in if we need it */
3015 if (dst
.file
== MRF
)
3016 dst
.reg
= dst
.reg
& ~BRW_MRF_COMPR4
;
3019 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3020 if (inst
->src
[i
].file
!= BAD_FILE
) {
3021 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3022 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3024 ibld
.exec_all().MOV(mov_dst
, mov_src
);
3026 dst
= offset(dst
, 1);
3029 dst
.width
= inst
->exec_size
;
3030 if (inst
->dst
.file
== MRF
&& (inst
->dst
.reg
& BRW_MRF_COMPR4
) &&
3031 inst
->exec_size
> 8) {
3032 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3033 * a straightforward copy. Instead, the result of the
3034 * LOAD_PAYLOAD is treated as interleaved and the first four
3035 * non-header sources are unpacked as:
3046 * This is used for gen <= 5 fb writes.
3048 assert(inst
->exec_size
== 16);
3049 assert(inst
->header_size
+ 4 <= inst
->sources
);
3050 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3051 if (inst
->src
[i
].file
!= BAD_FILE
) {
3052 if (devinfo
->has_compr4
) {
3053 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3054 compr4_dst
.reg
|= BRW_MRF_COMPR4
;
3055 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3057 /* Platform doesn't have COMPR4. We have to fake it */
3058 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3060 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3061 ibld
.half(1).MOV(offset(mov_dst
, 4), half(inst
->src
[i
], 1));
3068 /* The loop above only ever incremented us through the first set
3069 * of 4 registers. However, thanks to the magic of COMPR4, we
3070 * actually wrote to the first 8 registers, so we need to take
3071 * that into account now.
3075 /* The COMPR4 code took care of the first 4 sources. We'll let
3076 * the regular path handle any remaining sources. Yes, we are
3077 * modifying the instruction but we're about to delete it so
3078 * this really doesn't hurt anything.
3080 inst
->header_size
+= 4;
3083 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3084 if (inst
->src
[i
].file
!= BAD_FILE
)
3085 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3086 dst
= offset(dst
, 1);
3089 inst
->remove(block
);
3094 invalidate_live_intervals();
3100 fs_visitor::lower_integer_multiplication()
3102 bool progress
= false;
3104 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit operation
3105 * directly, but Cherryview cannot.
3107 if (devinfo
->gen
>= 8 && !devinfo
->is_cherryview
)
3110 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3111 if (inst
->opcode
!= BRW_OPCODE_MUL
||
3112 inst
->dst
.is_accumulator() ||
3113 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3114 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3117 const fs_builder ibld
= bld
.at(block
, inst
);
3119 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3120 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3123 * If multiplying by an immediate value that fits in 16-bits, do a
3124 * single MUL instruction with that value in the proper location.
3126 if (inst
->src
[1].file
== IMM
&&
3127 inst
->src
[1].fixed_hw_reg
.dw1
.ud
< (1 << 16)) {
3128 if (devinfo
->gen
< 7) {
3129 fs_reg
imm(GRF
, alloc
.allocate(dispatch_width
/ 8),
3130 inst
->dst
.type
, dispatch_width
);
3131 ibld
.MOV(imm
, inst
->src
[1]);
3132 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3134 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3137 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3138 * do 32-bit integer multiplication in one instruction, but instead
3139 * must do a sequence (which actually calculates a 64-bit result):
3141 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3142 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3143 * mov(8) g2<1>D acc0<8,8,1>D
3145 * But on Gen > 6, the ability to use second accumulator register
3146 * (acc1) for non-float data types was removed, preventing a simple
3147 * implementation in SIMD16. A 16-channel result can be calculated by
3148 * executing the three instructions twice in SIMD8, once with quarter
3149 * control of 1Q for the first eight channels and again with 2Q for
3150 * the second eight channels.
3152 * Which accumulator register is implicitly accessed (by AccWrEnable
3153 * for instance) is determined by the quarter control. Unfortunately
3154 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3155 * implicit accumulator access by an instruction with 2Q will access
3156 * acc1 regardless of whether the data type is usable in acc1.
3158 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3159 * integer data types.
3161 * Since we only want the low 32-bits of the result, we can do two
3162 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3163 * adjust the high result and add them (like the mach is doing):
3165 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3166 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3167 * shl(8) g9<1>D g8<8,8,1>D 16D
3168 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3170 * We avoid the shl instruction by realizing that we only want to add
3171 * the low 16-bits of the "high" result to the high 16-bits of the
3172 * "low" result and using proper regioning on the add:
3174 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3175 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3176 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3178 * Since it does not use the (single) accumulator register, we can
3179 * schedule multi-component multiplications much better.
3182 if (inst
->conditional_mod
&& inst
->dst
.is_null()) {
3183 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
3184 inst
->dst
.type
, dispatch_width
);
3186 fs_reg low
= inst
->dst
;
3187 fs_reg
high(GRF
, alloc
.allocate(dispatch_width
/ 8),
3188 inst
->dst
.type
, dispatch_width
);
3190 if (devinfo
->gen
>= 7) {
3191 fs_reg src1_0_w
= inst
->src
[1];
3192 fs_reg src1_1_w
= inst
->src
[1];
3194 if (inst
->src
[1].file
== IMM
) {
3195 src1_0_w
.fixed_hw_reg
.dw1
.ud
&= 0xffff;
3196 src1_1_w
.fixed_hw_reg
.dw1
.ud
>>= 16;
3198 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3199 if (src1_0_w
.stride
!= 0) {
3200 assert(src1_0_w
.stride
== 1);
3201 src1_0_w
.stride
= 2;
3204 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3205 if (src1_1_w
.stride
!= 0) {
3206 assert(src1_1_w
.stride
== 1);
3207 src1_1_w
.stride
= 2;
3209 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3211 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3212 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3214 fs_reg src0_0_w
= inst
->src
[0];
3215 fs_reg src0_1_w
= inst
->src
[0];
3217 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3218 if (src0_0_w
.stride
!= 0) {
3219 assert(src0_0_w
.stride
== 1);
3220 src0_0_w
.stride
= 2;
3223 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3224 if (src0_1_w
.stride
!= 0) {
3225 assert(src0_1_w
.stride
== 1);
3226 src0_1_w
.stride
= 2;
3228 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3230 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3231 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3234 fs_reg dst
= inst
->dst
;
3235 dst
.type
= BRW_REGISTER_TYPE_UW
;
3236 dst
.subreg_offset
= 2;
3239 high
.type
= BRW_REGISTER_TYPE_UW
;
3242 low
.type
= BRW_REGISTER_TYPE_UW
;
3243 low
.subreg_offset
= 2;
3246 ibld
.ADD(dst
, low
, high
);
3248 if (inst
->conditional_mod
) {
3249 fs_reg
null(retype(ibld
.null_reg_f(), inst
->dst
.type
));
3250 set_condmod(inst
->conditional_mod
,
3251 ibld
.MOV(null
, inst
->dst
));
3255 inst
->remove(block
);
3260 invalidate_live_intervals();
3266 fs_visitor::dump_instructions()
3268 dump_instructions(NULL
);
3272 fs_visitor::dump_instructions(const char *name
)
3274 FILE *file
= stderr
;
3275 if (name
&& geteuid() != 0) {
3276 file
= fopen(name
, "w");
3282 calculate_register_pressure();
3283 int ip
= 0, max_pressure
= 0;
3284 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
3285 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
3286 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
3287 dump_instruction(inst
, file
);
3290 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
3293 foreach_in_list(backend_instruction
, inst
, &instructions
) {
3294 fprintf(file
, "%4d: ", ip
++);
3295 dump_instruction(inst
, file
);
3299 if (file
!= stderr
) {
3305 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
3307 dump_instruction(be_inst
, stderr
);
3311 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
3313 fs_inst
*inst
= (fs_inst
*)be_inst
;
3315 if (inst
->predicate
) {
3316 fprintf(file
, "(%cf0.%d) ",
3317 inst
->predicate_inverse
? '-' : '+',
3321 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
3323 fprintf(file
, ".sat");
3324 if (inst
->conditional_mod
) {
3325 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
3326 if (!inst
->predicate
&&
3327 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
3328 inst
->opcode
!= BRW_OPCODE_IF
&&
3329 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
3330 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
3333 fprintf(file
, "(%d) ", inst
->exec_size
);
3336 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
3339 switch (inst
->dst
.file
) {
3341 fprintf(file
, "vgrf%d", inst
->dst
.reg
);
3342 if (inst
->dst
.width
!= dispatch_width
)
3343 fprintf(file
, "@%d", inst
->dst
.width
);
3344 if (alloc
.sizes
[inst
->dst
.reg
] != inst
->dst
.width
/ 8 ||
3345 inst
->dst
.subreg_offset
)
3346 fprintf(file
, "+%d.%d",
3347 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
3350 fprintf(file
, "m%d", inst
->dst
.reg
);
3353 fprintf(file
, "(null)");
3356 fprintf(file
, "***u%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
3359 fprintf(file
, "***attr%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
3362 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
3363 switch (inst
->dst
.fixed_hw_reg
.nr
) {
3365 fprintf(file
, "null");
3367 case BRW_ARF_ADDRESS
:
3368 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
3370 case BRW_ARF_ACCUMULATOR
:
3371 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
3374 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
3375 inst
->dst
.fixed_hw_reg
.subnr
);
3378 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
3379 inst
->dst
.fixed_hw_reg
.subnr
);
3383 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
3385 if (inst
->dst
.fixed_hw_reg
.subnr
)
3386 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
3389 fprintf(file
, "???");
3392 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
3394 for (int i
= 0; i
< inst
->sources
; i
++) {
3395 if (inst
->src
[i
].negate
)
3397 if (inst
->src
[i
].abs
)
3399 switch (inst
->src
[i
].file
) {
3401 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
3402 if (inst
->src
[i
].width
!= dispatch_width
)
3403 fprintf(file
, "@%d", inst
->src
[i
].width
);
3404 if (alloc
.sizes
[inst
->src
[i
].reg
] != inst
->src
[i
].width
/ 8 ||
3405 inst
->src
[i
].subreg_offset
)
3406 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
3407 inst
->src
[i
].subreg_offset
);
3410 fprintf(file
, "***m%d***", inst
->src
[i
].reg
);
3413 fprintf(file
, "attr%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
3416 fprintf(file
, "u%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
3417 if (inst
->src
[i
].reladdr
) {
3418 fprintf(file
, "+reladdr");
3419 } else if (inst
->src
[i
].subreg_offset
) {
3420 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
3421 inst
->src
[i
].subreg_offset
);
3425 fprintf(file
, "(null)");
3428 switch (inst
->src
[i
].type
) {
3429 case BRW_REGISTER_TYPE_F
:
3430 fprintf(file
, "%ff", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
3432 case BRW_REGISTER_TYPE_W
:
3433 case BRW_REGISTER_TYPE_D
:
3434 fprintf(file
, "%dd", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
3436 case BRW_REGISTER_TYPE_UW
:
3437 case BRW_REGISTER_TYPE_UD
:
3438 fprintf(file
, "%uu", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
3440 case BRW_REGISTER_TYPE_VF
:
3441 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
3442 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
3443 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
3444 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
3445 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
3448 fprintf(file
, "???");
3453 if (inst
->src
[i
].fixed_hw_reg
.negate
)
3455 if (inst
->src
[i
].fixed_hw_reg
.abs
)
3457 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
3458 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
3460 fprintf(file
, "null");
3462 case BRW_ARF_ADDRESS
:
3463 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3465 case BRW_ARF_ACCUMULATOR
:
3466 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3469 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
3470 inst
->src
[i
].fixed_hw_reg
.subnr
);
3473 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
3474 inst
->src
[i
].fixed_hw_reg
.subnr
);
3478 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
3480 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
3481 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3482 if (inst
->src
[i
].fixed_hw_reg
.abs
)
3486 fprintf(file
, "???");
3489 if (inst
->src
[i
].abs
)
3492 if (inst
->src
[i
].file
!= IMM
) {
3493 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
3496 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
3497 fprintf(file
, ", ");
3502 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
3503 if (inst
->force_sechalf
)
3504 fprintf(file
, "2ndhalf ");
3506 fprintf(file
, "1sthalf ");
3509 fprintf(file
, "\n");
3513 * Possibly returns an instruction that set up @param reg.
3515 * Sometimes we want to take the result of some expression/variable
3516 * dereference tree and rewrite the instruction generating the result
3517 * of the tree. When processing the tree, we know that the
3518 * instructions generated are all writing temporaries that are dead
3519 * outside of this tree. So, if we have some instructions that write
3520 * a temporary, we're free to point that temp write somewhere else.
3522 * Note that this doesn't guarantee that the instruction generated
3523 * only reg -- it might be the size=4 destination of a texture instruction.
3526 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
3531 end
->is_partial_write() ||
3533 !reg
.equals(end
->dst
)) {
3541 fs_visitor::setup_payload_gen6()
3544 (prog
->InputsRead
& (1 << VARYING_SLOT_POS
)) != 0;
3545 unsigned barycentric_interp_modes
=
3546 (stage
== MESA_SHADER_FRAGMENT
) ?
3547 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
3549 assert(devinfo
->gen
>= 6);
3551 /* R0-1: masks, pixel X/Y coordinates. */
3552 payload
.num_regs
= 2;
3553 /* R2: only for 32-pixel dispatch.*/
3555 /* R3-26: barycentric interpolation coordinates. These appear in the
3556 * same order that they appear in the brw_wm_barycentric_interp_mode
3557 * enum. Each set of coordinates occupies 2 registers if dispatch width
3558 * == 8 and 4 registers if dispatch width == 16. Coordinates only
3559 * appear if they were enabled using the "Barycentric Interpolation
3560 * Mode" bits in WM_STATE.
3562 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
3563 if (barycentric_interp_modes
& (1 << i
)) {
3564 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
3565 payload
.num_regs
+= 2;
3566 if (dispatch_width
== 16) {
3567 payload
.num_regs
+= 2;
3572 /* R27: interpolated depth if uses source depth */
3574 payload
.source_depth_reg
= payload
.num_regs
;
3576 if (dispatch_width
== 16) {
3577 /* R28: interpolated depth if not SIMD8. */
3581 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
3583 payload
.source_w_reg
= payload
.num_regs
;
3585 if (dispatch_width
== 16) {
3586 /* R30: interpolated W if not SIMD8. */
3591 if (stage
== MESA_SHADER_FRAGMENT
) {
3592 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3593 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3594 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
3595 /* R31: MSAA position offsets. */
3596 if (prog_data
->uses_pos_offset
) {
3597 payload
.sample_pos_reg
= payload
.num_regs
;
3602 /* R32: MSAA input coverage mask */
3603 if (prog
->SystemValuesRead
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
3604 assert(devinfo
->gen
>= 7);
3605 payload
.sample_mask_in_reg
= payload
.num_regs
;
3607 if (dispatch_width
== 16) {
3608 /* R33: input coverage mask if not SIMD8. */
3613 /* R34-: bary for 32-pixel. */
3614 /* R58-59: interp W for 32-pixel. */
3616 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
3617 source_depth_to_render_target
= true;
3622 fs_visitor::setup_vs_payload()
3624 /* R0: thread header, R1: urb handles */
3625 payload
.num_regs
= 2;
3629 fs_visitor::setup_cs_payload()
3631 assert(devinfo
->gen
>= 7);
3633 payload
.num_regs
= 1;
3637 fs_visitor::assign_binding_table_offsets()
3639 assert(stage
== MESA_SHADER_FRAGMENT
);
3640 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3641 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3642 uint32_t next_binding_table_offset
= 0;
3644 /* If there are no color regions, we still perform an FB write to a null
3645 * renderbuffer, which we place at surface index 0.
3647 prog_data
->binding_table
.render_target_start
= next_binding_table_offset
;
3648 next_binding_table_offset
+= MAX2(key
->nr_color_regions
, 1);
3650 assign_common_binding_table_offsets(next_binding_table_offset
);
3654 fs_visitor::calculate_register_pressure()
3656 invalidate_live_intervals();
3657 calculate_live_intervals();
3659 unsigned num_instructions
= 0;
3660 foreach_block(block
, cfg
)
3661 num_instructions
+= block
->instructions
.length();
3663 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
3665 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
3666 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
3667 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
3672 fs_visitor::optimize()
3674 /* bld is the common builder object pointing at the end of the program we
3675 * used to translate it into i965 IR. For the optimization and lowering
3676 * passes coming next, any code added after the end of the program without
3677 * having explicitly called fs_builder::at() clearly points at a mistake.
3678 * Ideally optimization passes wouldn't be part of the visitor so they
3679 * wouldn't have access to bld at all, but they do, so just in case some
3680 * pass forgets to ask for a location explicitly set it to NULL here to
3683 bld
= bld
.at(NULL
, NULL
);
3685 split_virtual_grfs();
3687 move_uniform_array_access_to_pull_constants();
3688 assign_constant_locations();
3689 demote_pull_constants();
3691 #define OPT(pass, args...) ({ \
3693 bool this_progress = pass(args); \
3695 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
3696 char filename[64]; \
3697 snprintf(filename, 64, "%s%d-%04d-%02d-%02d-" #pass, \
3698 stage_abbrev, dispatch_width, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
3700 backend_shader::dump_instructions(filename); \
3703 progress = progress || this_progress; \
3707 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
3709 snprintf(filename
, 64, "%s%d-%04d-00-start",
3710 stage_abbrev
, dispatch_width
,
3711 shader_prog
? shader_prog
->Name
: 0);
3713 backend_shader::dump_instructions(filename
);
3724 OPT(remove_duplicate_mrf_writes
);
3728 OPT(opt_copy_propagate
);
3729 OPT(opt_peephole_predicated_break
);
3730 OPT(opt_cmod_propagation
);
3731 OPT(dead_code_eliminate
);
3732 OPT(opt_peephole_sel
);
3733 OPT(dead_control_flow_eliminate
, this);
3734 OPT(opt_register_renaming
);
3735 OPT(opt_redundant_discard_jumps
);
3736 OPT(opt_saturate_propagation
);
3737 OPT(opt_zero_samples
);
3738 OPT(register_coalesce
);
3739 OPT(compute_to_mrf
);
3740 OPT(eliminate_find_live_channel
);
3742 OPT(compact_virtual_grfs
);
3747 OPT(opt_sampler_eot
);
3749 if (OPT(lower_load_payload
)) {
3750 split_virtual_grfs();
3751 OPT(register_coalesce
);
3752 OPT(compute_to_mrf
);
3753 OPT(dead_code_eliminate
);
3756 OPT(opt_combine_constants
);
3757 OPT(lower_integer_multiplication
);
3759 lower_uniform_pull_constant_loads();
3763 * Three source instruction must have a GRF/MRF destination register.
3764 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
3767 fs_visitor::fixup_3src_null_dest()
3769 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3770 if (inst
->is_3src() && inst
->dst
.is_null()) {
3771 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
3778 fs_visitor::allocate_registers()
3780 bool allocated_without_spills
;
3782 static const enum instruction_scheduler_mode pre_modes
[] = {
3784 SCHEDULE_PRE_NON_LIFO
,
3788 /* Try each scheduling heuristic to see if it can successfully register
3789 * allocate without spilling. They should be ordered by decreasing
3790 * performance but increasing likelihood of allocating.
3792 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
3793 schedule_instructions(pre_modes
[i
]);
3796 assign_regs_trivial();
3797 allocated_without_spills
= true;
3799 allocated_without_spills
= assign_regs(false);
3801 if (allocated_without_spills
)
3805 if (!allocated_without_spills
) {
3806 /* We assume that any spilling is worse than just dropping back to
3807 * SIMD8. There's probably actually some intermediate point where
3808 * SIMD16 with a couple of spills is still better.
3810 if (dispatch_width
== 16) {
3811 fail("Failure to register allocate. Reduce number of "
3812 "live scalar values to avoid this.");
3814 perf_debug("%s shader triggered register spilling. "
3815 "Try reducing the number of live scalar values to "
3816 "improve performance.\n", stage_name
);
3819 /* Since we're out of heuristics, just go spill registers until we
3820 * get an allocation.
3822 while (!assign_regs(true)) {
3828 /* This must come after all optimization and register allocation, since
3829 * it inserts dead code that happens to have side effects, and it does
3830 * so based on the actual physical registers in use.
3832 insert_gen4_send_dependency_workarounds();
3837 if (!allocated_without_spills
)
3838 schedule_instructions(SCHEDULE_POST
);
3840 if (last_scratch
> 0)
3841 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
3845 fs_visitor::run_vs()
3847 assert(stage
== MESA_SHADER_VERTEX
);
3849 assign_common_binding_table_offsets(0);
3852 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3853 emit_shader_time_begin();
3862 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3863 emit_shader_time_end();
3869 assign_curb_setup();
3870 assign_vs_urb_setup();
3872 fixup_3src_null_dest();
3873 allocate_registers();
3879 fs_visitor::run_fs()
3881 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3882 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
3884 assert(stage
== MESA_SHADER_FRAGMENT
);
3886 sanity_param_count
= prog
->Parameters
->NumParameters
;
3888 assign_binding_table_offsets();
3890 if (devinfo
->gen
>= 6)
3891 setup_payload_gen6();
3893 setup_payload_gen4();
3897 } else if (brw
->use_rep_send
&& dispatch_width
== 16) {
3898 emit_repclear_shader();
3900 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3901 emit_shader_time_begin();
3903 calculate_urb_setup();
3904 if (prog
->InputsRead
> 0) {
3905 if (devinfo
->gen
< 6)
3906 emit_interpolation_setup_gen4();
3908 emit_interpolation_setup_gen6();
3911 /* We handle discards by keeping track of the still-live pixels in f0.1.
3912 * Initialize it with the dispatched pixels.
3914 if (wm_prog_data
->uses_kill
) {
3915 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
3916 discard_init
->flag_subreg
= 1;
3919 /* Generate FS IR for main(). (the visitor only descends into
3920 * functions called "main").
3927 if (wm_prog_data
->uses_kill
)
3928 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
3930 if (wm_key
->alpha_test_func
)
3935 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3936 emit_shader_time_end();
3942 assign_curb_setup();
3945 fixup_3src_null_dest();
3946 allocate_registers();
3952 if (dispatch_width
== 8)
3953 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
3955 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
3957 /* If any state parameters were appended, then ParameterValues could have
3958 * been realloced, in which case the driver uniform storage set up by
3959 * _mesa_associate_uniform_storage() would point to freed memory. Make
3960 * sure that didn't happen.
3962 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
3968 fs_visitor::run_cs()
3970 assert(stage
== MESA_SHADER_COMPUTE
);
3973 sanity_param_count
= prog
->Parameters
->NumParameters
;
3975 assign_common_binding_table_offsets(0);
3979 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3980 emit_shader_time_begin();
3987 emit_cs_terminate();
3989 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3990 emit_shader_time_end();
3996 assign_curb_setup();
3998 fixup_3src_null_dest();
3999 allocate_registers();
4004 /* If any state parameters were appended, then ParameterValues could have
4005 * been realloced, in which case the driver uniform storage set up by
4006 * _mesa_associate_uniform_storage() would point to freed memory. Make
4007 * sure that didn't happen.
4009 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
4015 brw_wm_fs_emit(struct brw_context
*brw
,
4017 const struct brw_wm_prog_key
*key
,
4018 struct brw_wm_prog_data
*prog_data
,
4019 struct gl_fragment_program
*fp
,
4020 struct gl_shader_program
*prog
,
4021 unsigned *final_assembly_size
)
4023 bool start_busy
= false;
4024 double start_time
= 0;
4026 if (unlikely(brw
->perf_debug
)) {
4027 start_busy
= (brw
->batch
.last_bo
&&
4028 drm_intel_bo_busy(brw
->batch
.last_bo
));
4029 start_time
= get_time();
4032 struct brw_shader
*shader
= NULL
;
4034 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
4036 if (unlikely(INTEL_DEBUG
& DEBUG_WM
))
4037 brw_dump_ir("fragment", prog
, &shader
->base
, &fp
->Base
);
4039 /* Now the main event: Visit the shader IR and generate our FS IR for it.
4041 fs_visitor
v(brw
, mem_ctx
, MESA_SHADER_FRAGMENT
, key
, &prog_data
->base
,
4042 prog
, &fp
->Base
, 8);
4045 prog
->LinkStatus
= false;
4046 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
4049 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
4055 cfg_t
*simd16_cfg
= NULL
;
4056 fs_visitor
v2(brw
, mem_ctx
, MESA_SHADER_FRAGMENT
, key
, &prog_data
->base
,
4057 prog
, &fp
->Base
, 16);
4058 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || brw
->use_rep_send
)) {
4059 if (!v
.simd16_unsupported
) {
4060 /* Try a SIMD16 compile */
4061 v2
.import_uniforms(&v
);
4063 perf_debug("SIMD16 shader failed to compile, falling back to "
4064 "SIMD8 at a 10-20%% performance cost: %s", v2
.fail_msg
);
4066 simd16_cfg
= v2
.cfg
;
4069 perf_debug("SIMD16 shader unsupported, falling back to "
4070 "SIMD8 at a 10-20%% performance cost: %s", v
.no16_msg
);
4075 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || brw
->no_simd8
;
4076 if ((no_simd8
|| brw
->gen
< 5) && simd16_cfg
) {
4078 prog_data
->no_8
= true;
4081 prog_data
->no_8
= false;
4084 fs_generator
g(brw
->intelScreen
->compiler
,
4085 mem_ctx
, (void *) key
, &prog_data
->base
,
4086 &fp
->Base
, v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
4088 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
4091 name
= ralloc_asprintf(mem_ctx
, "%s fragment shader %d",
4092 prog
->Label
? prog
->Label
: "unnamed",
4095 name
= ralloc_asprintf(mem_ctx
, "fragment program %d", fp
->Base
.Id
);
4097 g
.enable_debug(name
);
4101 g
.generate_code(simd8_cfg
, 8);
4103 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
4105 if (unlikely(brw
->perf_debug
) && shader
) {
4106 if (shader
->compiled_once
)
4107 brw_wm_debug_recompile(brw
, prog
, key
);
4108 shader
->compiled_once
= true;
4110 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
4111 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
4112 (get_time() - start_time
) * 1000);
4116 return g
.get_assembly(final_assembly_size
);
4120 brw_fs_precompile(struct gl_context
*ctx
,
4121 struct gl_shader_program
*shader_prog
,
4122 struct gl_program
*prog
)
4124 struct brw_context
*brw
= brw_context(ctx
);
4125 struct brw_wm_prog_key key
;
4127 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*) prog
;
4128 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
4129 bool program_uses_dfdy
= fp
->UsesDFdy
;
4131 memset(&key
, 0, sizeof(key
));
4135 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
4137 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
4138 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
4140 /* Just assume depth testing. */
4141 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
4142 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
4145 if (brw
->gen
< 6 || _mesa_bitcount_64(fp
->Base
.InputsRead
&
4146 BRW_FS_VARYING_INPUT_MASK
) > 16)
4147 key
.input_slots_valid
= fp
->Base
.InputsRead
| VARYING_BIT_POS
;
4149 brw_setup_tex_for_precompile(brw
, &key
.tex
, &fp
->Base
);
4151 if (fp
->Base
.InputsRead
& VARYING_BIT_POS
) {
4152 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
4155 key
.nr_color_regions
= _mesa_bitcount_64(fp
->Base
.OutputsWritten
&
4156 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
4157 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
)));
4159 if ((fp
->Base
.InputsRead
& VARYING_BIT_POS
) || program_uses_dfdy
) {
4160 key
.render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
) ||
4161 key
.nr_color_regions
> 1;
4164 key
.program_string_id
= bfp
->id
;
4166 uint32_t old_prog_offset
= brw
->wm
.base
.prog_offset
;
4167 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
4169 bool success
= brw_codegen_wm_prog(brw
, shader_prog
, bfp
, &key
);
4171 brw
->wm
.base
.prog_offset
= old_prog_offset
;
4172 brw
->wm
.prog_data
= old_prog_data
;
4178 brw_setup_tex_for_precompile(struct brw_context
*brw
,
4179 struct brw_sampler_prog_key_data
*tex
,
4180 struct gl_program
*prog
)
4182 const bool has_shader_channel_select
= brw
->is_haswell
|| brw
->gen
>= 8;
4183 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
4184 for (unsigned i
= 0; i
< sampler_count
; i
++) {
4185 if (!has_shader_channel_select
&& (prog
->ShadowSamplers
& (1 << i
))) {
4186 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
4188 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
4190 /* Color sampler: assume no swizzling. */
4191 tex
->swizzles
[i
] = SWIZZLE_XYZW
;