2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
33 #include <sys/types.h>
35 #include "main/hash_table.h"
36 #include "main/macros.h"
37 #include "main/shaderobj.h"
38 #include "main/uniforms.h"
39 #include "main/fbobject.h"
40 #include "program/prog_parameter.h"
41 #include "program/prog_print.h"
42 #include "program/register_allocate.h"
43 #include "program/sampler.h"
44 #include "program/hash_table.h"
45 #include "brw_context.h"
50 #include "glsl/glsl_types.h"
51 #include "glsl/ir_print_visitor.h"
56 memset(this, 0, sizeof(*this));
57 this->opcode
= BRW_OPCODE_NOP
;
58 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
60 this->dst
= reg_undef
;
61 this->src
[0] = reg_undef
;
62 this->src
[1] = reg_undef
;
63 this->src
[2] = reg_undef
;
65 /* This will be the case for almost all instructions. */
66 this->regs_written
= 1;
74 fs_inst::fs_inst(enum opcode opcode
)
77 this->opcode
= opcode
;
80 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
)
83 this->opcode
= opcode
;
87 assert(dst
.reg_offset
>= 0);
90 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
)
93 this->opcode
= opcode
;
98 assert(dst
.reg_offset
>= 0);
99 if (src
[0].file
== GRF
)
100 assert(src
[0].reg_offset
>= 0);
103 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
106 this->opcode
= opcode
;
112 assert(dst
.reg_offset
>= 0);
113 if (src
[0].file
== GRF
)
114 assert(src
[0].reg_offset
>= 0);
115 if (src
[1].file
== GRF
)
116 assert(src
[1].reg_offset
>= 0);
119 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
,
120 fs_reg src0
, fs_reg src1
, fs_reg src2
)
123 this->opcode
= opcode
;
130 assert(dst
.reg_offset
>= 0);
131 if (src
[0].file
== GRF
)
132 assert(src
[0].reg_offset
>= 0);
133 if (src
[1].file
== GRF
)
134 assert(src
[1].reg_offset
>= 0);
135 if (src
[2].file
== GRF
)
136 assert(src
[2].reg_offset
>= 0);
141 fs_visitor::op(fs_reg dst, fs_reg src0) \
143 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0); \
148 fs_visitor::op(fs_reg dst, fs_reg src0, fs_reg src1) \
150 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1); \
155 fs_visitor::op(fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2) \
157 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1, src2);\
177 /** Gen4 predicated IF. */
179 fs_visitor::IF(uint32_t predicate
)
181 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
);
182 inst
->predicate
= predicate
;
186 /** Gen6+ IF with embedded comparison. */
188 fs_visitor::IF(fs_reg src0
, fs_reg src1
, uint32_t condition
)
190 assert(intel
->gen
>= 6);
191 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
,
192 reg_null_d
, src0
, src1
);
193 inst
->conditional_mod
= condition
;
198 * CMP: Sets the low bit of the destination channels with the result
199 * of the comparison, while the upper bits are undefined, and updates
200 * the flag register with the packed 16 bits of the result.
203 fs_visitor::CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
, uint32_t condition
)
207 /* Take the instruction:
209 * CMP null<d> src0<f> src1<f>
211 * Original gen4 does type conversion to the destination type before
212 * comparison, producing garbage results for floating point comparisons.
213 * gen5 does the comparison on the execution type (resolved source types),
214 * so dst type doesn't matter. gen6 does comparison and then uses the
215 * result as if it was the dst type with no conversion, which happens to
216 * mostly work out for float-interpreted-as-int since our comparisons are
219 if (intel
->gen
== 4) {
220 dst
.type
= src0
.type
;
221 if (dst
.file
== FIXED_HW_REG
)
222 dst
.fixed_hw_reg
.type
= dst
.type
;
225 resolve_ud_negate(&src0
);
226 resolve_ud_negate(&src1
);
228 inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_CMP
, dst
, src0
, src1
);
229 inst
->conditional_mod
= condition
;
235 fs_visitor::VARYING_PULL_CONSTANT_LOAD(fs_reg dst
, fs_reg surf_index
,
236 fs_reg varying_offset
,
237 uint32_t const_offset
)
239 exec_list instructions
;
242 /* We have our constant surface use a pitch of 4 bytes, so our index can
243 * be any component of a vector, and then we load 4 contiguous
244 * components starting from that.
246 * We break down the const_offset to a portion added to the variable
247 * offset and a portion done using reg_offset, which means that if you
248 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
249 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
250 * CSE can later notice that those loads are all the same and eliminate
251 * the redundant ones.
253 fs_reg vec4_offset
= fs_reg(this, glsl_type::int_type
);
254 instructions
.push_tail(ADD(vec4_offset
,
255 varying_offset
, const_offset
& ~3));
258 if (intel
->gen
== 4 && dispatch_width
== 8) {
259 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
260 * u, v, r) as parameters, or we can just use the SIMD16 message
261 * consisting of (header, u). We choose the second, at the cost of a
262 * longer return length.
269 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
271 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
272 fs_reg vec4_result
= fs_reg(GRF
, virtual_grf_alloc(4 * scale
), dst
.type
);
273 inst
= new(mem_ctx
) fs_inst(op
, vec4_result
, surf_index
, vec4_offset
);
274 inst
->regs_written
= 4 * scale
;
275 instructions
.push_tail(inst
);
277 if (intel
->gen
< 7) {
279 inst
->header_present
= true;
283 inst
->mlen
= 1 + dispatch_width
/ 8;
286 vec4_result
.reg_offset
+= (const_offset
& 3) * scale
;
287 instructions
.push_tail(MOV(dst
, vec4_result
));
293 * A helper for MOV generation for fixing up broken hardware SEND dependency
297 fs_visitor::DEP_RESOLVE_MOV(int grf
)
299 fs_inst
*inst
= MOV(brw_null_reg(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
302 inst
->annotation
= "send dependency resolve";
304 /* The caller always wants uncompressed to emit the minimal extra
305 * dependencies, and to avoid having to deal with aligning its regs to 2.
307 inst
->force_uncompressed
= true;
313 fs_inst::equals(fs_inst
*inst
)
315 return (opcode
== inst
->opcode
&&
316 dst
.equals(inst
->dst
) &&
317 src
[0].equals(inst
->src
[0]) &&
318 src
[1].equals(inst
->src
[1]) &&
319 src
[2].equals(inst
->src
[2]) &&
320 saturate
== inst
->saturate
&&
321 predicate
== inst
->predicate
&&
322 conditional_mod
== inst
->conditional_mod
&&
323 mlen
== inst
->mlen
&&
324 base_mrf
== inst
->base_mrf
&&
325 sampler
== inst
->sampler
&&
326 target
== inst
->target
&&
328 header_present
== inst
->header_present
&&
329 shadow_compare
== inst
->shadow_compare
&&
330 offset
== inst
->offset
);
334 fs_inst::overwrites_reg(const fs_reg
®
)
336 return (reg
.file
== dst
.file
&&
337 reg
.reg
== dst
.reg
&&
338 reg
.reg_offset
>= dst
.reg_offset
&&
339 reg
.reg_offset
< dst
.reg_offset
+ regs_written
);
345 return (opcode
== SHADER_OPCODE_TEX
||
346 opcode
== FS_OPCODE_TXB
||
347 opcode
== SHADER_OPCODE_TXD
||
348 opcode
== SHADER_OPCODE_TXF
||
349 opcode
== SHADER_OPCODE_TXF_MS
||
350 opcode
== SHADER_OPCODE_TXL
||
351 opcode
== SHADER_OPCODE_TXS
||
352 opcode
== SHADER_OPCODE_LOD
);
358 return (opcode
== SHADER_OPCODE_RCP
||
359 opcode
== SHADER_OPCODE_RSQ
||
360 opcode
== SHADER_OPCODE_SQRT
||
361 opcode
== SHADER_OPCODE_EXP2
||
362 opcode
== SHADER_OPCODE_LOG2
||
363 opcode
== SHADER_OPCODE_SIN
||
364 opcode
== SHADER_OPCODE_COS
||
365 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
366 opcode
== SHADER_OPCODE_INT_REMAINDER
||
367 opcode
== SHADER_OPCODE_POW
);
371 fs_inst::is_control_flow()
375 case BRW_OPCODE_WHILE
:
377 case BRW_OPCODE_ELSE
:
378 case BRW_OPCODE_ENDIF
:
379 case BRW_OPCODE_BREAK
:
380 case BRW_OPCODE_CONTINUE
:
388 fs_inst::is_send_from_grf()
390 return (opcode
== FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
||
391 opcode
== SHADER_OPCODE_SHADER_TIME_ADD
||
392 (opcode
== FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
&&
393 src
[1].file
== GRF
));
397 fs_visitor::can_do_source_mods(fs_inst
*inst
)
399 if (intel
->gen
== 6 && inst
->is_math())
402 if (inst
->is_send_from_grf())
411 memset(this, 0, sizeof(*this));
415 /** Generic unset register constructor. */
419 this->file
= BAD_FILE
;
422 /** Immediate value constructor. */
423 fs_reg::fs_reg(float f
)
427 this->type
= BRW_REGISTER_TYPE_F
;
431 /** Immediate value constructor. */
432 fs_reg::fs_reg(int32_t i
)
436 this->type
= BRW_REGISTER_TYPE_D
;
440 /** Immediate value constructor. */
441 fs_reg::fs_reg(uint32_t u
)
445 this->type
= BRW_REGISTER_TYPE_UD
;
449 /** Fixed brw_reg Immediate value constructor. */
450 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
453 this->file
= FIXED_HW_REG
;
454 this->fixed_hw_reg
= fixed_hw_reg
;
455 this->type
= fixed_hw_reg
.type
;
459 fs_reg::equals(const fs_reg
&r
) const
461 return (file
== r
.file
&&
463 reg_offset
== r
.reg_offset
&&
465 negate
== r
.negate
&&
467 !reladdr
&& !r
.reladdr
&&
468 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
469 sizeof(fixed_hw_reg
)) == 0 &&
475 fs_reg::is_zero() const
480 return type
== BRW_REGISTER_TYPE_F
? imm
.f
== 0.0 : imm
.i
== 0;
484 fs_reg::is_one() const
489 return type
== BRW_REGISTER_TYPE_F
? imm
.f
== 1.0 : imm
.i
== 1;
493 fs_visitor::type_size(const struct glsl_type
*type
)
495 unsigned int size
, i
;
497 switch (type
->base_type
) {
500 case GLSL_TYPE_FLOAT
:
502 return type
->components();
503 case GLSL_TYPE_ARRAY
:
504 return type_size(type
->fields
.array
) * type
->length
;
505 case GLSL_TYPE_STRUCT
:
507 for (i
= 0; i
< type
->length
; i
++) {
508 size
+= type_size(type
->fields
.structure
[i
].type
);
511 case GLSL_TYPE_SAMPLER
:
512 /* Samplers take up no register space, since they're baked in at
517 case GLSL_TYPE_ERROR
:
518 case GLSL_TYPE_INTERFACE
:
519 assert(!"not reached");
527 fs_visitor::get_timestamp()
529 assert(intel
->gen
>= 7);
531 fs_reg ts
= fs_reg(retype(brw_vec1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
534 BRW_REGISTER_TYPE_UD
));
536 fs_reg dst
= fs_reg(this, glsl_type::uint_type
);
538 fs_inst
*mov
= emit(MOV(dst
, ts
));
539 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
540 * even if it's not enabled in the dispatch.
542 mov
->force_writemask_all
= true;
543 mov
->force_uncompressed
= true;
545 /* The caller wants the low 32 bits of the timestamp. Since it's running
546 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
547 * which is plenty of time for our purposes. It is identical across the
548 * EUs, but since it's tracking GPU core speed it will increment at a
549 * varying rate as render P-states change.
551 * The caller could also check if render P-states have changed (or anything
552 * else that might disrupt timing) by setting smear to 2 and checking if
553 * that field is != 0.
561 fs_visitor::emit_shader_time_begin()
563 current_annotation
= "shader time start";
564 shader_start_time
= get_timestamp();
568 fs_visitor::emit_shader_time_end()
570 current_annotation
= "shader time end";
572 enum shader_time_shader_type type
, written_type
, reset_type
;
573 if (dispatch_width
== 8) {
575 written_type
= ST_FS8_WRITTEN
;
576 reset_type
= ST_FS8_RESET
;
578 assert(dispatch_width
== 16);
580 written_type
= ST_FS16_WRITTEN
;
581 reset_type
= ST_FS16_RESET
;
584 fs_reg shader_end_time
= get_timestamp();
586 /* Check that there weren't any timestamp reset events (assuming these
587 * were the only two timestamp reads that happened).
589 fs_reg reset
= shader_end_time
;
591 fs_inst
*test
= emit(AND(reg_null_d
, reset
, fs_reg(1u)));
592 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
593 emit(IF(BRW_PREDICATE_NORMAL
));
595 push_force_uncompressed();
596 fs_reg start
= shader_start_time
;
598 fs_reg diff
= fs_reg(this, glsl_type::uint_type
);
599 emit(ADD(diff
, start
, shader_end_time
));
601 /* If there were no instructions between the two timestamp gets, the diff
602 * is 2 cycles. Remove that overhead, so I can forget about that when
603 * trying to determine the time taken for single instructions.
605 emit(ADD(diff
, diff
, fs_reg(-2u)));
607 emit_shader_time_write(type
, diff
);
608 emit_shader_time_write(written_type
, fs_reg(1u));
609 emit(BRW_OPCODE_ELSE
);
610 emit_shader_time_write(reset_type
, fs_reg(1u));
611 emit(BRW_OPCODE_ENDIF
);
613 pop_force_uncompressed();
617 fs_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
620 int shader_time_index
=
621 brw_get_shader_time_index(brw
, shader_prog
, &fp
->Base
, type
);
622 fs_reg offset
= fs_reg(shader_time_index
* SHADER_TIME_STRIDE
);
625 if (dispatch_width
== 8)
626 payload
= fs_reg(this, glsl_type::uvec2_type
);
628 payload
= fs_reg(this, glsl_type::uint_type
);
630 emit(fs_inst(SHADER_OPCODE_SHADER_TIME_ADD
,
631 fs_reg(), payload
, offset
, value
));
635 fs_visitor::fail(const char *format
, ...)
645 va_start(va
, format
);
646 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
648 msg
= ralloc_asprintf(mem_ctx
, "FS compile failed: %s\n", msg
);
650 this->fail_msg
= msg
;
652 if (INTEL_DEBUG
& DEBUG_WM
) {
653 fprintf(stderr
, "%s", msg
);
658 fs_visitor::emit(enum opcode opcode
)
660 return emit(fs_inst(opcode
));
664 fs_visitor::emit(enum opcode opcode
, fs_reg dst
)
666 return emit(fs_inst(opcode
, dst
));
670 fs_visitor::emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
)
672 return emit(fs_inst(opcode
, dst
, src0
));
676 fs_visitor::emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
678 return emit(fs_inst(opcode
, dst
, src0
, src1
));
682 fs_visitor::emit(enum opcode opcode
, fs_reg dst
,
683 fs_reg src0
, fs_reg src1
, fs_reg src2
)
685 return emit(fs_inst(opcode
, dst
, src0
, src1
, src2
));
689 fs_visitor::push_force_uncompressed()
691 force_uncompressed_stack
++;
695 fs_visitor::pop_force_uncompressed()
697 force_uncompressed_stack
--;
698 assert(force_uncompressed_stack
>= 0);
702 fs_visitor::push_force_sechalf()
704 force_sechalf_stack
++;
708 fs_visitor::pop_force_sechalf()
710 force_sechalf_stack
--;
711 assert(force_sechalf_stack
>= 0);
715 * Returns true if the instruction has a flag that means it won't
716 * update an entire destination register.
718 * For example, dead code elimination and live variable analysis want to know
719 * when a write to a variable screens off any preceding values that were in
723 fs_inst::is_partial_write()
725 return (this->predicate
||
726 this->force_uncompressed
||
727 this->force_sechalf
);
731 * Returns how many MRFs an FS opcode will write over.
733 * Note that this is not the 0 or 1 implied writes in an actual gen
734 * instruction -- the FS opcodes often generate MOVs in addition.
737 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
742 switch (inst
->opcode
) {
743 case SHADER_OPCODE_RCP
:
744 case SHADER_OPCODE_RSQ
:
745 case SHADER_OPCODE_SQRT
:
746 case SHADER_OPCODE_EXP2
:
747 case SHADER_OPCODE_LOG2
:
748 case SHADER_OPCODE_SIN
:
749 case SHADER_OPCODE_COS
:
750 return 1 * dispatch_width
/ 8;
751 case SHADER_OPCODE_POW
:
752 case SHADER_OPCODE_INT_QUOTIENT
:
753 case SHADER_OPCODE_INT_REMAINDER
:
754 return 2 * dispatch_width
/ 8;
755 case SHADER_OPCODE_TEX
:
757 case SHADER_OPCODE_TXD
:
758 case SHADER_OPCODE_TXF
:
759 case SHADER_OPCODE_TXF_MS
:
760 case SHADER_OPCODE_TXL
:
761 case SHADER_OPCODE_TXS
:
762 case SHADER_OPCODE_LOD
:
764 case FS_OPCODE_FB_WRITE
:
766 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
767 case FS_OPCODE_UNSPILL
:
769 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
771 case FS_OPCODE_SPILL
:
774 assert(!"not reached");
780 fs_visitor::virtual_grf_alloc(int size
)
782 if (virtual_grf_array_size
<= virtual_grf_count
) {
783 if (virtual_grf_array_size
== 0)
784 virtual_grf_array_size
= 16;
786 virtual_grf_array_size
*= 2;
787 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
788 virtual_grf_array_size
);
790 virtual_grf_sizes
[virtual_grf_count
] = size
;
791 return virtual_grf_count
++;
794 /** Fixed HW reg constructor. */
795 fs_reg::fs_reg(enum register_file file
, int reg
)
800 this->type
= BRW_REGISTER_TYPE_F
;
803 /** Fixed HW reg constructor. */
804 fs_reg::fs_reg(enum register_file file
, int reg
, uint32_t type
)
812 /** Automatic reg constructor. */
813 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
818 this->reg
= v
->virtual_grf_alloc(v
->type_size(type
));
819 this->reg_offset
= 0;
820 this->type
= brw_type_for_base_type(type
);
824 fs_visitor::variable_storage(ir_variable
*var
)
826 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
830 import_uniforms_callback(const void *key
,
834 struct hash_table
*dst_ht
= (struct hash_table
*)closure
;
835 const fs_reg
*reg
= (const fs_reg
*)data
;
837 if (reg
->file
!= UNIFORM
)
840 hash_table_insert(dst_ht
, data
, key
);
843 /* For 16-wide, we need to follow from the uniform setup of 8-wide dispatch.
844 * This brings in those uniform definitions
847 fs_visitor::import_uniforms(fs_visitor
*v
)
849 hash_table_call_foreach(v
->variable_ht
,
850 import_uniforms_callback
,
852 this->params_remap
= v
->params_remap
;
855 /* Our support for uniforms is piggy-backed on the struct
856 * gl_fragment_program, because that's where the values actually
857 * get stored, rather than in some global gl_shader_program uniform
861 fs_visitor::setup_uniform_values(ir_variable
*ir
)
863 int namelen
= strlen(ir
->name
);
865 /* The data for our (non-builtin) uniforms is stored in a series of
866 * gl_uniform_driver_storage structs for each subcomponent that
867 * glGetUniformLocation() could name. We know it's been set up in the same
868 * order we'd walk the type, so walk the list of storage and find anything
869 * with our name, or the prefix of a component that starts with our name.
871 unsigned params_before
= c
->prog_data
.nr_params
;
872 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
873 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
875 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
876 (storage
->name
[namelen
] != 0 &&
877 storage
->name
[namelen
] != '.' &&
878 storage
->name
[namelen
] != '[')) {
882 unsigned slots
= storage
->type
->component_slots();
883 if (storage
->array_elements
)
884 slots
*= storage
->array_elements
;
886 for (unsigned i
= 0; i
< slots
; i
++) {
887 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
888 &storage
->storage
[i
].f
;
892 /* Make sure we actually initialized the right amount of stuff here. */
893 assert(params_before
+ ir
->type
->component_slots() ==
894 c
->prog_data
.nr_params
);
898 /* Our support for builtin uniforms is even scarier than non-builtin.
899 * It sits on top of the PROG_STATE_VAR parameters that are
900 * automatically updated from GL context state.
903 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
905 const ir_state_slot
*const slots
= ir
->state_slots
;
906 assert(ir
->state_slots
!= NULL
);
908 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
909 /* This state reference has already been setup by ir_to_mesa, but we'll
910 * get the same index back here.
912 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
913 (gl_state_index
*)slots
[i
].tokens
);
915 /* Add each of the unique swizzles of the element as a parameter.
916 * This'll end up matching the expected layout of the
917 * array/matrix/structure we're trying to fill in.
920 for (unsigned int j
= 0; j
< 4; j
++) {
921 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
922 if (swiz
== last_swiz
)
926 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
927 &fp
->Base
.Parameters
->ParameterValues
[index
][swiz
].f
;
933 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
935 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
937 bool flip
= !ir
->origin_upper_left
^ c
->key
.render_to_fbo
;
940 if (ir
->pixel_center_integer
) {
941 emit(MOV(wpos
, this->pixel_x
));
943 emit(ADD(wpos
, this->pixel_x
, fs_reg(0.5f
)));
948 if (!flip
&& ir
->pixel_center_integer
) {
949 emit(MOV(wpos
, this->pixel_y
));
951 fs_reg pixel_y
= this->pixel_y
;
952 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
955 pixel_y
.negate
= true;
956 offset
+= c
->key
.drawable_height
- 1.0;
959 emit(ADD(wpos
, pixel_y
, fs_reg(offset
)));
964 if (intel
->gen
>= 6) {
965 emit(MOV(wpos
, fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
967 emit(FS_OPCODE_LINTERP
, wpos
,
968 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
969 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
970 interp_reg(VARYING_SLOT_POS
, 2));
974 /* gl_FragCoord.w: Already set up in emit_interpolation */
975 emit(BRW_OPCODE_MOV
, wpos
, this->wpos_w
);
981 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
982 glsl_interp_qualifier interpolation_mode
,
985 brw_wm_barycentric_interp_mode barycoord_mode
;
987 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
988 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
990 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
992 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
993 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
995 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
997 return emit(FS_OPCODE_LINTERP
, attr
,
998 this->delta_x
[barycoord_mode
],
999 this->delta_y
[barycoord_mode
], interp
);
1003 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
1005 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1006 reg
->type
= brw_type_for_base_type(ir
->type
->get_scalar_type());
1009 unsigned int array_elements
;
1010 const glsl_type
*type
;
1012 if (ir
->type
->is_array()) {
1013 array_elements
= ir
->type
->length
;
1014 if (array_elements
== 0) {
1015 fail("dereferenced array '%s' has length 0\n", ir
->name
);
1017 type
= ir
->type
->fields
.array
;
1023 glsl_interp_qualifier interpolation_mode
=
1024 ir
->determine_interpolation_mode(c
->key
.flat_shade
);
1026 int location
= ir
->location
;
1027 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1028 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1029 if (urb_setup
[location
] == -1) {
1030 /* If there's no incoming setup data for this slot, don't
1031 * emit interpolation for it.
1033 attr
.reg_offset
+= type
->vector_elements
;
1038 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1039 /* Constant interpolation (flat shading) case. The SF has
1040 * handed us defined values in only the constant offset
1041 * field of the setup reg.
1043 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1044 struct brw_reg interp
= interp_reg(location
, k
);
1045 interp
= suboffset(interp
, 3);
1046 interp
.type
= reg
->type
;
1047 emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1051 /* Smooth/noperspective interpolation case. */
1052 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1053 /* FINISHME: At some point we probably want to push
1054 * this farther by giving similar treatment to the
1055 * other potentially constant components of the
1056 * attribute, as well as making brw_vs_constval.c
1057 * handle varyings other than gl_TexCoord.
1059 struct brw_reg interp
= interp_reg(location
, k
);
1060 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1062 if (brw
->needs_unlit_centroid_workaround
&& ir
->centroid
) {
1063 /* Get the pixel/sample mask into f0 so that we know
1064 * which pixels are lit. Then, for each channel that is
1065 * unlit, replace the centroid data with non-centroid
1068 emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1069 fs_inst
*inst
= emit_linterp(attr
, fs_reg(interp
),
1070 interpolation_mode
, false);
1071 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1072 inst
->predicate_inverse
= true;
1074 if (intel
->gen
< 6) {
1075 emit(BRW_OPCODE_MUL
, attr
, attr
, this->pixel_w
);
1089 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
1091 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1093 /* The frontfacing comes in as a bit in the thread payload. */
1094 if (intel
->gen
>= 6) {
1095 emit(BRW_OPCODE_ASR
, *reg
,
1096 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1098 emit(BRW_OPCODE_NOT
, *reg
, *reg
);
1099 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1));
1101 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
1102 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
1105 emit(CMP(*reg
, fs_reg(r1_6ud
), fs_reg(1u << 31), BRW_CONDITIONAL_L
));
1106 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u));
1113 fs_visitor::fix_math_operand(fs_reg src
)
1115 /* Can't do hstride == 0 args on gen6 math, so expand it out. We
1116 * might be able to do better by doing execsize = 1 math and then
1117 * expanding that result out, but we would need to be careful with
1120 * The hardware ignores source modifiers (negate and abs) on math
1121 * instructions, so we also move to a temp to set those up.
1123 if (intel
->gen
== 6 && src
.file
!= UNIFORM
&& src
.file
!= IMM
&&
1124 !src
.abs
&& !src
.negate
)
1127 /* Gen7 relaxes most of the above restrictions, but still can't use IMM
1130 if (intel
->gen
>= 7 && src
.file
!= IMM
)
1133 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
1134 expanded
.type
= src
.type
;
1135 emit(BRW_OPCODE_MOV
, expanded
, src
);
1140 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src
)
1143 case SHADER_OPCODE_RCP
:
1144 case SHADER_OPCODE_RSQ
:
1145 case SHADER_OPCODE_SQRT
:
1146 case SHADER_OPCODE_EXP2
:
1147 case SHADER_OPCODE_LOG2
:
1148 case SHADER_OPCODE_SIN
:
1149 case SHADER_OPCODE_COS
:
1152 assert(!"not reached: bad math opcode");
1156 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
1157 * might be able to do better by doing execsize = 1 math and then
1158 * expanding that result out, but we would need to be careful with
1161 * Gen 6 hardware ignores source modifiers (negate and abs) on math
1162 * instructions, so we also move to a temp to set those up.
1164 if (intel
->gen
>= 6)
1165 src
= fix_math_operand(src
);
1167 fs_inst
*inst
= emit(opcode
, dst
, src
);
1169 if (intel
->gen
< 6) {
1171 inst
->mlen
= dispatch_width
/ 8;
1178 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
1184 case SHADER_OPCODE_INT_QUOTIENT
:
1185 case SHADER_OPCODE_INT_REMAINDER
:
1186 if (intel
->gen
>= 7 && dispatch_width
== 16)
1187 fail("16-wide INTDIV unsupported\n");
1189 case SHADER_OPCODE_POW
:
1192 assert(!"not reached: unsupported binary math opcode.");
1196 if (intel
->gen
>= 6) {
1197 src0
= fix_math_operand(src0
);
1198 src1
= fix_math_operand(src1
);
1200 inst
= emit(opcode
, dst
, src0
, src1
);
1202 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
1203 * "Message Payload":
1205 * "Operand0[7]. For the INT DIV functions, this operand is the
1208 * "Operand1[7]. For the INT DIV functions, this operand is the
1211 bool is_int_div
= opcode
!= SHADER_OPCODE_POW
;
1212 fs_reg
&op0
= is_int_div
? src1
: src0
;
1213 fs_reg
&op1
= is_int_div
? src0
: src1
;
1215 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1, op1
.type
), op1
);
1216 inst
= emit(opcode
, dst
, op0
, reg_null_f
);
1218 inst
->base_mrf
= base_mrf
;
1219 inst
->mlen
= 2 * dispatch_width
/ 8;
1225 fs_visitor::assign_curb_setup()
1227 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
1228 if (dispatch_width
== 8) {
1229 c
->prog_data
.first_curbe_grf
= c
->nr_payload_regs
;
1231 c
->prog_data
.first_curbe_grf_16
= c
->nr_payload_regs
;
1234 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1235 foreach_list(node
, &this->instructions
) {
1236 fs_inst
*inst
= (fs_inst
*)node
;
1238 for (unsigned int i
= 0; i
< 3; i
++) {
1239 if (inst
->src
[i
].file
== UNIFORM
) {
1240 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1241 struct brw_reg brw_reg
= brw_vec1_grf(c
->nr_payload_regs
+
1245 inst
->src
[i
].file
= FIXED_HW_REG
;
1246 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
1253 fs_visitor::calculate_urb_setup()
1255 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1260 /* Figure out where each of the incoming setup attributes lands. */
1261 if (intel
->gen
>= 6) {
1262 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1263 if (fp
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
1264 urb_setup
[i
] = urb_next
++;
1268 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1269 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1270 /* Point size is packed into the header, not as a general attribute */
1271 if (i
== VARYING_SLOT_PSIZ
)
1274 if (c
->key
.input_slots_valid
& BITFIELD64_BIT(i
)) {
1275 /* The back color slot is skipped when the front color is
1276 * also written to. In addition, some slots can be
1277 * written in the vertex shader and not read in the
1278 * fragment shader. So the register number must always be
1279 * incremented, mapped or not.
1281 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1282 urb_setup
[i
] = urb_next
;
1288 * It's a FS only attribute, and we did interpolation for this attribute
1289 * in SF thread. So, count it here, too.
1291 * See compile_sf_prog() for more info.
1293 if (fp
->Base
.InputsRead
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1294 urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1297 /* Each attribute is 4 setup channels, each of which is half a reg. */
1298 c
->prog_data
.urb_read_length
= urb_next
* 2;
1302 fs_visitor::assign_urb_setup()
1304 int urb_start
= c
->nr_payload_regs
+ c
->prog_data
.curb_read_length
;
1306 /* Offset all the urb_setup[] index by the actual position of the
1307 * setup regs, now that the location of the constants has been chosen.
1309 foreach_list(node
, &this->instructions
) {
1310 fs_inst
*inst
= (fs_inst
*)node
;
1312 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1313 assert(inst
->src
[2].file
== FIXED_HW_REG
);
1314 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
1317 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1318 assert(inst
->src
[0].file
== FIXED_HW_REG
);
1319 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1323 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
1327 * Split large virtual GRFs into separate components if we can.
1329 * This is mostly duplicated with what brw_fs_vector_splitting does,
1330 * but that's really conservative because it's afraid of doing
1331 * splitting that doesn't result in real progress after the rest of
1332 * the optimization phases, which would cause infinite looping in
1333 * optimization. We can do it once here, safely. This also has the
1334 * opportunity to split interpolated values, or maybe even uniforms,
1335 * which we don't have at the IR level.
1337 * We want to split, because virtual GRFs are what we register
1338 * allocate and spill (due to contiguousness requirements for some
1339 * instructions), and they're what we naturally generate in the
1340 * codegen process, but most virtual GRFs don't actually need to be
1341 * contiguous sets of GRFs. If we split, we'll end up with reduced
1342 * live intervals and better dead code elimination and coalescing.
1345 fs_visitor::split_virtual_grfs()
1347 int num_vars
= this->virtual_grf_count
;
1348 bool split_grf
[num_vars
];
1349 int new_virtual_grf
[num_vars
];
1351 /* Try to split anything > 0 sized. */
1352 for (int i
= 0; i
< num_vars
; i
++) {
1353 if (this->virtual_grf_sizes
[i
] != 1)
1354 split_grf
[i
] = true;
1356 split_grf
[i
] = false;
1360 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].file
== GRF
) {
1361 /* PLN opcodes rely on the delta_xy being contiguous. We only have to
1362 * check this for BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because prior to
1363 * Gen6, that was the only supported interpolation mode, and since Gen6,
1364 * delta_x and delta_y are in fixed hardware registers.
1366 split_grf
[this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
] =
1370 foreach_list(node
, &this->instructions
) {
1371 fs_inst
*inst
= (fs_inst
*)node
;
1373 /* If there's a SEND message that requires contiguous destination
1374 * registers, no splitting is allowed.
1376 if (inst
->regs_written
> 1) {
1377 split_grf
[inst
->dst
.reg
] = false;
1380 /* If we're sending from a GRF, don't split it, on the assumption that
1381 * the send is reading the whole thing.
1383 if (inst
->is_send_from_grf()) {
1384 split_grf
[inst
->src
[0].reg
] = false;
1388 /* Allocate new space for split regs. Note that the virtual
1389 * numbers will be contiguous.
1391 for (int i
= 0; i
< num_vars
; i
++) {
1393 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1394 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1395 int reg
= virtual_grf_alloc(1);
1396 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1399 this->virtual_grf_sizes
[i
] = 1;
1403 foreach_list(node
, &this->instructions
) {
1404 fs_inst
*inst
= (fs_inst
*)node
;
1406 if (inst
->dst
.file
== GRF
&&
1407 split_grf
[inst
->dst
.reg
] &&
1408 inst
->dst
.reg_offset
!= 0) {
1409 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1410 inst
->dst
.reg_offset
- 1);
1411 inst
->dst
.reg_offset
= 0;
1413 for (int i
= 0; i
< 3; i
++) {
1414 if (inst
->src
[i
].file
== GRF
&&
1415 split_grf
[inst
->src
[i
].reg
] &&
1416 inst
->src
[i
].reg_offset
!= 0) {
1417 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1418 inst
->src
[i
].reg_offset
- 1);
1419 inst
->src
[i
].reg_offset
= 0;
1423 this->live_intervals_valid
= false;
1427 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1429 * During code generation, we create tons of temporary variables, many of
1430 * which get immediately killed and are never used again. Yet, in later
1431 * optimization and analysis passes, such as compute_live_intervals, we need
1432 * to loop over all the virtual GRFs. Compacting them can save a lot of
1436 fs_visitor::compact_virtual_grfs()
1438 /* Mark which virtual GRFs are used, and count how many. */
1439 int remap_table
[this->virtual_grf_count
];
1440 memset(remap_table
, -1, sizeof(remap_table
));
1442 foreach_list(node
, &this->instructions
) {
1443 const fs_inst
*inst
= (const fs_inst
*) node
;
1445 if (inst
->dst
.file
== GRF
)
1446 remap_table
[inst
->dst
.reg
] = 0;
1448 for (int i
= 0; i
< 3; i
++) {
1449 if (inst
->src
[i
].file
== GRF
)
1450 remap_table
[inst
->src
[i
].reg
] = 0;
1454 /* In addition to registers used in instructions, fs_visitor keeps
1455 * direct references to certain special values which must be patched:
1457 fs_reg
*special
[] = {
1458 &frag_depth
, &pixel_x
, &pixel_y
, &pixel_w
, &wpos_w
, &dual_src_output
,
1459 &outputs
[0], &outputs
[1], &outputs
[2], &outputs
[3],
1460 &outputs
[4], &outputs
[5], &outputs
[6], &outputs
[7],
1461 &delta_x
[0], &delta_x
[1], &delta_x
[2],
1462 &delta_x
[3], &delta_x
[4], &delta_x
[5],
1463 &delta_y
[0], &delta_y
[1], &delta_y
[2],
1464 &delta_y
[3], &delta_y
[4], &delta_y
[5],
1466 STATIC_ASSERT(BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
== 6);
1467 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
== 8);
1469 /* Treat all special values as used, to be conservative */
1470 for (unsigned i
= 0; i
< ARRAY_SIZE(special
); i
++) {
1471 if (special
[i
]->file
== GRF
)
1472 remap_table
[special
[i
]->reg
] = 0;
1475 /* Compact the GRF arrays. */
1477 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
1478 if (remap_table
[i
] != -1) {
1479 remap_table
[i
] = new_index
;
1480 virtual_grf_sizes
[new_index
] = virtual_grf_sizes
[i
];
1481 if (live_intervals_valid
) {
1482 virtual_grf_use
[new_index
] = virtual_grf_use
[i
];
1483 virtual_grf_def
[new_index
] = virtual_grf_def
[i
];
1489 this->virtual_grf_count
= new_index
;
1491 /* Patch all the instructions to use the newly renumbered registers */
1492 foreach_list(node
, &this->instructions
) {
1493 fs_inst
*inst
= (fs_inst
*) node
;
1495 if (inst
->dst
.file
== GRF
)
1496 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
1498 for (int i
= 0; i
< 3; i
++) {
1499 if (inst
->src
[i
].file
== GRF
)
1500 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
1504 /* Patch all the references to special values */
1505 for (unsigned i
= 0; i
< ARRAY_SIZE(special
); i
++) {
1506 if (special
[i
]->file
== GRF
&& remap_table
[special
[i
]->reg
] != -1)
1507 special
[i
]->reg
= remap_table
[special
[i
]->reg
];
1512 fs_visitor::remove_dead_constants()
1514 if (dispatch_width
== 8) {
1515 this->params_remap
= ralloc_array(mem_ctx
, int, c
->prog_data
.nr_params
);
1517 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++)
1518 this->params_remap
[i
] = -1;
1520 /* Find which params are still in use. */
1521 foreach_list(node
, &this->instructions
) {
1522 fs_inst
*inst
= (fs_inst
*)node
;
1524 for (int i
= 0; i
< 3; i
++) {
1525 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1527 if (inst
->src
[i
].file
!= UNIFORM
)
1530 assert(constant_nr
< (int)c
->prog_data
.nr_params
);
1532 /* For now, set this to non-negative. We'll give it the
1533 * actual new number in a moment, in order to keep the
1534 * register numbers nicely ordered.
1536 this->params_remap
[constant_nr
] = 0;
1540 /* Figure out what the new numbers for the params will be. At some
1541 * point when we're doing uniform array access, we're going to want
1542 * to keep the distinction between .reg and .reg_offset, but for
1543 * now we don't care.
1545 unsigned int new_nr_params
= 0;
1546 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1547 if (this->params_remap
[i
] != -1) {
1548 this->params_remap
[i
] = new_nr_params
++;
1552 /* Update the list of params to be uploaded to match our new numbering. */
1553 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1554 int remapped
= this->params_remap
[i
];
1559 c
->prog_data
.param
[remapped
] = c
->prog_data
.param
[i
];
1562 c
->prog_data
.nr_params
= new_nr_params
;
1564 /* This should have been generated in the 8-wide pass already. */
1565 assert(this->params_remap
);
1568 /* Now do the renumbering of the shader to remove unused params. */
1569 foreach_list(node
, &this->instructions
) {
1570 fs_inst
*inst
= (fs_inst
*)node
;
1572 for (int i
= 0; i
< 3; i
++) {
1573 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1575 if (inst
->src
[i
].file
!= UNIFORM
)
1578 assert(this->params_remap
[constant_nr
] != -1);
1579 inst
->src
[i
].reg
= this->params_remap
[constant_nr
];
1580 inst
->src
[i
].reg_offset
= 0;
1588 * Implements array access of uniforms by inserting a
1589 * PULL_CONSTANT_LOAD instruction.
1591 * Unlike temporary GRF array access (where we don't support it due to
1592 * the difficulty of doing relative addressing on instruction
1593 * destinations), we could potentially do array access of uniforms
1594 * that were loaded in GRF space as push constants. In real-world
1595 * usage we've seen, though, the arrays being used are always larger
1596 * than we could load as push constants, so just always move all
1597 * uniform array access out to a pull constant buffer.
1600 fs_visitor::move_uniform_array_access_to_pull_constants()
1602 int pull_constant_loc
[c
->prog_data
.nr_params
];
1604 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1605 pull_constant_loc
[i
] = -1;
1608 /* Walk through and find array access of uniforms. Put a copy of that
1609 * uniform in the pull constant buffer.
1611 * Note that we don't move constant-indexed accesses to arrays. No
1612 * testing has been done of the performance impact of this choice.
1614 foreach_list_safe(node
, &this->instructions
) {
1615 fs_inst
*inst
= (fs_inst
*)node
;
1617 for (int i
= 0 ; i
< 3; i
++) {
1618 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
1621 int uniform
= inst
->src
[i
].reg
;
1623 /* If this array isn't already present in the pull constant buffer,
1626 if (pull_constant_loc
[uniform
] == -1) {
1627 const float **values
= &c
->prog_data
.param
[uniform
];
1629 pull_constant_loc
[uniform
] = c
->prog_data
.nr_pull_params
;
1631 assert(param_size
[uniform
]);
1633 for (int j
= 0; j
< param_size
[uniform
]; j
++) {
1634 c
->prog_data
.pull_param
[c
->prog_data
.nr_pull_params
++] =
1639 /* Set up the annotation tracking for new generated instructions. */
1641 current_annotation
= inst
->annotation
;
1643 fs_reg surf_index
= fs_reg((unsigned)SURF_INDEX_FRAG_CONST_BUFFER
);
1644 fs_reg temp
= fs_reg(this, glsl_type::float_type
);
1645 exec_list list
= VARYING_PULL_CONSTANT_LOAD(temp
,
1647 *inst
->src
[i
].reladdr
,
1648 pull_constant_loc
[uniform
] +
1649 inst
->src
[i
].reg_offset
);
1650 inst
->insert_before(&list
);
1652 inst
->src
[i
].file
= temp
.file
;
1653 inst
->src
[i
].reg
= temp
.reg
;
1654 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
1655 inst
->src
[i
].reladdr
= NULL
;
1661 * Choose accesses from the UNIFORM file to demote to using the pull
1664 * We allow a fragment shader to have more than the specified minimum
1665 * maximum number of fragment shader uniform components (64). If
1666 * there are too many of these, they'd fill up all of register space.
1667 * So, this will push some of them out to the pull constant buffer and
1668 * update the program to load them.
1671 fs_visitor::setup_pull_constants()
1673 /* Only allow 16 registers (128 uniform components) as push constants. */
1674 unsigned int max_uniform_components
= 16 * 8;
1675 if (c
->prog_data
.nr_params
<= max_uniform_components
)
1678 if (dispatch_width
== 16) {
1679 fail("Pull constants not supported in 16-wide\n");
1683 /* Just demote the end of the list. We could probably do better
1684 * here, demoting things that are rarely used in the program first.
1686 unsigned int pull_uniform_base
= max_uniform_components
;
1688 int pull_constant_loc
[c
->prog_data
.nr_params
];
1689 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1690 if (i
< pull_uniform_base
) {
1691 pull_constant_loc
[i
] = -1;
1693 pull_constant_loc
[i
] = -1;
1694 /* If our constant is already being uploaded for reladdr purposes,
1697 for (unsigned int j
= 0; j
< c
->prog_data
.nr_pull_params
; j
++) {
1698 if (c
->prog_data
.pull_param
[j
] == c
->prog_data
.param
[i
]) {
1699 pull_constant_loc
[i
] = j
;
1703 if (pull_constant_loc
[i
] == -1) {
1704 int pull_index
= c
->prog_data
.nr_pull_params
++;
1705 c
->prog_data
.pull_param
[pull_index
] = c
->prog_data
.param
[i
];
1706 pull_constant_loc
[i
] = pull_index
;;
1710 c
->prog_data
.nr_params
= pull_uniform_base
;
1712 foreach_list(node
, &this->instructions
) {
1713 fs_inst
*inst
= (fs_inst
*)node
;
1715 for (int i
= 0; i
< 3; i
++) {
1716 if (inst
->src
[i
].file
!= UNIFORM
)
1719 int pull_index
= pull_constant_loc
[inst
->src
[i
].reg
+
1720 inst
->src
[i
].reg_offset
];
1721 if (pull_index
== -1)
1724 assert(!inst
->src
[i
].reladdr
);
1726 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
1727 fs_reg index
= fs_reg((unsigned)SURF_INDEX_FRAG_CONST_BUFFER
);
1728 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
1730 new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
1731 dst
, index
, offset
);
1732 pull
->ir
= inst
->ir
;
1733 pull
->annotation
= inst
->annotation
;
1735 inst
->insert_before(pull
);
1737 inst
->src
[i
].file
= GRF
;
1738 inst
->src
[i
].reg
= dst
.reg
;
1739 inst
->src
[i
].reg_offset
= 0;
1740 inst
->src
[i
].smear
= pull_index
& 3;
1746 fs_visitor::opt_algebraic()
1748 bool progress
= false;
1750 foreach_list(node
, &this->instructions
) {
1751 fs_inst
*inst
= (fs_inst
*)node
;
1753 switch (inst
->opcode
) {
1754 case BRW_OPCODE_MUL
:
1755 if (inst
->src
[1].file
!= IMM
)
1759 if (inst
->src
[1].is_one()) {
1760 inst
->opcode
= BRW_OPCODE_MOV
;
1761 inst
->src
[1] = reg_undef
;
1767 if (inst
->src
[1].is_zero()) {
1768 inst
->opcode
= BRW_OPCODE_MOV
;
1769 inst
->src
[0] = inst
->src
[1];
1770 inst
->src
[1] = reg_undef
;
1776 case BRW_OPCODE_ADD
:
1777 if (inst
->src
[1].file
!= IMM
)
1781 if (inst
->src
[1].is_zero()) {
1782 inst
->opcode
= BRW_OPCODE_MOV
;
1783 inst
->src
[1] = reg_undef
;
1797 * Must be called after calculate_live_intervales() to remove unused
1798 * writes to registers -- register allocation will fail otherwise
1799 * because something deffed but not used won't be considered to
1800 * interfere with other regs.
1803 fs_visitor::dead_code_eliminate()
1805 bool progress
= false;
1808 calculate_live_intervals();
1810 foreach_list_safe(node
, &this->instructions
) {
1811 fs_inst
*inst
= (fs_inst
*)node
;
1813 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
1822 live_intervals_valid
= false;
1827 struct dead_code_hash_key
1834 dead_code_hash_compare(const void *a
, const void *b
)
1836 return memcmp(a
, b
, sizeof(struct dead_code_hash_key
)) == 0;
1840 clear_dead_code_hash(struct hash_table
*ht
)
1842 struct hash_entry
*entry
;
1844 hash_table_foreach(ht
, entry
) {
1845 _mesa_hash_table_remove(ht
, entry
);
1850 insert_dead_code_hash(struct hash_table
*ht
,
1851 int vgrf
, int reg_offset
, fs_inst
*inst
)
1853 /* We don't bother freeing keys, because they'll be GCed with the ht. */
1854 struct dead_code_hash_key
*key
= ralloc(ht
, struct dead_code_hash_key
);
1857 key
->reg_offset
= reg_offset
;
1859 _mesa_hash_table_insert(ht
, _mesa_hash_data(key
, sizeof(*key
)), key
, inst
);
1862 static struct hash_entry
*
1863 get_dead_code_hash_entry(struct hash_table
*ht
, int vgrf
, int reg_offset
)
1865 struct dead_code_hash_key key
;
1868 key
.reg_offset
= reg_offset
;
1870 return _mesa_hash_table_search(ht
, _mesa_hash_data(&key
, sizeof(key
)), &key
);
1874 remove_dead_code_hash(struct hash_table
*ht
,
1875 int vgrf
, int reg_offset
)
1877 struct hash_entry
*entry
= get_dead_code_hash_entry(ht
, vgrf
, reg_offset
);
1881 _mesa_hash_table_remove(ht
, entry
);
1885 * Walks basic blocks, removing any regs that are written but not read before
1888 * The dead_code_eliminate() function implements a global dead code
1889 * elimination, but it only handles the removing the last write to a register
1890 * if it's never read. This one can handle intermediate writes, but only
1891 * within a basic block.
1894 fs_visitor::dead_code_eliminate_local()
1896 struct hash_table
*ht
;
1897 bool progress
= false;
1899 ht
= _mesa_hash_table_create(mem_ctx
, dead_code_hash_compare
);
1901 foreach_list_safe(node
, &this->instructions
) {
1902 fs_inst
*inst
= (fs_inst
*)node
;
1904 /* At a basic block, empty the HT since we don't understand dataflow
1907 if (inst
->is_control_flow()) {
1908 clear_dead_code_hash(ht
);
1912 /* Clear the HT of any instructions that got read. */
1913 for (int i
= 0; i
< 3; i
++) {
1914 fs_reg src
= inst
->src
[i
];
1915 if (src
.file
!= GRF
)
1919 if (inst
->is_send_from_grf())
1920 read
= virtual_grf_sizes
[src
.reg
] - src
.reg_offset
;
1922 for (int reg_offset
= src
.reg_offset
;
1923 reg_offset
< src
.reg_offset
+ read
;
1925 remove_dead_code_hash(ht
, src
.reg
, reg_offset
);
1929 /* Add any update of a GRF to the HT, removing a previous write if it
1932 if (inst
->dst
.file
== GRF
) {
1933 if (inst
->regs_written
> 1) {
1934 /* We don't know how to trim channels from an instruction's
1935 * writes, so we can't incrementally remove unread channels from
1936 * it. Just remove whatever it overwrites from the table
1938 for (int i
= 0; i
< inst
->regs_written
; i
++) {
1939 remove_dead_code_hash(ht
,
1941 inst
->dst
.reg_offset
+ i
);
1944 struct hash_entry
*entry
=
1945 get_dead_code_hash_entry(ht
, inst
->dst
.reg
,
1946 inst
->dst
.reg_offset
);
1948 if (inst
->is_partial_write()) {
1949 /* For a partial write, we can't remove any previous dead code
1950 * candidate, since we're just modifying their result, but we can
1951 * be dead code eliminiated ourselves.
1956 insert_dead_code_hash(ht
, inst
->dst
.reg
, inst
->dst
.reg_offset
,
1961 /* We're completely updating a channel, and there was a
1962 * previous write to the channel that wasn't read. Kill it!
1964 fs_inst
*inst
= (fs_inst
*)entry
->data
;
1967 _mesa_hash_table_remove(ht
, entry
);
1970 insert_dead_code_hash(ht
, inst
->dst
.reg
, inst
->dst
.reg_offset
,
1977 _mesa_hash_table_destroy(ht
, NULL
);
1980 live_intervals_valid
= false;
1986 * Implements a second type of register coalescing: This one checks if
1987 * the two regs involved in a raw move don't interfere, in which case
1988 * they can both by stored in the same place and the MOV removed.
1991 fs_visitor::register_coalesce_2()
1993 bool progress
= false;
1995 calculate_live_intervals();
1997 foreach_list_safe(node
, &this->instructions
) {
1998 fs_inst
*inst
= (fs_inst
*)node
;
2000 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2003 inst
->src
[0].file
!= GRF
||
2004 inst
->src
[0].negate
||
2006 inst
->src
[0].smear
!= -1 ||
2007 inst
->dst
.file
!= GRF
||
2008 inst
->dst
.type
!= inst
->src
[0].type
||
2009 virtual_grf_sizes
[inst
->src
[0].reg
] != 1 ||
2010 virtual_grf_interferes(inst
->dst
.reg
, inst
->src
[0].reg
)) {
2014 int reg_from
= inst
->src
[0].reg
;
2015 assert(inst
->src
[0].reg_offset
== 0);
2016 int reg_to
= inst
->dst
.reg
;
2017 int reg_to_offset
= inst
->dst
.reg_offset
;
2019 foreach_list(node
, &this->instructions
) {
2020 fs_inst
*scan_inst
= (fs_inst
*)node
;
2022 if (scan_inst
->dst
.file
== GRF
&&
2023 scan_inst
->dst
.reg
== reg_from
) {
2024 scan_inst
->dst
.reg
= reg_to
;
2025 scan_inst
->dst
.reg_offset
= reg_to_offset
;
2027 for (int i
= 0; i
< 3; i
++) {
2028 if (scan_inst
->src
[i
].file
== GRF
&&
2029 scan_inst
->src
[i
].reg
== reg_from
) {
2030 scan_inst
->src
[i
].reg
= reg_to
;
2031 scan_inst
->src
[i
].reg_offset
= reg_to_offset
;
2038 /* We don't need to recalculate live intervals inside the loop despite
2039 * flagging live_intervals_valid because we only use live intervals for
2040 * the interferes test, and we must have had a situation where the
2051 * Some register R that might get coalesced with one of these two could
2052 * only be referencing "to", otherwise "from"'s range would have been
2053 * longer. R's range could also only start at the end of "to" or later,
2054 * otherwise it will conflict with "to" when we try to coalesce "to"
2057 live_intervals_valid
= false;
2067 fs_visitor::register_coalesce()
2069 bool progress
= false;
2073 foreach_list_safe(node
, &this->instructions
) {
2074 fs_inst
*inst
= (fs_inst
*)node
;
2076 /* Make sure that we dominate the instructions we're going to
2077 * scan for interfering with our coalescing, or we won't have
2078 * scanned enough to see if anything interferes with our
2079 * coalescing. We don't dominate the following instructions if
2080 * we're in a loop or an if block.
2082 switch (inst
->opcode
) {
2086 case BRW_OPCODE_WHILE
:
2092 case BRW_OPCODE_ENDIF
:
2098 if (loop_depth
|| if_depth
)
2101 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2104 inst
->dst
.file
!= GRF
|| (inst
->src
[0].file
!= GRF
&&
2105 inst
->src
[0].file
!= UNIFORM
)||
2106 inst
->dst
.type
!= inst
->src
[0].type
)
2109 bool has_source_modifiers
= (inst
->src
[0].abs
||
2110 inst
->src
[0].negate
||
2111 inst
->src
[0].smear
!= -1 ||
2112 inst
->src
[0].file
== UNIFORM
);
2114 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
2115 * them: check for no writes to either one until the exit of the
2118 bool interfered
= false;
2120 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->next
;
2121 !scan_inst
->is_tail_sentinel();
2122 scan_inst
= (fs_inst
*)scan_inst
->next
) {
2123 if (scan_inst
->dst
.file
== GRF
) {
2124 if (scan_inst
->overwrites_reg(inst
->dst
) ||
2125 scan_inst
->overwrites_reg(inst
->src
[0])) {
2131 /* The gen6 MATH instruction can't handle source modifiers or
2132 * unusual register regions, so avoid coalescing those for
2133 * now. We should do something more specific.
2135 if (has_source_modifiers
&& !can_do_source_mods(scan_inst
)) {
2140 /* The accumulator result appears to get used for the
2141 * conditional modifier generation. When negating a UD
2142 * value, there is a 33rd bit generated for the sign in the
2143 * accumulator value, so now you can't check, for example,
2144 * equality with a 32-bit value. See piglit fs-op-neg-uint.
2146 if (scan_inst
->conditional_mod
&&
2147 inst
->src
[0].negate
&&
2148 inst
->src
[0].type
== BRW_REGISTER_TYPE_UD
) {
2157 /* Rewrite the later usage to point at the source of the move to
2160 for (fs_inst
*scan_inst
= inst
;
2161 !scan_inst
->is_tail_sentinel();
2162 scan_inst
= (fs_inst
*)scan_inst
->next
) {
2163 for (int i
= 0; i
< 3; i
++) {
2164 if (scan_inst
->src
[i
].file
== GRF
&&
2165 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
2166 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
2167 fs_reg new_src
= inst
->src
[0];
2168 if (scan_inst
->src
[i
].abs
) {
2172 new_src
.negate
^= scan_inst
->src
[i
].negate
;
2173 scan_inst
->src
[i
] = new_src
;
2183 live_intervals_valid
= false;
2190 fs_visitor::compute_to_mrf()
2192 bool progress
= false;
2195 calculate_live_intervals();
2197 foreach_list_safe(node
, &this->instructions
) {
2198 fs_inst
*inst
= (fs_inst
*)node
;
2203 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2205 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2206 inst
->dst
.type
!= inst
->src
[0].type
||
2207 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
2210 /* Work out which hardware MRF registers are written by this
2213 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2215 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2216 mrf_high
= mrf_low
+ 4;
2217 } else if (dispatch_width
== 16 &&
2218 (!inst
->force_uncompressed
&& !inst
->force_sechalf
)) {
2219 mrf_high
= mrf_low
+ 1;
2224 /* Can't compute-to-MRF this GRF if someone else was going to
2227 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
2230 /* Found a move of a GRF to a MRF. Let's see if we can go
2231 * rewrite the thing that made this GRF to write into the MRF.
2234 for (scan_inst
= (fs_inst
*)inst
->prev
;
2235 scan_inst
->prev
!= NULL
;
2236 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2237 if (scan_inst
->dst
.file
== GRF
&&
2238 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2239 /* Found the last thing to write our reg we want to turn
2240 * into a compute-to-MRF.
2243 /* If this one instruction didn't populate all the
2244 * channels, bail. We might be able to rewrite everything
2245 * that writes that reg, but it would require smarter
2246 * tracking to delay the rewriting until complete success.
2248 if (scan_inst
->is_partial_write())
2251 /* Things returning more than one register would need us to
2252 * understand coalescing out more than one MOV at a time.
2254 if (scan_inst
->regs_written
> 1)
2257 /* SEND instructions can't have MRF as a destination. */
2258 if (scan_inst
->mlen
)
2261 if (intel
->gen
== 6) {
2262 /* gen6 math instructions must have the destination be
2263 * GRF, so no compute-to-MRF for them.
2265 if (scan_inst
->is_math()) {
2270 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2271 /* Found the creator of our MRF's source value. */
2272 scan_inst
->dst
.file
= MRF
;
2273 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2274 scan_inst
->saturate
|= inst
->saturate
;
2281 /* We don't handle control flow here. Most computation of
2282 * values that end up in MRFs are shortly before the MRF
2285 if (scan_inst
->is_control_flow() && scan_inst
->opcode
!= BRW_OPCODE_IF
)
2288 /* You can't read from an MRF, so if someone else reads our
2289 * MRF's source GRF that we wanted to rewrite, that stops us.
2291 bool interfered
= false;
2292 for (int i
= 0; i
< 3; i
++) {
2293 if (scan_inst
->src
[i
].file
== GRF
&&
2294 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2295 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2302 if (scan_inst
->dst
.file
== MRF
) {
2303 /* If somebody else writes our MRF here, we can't
2304 * compute-to-MRF before that.
2306 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2309 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2310 scan_mrf_high
= scan_mrf_low
+ 4;
2311 } else if (dispatch_width
== 16 &&
2312 (!scan_inst
->force_uncompressed
&&
2313 !scan_inst
->force_sechalf
)) {
2314 scan_mrf_high
= scan_mrf_low
+ 1;
2316 scan_mrf_high
= scan_mrf_low
;
2319 if (mrf_low
== scan_mrf_low
||
2320 mrf_low
== scan_mrf_high
||
2321 mrf_high
== scan_mrf_low
||
2322 mrf_high
== scan_mrf_high
) {
2327 if (scan_inst
->mlen
> 0) {
2328 /* Found a SEND instruction, which means that there are
2329 * live values in MRFs from base_mrf to base_mrf +
2330 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2333 if (mrf_low
>= scan_inst
->base_mrf
&&
2334 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2337 if (mrf_high
>= scan_inst
->base_mrf
&&
2338 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2346 live_intervals_valid
= false;
2352 * Walks through basic blocks, looking for repeated MRF writes and
2353 * removing the later ones.
2356 fs_visitor::remove_duplicate_mrf_writes()
2358 fs_inst
*last_mrf_move
[16];
2359 bool progress
= false;
2361 /* Need to update the MRF tracking for compressed instructions. */
2362 if (dispatch_width
== 16)
2365 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2367 foreach_list_safe(node
, &this->instructions
) {
2368 fs_inst
*inst
= (fs_inst
*)node
;
2370 if (inst
->is_control_flow()) {
2371 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2374 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2375 inst
->dst
.file
== MRF
) {
2376 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2377 if (prev_inst
&& inst
->equals(prev_inst
)) {
2384 /* Clear out the last-write records for MRFs that were overwritten. */
2385 if (inst
->dst
.file
== MRF
) {
2386 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2389 if (inst
->mlen
> 0) {
2390 /* Found a SEND instruction, which will include two or fewer
2391 * implied MRF writes. We could do better here.
2393 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2394 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2398 /* Clear out any MRF move records whose sources got overwritten. */
2399 if (inst
->dst
.file
== GRF
) {
2400 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
2401 if (last_mrf_move
[i
] &&
2402 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2403 last_mrf_move
[i
] = NULL
;
2408 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2409 inst
->dst
.file
== MRF
&&
2410 inst
->src
[0].file
== GRF
&&
2412 last_mrf_move
[inst
->dst
.reg
] = inst
;
2417 live_intervals_valid
= false;
2423 clear_deps_for_inst_src(fs_inst
*inst
, int dispatch_width
, bool *deps
,
2424 int first_grf
, int grf_len
)
2426 bool inst_16wide
= (dispatch_width
> 8 &&
2427 !inst
->force_uncompressed
&&
2428 !inst
->force_sechalf
);
2430 /* Clear the flag for registers that actually got read (as expected). */
2431 for (int i
= 0; i
< 3; i
++) {
2433 if (inst
->src
[i
].file
== GRF
) {
2434 grf
= inst
->src
[i
].reg
;
2435 } else if (inst
->src
[i
].file
== FIXED_HW_REG
&&
2436 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
2437 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
2442 if (grf
>= first_grf
&&
2443 grf
< first_grf
+ grf_len
) {
2444 deps
[grf
- first_grf
] = false;
2446 deps
[grf
- first_grf
+ 1] = false;
2452 * Implements this workaround for the original 965:
2454 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2455 * check for post destination dependencies on this instruction, software
2456 * must ensure that there is no destination hazard for the case of ‘write
2457 * followed by a posted write’ shown in the following example.
2460 * 2. send r3.xy <rest of send instruction>
2463 * Due to no post-destination dependency check on the ‘send’, the above
2464 * code sequence could have two instructions (1 and 2) in flight at the
2465 * same time that both consider ‘r3’ as the target of their final writes.
2468 fs_visitor::insert_gen4_pre_send_dependency_workarounds(fs_inst
*inst
)
2470 int reg_size
= dispatch_width
/ 8;
2471 int write_len
= inst
->regs_written
* reg_size
;
2472 int first_write_grf
= inst
->dst
.reg
;
2473 bool needs_dep
[BRW_MAX_MRF
];
2474 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2476 memset(needs_dep
, false, sizeof(needs_dep
));
2477 memset(needs_dep
, true, write_len
);
2479 clear_deps_for_inst_src(inst
, dispatch_width
,
2480 needs_dep
, first_write_grf
, write_len
);
2482 /* Walk backwards looking for writes to registers we're writing which
2483 * aren't read since being written. If we hit the start of the program,
2484 * we assume that there are no outstanding dependencies on entry to the
2487 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->prev
;
2489 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2491 /* If we hit control flow, assume that there *are* outstanding
2492 * dependencies, and force their cleanup before our instruction.
2494 if (scan_inst
->is_control_flow()) {
2495 for (int i
= 0; i
< write_len
; i
++) {
2497 inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2503 bool scan_inst_16wide
= (dispatch_width
> 8 &&
2504 !scan_inst
->force_uncompressed
&&
2505 !scan_inst
->force_sechalf
);
2507 /* We insert our reads as late as possible on the assumption that any
2508 * instruction but a MOV that might have left us an outstanding
2509 * dependency has more latency than a MOV.
2511 if (scan_inst
->dst
.file
== GRF
) {
2512 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2513 int reg
= scan_inst
->dst
.reg
+ i
* reg_size
;
2515 if (reg
>= first_write_grf
&&
2516 reg
< first_write_grf
+ write_len
&&
2517 needs_dep
[reg
- first_write_grf
]) {
2518 inst
->insert_before(DEP_RESOLVE_MOV(reg
));
2519 needs_dep
[reg
- first_write_grf
] = false;
2520 if (scan_inst_16wide
)
2521 needs_dep
[reg
- first_write_grf
+ 1] = false;
2526 /* Clear the flag for registers that actually got read (as expected). */
2527 clear_deps_for_inst_src(scan_inst
, dispatch_width
,
2528 needs_dep
, first_write_grf
, write_len
);
2530 /* Continue the loop only if we haven't resolved all the dependencies */
2532 for (i
= 0; i
< write_len
; i
++) {
2542 * Implements this workaround for the original 965:
2544 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2545 * used as a destination register until after it has been sourced by an
2546 * instruction with a different destination register.
2549 fs_visitor::insert_gen4_post_send_dependency_workarounds(fs_inst
*inst
)
2551 int write_len
= inst
->regs_written
* dispatch_width
/ 8;
2552 int first_write_grf
= inst
->dst
.reg
;
2553 bool needs_dep
[BRW_MAX_MRF
];
2554 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2556 memset(needs_dep
, false, sizeof(needs_dep
));
2557 memset(needs_dep
, true, write_len
);
2558 /* Walk forwards looking for writes to registers we're writing which aren't
2559 * read before being written.
2561 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->next
;
2562 !scan_inst
->is_tail_sentinel();
2563 scan_inst
= (fs_inst
*)scan_inst
->next
) {
2564 /* If we hit control flow, force resolve all remaining dependencies. */
2565 if (scan_inst
->is_control_flow()) {
2566 for (int i
= 0; i
< write_len
; i
++) {
2568 scan_inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2573 /* Clear the flag for registers that actually got read (as expected). */
2574 clear_deps_for_inst_src(scan_inst
, dispatch_width
,
2575 needs_dep
, first_write_grf
, write_len
);
2577 /* We insert our reads as late as possible since they're reading the
2578 * result of a SEND, which has massive latency.
2580 if (scan_inst
->dst
.file
== GRF
&&
2581 scan_inst
->dst
.reg
>= first_write_grf
&&
2582 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
2583 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
2584 scan_inst
->insert_before(DEP_RESOLVE_MOV(scan_inst
->dst
.reg
));
2585 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
2588 /* Continue the loop only if we haven't resolved all the dependencies */
2590 for (i
= 0; i
< write_len
; i
++) {
2598 /* If we hit the end of the program, resolve all remaining dependencies out
2601 fs_inst
*last_inst
= (fs_inst
*)this->instructions
.get_tail();
2602 assert(last_inst
->eot
);
2603 for (int i
= 0; i
< write_len
; i
++) {
2605 last_inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2610 fs_visitor::insert_gen4_send_dependency_workarounds()
2612 if (intel
->gen
!= 4 || intel
->is_g4x
)
2615 /* Note that we're done with register allocation, so GRF fs_regs always
2616 * have a .reg_offset of 0.
2619 foreach_list_safe(node
, &this->instructions
) {
2620 fs_inst
*inst
= (fs_inst
*)node
;
2622 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
2623 insert_gen4_pre_send_dependency_workarounds(inst
);
2624 insert_gen4_post_send_dependency_workarounds(inst
);
2630 * Turns the generic expression-style uniform pull constant load instruction
2631 * into a hardware-specific series of instructions for loading a pull
2634 * The expression style allows the CSE pass before this to optimize out
2635 * repeated loads from the same offset, and gives the pre-register-allocation
2636 * scheduling full flexibility, while the conversion to native instructions
2637 * allows the post-register-allocation scheduler the best information
2640 * Note that execution masking for setting up pull constant loads is special:
2641 * the channels that need to be written are unrelated to the current execution
2642 * mask, since a later instruction will use one of the result channels as a
2643 * source operand for all 8 or 16 of its channels.
2646 fs_visitor::lower_uniform_pull_constant_loads()
2648 foreach_list(node
, &this->instructions
) {
2649 fs_inst
*inst
= (fs_inst
*)node
;
2651 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
2654 if (intel
->gen
>= 7) {
2655 /* The offset arg before was a vec4-aligned byte offset. We need to
2656 * turn it into a dword offset.
2658 fs_reg const_offset_reg
= inst
->src
[1];
2659 assert(const_offset_reg
.file
== IMM
&&
2660 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
2661 const_offset_reg
.imm
.u
/= 4;
2662 fs_reg payload
= fs_reg(this, glsl_type::uint_type
);
2664 /* This is actually going to be a MOV, but since only the first dword
2665 * is accessed, we have a special opcode to do just that one. Note
2666 * that this needs to be an operation that will be considered a def
2667 * by live variable analysis, or register allocation will explode.
2669 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
2670 payload
, const_offset_reg
);
2671 setup
->force_writemask_all
= true;
2673 setup
->ir
= inst
->ir
;
2674 setup
->annotation
= inst
->annotation
;
2675 inst
->insert_before(setup
);
2677 /* Similarly, this will only populate the first 4 channels of the
2678 * result register (since we only use smear values from 0-3), but we
2679 * don't tell the optimizer.
2681 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
2682 inst
->src
[1] = payload
;
2684 this->live_intervals_valid
= false;
2686 /* Before register allocation, we didn't tell the scheduler about the
2687 * MRF we use. We know it's safe to use this MRF because nothing
2688 * else does except for register spill/unspill, which generates and
2689 * uses its MRF within a single IR instruction.
2691 inst
->base_mrf
= 14;
2698 fs_visitor::dump_instruction(fs_inst
*inst
)
2700 if (inst
->predicate
) {
2701 printf("(%cf0.%d) ",
2702 inst
->predicate_inverse
? '-' : '+',
2706 printf("%s", brw_instruction_name(inst
->opcode
));
2709 if (inst
->conditional_mod
) {
2711 if (!inst
->predicate
&&
2712 (intel
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
2713 inst
->opcode
!= BRW_OPCODE_IF
&&
2714 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
2715 printf(".f0.%d\n", inst
->flag_subreg
);
2721 switch (inst
->dst
.file
) {
2723 printf("vgrf%d", inst
->dst
.reg
);
2724 if (inst
->dst
.reg_offset
)
2725 printf("+%d", inst
->dst
.reg_offset
);
2728 printf("m%d", inst
->dst
.reg
);
2734 printf("***u%d***", inst
->dst
.reg
);
2742 for (int i
= 0; i
< 3; i
++) {
2743 if (inst
->src
[i
].negate
)
2745 if (inst
->src
[i
].abs
)
2747 switch (inst
->src
[i
].file
) {
2749 printf("vgrf%d", inst
->src
[i
].reg
);
2750 if (inst
->src
[i
].reg_offset
)
2751 printf("+%d", inst
->src
[i
].reg_offset
);
2754 printf("***m%d***", inst
->src
[i
].reg
);
2757 printf("u%d", inst
->src
[i
].reg
);
2758 if (inst
->src
[i
].reg_offset
)
2759 printf(".%d", inst
->src
[i
].reg_offset
);
2765 switch (inst
->src
[i
].type
) {
2766 case BRW_REGISTER_TYPE_F
:
2767 printf("%ff", inst
->src
[i
].imm
.f
);
2769 case BRW_REGISTER_TYPE_D
:
2770 printf("%dd", inst
->src
[i
].imm
.i
);
2772 case BRW_REGISTER_TYPE_UD
:
2773 printf("%uu", inst
->src
[i
].imm
.u
);
2784 if (inst
->src
[i
].abs
)
2793 if (inst
->force_uncompressed
)
2796 if (inst
->force_sechalf
)
2803 fs_visitor::dump_instructions()
2806 foreach_list(node
, &this->instructions
) {
2807 fs_inst
*inst
= (fs_inst
*)node
;
2808 printf("%d: ", ip
++);
2809 dump_instruction(inst
);
2814 * Possibly returns an instruction that set up @param reg.
2816 * Sometimes we want to take the result of some expression/variable
2817 * dereference tree and rewrite the instruction generating the result
2818 * of the tree. When processing the tree, we know that the
2819 * instructions generated are all writing temporaries that are dead
2820 * outside of this tree. So, if we have some instructions that write
2821 * a temporary, we're free to point that temp write somewhere else.
2823 * Note that this doesn't guarantee that the instruction generated
2824 * only reg -- it might be the size=4 destination of a texture instruction.
2827 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
2832 end
->is_partial_write() ||
2834 !reg
.equals(end
->dst
)) {
2842 fs_visitor::setup_payload_gen6()
2844 struct intel_context
*intel
= &brw
->intel
;
2846 (fp
->Base
.InputsRead
& (1 << VARYING_SLOT_POS
)) != 0;
2847 unsigned barycentric_interp_modes
= c
->prog_data
.barycentric_interp_modes
;
2849 assert(intel
->gen
>= 6);
2851 /* R0-1: masks, pixel X/Y coordinates. */
2852 c
->nr_payload_regs
= 2;
2853 /* R2: only for 32-pixel dispatch.*/
2855 /* R3-26: barycentric interpolation coordinates. These appear in the
2856 * same order that they appear in the brw_wm_barycentric_interp_mode
2857 * enum. Each set of coordinates occupies 2 registers if dispatch width
2858 * == 8 and 4 registers if dispatch width == 16. Coordinates only
2859 * appear if they were enabled using the "Barycentric Interpolation
2860 * Mode" bits in WM_STATE.
2862 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
2863 if (barycentric_interp_modes
& (1 << i
)) {
2864 c
->barycentric_coord_reg
[i
] = c
->nr_payload_regs
;
2865 c
->nr_payload_regs
+= 2;
2866 if (dispatch_width
== 16) {
2867 c
->nr_payload_regs
+= 2;
2872 /* R27: interpolated depth if uses source depth */
2874 c
->source_depth_reg
= c
->nr_payload_regs
;
2875 c
->nr_payload_regs
++;
2876 if (dispatch_width
== 16) {
2877 /* R28: interpolated depth if not 8-wide. */
2878 c
->nr_payload_regs
++;
2881 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
2883 c
->source_w_reg
= c
->nr_payload_regs
;
2884 c
->nr_payload_regs
++;
2885 if (dispatch_width
== 16) {
2886 /* R30: interpolated W if not 8-wide. */
2887 c
->nr_payload_regs
++;
2890 /* R31: MSAA position offsets. */
2891 /* R32-: bary for 32-pixel. */
2892 /* R58-59: interp W for 32-pixel. */
2894 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
2895 c
->source_depth_to_render_target
= true;
2902 sanity_param_count
= fp
->Base
.Parameters
->NumParameters
;
2903 uint32_t orig_nr_params
= c
->prog_data
.nr_params
;
2905 if (intel
->gen
>= 6)
2906 setup_payload_gen6();
2908 setup_payload_gen4();
2913 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2914 emit_shader_time_begin();
2916 calculate_urb_setup();
2918 emit_interpolation_setup_gen4();
2920 emit_interpolation_setup_gen6();
2922 /* We handle discards by keeping track of the still-live pixels in f0.1.
2923 * Initialize it with the dispatched pixels.
2926 fs_inst
*discard_init
= emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
2927 discard_init
->flag_subreg
= 1;
2930 /* Generate FS IR for main(). (the visitor only descends into
2931 * functions called "main").
2934 foreach_list(node
, &*shader
->ir
) {
2935 ir_instruction
*ir
= (ir_instruction
*)node
;
2937 this->result
= reg_undef
;
2941 emit_fragment_program_code();
2947 emit(FS_OPCODE_PLACEHOLDER_HALT
);
2951 split_virtual_grfs();
2953 move_uniform_array_access_to_pull_constants();
2954 setup_pull_constants();
2960 compact_virtual_grfs();
2962 progress
= remove_duplicate_mrf_writes() || progress
;
2964 progress
= opt_algebraic() || progress
;
2965 progress
= opt_cse() || progress
;
2966 progress
= opt_copy_propagate() || progress
;
2967 progress
= dead_code_eliminate() || progress
;
2968 progress
= dead_code_eliminate_local() || progress
;
2969 progress
= register_coalesce() || progress
;
2970 progress
= register_coalesce_2() || progress
;
2971 progress
= compute_to_mrf() || progress
;
2974 remove_dead_constants();
2976 schedule_instructions(false);
2978 lower_uniform_pull_constant_loads();
2980 assign_curb_setup();
2984 /* Debug of register spilling: Go spill everything. */
2985 for (int i
= 0; i
< virtual_grf_count
; i
++) {
2991 assign_regs_trivial();
2993 while (!assign_regs()) {
2999 assert(force_uncompressed_stack
== 0);
3000 assert(force_sechalf_stack
== 0);
3002 /* This must come after all optimization and register allocation, since
3003 * it inserts dead code that happens to have side effects, and it does
3004 * so based on the actual physical registers in use.
3006 insert_gen4_send_dependency_workarounds();
3011 schedule_instructions(true);
3013 if (dispatch_width
== 8) {
3014 c
->prog_data
.reg_blocks
= brw_register_blocks(grf_used
);
3016 c
->prog_data
.reg_blocks_16
= brw_register_blocks(grf_used
);
3018 /* Make sure we didn't try to sneak in an extra uniform */
3019 assert(orig_nr_params
== c
->prog_data
.nr_params
);
3020 (void) orig_nr_params
;
3023 /* If any state parameters were appended, then ParameterValues could have
3024 * been realloced, in which case the driver uniform storage set up by
3025 * _mesa_associate_uniform_storage() would point to freed memory. Make
3026 * sure that didn't happen.
3028 assert(sanity_param_count
== fp
->Base
.Parameters
->NumParameters
);
3034 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
,
3035 struct gl_fragment_program
*fp
,
3036 struct gl_shader_program
*prog
,
3037 unsigned *final_assembly_size
)
3039 struct intel_context
*intel
= &brw
->intel
;
3040 bool start_busy
= false;
3041 float start_time
= 0;
3043 if (unlikely(intel
->perf_debug
)) {
3044 start_busy
= (intel
->batch
.last_bo
&&
3045 drm_intel_bo_busy(intel
->batch
.last_bo
));
3046 start_time
= get_time();
3049 struct brw_shader
*shader
= NULL
;
3051 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3053 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3055 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3056 _mesa_print_ir(shader
->ir
, NULL
);
3059 printf("ARB_fragment_program %d ir for native fragment shader\n",
3061 _mesa_print_program(&fp
->Base
);
3065 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3067 fs_visitor
v(brw
, c
, prog
, fp
, 8);
3070 prog
->LinkStatus
= false;
3071 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
3074 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
3080 exec_list
*simd16_instructions
= NULL
;
3081 fs_visitor
v2(brw
, c
, prog
, fp
, 16);
3082 bool no16
= INTEL_DEBUG
& DEBUG_NO16
;
3083 if (intel
->gen
>= 5 && c
->prog_data
.nr_pull_params
== 0 && likely(!no16
)) {
3084 v2
.import_uniforms(&v
);
3086 perf_debug("16-wide shader failed to compile, falling back to "
3087 "8-wide at a 10-20%% performance cost: %s", v2
.fail_msg
);
3089 simd16_instructions
= &v2
.instructions
;
3093 c
->prog_data
.dispatch_width
= 8;
3095 fs_generator
g(brw
, c
, prog
, fp
, v
.dual_src_output
.file
!= BAD_FILE
);
3096 const unsigned *generated
= g
.generate_assembly(&v
.instructions
,
3097 simd16_instructions
,
3098 final_assembly_size
);
3100 if (unlikely(intel
->perf_debug
) && shader
) {
3101 if (shader
->compiled_once
)
3102 brw_wm_debug_recompile(brw
, prog
, &c
->key
);
3103 shader
->compiled_once
= true;
3105 if (start_busy
&& !drm_intel_bo_busy(intel
->batch
.last_bo
)) {
3106 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
3107 (get_time() - start_time
) * 1000);
3115 brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
3117 struct brw_context
*brw
= brw_context(ctx
);
3118 struct intel_context
*intel
= &brw
->intel
;
3119 struct brw_wm_prog_key key
;
3121 if (!prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
])
3124 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)
3125 prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
]->Program
;
3126 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
3127 bool program_uses_dfdy
= fp
->UsesDFdy
;
3129 memset(&key
, 0, sizeof(key
));
3131 if (intel
->gen
< 6) {
3133 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
3135 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
3136 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
3138 /* Just assume depth testing. */
3139 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
3140 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
3144 key
.input_slots_valid
|= BITFIELD64_BIT(VARYING_SLOT_POS
);
3146 for (int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
3147 if (!(fp
->Base
.InputsRead
& BITFIELD64_BIT(i
)))
3150 if (intel
->gen
< 6) {
3151 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
3152 key
.input_slots_valid
|= BITFIELD64_BIT(i
);
3156 key
.clamp_fragment_color
= true;
3158 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
3159 if (fp
->Base
.ShadowSamplers
& (1 << i
)) {
3160 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
3161 key
.tex
.swizzles
[i
] =
3162 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
3164 /* Color sampler: assume no swizzling. */
3165 key
.tex
.swizzles
[i
] = SWIZZLE_XYZW
;
3169 if (fp
->Base
.InputsRead
& VARYING_BIT_POS
) {
3170 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
3173 if ((fp
->Base
.InputsRead
& VARYING_BIT_POS
) || program_uses_dfdy
) {
3174 key
.render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3177 key
.nr_color_regions
= 1;
3179 key
.program_string_id
= bfp
->id
;
3181 uint32_t old_prog_offset
= brw
->wm
.prog_offset
;
3182 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
3184 bool success
= do_wm_prog(brw
, prog
, bfp
, &key
);
3186 brw
->wm
.prog_offset
= old_prog_offset
;
3187 brw
->wm
.prog_data
= old_prog_data
;