2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
33 #include <sys/types.h>
35 #include "main/macros.h"
36 #include "main/shaderobj.h"
37 #include "main/uniforms.h"
38 #include "main/fbobject.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/register_allocate.h"
42 #include "program/sampler.h"
43 #include "program/hash_table.h"
44 #include "brw_context.h"
49 #include "glsl/glsl_types.h"
50 #include "glsl/ir_print_visitor.h"
55 memset(this, 0, sizeof(*this));
56 this->opcode
= BRW_OPCODE_NOP
;
57 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
59 this->dst
= reg_undef
;
60 this->src
[0] = reg_undef
;
61 this->src
[1] = reg_undef
;
62 this->src
[2] = reg_undef
;
70 fs_inst::fs_inst(enum opcode opcode
)
73 this->opcode
= opcode
;
76 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
)
79 this->opcode
= opcode
;
83 assert(dst
.reg_offset
>= 0);
86 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
)
89 this->opcode
= opcode
;
94 assert(dst
.reg_offset
>= 0);
95 if (src
[0].file
== GRF
)
96 assert(src
[0].reg_offset
>= 0);
99 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
102 this->opcode
= opcode
;
108 assert(dst
.reg_offset
>= 0);
109 if (src
[0].file
== GRF
)
110 assert(src
[0].reg_offset
>= 0);
111 if (src
[1].file
== GRF
)
112 assert(src
[1].reg_offset
>= 0);
115 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
,
116 fs_reg src0
, fs_reg src1
, fs_reg src2
)
119 this->opcode
= opcode
;
126 assert(dst
.reg_offset
>= 0);
127 if (src
[0].file
== GRF
)
128 assert(src
[0].reg_offset
>= 0);
129 if (src
[1].file
== GRF
)
130 assert(src
[1].reg_offset
>= 0);
131 if (src
[2].file
== GRF
)
132 assert(src
[2].reg_offset
>= 0);
137 fs_visitor::op(fs_reg dst, fs_reg src0) \
139 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0); \
144 fs_visitor::op(fs_reg dst, fs_reg src0, fs_reg src1) \
146 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1); \
165 /** Gen4 predicated IF. */
167 fs_visitor::IF(uint32_t predicate
)
169 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
);
170 inst
->predicate
= predicate
;
174 /** Gen6+ IF with embedded comparison. */
176 fs_visitor::IF(fs_reg src0
, fs_reg src1
, uint32_t condition
)
178 assert(intel
->gen
>= 6);
179 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
,
180 reg_null_d
, src0
, src1
);
181 inst
->conditional_mod
= condition
;
186 * CMP: Sets the low bit of the destination channels with the result
187 * of the comparison, while the upper bits are undefined, and updates
188 * the flag register with the packed 16 bits of the result.
191 fs_visitor::CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
, uint32_t condition
)
195 /* Take the instruction:
197 * CMP null<d> src0<f> src1<f>
199 * Original gen4 does type conversion to the destination type before
200 * comparison, producing garbage results for floating point comparisons.
201 * gen5 does the comparison on the execution type (resolved source types),
202 * so dst type doesn't matter. gen6 does comparison and then uses the
203 * result as if it was the dst type with no conversion, which happens to
204 * mostly work out for float-interpreted-as-int since our comparisons are
207 if (intel
->gen
== 4) {
208 dst
.type
= src0
.type
;
209 if (dst
.file
== FIXED_HW_REG
)
210 dst
.fixed_hw_reg
.type
= dst
.type
;
213 resolve_ud_negate(&src0
);
214 resolve_ud_negate(&src1
);
216 inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_CMP
, dst
, src0
, src1
);
217 inst
->conditional_mod
= condition
;
223 fs_visitor::VARYING_PULL_CONSTANT_LOAD(fs_reg dst
, fs_reg surf_index
,
226 exec_list instructions
;
229 if (intel
->gen
>= 7) {
230 inst
= new(mem_ctx
) fs_inst(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
,
231 dst
, surf_index
, offset
);
232 instructions
.push_tail(inst
);
235 bool header_present
= true;
237 fs_reg mrf
= fs_reg(MRF
, base_mrf
+ header_present
);
238 mrf
.type
= BRW_REGISTER_TYPE_D
;
240 /* On gen6+ we want the dword offset passed in, but on gen4/5 we need a
241 * dword-aligned byte offset.
243 if (intel
->gen
== 6) {
244 instructions
.push_tail(MOV(mrf
, offset
));
246 instructions
.push_tail(MUL(mrf
, offset
, fs_reg(4)));
248 inst
= MOV(mrf
, offset
);
249 inst
= new(mem_ctx
) fs_inst(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
,
251 inst
->header_present
= header_present
;
252 inst
->base_mrf
= base_mrf
;
253 inst
->mlen
= header_present
+ dispatch_width
/ 8;
255 instructions
.push_tail(inst
);
262 fs_inst::equals(fs_inst
*inst
)
264 return (opcode
== inst
->opcode
&&
265 dst
.equals(inst
->dst
) &&
266 src
[0].equals(inst
->src
[0]) &&
267 src
[1].equals(inst
->src
[1]) &&
268 src
[2].equals(inst
->src
[2]) &&
269 saturate
== inst
->saturate
&&
270 predicate
== inst
->predicate
&&
271 conditional_mod
== inst
->conditional_mod
&&
272 mlen
== inst
->mlen
&&
273 base_mrf
== inst
->base_mrf
&&
274 sampler
== inst
->sampler
&&
275 target
== inst
->target
&&
277 header_present
== inst
->header_present
&&
278 shadow_compare
== inst
->shadow_compare
&&
279 offset
== inst
->offset
);
283 fs_inst::regs_written()
288 /* The SINCOS and INT_DIV_QUOTIENT_AND_REMAINDER math functions return 2,
289 * but we don't currently use them...nor do we have an opcode for them.
296 fs_inst::overwrites_reg(const fs_reg
®
)
298 return (reg
.file
== dst
.file
&&
299 reg
.reg
== dst
.reg
&&
300 reg
.reg_offset
>= dst
.reg_offset
&&
301 reg
.reg_offset
< dst
.reg_offset
+ regs_written());
307 return (opcode
== SHADER_OPCODE_TEX
||
308 opcode
== FS_OPCODE_TXB
||
309 opcode
== SHADER_OPCODE_TXD
||
310 opcode
== SHADER_OPCODE_TXF
||
311 opcode
== SHADER_OPCODE_TXL
||
312 opcode
== SHADER_OPCODE_TXS
);
318 return (opcode
== SHADER_OPCODE_RCP
||
319 opcode
== SHADER_OPCODE_RSQ
||
320 opcode
== SHADER_OPCODE_SQRT
||
321 opcode
== SHADER_OPCODE_EXP2
||
322 opcode
== SHADER_OPCODE_LOG2
||
323 opcode
== SHADER_OPCODE_SIN
||
324 opcode
== SHADER_OPCODE_COS
||
325 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
326 opcode
== SHADER_OPCODE_INT_REMAINDER
||
327 opcode
== SHADER_OPCODE_POW
);
331 fs_inst::is_send_from_grf()
333 return (opcode
== FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
||
334 (opcode
== FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
&&
335 src
[1].file
== GRF
));
339 fs_visitor::can_do_source_mods(fs_inst
*inst
)
341 if (intel
->gen
== 6 && inst
->is_math())
344 if (inst
->is_send_from_grf())
353 memset(this, 0, sizeof(*this));
357 /** Generic unset register constructor. */
361 this->file
= BAD_FILE
;
364 /** Immediate value constructor. */
365 fs_reg::fs_reg(float f
)
369 this->type
= BRW_REGISTER_TYPE_F
;
373 /** Immediate value constructor. */
374 fs_reg::fs_reg(int32_t i
)
378 this->type
= BRW_REGISTER_TYPE_D
;
382 /** Immediate value constructor. */
383 fs_reg::fs_reg(uint32_t u
)
387 this->type
= BRW_REGISTER_TYPE_UD
;
391 /** Fixed brw_reg Immediate value constructor. */
392 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
395 this->file
= FIXED_HW_REG
;
396 this->fixed_hw_reg
= fixed_hw_reg
;
397 this->type
= fixed_hw_reg
.type
;
401 fs_reg::equals(const fs_reg
&r
) const
403 return (file
== r
.file
&&
405 reg_offset
== r
.reg_offset
&&
407 negate
== r
.negate
&&
409 !reladdr
&& !r
.reladdr
&&
410 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
411 sizeof(fixed_hw_reg
)) == 0 &&
417 fs_reg::is_zero() const
422 return type
== BRW_REGISTER_TYPE_F
? imm
.f
== 0.0 : imm
.i
== 0;
426 fs_reg::is_one() const
431 return type
== BRW_REGISTER_TYPE_F
? imm
.f
== 1.0 : imm
.i
== 1;
435 fs_visitor::type_size(const struct glsl_type
*type
)
437 unsigned int size
, i
;
439 switch (type
->base_type
) {
442 case GLSL_TYPE_FLOAT
:
444 return type
->components();
445 case GLSL_TYPE_ARRAY
:
446 return type_size(type
->fields
.array
) * type
->length
;
447 case GLSL_TYPE_STRUCT
:
449 for (i
= 0; i
< type
->length
; i
++) {
450 size
+= type_size(type
->fields
.structure
[i
].type
);
453 case GLSL_TYPE_SAMPLER
:
454 /* Samplers take up no register space, since they're baked in at
459 assert(!"not reached");
465 fs_visitor::get_timestamp()
467 assert(intel
->gen
>= 7);
469 fs_reg ts
= fs_reg(retype(brw_vec1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
472 BRW_REGISTER_TYPE_UD
));
474 fs_reg dst
= fs_reg(this, glsl_type::uint_type
);
476 fs_inst
*mov
= emit(MOV(dst
, ts
));
477 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
478 * even if it's not enabled in the dispatch.
480 mov
->force_writemask_all
= true;
481 mov
->force_uncompressed
= true;
483 /* The caller wants the low 32 bits of the timestamp. Since it's running
484 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
485 * which is plenty of time for our purposes. It is identical across the
486 * EUs, but since it's tracking GPU core speed it will increment at a
487 * varying rate as render P-states change.
489 * The caller could also check if render P-states have changed (or anything
490 * else that might disrupt timing) by setting smear to 2 and checking if
491 * that field is != 0.
499 fs_visitor::emit_shader_time_begin()
501 current_annotation
= "shader time start";
502 shader_start_time
= get_timestamp();
506 fs_visitor::emit_shader_time_end()
508 current_annotation
= "shader time end";
510 enum shader_time_shader_type type
, written_type
, reset_type
;
511 if (dispatch_width
== 8) {
513 written_type
= ST_FS8_WRITTEN
;
514 reset_type
= ST_FS8_RESET
;
516 assert(dispatch_width
== 16);
518 written_type
= ST_FS16_WRITTEN
;
519 reset_type
= ST_FS16_RESET
;
522 fs_reg shader_end_time
= get_timestamp();
524 /* Check that there weren't any timestamp reset events (assuming these
525 * were the only two timestamp reads that happened).
527 fs_reg reset
= shader_end_time
;
529 fs_inst
*test
= emit(AND(reg_null_d
, reset
, fs_reg(1u)));
530 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
531 emit(IF(BRW_PREDICATE_NORMAL
));
533 push_force_uncompressed();
534 fs_reg start
= shader_start_time
;
536 fs_reg diff
= fs_reg(this, glsl_type::uint_type
);
537 emit(ADD(diff
, start
, shader_end_time
));
539 /* If there were no instructions between the two timestamp gets, the diff
540 * is 2 cycles. Remove that overhead, so I can forget about that when
541 * trying to determine the time taken for single instructions.
543 emit(ADD(diff
, diff
, fs_reg(-2u)));
545 emit_shader_time_write(type
, diff
);
546 emit_shader_time_write(written_type
, fs_reg(1u));
547 emit(BRW_OPCODE_ELSE
);
548 emit_shader_time_write(reset_type
, fs_reg(1u));
549 emit(BRW_OPCODE_ENDIF
);
551 pop_force_uncompressed();
555 fs_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
558 /* Choose an index in the buffer and set up tracking information for our
561 int shader_time_index
= brw
->shader_time
.num_entries
++;
562 assert(shader_time_index
<= brw
->shader_time
.max_entries
);
563 brw
->shader_time
.types
[shader_time_index
] = type
;
565 _mesa_reference_shader_program(ctx
,
566 &brw
->shader_time
.programs
[shader_time_index
],
572 fs_reg offset_mrf
= fs_reg(MRF
, base_mrf
);
573 offset_mrf
.type
= BRW_REGISTER_TYPE_UD
;
574 emit(MOV(offset_mrf
, fs_reg(shader_time_index
* 4)));
576 fs_reg time_mrf
= fs_reg(MRF
, base_mrf
+ 1);
577 time_mrf
.type
= BRW_REGISTER_TYPE_UD
;
578 emit(MOV(time_mrf
, value
));
580 fs_inst
*inst
= emit(fs_inst(SHADER_OPCODE_SHADER_TIME_ADD
));
581 inst
->base_mrf
= base_mrf
;
586 fs_visitor::fail(const char *format
, ...)
596 va_start(va
, format
);
597 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
599 msg
= ralloc_asprintf(mem_ctx
, "FS compile failed: %s\n", msg
);
601 this->fail_msg
= msg
;
603 if (INTEL_DEBUG
& DEBUG_WM
) {
604 fprintf(stderr
, "%s", msg
);
609 fs_visitor::emit(enum opcode opcode
)
611 return emit(fs_inst(opcode
));
615 fs_visitor::emit(enum opcode opcode
, fs_reg dst
)
617 return emit(fs_inst(opcode
, dst
));
621 fs_visitor::emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
)
623 return emit(fs_inst(opcode
, dst
, src0
));
627 fs_visitor::emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
629 return emit(fs_inst(opcode
, dst
, src0
, src1
));
633 fs_visitor::emit(enum opcode opcode
, fs_reg dst
,
634 fs_reg src0
, fs_reg src1
, fs_reg src2
)
636 return emit(fs_inst(opcode
, dst
, src0
, src1
, src2
));
640 fs_visitor::push_force_uncompressed()
642 force_uncompressed_stack
++;
646 fs_visitor::pop_force_uncompressed()
648 force_uncompressed_stack
--;
649 assert(force_uncompressed_stack
>= 0);
653 fs_visitor::push_force_sechalf()
655 force_sechalf_stack
++;
659 fs_visitor::pop_force_sechalf()
661 force_sechalf_stack
--;
662 assert(force_sechalf_stack
>= 0);
666 * Returns how many MRFs an FS opcode will write over.
668 * Note that this is not the 0 or 1 implied writes in an actual gen
669 * instruction -- the FS opcodes often generate MOVs in addition.
672 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
677 switch (inst
->opcode
) {
678 case SHADER_OPCODE_RCP
:
679 case SHADER_OPCODE_RSQ
:
680 case SHADER_OPCODE_SQRT
:
681 case SHADER_OPCODE_EXP2
:
682 case SHADER_OPCODE_LOG2
:
683 case SHADER_OPCODE_SIN
:
684 case SHADER_OPCODE_COS
:
685 return 1 * dispatch_width
/ 8;
686 case SHADER_OPCODE_POW
:
687 case SHADER_OPCODE_INT_QUOTIENT
:
688 case SHADER_OPCODE_INT_REMAINDER
:
689 return 2 * dispatch_width
/ 8;
690 case SHADER_OPCODE_TEX
:
692 case SHADER_OPCODE_TXD
:
693 case SHADER_OPCODE_TXF
:
694 case SHADER_OPCODE_TXL
:
695 case SHADER_OPCODE_TXS
:
697 case SHADER_OPCODE_SHADER_TIME_ADD
:
699 case FS_OPCODE_FB_WRITE
:
701 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
702 case FS_OPCODE_UNSPILL
:
704 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
705 return inst
->header_present
;
706 case FS_OPCODE_SPILL
:
709 assert(!"not reached");
715 fs_visitor::virtual_grf_alloc(int size
)
717 if (virtual_grf_array_size
<= virtual_grf_count
) {
718 if (virtual_grf_array_size
== 0)
719 virtual_grf_array_size
= 16;
721 virtual_grf_array_size
*= 2;
722 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
723 virtual_grf_array_size
);
725 virtual_grf_sizes
[virtual_grf_count
] = size
;
726 return virtual_grf_count
++;
729 /** Fixed HW reg constructor. */
730 fs_reg::fs_reg(enum register_file file
, int reg
)
735 this->type
= BRW_REGISTER_TYPE_F
;
738 /** Fixed HW reg constructor. */
739 fs_reg::fs_reg(enum register_file file
, int reg
, uint32_t type
)
747 /** Automatic reg constructor. */
748 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
753 this->reg
= v
->virtual_grf_alloc(v
->type_size(type
));
754 this->reg_offset
= 0;
755 this->type
= brw_type_for_base_type(type
);
759 fs_visitor::variable_storage(ir_variable
*var
)
761 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
765 import_uniforms_callback(const void *key
,
769 struct hash_table
*dst_ht
= (struct hash_table
*)closure
;
770 const fs_reg
*reg
= (const fs_reg
*)data
;
772 if (reg
->file
!= UNIFORM
)
775 hash_table_insert(dst_ht
, data
, key
);
778 /* For 16-wide, we need to follow from the uniform setup of 8-wide dispatch.
779 * This brings in those uniform definitions
782 fs_visitor::import_uniforms(fs_visitor
*v
)
784 hash_table_call_foreach(v
->variable_ht
,
785 import_uniforms_callback
,
787 this->params_remap
= v
->params_remap
;
790 /* Our support for uniforms is piggy-backed on the struct
791 * gl_fragment_program, because that's where the values actually
792 * get stored, rather than in some global gl_shader_program uniform
796 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
798 unsigned int offset
= 0;
800 if (type
->is_matrix()) {
801 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
802 type
->vector_elements
,
805 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
806 offset
+= setup_uniform_values(loc
+ offset
, column
);
812 switch (type
->base_type
) {
813 case GLSL_TYPE_FLOAT
:
817 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
818 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
819 &fp
->Base
.Parameters
->ParameterValues
[loc
][i
].f
;
823 case GLSL_TYPE_STRUCT
:
824 for (unsigned int i
= 0; i
< type
->length
; i
++) {
825 offset
+= setup_uniform_values(loc
+ offset
,
826 type
->fields
.structure
[i
].type
);
830 case GLSL_TYPE_ARRAY
:
831 for (unsigned int i
= 0; i
< type
->length
; i
++) {
832 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
836 case GLSL_TYPE_SAMPLER
:
837 /* The sampler takes up a slot, but we don't use any values from it. */
841 assert(!"not reached");
847 /* Our support for builtin uniforms is even scarier than non-builtin.
848 * It sits on top of the PROG_STATE_VAR parameters that are
849 * automatically updated from GL context state.
852 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
854 const ir_state_slot
*const slots
= ir
->state_slots
;
855 assert(ir
->state_slots
!= NULL
);
857 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
858 /* This state reference has already been setup by ir_to_mesa, but we'll
859 * get the same index back here.
861 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
862 (gl_state_index
*)slots
[i
].tokens
);
864 /* Add each of the unique swizzles of the element as a parameter.
865 * This'll end up matching the expected layout of the
866 * array/matrix/structure we're trying to fill in.
869 for (unsigned int j
= 0; j
< 4; j
++) {
870 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
871 if (swiz
== last_swiz
)
875 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
876 &fp
->Base
.Parameters
->ParameterValues
[index
][swiz
].f
;
882 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
884 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
886 bool flip
= !ir
->origin_upper_left
^ c
->key
.render_to_fbo
;
889 if (ir
->pixel_center_integer
) {
890 emit(MOV(wpos
, this->pixel_x
));
892 emit(ADD(wpos
, this->pixel_x
, fs_reg(0.5f
)));
897 if (!flip
&& ir
->pixel_center_integer
) {
898 emit(MOV(wpos
, this->pixel_y
));
900 fs_reg pixel_y
= this->pixel_y
;
901 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
904 pixel_y
.negate
= true;
905 offset
+= c
->key
.drawable_height
- 1.0;
908 emit(ADD(wpos
, pixel_y
, fs_reg(offset
)));
913 if (intel
->gen
>= 6) {
914 emit(MOV(wpos
, fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
916 emit(FS_OPCODE_LINTERP
, wpos
,
917 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
918 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
919 interp_reg(FRAG_ATTRIB_WPOS
, 2));
923 /* gl_FragCoord.w: Already set up in emit_interpolation */
924 emit(BRW_OPCODE_MOV
, wpos
, this->wpos_w
);
930 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
931 glsl_interp_qualifier interpolation_mode
,
934 brw_wm_barycentric_interp_mode barycoord_mode
;
936 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
937 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
939 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
941 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
942 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
944 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
946 return emit(FS_OPCODE_LINTERP
, attr
,
947 this->delta_x
[barycoord_mode
],
948 this->delta_y
[barycoord_mode
], interp
);
952 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
954 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
955 reg
->type
= brw_type_for_base_type(ir
->type
->get_scalar_type());
958 unsigned int array_elements
;
959 const glsl_type
*type
;
961 if (ir
->type
->is_array()) {
962 array_elements
= ir
->type
->length
;
963 if (array_elements
== 0) {
964 fail("dereferenced array '%s' has length 0\n", ir
->name
);
966 type
= ir
->type
->fields
.array
;
972 glsl_interp_qualifier interpolation_mode
=
973 ir
->determine_interpolation_mode(c
->key
.flat_shade
);
975 int location
= ir
->location
;
976 for (unsigned int i
= 0; i
< array_elements
; i
++) {
977 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
978 if (urb_setup
[location
] == -1) {
979 /* If there's no incoming setup data for this slot, don't
980 * emit interpolation for it.
982 attr
.reg_offset
+= type
->vector_elements
;
987 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
988 /* Constant interpolation (flat shading) case. The SF has
989 * handed us defined values in only the constant offset
990 * field of the setup reg.
992 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
993 struct brw_reg interp
= interp_reg(location
, k
);
994 interp
= suboffset(interp
, 3);
995 interp
.type
= reg
->type
;
996 emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1000 /* Smooth/noperspective interpolation case. */
1001 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1002 /* FINISHME: At some point we probably want to push
1003 * this farther by giving similar treatment to the
1004 * other potentially constant components of the
1005 * attribute, as well as making brw_vs_constval.c
1006 * handle varyings other than gl_TexCoord.
1008 if (location
>= FRAG_ATTRIB_TEX0
&&
1009 location
<= FRAG_ATTRIB_TEX7
&&
1010 k
== 3 && !(c
->key
.proj_attrib_mask
& (1 << location
))) {
1011 emit(BRW_OPCODE_MOV
, attr
, fs_reg(1.0f
));
1013 struct brw_reg interp
= interp_reg(location
, k
);
1014 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1016 if (brw
->needs_unlit_centroid_workaround
&& ir
->centroid
) {
1017 /* Get the pixel/sample mask into f0 so that we know
1018 * which pixels are lit. Then, for each channel that is
1019 * unlit, replace the centroid data with non-centroid
1022 emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
, attr
);
1023 fs_inst
*inst
= emit_linterp(attr
, fs_reg(interp
),
1024 interpolation_mode
, false);
1025 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1026 inst
->predicate_inverse
= true;
1028 if (intel
->gen
< 6) {
1029 emit(BRW_OPCODE_MUL
, attr
, attr
, this->pixel_w
);
1044 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
1046 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1048 /* The frontfacing comes in as a bit in the thread payload. */
1049 if (intel
->gen
>= 6) {
1050 emit(BRW_OPCODE_ASR
, *reg
,
1051 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1053 emit(BRW_OPCODE_NOT
, *reg
, *reg
);
1054 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1));
1056 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
1057 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
1060 emit(CMP(*reg
, fs_reg(r1_6ud
), fs_reg(1u << 31), BRW_CONDITIONAL_L
));
1061 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u));
1068 fs_visitor::fix_math_operand(fs_reg src
)
1070 /* Can't do hstride == 0 args on gen6 math, so expand it out. We
1071 * might be able to do better by doing execsize = 1 math and then
1072 * expanding that result out, but we would need to be careful with
1075 * The hardware ignores source modifiers (negate and abs) on math
1076 * instructions, so we also move to a temp to set those up.
1078 if (intel
->gen
== 6 && src
.file
!= UNIFORM
&& src
.file
!= IMM
&&
1079 !src
.abs
&& !src
.negate
)
1082 /* Gen7 relaxes most of the above restrictions, but still can't use IMM
1085 if (intel
->gen
>= 7 && src
.file
!= IMM
)
1088 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
1089 expanded
.type
= src
.type
;
1090 emit(BRW_OPCODE_MOV
, expanded
, src
);
1095 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src
)
1098 case SHADER_OPCODE_RCP
:
1099 case SHADER_OPCODE_RSQ
:
1100 case SHADER_OPCODE_SQRT
:
1101 case SHADER_OPCODE_EXP2
:
1102 case SHADER_OPCODE_LOG2
:
1103 case SHADER_OPCODE_SIN
:
1104 case SHADER_OPCODE_COS
:
1107 assert(!"not reached: bad math opcode");
1111 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
1112 * might be able to do better by doing execsize = 1 math and then
1113 * expanding that result out, but we would need to be careful with
1116 * Gen 6 hardware ignores source modifiers (negate and abs) on math
1117 * instructions, so we also move to a temp to set those up.
1119 if (intel
->gen
>= 6)
1120 src
= fix_math_operand(src
);
1122 fs_inst
*inst
= emit(opcode
, dst
, src
);
1124 if (intel
->gen
< 6) {
1126 inst
->mlen
= dispatch_width
/ 8;
1133 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
1139 case SHADER_OPCODE_INT_QUOTIENT
:
1140 case SHADER_OPCODE_INT_REMAINDER
:
1141 if (intel
->gen
>= 7 && dispatch_width
== 16)
1142 fail("16-wide INTDIV unsupported\n");
1144 case SHADER_OPCODE_POW
:
1147 assert(!"not reached: unsupported binary math opcode.");
1151 if (intel
->gen
>= 6) {
1152 src0
= fix_math_operand(src0
);
1153 src1
= fix_math_operand(src1
);
1155 inst
= emit(opcode
, dst
, src0
, src1
);
1157 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
1158 * "Message Payload":
1160 * "Operand0[7]. For the INT DIV functions, this operand is the
1163 * "Operand1[7]. For the INT DIV functions, this operand is the
1166 bool is_int_div
= opcode
!= SHADER_OPCODE_POW
;
1167 fs_reg
&op0
= is_int_div
? src1
: src0
;
1168 fs_reg
&op1
= is_int_div
? src0
: src1
;
1170 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1, op1
.type
), op1
);
1171 inst
= emit(opcode
, dst
, op0
, reg_null_f
);
1173 inst
->base_mrf
= base_mrf
;
1174 inst
->mlen
= 2 * dispatch_width
/ 8;
1180 fs_visitor::assign_curb_setup()
1182 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
1183 if (dispatch_width
== 8) {
1184 c
->prog_data
.first_curbe_grf
= c
->nr_payload_regs
;
1186 c
->prog_data
.first_curbe_grf_16
= c
->nr_payload_regs
;
1189 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1190 foreach_list(node
, &this->instructions
) {
1191 fs_inst
*inst
= (fs_inst
*)node
;
1193 for (unsigned int i
= 0; i
< 3; i
++) {
1194 if (inst
->src
[i
].file
== UNIFORM
) {
1195 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1196 struct brw_reg brw_reg
= brw_vec1_grf(c
->nr_payload_regs
+
1200 inst
->src
[i
].file
= FIXED_HW_REG
;
1201 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
1208 fs_visitor::calculate_urb_setup()
1210 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
1215 /* Figure out where each of the incoming setup attributes lands. */
1216 if (intel
->gen
>= 6) {
1217 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
1218 if (fp
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
1219 urb_setup
[i
] = urb_next
++;
1223 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1224 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
1225 /* Point size is packed into the header, not as a general attribute */
1226 if (i
== VERT_RESULT_PSIZ
)
1229 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
1230 int fp_index
= _mesa_vert_result_to_frag_attrib((gl_vert_result
) i
);
1232 /* The back color slot is skipped when the front color is
1233 * also written to. In addition, some slots can be
1234 * written in the vertex shader and not read in the
1235 * fragment shader. So the register number must always be
1236 * incremented, mapped or not.
1239 urb_setup
[fp_index
] = urb_next
;
1245 * It's a FS only attribute, and we did interpolation for this attribute
1246 * in SF thread. So, count it here, too.
1248 * See compile_sf_prog() for more info.
1250 if (fp
->Base
.InputsRead
& BITFIELD64_BIT(FRAG_ATTRIB_PNTC
))
1251 urb_setup
[FRAG_ATTRIB_PNTC
] = urb_next
++;
1254 /* Each attribute is 4 setup channels, each of which is half a reg. */
1255 c
->prog_data
.urb_read_length
= urb_next
* 2;
1259 fs_visitor::assign_urb_setup()
1261 int urb_start
= c
->nr_payload_regs
+ c
->prog_data
.curb_read_length
;
1263 /* Offset all the urb_setup[] index by the actual position of the
1264 * setup regs, now that the location of the constants has been chosen.
1266 foreach_list(node
, &this->instructions
) {
1267 fs_inst
*inst
= (fs_inst
*)node
;
1269 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1270 assert(inst
->src
[2].file
== FIXED_HW_REG
);
1271 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
1274 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1275 assert(inst
->src
[0].file
== FIXED_HW_REG
);
1276 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1280 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
1284 * Split large virtual GRFs into separate components if we can.
1286 * This is mostly duplicated with what brw_fs_vector_splitting does,
1287 * but that's really conservative because it's afraid of doing
1288 * splitting that doesn't result in real progress after the rest of
1289 * the optimization phases, which would cause infinite looping in
1290 * optimization. We can do it once here, safely. This also has the
1291 * opportunity to split interpolated values, or maybe even uniforms,
1292 * which we don't have at the IR level.
1294 * We want to split, because virtual GRFs are what we register
1295 * allocate and spill (due to contiguousness requirements for some
1296 * instructions), and they're what we naturally generate in the
1297 * codegen process, but most virtual GRFs don't actually need to be
1298 * contiguous sets of GRFs. If we split, we'll end up with reduced
1299 * live intervals and better dead code elimination and coalescing.
1302 fs_visitor::split_virtual_grfs()
1304 int num_vars
= this->virtual_grf_count
;
1305 bool split_grf
[num_vars
];
1306 int new_virtual_grf
[num_vars
];
1308 /* Try to split anything > 0 sized. */
1309 for (int i
= 0; i
< num_vars
; i
++) {
1310 if (this->virtual_grf_sizes
[i
] != 1)
1311 split_grf
[i
] = true;
1313 split_grf
[i
] = false;
1317 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].file
== GRF
) {
1318 /* PLN opcodes rely on the delta_xy being contiguous. We only have to
1319 * check this for BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because prior to
1320 * Gen6, that was the only supported interpolation mode, and since Gen6,
1321 * delta_x and delta_y are in fixed hardware registers.
1323 split_grf
[this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
] =
1327 foreach_list(node
, &this->instructions
) {
1328 fs_inst
*inst
= (fs_inst
*)node
;
1330 /* If there's a SEND message that requires contiguous destination
1331 * registers, no splitting is allowed.
1333 if (inst
->regs_written() > 1) {
1334 split_grf
[inst
->dst
.reg
] = false;
1338 /* Allocate new space for split regs. Note that the virtual
1339 * numbers will be contiguous.
1341 for (int i
= 0; i
< num_vars
; i
++) {
1343 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1344 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1345 int reg
= virtual_grf_alloc(1);
1346 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1349 this->virtual_grf_sizes
[i
] = 1;
1353 foreach_list(node
, &this->instructions
) {
1354 fs_inst
*inst
= (fs_inst
*)node
;
1356 if (inst
->dst
.file
== GRF
&&
1357 split_grf
[inst
->dst
.reg
] &&
1358 inst
->dst
.reg_offset
!= 0) {
1359 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1360 inst
->dst
.reg_offset
- 1);
1361 inst
->dst
.reg_offset
= 0;
1363 for (int i
= 0; i
< 3; i
++) {
1364 if (inst
->src
[i
].file
== GRF
&&
1365 split_grf
[inst
->src
[i
].reg
] &&
1366 inst
->src
[i
].reg_offset
!= 0) {
1367 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1368 inst
->src
[i
].reg_offset
- 1);
1369 inst
->src
[i
].reg_offset
= 0;
1373 this->live_intervals_valid
= false;
1377 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1379 * During code generation, we create tons of temporary variables, many of
1380 * which get immediately killed and are never used again. Yet, in later
1381 * optimization and analysis passes, such as compute_live_intervals, we need
1382 * to loop over all the virtual GRFs. Compacting them can save a lot of
1386 fs_visitor::compact_virtual_grfs()
1388 /* Mark which virtual GRFs are used, and count how many. */
1389 int remap_table
[this->virtual_grf_count
];
1390 memset(remap_table
, -1, sizeof(remap_table
));
1392 foreach_list(node
, &this->instructions
) {
1393 const fs_inst
*inst
= (const fs_inst
*) node
;
1395 if (inst
->dst
.file
== GRF
)
1396 remap_table
[inst
->dst
.reg
] = 0;
1398 for (int i
= 0; i
< 3; i
++) {
1399 if (inst
->src
[i
].file
== GRF
)
1400 remap_table
[inst
->src
[i
].reg
] = 0;
1404 /* In addition to registers used in instructions, fs_visitor keeps
1405 * direct references to certain special values which must be patched:
1407 fs_reg
*special
[] = {
1408 &frag_depth
, &pixel_x
, &pixel_y
, &pixel_w
, &wpos_w
, &dual_src_output
,
1409 &outputs
[0], &outputs
[1], &outputs
[2], &outputs
[3],
1410 &outputs
[4], &outputs
[5], &outputs
[6], &outputs
[7],
1411 &delta_x
[0], &delta_x
[1], &delta_x
[2],
1412 &delta_x
[3], &delta_x
[4], &delta_x
[5],
1413 &delta_y
[0], &delta_y
[1], &delta_y
[2],
1414 &delta_y
[3], &delta_y
[4], &delta_y
[5],
1416 STATIC_ASSERT(BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
== 6);
1417 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
== 8);
1419 /* Treat all special values as used, to be conservative */
1420 for (unsigned i
= 0; i
< ARRAY_SIZE(special
); i
++) {
1421 if (special
[i
]->file
== GRF
)
1422 remap_table
[special
[i
]->reg
] = 0;
1425 /* Compact the GRF arrays. */
1427 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
1428 if (remap_table
[i
] != -1) {
1429 remap_table
[i
] = new_index
;
1430 virtual_grf_sizes
[new_index
] = virtual_grf_sizes
[i
];
1431 if (live_intervals_valid
) {
1432 virtual_grf_use
[new_index
] = virtual_grf_use
[i
];
1433 virtual_grf_def
[new_index
] = virtual_grf_def
[i
];
1439 this->virtual_grf_count
= new_index
;
1441 /* Patch all the instructions to use the newly renumbered registers */
1442 foreach_list(node
, &this->instructions
) {
1443 fs_inst
*inst
= (fs_inst
*) node
;
1445 if (inst
->dst
.file
== GRF
)
1446 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
1448 for (int i
= 0; i
< 3; i
++) {
1449 if (inst
->src
[i
].file
== GRF
)
1450 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
1454 /* Patch all the references to special values */
1455 for (unsigned i
= 0; i
< ARRAY_SIZE(special
); i
++) {
1456 if (special
[i
]->file
== GRF
&& remap_table
[special
[i
]->reg
] != -1)
1457 special
[i
]->reg
= remap_table
[special
[i
]->reg
];
1462 fs_visitor::remove_dead_constants()
1464 if (dispatch_width
== 8) {
1465 this->params_remap
= ralloc_array(mem_ctx
, int, c
->prog_data
.nr_params
);
1467 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++)
1468 this->params_remap
[i
] = -1;
1470 /* Find which params are still in use. */
1471 foreach_list(node
, &this->instructions
) {
1472 fs_inst
*inst
= (fs_inst
*)node
;
1474 for (int i
= 0; i
< 3; i
++) {
1475 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1477 if (inst
->src
[i
].file
!= UNIFORM
)
1480 assert(constant_nr
< (int)c
->prog_data
.nr_params
);
1482 /* For now, set this to non-negative. We'll give it the
1483 * actual new number in a moment, in order to keep the
1484 * register numbers nicely ordered.
1486 this->params_remap
[constant_nr
] = 0;
1490 /* Figure out what the new numbers for the params will be. At some
1491 * point when we're doing uniform array access, we're going to want
1492 * to keep the distinction between .reg and .reg_offset, but for
1493 * now we don't care.
1495 unsigned int new_nr_params
= 0;
1496 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1497 if (this->params_remap
[i
] != -1) {
1498 this->params_remap
[i
] = new_nr_params
++;
1502 /* Update the list of params to be uploaded to match our new numbering. */
1503 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1504 int remapped
= this->params_remap
[i
];
1509 c
->prog_data
.param
[remapped
] = c
->prog_data
.param
[i
];
1512 c
->prog_data
.nr_params
= new_nr_params
;
1514 /* This should have been generated in the 8-wide pass already. */
1515 assert(this->params_remap
);
1518 /* Now do the renumbering of the shader to remove unused params. */
1519 foreach_list(node
, &this->instructions
) {
1520 fs_inst
*inst
= (fs_inst
*)node
;
1522 for (int i
= 0; i
< 3; i
++) {
1523 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1525 if (inst
->src
[i
].file
!= UNIFORM
)
1528 assert(this->params_remap
[constant_nr
] != -1);
1529 inst
->src
[i
].reg
= this->params_remap
[constant_nr
];
1530 inst
->src
[i
].reg_offset
= 0;
1538 * Implements array access of uniforms by inserting a
1539 * PULL_CONSTANT_LOAD instruction.
1541 * Unlike temporary GRF array access (where we don't support it due to
1542 * the difficulty of doing relative addressing on instruction
1543 * destinations), we could potentially do array access of uniforms
1544 * that were loaded in GRF space as push constants. In real-world
1545 * usage we've seen, though, the arrays being used are always larger
1546 * than we could load as push constants, so just always move all
1547 * uniform array access out to a pull constant buffer.
1550 fs_visitor::move_uniform_array_access_to_pull_constants()
1552 int pull_constant_loc
[c
->prog_data
.nr_params
];
1554 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1555 pull_constant_loc
[i
] = -1;
1558 /* Walk through and find array access of uniforms. Put a copy of that
1559 * uniform in the pull constant buffer.
1561 * Note that we don't move constant-indexed accesses to arrays. No
1562 * testing has been done of the performance impact of this choice.
1564 foreach_list_safe(node
, &this->instructions
) {
1565 fs_inst
*inst
= (fs_inst
*)node
;
1567 for (int i
= 0 ; i
< 3; i
++) {
1568 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
1571 int uniform
= inst
->src
[i
].reg
;
1573 /* If this array isn't already present in the pull constant buffer,
1576 if (pull_constant_loc
[uniform
] == -1) {
1577 const float **values
= &c
->prog_data
.param
[uniform
];
1579 pull_constant_loc
[uniform
] = c
->prog_data
.nr_pull_params
;
1581 assert(param_size
[uniform
]);
1583 for (int j
= 0; j
< param_size
[uniform
]; j
++) {
1584 c
->prog_data
.pull_param
[c
->prog_data
.nr_pull_params
++] =
1589 /* Set up the annotation tracking for new generated instructions. */
1591 current_annotation
= inst
->annotation
;
1593 fs_reg offset
= fs_reg(this, glsl_type::int_type
);
1594 inst
->insert_before(ADD(offset
, *inst
->src
[i
].reladdr
,
1595 fs_reg(pull_constant_loc
[uniform
] +
1596 inst
->src
[i
].reg_offset
)));
1598 fs_reg surf_index
= fs_reg((unsigned)SURF_INDEX_FRAG_CONST_BUFFER
);
1599 fs_reg temp
= fs_reg(this, glsl_type::float_type
);
1600 exec_list list
= VARYING_PULL_CONSTANT_LOAD(temp
,
1601 surf_index
, offset
);
1602 inst
->insert_before(&list
);
1604 inst
->src
[i
].file
= temp
.file
;
1605 inst
->src
[i
].reg
= temp
.reg
;
1606 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
1607 inst
->src
[i
].reladdr
= NULL
;
1613 * Choose accesses from the UNIFORM file to demote to using the pull
1616 * We allow a fragment shader to have more than the specified minimum
1617 * maximum number of fragment shader uniform components (64). If
1618 * there are too many of these, they'd fill up all of register space.
1619 * So, this will push some of them out to the pull constant buffer and
1620 * update the program to load them.
1623 fs_visitor::setup_pull_constants()
1625 /* Only allow 16 registers (128 uniform components) as push constants. */
1626 unsigned int max_uniform_components
= 16 * 8;
1627 if (c
->prog_data
.nr_params
<= max_uniform_components
)
1630 if (dispatch_width
== 16) {
1631 fail("Pull constants not supported in 16-wide\n");
1635 /* Just demote the end of the list. We could probably do better
1636 * here, demoting things that are rarely used in the program first.
1638 unsigned int pull_uniform_base
= max_uniform_components
;
1640 int pull_constant_loc
[c
->prog_data
.nr_params
];
1641 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1642 if (i
< pull_uniform_base
) {
1643 pull_constant_loc
[i
] = -1;
1645 pull_constant_loc
[i
] = -1;
1646 /* If our constant is already being uploaded for reladdr purposes,
1649 for (unsigned int j
= 0; j
< c
->prog_data
.nr_pull_params
; j
++) {
1650 if (c
->prog_data
.pull_param
[j
] == c
->prog_data
.param
[i
]) {
1651 pull_constant_loc
[i
] = j
;
1655 if (pull_constant_loc
[i
] == -1) {
1656 int pull_index
= c
->prog_data
.nr_pull_params
++;
1657 c
->prog_data
.pull_param
[pull_index
] = c
->prog_data
.param
[i
];
1658 pull_constant_loc
[i
] = pull_index
;;
1662 c
->prog_data
.nr_params
= pull_uniform_base
;
1664 foreach_list(node
, &this->instructions
) {
1665 fs_inst
*inst
= (fs_inst
*)node
;
1667 for (int i
= 0; i
< 3; i
++) {
1668 if (inst
->src
[i
].file
!= UNIFORM
)
1671 int pull_index
= pull_constant_loc
[inst
->src
[i
].reg
+
1672 inst
->src
[i
].reg_offset
];
1673 if (pull_index
== -1)
1676 assert(!inst
->src
[i
].reladdr
);
1678 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
1679 fs_reg index
= fs_reg((unsigned)SURF_INDEX_FRAG_CONST_BUFFER
);
1680 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
1682 new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
1683 dst
, index
, offset
);
1684 pull
->ir
= inst
->ir
;
1685 pull
->annotation
= inst
->annotation
;
1686 pull
->base_mrf
= 14;
1689 inst
->insert_before(pull
);
1691 inst
->src
[i
].file
= GRF
;
1692 inst
->src
[i
].reg
= dst
.reg
;
1693 inst
->src
[i
].reg_offset
= 0;
1694 inst
->src
[i
].smear
= pull_index
& 3;
1700 fs_visitor::opt_algebraic()
1702 bool progress
= false;
1704 foreach_list(node
, &this->instructions
) {
1705 fs_inst
*inst
= (fs_inst
*)node
;
1707 switch (inst
->opcode
) {
1708 case BRW_OPCODE_MUL
:
1709 if (inst
->src
[1].file
!= IMM
)
1713 if (inst
->src
[1].is_one()) {
1714 inst
->opcode
= BRW_OPCODE_MOV
;
1715 inst
->src
[1] = reg_undef
;
1721 if (inst
->src
[1].is_zero()) {
1722 inst
->opcode
= BRW_OPCODE_MOV
;
1723 inst
->src
[0] = inst
->src
[1];
1724 inst
->src
[1] = reg_undef
;
1730 case BRW_OPCODE_ADD
:
1731 if (inst
->src
[1].file
!= IMM
)
1735 if (inst
->src
[1].is_zero()) {
1736 inst
->opcode
= BRW_OPCODE_MOV
;
1737 inst
->src
[1] = reg_undef
;
1751 * Must be called after calculate_live_intervales() to remove unused
1752 * writes to registers -- register allocation will fail otherwise
1753 * because something deffed but not used won't be considered to
1754 * interfere with other regs.
1757 fs_visitor::dead_code_eliminate()
1759 bool progress
= false;
1762 calculate_live_intervals();
1764 foreach_list_safe(node
, &this->instructions
) {
1765 fs_inst
*inst
= (fs_inst
*)node
;
1767 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
1776 live_intervals_valid
= false;
1782 * Implements a second type of register coalescing: This one checks if
1783 * the two regs involved in a raw move don't interfere, in which case
1784 * they can both by stored in the same place and the MOV removed.
1787 fs_visitor::register_coalesce_2()
1789 bool progress
= false;
1791 calculate_live_intervals();
1793 foreach_list_safe(node
, &this->instructions
) {
1794 fs_inst
*inst
= (fs_inst
*)node
;
1796 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1799 inst
->src
[0].file
!= GRF
||
1800 inst
->src
[0].negate
||
1802 inst
->src
[0].smear
!= -1 ||
1803 inst
->dst
.file
!= GRF
||
1804 inst
->dst
.type
!= inst
->src
[0].type
||
1805 virtual_grf_sizes
[inst
->src
[0].reg
] != 1 ||
1806 virtual_grf_interferes(inst
->dst
.reg
, inst
->src
[0].reg
)) {
1810 int reg_from
= inst
->src
[0].reg
;
1811 assert(inst
->src
[0].reg_offset
== 0);
1812 int reg_to
= inst
->dst
.reg
;
1813 int reg_to_offset
= inst
->dst
.reg_offset
;
1815 foreach_list(node
, &this->instructions
) {
1816 fs_inst
*scan_inst
= (fs_inst
*)node
;
1818 if (scan_inst
->dst
.file
== GRF
&&
1819 scan_inst
->dst
.reg
== reg_from
) {
1820 scan_inst
->dst
.reg
= reg_to
;
1821 scan_inst
->dst
.reg_offset
= reg_to_offset
;
1823 for (int i
= 0; i
< 3; i
++) {
1824 if (scan_inst
->src
[i
].file
== GRF
&&
1825 scan_inst
->src
[i
].reg
== reg_from
) {
1826 scan_inst
->src
[i
].reg
= reg_to
;
1827 scan_inst
->src
[i
].reg_offset
= reg_to_offset
;
1834 /* We don't need to recalculate live intervals inside the loop despite
1835 * flagging live_intervals_valid because we only use live intervals for
1836 * the interferes test, and we must have had a situation where the
1847 * Some register R that might get coalesced with one of these two could
1848 * only be referencing "to", otherwise "from"'s range would have been
1849 * longer. R's range could also only start at the end of "to" or later,
1850 * otherwise it will conflict with "to" when we try to coalesce "to"
1853 live_intervals_valid
= false;
1863 fs_visitor::register_coalesce()
1865 bool progress
= false;
1869 foreach_list_safe(node
, &this->instructions
) {
1870 fs_inst
*inst
= (fs_inst
*)node
;
1872 /* Make sure that we dominate the instructions we're going to
1873 * scan for interfering with our coalescing, or we won't have
1874 * scanned enough to see if anything interferes with our
1875 * coalescing. We don't dominate the following instructions if
1876 * we're in a loop or an if block.
1878 switch (inst
->opcode
) {
1882 case BRW_OPCODE_WHILE
:
1888 case BRW_OPCODE_ENDIF
:
1894 if (loop_depth
|| if_depth
)
1897 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1900 inst
->dst
.file
!= GRF
|| (inst
->src
[0].file
!= GRF
&&
1901 inst
->src
[0].file
!= UNIFORM
)||
1902 inst
->dst
.type
!= inst
->src
[0].type
)
1905 bool has_source_modifiers
= (inst
->src
[0].abs
||
1906 inst
->src
[0].negate
||
1907 inst
->src
[0].file
== UNIFORM
);
1909 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
1910 * them: check for no writes to either one until the exit of the
1913 bool interfered
= false;
1915 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->next
;
1916 !scan_inst
->is_tail_sentinel();
1917 scan_inst
= (fs_inst
*)scan_inst
->next
) {
1918 if (scan_inst
->dst
.file
== GRF
) {
1919 if (scan_inst
->overwrites_reg(inst
->dst
) ||
1920 scan_inst
->overwrites_reg(inst
->src
[0])) {
1926 /* The gen6 MATH instruction can't handle source modifiers or
1927 * unusual register regions, so avoid coalescing those for
1928 * now. We should do something more specific.
1930 if (has_source_modifiers
&& !can_do_source_mods(scan_inst
)) {
1935 /* The accumulator result appears to get used for the
1936 * conditional modifier generation. When negating a UD
1937 * value, there is a 33rd bit generated for the sign in the
1938 * accumulator value, so now you can't check, for example,
1939 * equality with a 32-bit value. See piglit fs-op-neg-uint.
1941 if (scan_inst
->conditional_mod
&&
1942 inst
->src
[0].negate
&&
1943 inst
->src
[0].type
== BRW_REGISTER_TYPE_UD
) {
1952 /* Rewrite the later usage to point at the source of the move to
1955 for (fs_inst
*scan_inst
= inst
;
1956 !scan_inst
->is_tail_sentinel();
1957 scan_inst
= (fs_inst
*)scan_inst
->next
) {
1958 for (int i
= 0; i
< 3; i
++) {
1959 if (scan_inst
->src
[i
].file
== GRF
&&
1960 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
1961 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
1962 fs_reg new_src
= inst
->src
[0];
1963 if (scan_inst
->src
[i
].abs
) {
1967 new_src
.negate
^= scan_inst
->src
[i
].negate
;
1968 scan_inst
->src
[i
] = new_src
;
1978 live_intervals_valid
= false;
1985 fs_visitor::compute_to_mrf()
1987 bool progress
= false;
1990 calculate_live_intervals();
1992 foreach_list_safe(node
, &this->instructions
) {
1993 fs_inst
*inst
= (fs_inst
*)node
;
1998 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2000 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2001 inst
->dst
.type
!= inst
->src
[0].type
||
2002 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
2005 /* Work out which hardware MRF registers are written by this
2008 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2010 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2011 mrf_high
= mrf_low
+ 4;
2012 } else if (dispatch_width
== 16 &&
2013 (!inst
->force_uncompressed
&& !inst
->force_sechalf
)) {
2014 mrf_high
= mrf_low
+ 1;
2019 /* Can't compute-to-MRF this GRF if someone else was going to
2022 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
2025 /* Found a move of a GRF to a MRF. Let's see if we can go
2026 * rewrite the thing that made this GRF to write into the MRF.
2029 for (scan_inst
= (fs_inst
*)inst
->prev
;
2030 scan_inst
->prev
!= NULL
;
2031 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2032 if (scan_inst
->dst
.file
== GRF
&&
2033 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2034 /* Found the last thing to write our reg we want to turn
2035 * into a compute-to-MRF.
2038 /* SENDs can only write to GRFs, so no compute-to-MRF. */
2039 if (scan_inst
->mlen
) {
2043 /* If it's predicated, it (probably) didn't populate all
2044 * the channels. We might be able to rewrite everything
2045 * that writes that reg, but it would require smarter
2046 * tracking to delay the rewriting until complete success.
2048 if (scan_inst
->predicate
)
2051 /* If it's half of register setup and not the same half as
2052 * our MOV we're trying to remove, bail for now.
2054 if (scan_inst
->force_uncompressed
!= inst
->force_uncompressed
||
2055 scan_inst
->force_sechalf
!= inst
->force_sechalf
) {
2059 /* SEND instructions can't have MRF as a destination. */
2060 if (scan_inst
->mlen
)
2063 if (intel
->gen
>= 6) {
2064 /* gen6 math instructions must have the destination be
2065 * GRF, so no compute-to-MRF for them.
2067 if (scan_inst
->is_math()) {
2072 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2073 /* Found the creator of our MRF's source value. */
2074 scan_inst
->dst
.file
= MRF
;
2075 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2076 scan_inst
->saturate
|= inst
->saturate
;
2083 /* We don't handle flow control here. Most computation of
2084 * values that end up in MRFs are shortly before the MRF
2087 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2088 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2089 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2090 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2094 /* You can't read from an MRF, so if someone else reads our
2095 * MRF's source GRF that we wanted to rewrite, that stops us.
2097 bool interfered
= false;
2098 for (int i
= 0; i
< 3; i
++) {
2099 if (scan_inst
->src
[i
].file
== GRF
&&
2100 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2101 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2108 if (scan_inst
->dst
.file
== MRF
) {
2109 /* If somebody else writes our MRF here, we can't
2110 * compute-to-MRF before that.
2112 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2115 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2116 scan_mrf_high
= scan_mrf_low
+ 4;
2117 } else if (dispatch_width
== 16 &&
2118 (!scan_inst
->force_uncompressed
&&
2119 !scan_inst
->force_sechalf
)) {
2120 scan_mrf_high
= scan_mrf_low
+ 1;
2122 scan_mrf_high
= scan_mrf_low
;
2125 if (mrf_low
== scan_mrf_low
||
2126 mrf_low
== scan_mrf_high
||
2127 mrf_high
== scan_mrf_low
||
2128 mrf_high
== scan_mrf_high
) {
2133 if (scan_inst
->mlen
> 0) {
2134 /* Found a SEND instruction, which means that there are
2135 * live values in MRFs from base_mrf to base_mrf +
2136 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2139 if (mrf_low
>= scan_inst
->base_mrf
&&
2140 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2143 if (mrf_high
>= scan_inst
->base_mrf
&&
2144 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2152 live_intervals_valid
= false;
2158 * Walks through basic blocks, looking for repeated MRF writes and
2159 * removing the later ones.
2162 fs_visitor::remove_duplicate_mrf_writes()
2164 fs_inst
*last_mrf_move
[16];
2165 bool progress
= false;
2167 /* Need to update the MRF tracking for compressed instructions. */
2168 if (dispatch_width
== 16)
2171 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2173 foreach_list_safe(node
, &this->instructions
) {
2174 fs_inst
*inst
= (fs_inst
*)node
;
2176 switch (inst
->opcode
) {
2178 case BRW_OPCODE_WHILE
:
2180 case BRW_OPCODE_ELSE
:
2181 case BRW_OPCODE_ENDIF
:
2182 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2188 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2189 inst
->dst
.file
== MRF
) {
2190 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2191 if (prev_inst
&& inst
->equals(prev_inst
)) {
2198 /* Clear out the last-write records for MRFs that were overwritten. */
2199 if (inst
->dst
.file
== MRF
) {
2200 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2203 if (inst
->mlen
> 0) {
2204 /* Found a SEND instruction, which will include two or fewer
2205 * implied MRF writes. We could do better here.
2207 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2208 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2212 /* Clear out any MRF move records whose sources got overwritten. */
2213 if (inst
->dst
.file
== GRF
) {
2214 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
2215 if (last_mrf_move
[i
] &&
2216 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2217 last_mrf_move
[i
] = NULL
;
2222 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2223 inst
->dst
.file
== MRF
&&
2224 inst
->src
[0].file
== GRF
&&
2226 last_mrf_move
[inst
->dst
.reg
] = inst
;
2231 live_intervals_valid
= false;
2237 fs_visitor::dump_instruction(fs_inst
*inst
)
2239 if (inst
->predicate
) {
2240 printf("(%cf0.%d) ",
2241 inst
->predicate_inverse
? '-' : '+',
2245 if (inst
->opcode
< ARRAY_SIZE(opcode_descs
) &&
2246 opcode_descs
[inst
->opcode
].name
) {
2247 printf("%s", opcode_descs
[inst
->opcode
].name
);
2249 printf("op%d", inst
->opcode
);
2253 if (inst
->conditional_mod
) {
2255 if (!inst
->predicate
&&
2256 (intel
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
2257 inst
->opcode
!= BRW_OPCODE_IF
&&
2258 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
2259 printf(".f0.%d\n", inst
->flag_subreg
);
2265 switch (inst
->dst
.file
) {
2267 printf("vgrf%d", inst
->dst
.reg
);
2268 if (inst
->dst
.reg_offset
)
2269 printf("+%d", inst
->dst
.reg_offset
);
2272 printf("m%d", inst
->dst
.reg
);
2278 printf("***u%d***", inst
->dst
.reg
);
2286 for (int i
= 0; i
< 3; i
++) {
2287 if (inst
->src
[i
].negate
)
2289 if (inst
->src
[i
].abs
)
2291 switch (inst
->src
[i
].file
) {
2293 printf("vgrf%d", inst
->src
[i
].reg
);
2294 if (inst
->src
[i
].reg_offset
)
2295 printf("+%d", inst
->src
[i
].reg_offset
);
2298 printf("***m%d***", inst
->src
[i
].reg
);
2301 printf("u%d", inst
->src
[i
].reg
);
2302 if (inst
->src
[i
].reg_offset
)
2303 printf(".%d", inst
->src
[i
].reg_offset
);
2312 if (inst
->src
[i
].abs
)
2321 if (inst
->force_uncompressed
)
2324 if (inst
->force_sechalf
)
2331 fs_visitor::dump_instructions()
2334 foreach_list(node
, &this->instructions
) {
2335 fs_inst
*inst
= (fs_inst
*)node
;
2336 printf("%d: ", ip
++);
2337 dump_instruction(inst
);
2342 * Possibly returns an instruction that set up @param reg.
2344 * Sometimes we want to take the result of some expression/variable
2345 * dereference tree and rewrite the instruction generating the result
2346 * of the tree. When processing the tree, we know that the
2347 * instructions generated are all writing temporaries that are dead
2348 * outside of this tree. So, if we have some instructions that write
2349 * a temporary, we're free to point that temp write somewhere else.
2351 * Note that this doesn't guarantee that the instruction generated
2352 * only reg -- it might be the size=4 destination of a texture instruction.
2355 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
2361 end
->force_uncompressed
||
2362 end
->force_sechalf
||
2364 !reg
.equals(end
->dst
)) {
2372 fs_visitor::setup_payload_gen6()
2374 struct intel_context
*intel
= &brw
->intel
;
2376 (fp
->Base
.InputsRead
& (1 << FRAG_ATTRIB_WPOS
)) != 0;
2377 unsigned barycentric_interp_modes
= c
->prog_data
.barycentric_interp_modes
;
2379 assert(intel
->gen
>= 6);
2381 /* R0-1: masks, pixel X/Y coordinates. */
2382 c
->nr_payload_regs
= 2;
2383 /* R2: only for 32-pixel dispatch.*/
2385 /* R3-26: barycentric interpolation coordinates. These appear in the
2386 * same order that they appear in the brw_wm_barycentric_interp_mode
2387 * enum. Each set of coordinates occupies 2 registers if dispatch width
2388 * == 8 and 4 registers if dispatch width == 16. Coordinates only
2389 * appear if they were enabled using the "Barycentric Interpolation
2390 * Mode" bits in WM_STATE.
2392 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
2393 if (barycentric_interp_modes
& (1 << i
)) {
2394 c
->barycentric_coord_reg
[i
] = c
->nr_payload_regs
;
2395 c
->nr_payload_regs
+= 2;
2396 if (dispatch_width
== 16) {
2397 c
->nr_payload_regs
+= 2;
2402 /* R27: interpolated depth if uses source depth */
2404 c
->source_depth_reg
= c
->nr_payload_regs
;
2405 c
->nr_payload_regs
++;
2406 if (dispatch_width
== 16) {
2407 /* R28: interpolated depth if not 8-wide. */
2408 c
->nr_payload_regs
++;
2411 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
2413 c
->source_w_reg
= c
->nr_payload_regs
;
2414 c
->nr_payload_regs
++;
2415 if (dispatch_width
== 16) {
2416 /* R30: interpolated W if not 8-wide. */
2417 c
->nr_payload_regs
++;
2420 /* R31: MSAA position offsets. */
2421 /* R32-: bary for 32-pixel. */
2422 /* R58-59: interp W for 32-pixel. */
2424 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
2425 c
->source_depth_to_render_target
= true;
2432 sanity_param_count
= fp
->Base
.Parameters
->NumParameters
;
2433 uint32_t orig_nr_params
= c
->prog_data
.nr_params
;
2435 if (intel
->gen
>= 6)
2436 setup_payload_gen6();
2438 setup_payload_gen4();
2443 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2444 emit_shader_time_begin();
2446 calculate_urb_setup();
2448 emit_interpolation_setup_gen4();
2450 emit_interpolation_setup_gen6();
2452 /* We handle discards by keeping track of the still-live pixels in f0.1.
2453 * Initialize it with the dispatched pixels.
2456 fs_inst
*discard_init
= emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
2457 discard_init
->flag_subreg
= 1;
2460 /* Generate FS IR for main(). (the visitor only descends into
2461 * functions called "main").
2464 foreach_list(node
, &*shader
->ir
) {
2465 ir_instruction
*ir
= (ir_instruction
*)node
;
2467 this->result
= reg_undef
;
2471 emit_fragment_program_code();
2477 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2478 emit_shader_time_end();
2482 split_virtual_grfs();
2484 move_uniform_array_access_to_pull_constants();
2485 setup_pull_constants();
2491 compact_virtual_grfs();
2493 progress
= remove_duplicate_mrf_writes() || progress
;
2495 progress
= opt_algebraic() || progress
;
2496 progress
= opt_cse() || progress
;
2497 progress
= opt_copy_propagate() || progress
;
2498 progress
= dead_code_eliminate() || progress
;
2499 progress
= register_coalesce() || progress
;
2500 progress
= register_coalesce_2() || progress
;
2501 progress
= compute_to_mrf() || progress
;
2504 remove_dead_constants();
2506 schedule_instructions(false);
2508 assign_curb_setup();
2512 /* Debug of register spilling: Go spill everything. */
2513 for (int i
= 0; i
< virtual_grf_count
; i
++) {
2519 assign_regs_trivial();
2521 while (!assign_regs()) {
2527 assert(force_uncompressed_stack
== 0);
2528 assert(force_sechalf_stack
== 0);
2533 schedule_instructions(true);
2535 if (dispatch_width
== 8) {
2536 c
->prog_data
.reg_blocks
= brw_register_blocks(grf_used
);
2538 c
->prog_data
.reg_blocks_16
= brw_register_blocks(grf_used
);
2540 /* Make sure we didn't try to sneak in an extra uniform */
2541 assert(orig_nr_params
== c
->prog_data
.nr_params
);
2542 (void) orig_nr_params
;
2545 /* If any state parameters were appended, then ParameterValues could have
2546 * been realloced, in which case the driver uniform storage set up by
2547 * _mesa_associate_uniform_storage() would point to freed memory. Make
2548 * sure that didn't happen.
2550 assert(sanity_param_count
== fp
->Base
.Parameters
->NumParameters
);
2556 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
,
2557 struct gl_fragment_program
*fp
,
2558 struct gl_shader_program
*prog
,
2559 unsigned *final_assembly_size
)
2561 struct intel_context
*intel
= &brw
->intel
;
2562 bool start_busy
= false;
2563 float start_time
= 0;
2565 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
2566 start_busy
= (intel
->batch
.last_bo
&&
2567 drm_intel_bo_busy(intel
->batch
.last_bo
));
2568 start_time
= get_time();
2571 struct brw_shader
*shader
= NULL
;
2573 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
2575 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
2577 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
2578 _mesa_print_ir(shader
->ir
, NULL
);
2581 printf("ARB_fragment_program %d ir for native fragment shader\n",
2583 _mesa_print_program(&fp
->Base
);
2587 /* Now the main event: Visit the shader IR and generate our FS IR for it.
2589 fs_visitor
v(brw
, c
, prog
, fp
, 8);
2591 prog
->LinkStatus
= false;
2592 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
2594 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
2600 exec_list
*simd16_instructions
= NULL
;
2601 fs_visitor
v2(brw
, c
, prog
, fp
, 16);
2602 if (intel
->gen
>= 5 && c
->prog_data
.nr_pull_params
== 0) {
2603 v2
.import_uniforms(&v
);
2605 perf_debug("16-wide shader failed to compile, falling back to "
2606 "8-wide at a 10-20%% performance cost: %s", v2
.fail_msg
);
2608 simd16_instructions
= &v2
.instructions
;
2612 c
->prog_data
.dispatch_width
= 8;
2614 fs_generator
g(brw
, c
, prog
, fp
, v
.dual_src_output
.file
!= BAD_FILE
);
2615 const unsigned *generated
= g
.generate_assembly(&v
.instructions
,
2616 simd16_instructions
,
2617 final_assembly_size
);
2619 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
) && shader
) {
2620 if (shader
->compiled_once
)
2621 brw_wm_debug_recompile(brw
, prog
, &c
->key
);
2622 shader
->compiled_once
= true;
2624 if (start_busy
&& !drm_intel_bo_busy(intel
->batch
.last_bo
)) {
2625 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
2626 (get_time() - start_time
) * 1000);
2634 brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
2636 struct brw_context
*brw
= brw_context(ctx
);
2637 struct intel_context
*intel
= &brw
->intel
;
2638 struct brw_wm_prog_key key
;
2640 if (!prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
])
2643 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)
2644 prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
]->Program
;
2645 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
2646 bool program_uses_dfdy
= fp
->UsesDFdy
;
2648 memset(&key
, 0, sizeof(key
));
2650 if (intel
->gen
< 6) {
2652 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
2654 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
2655 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
2657 /* Just assume depth testing. */
2658 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
2659 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
2662 if (prog
->Name
!= 0)
2663 key
.proj_attrib_mask
= 0xffffffff;
2666 key
.vp_outputs_written
|= BITFIELD64_BIT(FRAG_ATTRIB_WPOS
);
2668 for (int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2669 if (!(fp
->Base
.InputsRead
& BITFIELD64_BIT(i
)))
2672 if (prog
->Name
== 0)
2673 key
.proj_attrib_mask
|= 1 << i
;
2675 if (intel
->gen
< 6) {
2676 int vp_index
= _mesa_vert_result_to_frag_attrib((gl_vert_result
) i
);
2679 key
.vp_outputs_written
|= BITFIELD64_BIT(vp_index
);
2683 key
.clamp_fragment_color
= true;
2685 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
2686 if (fp
->Base
.ShadowSamplers
& (1 << i
)) {
2687 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
2688 key
.tex
.swizzles
[i
] =
2689 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
2691 /* Color sampler: assume no swizzling. */
2692 key
.tex
.swizzles
[i
] = SWIZZLE_XYZW
;
2696 if (fp
->Base
.InputsRead
& FRAG_BIT_WPOS
) {
2697 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
2700 if ((fp
->Base
.InputsRead
& FRAG_BIT_WPOS
) || program_uses_dfdy
) {
2701 key
.render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2704 key
.nr_color_regions
= 1;
2706 key
.program_string_id
= bfp
->id
;
2708 uint32_t old_prog_offset
= brw
->wm
.prog_offset
;
2709 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
2711 bool success
= do_wm_prog(brw
, prog
, bfp
, &key
);
2713 brw
->wm
.prog_offset
= old_prog_offset
;
2714 brw
->wm
.prog_data
= old_prog_data
;