2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
32 #include "brw_context.h"
37 #include "brw_vec4_gs_visitor.h"
39 #include "brw_program.h"
40 #include "brw_dead_control_flow.h"
41 #include "compiler/glsl_types.h"
42 #include "program/prog_parameter.h"
47 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
48 const fs_reg
*src
, unsigned sources
)
50 memset(this, 0, sizeof(*this));
52 this->src
= new fs_reg
[MAX2(sources
, 3)];
53 for (unsigned i
= 0; i
< sources
; i
++)
54 this->src
[i
] = src
[i
];
56 this->opcode
= opcode
;
58 this->sources
= sources
;
59 this->exec_size
= exec_size
;
61 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
63 assert(this->exec_size
!= 0);
65 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
67 /* This will be the case for almost all instructions. */
74 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
78 this->regs_written
= 0;
82 unreachable("Invalid destination register file");
85 this->writes_accumulator
= false;
90 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
93 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
95 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
98 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
100 init(opcode
, exec_size
, dst
, NULL
, 0);
103 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
106 const fs_reg src
[1] = { src0
};
107 init(opcode
, exec_size
, dst
, src
, 1);
110 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
111 const fs_reg
&src0
, const fs_reg
&src1
)
113 const fs_reg src
[2] = { src0
, src1
};
114 init(opcode
, exec_size
, dst
, src
, 2);
117 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
118 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
120 const fs_reg src
[3] = { src0
, src1
, src2
};
121 init(opcode
, exec_size
, dst
, src
, 3);
124 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
125 const fs_reg src
[], unsigned sources
)
127 init(opcode
, exec_width
, dst
, src
, sources
);
130 fs_inst::fs_inst(const fs_inst
&that
)
132 memcpy(this, &that
, sizeof(that
));
134 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
136 for (unsigned i
= 0; i
< that
.sources
; i
++)
137 this->src
[i
] = that
.src
[i
];
146 fs_inst::resize_sources(uint8_t num_sources
)
148 if (this->sources
!= num_sources
) {
149 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
151 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
152 src
[i
] = this->src
[i
];
156 this->sources
= num_sources
;
161 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
163 const fs_reg
&surf_index
,
164 const fs_reg
&varying_offset
,
165 uint32_t const_offset
)
167 /* We have our constant surface use a pitch of 4 bytes, so our index can
168 * be any component of a vector, and then we load 4 contiguous
169 * components starting from that.
171 * We break down the const_offset to a portion added to the variable
172 * offset and a portion done using reg_offset, which means that if you
173 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
174 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
175 * CSE can later notice that those loads are all the same and eliminate
176 * the redundant ones.
178 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
179 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
181 /* The pull load message will load a vec4 (16 bytes). If we are loading
182 * a double this means we are only loading 2 elements worth of data.
183 * We also want to use a 32-bit data type for the dst of the load operation
184 * so other parts of the driver don't get confused about the size of the
187 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
188 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
189 vec4_result
, surf_index
, vec4_offset
);
190 inst
->regs_written
= 4 * bld
.dispatch_width() / 8;
192 if (type_sz(dst
.type
) == 8) {
193 shuffle_32bit_load_result_to_64bit_data(
194 bld
, retype(vec4_result
, dst
.type
), vec4_result
, 2);
197 vec4_result
.type
= dst
.type
;
198 bld
.MOV(dst
, offset(vec4_result
, bld
,
199 (const_offset
& 0xf) / type_sz(vec4_result
.type
)));
203 * A helper for MOV generation for fixing up broken hardware SEND dependency
207 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
209 /* The caller always wants uncompressed to emit the minimal extra
210 * dependencies, and to avoid having to deal with aligning its regs to 2.
212 const fs_builder ubld
= bld
.annotate("send dependency resolve")
215 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
219 fs_inst::equals(fs_inst
*inst
) const
221 return (opcode
== inst
->opcode
&&
222 dst
.equals(inst
->dst
) &&
223 src
[0].equals(inst
->src
[0]) &&
224 src
[1].equals(inst
->src
[1]) &&
225 src
[2].equals(inst
->src
[2]) &&
226 saturate
== inst
->saturate
&&
227 predicate
== inst
->predicate
&&
228 conditional_mod
== inst
->conditional_mod
&&
229 mlen
== inst
->mlen
&&
230 base_mrf
== inst
->base_mrf
&&
231 target
== inst
->target
&&
233 header_size
== inst
->header_size
&&
234 shadow_compare
== inst
->shadow_compare
&&
235 exec_size
== inst
->exec_size
&&
236 offset
== inst
->offset
);
240 fs_inst::overwrites_reg(const fs_reg
®
) const
242 return reg
.in_range(dst
, regs_written
);
246 fs_inst::is_send_from_grf() const
249 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
250 case SHADER_OPCODE_SHADER_TIME_ADD
:
251 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
252 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
253 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
254 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
255 case SHADER_OPCODE_UNTYPED_ATOMIC
:
256 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
257 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
258 case SHADER_OPCODE_TYPED_ATOMIC
:
259 case SHADER_OPCODE_TYPED_SURFACE_READ
:
260 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
261 case SHADER_OPCODE_URB_WRITE_SIMD8
:
262 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
263 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
264 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
265 case SHADER_OPCODE_URB_READ_SIMD8
:
266 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
268 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
269 return src
[1].file
== VGRF
;
270 case FS_OPCODE_FB_WRITE
:
271 return src
[0].file
== VGRF
;
274 return src
[0].file
== VGRF
;
281 * Returns true if this instruction's sources and destinations cannot
282 * safely be the same register.
284 * In most cases, a register can be written over safely by the same
285 * instruction that is its last use. For a single instruction, the
286 * sources are dereferenced before writing of the destination starts
289 * However, there are a few cases where this can be problematic:
291 * - Virtual opcodes that translate to multiple instructions in the
292 * code generator: if src == dst and one instruction writes the
293 * destination before a later instruction reads the source, then
294 * src will have been clobbered.
296 * - SIMD16 compressed instructions with certain regioning (see below).
298 * The register allocator uses this information to set up conflicts between
299 * GRF sources and the destination.
302 fs_inst::has_source_and_destination_hazard() const
305 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
306 /* Multiple partial writes to the destination */
309 /* The SIMD16 compressed instruction
311 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
313 * is actually decoded in hardware as:
315 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
316 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
318 * Which is safe. However, if we have uniform accesses
319 * happening, we get into trouble:
321 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
322 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
324 * Now our destination for the first instruction overwrote the
325 * second instruction's src0, and we get garbage for those 8
326 * pixels. There's a similar issue for the pre-gen6
327 * pixel_x/pixel_y, which are registers of 16-bit values and thus
328 * would get stomped by the first decode as well.
330 if (exec_size
== 16) {
331 for (int i
= 0; i
< sources
; i
++) {
332 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
333 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
334 src
[i
].type
== BRW_REGISTER_TYPE_W
||
335 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
336 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
346 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
348 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
351 fs_reg reg
= this->src
[0];
352 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
355 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
358 for (int i
= 0; i
< this->sources
; i
++) {
359 reg
.type
= this->src
[i
].type
;
360 if (!this->src
[i
].equals(reg
))
363 if (i
< this->header_size
) {
366 reg
= horiz_offset(reg
, this->exec_size
);
374 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
376 if (devinfo
->gen
== 6 && is_math())
379 if (is_send_from_grf())
382 if (!backend_instruction::can_do_source_mods())
389 fs_inst::can_change_types() const
391 return dst
.type
== src
[0].type
&&
392 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
393 (opcode
== BRW_OPCODE_MOV
||
394 (opcode
== BRW_OPCODE_SEL
&&
395 dst
.type
== src
[1].type
&&
396 predicate
!= BRW_PREDICATE_NONE
&&
397 !src
[1].abs
&& !src
[1].negate
));
401 fs_inst::has_side_effects() const
403 return this->eot
|| backend_instruction::has_side_effects();
409 memset(this, 0, sizeof(*this));
413 /** Generic unset register constructor. */
417 this->file
= BAD_FILE
;
420 fs_reg::fs_reg(struct ::brw_reg reg
) :
423 this->reg_offset
= 0;
424 this->subreg_offset
= 0;
426 if (this->file
== IMM
&&
427 (this->type
!= BRW_REGISTER_TYPE_V
&&
428 this->type
!= BRW_REGISTER_TYPE_UV
&&
429 this->type
!= BRW_REGISTER_TYPE_VF
)) {
435 fs_reg::equals(const fs_reg
&r
) const
437 return (this->backend_reg::equals(r
) &&
438 subreg_offset
== r
.subreg_offset
&&
443 fs_reg::set_smear(unsigned subreg
)
445 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
446 subreg_offset
= subreg
* type_sz(type
);
452 fs_reg::is_contiguous() const
458 fs_reg::component_size(unsigned width
) const
460 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
463 return MAX2(width
* stride
, 1) * type_sz(type
);
467 type_size_scalar(const struct glsl_type
*type
)
469 unsigned int size
, i
;
471 switch (type
->base_type
) {
474 case GLSL_TYPE_FLOAT
:
476 return type
->components();
477 case GLSL_TYPE_DOUBLE
:
478 return type
->components() * 2;
479 case GLSL_TYPE_ARRAY
:
480 return type_size_scalar(type
->fields
.array
) * type
->length
;
481 case GLSL_TYPE_STRUCT
:
483 for (i
= 0; i
< type
->length
; i
++) {
484 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
487 case GLSL_TYPE_SAMPLER
:
488 /* Samplers take up no register space, since they're baked in at
492 case GLSL_TYPE_ATOMIC_UINT
:
494 case GLSL_TYPE_SUBROUTINE
:
496 case GLSL_TYPE_IMAGE
:
497 return BRW_IMAGE_PARAM_SIZE
;
499 case GLSL_TYPE_ERROR
:
500 case GLSL_TYPE_INTERFACE
:
501 case GLSL_TYPE_FUNCTION
:
502 unreachable("not reached");
509 * Returns the number of scalar components needed to store type, assuming
510 * that vectors are padded out to vec4.
512 * This has the packing rules of type_size_vec4(), but counts components
513 * similar to type_size_scalar().
516 type_size_vec4_times_4(const struct glsl_type
*type
)
518 return 4 * type_size_vec4(type
);
521 /* Attribute arrays are loaded as one vec4 per element (or matrix column),
522 * except for double-precision types, which are loaded as one dvec4.
525 type_size_vs_input(const struct glsl_type
*type
)
527 if (type
->is_double()) {
528 return type_size_dvec4(type
);
530 return type_size_vec4(type
);
535 * Create a MOV to read the timestamp register.
537 * The caller is responsible for emitting the MOV. The return value is
538 * the destination of the MOV, with extra parameters set.
541 fs_visitor::get_timestamp(const fs_builder
&bld
)
543 assert(devinfo
->gen
>= 7);
545 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
548 BRW_REGISTER_TYPE_UD
));
550 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
552 /* We want to read the 3 fields we care about even if it's not enabled in
555 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
561 fs_visitor::emit_shader_time_begin()
563 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
565 /* We want only the low 32 bits of the timestamp. Since it's running
566 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
567 * which is plenty of time for our purposes. It is identical across the
568 * EUs, but since it's tracking GPU core speed it will increment at a
569 * varying rate as render P-states change.
571 shader_start_time
.set_smear(0);
575 fs_visitor::emit_shader_time_end()
577 /* Insert our code just before the final SEND with EOT. */
578 exec_node
*end
= this->instructions
.get_tail();
579 assert(end
&& ((fs_inst
*) end
)->eot
);
580 const fs_builder ibld
= bld
.annotate("shader time end")
581 .exec_all().at(NULL
, end
);
583 fs_reg shader_end_time
= get_timestamp(ibld
);
585 /* We only use the low 32 bits of the timestamp - see
586 * emit_shader_time_begin()).
588 * We could also check if render P-states have changed (or anything
589 * else that might disrupt timing) by setting smear to 2 and checking if
590 * that field is != 0.
592 shader_end_time
.set_smear(0);
594 /* Check that there weren't any timestamp reset events (assuming these
595 * were the only two timestamp reads that happened).
597 fs_reg reset
= shader_end_time
;
599 set_condmod(BRW_CONDITIONAL_Z
,
600 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
601 ibld
.IF(BRW_PREDICATE_NORMAL
);
603 fs_reg start
= shader_start_time
;
605 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
608 const fs_builder cbld
= ibld
.group(1, 0);
609 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
611 /* If there were no instructions between the two timestamp gets, the diff
612 * is 2 cycles. Remove that overhead, so I can forget about that when
613 * trying to determine the time taken for single instructions.
615 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
616 SHADER_TIME_ADD(cbld
, 0, diff
);
617 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
618 ibld
.emit(BRW_OPCODE_ELSE
);
619 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
620 ibld
.emit(BRW_OPCODE_ENDIF
);
624 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
625 int shader_time_subindex
,
628 int index
= shader_time_index
* 3 + shader_time_subindex
;
629 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
632 if (dispatch_width
== 8)
633 payload
= vgrf(glsl_type::uvec2_type
);
635 payload
= vgrf(glsl_type::uint_type
);
637 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
641 fs_visitor::vfail(const char *format
, va_list va
)
650 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
651 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
653 this->fail_msg
= msg
;
656 fprintf(stderr
, "%s", msg
);
661 fs_visitor::fail(const char *format
, ...)
665 va_start(va
, format
);
671 * Mark this program as impossible to compile with dispatch width greater
674 * During the SIMD8 compile (which happens first), we can detect and flag
675 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
676 * SIMD16+ compile altogether.
678 * During a compile of dispatch width greater than n (if one happens anyway),
679 * this just calls fail().
682 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
684 if (dispatch_width
> n
) {
687 max_dispatch_width
= n
;
688 compiler
->shader_perf_log(log_data
,
689 "Shader dispatch width limited to SIMD%d: %s",
695 * Returns true if the instruction has a flag that means it won't
696 * update an entire destination register.
698 * For example, dead code elimination and live variable analysis want to know
699 * when a write to a variable screens off any preceding values that were in
703 fs_inst::is_partial_write() const
705 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
706 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
707 !this->dst
.is_contiguous() ||
708 this->dst
.subreg_offset
> 0);
712 fs_inst::components_read(unsigned i
) const
715 case FS_OPCODE_LINTERP
:
721 case FS_OPCODE_PIXEL_X
:
722 case FS_OPCODE_PIXEL_Y
:
726 case FS_OPCODE_FB_WRITE_LOGICAL
:
727 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
728 /* First/second FB write color. */
730 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
734 case SHADER_OPCODE_TEX_LOGICAL
:
735 case SHADER_OPCODE_TXD_LOGICAL
:
736 case SHADER_OPCODE_TXF_LOGICAL
:
737 case SHADER_OPCODE_TXL_LOGICAL
:
738 case SHADER_OPCODE_TXS_LOGICAL
:
739 case FS_OPCODE_TXB_LOGICAL
:
740 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
741 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
742 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
743 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
744 case SHADER_OPCODE_LOD_LOGICAL
:
745 case SHADER_OPCODE_TG4_LOGICAL
:
746 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
747 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
748 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
749 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
750 /* Texture coordinates. */
751 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
752 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
753 /* Texture derivatives. */
754 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
755 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
756 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
757 /* Texture offset. */
758 else if (i
== TEX_LOGICAL_SRC_OFFSET_VALUE
)
761 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
766 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
767 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
768 assert(src
[3].file
== IMM
);
769 /* Surface coordinates. */
772 /* Surface operation source (ignored for reads). */
778 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
779 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
780 assert(src
[3].file
== IMM
&&
782 /* Surface coordinates. */
785 /* Surface operation source. */
791 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
792 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
793 assert(src
[3].file
== IMM
&&
795 const unsigned op
= src
[4].ud
;
796 /* Surface coordinates. */
799 /* Surface operation source. */
800 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
802 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
803 op
== BRW_AOP_PREDEC
))
815 fs_inst::regs_read(int arg
) const
818 case FS_OPCODE_FB_WRITE
:
819 case SHADER_OPCODE_URB_WRITE_SIMD8
:
820 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
821 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
822 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
823 case SHADER_OPCODE_URB_READ_SIMD8
:
824 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
825 case SHADER_OPCODE_UNTYPED_ATOMIC
:
826 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
827 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
828 case SHADER_OPCODE_TYPED_ATOMIC
:
829 case SHADER_OPCODE_TYPED_SURFACE_READ
:
830 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
831 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
836 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
837 /* The payload is actually stored in src1 */
842 case FS_OPCODE_LINTERP
:
847 case SHADER_OPCODE_LOAD_PAYLOAD
:
848 if (arg
< this->header_size
)
852 case CS_OPCODE_CS_TERMINATE
:
853 case SHADER_OPCODE_BARRIER
:
856 case SHADER_OPCODE_MOV_INDIRECT
:
858 assert(src
[2].file
== IMM
);
859 unsigned region_length
= src
[2].ud
;
861 if (src
[0].file
== UNIFORM
) {
862 assert(region_length
% 4 == 0);
863 return region_length
/ 4;
864 } else if (src
[0].file
== FIXED_GRF
) {
865 /* If the start of the region is not register aligned, then
866 * there's some portion of the register that's technically
867 * unread at the beginning.
869 * However, the register allocator works in terms of whole
870 * registers, and does not use subnr. It assumes that the
871 * read starts at the beginning of the register, and extends
872 * regs_read() whole registers beyond that.
874 * To compensate, we extend the region length to include this
875 * unread portion at the beginning.
878 region_length
+= src
[0].subnr
;
880 return DIV_ROUND_UP(region_length
, REG_SIZE
);
882 assert(!"Invalid register file");
888 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
893 switch (src
[arg
].file
) {
903 return DIV_ROUND_UP(components_read(arg
) *
904 src
[arg
].component_size(exec_size
),
907 unreachable("MRF registers are not allowed as sources");
913 /* Return the subset of flag registers that an instruction could
914 * potentially read or write based on the execution controls and flag
915 * subregister number of the instruction.
918 flag_mask(const fs_inst
*inst
)
920 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
921 const unsigned end
= start
+ inst
->exec_size
;
922 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
927 fs_inst::flags_read(const brw_device_info
*devinfo
) const
929 /* XXX - This doesn't consider explicit uses of the flag register as source
932 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
933 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
934 /* The vertical predication modes combine corresponding bits from
935 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
937 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
938 return flag_mask(this) << shift
| flag_mask(this);
939 } else if (predicate
) {
940 return flag_mask(this);
947 fs_inst::flags_written() const
949 /* XXX - This doesn't consider explicit uses of the flag register as
950 * destination region.
952 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
953 opcode
!= BRW_OPCODE_IF
&&
954 opcode
!= BRW_OPCODE_WHILE
)) ||
955 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
956 return flag_mask(this);
963 * Returns how many MRFs an FS opcode will write over.
965 * Note that this is not the 0 or 1 implied writes in an actual gen
966 * instruction -- the FS opcodes often generate MOVs in addition.
969 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
974 if (inst
->base_mrf
== -1)
977 switch (inst
->opcode
) {
978 case SHADER_OPCODE_RCP
:
979 case SHADER_OPCODE_RSQ
:
980 case SHADER_OPCODE_SQRT
:
981 case SHADER_OPCODE_EXP2
:
982 case SHADER_OPCODE_LOG2
:
983 case SHADER_OPCODE_SIN
:
984 case SHADER_OPCODE_COS
:
985 return 1 * dispatch_width
/ 8;
986 case SHADER_OPCODE_POW
:
987 case SHADER_OPCODE_INT_QUOTIENT
:
988 case SHADER_OPCODE_INT_REMAINDER
:
989 return 2 * dispatch_width
/ 8;
990 case SHADER_OPCODE_TEX
:
992 case SHADER_OPCODE_TXD
:
993 case SHADER_OPCODE_TXF
:
994 case SHADER_OPCODE_TXF_LZ
:
995 case SHADER_OPCODE_TXF_CMS
:
996 case SHADER_OPCODE_TXF_CMS_W
:
997 case SHADER_OPCODE_TXF_MCS
:
998 case SHADER_OPCODE_TG4
:
999 case SHADER_OPCODE_TG4_OFFSET
:
1000 case SHADER_OPCODE_TXL
:
1001 case SHADER_OPCODE_TXL_LZ
:
1002 case SHADER_OPCODE_TXS
:
1003 case SHADER_OPCODE_LOD
:
1004 case SHADER_OPCODE_SAMPLEINFO
:
1006 case FS_OPCODE_FB_WRITE
:
1008 case FS_OPCODE_GET_BUFFER_SIZE
:
1009 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1010 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1012 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
1014 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1016 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1017 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1018 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
1019 case SHADER_OPCODE_TYPED_ATOMIC
:
1020 case SHADER_OPCODE_TYPED_SURFACE_READ
:
1021 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
1022 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1023 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
1024 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
1025 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
1026 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
1027 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
1028 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
1029 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
1032 unreachable("not reached");
1037 fs_visitor::vgrf(const glsl_type
*const type
)
1039 int reg_width
= dispatch_width
/ 8;
1040 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
1041 brw_type_for_base_type(type
));
1044 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1049 this->type
= BRW_REGISTER_TYPE_F
;
1050 this->stride
= (file
== UNIFORM
? 0 : 1);
1053 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1059 this->stride
= (file
== UNIFORM
? 0 : 1);
1062 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1063 * This brings in those uniform definitions
1066 fs_visitor::import_uniforms(fs_visitor
*v
)
1068 this->push_constant_loc
= v
->push_constant_loc
;
1069 this->pull_constant_loc
= v
->pull_constant_loc
;
1070 this->uniforms
= v
->uniforms
;
1074 fs_visitor::emit_fragcoord_interpolation()
1076 assert(stage
== MESA_SHADER_FRAGMENT
);
1077 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
1080 /* gl_FragCoord.x */
1081 bld
.MOV(wpos
, this->pixel_x
);
1082 wpos
= offset(wpos
, bld
, 1);
1084 /* gl_FragCoord.y */
1085 bld
.MOV(wpos
, this->pixel_y
);
1086 wpos
= offset(wpos
, bld
, 1);
1088 /* gl_FragCoord.z */
1089 if (devinfo
->gen
>= 6) {
1090 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1092 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1093 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1094 interp_reg(VARYING_SLOT_POS
, 2));
1096 wpos
= offset(wpos
, bld
, 1);
1098 /* gl_FragCoord.w: Already set up in emit_interpolation */
1099 bld
.MOV(wpos
, this->wpos_w
);
1105 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1106 glsl_interp_qualifier interpolation_mode
,
1107 bool is_centroid
, bool is_sample
)
1109 brw_wm_barycentric_interp_mode barycoord_mode
;
1110 if (devinfo
->gen
>= 6) {
1112 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1113 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1115 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1116 } else if (is_sample
) {
1117 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1118 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1120 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1122 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1123 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1125 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1128 /* On Ironlake and below, there is only one interpolation mode.
1129 * Centroid interpolation doesn't mean anything on this hardware --
1130 * there is no multisampling.
1132 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1134 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1135 this->delta_xy
[barycoord_mode
], interp
);
1139 fs_visitor::emit_general_interpolation(fs_reg
*attr
, const char *name
,
1140 const glsl_type
*type
,
1141 glsl_interp_qualifier interpolation_mode
,
1142 int *location
, bool mod_centroid
,
1145 assert(stage
== MESA_SHADER_FRAGMENT
);
1146 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1147 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1149 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1151 *location
== VARYING_SLOT_COL0
|| *location
== VARYING_SLOT_COL1
;
1152 if (key
->flat_shade
&& is_gl_Color
) {
1153 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1155 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1159 if (type
->is_array() || type
->is_matrix()) {
1160 const glsl_type
*elem_type
= glsl_get_array_element(type
);
1161 const unsigned length
= glsl_get_length(type
);
1163 for (unsigned i
= 0; i
< length
; i
++) {
1164 emit_general_interpolation(attr
, name
, elem_type
, interpolation_mode
,
1165 location
, mod_centroid
, mod_sample
);
1167 } else if (type
->is_record()) {
1168 for (unsigned i
= 0; i
< type
->length
; i
++) {
1169 const glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
1170 emit_general_interpolation(attr
, name
, field_type
, interpolation_mode
,
1171 location
, mod_centroid
, mod_sample
);
1174 assert(type
->is_scalar() || type
->is_vector());
1176 if (prog_data
->urb_setup
[*location
] == -1) {
1177 /* If there's no incoming setup data for this slot, don't
1178 * emit interpolation for it.
1180 *attr
= offset(*attr
, bld
, type
->vector_elements
);
1185 attr
->type
= brw_type_for_base_type(type
->get_scalar_type());
1187 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1188 /* Constant interpolation (flat shading) case. The SF has
1189 * handed us defined values in only the constant offset
1190 * field of the setup reg.
1192 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1193 struct brw_reg interp
= interp_reg(*location
, i
);
1194 interp
= suboffset(interp
, 3);
1195 interp
.type
= attr
->type
;
1196 bld
.emit(FS_OPCODE_CINTERP
, *attr
, fs_reg(interp
));
1197 *attr
= offset(*attr
, bld
, 1);
1200 /* Smooth/noperspective interpolation case. */
1201 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1202 struct brw_reg interp
= interp_reg(*location
, i
);
1203 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1204 /* Get the pixel/sample mask into f0 so that we know
1205 * which pixels are lit. Then, for each channel that is
1206 * unlit, replace the centroid data with non-centroid
1209 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1212 inst
= emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1214 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1215 inst
->predicate_inverse
= true;
1216 if (devinfo
->has_pln
)
1217 inst
->no_dd_clear
= true;
1219 inst
= emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1220 mod_centroid
&& !key
->persample_interp
,
1221 mod_sample
|| key
->persample_interp
);
1222 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1223 inst
->predicate_inverse
= false;
1224 if (devinfo
->has_pln
)
1225 inst
->no_dd_check
= true;
1228 emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1229 mod_centroid
&& !key
->persample_interp
,
1230 mod_sample
|| key
->persample_interp
);
1232 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1233 bld
.MUL(*attr
, *attr
, this->pixel_w
);
1235 *attr
= offset(*attr
, bld
, 1);
1243 fs_visitor::emit_frontfacing_interpolation()
1245 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1247 if (devinfo
->gen
>= 6) {
1248 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1249 * a boolean result from this (~0/true or 0/false).
1251 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1252 * this task in only one instruction:
1253 * - a negation source modifier will flip the bit; and
1254 * - a W -> D type conversion will sign extend the bit into the high
1255 * word of the destination.
1257 * An ASR 15 fills the low word of the destination.
1259 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1262 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1264 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1265 * a boolean result from this (1/true or 0/false).
1267 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1268 * the negation source modifier to flip it. Unfortunately the SHR
1269 * instruction only operates on UD (or D with an abs source modifier)
1270 * sources without negation.
1272 * Instead, use ASR (which will give ~0/true or 0/false).
1274 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1277 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1284 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1286 assert(stage
== MESA_SHADER_FRAGMENT
);
1287 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1288 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1290 if (wm_prog_data
->persample_dispatch
) {
1291 /* Convert int_sample_pos to floating point */
1292 bld
.MOV(dst
, int_sample_pos
);
1293 /* Scale to the range [0, 1] */
1294 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1297 /* From ARB_sample_shading specification:
1298 * "When rendering to a non-multisample buffer, or if multisample
1299 * rasterization is disabled, gl_SamplePosition will always be
1302 bld
.MOV(dst
, brw_imm_f(0.5f
));
1307 fs_visitor::emit_samplepos_setup()
1309 assert(devinfo
->gen
>= 6);
1311 const fs_builder abld
= bld
.annotate("compute sample position");
1312 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1314 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1315 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1317 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1318 * mode will be enabled.
1320 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1321 * R31.1:0 Position Offset X/Y for Slot[3:0]
1322 * R31.3:2 Position Offset X/Y for Slot[7:4]
1325 * The X, Y sample positions come in as bytes in thread payload. So, read
1326 * the positions using vstride=16, width=8, hstride=2.
1328 struct brw_reg sample_pos_reg
=
1329 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1330 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1332 if (dispatch_width
== 8) {
1333 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1335 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1336 abld
.half(1).MOV(half(int_sample_x
, 1),
1337 fs_reg(suboffset(sample_pos_reg
, 16)));
1339 /* Compute gl_SamplePosition.x */
1340 compute_sample_position(pos
, int_sample_x
);
1341 pos
= offset(pos
, abld
, 1);
1342 if (dispatch_width
== 8) {
1343 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1345 abld
.half(0).MOV(half(int_sample_y
, 0),
1346 fs_reg(suboffset(sample_pos_reg
, 1)));
1347 abld
.half(1).MOV(half(int_sample_y
, 1),
1348 fs_reg(suboffset(sample_pos_reg
, 17)));
1350 /* Compute gl_SamplePosition.y */
1351 compute_sample_position(pos
, int_sample_y
);
1356 fs_visitor::emit_sampleid_setup()
1358 assert(stage
== MESA_SHADER_FRAGMENT
);
1359 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1360 assert(devinfo
->gen
>= 6);
1362 const fs_builder abld
= bld
.annotate("compute sample id");
1363 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1365 if (!key
->multisample_fbo
) {
1366 /* As per GL_ARB_sample_shading specification:
1367 * "When rendering to a non-multisample buffer, or if multisample
1368 * rasterization is disabled, gl_SampleID will always be zero."
1370 abld
.MOV(*reg
, brw_imm_d(0));
1371 } else if (devinfo
->gen
>= 8) {
1372 /* Sample ID comes in as 4-bit numbers in g1.0:
1374 * 15:12 Slot 3 SampleID (only used in SIMD16)
1375 * 11:8 Slot 2 SampleID (only used in SIMD16)
1376 * 7:4 Slot 1 SampleID
1377 * 3:0 Slot 0 SampleID
1379 * Each slot corresponds to four channels, so we want to replicate each
1380 * half-byte value to 4 channels in a row:
1382 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1383 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1385 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1386 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1388 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1389 * channels to read the first byte (7:0), and the second group of 8
1390 * channels to read the second byte (15:8). Then, we shift right by
1391 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1392 * values into place. Finally, we AND with 0xf to keep the low nibble.
1394 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1395 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1397 * TODO: These payload bits exist on Gen7 too, but they appear to always
1398 * be zero, so this code fails to work. We should find out why.
1400 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1402 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1403 BRW_REGISTER_TYPE_B
), 1, 8, 0)),
1404 brw_imm_v(0x44440000));
1405 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1407 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1409 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1411 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1412 * 8x multisampling, subspan 0 will represent sample N (where N
1413 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1414 * 7. We can find the value of N by looking at R0.0 bits 7:6
1415 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1416 * (since samples are always delivered in pairs). That is, we
1417 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1418 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1419 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1420 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1421 * populating a temporary variable with the sequence (0, 1, 2, 3),
1422 * and then reading from it using vstride=1, width=4, hstride=0.
1423 * These computations hold good for 4x multisampling as well.
1425 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1426 * the first four slots are sample 0 of subspan 0; the next four
1427 * are sample 1 of subspan 0; the third group is sample 0 of
1428 * subspan 1, and finally sample 1 of subspan 1.
1431 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1432 * accomodate 16x MSAA.
1434 abld
.exec_all().group(1, 0)
1435 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1437 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1439 /* This works for both SIMD8 and SIMD16 */
1440 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1442 /* This special instruction takes care of setting vstride=1,
1443 * width=4, hstride=0 of t2 during an ADD instruction.
1445 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1452 fs_visitor::emit_samplemaskin_setup()
1454 assert(stage
== MESA_SHADER_FRAGMENT
);
1455 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1456 assert(devinfo
->gen
>= 6);
1458 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1460 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1461 BRW_REGISTER_TYPE_D
));
1463 if (wm_prog_data
->persample_dispatch
) {
1464 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1465 * and a mask representing which sample is being processed by the
1466 * current shader invocation.
1468 * From the OES_sample_variables specification:
1469 * "When per-sample shading is active due to the use of a fragment input
1470 * qualified by "sample" or due to the use of the gl_SampleID or
1471 * gl_SamplePosition variables, only the bit for the current sample is
1472 * set in gl_SampleMaskIn."
1474 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1476 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1477 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1479 fs_reg one
= vgrf(glsl_type::int_type
);
1480 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1481 abld
.MOV(one
, brw_imm_d(1));
1482 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1483 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1485 /* In per-pixel mode, the coverage mask is sufficient. */
1486 *reg
= coverage_mask
;
1492 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1494 if (!src
.abs
&& !src
.negate
)
1497 fs_reg temp
= bld
.vgrf(src
.type
);
1504 fs_visitor::emit_discard_jump()
1506 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1508 /* For performance, after a discard, jump to the end of the
1509 * shader if all relevant channels have been discarded.
1511 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1512 discard_jump
->flag_subreg
= 1;
1514 discard_jump
->predicate
= (dispatch_width
== 8)
1515 ? BRW_PREDICATE_ALIGN1_ANY8H
1516 : BRW_PREDICATE_ALIGN1_ANY16H
;
1517 discard_jump
->predicate_inverse
= true;
1521 fs_visitor::emit_gs_thread_end()
1523 assert(stage
== MESA_SHADER_GEOMETRY
);
1525 struct brw_gs_prog_data
*gs_prog_data
=
1526 (struct brw_gs_prog_data
*) prog_data
;
1528 if (gs_compile
->control_data_header_size_bits
> 0) {
1529 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1532 const fs_builder abld
= bld
.annotate("thread end");
1535 if (gs_prog_data
->static_vertex_count
!= -1) {
1536 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1537 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1538 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1539 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1540 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1543 /* Delete now dead instructions. */
1544 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1550 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1554 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1555 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1556 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1559 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1560 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1561 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1562 sources
[1] = this->final_gs_vertex_count
;
1563 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1564 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1572 fs_visitor::assign_curb_setup()
1574 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1576 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1577 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1578 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1579 if (inst
->src
[i
].file
== UNIFORM
) {
1580 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1582 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1583 constant_nr
= push_constant_loc
[uniform_nr
];
1585 /* Section 5.11 of the OpenGL 4.1 spec says:
1586 * "Out-of-bounds reads return undefined values, which include
1587 * values from other variables of the active program or zero."
1588 * Just return the first push constant.
1593 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1596 brw_reg
.abs
= inst
->src
[i
].abs
;
1597 brw_reg
.negate
= inst
->src
[i
].negate
;
1599 assert(inst
->src
[i
].stride
== 0);
1600 inst
->src
[i
] = byte_offset(
1601 retype(brw_reg
, inst
->src
[i
].type
),
1602 inst
->src
[i
].subreg_offset
);
1607 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1608 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1612 fs_visitor::calculate_urb_setup()
1614 assert(stage
== MESA_SHADER_FRAGMENT
);
1615 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1616 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1618 memset(prog_data
->urb_setup
, -1,
1619 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1622 /* Figure out where each of the incoming setup attributes lands. */
1623 if (devinfo
->gen
>= 6) {
1624 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1625 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1626 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1627 * first 16 varying inputs, so we can put them wherever we want.
1628 * Just put them in order.
1630 * This is useful because it means that (a) inputs not used by the
1631 * fragment shader won't take up valuable register space, and (b) we
1632 * won't have to recompile the fragment shader if it gets paired with
1633 * a different vertex (or geometry) shader.
1635 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1636 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1637 BITFIELD64_BIT(i
)) {
1638 prog_data
->urb_setup
[i
] = urb_next
++;
1642 bool include_vue_header
=
1643 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1645 /* We have enough input varyings that the SF/SBE pipeline stage can't
1646 * arbitrarily rearrange them to suit our whim; we have to put them
1647 * in an order that matches the output of the previous pipeline stage
1648 * (geometry or vertex shader).
1650 struct brw_vue_map prev_stage_vue_map
;
1651 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1652 key
->input_slots_valid
,
1653 nir
->info
.separate_shader
);
1655 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1657 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1658 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1660 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1661 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1662 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1663 BITFIELD64_BIT(varying
))) {
1664 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1667 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1670 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1671 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1672 /* Point size is packed into the header, not as a general attribute */
1673 if (i
== VARYING_SLOT_PSIZ
)
1676 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1677 /* The back color slot is skipped when the front color is
1678 * also written to. In addition, some slots can be
1679 * written in the vertex shader and not read in the
1680 * fragment shader. So the register number must always be
1681 * incremented, mapped or not.
1683 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1684 prog_data
->urb_setup
[i
] = urb_next
;
1690 * It's a FS only attribute, and we did interpolation for this attribute
1691 * in SF thread. So, count it here, too.
1693 * See compile_sf_prog() for more info.
1695 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1696 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1699 prog_data
->num_varying_inputs
= urb_next
;
1703 fs_visitor::assign_urb_setup()
1705 assert(stage
== MESA_SHADER_FRAGMENT
);
1706 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1708 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1710 /* Offset all the urb_setup[] index by the actual position of the
1711 * setup regs, now that the location of the constants has been chosen.
1713 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1714 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1715 assert(inst
->src
[1].file
== FIXED_GRF
);
1716 inst
->src
[1].nr
+= urb_start
;
1719 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1720 assert(inst
->src
[0].file
== FIXED_GRF
);
1721 inst
->src
[0].nr
+= urb_start
;
1725 /* Each attribute is 4 setup channels, each of which is half a reg. */
1726 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1730 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1732 for (int i
= 0; i
< inst
->sources
; i
++) {
1733 if (inst
->src
[i
].file
== ATTR
) {
1734 int grf
= payload
.num_regs
+
1735 prog_data
->curb_read_length
+
1737 inst
->src
[i
].reg_offset
;
1739 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1741 * VertStride must be used to cross GRF register boundaries. This
1742 * rule implies that elements within a 'Width' cannot cross GRF
1745 * So, for registers that are large enough, we have to split the exec
1746 * size in two and trust the compression state to sort it out.
1748 unsigned total_size
= inst
->exec_size
*
1749 inst
->src
[i
].stride
*
1750 type_sz(inst
->src
[i
].type
);
1752 assert(total_size
<= 2 * REG_SIZE
);
1753 const unsigned exec_size
=
1754 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1756 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1757 struct brw_reg reg
=
1758 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1759 inst
->src
[i
].subreg_offset
),
1760 exec_size
* inst
->src
[i
].stride
,
1761 width
, inst
->src
[i
].stride
);
1762 reg
.abs
= inst
->src
[i
].abs
;
1763 reg
.negate
= inst
->src
[i
].negate
;
1771 fs_visitor::assign_vs_urb_setup()
1773 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1775 assert(stage
== MESA_SHADER_VERTEX
);
1777 /* Each attribute is 4 regs. */
1778 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1780 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1782 /* Rewrite all ATTR file references to the hw grf that they land in. */
1783 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1784 convert_attr_sources_to_hw_regs(inst
);
1789 fs_visitor::assign_tcs_single_patch_urb_setup()
1791 assert(stage
== MESA_SHADER_TESS_CTRL
);
1793 /* Rewrite all ATTR file references to HW_REGs. */
1794 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1795 convert_attr_sources_to_hw_regs(inst
);
1800 fs_visitor::assign_tes_urb_setup()
1802 assert(stage
== MESA_SHADER_TESS_EVAL
);
1804 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1806 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1808 /* Rewrite all ATTR file references to HW_REGs. */
1809 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1810 convert_attr_sources_to_hw_regs(inst
);
1815 fs_visitor::assign_gs_urb_setup()
1817 assert(stage
== MESA_SHADER_GEOMETRY
);
1819 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1821 first_non_payload_grf
+=
1822 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1824 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1825 /* Rewrite all ATTR file references to GRFs. */
1826 convert_attr_sources_to_hw_regs(inst
);
1832 * Split large virtual GRFs into separate components if we can.
1834 * This is mostly duplicated with what brw_fs_vector_splitting does,
1835 * but that's really conservative because it's afraid of doing
1836 * splitting that doesn't result in real progress after the rest of
1837 * the optimization phases, which would cause infinite looping in
1838 * optimization. We can do it once here, safely. This also has the
1839 * opportunity to split interpolated values, or maybe even uniforms,
1840 * which we don't have at the IR level.
1842 * We want to split, because virtual GRFs are what we register
1843 * allocate and spill (due to contiguousness requirements for some
1844 * instructions), and they're what we naturally generate in the
1845 * codegen process, but most virtual GRFs don't actually need to be
1846 * contiguous sets of GRFs. If we split, we'll end up with reduced
1847 * live intervals and better dead code elimination and coalescing.
1850 fs_visitor::split_virtual_grfs()
1852 int num_vars
= this->alloc
.count
;
1854 /* Count the total number of registers */
1856 int vgrf_to_reg
[num_vars
];
1857 for (int i
= 0; i
< num_vars
; i
++) {
1858 vgrf_to_reg
[i
] = reg_count
;
1859 reg_count
+= alloc
.sizes
[i
];
1862 /* An array of "split points". For each register slot, this indicates
1863 * if this slot can be separated from the previous slot. Every time an
1864 * instruction uses multiple elements of a register (as a source or
1865 * destination), we mark the used slots as inseparable. Then we go
1866 * through and split the registers into the smallest pieces we can.
1868 bool split_points
[reg_count
];
1869 memset(split_points
, 0, sizeof(split_points
));
1871 /* Mark all used registers as fully splittable */
1872 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1873 if (inst
->dst
.file
== VGRF
) {
1874 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1875 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1876 split_points
[reg
+ j
] = true;
1879 for (int i
= 0; i
< inst
->sources
; i
++) {
1880 if (inst
->src
[i
].file
== VGRF
) {
1881 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1882 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1883 split_points
[reg
+ j
] = true;
1888 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1889 if (inst
->dst
.file
== VGRF
) {
1890 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1891 for (int j
= 1; j
< inst
->regs_written
; j
++)
1892 split_points
[reg
+ j
] = false;
1894 for (int i
= 0; i
< inst
->sources
; i
++) {
1895 if (inst
->src
[i
].file
== VGRF
) {
1896 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1897 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1898 split_points
[reg
+ j
] = false;
1903 int new_virtual_grf
[reg_count
];
1904 int new_reg_offset
[reg_count
];
1907 for (int i
= 0; i
< num_vars
; i
++) {
1908 /* The first one should always be 0 as a quick sanity check. */
1909 assert(split_points
[reg
] == false);
1912 new_reg_offset
[reg
] = 0;
1917 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1918 /* If this is a split point, reset the offset to 0 and allocate a
1919 * new virtual GRF for the previous offset many registers
1921 if (split_points
[reg
]) {
1922 assert(offset
<= MAX_VGRF_SIZE
);
1923 int grf
= alloc
.allocate(offset
);
1924 for (int k
= reg
- offset
; k
< reg
; k
++)
1925 new_virtual_grf
[k
] = grf
;
1928 new_reg_offset
[reg
] = offset
;
1933 /* The last one gets the original register number */
1934 assert(offset
<= MAX_VGRF_SIZE
);
1935 alloc
.sizes
[i
] = offset
;
1936 for (int k
= reg
- offset
; k
< reg
; k
++)
1937 new_virtual_grf
[k
] = i
;
1939 assert(reg
== reg_count
);
1941 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1942 if (inst
->dst
.file
== VGRF
) {
1943 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1944 inst
->dst
.nr
= new_virtual_grf
[reg
];
1945 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1946 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1948 for (int i
= 0; i
< inst
->sources
; i
++) {
1949 if (inst
->src
[i
].file
== VGRF
) {
1950 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1951 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1952 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1953 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1957 invalidate_live_intervals();
1961 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1963 * During code generation, we create tons of temporary variables, many of
1964 * which get immediately killed and are never used again. Yet, in later
1965 * optimization and analysis passes, such as compute_live_intervals, we need
1966 * to loop over all the virtual GRFs. Compacting them can save a lot of
1970 fs_visitor::compact_virtual_grfs()
1972 bool progress
= false;
1973 int remap_table
[this->alloc
.count
];
1974 memset(remap_table
, -1, sizeof(remap_table
));
1976 /* Mark which virtual GRFs are used. */
1977 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1978 if (inst
->dst
.file
== VGRF
)
1979 remap_table
[inst
->dst
.nr
] = 0;
1981 for (int i
= 0; i
< inst
->sources
; i
++) {
1982 if (inst
->src
[i
].file
== VGRF
)
1983 remap_table
[inst
->src
[i
].nr
] = 0;
1987 /* Compact the GRF arrays. */
1989 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1990 if (remap_table
[i
] == -1) {
1991 /* We just found an unused register. This means that we are
1992 * actually going to compact something.
1996 remap_table
[i
] = new_index
;
1997 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1998 invalidate_live_intervals();
2003 this->alloc
.count
= new_index
;
2005 /* Patch all the instructions to use the newly renumbered registers */
2006 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2007 if (inst
->dst
.file
== VGRF
)
2008 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
2010 for (int i
= 0; i
< inst
->sources
; i
++) {
2011 if (inst
->src
[i
].file
== VGRF
)
2012 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
2016 /* Patch all the references to delta_xy, since they're used in register
2017 * allocation. If they're unused, switch them to BAD_FILE so we don't
2018 * think some random VGRF is delta_xy.
2020 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2021 if (delta_xy
[i
].file
== VGRF
) {
2022 if (remap_table
[delta_xy
[i
].nr
] != -1) {
2023 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
2025 delta_xy
[i
].file
= BAD_FILE
;
2034 set_push_pull_constant_loc(unsigned uniform
, int *chunk_start
, bool contiguous
,
2035 int *push_constant_loc
, int *pull_constant_loc
,
2036 unsigned *num_push_constants
,
2037 unsigned *num_pull_constants
,
2038 const unsigned max_push_components
,
2039 const unsigned max_chunk_size
,
2040 struct brw_stage_prog_data
*stage_prog_data
)
2042 /* This is the first live uniform in the chunk */
2043 if (*chunk_start
< 0)
2044 *chunk_start
= uniform
;
2046 /* If this element does not need to be contiguous with the next, we
2047 * split at this point and everything between chunk_start and u forms a
2051 unsigned chunk_size
= uniform
- *chunk_start
+ 1;
2053 /* Decide whether we should push or pull this parameter. In the
2054 * Vulkan driver, push constants are explicitly exposed via the API
2055 * so we push everything. In GL, we only push small arrays.
2057 if (stage_prog_data
->pull_param
== NULL
||
2058 (*num_push_constants
+ chunk_size
<= max_push_components
&&
2059 chunk_size
<= max_chunk_size
)) {
2060 assert(*num_push_constants
+ chunk_size
<= max_push_components
);
2061 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
2062 push_constant_loc
[j
] = (*num_push_constants
)++;
2064 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
2065 pull_constant_loc
[j
] = (*num_pull_constants
)++;
2073 * Assign UNIFORM file registers to either push constants or pull constants.
2075 * We allow a fragment shader to have more than the specified minimum
2076 * maximum number of fragment shader uniform components (64). If
2077 * there are too many of these, they'd fill up all of register space.
2078 * So, this will push some of them out to the pull constant buffer and
2079 * update the program to load them.
2082 fs_visitor::assign_constant_locations()
2084 /* Only the first compile gets to decide on locations. */
2085 if (dispatch_width
!= min_dispatch_width
)
2088 bool is_live
[uniforms
];
2089 memset(is_live
, 0, sizeof(is_live
));
2090 bool is_live_64bit
[uniforms
];
2091 memset(is_live_64bit
, 0, sizeof(is_live_64bit
));
2093 /* For each uniform slot, a value of true indicates that the given slot and
2094 * the next slot must remain contiguous. This is used to keep us from
2095 * splitting arrays apart.
2097 bool contiguous
[uniforms
];
2098 memset(contiguous
, 0, sizeof(contiguous
));
2100 /* First, we walk through the instructions and do two things:
2102 * 1) Figure out which uniforms are live.
2104 * 2) Mark any indirectly used ranges of registers as contiguous.
2106 * Note that we don't move constant-indexed accesses to arrays. No
2107 * testing has been done of the performance impact of this choice.
2109 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2110 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2111 if (inst
->src
[i
].file
!= UNIFORM
)
2114 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2116 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2117 assert(inst
->src
[2].ud
% 4 == 0);
2118 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
2119 assert(last
< uniforms
);
2121 for (unsigned j
= constant_nr
; j
< last
; j
++) {
2123 contiguous
[j
] = true;
2124 if (type_sz(inst
->src
[i
].type
) == 8) {
2125 is_live_64bit
[j
] = true;
2128 is_live
[last
] = true;
2130 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
) {
2131 int regs_read
= inst
->components_read(i
) *
2132 type_sz(inst
->src
[i
].type
) / 4;
2133 for (int j
= 0; j
< regs_read
; j
++) {
2134 is_live
[constant_nr
+ j
] = true;
2135 if (type_sz(inst
->src
[i
].type
) == 8) {
2136 is_live_64bit
[constant_nr
+ j
] = true;
2144 /* Only allow 16 registers (128 uniform components) as push constants.
2146 * Just demote the end of the list. We could probably do better
2147 * here, demoting things that are rarely used in the program first.
2149 * If changing this value, note the limitation about total_regs in
2152 const unsigned int max_push_components
= 16 * 8;
2154 /* We push small arrays, but no bigger than 16 floats. This is big enough
2155 * for a vec4 but hopefully not large enough to push out other stuff. We
2156 * should probably use a better heuristic at some point.
2158 const unsigned int max_chunk_size
= 16;
2160 unsigned int num_push_constants
= 0;
2161 unsigned int num_pull_constants
= 0;
2163 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2164 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2166 /* Default to -1 meaning no location */
2167 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2168 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2170 int chunk_start
= -1;
2172 /* First push 64-bit uniforms to ensure they are properly aligned */
2173 for (unsigned u
= 0; u
< uniforms
; u
++) {
2174 if (!is_live
[u
] || !is_live_64bit
[u
])
2177 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2178 push_constant_loc
, pull_constant_loc
,
2179 &num_push_constants
, &num_pull_constants
,
2180 max_push_components
, max_chunk_size
,
2185 /* Then push the rest of uniforms */
2186 for (unsigned u
= 0; u
< uniforms
; u
++) {
2187 if (!is_live
[u
] || is_live_64bit
[u
])
2190 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2191 push_constant_loc
, pull_constant_loc
,
2192 &num_push_constants
, &num_pull_constants
,
2193 max_push_components
, max_chunk_size
,
2197 /* As the uniforms are going to be reordered, take the data from a temporary
2198 * copy of the original param[].
2200 gl_constant_value
**param
= ralloc_array(NULL
, gl_constant_value
*,
2201 stage_prog_data
->nr_params
);
2202 memcpy(param
, stage_prog_data
->param
,
2203 sizeof(gl_constant_value
*) * stage_prog_data
->nr_params
);
2204 stage_prog_data
->nr_params
= num_push_constants
;
2205 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2207 /* Up until now, the param[] array has been indexed by reg + reg_offset
2208 * of UNIFORM registers. Move pull constants into pull_param[] and
2209 * condense param[] to only contain the uniforms we chose to push.
2211 * NOTE: Because we are condensing the params[] array, we know that
2212 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2213 * having to make a copy.
2215 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2216 const gl_constant_value
*value
= param
[i
];
2218 if (pull_constant_loc
[i
] != -1) {
2219 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2220 } else if (push_constant_loc
[i
] != -1) {
2221 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2228 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2229 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2232 fs_visitor::lower_constant_loads()
2234 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2236 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2237 /* Set up the annotation tracking for new generated instructions. */
2238 const fs_builder
ibld(this, block
, inst
);
2240 for (int i
= 0; i
< inst
->sources
; i
++) {
2241 if (inst
->src
[i
].file
!= UNIFORM
)
2244 /* We'll handle this case later */
2245 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2248 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2249 if (location
>= uniforms
)
2250 continue; /* Out of bounds access */
2252 int pull_index
= pull_constant_loc
[location
];
2254 if (pull_index
== -1)
2257 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2260 if (type_sz(inst
->src
[i
].type
) <= 4)
2261 dst
= vgrf(glsl_type::float_type
);
2263 dst
= vgrf(glsl_type::double_type
);
2265 assert(inst
->src
[i
].stride
== 0);
2267 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2268 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2269 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2270 dst
, brw_imm_ud(index
), offset
);
2272 /* Rewrite the instruction to use the temporary VGRF. */
2273 inst
->src
[i
].file
= VGRF
;
2274 inst
->src
[i
].nr
= dst
.nr
;
2275 inst
->src
[i
].reg_offset
= 0;
2276 inst
->src
[i
].set_smear((pull_index
& 3) * 4 /
2277 type_sz(inst
->src
[i
].type
));
2279 brw_mark_surface_used(prog_data
, index
);
2282 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2283 inst
->src
[0].file
== UNIFORM
) {
2285 unsigned location
= inst
->src
[0].nr
+ inst
->src
[0].reg_offset
;
2286 if (location
>= uniforms
)
2287 continue; /* Out of bounds access */
2289 int pull_index
= pull_constant_loc
[location
];
2291 if (pull_index
== -1)
2294 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2298 inst
->remove(block
);
2300 brw_mark_surface_used(prog_data
, index
);
2303 invalidate_live_intervals();
2307 fs_visitor::opt_algebraic()
2309 bool progress
= false;
2311 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2312 switch (inst
->opcode
) {
2313 case BRW_OPCODE_MOV
:
2314 if (inst
->src
[0].file
!= IMM
)
2317 if (inst
->saturate
) {
2318 if (inst
->dst
.type
!= inst
->src
[0].type
)
2319 assert(!"unimplemented: saturate mixed types");
2321 if (brw_saturate_immediate(inst
->dst
.type
,
2322 &inst
->src
[0].as_brw_reg())) {
2323 inst
->saturate
= false;
2329 case BRW_OPCODE_MUL
:
2330 if (inst
->src
[1].file
!= IMM
)
2334 if (inst
->src
[1].is_one()) {
2335 inst
->opcode
= BRW_OPCODE_MOV
;
2336 inst
->src
[1] = reg_undef
;
2342 if (inst
->src
[1].is_negative_one()) {
2343 inst
->opcode
= BRW_OPCODE_MOV
;
2344 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2345 inst
->src
[1] = reg_undef
;
2351 if (inst
->src
[1].is_zero()) {
2352 inst
->opcode
= BRW_OPCODE_MOV
;
2353 inst
->src
[0] = inst
->src
[1];
2354 inst
->src
[1] = reg_undef
;
2359 if (inst
->src
[0].file
== IMM
) {
2360 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2361 inst
->opcode
= BRW_OPCODE_MOV
;
2362 inst
->src
[0].f
*= inst
->src
[1].f
;
2363 inst
->src
[1] = reg_undef
;
2368 case BRW_OPCODE_ADD
:
2369 if (inst
->src
[1].file
!= IMM
)
2373 if (inst
->src
[1].is_zero()) {
2374 inst
->opcode
= BRW_OPCODE_MOV
;
2375 inst
->src
[1] = reg_undef
;
2380 if (inst
->src
[0].file
== IMM
) {
2381 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2382 inst
->opcode
= BRW_OPCODE_MOV
;
2383 inst
->src
[0].f
+= inst
->src
[1].f
;
2384 inst
->src
[1] = reg_undef
;
2390 if (inst
->src
[0].equals(inst
->src
[1])) {
2391 inst
->opcode
= BRW_OPCODE_MOV
;
2392 inst
->src
[1] = reg_undef
;
2397 case BRW_OPCODE_LRP
:
2398 if (inst
->src
[1].equals(inst
->src
[2])) {
2399 inst
->opcode
= BRW_OPCODE_MOV
;
2400 inst
->src
[0] = inst
->src
[1];
2401 inst
->src
[1] = reg_undef
;
2402 inst
->src
[2] = reg_undef
;
2407 case BRW_OPCODE_CMP
:
2408 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2410 inst
->src
[0].negate
&&
2411 inst
->src
[1].is_zero()) {
2412 inst
->src
[0].abs
= false;
2413 inst
->src
[0].negate
= false;
2414 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2419 case BRW_OPCODE_SEL
:
2420 if (inst
->src
[0].equals(inst
->src
[1])) {
2421 inst
->opcode
= BRW_OPCODE_MOV
;
2422 inst
->src
[1] = reg_undef
;
2423 inst
->predicate
= BRW_PREDICATE_NONE
;
2424 inst
->predicate_inverse
= false;
2426 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2427 switch (inst
->conditional_mod
) {
2428 case BRW_CONDITIONAL_LE
:
2429 case BRW_CONDITIONAL_L
:
2430 switch (inst
->src
[1].type
) {
2431 case BRW_REGISTER_TYPE_F
:
2432 if (inst
->src
[1].f
>= 1.0f
) {
2433 inst
->opcode
= BRW_OPCODE_MOV
;
2434 inst
->src
[1] = reg_undef
;
2435 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2443 case BRW_CONDITIONAL_GE
:
2444 case BRW_CONDITIONAL_G
:
2445 switch (inst
->src
[1].type
) {
2446 case BRW_REGISTER_TYPE_F
:
2447 if (inst
->src
[1].f
<= 0.0f
) {
2448 inst
->opcode
= BRW_OPCODE_MOV
;
2449 inst
->src
[1] = reg_undef
;
2450 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2462 case BRW_OPCODE_MAD
:
2463 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2464 inst
->opcode
= BRW_OPCODE_MOV
;
2465 inst
->src
[1] = reg_undef
;
2466 inst
->src
[2] = reg_undef
;
2468 } else if (inst
->src
[0].is_zero()) {
2469 inst
->opcode
= BRW_OPCODE_MUL
;
2470 inst
->src
[0] = inst
->src
[2];
2471 inst
->src
[2] = reg_undef
;
2473 } else if (inst
->src
[1].is_one()) {
2474 inst
->opcode
= BRW_OPCODE_ADD
;
2475 inst
->src
[1] = inst
->src
[2];
2476 inst
->src
[2] = reg_undef
;
2478 } else if (inst
->src
[2].is_one()) {
2479 inst
->opcode
= BRW_OPCODE_ADD
;
2480 inst
->src
[2] = reg_undef
;
2482 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2483 inst
->opcode
= BRW_OPCODE_ADD
;
2484 inst
->src
[1].f
*= inst
->src
[2].f
;
2485 inst
->src
[2] = reg_undef
;
2489 case SHADER_OPCODE_BROADCAST
:
2490 if (is_uniform(inst
->src
[0])) {
2491 inst
->opcode
= BRW_OPCODE_MOV
;
2493 inst
->force_writemask_all
= true;
2495 } else if (inst
->src
[1].file
== IMM
) {
2496 inst
->opcode
= BRW_OPCODE_MOV
;
2497 inst
->src
[0] = component(inst
->src
[0],
2500 inst
->force_writemask_all
= true;
2509 /* Swap if src[0] is immediate. */
2510 if (progress
&& inst
->is_commutative()) {
2511 if (inst
->src
[0].file
== IMM
) {
2512 fs_reg tmp
= inst
->src
[1];
2513 inst
->src
[1] = inst
->src
[0];
2522 * Optimize sample messages that have constant zero values for the trailing
2523 * texture coordinates. We can just reduce the message length for these
2524 * instructions instead of reserving a register for it. Trailing parameters
2525 * that aren't sent default to zero anyway. This will cause the dead code
2526 * eliminator to remove the MOV instruction that would otherwise be emitted to
2527 * set up the zero value.
2530 fs_visitor::opt_zero_samples()
2532 /* Gen4 infers the texturing opcode based on the message length so we can't
2535 if (devinfo
->gen
< 5)
2538 bool progress
= false;
2540 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2541 if (!inst
->is_tex())
2544 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2546 if (load_payload
->is_head_sentinel() ||
2547 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2550 /* We don't want to remove the message header or the first parameter.
2551 * Removing the first parameter is not allowed, see the Haswell PRM
2552 * volume 7, page 149:
2554 * "Parameter 0 is required except for the sampleinfo message, which
2555 * has no parameter 0"
2557 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2558 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2559 (inst
->exec_size
/ 8) +
2560 inst
->header_size
- 1].is_zero()) {
2561 inst
->mlen
-= inst
->exec_size
/ 8;
2567 invalidate_live_intervals();
2573 * Optimize sample messages which are followed by the final RT write.
2575 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2576 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2577 * final texturing results copied to the framebuffer write payload and modify
2578 * them to write to the framebuffer directly.
2581 fs_visitor::opt_sampler_eot()
2583 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2585 if (stage
!= MESA_SHADER_FRAGMENT
)
2588 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2591 /* FINISHME: It should be possible to implement this optimization when there
2592 * are multiple drawbuffers.
2594 if (key
->nr_color_regions
!= 1)
2597 /* Requires emitting a bunch of saturating MOV instructions during logical
2598 * send lowering to clamp the color payload, which the sampler unit isn't
2599 * going to do for us.
2601 if (key
->clamp_fragment_color
)
2604 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2605 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2606 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2607 assert(fb_write
->eot
);
2608 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2610 /* There wasn't one; nothing to do. */
2611 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2614 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2616 /* 3D Sampler » Messages » Message Format
2618 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2619 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2621 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2622 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2623 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2624 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2625 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2626 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2627 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2628 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2631 /* XXX - This shouldn't be necessary. */
2632 if (tex_inst
->prev
->is_head_sentinel())
2635 /* Check that the FB write sources are fully initialized by the single
2636 * texturing instruction.
2638 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2639 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2640 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2641 fb_write
->regs_read(i
) != tex_inst
->regs_written
)
2643 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2644 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2649 assert(!tex_inst
->eot
); /* We can't get here twice */
2650 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2652 const fs_builder
ibld(this, block
, tex_inst
);
2654 tex_inst
->offset
|= fb_write
->target
<< 24;
2655 tex_inst
->eot
= true;
2656 tex_inst
->dst
= ibld
.null_reg_ud();
2657 tex_inst
->regs_written
= 0;
2658 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2660 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2661 * flag and submit a header together with the sampler message as required
2664 invalidate_live_intervals();
2669 fs_visitor::opt_register_renaming()
2671 bool progress
= false;
2674 int remap
[alloc
.count
];
2675 memset(remap
, -1, sizeof(int) * alloc
.count
);
2677 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2678 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2680 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2681 inst
->opcode
== BRW_OPCODE_WHILE
) {
2685 /* Rewrite instruction sources. */
2686 for (int i
= 0; i
< inst
->sources
; i
++) {
2687 if (inst
->src
[i
].file
== VGRF
&&
2688 remap
[inst
->src
[i
].nr
] != -1 &&
2689 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2690 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2695 const int dst
= inst
->dst
.nr
;
2698 inst
->dst
.file
== VGRF
&&
2699 alloc
.sizes
[inst
->dst
.nr
] == inst
->regs_written
&&
2700 !inst
->is_partial_write()) {
2701 if (remap
[dst
] == -1) {
2704 remap
[dst
] = alloc
.allocate(inst
->regs_written
);
2705 inst
->dst
.nr
= remap
[dst
];
2708 } else if (inst
->dst
.file
== VGRF
&&
2710 remap
[dst
] != dst
) {
2711 inst
->dst
.nr
= remap
[dst
];
2717 invalidate_live_intervals();
2719 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2720 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2721 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2730 * Remove redundant or useless discard jumps.
2732 * For example, we can eliminate jumps in the following sequence:
2734 * discard-jump (redundant with the next jump)
2735 * discard-jump (useless; jumps to the next instruction)
2739 fs_visitor::opt_redundant_discard_jumps()
2741 bool progress
= false;
2743 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2745 fs_inst
*placeholder_halt
= NULL
;
2746 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2747 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2748 placeholder_halt
= inst
;
2753 if (!placeholder_halt
)
2756 /* Delete any HALTs immediately before the placeholder halt. */
2757 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2758 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2759 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2760 prev
->remove(last_bblock
);
2765 invalidate_live_intervals();
2771 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2772 * from \p r which overlaps the region starting at \p r and spanning \p n GRF
2775 static inline unsigned
2776 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned n
)
2778 const int rel_offset
= (reg_offset(s
) - reg_offset(r
)) / REG_SIZE
;
2779 assert(reg_space(r
) == reg_space(s
) &&
2780 rel_offset
>= 0 && rel_offset
< int(8 * sizeof(unsigned)));
2781 return ((1 << n
) - 1) << rel_offset
;
2785 fs_visitor::compute_to_mrf()
2787 bool progress
= false;
2790 /* No MRFs on Gen >= 7. */
2791 if (devinfo
->gen
>= 7)
2794 calculate_live_intervals();
2796 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2800 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2801 inst
->is_partial_write() ||
2802 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2803 inst
->dst
.type
!= inst
->src
[0].type
||
2804 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2805 !inst
->src
[0].is_contiguous() ||
2806 inst
->src
[0].subreg_offset
)
2809 /* Can't compute-to-MRF this GRF if someone else was going to
2812 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2815 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
2816 * things that computed the value of all GRFs of the source region. The
2817 * regs_left bitset keeps track of the registers we haven't yet found a
2818 * generating instruction for.
2820 unsigned regs_left
= (1 << inst
->regs_read(0)) - 1;
2822 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2823 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2824 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2825 /* Found the last thing to write our reg we want to turn
2826 * into a compute-to-MRF.
2829 /* If this one instruction didn't populate all the
2830 * channels, bail. We might be able to rewrite everything
2831 * that writes that reg, but it would require smarter
2834 if (scan_inst
->is_partial_write())
2837 /* Handling things not fully contained in the source of the copy
2838 * would need us to understand coalescing out more than one MOV at
2841 if (scan_inst
->dst
.reg_offset
< inst
->src
[0].reg_offset
||
2842 scan_inst
->dst
.reg_offset
+ scan_inst
->regs_written
>
2843 inst
->src
[0].reg_offset
+ inst
->regs_read(0))
2846 /* SEND instructions can't have MRF as a destination. */
2847 if (scan_inst
->mlen
)
2850 if (devinfo
->gen
== 6) {
2851 /* gen6 math instructions must have the destination be
2852 * GRF, so no compute-to-MRF for them.
2854 if (scan_inst
->is_math()) {
2859 /* Clear the bits for any registers this instruction overwrites. */
2860 regs_left
&= ~mask_relative_to(
2861 inst
->src
[0], scan_inst
->dst
, scan_inst
->regs_written
);
2866 /* We don't handle control flow here. Most computation of
2867 * values that end up in MRFs are shortly before the MRF
2870 if (block
->start() == scan_inst
)
2873 /* You can't read from an MRF, so if someone else reads our
2874 * MRF's source GRF that we wanted to rewrite, that stops us.
2876 bool interfered
= false;
2877 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2878 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->regs_read(i
) * REG_SIZE
,
2879 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2886 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2887 inst
->dst
, inst
->regs_written
* REG_SIZE
)) {
2888 /* If somebody else writes our MRF here, we can't
2889 * compute-to-MRF before that.
2894 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
2895 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
2896 inst
->dst
, inst
->regs_written
* REG_SIZE
)) {
2897 /* Found a SEND instruction, which means that there are
2898 * live values in MRFs from base_mrf to base_mrf +
2899 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2909 /* Found all generating instructions of our MRF's source value, so it
2910 * should be safe to rewrite them to point to the MRF directly.
2912 regs_left
= (1 << inst
->regs_read(0)) - 1;
2914 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2915 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2916 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2917 /* Clear the bits for any registers this instruction overwrites. */
2918 regs_left
&= ~mask_relative_to(
2919 inst
->src
[0], scan_inst
->dst
, scan_inst
->regs_written
);
2921 const unsigned rel_offset
= (reg_offset(scan_inst
->dst
) -
2922 reg_offset(inst
->src
[0])) / REG_SIZE
;
2924 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2925 /* Apply the same address transformation done by the hardware
2926 * for COMPR4 MRF writes.
2928 assert(rel_offset
< 2);
2929 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
* 4;
2931 /* Clear the COMPR4 bit if the generating instruction is not
2934 if (scan_inst
->regs_written
< 2)
2935 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
2938 /* Calculate the MRF number the result of this instruction is
2939 * ultimately written to.
2941 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
;
2944 scan_inst
->dst
.file
= MRF
;
2945 scan_inst
->dst
.reg_offset
= 0;
2946 scan_inst
->saturate
|= inst
->saturate
;
2953 inst
->remove(block
);
2958 invalidate_live_intervals();
2964 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2965 * flow. We could probably do better here with some form of divergence
2969 fs_visitor::eliminate_find_live_channel()
2971 bool progress
= false;
2974 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2975 switch (inst
->opcode
) {
2981 case BRW_OPCODE_ENDIF
:
2982 case BRW_OPCODE_WHILE
:
2986 case FS_OPCODE_DISCARD_JUMP
:
2987 /* This can potentially make control flow non-uniform until the end
2992 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2994 inst
->opcode
= BRW_OPCODE_MOV
;
2995 inst
->src
[0] = brw_imm_ud(0u);
2997 inst
->force_writemask_all
= true;
3011 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
3012 * instructions to FS_OPCODE_REP_FB_WRITE.
3015 fs_visitor::emit_repclear_shader()
3017 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3019 int color_mrf
= base_mrf
+ 2;
3023 mov
= bld
.exec_all().group(4, 0)
3024 .MOV(brw_message_reg(color_mrf
),
3025 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
3027 struct brw_reg reg
=
3028 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
3029 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
3030 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
3032 mov
= bld
.exec_all().group(4, 0)
3033 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
3037 if (key
->nr_color_regions
== 1) {
3038 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3039 write
->saturate
= key
->clamp_fragment_color
;
3040 write
->base_mrf
= color_mrf
;
3042 write
->header_size
= 0;
3045 assume(key
->nr_color_regions
> 0);
3046 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
3047 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3048 write
->saturate
= key
->clamp_fragment_color
;
3049 write
->base_mrf
= base_mrf
;
3051 write
->header_size
= 2;
3059 assign_constant_locations();
3060 assign_curb_setup();
3062 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3064 assert(mov
->src
[0].file
== FIXED_GRF
);
3065 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3070 * Walks through basic blocks, looking for repeated MRF writes and
3071 * removing the later ones.
3074 fs_visitor::remove_duplicate_mrf_writes()
3076 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3077 bool progress
= false;
3079 /* Need to update the MRF tracking for compressed instructions. */
3080 if (dispatch_width
>= 16)
3083 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3085 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3086 if (inst
->is_control_flow()) {
3087 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3090 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3091 inst
->dst
.file
== MRF
) {
3092 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3093 if (prev_inst
&& inst
->equals(prev_inst
)) {
3094 inst
->remove(block
);
3100 /* Clear out the last-write records for MRFs that were overwritten. */
3101 if (inst
->dst
.file
== MRF
) {
3102 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3105 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3106 /* Found a SEND instruction, which will include two or fewer
3107 * implied MRF writes. We could do better here.
3109 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3110 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3114 /* Clear out any MRF move records whose sources got overwritten. */
3115 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3116 if (last_mrf_move
[i
] &&
3117 regions_overlap(inst
->dst
, inst
->regs_written
* REG_SIZE
,
3118 last_mrf_move
[i
]->src
[0],
3119 last_mrf_move
[i
]->regs_read(0) * REG_SIZE
)) {
3120 last_mrf_move
[i
] = NULL
;
3124 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3125 inst
->dst
.file
== MRF
&&
3126 inst
->src
[0].file
!= ARF
&&
3127 !inst
->is_partial_write()) {
3128 last_mrf_move
[inst
->dst
.nr
] = inst
;
3133 invalidate_live_intervals();
3139 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3141 /* Clear the flag for registers that actually got read (as expected). */
3142 for (int i
= 0; i
< inst
->sources
; i
++) {
3144 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3145 grf
= inst
->src
[i
].nr
;
3150 if (grf
>= first_grf
&&
3151 grf
< first_grf
+ grf_len
) {
3152 deps
[grf
- first_grf
] = false;
3153 if (inst
->exec_size
== 16)
3154 deps
[grf
- first_grf
+ 1] = false;
3160 * Implements this workaround for the original 965:
3162 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3163 * check for post destination dependencies on this instruction, software
3164 * must ensure that there is no destination hazard for the case of ‘write
3165 * followed by a posted write’ shown in the following example.
3168 * 2. send r3.xy <rest of send instruction>
3171 * Due to no post-destination dependency check on the ‘send’, the above
3172 * code sequence could have two instructions (1 and 2) in flight at the
3173 * same time that both consider ‘r3’ as the target of their final writes.
3176 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3179 int write_len
= inst
->regs_written
;
3180 int first_write_grf
= inst
->dst
.nr
;
3181 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3182 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3184 memset(needs_dep
, false, sizeof(needs_dep
));
3185 memset(needs_dep
, true, write_len
);
3187 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3189 /* Walk backwards looking for writes to registers we're writing which
3190 * aren't read since being written. If we hit the start of the program,
3191 * we assume that there are no outstanding dependencies on entry to the
3194 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3195 /* If we hit control flow, assume that there *are* outstanding
3196 * dependencies, and force their cleanup before our instruction.
3198 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3199 for (int i
= 0; i
< write_len
; i
++) {
3201 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3202 first_write_grf
+ i
);
3207 /* We insert our reads as late as possible on the assumption that any
3208 * instruction but a MOV that might have left us an outstanding
3209 * dependency has more latency than a MOV.
3211 if (scan_inst
->dst
.file
== VGRF
) {
3212 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
3213 int reg
= scan_inst
->dst
.nr
+ i
;
3215 if (reg
>= first_write_grf
&&
3216 reg
< first_write_grf
+ write_len
&&
3217 needs_dep
[reg
- first_write_grf
]) {
3218 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3219 needs_dep
[reg
- first_write_grf
] = false;
3220 if (scan_inst
->exec_size
== 16)
3221 needs_dep
[reg
- first_write_grf
+ 1] = false;
3226 /* Clear the flag for registers that actually got read (as expected). */
3227 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3229 /* Continue the loop only if we haven't resolved all the dependencies */
3231 for (i
= 0; i
< write_len
; i
++) {
3241 * Implements this workaround for the original 965:
3243 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3244 * used as a destination register until after it has been sourced by an
3245 * instruction with a different destination register.
3248 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3250 int write_len
= inst
->regs_written
;
3251 int first_write_grf
= inst
->dst
.nr
;
3252 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3253 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3255 memset(needs_dep
, false, sizeof(needs_dep
));
3256 memset(needs_dep
, true, write_len
);
3257 /* Walk forwards looking for writes to registers we're writing which aren't
3258 * read before being written.
3260 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3261 /* If we hit control flow, force resolve all remaining dependencies. */
3262 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3263 for (int i
= 0; i
< write_len
; i
++) {
3265 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3266 first_write_grf
+ i
);
3271 /* Clear the flag for registers that actually got read (as expected). */
3272 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3274 /* We insert our reads as late as possible since they're reading the
3275 * result of a SEND, which has massive latency.
3277 if (scan_inst
->dst
.file
== VGRF
&&
3278 scan_inst
->dst
.nr
>= first_write_grf
&&
3279 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3280 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3281 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3283 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3286 /* Continue the loop only if we haven't resolved all the dependencies */
3288 for (i
= 0; i
< write_len
; i
++) {
3298 fs_visitor::insert_gen4_send_dependency_workarounds()
3300 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3303 bool progress
= false;
3305 /* Note that we're done with register allocation, so GRF fs_regs always
3306 * have a .reg_offset of 0.
3309 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3310 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3311 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3312 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3318 invalidate_live_intervals();
3322 * Turns the generic expression-style uniform pull constant load instruction
3323 * into a hardware-specific series of instructions for loading a pull
3326 * The expression style allows the CSE pass before this to optimize out
3327 * repeated loads from the same offset, and gives the pre-register-allocation
3328 * scheduling full flexibility, while the conversion to native instructions
3329 * allows the post-register-allocation scheduler the best information
3332 * Note that execution masking for setting up pull constant loads is special:
3333 * the channels that need to be written are unrelated to the current execution
3334 * mask, since a later instruction will use one of the result channels as a
3335 * source operand for all 8 or 16 of its channels.
3338 fs_visitor::lower_uniform_pull_constant_loads()
3340 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3341 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3344 if (devinfo
->gen
>= 7) {
3345 /* The offset arg is a vec4-aligned immediate byte offset. */
3346 fs_reg const_offset_reg
= inst
->src
[1];
3347 assert(const_offset_reg
.file
== IMM
&&
3348 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3349 assert(const_offset_reg
.ud
% 16 == 0);
3351 fs_reg payload
, offset
;
3352 if (devinfo
->gen
>= 9) {
3353 /* We have to use a message header on Skylake to get SIMD4x2
3354 * mode. Reserve space for the register.
3356 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3357 offset
.reg_offset
++;
3360 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3364 /* This is actually going to be a MOV, but since only the first dword
3365 * is accessed, we have a special opcode to do just that one. Note
3366 * that this needs to be an operation that will be considered a def
3367 * by live variable analysis, or register allocation will explode.
3369 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3370 8, offset
, const_offset_reg
);
3371 setup
->force_writemask_all
= true;
3373 setup
->ir
= inst
->ir
;
3374 setup
->annotation
= inst
->annotation
;
3375 inst
->insert_before(block
, setup
);
3377 /* Similarly, this will only populate the first 4 channels of the
3378 * result register (since we only use smear values from 0-3), but we
3379 * don't tell the optimizer.
3381 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3382 inst
->src
[1] = payload
;
3383 inst
->base_mrf
= -1;
3385 invalidate_live_intervals();
3387 /* Before register allocation, we didn't tell the scheduler about the
3388 * MRF we use. We know it's safe to use this MRF because nothing
3389 * else does except for register spill/unspill, which generates and
3390 * uses its MRF within a single IR instruction.
3392 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3399 fs_visitor::lower_load_payload()
3401 bool progress
= false;
3403 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3404 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3407 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3408 assert(inst
->saturate
== false);
3409 fs_reg dst
= inst
->dst
;
3411 /* Get rid of COMPR4. We'll add it back in if we need it */
3412 if (dst
.file
== MRF
)
3413 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3415 const fs_builder
ibld(this, block
, inst
);
3416 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3418 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3419 if (inst
->src
[i
].file
!= BAD_FILE
) {
3420 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3421 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3422 hbld
.MOV(mov_dst
, mov_src
);
3424 dst
= offset(dst
, hbld
, 1);
3427 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3428 inst
->exec_size
> 8) {
3429 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3430 * a straightforward copy. Instead, the result of the
3431 * LOAD_PAYLOAD is treated as interleaved and the first four
3432 * non-header sources are unpacked as:
3443 * This is used for gen <= 5 fb writes.
3445 assert(inst
->exec_size
== 16);
3446 assert(inst
->header_size
+ 4 <= inst
->sources
);
3447 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3448 if (inst
->src
[i
].file
!= BAD_FILE
) {
3449 if (devinfo
->has_compr4
) {
3450 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3451 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3452 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3454 /* Platform doesn't have COMPR4. We have to fake it */
3455 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3456 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3458 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3465 /* The loop above only ever incremented us through the first set
3466 * of 4 registers. However, thanks to the magic of COMPR4, we
3467 * actually wrote to the first 8 registers, so we need to take
3468 * that into account now.
3472 /* The COMPR4 code took care of the first 4 sources. We'll let
3473 * the regular path handle any remaining sources. Yes, we are
3474 * modifying the instruction but we're about to delete it so
3475 * this really doesn't hurt anything.
3477 inst
->header_size
+= 4;
3480 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3481 if (inst
->src
[i
].file
!= BAD_FILE
)
3482 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3483 dst
= offset(dst
, ibld
, 1);
3486 inst
->remove(block
);
3491 invalidate_live_intervals();
3497 fs_visitor::lower_integer_multiplication()
3499 bool progress
= false;
3501 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3502 const fs_builder
ibld(this, block
, inst
);
3504 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3505 if (inst
->dst
.is_accumulator() ||
3506 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3507 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3510 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3511 * operation directly, but CHV/BXT cannot.
3513 if (devinfo
->gen
>= 8 &&
3514 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3517 if (inst
->src
[1].file
== IMM
&&
3518 inst
->src
[1].ud
< (1 << 16)) {
3519 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3520 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3523 * If multiplying by an immediate value that fits in 16-bits, do a
3524 * single MUL instruction with that value in the proper location.
3526 if (devinfo
->gen
< 7) {
3527 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3529 ibld
.MOV(imm
, inst
->src
[1]);
3530 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3532 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3535 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3536 * do 32-bit integer multiplication in one instruction, but instead
3537 * must do a sequence (which actually calculates a 64-bit result):
3539 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3540 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3541 * mov(8) g2<1>D acc0<8,8,1>D
3543 * But on Gen > 6, the ability to use second accumulator register
3544 * (acc1) for non-float data types was removed, preventing a simple
3545 * implementation in SIMD16. A 16-channel result can be calculated by
3546 * executing the three instructions twice in SIMD8, once with quarter
3547 * control of 1Q for the first eight channels and again with 2Q for
3548 * the second eight channels.
3550 * Which accumulator register is implicitly accessed (by AccWrEnable
3551 * for instance) is determined by the quarter control. Unfortunately
3552 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3553 * implicit accumulator access by an instruction with 2Q will access
3554 * acc1 regardless of whether the data type is usable in acc1.
3556 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3557 * integer data types.
3559 * Since we only want the low 32-bits of the result, we can do two
3560 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3561 * adjust the high result and add them (like the mach is doing):
3563 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3564 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3565 * shl(8) g9<1>D g8<8,8,1>D 16D
3566 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3568 * We avoid the shl instruction by realizing that we only want to add
3569 * the low 16-bits of the "high" result to the high 16-bits of the
3570 * "low" result and using proper regioning on the add:
3572 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3573 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3574 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3576 * Since it does not use the (single) accumulator register, we can
3577 * schedule multi-component multiplications much better.
3580 fs_reg orig_dst
= inst
->dst
;
3581 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3582 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3585 fs_reg low
= inst
->dst
;
3586 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3589 if (devinfo
->gen
>= 7) {
3590 fs_reg src1_0_w
= inst
->src
[1];
3591 fs_reg src1_1_w
= inst
->src
[1];
3593 if (inst
->src
[1].file
== IMM
) {
3594 src1_0_w
.ud
&= 0xffff;
3597 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3598 if (src1_0_w
.stride
!= 0) {
3599 assert(src1_0_w
.stride
== 1);
3600 src1_0_w
.stride
= 2;
3603 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3604 if (src1_1_w
.stride
!= 0) {
3605 assert(src1_1_w
.stride
== 1);
3606 src1_1_w
.stride
= 2;
3608 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3610 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3611 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3613 fs_reg src0_0_w
= inst
->src
[0];
3614 fs_reg src0_1_w
= inst
->src
[0];
3616 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3617 if (src0_0_w
.stride
!= 0) {
3618 assert(src0_0_w
.stride
== 1);
3619 src0_0_w
.stride
= 2;
3622 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3623 if (src0_1_w
.stride
!= 0) {
3624 assert(src0_1_w
.stride
== 1);
3625 src0_1_w
.stride
= 2;
3627 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3629 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3630 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3633 fs_reg dst
= inst
->dst
;
3634 dst
.type
= BRW_REGISTER_TYPE_UW
;
3635 dst
.subreg_offset
= 2;
3638 high
.type
= BRW_REGISTER_TYPE_UW
;
3641 low
.type
= BRW_REGISTER_TYPE_UW
;
3642 low
.subreg_offset
= 2;
3645 ibld
.ADD(dst
, low
, high
);
3647 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3648 set_condmod(inst
->conditional_mod
,
3649 ibld
.MOV(orig_dst
, inst
->dst
));
3653 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3654 /* Should have been lowered to 8-wide. */
3655 assert(inst
->exec_size
<= 8);
3656 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3658 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3659 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3661 if (devinfo
->gen
>= 8) {
3662 /* Until Gen8, integer multiplies read 32-bits from one source,
3663 * and 16-bits from the other, and relying on the MACH instruction
3664 * to generate the high bits of the result.
3666 * On Gen8, the multiply instruction does a full 32x32-bit
3667 * multiply, but in order to do a 64-bit multiply we can simulate
3668 * the previous behavior and then use a MACH instruction.
3670 * FINISHME: Don't use source modifiers on src1.
3672 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3673 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3674 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3675 mul
->src
[1].stride
*= 2;
3677 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3679 /* Among other things the quarter control bits influence which
3680 * accumulator register is used by the hardware for instructions
3681 * that access the accumulator implicitly (e.g. MACH). A
3682 * second-half instruction would normally map to acc1, which
3683 * doesn't exist on Gen7 and up (the hardware does emulate it for
3684 * floating-point instructions *only* by taking advantage of the
3685 * extra precision of acc0 not normally used for floating point
3688 * HSW and up are careful enough not to try to access an
3689 * accumulator register that doesn't exist, but on earlier Gen7
3690 * hardware we need to make sure that the quarter control bits are
3691 * zero to avoid non-deterministic behaviour and emit an extra MOV
3692 * to get the result masked correctly according to the current
3696 mach
->force_writemask_all
= true;
3697 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3698 ibld
.MOV(inst
->dst
, mach
->dst
);
3704 inst
->remove(block
);
3709 invalidate_live_intervals();
3715 fs_visitor::lower_minmax()
3717 assert(devinfo
->gen
< 6);
3719 bool progress
= false;
3721 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3722 const fs_builder
ibld(this, block
, inst
);
3724 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3725 inst
->predicate
== BRW_PREDICATE_NONE
) {
3726 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3727 * the original SEL.L/GE instruction
3729 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3730 inst
->conditional_mod
);
3731 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3732 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3739 invalidate_live_intervals();
3745 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3746 fs_reg
*dst
, fs_reg color
, unsigned components
)
3748 if (key
->clamp_fragment_color
) {
3749 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3750 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3752 for (unsigned i
= 0; i
< components
; i
++)
3754 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3759 for (unsigned i
= 0; i
< components
; i
++)
3760 dst
[i
] = offset(color
, bld
, i
);
3764 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3765 const brw_wm_prog_data
*prog_data
,
3766 const brw_wm_prog_key
*key
,
3767 const fs_visitor::thread_payload
&payload
)
3769 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3770 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3771 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3772 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3773 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3774 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3775 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3776 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3777 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3778 const unsigned components
=
3779 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3781 /* We can potentially have a message length of up to 15, so we have to set
3782 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3785 int header_size
= 2, payload_header_size
;
3786 unsigned length
= 0;
3788 /* From the Sandy Bridge PRM, volume 4, page 198:
3790 * "Dispatched Pixel Enables. One bit per pixel indicating
3791 * which pixels were originally enabled when the thread was
3792 * dispatched. This field is only required for the end-of-
3793 * thread message and on all dual-source messages."
3795 if (devinfo
->gen
>= 6 &&
3796 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3797 color1
.file
== BAD_FILE
&&
3798 key
->nr_color_regions
== 1) {
3802 if (header_size
!= 0) {
3803 assert(header_size
== 2);
3804 /* Allocate 2 registers for a header */
3808 if (payload
.aa_dest_stencil_reg
) {
3809 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3810 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3811 .MOV(sources
[length
],
3812 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3816 if (sample_mask
.file
!= BAD_FILE
) {
3817 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3818 BRW_REGISTER_TYPE_UD
);
3820 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3821 * relevant. Since it's unsigned single words one vgrf is always
3822 * 16-wide, but only the lower or higher 8 channels will be used by the
3823 * hardware when doing a SIMD8 write depending on whether we have
3824 * selected the subspans for the first or second half respectively.
3826 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3827 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3828 sample_mask
.stride
*= 2;
3830 bld
.exec_all().annotate("FB write oMask")
3831 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3837 payload_header_size
= length
;
3839 if (src0_alpha
.file
!= BAD_FILE
) {
3840 /* FIXME: This is being passed at the wrong location in the payload and
3841 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3842 * It's supposed to be immediately before oMask but there seems to be no
3843 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3844 * requires header sources to form a contiguous segment at the beginning
3845 * of the message and src0_alpha has per-channel semantics.
3847 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3851 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3854 if (color1
.file
!= BAD_FILE
) {
3855 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3859 if (src_depth
.file
!= BAD_FILE
) {
3860 sources
[length
] = src_depth
;
3864 if (dst_depth
.file
!= BAD_FILE
) {
3865 sources
[length
] = dst_depth
;
3869 if (src_stencil
.file
!= BAD_FILE
) {
3870 assert(devinfo
->gen
>= 9);
3871 assert(bld
.dispatch_width() != 16);
3873 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3874 * available on gen9+. As such it's impossible to have both enabled at the
3875 * same time and therefore length cannot overrun the array.
3877 assert(length
< 15);
3879 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3880 bld
.exec_all().annotate("FB write OS")
3881 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
3882 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
3887 if (devinfo
->gen
>= 7) {
3888 /* Send from the GRF */
3889 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3890 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3891 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3892 load
->dst
= payload
;
3894 inst
->src
[0] = payload
;
3895 inst
->resize_sources(1);
3896 inst
->base_mrf
= -1;
3898 /* Send from the MRF */
3899 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3900 sources
, length
, payload_header_size
);
3902 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3903 * will do this for us if we just give it a COMPR4 destination.
3905 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3906 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3908 inst
->resize_sources(0);
3912 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3913 inst
->mlen
= load
->regs_written
;
3914 inst
->header_size
= header_size
;
3918 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3919 const fs_reg
&coordinate
,
3920 const fs_reg
&shadow_c
,
3921 const fs_reg
&lod
, const fs_reg
&lod2
,
3922 const fs_reg
&surface
,
3923 const fs_reg
&sampler
,
3924 unsigned coord_components
,
3925 unsigned grad_components
)
3927 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3928 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3929 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3930 fs_reg msg_end
= msg_begin
;
3933 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3935 for (unsigned i
= 0; i
< coord_components
; i
++)
3936 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3937 offset(coordinate
, bld
, i
));
3939 msg_end
= offset(msg_end
, bld
, coord_components
);
3941 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3942 * require all three components to be present and zero if they are unused.
3944 if (coord_components
> 0 &&
3945 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3946 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3947 for (unsigned i
= coord_components
; i
< 3; i
++)
3948 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3950 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3953 if (op
== SHADER_OPCODE_TXD
) {
3954 /* TXD unsupported in SIMD16 mode. */
3955 assert(bld
.dispatch_width() == 8);
3957 /* the slots for u and v are always present, but r is optional */
3958 if (coord_components
< 2)
3959 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3962 * dPdx = dudx, dvdx, drdx
3963 * dPdy = dudy, dvdy, drdy
3965 * 1-arg: Does not exist.
3967 * 2-arg: dudx dvdx dudy dvdy
3968 * dPdx.x dPdx.y dPdy.x dPdy.y
3971 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3972 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3973 * m5 m6 m7 m8 m9 m10
3975 for (unsigned i
= 0; i
< grad_components
; i
++)
3976 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3978 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3980 for (unsigned i
= 0; i
< grad_components
; i
++)
3981 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3983 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3987 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3988 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3990 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3991 bld
.dispatch_width() == 16);
3993 const brw_reg_type type
=
3994 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3995 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3996 bld
.MOV(retype(msg_end
, type
), lod
);
3997 msg_end
= offset(msg_end
, bld
, 1);
4000 if (shadow_c
.file
!= BAD_FILE
) {
4001 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
4002 /* There's no plain shadow compare message, so we use shadow
4003 * compare with a bias of 0.0.
4005 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
4006 msg_end
= offset(msg_end
, bld
, 1);
4009 bld
.MOV(msg_end
, shadow_c
);
4010 msg_end
= offset(msg_end
, bld
, 1);
4014 inst
->src
[0] = reg_undef
;
4015 inst
->src
[1] = surface
;
4016 inst
->src
[2] = sampler
;
4017 inst
->resize_sources(3);
4018 inst
->base_mrf
= msg_begin
.nr
;
4019 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
4020 inst
->header_size
= 1;
4024 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4025 const fs_reg
&coordinate
,
4026 const fs_reg
&shadow_c
,
4027 const fs_reg
&lod
, const fs_reg
&lod2
,
4028 const fs_reg
&sample_index
,
4029 const fs_reg
&surface
,
4030 const fs_reg
&sampler
,
4031 const fs_reg
&offset_value
,
4032 unsigned coord_components
,
4033 unsigned grad_components
)
4035 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
4036 fs_reg msg_coords
= message
;
4037 unsigned header_size
= 0;
4039 if (offset_value
.file
!= BAD_FILE
) {
4040 /* The offsets set up by the visitor are in the m1 header, so we can't
4047 for (unsigned i
= 0; i
< coord_components
; i
++)
4048 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
4049 offset(coordinate
, bld
, i
));
4051 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
4052 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
4054 if (shadow_c
.file
!= BAD_FILE
) {
4055 fs_reg msg_shadow
= msg_lod
;
4056 bld
.MOV(msg_shadow
, shadow_c
);
4057 msg_lod
= offset(msg_shadow
, bld
, 1);
4062 case SHADER_OPCODE_TXL
:
4064 bld
.MOV(msg_lod
, lod
);
4065 msg_end
= offset(msg_lod
, bld
, 1);
4067 case SHADER_OPCODE_TXD
:
4070 * dPdx = dudx, dvdx, drdx
4071 * dPdy = dudy, dvdy, drdy
4073 * Load up these values:
4074 * - dudx dudy dvdx dvdy drdx drdy
4075 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
4078 for (unsigned i
= 0; i
< grad_components
; i
++) {
4079 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
4080 msg_end
= offset(msg_end
, bld
, 1);
4082 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
4083 msg_end
= offset(msg_end
, bld
, 1);
4086 case SHADER_OPCODE_TXS
:
4087 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4088 bld
.MOV(msg_lod
, lod
);
4089 msg_end
= offset(msg_lod
, bld
, 1);
4091 case SHADER_OPCODE_TXF
:
4092 msg_lod
= offset(msg_coords
, bld
, 3);
4093 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4094 msg_end
= offset(msg_lod
, bld
, 1);
4096 case SHADER_OPCODE_TXF_CMS
:
4097 msg_lod
= offset(msg_coords
, bld
, 3);
4099 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4101 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4102 msg_end
= offset(msg_lod
, bld
, 2);
4109 inst
->src
[0] = reg_undef
;
4110 inst
->src
[1] = surface
;
4111 inst
->src
[2] = sampler
;
4112 inst
->resize_sources(3);
4113 inst
->base_mrf
= message
.nr
;
4114 inst
->mlen
= msg_end
.nr
- message
.nr
;
4115 inst
->header_size
= header_size
;
4117 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4118 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4122 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
4124 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4127 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4131 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4132 const fs_reg
&coordinate
,
4133 const fs_reg
&shadow_c
,
4134 fs_reg lod
, const fs_reg
&lod2
,
4135 const fs_reg
&sample_index
,
4137 const fs_reg
&surface
,
4138 const fs_reg
&sampler
,
4139 const fs_reg
&offset_value
,
4140 unsigned coord_components
,
4141 unsigned grad_components
)
4143 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4144 int reg_width
= bld
.dispatch_width() / 8;
4145 unsigned header_size
= 0, length
= 0;
4146 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4147 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4148 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4150 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4151 offset_value
.file
!= BAD_FILE
|| inst
->eot
||
4152 op
== SHADER_OPCODE_SAMPLEINFO
||
4153 is_high_sampler(devinfo
, sampler
)) {
4154 /* For general texture offsets (no txf workaround), we need a header to
4155 * put them in. Note that we're only reserving space for it in the
4156 * message payload as it will be initialized implicitly by the
4159 * TG4 needs to place its channel select in the header, for interaction
4160 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4161 * larger sampler numbers we need to offset the Sampler State Pointer in
4165 sources
[0] = fs_reg();
4168 /* If we're requesting fewer than four channels worth of response,
4169 * and we have an explicit header, we need to set up the sampler
4170 * writemask. It's reversed from normal: 1 means "don't write".
4172 if (!inst
->eot
&& inst
->regs_written
!= 4 * reg_width
) {
4173 assert((inst
->regs_written
% reg_width
) == 0);
4174 unsigned mask
= ~((1 << (inst
->regs_written
/ reg_width
)) - 1) & 0xf;
4175 inst
->offset
|= mask
<< 12;
4179 if (shadow_c
.file
!= BAD_FILE
) {
4180 bld
.MOV(sources
[length
], shadow_c
);
4184 bool coordinate_done
= false;
4186 /* The sampler can only meaningfully compute LOD for fragment shader
4187 * messages. For all other stages, we change the opcode to TXL and
4188 * hardcode the LOD to 0.
4190 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
4191 op
== SHADER_OPCODE_TEX
) {
4192 op
= SHADER_OPCODE_TXL
;
4193 lod
= brw_imm_f(0.0f
);
4196 /* Set up the LOD info */
4199 case SHADER_OPCODE_TXL
:
4200 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4201 op
= SHADER_OPCODE_TXL_LZ
;
4204 bld
.MOV(sources
[length
], lod
);
4207 case SHADER_OPCODE_TXD
:
4208 /* TXD should have been lowered in SIMD16 mode. */
4209 assert(bld
.dispatch_width() == 8);
4211 /* Load dPdx and the coordinate together:
4212 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4214 for (unsigned i
= 0; i
< coord_components
; i
++) {
4215 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4217 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4218 * only derivatives for (u, v, r).
4220 if (i
< grad_components
) {
4221 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4222 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4226 coordinate_done
= true;
4228 case SHADER_OPCODE_TXS
:
4229 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4232 case SHADER_OPCODE_TXF
:
4233 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4234 * On Gen9 they are u, v, lod, r
4236 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4238 if (devinfo
->gen
>= 9) {
4239 if (coord_components
>= 2) {
4240 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4241 offset(coordinate
, bld
, 1));
4246 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4247 op
= SHADER_OPCODE_TXF_LZ
;
4249 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4253 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4254 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4255 offset(coordinate
, bld
, i
));
4257 coordinate_done
= true;
4260 case SHADER_OPCODE_TXF_CMS
:
4261 case SHADER_OPCODE_TXF_CMS_W
:
4262 case SHADER_OPCODE_TXF_UMS
:
4263 case SHADER_OPCODE_TXF_MCS
:
4264 if (op
== SHADER_OPCODE_TXF_UMS
||
4265 op
== SHADER_OPCODE_TXF_CMS
||
4266 op
== SHADER_OPCODE_TXF_CMS_W
) {
4267 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4271 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4272 /* Data from the multisample control surface. */
4273 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4276 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4279 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4280 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4283 offset(mcs
, bld
, 1));
4288 /* There is no offsetting for this message; just copy in the integer
4289 * texture coordinates.
4291 for (unsigned i
= 0; i
< coord_components
; i
++)
4292 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4293 offset(coordinate
, bld
, i
));
4295 coordinate_done
= true;
4297 case SHADER_OPCODE_TG4_OFFSET
:
4298 /* gather4_po_c should have been lowered in SIMD16 mode. */
4299 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
4301 /* More crazy intermixing */
4302 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4303 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4305 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4306 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4307 offset(offset_value
, bld
, i
));
4309 if (coord_components
== 3) /* r if present */
4310 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4312 coordinate_done
= true;
4318 /* Set up the coordinate (except for cases where it was done above) */
4319 if (!coordinate_done
) {
4320 for (unsigned i
= 0; i
< coord_components
; i
++)
4321 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4326 mlen
= length
* reg_width
- header_size
;
4328 mlen
= length
* reg_width
;
4330 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4331 BRW_REGISTER_TYPE_F
);
4332 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4334 /* Generate the SEND. */
4336 inst
->src
[0] = src_payload
;
4337 inst
->src
[1] = surface
;
4338 inst
->src
[2] = sampler
;
4339 inst
->resize_sources(3);
4340 inst
->base_mrf
= -1;
4342 inst
->header_size
= header_size
;
4344 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4345 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4349 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4351 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4352 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4353 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4354 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4355 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4356 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4357 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4358 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4359 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4360 const fs_reg
&offset_value
= inst
->src
[TEX_LOGICAL_SRC_OFFSET_VALUE
];
4361 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4362 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4363 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4364 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4366 if (devinfo
->gen
>= 7) {
4367 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4368 shadow_c
, lod
, lod2
, sample_index
,
4369 mcs
, surface
, sampler
, offset_value
,
4370 coord_components
, grad_components
);
4371 } else if (devinfo
->gen
>= 5) {
4372 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4373 shadow_c
, lod
, lod2
, sample_index
,
4374 surface
, sampler
, offset_value
,
4375 coord_components
, grad_components
);
4377 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4378 shadow_c
, lod
, lod2
,
4380 coord_components
, grad_components
);
4385 * Initialize the header present in some typed and untyped surface
4389 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4391 fs_builder ubld
= bld
.exec_all().group(8, 0);
4392 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4393 ubld
.MOV(dst
, brw_imm_d(0));
4394 ubld
.MOV(component(dst
, 7), sample_mask
);
4399 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4400 const fs_reg
&sample_mask
)
4402 /* Get the logical send arguments. */
4403 const fs_reg
&addr
= inst
->src
[0];
4404 const fs_reg
&src
= inst
->src
[1];
4405 const fs_reg
&surface
= inst
->src
[2];
4406 const UNUSED fs_reg
&dims
= inst
->src
[3];
4407 const fs_reg
&arg
= inst
->src
[4];
4409 /* Calculate the total number of components of the payload. */
4410 const unsigned addr_sz
= inst
->components_read(0);
4411 const unsigned src_sz
= inst
->components_read(1);
4412 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4413 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4415 /* Allocate space for the payload. */
4416 fs_reg
*const components
= new fs_reg
[sz
];
4417 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4420 /* Construct the payload. */
4422 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4424 for (unsigned i
= 0; i
< addr_sz
; i
++)
4425 components
[n
++] = offset(addr
, bld
, i
);
4427 for (unsigned i
= 0; i
< src_sz
; i
++)
4428 components
[n
++] = offset(src
, bld
, i
);
4430 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4432 /* Update the original instruction. */
4434 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4435 inst
->header_size
= header_sz
;
4437 inst
->src
[0] = payload
;
4438 inst
->src
[1] = surface
;
4440 inst
->resize_sources(3);
4442 delete[] components
;
4446 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4448 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4450 if (devinfo
->gen
>= 7) {
4451 /* We are switching the instruction from an ALU-like instruction to a
4452 * send-from-grf instruction. Since sends can't handle strides or
4453 * source modifiers, we have to make a copy of the offset source.
4455 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4456 bld
.MOV(tmp
, inst
->src
[1]);
4459 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4462 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4463 BRW_REGISTER_TYPE_UD
);
4465 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4467 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4468 inst
->resize_sources(1);
4469 inst
->base_mrf
= payload
.nr
;
4470 inst
->header_size
= 1;
4471 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4476 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4478 assert(bld
.shader
->devinfo
->gen
< 6);
4481 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4483 if (inst
->sources
> 1) {
4484 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4485 * "Message Payload":
4487 * "Operand0[7]. For the INT DIV functions, this operand is the
4490 * "Operand1[7]. For the INT DIV functions, this operand is the
4493 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4494 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4495 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4497 inst
->resize_sources(1);
4498 inst
->src
[0] = src0
;
4500 assert(inst
->exec_size
== 8);
4501 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4506 fs_visitor::lower_logical_sends()
4508 bool progress
= false;
4510 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4511 const fs_builder
ibld(this, block
, inst
);
4513 switch (inst
->opcode
) {
4514 case FS_OPCODE_FB_WRITE_LOGICAL
:
4515 assert(stage
== MESA_SHADER_FRAGMENT
);
4516 lower_fb_write_logical_send(ibld
, inst
,
4517 (const brw_wm_prog_data
*)prog_data
,
4518 (const brw_wm_prog_key
*)key
,
4522 case SHADER_OPCODE_TEX_LOGICAL
:
4523 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4526 case SHADER_OPCODE_TXD_LOGICAL
:
4527 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4530 case SHADER_OPCODE_TXF_LOGICAL
:
4531 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4534 case SHADER_OPCODE_TXL_LOGICAL
:
4535 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4538 case SHADER_OPCODE_TXS_LOGICAL
:
4539 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4542 case FS_OPCODE_TXB_LOGICAL
:
4543 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4546 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4547 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4550 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4551 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4554 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4555 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4558 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4559 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4562 case SHADER_OPCODE_LOD_LOGICAL
:
4563 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4566 case SHADER_OPCODE_TG4_LOGICAL
:
4567 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4570 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4571 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4574 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4575 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
4578 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4579 lower_surface_logical_send(ibld
, inst
,
4580 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4584 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4585 lower_surface_logical_send(ibld
, inst
,
4586 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4587 ibld
.sample_mask_reg());
4590 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4591 lower_surface_logical_send(ibld
, inst
,
4592 SHADER_OPCODE_UNTYPED_ATOMIC
,
4593 ibld
.sample_mask_reg());
4596 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4597 lower_surface_logical_send(ibld
, inst
,
4598 SHADER_OPCODE_TYPED_SURFACE_READ
,
4602 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4603 lower_surface_logical_send(ibld
, inst
,
4604 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4605 ibld
.sample_mask_reg());
4608 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4609 lower_surface_logical_send(ibld
, inst
,
4610 SHADER_OPCODE_TYPED_ATOMIC
,
4611 ibld
.sample_mask_reg());
4614 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4615 lower_varying_pull_constant_logical_send(ibld
, inst
);
4618 case SHADER_OPCODE_RCP
:
4619 case SHADER_OPCODE_RSQ
:
4620 case SHADER_OPCODE_SQRT
:
4621 case SHADER_OPCODE_EXP2
:
4622 case SHADER_OPCODE_LOG2
:
4623 case SHADER_OPCODE_SIN
:
4624 case SHADER_OPCODE_COS
:
4625 case SHADER_OPCODE_POW
:
4626 case SHADER_OPCODE_INT_QUOTIENT
:
4627 case SHADER_OPCODE_INT_REMAINDER
:
4628 /* The math opcodes are overloaded for the send-like and
4629 * expression-like instructions which seems kind of icky. Gen6+ has
4630 * a native (but rather quirky) MATH instruction so we don't need to
4631 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
4632 * logical instructions (which we can easily recognize because they
4633 * have mlen = 0) into send-like virtual instructions.
4635 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
4636 lower_math_logical_send(ibld
, inst
);
4651 invalidate_live_intervals();
4657 * Get the closest allowed SIMD width for instruction \p inst accounting for
4658 * some common regioning and execution control restrictions that apply to FPU
4659 * instructions. These restrictions don't necessarily have any relevance to
4660 * instructions not executed by the FPU pipeline like extended math, control
4661 * flow or send message instructions.
4663 * For virtual opcodes it's really up to the instruction -- In some cases
4664 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
4665 * instructions) it may simplify virtual instruction lowering if we can
4666 * enforce FPU-like regioning restrictions already on the virtual instruction,
4667 * in other cases (e.g. virtual send-like instructions) this may be
4668 * excessively restrictive.
4671 get_fpu_lowered_simd_width(const struct brw_device_info
*devinfo
,
4672 const fs_inst
*inst
)
4674 /* Maximum execution size representable in the instruction controls. */
4675 unsigned max_width
= MIN2(32, inst
->exec_size
);
4677 /* According to the PRMs:
4678 * "A. In Direct Addressing mode, a source cannot span more than 2
4679 * adjacent GRF registers.
4680 * B. A destination cannot span more than 2 adjacent GRF registers."
4682 * Look for the source or destination with the largest register region
4683 * which is the one that is going to limit the overall execution size of
4684 * the instruction due to this rule.
4686 unsigned reg_count
= inst
->regs_written
;
4688 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4689 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4691 /* Calculate the maximum execution size of the instruction based on the
4692 * factor by which it goes over the hardware limit of 2 GRFs.
4695 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
4697 /* According to the IVB PRMs:
4698 * "When destination spans two registers, the source MUST span two
4699 * registers. The exception to the above rule:
4701 * - When source is scalar, the source registers are not incremented.
4702 * - When source is packed integer Word and destination is packed
4703 * integer DWord, the source register is not incremented but the
4704 * source sub register is incremented."
4706 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
4707 * restrictions. The code below intentionally doesn't check whether the
4708 * destination type is integer because empirically the hardware doesn't
4709 * seem to care what the actual type is as long as it's dword-aligned.
4711 if (devinfo
->gen
< 8) {
4712 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
4713 if (inst
->regs_written
== 2 &&
4714 inst
->regs_read(i
) != 0 && inst
->regs_read(i
) != 2 &&
4715 !is_uniform(inst
->src
[i
]) &&
4716 !(type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
4717 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1))
4718 max_width
= MIN2(max_width
, inst
->exec_size
/
4719 inst
->regs_written
);
4723 /* From the IVB PRMs:
4724 * "When an instruction is SIMD32, the low 16 bits of the execution mask
4725 * are applied for both halves of the SIMD32 instruction. If different
4726 * execution mask channels are required, split the instruction into two
4727 * SIMD16 instructions."
4729 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
4730 * 32-wide control flow support in hardware and will behave similarly.
4732 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
4733 max_width
= MIN2(max_width
, 16);
4735 /* From the IVB PRMs (applies to HSW too):
4736 * "Instructions with condition modifiers must not use SIMD32."
4738 * From the BDW PRMs (applies to later hardware too):
4739 * "Ternary instruction with condition modifiers must not use SIMD32."
4741 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
4742 max_width
= MIN2(max_width
, 16);
4744 /* From the IVB PRMs (applies to other devices that don't have the
4745 * brw_device_info::supports_simd16_3src flag set):
4746 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
4747 * SIMD8 is not allowed for DF operations."
4749 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
4750 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4752 /* Only power-of-two execution sizes are representable in the instruction
4755 return 1 << _mesa_logbase2(max_width
);
4759 * Get the closest native SIMD width supported by the hardware for instruction
4760 * \p inst. The instruction will be left untouched by
4761 * fs_visitor::lower_simd_width() if the returned value is equal to the
4762 * original execution size.
4765 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4766 const fs_inst
*inst
)
4768 switch (inst
->opcode
) {
4769 case BRW_OPCODE_MOV
:
4770 case BRW_OPCODE_SEL
:
4771 case BRW_OPCODE_NOT
:
4772 case BRW_OPCODE_AND
:
4774 case BRW_OPCODE_XOR
:
4775 case BRW_OPCODE_SHR
:
4776 case BRW_OPCODE_SHL
:
4777 case BRW_OPCODE_ASR
:
4778 case BRW_OPCODE_CMPN
:
4779 case BRW_OPCODE_CSEL
:
4780 case BRW_OPCODE_F32TO16
:
4781 case BRW_OPCODE_F16TO32
:
4782 case BRW_OPCODE_BFREV
:
4783 case BRW_OPCODE_BFE
:
4784 case BRW_OPCODE_ADD
:
4785 case BRW_OPCODE_MUL
:
4786 case BRW_OPCODE_AVG
:
4787 case BRW_OPCODE_FRC
:
4788 case BRW_OPCODE_RNDU
:
4789 case BRW_OPCODE_RNDD
:
4790 case BRW_OPCODE_RNDE
:
4791 case BRW_OPCODE_RNDZ
:
4792 case BRW_OPCODE_LZD
:
4793 case BRW_OPCODE_FBH
:
4794 case BRW_OPCODE_FBL
:
4795 case BRW_OPCODE_CBIT
:
4796 case BRW_OPCODE_SAD2
:
4797 case BRW_OPCODE_MAD
:
4798 case BRW_OPCODE_LRP
:
4799 case FS_OPCODE_PACK
:
4800 return get_fpu_lowered_simd_width(devinfo
, inst
);
4802 case BRW_OPCODE_CMP
: {
4803 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
4804 * when the destination is a GRF the dependency-clear bit on the flag
4805 * register is cleared early.
4807 * Suggested workarounds are to disable coissuing CMP instructions
4808 * or to split CMP(16) instructions into two CMP(8) instructions.
4810 * We choose to split into CMP(8) instructions since disabling
4811 * coissuing would affect CMP instructions not otherwise affected by
4814 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4815 !inst
->dst
.is_null() ? 8 : ~0);
4816 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
4818 case BRW_OPCODE_BFI1
:
4819 case BRW_OPCODE_BFI2
:
4820 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
4822 * "Force BFI instructions to be executed always in SIMD8."
4824 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
4825 get_fpu_lowered_simd_width(devinfo
, inst
));
4828 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
4829 return inst
->exec_size
;
4831 case SHADER_OPCODE_RCP
:
4832 case SHADER_OPCODE_RSQ
:
4833 case SHADER_OPCODE_SQRT
:
4834 case SHADER_OPCODE_EXP2
:
4835 case SHADER_OPCODE_LOG2
:
4836 case SHADER_OPCODE_SIN
:
4837 case SHADER_OPCODE_COS
:
4838 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
4841 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4842 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
4843 MIN2(8, inst
->exec_size
));
4845 case SHADER_OPCODE_POW
:
4846 /* SIMD16 is only allowed on Gen7+. */
4847 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4848 MIN2(8, inst
->exec_size
));
4850 case SHADER_OPCODE_INT_QUOTIENT
:
4851 case SHADER_OPCODE_INT_REMAINDER
:
4852 /* Integer division is limited to SIMD8 on all generations. */
4853 return MIN2(8, inst
->exec_size
);
4855 case FS_OPCODE_LINTERP
:
4856 case FS_OPCODE_GET_BUFFER_SIZE
:
4857 case FS_OPCODE_DDX_COARSE
:
4858 case FS_OPCODE_DDX_FINE
:
4859 case FS_OPCODE_DDY_COARSE
:
4860 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
4861 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
4862 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
4863 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
4864 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
4865 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
4866 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
4867 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
4868 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
4869 return MIN2(16, inst
->exec_size
);
4871 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4872 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
4873 * message used to implement varying pull constant loads, so expand it
4874 * to SIMD16. An alternative with longer message payload length but
4875 * shorter return payload would be to use the SIMD8 sampler message that
4876 * takes (header, u, v, r) as parameters instead of (header, u).
4878 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
4880 case FS_OPCODE_DDY_FINE
:
4881 /* The implementation of this virtual opcode may require emitting
4882 * compressed Align16 instructions, which are severely limited on some
4885 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
4886 * Region Restrictions):
4888 * "In Align16 access mode, SIMD16 is not allowed for DW operations
4889 * and SIMD8 is not allowed for DF operations."
4891 * In this context, "DW operations" means "operations acting on 32-bit
4892 * values", so it includes operations on floats.
4894 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
4895 * (Instruction Compression -> Rules and Restrictions):
4897 * "A compressed instruction must be in Align1 access mode. Align16
4898 * mode instructions cannot be compressed."
4900 * Similar text exists in the g45 PRM.
4902 * Empirically, compressed align16 instructions using odd register
4903 * numbers don't appear to work on Sandybridge either.
4905 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
4906 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
4907 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
4909 case SHADER_OPCODE_MULH
:
4910 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4911 * is 8-wide on Gen7+.
4913 return (devinfo
->gen
>= 7 ? 8 :
4914 get_fpu_lowered_simd_width(devinfo
, inst
));
4916 case FS_OPCODE_FB_WRITE_LOGICAL
:
4917 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4920 assert(devinfo
->gen
!= 6 ||
4921 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4922 inst
->exec_size
== 8);
4923 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4924 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4925 8 : MIN2(16, inst
->exec_size
));
4927 case SHADER_OPCODE_TEX_LOGICAL
:
4928 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4929 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4930 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4931 case SHADER_OPCODE_LOD_LOGICAL
:
4932 case SHADER_OPCODE_TG4_LOGICAL
:
4933 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4934 return MIN2(16, inst
->exec_size
);
4936 case SHADER_OPCODE_TXD_LOGICAL
:
4937 /* TXD is unsupported in SIMD16 mode. */
4940 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4941 /* gather4_po_c is unsupported in SIMD16 mode. */
4942 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4943 return (shadow_c
.file
!= BAD_FILE
? 8 : MIN2(16, inst
->exec_size
));
4945 case SHADER_OPCODE_TXL_LOGICAL
:
4946 case FS_OPCODE_TXB_LOGICAL
: {
4947 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4948 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4949 * mode because the message exceeds the maximum length of 11.
4951 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4952 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4954 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4957 return MIN2(16, inst
->exec_size
);
4959 case SHADER_OPCODE_TXF_LOGICAL
:
4960 case SHADER_OPCODE_TXS_LOGICAL
:
4961 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4962 * messages. Use SIMD16 instead.
4964 if (devinfo
->gen
== 4)
4967 return MIN2(16, inst
->exec_size
);
4969 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4970 /* This opcode can take up to 6 arguments which means that in some
4971 * circumstances it can end up with a message that is too long in SIMD16
4974 const unsigned coord_components
=
4975 inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4976 /* First three arguments are the sample index and the two arguments for
4979 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
4982 return MIN2(16, inst
->exec_size
);
4985 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4986 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4987 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4990 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4991 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4992 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4993 return MIN2(16, inst
->exec_size
);
4995 case SHADER_OPCODE_URB_READ_SIMD8
:
4996 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
4997 case SHADER_OPCODE_URB_WRITE_SIMD8
:
4998 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
4999 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
5000 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
5001 return MIN2(8, inst
->exec_size
);
5003 case SHADER_OPCODE_MOV_INDIRECT
:
5004 /* Prior to Broadwell, we only have 8 address subregisters */
5005 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
5006 2 * REG_SIZE
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
5009 case SHADER_OPCODE_LOAD_PAYLOAD
: {
5010 const unsigned reg_count
=
5011 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
5013 if (reg_count
> 2) {
5014 /* Only LOAD_PAYLOAD instructions with per-channel destination region
5015 * can be easily lowered (which excludes headers and heterogeneous
5018 assert(!inst
->header_size
);
5019 for (unsigned i
= 0; i
< inst
->sources
; i
++)
5020 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
5021 inst
->src
[i
].file
== BAD_FILE
);
5023 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
5025 return inst
->exec_size
;
5029 return inst
->exec_size
;
5034 * Return true if splitting out the group of channels of instruction \p inst
5035 * given by lbld.group() requires allocating a temporary for the i-th source
5036 * of the lowered instruction.
5039 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
5041 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
5042 (inst
->components_read(i
) == 1 &&
5043 lbld
.dispatch_width() <= inst
->exec_size
));
5047 * Extract the data that would be consumed by the channel group given by
5048 * lbld.group() from the i-th source region of instruction \p inst and return
5049 * it as result in packed form. If any copy instructions are required they
5050 * will be emitted before the given \p inst in \p block.
5053 emit_unzip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
,
5056 /* Specified channel group from the source region. */
5057 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group());
5059 if (needs_src_copy(lbld
, inst
, i
)) {
5060 /* Builder of the right width to perform the copy avoiding uninitialized
5061 * data if the lowered execution size is greater than the original
5062 * execution size of the instruction.
5064 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5065 inst
->exec_size
), 0);
5066 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
5068 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
5069 cbld
.at(block
, inst
)
5070 .MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
5074 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
5075 /* The source is invariant for all dispatch_width-wide groups of the
5078 return inst
->src
[i
];
5081 /* We can just point the lowered instruction at the right channel group
5082 * from the original region.
5089 * Insert data from a packed temporary into the channel group given by
5090 * lbld.group() of the destination region of instruction \p inst and return
5091 * the temporary as result. If any copy instructions are required they will
5092 * be emitted around the given \p inst in \p block.
5095 emit_zip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
)
5097 /* Builder of the right width to perform the copy avoiding uninitialized
5098 * data if the lowered execution size is greater than the original
5099 * execution size of the instruction.
5101 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5102 inst
->exec_size
), 0);
5104 /* Specified channel group from the destination region. */
5105 const fs_reg dst
= horiz_offset(inst
->dst
, lbld
.group());
5106 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
5107 inst
->dst
.component_size(inst
->exec_size
);
5108 const fs_reg tmp
= lbld
.vgrf(inst
->dst
.type
, dst_size
);
5110 if (inst
->predicate
) {
5111 /* Handle predication by copying the original contents of the
5112 * destination into the temporary before emitting the lowered
5115 for (unsigned k
= 0; k
< dst_size
; ++k
)
5116 cbld
.at(block
, inst
)
5117 .MOV(offset(tmp
, lbld
, k
), offset(dst
, inst
->exec_size
, k
));
5120 for (unsigned k
= 0; k
< dst_size
; ++k
)
5121 cbld
.at(block
, inst
->next
)
5122 .MOV(offset(dst
, inst
->exec_size
, k
), offset(tmp
, lbld
, k
));
5128 fs_visitor::lower_simd_width()
5130 bool progress
= false;
5132 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5133 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5135 if (lower_width
!= inst
->exec_size
) {
5136 /* Builder matching the original instruction. We may also need to
5137 * emit an instruction of width larger than the original, set the
5138 * execution size of the builder to the highest of both for now so
5139 * we're sure that both cases can be handled.
5141 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5142 const fs_builder ibld
= bld
.at(block
, inst
)
5143 .exec_all(inst
->force_writemask_all
)
5144 .group(max_width
, inst
->group
/ max_width
);
5146 /* Split the copies in chunks of the execution width of either the
5147 * original or the lowered instruction, whichever is lower.
5149 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5150 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
5151 inst
->dst
.component_size(inst
->exec_size
);
5153 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5155 for (unsigned i
= 0; i
< n
; i
++) {
5156 /* Emit a copy of the original instruction with the lowered width.
5157 * If the EOT flag was set throw it away except for the last
5158 * instruction to avoid killing the thread prematurely.
5160 fs_inst split_inst
= *inst
;
5161 split_inst
.exec_size
= lower_width
;
5162 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
5164 /* Select the correct channel enables for the i-th group, then
5165 * transform the sources and destination and emit the lowered
5168 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5170 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5171 split_inst
.src
[j
] = emit_unzip(lbld
, block
, inst
, j
);
5173 split_inst
.dst
= emit_zip(lbld
, block
, inst
);
5174 split_inst
.regs_written
=
5175 DIV_ROUND_UP(type_sz(inst
->dst
.type
) * dst_size
* lower_width
,
5178 lbld
.emit(split_inst
);
5181 inst
->remove(block
);
5187 invalidate_live_intervals();
5193 fs_visitor::dump_instructions()
5195 dump_instructions(NULL
);
5199 fs_visitor::dump_instructions(const char *name
)
5201 FILE *file
= stderr
;
5202 if (name
&& geteuid() != 0) {
5203 file
= fopen(name
, "w");
5209 calculate_register_pressure();
5210 int ip
= 0, max_pressure
= 0;
5211 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5212 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5213 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5214 dump_instruction(inst
, file
);
5217 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5220 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5221 fprintf(file
, "%4d: ", ip
++);
5222 dump_instruction(inst
, file
);
5226 if (file
!= stderr
) {
5232 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5234 dump_instruction(be_inst
, stderr
);
5238 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5240 fs_inst
*inst
= (fs_inst
*)be_inst
;
5242 if (inst
->predicate
) {
5243 fprintf(file
, "(%cf0.%d) ",
5244 inst
->predicate_inverse
? '-' : '+',
5248 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5250 fprintf(file
, ".sat");
5251 if (inst
->conditional_mod
) {
5252 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5253 if (!inst
->predicate
&&
5254 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5255 inst
->opcode
!= BRW_OPCODE_IF
&&
5256 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5257 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
5260 fprintf(file
, "(%d) ", inst
->exec_size
);
5263 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5266 switch (inst
->dst
.file
) {
5268 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
5269 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
5270 inst
->dst
.subreg_offset
)
5271 fprintf(file
, "+%d.%d",
5272 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
5275 fprintf(file
, "g%d", inst
->dst
.nr
);
5278 fprintf(file
, "m%d", inst
->dst
.nr
);
5281 fprintf(file
, "(null)");
5284 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
5287 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
5290 switch (inst
->dst
.nr
) {
5292 fprintf(file
, "null");
5294 case BRW_ARF_ADDRESS
:
5295 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
5297 case BRW_ARF_ACCUMULATOR
:
5298 fprintf(file
, "acc%d", inst
->dst
.subnr
);
5301 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5304 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5307 if (inst
->dst
.subnr
)
5308 fprintf(file
, "+%d", inst
->dst
.subnr
);
5311 unreachable("not reached");
5313 if (inst
->dst
.stride
!= 1)
5314 fprintf(file
, "<%u>", inst
->dst
.stride
);
5315 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
5317 for (int i
= 0; i
< inst
->sources
; i
++) {
5318 if (inst
->src
[i
].negate
)
5320 if (inst
->src
[i
].abs
)
5322 switch (inst
->src
[i
].file
) {
5324 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
5325 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
5326 inst
->src
[i
].subreg_offset
)
5327 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
5328 inst
->src
[i
].subreg_offset
);
5331 fprintf(file
, "g%d", inst
->src
[i
].nr
);
5334 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
5337 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
5340 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
5341 if (inst
->src
[i
].subreg_offset
) {
5342 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
5343 inst
->src
[i
].subreg_offset
);
5347 fprintf(file
, "(null)");
5350 switch (inst
->src
[i
].type
) {
5351 case BRW_REGISTER_TYPE_F
:
5352 fprintf(file
, "%-gf", inst
->src
[i
].f
);
5354 case BRW_REGISTER_TYPE_DF
:
5355 fprintf(file
, "%fdf", inst
->src
[i
].df
);
5357 case BRW_REGISTER_TYPE_W
:
5358 case BRW_REGISTER_TYPE_D
:
5359 fprintf(file
, "%dd", inst
->src
[i
].d
);
5361 case BRW_REGISTER_TYPE_UW
:
5362 case BRW_REGISTER_TYPE_UD
:
5363 fprintf(file
, "%uu", inst
->src
[i
].ud
);
5365 case BRW_REGISTER_TYPE_VF
:
5366 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
5367 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
5368 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
5369 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
5370 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5373 fprintf(file
, "???");
5378 switch (inst
->src
[i
].nr
) {
5380 fprintf(file
, "null");
5382 case BRW_ARF_ADDRESS
:
5383 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5385 case BRW_ARF_ACCUMULATOR
:
5386 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5389 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5392 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5395 if (inst
->src
[i
].subnr
)
5396 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
5399 if (inst
->src
[i
].abs
)
5402 if (inst
->src
[i
].file
!= IMM
) {
5404 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5405 unsigned hstride
= inst
->src
[i
].hstride
;
5406 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5408 stride
= inst
->src
[i
].stride
;
5411 fprintf(file
, "<%u>", stride
);
5413 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
5416 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5417 fprintf(file
, ", ");
5422 if (inst
->force_writemask_all
)
5423 fprintf(file
, "NoMask ");
5425 if (inst
->exec_size
!= dispatch_width
)
5426 fprintf(file
, "group%d ", inst
->group
);
5428 fprintf(file
, "\n");
5432 * Possibly returns an instruction that set up @param reg.
5434 * Sometimes we want to take the result of some expression/variable
5435 * dereference tree and rewrite the instruction generating the result
5436 * of the tree. When processing the tree, we know that the
5437 * instructions generated are all writing temporaries that are dead
5438 * outside of this tree. So, if we have some instructions that write
5439 * a temporary, we're free to point that temp write somewhere else.
5441 * Note that this doesn't guarantee that the instruction generated
5442 * only reg -- it might be the size=4 destination of a texture instruction.
5445 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5450 end
->is_partial_write() ||
5451 !reg
.equals(end
->dst
)) {
5459 fs_visitor::setup_fs_payload_gen6()
5461 assert(stage
== MESA_SHADER_FRAGMENT
);
5462 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5464 unsigned barycentric_interp_modes
=
5465 (stage
== MESA_SHADER_FRAGMENT
) ?
5466 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
5468 assert(devinfo
->gen
>= 6);
5470 /* R0-1: masks, pixel X/Y coordinates. */
5471 payload
.num_regs
= 2;
5472 /* R2: only for 32-pixel dispatch.*/
5474 /* R3-26: barycentric interpolation coordinates. These appear in the
5475 * same order that they appear in the brw_wm_barycentric_interp_mode
5476 * enum. Each set of coordinates occupies 2 registers if dispatch width
5477 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5478 * appear if they were enabled using the "Barycentric Interpolation
5479 * Mode" bits in WM_STATE.
5481 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
5482 if (barycentric_interp_modes
& (1 << i
)) {
5483 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5484 payload
.num_regs
+= 2;
5485 if (dispatch_width
== 16) {
5486 payload
.num_regs
+= 2;
5491 /* R27: interpolated depth if uses source depth */
5492 prog_data
->uses_src_depth
=
5493 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5494 if (prog_data
->uses_src_depth
) {
5495 payload
.source_depth_reg
= payload
.num_regs
;
5497 if (dispatch_width
== 16) {
5498 /* R28: interpolated depth if not SIMD8. */
5503 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5504 prog_data
->uses_src_w
=
5505 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5506 if (prog_data
->uses_src_w
) {
5507 payload
.source_w_reg
= payload
.num_regs
;
5509 if (dispatch_width
== 16) {
5510 /* R30: interpolated W if not SIMD8. */
5515 /* R31: MSAA position offsets. */
5516 if (prog_data
->persample_dispatch
&&
5517 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
)) {
5518 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
5520 * "MSDISPMODE_PERSAMPLE is required in order to select
5523 * So we can only really get sample positions if we are doing real
5524 * per-sample dispatch. If we need gl_SamplePosition and we don't have
5525 * persample dispatch, we hard-code it to 0.5.
5527 prog_data
->uses_pos_offset
= true;
5528 payload
.sample_pos_reg
= payload
.num_regs
;
5532 /* R32: MSAA input coverage mask */
5533 prog_data
->uses_sample_mask
=
5534 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5535 if (prog_data
->uses_sample_mask
) {
5536 assert(devinfo
->gen
>= 7);
5537 payload
.sample_mask_in_reg
= payload
.num_regs
;
5539 if (dispatch_width
== 16) {
5540 /* R33: input coverage mask if not SIMD8. */
5545 /* R34-: bary for 32-pixel. */
5546 /* R58-59: interp W for 32-pixel. */
5548 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5549 source_depth_to_render_target
= true;
5554 fs_visitor::setup_vs_payload()
5556 /* R0: thread header, R1: urb handles */
5557 payload
.num_regs
= 2;
5561 * We are building the local ID push constant data using the simplest possible
5562 * method. We simply push the local IDs directly as they should appear in the
5563 * registers for the uvec3 gl_LocalInvocationID variable.
5565 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
5566 * registers worth of push constant space.
5568 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
5569 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
5572 * FINISHME: There are a few easy optimizations to consider.
5574 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
5575 * no need for using push constant space for that dimension.
5577 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
5578 * easily use 16-bit words rather than 32-bit dwords in the push constant
5581 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
5582 * conveying the data, and thereby reduce push constant usage.
5586 fs_visitor::setup_gs_payload()
5588 assert(stage
== MESA_SHADER_GEOMETRY
);
5590 struct brw_gs_prog_data
*gs_prog_data
=
5591 (struct brw_gs_prog_data
*) prog_data
;
5592 struct brw_vue_prog_data
*vue_prog_data
=
5593 (struct brw_vue_prog_data
*) prog_data
;
5595 /* R0: thread header, R1: output URB handles */
5596 payload
.num_regs
= 2;
5598 if (gs_prog_data
->include_primitive_id
) {
5599 /* R2: Primitive ID 0..7 */
5603 /* Use a maximum of 24 registers for push-model inputs. */
5604 const unsigned max_push_components
= 24;
5606 /* If pushing our inputs would take too many registers, reduce the URB read
5607 * length (which is in HWords, or 8 registers), and resort to pulling.
5609 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5610 * have to multiply by VerticesIn to obtain the total storage requirement.
5612 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5613 max_push_components
) {
5614 gs_prog_data
->base
.include_vue_handles
= true;
5616 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5617 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5619 vue_prog_data
->urb_read_length
=
5620 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5625 fs_visitor::setup_cs_payload()
5627 assert(devinfo
->gen
>= 7);
5628 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
5630 payload
.num_regs
= 1;
5632 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
&&
5633 prog_data
->thread_local_id_index
< 0) {
5634 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
5635 payload
.local_invocation_id_reg
= payload
.num_regs
;
5636 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
5641 fs_visitor::calculate_register_pressure()
5643 invalidate_live_intervals();
5644 calculate_live_intervals();
5646 unsigned num_instructions
= 0;
5647 foreach_block(block
, cfg
)
5648 num_instructions
+= block
->instructions
.length();
5650 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5652 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5653 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5654 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5659 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
5661 * The needs_unlit_centroid_workaround ends up producing one of these per
5662 * channel of centroid input, so it's good to clean them up.
5664 * An assumption here is that nothing ever modifies the dispatched pixels
5665 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
5666 * dictates that anyway.
5669 fs_visitor::opt_drop_redundant_mov_to_flags()
5671 bool flag_mov_found
[2] = {false};
5672 bool progress
= false;
5674 /* Instructions removed by this pass can only be added if this were true */
5675 if (!devinfo
->needs_unlit_centroid_workaround
)
5678 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5679 if (inst
->is_control_flow()) {
5680 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
5681 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
5682 if (!flag_mov_found
[inst
->flag_subreg
]) {
5683 flag_mov_found
[inst
->flag_subreg
] = true;
5685 inst
->remove(block
);
5688 } else if (inst
->flags_written()) {
5689 flag_mov_found
[inst
->flag_subreg
] = false;
5697 fs_visitor::optimize()
5699 /* Start by validating the shader we currently have. */
5702 /* bld is the common builder object pointing at the end of the program we
5703 * used to translate it into i965 IR. For the optimization and lowering
5704 * passes coming next, any code added after the end of the program without
5705 * having explicitly called fs_builder::at() clearly points at a mistake.
5706 * Ideally optimization passes wouldn't be part of the visitor so they
5707 * wouldn't have access to bld at all, but they do, so just in case some
5708 * pass forgets to ask for a location explicitly set it to NULL here to
5709 * make it trip. The dispatch width is initialized to a bogus value to
5710 * make sure that optimizations set the execution controls explicitly to
5711 * match the code they are manipulating instead of relying on the defaults.
5713 bld
= fs_builder(this, 64);
5715 assign_constant_locations();
5716 lower_constant_loads();
5720 split_virtual_grfs();
5723 #define OPT(pass, args...) ({ \
5725 bool this_progress = pass(args); \
5727 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5728 char filename[64]; \
5729 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5730 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5732 backend_shader::dump_instructions(filename); \
5737 progress = progress || this_progress; \
5741 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5743 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5744 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5746 backend_shader::dump_instructions(filename
);
5749 bool progress
= false;
5753 OPT(opt_drop_redundant_mov_to_flags
);
5760 OPT(remove_duplicate_mrf_writes
);
5764 OPT(opt_copy_propagate
);
5765 OPT(opt_predicated_break
, this);
5766 OPT(opt_cmod_propagation
);
5767 OPT(dead_code_eliminate
);
5768 OPT(opt_peephole_sel
);
5769 OPT(dead_control_flow_eliminate
, this);
5770 OPT(opt_register_renaming
);
5771 OPT(opt_saturate_propagation
);
5772 OPT(register_coalesce
);
5773 OPT(compute_to_mrf
);
5774 OPT(eliminate_find_live_channel
);
5776 OPT(compact_virtual_grfs
);
5782 OPT(lower_simd_width
);
5784 /* After SIMD lowering just in case we had to unroll the EOT send. */
5785 OPT(opt_sampler_eot
);
5787 OPT(lower_logical_sends
);
5790 OPT(opt_copy_propagate
);
5791 /* Only run after logical send lowering because it's easier to implement
5792 * in terms of physical sends.
5794 if (OPT(opt_zero_samples
))
5795 OPT(opt_copy_propagate
);
5796 /* Run after logical send lowering to give it a chance to CSE the
5797 * LOAD_PAYLOAD instructions created to construct the payloads of
5798 * e.g. texturing messages in cases where it wasn't possible to CSE the
5799 * whole logical instruction.
5802 OPT(register_coalesce
);
5803 OPT(compute_to_mrf
);
5804 OPT(dead_code_eliminate
);
5805 OPT(remove_duplicate_mrf_writes
);
5806 OPT(opt_peephole_sel
);
5809 OPT(opt_redundant_discard_jumps
);
5811 if (OPT(lower_load_payload
)) {
5812 split_virtual_grfs();
5813 OPT(register_coalesce
);
5814 OPT(compute_to_mrf
);
5815 OPT(dead_code_eliminate
);
5818 if (OPT(lower_pack
)) {
5819 OPT(register_coalesce
);
5820 OPT(dead_code_eliminate
);
5823 if (OPT(lower_d2x
)) {
5824 OPT(opt_copy_propagate
);
5825 OPT(dead_code_eliminate
);
5828 OPT(opt_combine_constants
);
5829 OPT(lower_integer_multiplication
);
5831 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5832 OPT(opt_cmod_propagation
);
5834 OPT(opt_copy_propagate
);
5835 OPT(dead_code_eliminate
);
5838 lower_uniform_pull_constant_loads();
5844 * Three source instruction must have a GRF/MRF destination register.
5845 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5848 fs_visitor::fixup_3src_null_dest()
5850 bool progress
= false;
5852 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5853 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
5854 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5861 invalidate_live_intervals();
5865 fs_visitor::allocate_registers(bool allow_spilling
)
5867 bool allocated_without_spills
;
5869 static const enum instruction_scheduler_mode pre_modes
[] = {
5871 SCHEDULE_PRE_NON_LIFO
,
5875 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
5877 /* Try each scheduling heuristic to see if it can successfully register
5878 * allocate without spilling. They should be ordered by decreasing
5879 * performance but increasing likelihood of allocating.
5881 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5882 schedule_instructions(pre_modes
[i
]);
5885 assign_regs_trivial();
5886 allocated_without_spills
= true;
5888 allocated_without_spills
= assign_regs(false, spill_all
);
5890 if (allocated_without_spills
)
5894 if (!allocated_without_spills
) {
5895 /* We assume that any spilling is worse than just dropping back to
5896 * SIMD8. There's probably actually some intermediate point where
5897 * SIMD16 with a couple of spills is still better.
5899 if (dispatch_width
> min_dispatch_width
) {
5900 fail("Failure to register allocate. Reduce number of "
5901 "live scalar values to avoid this.");
5903 compiler
->shader_perf_log(log_data
,
5904 "%s shader triggered register spilling. "
5905 "Try reducing the number of live scalar "
5906 "values to improve performance.\n",
5910 /* Since we're out of heuristics, just go spill registers until we
5911 * get an allocation.
5913 while (!assign_regs(true, spill_all
)) {
5919 assert(last_scratch
== 0 || allow_spilling
);
5921 /* This must come after all optimization and register allocation, since
5922 * it inserts dead code that happens to have side effects, and it does
5923 * so based on the actual physical registers in use.
5925 insert_gen4_send_dependency_workarounds();
5930 schedule_instructions(SCHEDULE_POST
);
5932 if (last_scratch
> 0)
5933 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5937 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5939 assert(stage
== MESA_SHADER_VERTEX
);
5943 if (shader_time_index
>= 0)
5944 emit_shader_time_begin();
5951 compute_clip_distance(clip_planes
);
5955 if (shader_time_index
>= 0)
5956 emit_shader_time_end();
5962 assign_curb_setup();
5963 assign_vs_urb_setup();
5965 fixup_3src_null_dest();
5966 allocate_registers(true);
5972 fs_visitor::run_tcs_single_patch()
5974 assert(stage
== MESA_SHADER_TESS_CTRL
);
5976 struct brw_tcs_prog_data
*tcs_prog_data
=
5977 (struct brw_tcs_prog_data
*) prog_data
;
5979 /* r1-r4 contain the ICP handles. */
5980 payload
.num_regs
= 5;
5982 if (shader_time_index
>= 0)
5983 emit_shader_time_begin();
5985 /* Initialize gl_InvocationID */
5986 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
5987 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5988 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
5989 bld
.MOV(channels_ud
, channels_uw
);
5991 if (tcs_prog_data
->instances
== 1) {
5992 invocation_id
= channels_ud
;
5994 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5996 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
5997 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5998 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5999 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
6000 brw_imm_ud(INTEL_MASK(23, 17)));
6001 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
6003 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
6006 /* Fix the disptach mask */
6007 if (nir
->info
.tcs
.vertices_out
% 8) {
6008 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
6009 brw_imm_ud(nir
->info
.tcs
.vertices_out
), BRW_CONDITIONAL_L
);
6010 bld
.IF(BRW_PREDICATE_NORMAL
);
6015 if (nir
->info
.tcs
.vertices_out
% 8) {
6016 bld
.emit(BRW_OPCODE_ENDIF
);
6019 /* Emit EOT write; set TR DS Cache bit */
6021 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
6022 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
6023 fs_reg(brw_imm_ud(0)),
6025 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
6026 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
6028 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
6029 bld
.null_reg_ud(), payload
);
6031 inst
->base_mrf
= -1;
6034 if (shader_time_index
>= 0)
6035 emit_shader_time_end();
6044 assign_curb_setup();
6045 assign_tcs_single_patch_urb_setup();
6047 fixup_3src_null_dest();
6048 allocate_registers(true);
6054 fs_visitor::run_tes()
6056 assert(stage
== MESA_SHADER_TESS_EVAL
);
6058 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6059 payload
.num_regs
= 5;
6061 if (shader_time_index
>= 0)
6062 emit_shader_time_begin();
6071 if (shader_time_index
>= 0)
6072 emit_shader_time_end();
6078 assign_curb_setup();
6079 assign_tes_urb_setup();
6081 fixup_3src_null_dest();
6082 allocate_registers(true);
6088 fs_visitor::run_gs()
6090 assert(stage
== MESA_SHADER_GEOMETRY
);
6094 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6096 if (gs_compile
->control_data_header_size_bits
> 0) {
6097 /* Create a VGRF to store accumulated control data bits. */
6098 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6100 /* If we're outputting more than 32 control data bits, then EmitVertex()
6101 * will set control_data_bits to 0 after emitting the first vertex.
6102 * Otherwise, we need to initialize it to 0 here.
6104 if (gs_compile
->control_data_header_size_bits
<= 32) {
6105 const fs_builder abld
= bld
.annotate("initialize control data bits");
6106 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6110 if (shader_time_index
>= 0)
6111 emit_shader_time_begin();
6115 emit_gs_thread_end();
6117 if (shader_time_index
>= 0)
6118 emit_shader_time_end();
6127 assign_curb_setup();
6128 assign_gs_urb_setup();
6130 fixup_3src_null_dest();
6131 allocate_registers(true);
6137 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6139 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
6140 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6142 assert(stage
== MESA_SHADER_FRAGMENT
);
6144 if (devinfo
->gen
>= 6)
6145 setup_fs_payload_gen6();
6147 setup_fs_payload_gen4();
6151 } else if (do_rep_send
) {
6152 assert(dispatch_width
== 16);
6153 emit_repclear_shader();
6155 if (shader_time_index
>= 0)
6156 emit_shader_time_begin();
6158 calculate_urb_setup();
6159 if (nir
->info
.inputs_read
> 0) {
6160 if (devinfo
->gen
< 6)
6161 emit_interpolation_setup_gen4();
6163 emit_interpolation_setup_gen6();
6166 /* We handle discards by keeping track of the still-live pixels in f0.1.
6167 * Initialize it with the dispatched pixels.
6169 if (wm_prog_data
->uses_kill
) {
6170 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
6171 discard_init
->flag_subreg
= 1;
6174 /* Generate FS IR for main(). (the visitor only descends into
6175 * functions called "main").
6182 if (wm_prog_data
->uses_kill
)
6183 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6185 if (wm_key
->alpha_test_func
)
6190 if (shader_time_index
>= 0)
6191 emit_shader_time_end();
6197 assign_curb_setup();
6200 fixup_3src_null_dest();
6201 allocate_registers(allow_spilling
);
6211 fs_visitor::run_cs()
6213 assert(stage
== MESA_SHADER_COMPUTE
);
6217 if (shader_time_index
>= 0)
6218 emit_shader_time_begin();
6220 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6221 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6222 const fs_builder abld
= bld
.exec_all().group(1, 0);
6223 abld
.MOV(retype(suboffset(brw_sr0_reg(), 1), BRW_REGISTER_TYPE_UW
),
6224 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6232 emit_cs_terminate();
6234 if (shader_time_index
>= 0)
6235 emit_shader_time_end();
6241 assign_curb_setup();
6243 fixup_3src_null_dest();
6244 allocate_registers(true);
6253 * Return a bitfield where bit n is set if barycentric interpolation mode n
6254 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
6257 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
6258 bool shade_model_flat
,
6259 bool persample_shading
,
6260 const nir_shader
*shader
)
6262 unsigned barycentric_interp_modes
= 0;
6264 nir_foreach_variable(var
, &shader
->inputs
) {
6265 enum glsl_interp_qualifier interp_qualifier
=
6266 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
6267 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
6268 bool is_sample
= var
->data
.sample
|| persample_shading
;
6269 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
6270 (var
->data
.location
== VARYING_SLOT_COL1
);
6272 /* Ignore WPOS and FACE, because they don't require interpolation. */
6273 if (var
->data
.location
== VARYING_SLOT_POS
||
6274 var
->data
.location
== VARYING_SLOT_FACE
)
6277 /* Determine the set (or sets) of barycentric coordinates needed to
6278 * interpolate this variable. Note that when
6279 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
6280 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
6281 * for lit pixels, so we need both sets of barycentric coordinates.
6283 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
6285 barycentric_interp_modes
|=
6286 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
6287 } else if (is_sample
) {
6288 barycentric_interp_modes
|=
6289 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
6291 if ((!is_centroid
&& !is_sample
) ||
6292 devinfo
->needs_unlit_centroid_workaround
) {
6293 barycentric_interp_modes
|=
6294 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
6296 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
6297 (!(shade_model_flat
&& is_gl_Color
) &&
6298 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
6300 barycentric_interp_modes
|=
6301 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
6302 } else if (is_sample
) {
6303 barycentric_interp_modes
|=
6304 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
6306 if ((!is_centroid
&& !is_sample
) ||
6307 devinfo
->needs_unlit_centroid_workaround
) {
6308 barycentric_interp_modes
|=
6309 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
6314 return barycentric_interp_modes
;
6318 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
6319 bool shade_model_flat
, const nir_shader
*shader
)
6321 prog_data
->flat_inputs
= 0;
6323 nir_foreach_variable(var
, &shader
->inputs
) {
6324 enum glsl_interp_qualifier interp_qualifier
=
6325 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
6326 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
6327 (var
->data
.location
== VARYING_SLOT_COL1
);
6329 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
6331 if (input_index
< 0)
6335 if (interp_qualifier
== INTERP_QUALIFIER_FLAT
||
6336 (shade_model_flat
&& is_gl_Color
&&
6337 interp_qualifier
== INTERP_QUALIFIER_NONE
))
6338 prog_data
->flat_inputs
|= (1 << input_index
);
6343 computed_depth_mode(const nir_shader
*shader
)
6345 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6346 switch (shader
->info
.fs
.depth_layout
) {
6347 case FRAG_DEPTH_LAYOUT_NONE
:
6348 case FRAG_DEPTH_LAYOUT_ANY
:
6349 return BRW_PSCDEPTH_ON
;
6350 case FRAG_DEPTH_LAYOUT_GREATER
:
6351 return BRW_PSCDEPTH_ON_GE
;
6352 case FRAG_DEPTH_LAYOUT_LESS
:
6353 return BRW_PSCDEPTH_ON_LE
;
6354 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
6355 return BRW_PSCDEPTH_OFF
;
6358 return BRW_PSCDEPTH_OFF
;
6362 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
6364 const struct brw_wm_prog_key
*key
,
6365 struct brw_wm_prog_data
*prog_data
,
6366 const nir_shader
*src_shader
,
6367 struct gl_program
*prog
,
6368 int shader_time_index8
, int shader_time_index16
,
6369 bool allow_spilling
,
6371 unsigned *final_assembly_size
,
6374 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6375 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6377 brw_nir_lower_fs_inputs(shader
);
6378 brw_nir_lower_fs_outputs(shader
);
6379 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6381 /* key->alpha_test_func means simulating alpha testing via discards,
6382 * so the shader definitely kills pixels.
6384 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
6385 prog_data
->uses_omask
= key
->multisample_fbo
&&
6386 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
6387 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
6388 prog_data
->computed_stencil
=
6389 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
6391 prog_data
->persample_dispatch
=
6392 key
->multisample_fbo
&&
6393 (key
->persample_interp
||
6394 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
6395 SYSTEM_BIT_SAMPLE_POS
)) ||
6396 shader
->info
.fs
.uses_sample_qualifier
);
6398 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
6400 prog_data
->barycentric_interp_modes
=
6401 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
6403 key
->persample_interp
,
6406 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
;
6407 uint8_t simd8_grf_start
= 0, simd16_grf_start
= 0;
6408 unsigned simd8_grf_used
= 0, simd16_grf_used
= 0;
6410 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
6411 &prog_data
->base
, prog
, shader
, 8,
6412 shader_time_index8
);
6413 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
6415 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
6418 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
6420 simd8_grf_start
= v8
.payload
.num_regs
;
6421 simd8_grf_used
= v8
.grf_used
;
6424 if (v8
.max_dispatch_width
>= 16 &&
6425 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
6426 /* Try a SIMD16 compile */
6427 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
6428 &prog_data
->base
, prog
, shader
, 16,
6429 shader_time_index16
);
6430 v16
.import_uniforms(&v8
);
6431 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
6432 compiler
->shader_perf_log(log_data
,
6433 "SIMD16 shader failed to compile: %s",
6436 simd16_cfg
= v16
.cfg
;
6437 simd16_grf_start
= v16
.payload
.num_regs
;
6438 simd16_grf_used
= v16
.grf_used
;
6442 /* When the caller requests a repclear shader, they want SIMD16-only */
6446 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
6447 * at the top to select the shader. We've never implemented that.
6448 * Instead, we just give them exactly one shader and we pick the widest one
6451 if (compiler
->devinfo
->gen
< 5 && simd16_cfg
)
6454 if (prog_data
->persample_dispatch
) {
6455 /* Starting with SandyBridge (where we first get MSAA), the different
6456 * pixel dispatch combinations are grouped into classifications A
6457 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
6458 * generations, the only configurations supporting persample dispatch
6459 * are are this in which only one dispatch width is enabled.
6461 * If computed depth is enabled, SNB only allows SIMD8 while IVB+
6462 * allow SIMD8 or SIMD16 so we choose SIMD16 if available.
6464 if (compiler
->devinfo
->gen
== 6 &&
6465 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
) {
6467 } else if (simd16_cfg
) {
6472 /* We have to compute the flat inputs after the visitor is finished running
6473 * because it relies on prog_data->urb_setup which is computed in
6474 * fs_visitor::calculate_urb_setup().
6476 brw_compute_flat_inputs(prog_data
, key
->flat_shade
, shader
);
6478 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
6479 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6480 MESA_SHADER_FRAGMENT
);
6482 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
6483 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
6484 shader
->info
.label
? shader
->info
.label
:
6486 shader
->info
.name
));
6490 prog_data
->dispatch_8
= true;
6491 g
.generate_code(simd8_cfg
, 8);
6492 prog_data
->base
.dispatch_grf_start_reg
= simd8_grf_start
;
6493 prog_data
->reg_blocks_0
= brw_register_blocks(simd8_grf_used
);
6496 prog_data
->dispatch_16
= true;
6497 prog_data
->prog_offset_2
= g
.generate_code(simd16_cfg
, 16);
6498 prog_data
->dispatch_grf_start_reg_2
= simd16_grf_start
;
6499 prog_data
->reg_blocks_2
= brw_register_blocks(simd16_grf_used
);
6501 } else if (simd16_cfg
) {
6502 prog_data
->dispatch_16
= true;
6503 g
.generate_code(simd16_cfg
, 16);
6504 prog_data
->base
.dispatch_grf_start_reg
= simd16_grf_start
;
6505 prog_data
->reg_blocks_0
= brw_register_blocks(simd16_grf_used
);
6508 return g
.get_assembly(final_assembly_size
);
6512 fs_visitor::emit_cs_local_invocation_id_setup()
6514 assert(stage
== MESA_SHADER_COMPUTE
);
6516 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6518 struct brw_reg src
=
6519 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
6520 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
6522 src
.nr
+= dispatch_width
/ 8;
6523 bld
.MOV(offset(*reg
, bld
, 1), src
);
6524 src
.nr
+= dispatch_width
/ 8;
6525 bld
.MOV(offset(*reg
, bld
, 2), src
);
6531 fs_visitor::emit_cs_work_group_id_setup()
6533 assert(stage
== MESA_SHADER_COMPUTE
);
6535 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6537 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
6538 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
6539 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
6541 bld
.MOV(*reg
, r0_1
);
6542 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
6543 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
6549 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
6551 const struct brw_cs_prog_key
*key
,
6552 struct brw_cs_prog_data
*prog_data
,
6553 const nir_shader
*src_shader
,
6554 int shader_time_index
,
6555 unsigned *final_assembly_size
,
6558 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6559 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6561 brw_nir_lower_cs_shared(shader
);
6562 prog_data
->base
.total_shared
+= shader
->num_shared
;
6564 /* The driver isn't yet ready to support thread_local_id_index, so we force
6565 * it to disabled for now.
6567 prog_data
->thread_local_id_index
= -1;
6569 /* Now that we cloned the nir_shader, we can update num_uniforms based on
6570 * the thread_local_id_index.
6572 if (prog_data
->thread_local_id_index
>= 0) {
6573 shader
->num_uniforms
=
6574 MAX2(shader
->num_uniforms
,
6575 (unsigned)4 * (prog_data
->thread_local_id_index
+ 1));
6578 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6580 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
6581 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
6582 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
6583 unsigned local_workgroup_size
=
6584 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
6585 shader
->info
.cs
.local_size
[2];
6587 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
6588 unsigned simd_required
= DIV_ROUND_UP(local_workgroup_size
, max_cs_threads
);
6591 const char *fail_msg
= NULL
;
6593 /* Now the main event: Visit the shader IR and generate our CS IR for it.
6595 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6596 NULL
, /* Never used in core profile */
6597 shader
, 8, shader_time_index
);
6598 if (simd_required
<= 8) {
6600 fail_msg
= v8
.fail_msg
;
6603 prog_data
->simd_size
= 8;
6604 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
6608 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6609 NULL
, /* Never used in core profile */
6610 shader
, 16, shader_time_index
);
6611 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
6612 !fail_msg
&& v8
.max_dispatch_width
>= 16 &&
6613 simd_required
<= 16) {
6614 /* Try a SIMD16 compile */
6615 if (simd_required
<= 8)
6616 v16
.import_uniforms(&v8
);
6617 if (!v16
.run_cs()) {
6618 compiler
->shader_perf_log(log_data
,
6619 "SIMD16 shader failed to compile: %s",
6623 "Couldn't generate SIMD16 program and not "
6624 "enough threads for SIMD8";
6628 prog_data
->simd_size
= 16;
6629 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
6633 fs_visitor
v32(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6634 NULL
, /* Never used in core profile */
6635 shader
, 32, shader_time_index
);
6636 if (!fail_msg
&& v8
.max_dispatch_width
>= 32 &&
6637 (simd_required
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
6638 /* Try a SIMD32 compile */
6639 if (simd_required
<= 8)
6640 v32
.import_uniforms(&v8
);
6641 else if (simd_required
<= 16)
6642 v32
.import_uniforms(&v16
);
6644 if (!v32
.run_cs()) {
6645 compiler
->shader_perf_log(log_data
,
6646 "SIMD32 shader failed to compile: %s",
6650 "Couldn't generate SIMD32 program and not "
6651 "enough threads for SIMD16";
6655 prog_data
->simd_size
= 32;
6659 if (unlikely(cfg
== NULL
)) {
6662 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
6667 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
6668 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6669 MESA_SHADER_COMPUTE
);
6670 if (INTEL_DEBUG
& DEBUG_CS
) {
6671 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
6672 shader
->info
.label
? shader
->info
.label
:
6675 g
.enable_debug(name
);
6678 g
.generate_code(cfg
, prog_data
->simd_size
);
6680 return g
.get_assembly(final_assembly_size
);
6684 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*prog_data
,
6685 void *buffer
, uint32_t threads
, uint32_t stride
)
6687 if (prog_data
->local_invocation_id_regs
== 0)
6690 /* 'stride' should be an integer number of registers, that is, a multiple
6693 assert(stride
% 32 == 0);
6695 unsigned x
= 0, y
= 0, z
= 0;
6696 for (unsigned t
= 0; t
< threads
; t
++) {
6697 uint32_t *param
= (uint32_t *) buffer
+ stride
* t
/ 4;
6699 for (unsigned i
= 0; i
< prog_data
->simd_size
; i
++) {
6700 param
[0 * prog_data
->simd_size
+ i
] = x
;
6701 param
[1 * prog_data
->simd_size
+ i
] = y
;
6702 param
[2 * prog_data
->simd_size
+ i
] = z
;
6705 if (x
== prog_data
->local_size
[0]) {
6708 if (y
== prog_data
->local_size
[1]) {
6711 if (z
== prog_data
->local_size
[2])