2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "brw_vec4_gs_visitor.h"
48 #include "brw_dead_control_flow.h"
49 #include "main/uniforms.h"
50 #include "brw_fs_live_variables.h"
51 #include "glsl/nir/glsl_types.h"
52 #include "program/sampler.h"
57 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
58 const fs_reg
*src
, unsigned sources
)
60 memset(this, 0, sizeof(*this));
62 this->src
= new fs_reg
[MAX2(sources
, 3)];
63 for (unsigned i
= 0; i
< sources
; i
++)
64 this->src
[i
] = src
[i
];
66 this->opcode
= opcode
;
68 this->sources
= sources
;
69 this->exec_size
= exec_size
;
71 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
73 assert(this->exec_size
!= 0);
75 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
77 /* This will be the case for almost all instructions. */
84 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
88 this->regs_written
= 0;
92 unreachable("Invalid destination register file");
95 this->writes_accumulator
= false;
100 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
103 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
105 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
108 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
110 init(opcode
, exec_size
, dst
, NULL
, 0);
113 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
116 const fs_reg src
[1] = { src0
};
117 init(opcode
, exec_size
, dst
, src
, 1);
120 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
121 const fs_reg
&src0
, const fs_reg
&src1
)
123 const fs_reg src
[2] = { src0
, src1
};
124 init(opcode
, exec_size
, dst
, src
, 2);
127 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
128 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
130 const fs_reg src
[3] = { src0
, src1
, src2
};
131 init(opcode
, exec_size
, dst
, src
, 3);
134 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
135 const fs_reg src
[], unsigned sources
)
137 init(opcode
, exec_width
, dst
, src
, sources
);
140 fs_inst::fs_inst(const fs_inst
&that
)
142 memcpy(this, &that
, sizeof(that
));
144 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
146 for (unsigned i
= 0; i
< that
.sources
; i
++)
147 this->src
[i
] = that
.src
[i
];
156 fs_inst::resize_sources(uint8_t num_sources
)
158 if (this->sources
!= num_sources
) {
159 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
161 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
162 src
[i
] = this->src
[i
];
166 this->sources
= num_sources
;
171 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
173 const fs_reg
&surf_index
,
174 const fs_reg
&varying_offset
,
175 uint32_t const_offset
)
177 /* We have our constant surface use a pitch of 4 bytes, so our index can
178 * be any component of a vector, and then we load 4 contiguous
179 * components starting from that.
181 * We break down the const_offset to a portion added to the variable
182 * offset and a portion done using reg_offset, which means that if you
183 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
184 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
185 * CSE can later notice that those loads are all the same and eliminate
186 * the redundant ones.
188 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
189 bld
.ADD(vec4_offset
, varying_offset
, fs_reg(const_offset
& ~3));
192 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
193 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
194 * u, v, r) as parameters, or we can just use the SIMD16 message
195 * consisting of (header, u). We choose the second, at the cost of a
196 * longer return length.
202 if (devinfo
->gen
>= 7)
203 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
205 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
207 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
208 fs_reg vec4_result
= fs_reg(VGRF
, alloc
.allocate(regs_written
), dst
.type
);
209 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
210 inst
->regs_written
= regs_written
;
212 if (devinfo
->gen
< 7) {
213 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
);
214 inst
->header_size
= 1;
215 if (devinfo
->gen
== 4)
218 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
221 bld
.MOV(dst
, offset(vec4_result
, bld
, (const_offset
& 3) * scale
));
225 * A helper for MOV generation for fixing up broken hardware SEND dependency
229 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
231 /* The caller always wants uncompressed to emit the minimal extra
232 * dependencies, and to avoid having to deal with aligning its regs to 2.
234 const fs_builder ubld
= bld
.annotate("send dependency resolve")
237 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
241 fs_inst::equals(fs_inst
*inst
) const
243 return (opcode
== inst
->opcode
&&
244 dst
.equals(inst
->dst
) &&
245 src
[0].equals(inst
->src
[0]) &&
246 src
[1].equals(inst
->src
[1]) &&
247 src
[2].equals(inst
->src
[2]) &&
248 saturate
== inst
->saturate
&&
249 predicate
== inst
->predicate
&&
250 conditional_mod
== inst
->conditional_mod
&&
251 mlen
== inst
->mlen
&&
252 base_mrf
== inst
->base_mrf
&&
253 target
== inst
->target
&&
255 header_size
== inst
->header_size
&&
256 shadow_compare
== inst
->shadow_compare
&&
257 exec_size
== inst
->exec_size
&&
258 offset
== inst
->offset
);
262 fs_inst::overwrites_reg(const fs_reg
®
) const
264 return reg
.in_range(dst
, regs_written
);
268 fs_inst::is_send_from_grf() const
271 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
272 case SHADER_OPCODE_SHADER_TIME_ADD
:
273 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
274 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
275 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
276 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
277 case SHADER_OPCODE_UNTYPED_ATOMIC
:
278 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
279 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
280 case SHADER_OPCODE_TYPED_ATOMIC
:
281 case SHADER_OPCODE_TYPED_SURFACE_READ
:
282 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
283 case SHADER_OPCODE_URB_WRITE_SIMD8
:
284 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
285 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
286 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
287 case SHADER_OPCODE_URB_READ_SIMD8
:
288 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
290 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
291 return src
[1].file
== VGRF
;
292 case FS_OPCODE_FB_WRITE
:
293 return src
[0].file
== VGRF
;
296 return src
[0].file
== VGRF
;
303 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
305 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
308 fs_reg reg
= this->src
[0];
309 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
312 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
315 for (int i
= 0; i
< this->sources
; i
++) {
316 reg
.type
= this->src
[i
].type
;
317 if (!this->src
[i
].equals(reg
))
320 if (i
< this->header_size
) {
323 reg
.reg_offset
+= this->exec_size
/ 8;
331 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
333 if (devinfo
->gen
== 6 && is_math())
336 if (is_send_from_grf())
339 if (!backend_instruction::can_do_source_mods())
346 fs_inst::can_change_types() const
348 return dst
.type
== src
[0].type
&&
349 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
350 (opcode
== BRW_OPCODE_MOV
||
351 (opcode
== BRW_OPCODE_SEL
&&
352 dst
.type
== src
[1].type
&&
353 predicate
!= BRW_PREDICATE_NONE
&&
354 !src
[1].abs
&& !src
[1].negate
));
358 fs_inst::has_side_effects() const
360 return this->eot
|| backend_instruction::has_side_effects();
366 memset(this, 0, sizeof(*this));
370 /** Generic unset register constructor. */
374 this->file
= BAD_FILE
;
377 /** Immediate value constructor. */
378 fs_reg::fs_reg(float f
)
382 this->type
= BRW_REGISTER_TYPE_F
;
387 /** Immediate value constructor. */
388 fs_reg::fs_reg(int32_t i
)
392 this->type
= BRW_REGISTER_TYPE_D
;
397 /** Immediate value constructor. */
398 fs_reg::fs_reg(uint32_t u
)
402 this->type
= BRW_REGISTER_TYPE_UD
;
407 /** Vector float immediate value constructor. */
408 fs_reg::fs_reg(uint8_t vf
[4])
412 this->type
= BRW_REGISTER_TYPE_VF
;
413 memcpy(&this->ud
, vf
, sizeof(unsigned));
416 /** Vector float immediate value constructor. */
417 fs_reg::fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
421 this->type
= BRW_REGISTER_TYPE_VF
;
422 this->ud
= (vf0
<< 0) | (vf1
<< 8) | (vf2
<< 16) | (vf3
<< 24);
425 fs_reg::fs_reg(struct brw_reg reg
) :
428 this->reg_offset
= 0;
429 this->subreg_offset
= 0;
430 this->reladdr
= NULL
;
432 if (this->file
== IMM
&&
433 (this->type
!= BRW_REGISTER_TYPE_V
&&
434 this->type
!= BRW_REGISTER_TYPE_UV
&&
435 this->type
!= BRW_REGISTER_TYPE_VF
)) {
441 fs_reg::equals(const fs_reg
&r
) const
443 return (memcmp((brw_reg
*)this, (brw_reg
*)&r
, sizeof(brw_reg
)) == 0 &&
444 reg_offset
== r
.reg_offset
&&
445 subreg_offset
== r
.subreg_offset
&&
446 !reladdr
&& !r
.reladdr
&&
451 fs_reg::set_smear(unsigned subreg
)
453 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
454 subreg_offset
= subreg
* type_sz(type
);
460 fs_reg::is_contiguous() const
466 fs_reg::component_size(unsigned width
) const
468 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
471 return MAX2(width
* stride
, 1) * type_sz(type
);
475 type_size_scalar(const struct glsl_type
*type
)
477 unsigned int size
, i
;
479 switch (type
->base_type
) {
482 case GLSL_TYPE_FLOAT
:
484 return type
->components();
485 case GLSL_TYPE_ARRAY
:
486 return type_size_scalar(type
->fields
.array
) * type
->length
;
487 case GLSL_TYPE_STRUCT
:
489 for (i
= 0; i
< type
->length
; i
++) {
490 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
493 case GLSL_TYPE_SAMPLER
:
494 /* Samplers take up no register space, since they're baked in at
498 case GLSL_TYPE_ATOMIC_UINT
:
500 case GLSL_TYPE_SUBROUTINE
:
502 case GLSL_TYPE_IMAGE
:
503 return BRW_IMAGE_PARAM_SIZE
;
505 case GLSL_TYPE_ERROR
:
506 case GLSL_TYPE_INTERFACE
:
507 case GLSL_TYPE_DOUBLE
:
508 unreachable("not reached");
515 * Returns the number of scalar components needed to store type, assuming
516 * that vectors are padded out to vec4.
518 * This has the packing rules of type_size_vec4(), but counts components
519 * similar to type_size_scalar().
522 type_size_vec4_times_4(const struct glsl_type
*type
)
524 return 4 * type_size_vec4(type
);
528 * Create a MOV to read the timestamp register.
530 * The caller is responsible for emitting the MOV. The return value is
531 * the destination of the MOV, with extra parameters set.
534 fs_visitor::get_timestamp(const fs_builder
&bld
)
536 assert(devinfo
->gen
>= 7);
538 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
541 BRW_REGISTER_TYPE_UD
));
543 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
545 /* We want to read the 3 fields we care about even if it's not enabled in
548 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
554 fs_visitor::emit_shader_time_begin()
556 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
558 /* We want only the low 32 bits of the timestamp. Since it's running
559 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
560 * which is plenty of time for our purposes. It is identical across the
561 * EUs, but since it's tracking GPU core speed it will increment at a
562 * varying rate as render P-states change.
564 shader_start_time
.set_smear(0);
568 fs_visitor::emit_shader_time_end()
570 /* Insert our code just before the final SEND with EOT. */
571 exec_node
*end
= this->instructions
.get_tail();
572 assert(end
&& ((fs_inst
*) end
)->eot
);
573 const fs_builder ibld
= bld
.annotate("shader time end")
574 .exec_all().at(NULL
, end
);
576 fs_reg shader_end_time
= get_timestamp(ibld
);
578 /* We only use the low 32 bits of the timestamp - see
579 * emit_shader_time_begin()).
581 * We could also check if render P-states have changed (or anything
582 * else that might disrupt timing) by setting smear to 2 and checking if
583 * that field is != 0.
585 shader_end_time
.set_smear(0);
587 /* Check that there weren't any timestamp reset events (assuming these
588 * were the only two timestamp reads that happened).
590 fs_reg reset
= shader_end_time
;
592 set_condmod(BRW_CONDITIONAL_Z
,
593 ibld
.AND(ibld
.null_reg_ud(), reset
, fs_reg(1u)));
594 ibld
.IF(BRW_PREDICATE_NORMAL
);
596 fs_reg start
= shader_start_time
;
598 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
601 const fs_builder cbld
= ibld
.group(1, 0);
602 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
604 /* If there were no instructions between the two timestamp gets, the diff
605 * is 2 cycles. Remove that overhead, so I can forget about that when
606 * trying to determine the time taken for single instructions.
608 cbld
.ADD(diff
, diff
, fs_reg(-2u));
609 SHADER_TIME_ADD(cbld
, 0, diff
);
610 SHADER_TIME_ADD(cbld
, 1, fs_reg(1u));
611 ibld
.emit(BRW_OPCODE_ELSE
);
612 SHADER_TIME_ADD(cbld
, 2, fs_reg(1u));
613 ibld
.emit(BRW_OPCODE_ENDIF
);
617 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
618 int shader_time_subindex
,
621 int index
= shader_time_index
* 3 + shader_time_subindex
;
622 fs_reg offset
= fs_reg(index
* SHADER_TIME_STRIDE
);
625 if (dispatch_width
== 8)
626 payload
= vgrf(glsl_type::uvec2_type
);
628 payload
= vgrf(glsl_type::uint_type
);
630 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
634 fs_visitor::vfail(const char *format
, va_list va
)
643 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
644 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
646 this->fail_msg
= msg
;
649 fprintf(stderr
, "%s", msg
);
654 fs_visitor::fail(const char *format
, ...)
658 va_start(va
, format
);
664 * Mark this program as impossible to compile in SIMD16 mode.
666 * During the SIMD8 compile (which happens first), we can detect and flag
667 * things that are unsupported in SIMD16 mode, so the compiler can skip
668 * the SIMD16 compile altogether.
670 * During a SIMD16 compile (if one happens anyway), this just calls fail().
673 fs_visitor::no16(const char *msg
)
675 if (dispatch_width
== 16) {
678 simd16_unsupported
= true;
680 compiler
->shader_perf_log(log_data
,
681 "SIMD16 shader failed to compile: %s", msg
);
686 * Returns true if the instruction has a flag that means it won't
687 * update an entire destination register.
689 * For example, dead code elimination and live variable analysis want to know
690 * when a write to a variable screens off any preceding values that were in
694 fs_inst::is_partial_write() const
696 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
697 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
698 !this->dst
.is_contiguous());
702 fs_inst::components_read(unsigned i
) const
705 case FS_OPCODE_LINTERP
:
711 case FS_OPCODE_PIXEL_X
:
712 case FS_OPCODE_PIXEL_Y
:
716 case FS_OPCODE_FB_WRITE_LOGICAL
:
717 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
718 /* First/second FB write color. */
720 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
724 case SHADER_OPCODE_TEX_LOGICAL
:
725 case SHADER_OPCODE_TXD_LOGICAL
:
726 case SHADER_OPCODE_TXF_LOGICAL
:
727 case SHADER_OPCODE_TXL_LOGICAL
:
728 case SHADER_OPCODE_TXS_LOGICAL
:
729 case FS_OPCODE_TXB_LOGICAL
:
730 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
731 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
732 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
733 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
734 case SHADER_OPCODE_LOD_LOGICAL
:
735 case SHADER_OPCODE_TG4_LOGICAL
:
736 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
737 assert(src
[8].file
== IMM
&& src
[9].file
== IMM
);
738 /* Texture coordinates. */
741 /* Texture derivatives. */
742 else if ((i
== 2 || i
== 3) && opcode
== SHADER_OPCODE_TXD_LOGICAL
)
744 /* Texture offset. */
748 else if (i
== 5 && opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
753 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
754 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
755 assert(src
[3].file
== IMM
);
756 /* Surface coordinates. */
759 /* Surface operation source (ignored for reads). */
765 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
766 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
767 assert(src
[3].file
== IMM
&&
769 /* Surface coordinates. */
772 /* Surface operation source. */
778 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
779 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
780 assert(src
[3].file
== IMM
&&
782 const unsigned op
= src
[4].ud
;
783 /* Surface coordinates. */
786 /* Surface operation source. */
787 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
789 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
790 op
== BRW_AOP_PREDEC
))
802 fs_inst::regs_read(int arg
) const
805 case FS_OPCODE_FB_WRITE
:
806 case SHADER_OPCODE_URB_WRITE_SIMD8
:
807 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
808 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
809 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
810 case SHADER_OPCODE_URB_READ_SIMD8
:
811 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
812 case SHADER_OPCODE_UNTYPED_ATOMIC
:
813 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
814 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
815 case SHADER_OPCODE_TYPED_ATOMIC
:
816 case SHADER_OPCODE_TYPED_SURFACE_READ
:
817 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
818 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
823 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
824 /* The payload is actually stored in src1 */
829 case FS_OPCODE_LINTERP
:
834 case SHADER_OPCODE_LOAD_PAYLOAD
:
835 if (arg
< this->header_size
)
839 case CS_OPCODE_CS_TERMINATE
:
840 case SHADER_OPCODE_BARRIER
:
843 case SHADER_OPCODE_MOV_INDIRECT
:
845 assert(src
[2].file
== IMM
);
846 unsigned region_length
= src
[2].ud
;
848 if (src
[0].file
== FIXED_GRF
) {
849 /* If the start of the region is not register aligned, then
850 * there's some portion of the register that's technically
851 * unread at the beginning.
853 * However, the register allocator works in terms of whole
854 * registers, and does not use subnr. It assumes that the
855 * read starts at the beginning of the register, and extends
856 * regs_read() whole registers beyond that.
858 * To compensate, we extend the region length to include this
859 * unread portion at the beginning.
862 region_length
+= src
[0].subnr
* type_sz(src
[0].type
);
864 return DIV_ROUND_UP(region_length
, REG_SIZE
);
866 assert(!"Invalid register file");
872 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
877 switch (src
[arg
].file
) {
887 return DIV_ROUND_UP(components_read(arg
) *
888 src
[arg
].component_size(exec_size
),
891 unreachable("MRF registers are not allowed as sources");
897 fs_inst::reads_flag() const
903 fs_inst::writes_flag() const
905 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
906 opcode
!= BRW_OPCODE_IF
&&
907 opcode
!= BRW_OPCODE_WHILE
)) ||
908 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
912 * Returns how many MRFs an FS opcode will write over.
914 * Note that this is not the 0 or 1 implied writes in an actual gen
915 * instruction -- the FS opcodes often generate MOVs in addition.
918 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
923 if (inst
->base_mrf
== -1)
926 switch (inst
->opcode
) {
927 case SHADER_OPCODE_RCP
:
928 case SHADER_OPCODE_RSQ
:
929 case SHADER_OPCODE_SQRT
:
930 case SHADER_OPCODE_EXP2
:
931 case SHADER_OPCODE_LOG2
:
932 case SHADER_OPCODE_SIN
:
933 case SHADER_OPCODE_COS
:
934 return 1 * dispatch_width
/ 8;
935 case SHADER_OPCODE_POW
:
936 case SHADER_OPCODE_INT_QUOTIENT
:
937 case SHADER_OPCODE_INT_REMAINDER
:
938 return 2 * dispatch_width
/ 8;
939 case SHADER_OPCODE_TEX
:
941 case SHADER_OPCODE_TXD
:
942 case SHADER_OPCODE_TXF
:
943 case SHADER_OPCODE_TXF_CMS
:
944 case SHADER_OPCODE_TXF_CMS_W
:
945 case SHADER_OPCODE_TXF_MCS
:
946 case SHADER_OPCODE_TG4
:
947 case SHADER_OPCODE_TG4_OFFSET
:
948 case SHADER_OPCODE_TXL
:
949 case SHADER_OPCODE_TXS
:
950 case SHADER_OPCODE_LOD
:
951 case SHADER_OPCODE_SAMPLEINFO
:
953 case FS_OPCODE_FB_WRITE
:
955 case FS_OPCODE_GET_BUFFER_SIZE
:
956 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
957 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
959 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
961 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
963 case SHADER_OPCODE_UNTYPED_ATOMIC
:
964 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
965 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
966 case SHADER_OPCODE_TYPED_ATOMIC
:
967 case SHADER_OPCODE_TYPED_SURFACE_READ
:
968 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
969 case SHADER_OPCODE_URB_WRITE_SIMD8
:
970 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
971 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
972 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
973 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
974 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
975 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
976 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
979 unreachable("not reached");
984 fs_visitor::vgrf(const glsl_type
*const type
)
986 int reg_width
= dispatch_width
/ 8;
987 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
988 brw_type_for_base_type(type
));
991 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
996 this->type
= BRW_REGISTER_TYPE_F
;
997 this->stride
= (file
== UNIFORM
? 0 : 1);
1000 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1006 this->stride
= (file
== UNIFORM
? 0 : 1);
1009 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1010 * This brings in those uniform definitions
1013 fs_visitor::import_uniforms(fs_visitor
*v
)
1015 this->push_constant_loc
= v
->push_constant_loc
;
1016 this->pull_constant_loc
= v
->pull_constant_loc
;
1017 this->uniforms
= v
->uniforms
;
1018 this->param_size
= v
->param_size
;
1022 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
1023 bool origin_upper_left
)
1025 assert(stage
== MESA_SHADER_FRAGMENT
);
1026 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1027 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
1029 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
1031 /* gl_FragCoord.x */
1032 if (pixel_center_integer
) {
1033 bld
.MOV(wpos
, this->pixel_x
);
1035 bld
.ADD(wpos
, this->pixel_x
, fs_reg(0.5f
));
1037 wpos
= offset(wpos
, bld
, 1);
1039 /* gl_FragCoord.y */
1040 if (!flip
&& pixel_center_integer
) {
1041 bld
.MOV(wpos
, this->pixel_y
);
1043 fs_reg pixel_y
= this->pixel_y
;
1044 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
1047 pixel_y
.negate
= true;
1048 offset
+= key
->drawable_height
- 1.0f
;
1051 bld
.ADD(wpos
, pixel_y
, fs_reg(offset
));
1053 wpos
= offset(wpos
, bld
, 1);
1055 /* gl_FragCoord.z */
1056 if (devinfo
->gen
>= 6) {
1057 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1059 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1060 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1061 interp_reg(VARYING_SLOT_POS
, 2));
1063 wpos
= offset(wpos
, bld
, 1);
1065 /* gl_FragCoord.w: Already set up in emit_interpolation */
1066 bld
.MOV(wpos
, this->wpos_w
);
1072 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1073 glsl_interp_qualifier interpolation_mode
,
1074 bool is_centroid
, bool is_sample
)
1076 brw_wm_barycentric_interp_mode barycoord_mode
;
1077 if (devinfo
->gen
>= 6) {
1079 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1080 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1082 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1083 } else if (is_sample
) {
1084 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1085 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1087 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1089 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1090 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1092 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1095 /* On Ironlake and below, there is only one interpolation mode.
1096 * Centroid interpolation doesn't mean anything on this hardware --
1097 * there is no multisampling.
1099 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1101 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1102 this->delta_xy
[barycoord_mode
], interp
);
1106 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
1107 const glsl_type
*type
,
1108 glsl_interp_qualifier interpolation_mode
,
1109 int location
, bool mod_centroid
,
1112 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
1114 assert(stage
== MESA_SHADER_FRAGMENT
);
1115 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1116 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1118 unsigned int array_elements
;
1120 if (type
->is_array()) {
1121 array_elements
= type
->arrays_of_arrays_size();
1122 if (array_elements
== 0) {
1123 fail("dereferenced array '%s' has length 0\n", name
);
1125 type
= type
->without_array();
1130 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1132 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1133 if (key
->flat_shade
&& is_gl_Color
) {
1134 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1136 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1140 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1141 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1142 if (prog_data
->urb_setup
[location
] == -1) {
1143 /* If there's no incoming setup data for this slot, don't
1144 * emit interpolation for it.
1146 attr
= offset(attr
, bld
, type
->vector_elements
);
1151 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1152 /* Constant interpolation (flat shading) case. The SF has
1153 * handed us defined values in only the constant offset
1154 * field of the setup reg.
1156 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1157 struct brw_reg interp
= interp_reg(location
, k
);
1158 interp
= suboffset(interp
, 3);
1159 interp
.type
= attr
.type
;
1160 bld
.emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1161 attr
= offset(attr
, bld
, 1);
1164 /* Smooth/noperspective interpolation case. */
1165 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1166 struct brw_reg interp
= interp_reg(location
, k
);
1167 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1168 /* Get the pixel/sample mask into f0 so that we know
1169 * which pixels are lit. Then, for each channel that is
1170 * unlit, replace the centroid data with non-centroid
1173 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1176 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1178 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1179 inst
->predicate_inverse
= true;
1180 if (devinfo
->has_pln
)
1181 inst
->no_dd_clear
= true;
1183 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1184 mod_centroid
&& !key
->persample_shading
,
1185 mod_sample
|| key
->persample_shading
);
1186 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1187 inst
->predicate_inverse
= false;
1188 if (devinfo
->has_pln
)
1189 inst
->no_dd_check
= true;
1192 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1193 mod_centroid
&& !key
->persample_shading
,
1194 mod_sample
|| key
->persample_shading
);
1196 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1197 bld
.MUL(attr
, attr
, this->pixel_w
);
1199 attr
= offset(attr
, bld
, 1);
1209 fs_visitor::emit_frontfacing_interpolation()
1211 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1213 if (devinfo
->gen
>= 6) {
1214 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1215 * a boolean result from this (~0/true or 0/false).
1217 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1218 * this task in only one instruction:
1219 * - a negation source modifier will flip the bit; and
1220 * - a W -> D type conversion will sign extend the bit into the high
1221 * word of the destination.
1223 * An ASR 15 fills the low word of the destination.
1225 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1228 bld
.ASR(*reg
, g0
, fs_reg(15));
1230 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1231 * a boolean result from this (1/true or 0/false).
1233 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1234 * the negation source modifier to flip it. Unfortunately the SHR
1235 * instruction only operates on UD (or D with an abs source modifier)
1236 * sources without negation.
1238 * Instead, use ASR (which will give ~0/true or 0/false).
1240 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1243 bld
.ASR(*reg
, g1_6
, fs_reg(31));
1250 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1252 assert(stage
== MESA_SHADER_FRAGMENT
);
1253 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1254 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1256 if (key
->compute_pos_offset
) {
1257 /* Convert int_sample_pos to floating point */
1258 bld
.MOV(dst
, int_sample_pos
);
1259 /* Scale to the range [0, 1] */
1260 bld
.MUL(dst
, dst
, fs_reg(1 / 16.0f
));
1263 /* From ARB_sample_shading specification:
1264 * "When rendering to a non-multisample buffer, or if multisample
1265 * rasterization is disabled, gl_SamplePosition will always be
1268 bld
.MOV(dst
, fs_reg(0.5f
));
1273 fs_visitor::emit_samplepos_setup()
1275 assert(devinfo
->gen
>= 6);
1277 const fs_builder abld
= bld
.annotate("compute sample position");
1278 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1280 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1281 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1283 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1284 * mode will be enabled.
1286 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1287 * R31.1:0 Position Offset X/Y for Slot[3:0]
1288 * R31.3:2 Position Offset X/Y for Slot[7:4]
1291 * The X, Y sample positions come in as bytes in thread payload. So, read
1292 * the positions using vstride=16, width=8, hstride=2.
1294 struct brw_reg sample_pos_reg
=
1295 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1296 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1298 if (dispatch_width
== 8) {
1299 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1301 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1302 abld
.half(1).MOV(half(int_sample_x
, 1),
1303 fs_reg(suboffset(sample_pos_reg
, 16)));
1305 /* Compute gl_SamplePosition.x */
1306 compute_sample_position(pos
, int_sample_x
);
1307 pos
= offset(pos
, abld
, 1);
1308 if (dispatch_width
== 8) {
1309 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1311 abld
.half(0).MOV(half(int_sample_y
, 0),
1312 fs_reg(suboffset(sample_pos_reg
, 1)));
1313 abld
.half(1).MOV(half(int_sample_y
, 1),
1314 fs_reg(suboffset(sample_pos_reg
, 17)));
1316 /* Compute gl_SamplePosition.y */
1317 compute_sample_position(pos
, int_sample_y
);
1322 fs_visitor::emit_sampleid_setup()
1324 assert(stage
== MESA_SHADER_FRAGMENT
);
1325 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1326 assert(devinfo
->gen
>= 6);
1328 const fs_builder abld
= bld
.annotate("compute sample id");
1329 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1331 if (key
->compute_sample_id
) {
1332 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1334 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1336 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1337 * 8x multisampling, subspan 0 will represent sample N (where N
1338 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1339 * 7. We can find the value of N by looking at R0.0 bits 7:6
1340 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1341 * (since samples are always delivered in pairs). That is, we
1342 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1343 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1344 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1345 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1346 * populating a temporary variable with the sequence (0, 1, 2, 3),
1347 * and then reading from it using vstride=1, width=4, hstride=0.
1348 * These computations hold good for 4x multisampling as well.
1350 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1351 * the first four slots are sample 0 of subspan 0; the next four
1352 * are sample 1 of subspan 0; the third group is sample 0 of
1353 * subspan 1, and finally sample 1 of subspan 1.
1356 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1357 * accomodate 16x MSAA.
1359 unsigned sspi_mask
= devinfo
->gen
>= 9 ? 0x1c0 : 0xc0;
1361 abld
.exec_all().group(1, 0)
1362 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1364 abld
.exec_all().group(1, 0).SHR(t1
, t1
, fs_reg(5));
1366 /* This works for both SIMD8 and SIMD16 */
1367 abld
.exec_all().group(4, 0)
1368 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1370 /* This special instruction takes care of setting vstride=1,
1371 * width=4, hstride=0 of t2 during an ADD instruction.
1373 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1375 /* As per GL_ARB_sample_shading specification:
1376 * "When rendering to a non-multisample buffer, or if multisample
1377 * rasterization is disabled, gl_SampleID will always be zero."
1379 abld
.MOV(*reg
, fs_reg(0));
1386 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1388 if (!src
.abs
&& !src
.negate
)
1391 fs_reg temp
= bld
.vgrf(src
.type
);
1398 fs_visitor::emit_discard_jump()
1400 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1402 /* For performance, after a discard, jump to the end of the
1403 * shader if all relevant channels have been discarded.
1405 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1406 discard_jump
->flag_subreg
= 1;
1408 discard_jump
->predicate
= (dispatch_width
== 8)
1409 ? BRW_PREDICATE_ALIGN1_ANY8H
1410 : BRW_PREDICATE_ALIGN1_ANY16H
;
1411 discard_jump
->predicate_inverse
= true;
1415 fs_visitor::emit_gs_thread_end()
1417 assert(stage
== MESA_SHADER_GEOMETRY
);
1419 struct brw_gs_prog_data
*gs_prog_data
=
1420 (struct brw_gs_prog_data
*) prog_data
;
1422 if (gs_compile
->control_data_header_size_bits
> 0) {
1423 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1426 const fs_builder abld
= bld
.annotate("thread end");
1429 if (gs_prog_data
->static_vertex_count
!= -1) {
1430 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1431 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1432 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1433 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1434 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1437 /* Delete now dead instructions. */
1438 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1444 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1448 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1449 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1450 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1453 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1454 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1455 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1456 sources
[1] = this->final_gs_vertex_count
;
1457 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1458 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1466 fs_visitor::assign_curb_setup()
1468 if (dispatch_width
== 8) {
1469 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1471 if (stage
== MESA_SHADER_FRAGMENT
) {
1472 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1473 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1474 } else if (stage
== MESA_SHADER_COMPUTE
) {
1475 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1476 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1478 unreachable("Unsupported shader type!");
1482 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1484 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1485 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1486 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1487 if (inst
->src
[i
].file
== UNIFORM
) {
1488 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1490 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1491 constant_nr
= push_constant_loc
[uniform_nr
];
1493 /* Section 5.11 of the OpenGL 4.1 spec says:
1494 * "Out-of-bounds reads return undefined values, which include
1495 * values from other variables of the active program or zero."
1496 * Just return the first push constant.
1501 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1504 brw_reg
.abs
= inst
->src
[i
].abs
;
1505 brw_reg
.negate
= inst
->src
[i
].negate
;
1507 assert(inst
->src
[i
].stride
== 0);
1508 inst
->src
[i
] = byte_offset(
1509 retype(brw_reg
, inst
->src
[i
].type
),
1510 inst
->src
[i
].subreg_offset
);
1515 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1516 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1520 fs_visitor::calculate_urb_setup()
1522 assert(stage
== MESA_SHADER_FRAGMENT
);
1523 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1524 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1526 memset(prog_data
->urb_setup
, -1,
1527 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1530 /* Figure out where each of the incoming setup attributes lands. */
1531 if (devinfo
->gen
>= 6) {
1532 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1533 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1534 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1535 * first 16 varying inputs, so we can put them wherever we want.
1536 * Just put them in order.
1538 * This is useful because it means that (a) inputs not used by the
1539 * fragment shader won't take up valuable register space, and (b) we
1540 * won't have to recompile the fragment shader if it gets paired with
1541 * a different vertex (or geometry) shader.
1543 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1544 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1545 BITFIELD64_BIT(i
)) {
1546 prog_data
->urb_setup
[i
] = urb_next
++;
1550 bool include_vue_header
=
1551 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1553 /* We have enough input varyings that the SF/SBE pipeline stage can't
1554 * arbitrarily rearrange them to suit our whim; we have to put them
1555 * in an order that matches the output of the previous pipeline stage
1556 * (geometry or vertex shader).
1558 struct brw_vue_map prev_stage_vue_map
;
1559 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1560 key
->input_slots_valid
,
1561 nir
->info
.separate_shader
);
1563 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1565 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1566 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1568 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1569 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1570 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1571 BITFIELD64_BIT(varying
))) {
1572 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1575 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1578 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1579 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1580 /* Point size is packed into the header, not as a general attribute */
1581 if (i
== VARYING_SLOT_PSIZ
)
1584 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1585 /* The back color slot is skipped when the front color is
1586 * also written to. In addition, some slots can be
1587 * written in the vertex shader and not read in the
1588 * fragment shader. So the register number must always be
1589 * incremented, mapped or not.
1591 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1592 prog_data
->urb_setup
[i
] = urb_next
;
1598 * It's a FS only attribute, and we did interpolation for this attribute
1599 * in SF thread. So, count it here, too.
1601 * See compile_sf_prog() for more info.
1603 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1604 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1607 prog_data
->num_varying_inputs
= urb_next
;
1611 fs_visitor::assign_urb_setup()
1613 assert(stage
== MESA_SHADER_FRAGMENT
);
1614 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1616 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1618 /* Offset all the urb_setup[] index by the actual position of the
1619 * setup regs, now that the location of the constants has been chosen.
1621 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1622 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1623 assert(inst
->src
[1].file
== FIXED_GRF
);
1624 inst
->src
[1].nr
+= urb_start
;
1627 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1628 assert(inst
->src
[0].file
== FIXED_GRF
);
1629 inst
->src
[0].nr
+= urb_start
;
1633 /* Each attribute is 4 setup channels, each of which is half a reg. */
1634 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1638 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1640 for (int i
= 0; i
< inst
->sources
; i
++) {
1641 if (inst
->src
[i
].file
== ATTR
) {
1642 int grf
= payload
.num_regs
+
1643 prog_data
->curb_read_length
+
1645 inst
->src
[i
].reg_offset
;
1647 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : inst
->exec_size
;
1648 struct brw_reg reg
=
1649 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1650 inst
->src
[i
].subreg_offset
),
1651 inst
->exec_size
* inst
->src
[i
].stride
,
1652 width
, inst
->src
[i
].stride
);
1653 reg
.abs
= inst
->src
[i
].abs
;
1654 reg
.negate
= inst
->src
[i
].negate
;
1662 fs_visitor::assign_vs_urb_setup()
1664 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1666 assert(stage
== MESA_SHADER_VERTEX
);
1667 int count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1668 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1671 /* Each attribute is 4 regs. */
1672 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attributes
;
1674 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1676 /* Rewrite all ATTR file references to the hw grf that they land in. */
1677 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1678 convert_attr_sources_to_hw_regs(inst
);
1683 fs_visitor::assign_gs_urb_setup()
1685 assert(stage
== MESA_SHADER_GEOMETRY
);
1687 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1689 first_non_payload_grf
+=
1690 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1692 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1693 /* Rewrite all ATTR file references to GRFs. */
1694 convert_attr_sources_to_hw_regs(inst
);
1700 * Split large virtual GRFs into separate components if we can.
1702 * This is mostly duplicated with what brw_fs_vector_splitting does,
1703 * but that's really conservative because it's afraid of doing
1704 * splitting that doesn't result in real progress after the rest of
1705 * the optimization phases, which would cause infinite looping in
1706 * optimization. We can do it once here, safely. This also has the
1707 * opportunity to split interpolated values, or maybe even uniforms,
1708 * which we don't have at the IR level.
1710 * We want to split, because virtual GRFs are what we register
1711 * allocate and spill (due to contiguousness requirements for some
1712 * instructions), and they're what we naturally generate in the
1713 * codegen process, but most virtual GRFs don't actually need to be
1714 * contiguous sets of GRFs. If we split, we'll end up with reduced
1715 * live intervals and better dead code elimination and coalescing.
1718 fs_visitor::split_virtual_grfs()
1720 int num_vars
= this->alloc
.count
;
1722 /* Count the total number of registers */
1724 int vgrf_to_reg
[num_vars
];
1725 for (int i
= 0; i
< num_vars
; i
++) {
1726 vgrf_to_reg
[i
] = reg_count
;
1727 reg_count
+= alloc
.sizes
[i
];
1730 /* An array of "split points". For each register slot, this indicates
1731 * if this slot can be separated from the previous slot. Every time an
1732 * instruction uses multiple elements of a register (as a source or
1733 * destination), we mark the used slots as inseparable. Then we go
1734 * through and split the registers into the smallest pieces we can.
1736 bool split_points
[reg_count
];
1737 memset(split_points
, 0, sizeof(split_points
));
1739 /* Mark all used registers as fully splittable */
1740 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1741 if (inst
->dst
.file
== VGRF
) {
1742 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1743 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1744 split_points
[reg
+ j
] = true;
1747 for (int i
= 0; i
< inst
->sources
; i
++) {
1748 if (inst
->src
[i
].file
== VGRF
) {
1749 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1750 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1751 split_points
[reg
+ j
] = true;
1756 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1757 if (inst
->dst
.file
== VGRF
) {
1758 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1759 for (int j
= 1; j
< inst
->regs_written
; j
++)
1760 split_points
[reg
+ j
] = false;
1762 for (int i
= 0; i
< inst
->sources
; i
++) {
1763 if (inst
->src
[i
].file
== VGRF
) {
1764 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1765 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1766 split_points
[reg
+ j
] = false;
1771 int new_virtual_grf
[reg_count
];
1772 int new_reg_offset
[reg_count
];
1775 for (int i
= 0; i
< num_vars
; i
++) {
1776 /* The first one should always be 0 as a quick sanity check. */
1777 assert(split_points
[reg
] == false);
1780 new_reg_offset
[reg
] = 0;
1785 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1786 /* If this is a split point, reset the offset to 0 and allocate a
1787 * new virtual GRF for the previous offset many registers
1789 if (split_points
[reg
]) {
1790 assert(offset
<= MAX_VGRF_SIZE
);
1791 int grf
= alloc
.allocate(offset
);
1792 for (int k
= reg
- offset
; k
< reg
; k
++)
1793 new_virtual_grf
[k
] = grf
;
1796 new_reg_offset
[reg
] = offset
;
1801 /* The last one gets the original register number */
1802 assert(offset
<= MAX_VGRF_SIZE
);
1803 alloc
.sizes
[i
] = offset
;
1804 for (int k
= reg
- offset
; k
< reg
; k
++)
1805 new_virtual_grf
[k
] = i
;
1807 assert(reg
== reg_count
);
1809 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1810 if (inst
->dst
.file
== VGRF
) {
1811 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1812 inst
->dst
.nr
= new_virtual_grf
[reg
];
1813 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1814 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1816 for (int i
= 0; i
< inst
->sources
; i
++) {
1817 if (inst
->src
[i
].file
== VGRF
) {
1818 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1819 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1820 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1821 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1825 invalidate_live_intervals();
1829 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1831 * During code generation, we create tons of temporary variables, many of
1832 * which get immediately killed and are never used again. Yet, in later
1833 * optimization and analysis passes, such as compute_live_intervals, we need
1834 * to loop over all the virtual GRFs. Compacting them can save a lot of
1838 fs_visitor::compact_virtual_grfs()
1840 bool progress
= false;
1841 int remap_table
[this->alloc
.count
];
1842 memset(remap_table
, -1, sizeof(remap_table
));
1844 /* Mark which virtual GRFs are used. */
1845 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1846 if (inst
->dst
.file
== VGRF
)
1847 remap_table
[inst
->dst
.nr
] = 0;
1849 for (int i
= 0; i
< inst
->sources
; i
++) {
1850 if (inst
->src
[i
].file
== VGRF
)
1851 remap_table
[inst
->src
[i
].nr
] = 0;
1855 /* Compact the GRF arrays. */
1857 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1858 if (remap_table
[i
] == -1) {
1859 /* We just found an unused register. This means that we are
1860 * actually going to compact something.
1864 remap_table
[i
] = new_index
;
1865 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1866 invalidate_live_intervals();
1871 this->alloc
.count
= new_index
;
1873 /* Patch all the instructions to use the newly renumbered registers */
1874 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1875 if (inst
->dst
.file
== VGRF
)
1876 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1878 for (int i
= 0; i
< inst
->sources
; i
++) {
1879 if (inst
->src
[i
].file
== VGRF
)
1880 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1884 /* Patch all the references to delta_xy, since they're used in register
1885 * allocation. If they're unused, switch them to BAD_FILE so we don't
1886 * think some random VGRF is delta_xy.
1888 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1889 if (delta_xy
[i
].file
== VGRF
) {
1890 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1891 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1893 delta_xy
[i
].file
= BAD_FILE
;
1902 * Assign UNIFORM file registers to either push constants or pull constants.
1904 * We allow a fragment shader to have more than the specified minimum
1905 * maximum number of fragment shader uniform components (64). If
1906 * there are too many of these, they'd fill up all of register space.
1907 * So, this will push some of them out to the pull constant buffer and
1908 * update the program to load them. We also use pull constants for all
1909 * indirect constant loads because we don't support indirect accesses in
1913 fs_visitor::assign_constant_locations()
1915 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1916 if (dispatch_width
!= 8)
1919 unsigned int num_pull_constants
= 0;
1921 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1922 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1924 bool is_live
[uniforms
];
1925 memset(is_live
, 0, sizeof(is_live
));
1927 /* First, we walk through the instructions and do two things:
1929 * 1) Figure out which uniforms are live.
1931 * 2) Find all indirect access of uniform arrays and flag them as needing
1932 * to go into the pull constant buffer.
1934 * Note that we don't move constant-indexed accesses to arrays. No
1935 * testing has been done of the performance impact of this choice.
1937 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1938 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1939 if (inst
->src
[i
].file
!= UNIFORM
)
1942 if (inst
->src
[i
].reladdr
) {
1943 int uniform
= inst
->src
[i
].nr
;
1945 /* If this array isn't already present in the pull constant buffer,
1948 if (pull_constant_loc
[uniform
] == -1) {
1949 assert(param_size
[uniform
]);
1950 for (int j
= 0; j
< param_size
[uniform
]; j
++)
1951 pull_constant_loc
[uniform
+ j
] = num_pull_constants
++;
1954 /* Mark the the one accessed uniform as live */
1955 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1956 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1957 is_live
[constant_nr
] = true;
1962 /* Only allow 16 registers (128 uniform components) as push constants.
1964 * Just demote the end of the list. We could probably do better
1965 * here, demoting things that are rarely used in the program first.
1967 * If changing this value, note the limitation about total_regs in
1970 unsigned int max_push_components
= 16 * 8;
1971 unsigned int num_push_constants
= 0;
1973 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1975 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1976 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1977 /* This UNIFORM register is either dead, or has already been demoted
1978 * to a pull const. Mark it as no longer living in the param[] array.
1980 push_constant_loc
[i
] = -1;
1984 if (num_push_constants
< max_push_components
) {
1985 /* Retain as a push constant. Record the location in the params[]
1988 push_constant_loc
[i
] = num_push_constants
++;
1990 /* Demote to a pull constant. */
1991 push_constant_loc
[i
] = -1;
1992 pull_constant_loc
[i
] = num_pull_constants
++;
1996 stage_prog_data
->nr_params
= num_push_constants
;
1997 stage_prog_data
->nr_pull_params
= num_pull_constants
;
1999 /* Up until now, the param[] array has been indexed by reg + reg_offset
2000 * of UNIFORM registers. Move pull constants into pull_param[] and
2001 * condense param[] to only contain the uniforms we chose to push.
2003 * NOTE: Because we are condensing the params[] array, we know that
2004 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2005 * having to make a copy.
2007 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2008 const gl_constant_value
*value
= stage_prog_data
->param
[i
];
2010 if (pull_constant_loc
[i
] != -1) {
2011 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2012 } else if (push_constant_loc
[i
] != -1) {
2013 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2019 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2020 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2023 fs_visitor::demote_pull_constants()
2025 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2026 for (int i
= 0; i
< inst
->sources
; i
++) {
2027 if (inst
->src
[i
].file
!= UNIFORM
)
2031 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2032 if (location
>= uniforms
) /* Out of bounds access */
2035 pull_index
= pull_constant_loc
[location
];
2037 if (pull_index
== -1)
2040 /* Set up the annotation tracking for new generated instructions. */
2041 const fs_builder
ibld(this, block
, inst
);
2042 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2043 fs_reg dst
= vgrf(glsl_type::float_type
);
2045 assert(inst
->src
[i
].stride
== 0);
2047 /* Generate a pull load into dst. */
2048 if (inst
->src
[i
].reladdr
) {
2049 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
2051 *inst
->src
[i
].reladdr
,
2053 inst
->src
[i
].reladdr
= NULL
;
2054 inst
->src
[i
].stride
= 1;
2056 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2057 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
2058 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2059 dst
, fs_reg(index
), offset
);
2060 inst
->src
[i
].set_smear(pull_index
& 3);
2062 brw_mark_surface_used(prog_data
, index
);
2064 /* Rewrite the instruction to use the temporary VGRF. */
2065 inst
->src
[i
].file
= VGRF
;
2066 inst
->src
[i
].nr
= dst
.nr
;
2067 inst
->src
[i
].reg_offset
= 0;
2070 invalidate_live_intervals();
2074 fs_visitor::opt_algebraic()
2076 bool progress
= false;
2078 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2079 switch (inst
->opcode
) {
2080 case BRW_OPCODE_MOV
:
2081 if (inst
->src
[0].file
!= IMM
)
2084 if (inst
->saturate
) {
2085 if (inst
->dst
.type
!= inst
->src
[0].type
)
2086 assert(!"unimplemented: saturate mixed types");
2088 if (brw_saturate_immediate(inst
->dst
.type
, &inst
->src
[0])) {
2089 inst
->saturate
= false;
2095 case BRW_OPCODE_MUL
:
2096 if (inst
->src
[1].file
!= IMM
)
2100 if (inst
->src
[1].is_one()) {
2101 inst
->opcode
= BRW_OPCODE_MOV
;
2102 inst
->src
[1] = reg_undef
;
2108 if (inst
->src
[1].is_negative_one()) {
2109 inst
->opcode
= BRW_OPCODE_MOV
;
2110 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2111 inst
->src
[1] = reg_undef
;
2117 if (inst
->src
[1].is_zero()) {
2118 inst
->opcode
= BRW_OPCODE_MOV
;
2119 inst
->src
[0] = inst
->src
[1];
2120 inst
->src
[1] = reg_undef
;
2125 if (inst
->src
[0].file
== IMM
) {
2126 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2127 inst
->opcode
= BRW_OPCODE_MOV
;
2128 inst
->src
[0].f
*= inst
->src
[1].f
;
2129 inst
->src
[1] = reg_undef
;
2134 case BRW_OPCODE_ADD
:
2135 if (inst
->src
[1].file
!= IMM
)
2139 if (inst
->src
[1].is_zero()) {
2140 inst
->opcode
= BRW_OPCODE_MOV
;
2141 inst
->src
[1] = reg_undef
;
2146 if (inst
->src
[0].file
== IMM
) {
2147 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2148 inst
->opcode
= BRW_OPCODE_MOV
;
2149 inst
->src
[0].f
+= inst
->src
[1].f
;
2150 inst
->src
[1] = reg_undef
;
2156 if (inst
->src
[0].equals(inst
->src
[1])) {
2157 inst
->opcode
= BRW_OPCODE_MOV
;
2158 inst
->src
[1] = reg_undef
;
2163 case BRW_OPCODE_LRP
:
2164 if (inst
->src
[1].equals(inst
->src
[2])) {
2165 inst
->opcode
= BRW_OPCODE_MOV
;
2166 inst
->src
[0] = inst
->src
[1];
2167 inst
->src
[1] = reg_undef
;
2168 inst
->src
[2] = reg_undef
;
2173 case BRW_OPCODE_CMP
:
2174 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2176 inst
->src
[0].negate
&&
2177 inst
->src
[1].is_zero()) {
2178 inst
->src
[0].abs
= false;
2179 inst
->src
[0].negate
= false;
2180 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2185 case BRW_OPCODE_SEL
:
2186 if (inst
->src
[0].equals(inst
->src
[1])) {
2187 inst
->opcode
= BRW_OPCODE_MOV
;
2188 inst
->src
[1] = reg_undef
;
2189 inst
->predicate
= BRW_PREDICATE_NONE
;
2190 inst
->predicate_inverse
= false;
2192 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2193 switch (inst
->conditional_mod
) {
2194 case BRW_CONDITIONAL_LE
:
2195 case BRW_CONDITIONAL_L
:
2196 switch (inst
->src
[1].type
) {
2197 case BRW_REGISTER_TYPE_F
:
2198 if (inst
->src
[1].f
>= 1.0f
) {
2199 inst
->opcode
= BRW_OPCODE_MOV
;
2200 inst
->src
[1] = reg_undef
;
2201 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2209 case BRW_CONDITIONAL_GE
:
2210 case BRW_CONDITIONAL_G
:
2211 switch (inst
->src
[1].type
) {
2212 case BRW_REGISTER_TYPE_F
:
2213 if (inst
->src
[1].f
<= 0.0f
) {
2214 inst
->opcode
= BRW_OPCODE_MOV
;
2215 inst
->src
[1] = reg_undef
;
2216 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2228 case BRW_OPCODE_MAD
:
2229 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2230 inst
->opcode
= BRW_OPCODE_MOV
;
2231 inst
->src
[1] = reg_undef
;
2232 inst
->src
[2] = reg_undef
;
2234 } else if (inst
->src
[0].is_zero()) {
2235 inst
->opcode
= BRW_OPCODE_MUL
;
2236 inst
->src
[0] = inst
->src
[2];
2237 inst
->src
[2] = reg_undef
;
2239 } else if (inst
->src
[1].is_one()) {
2240 inst
->opcode
= BRW_OPCODE_ADD
;
2241 inst
->src
[1] = inst
->src
[2];
2242 inst
->src
[2] = reg_undef
;
2244 } else if (inst
->src
[2].is_one()) {
2245 inst
->opcode
= BRW_OPCODE_ADD
;
2246 inst
->src
[2] = reg_undef
;
2248 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2249 inst
->opcode
= BRW_OPCODE_ADD
;
2250 inst
->src
[1].f
*= inst
->src
[2].f
;
2251 inst
->src
[2] = reg_undef
;
2255 case SHADER_OPCODE_RCP
: {
2256 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2257 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2258 if (inst
->src
[0].equals(prev
->dst
)) {
2259 inst
->opcode
= SHADER_OPCODE_RSQ
;
2260 inst
->src
[0] = prev
->src
[0];
2266 case SHADER_OPCODE_BROADCAST
:
2267 if (is_uniform(inst
->src
[0])) {
2268 inst
->opcode
= BRW_OPCODE_MOV
;
2270 inst
->force_writemask_all
= true;
2272 } else if (inst
->src
[1].file
== IMM
) {
2273 inst
->opcode
= BRW_OPCODE_MOV
;
2274 inst
->src
[0] = component(inst
->src
[0],
2277 inst
->force_writemask_all
= true;
2286 /* Swap if src[0] is immediate. */
2287 if (progress
&& inst
->is_commutative()) {
2288 if (inst
->src
[0].file
== IMM
) {
2289 fs_reg tmp
= inst
->src
[1];
2290 inst
->src
[1] = inst
->src
[0];
2299 * Optimize sample messages that have constant zero values for the trailing
2300 * texture coordinates. We can just reduce the message length for these
2301 * instructions instead of reserving a register for it. Trailing parameters
2302 * that aren't sent default to zero anyway. This will cause the dead code
2303 * eliminator to remove the MOV instruction that would otherwise be emitted to
2304 * set up the zero value.
2307 fs_visitor::opt_zero_samples()
2309 /* Gen4 infers the texturing opcode based on the message length so we can't
2312 if (devinfo
->gen
< 5)
2315 bool progress
= false;
2317 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2318 if (!inst
->is_tex())
2321 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2323 if (load_payload
->is_head_sentinel() ||
2324 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2327 /* We don't want to remove the message header or the first parameter.
2328 * Removing the first parameter is not allowed, see the Haswell PRM
2329 * volume 7, page 149:
2331 * "Parameter 0 is required except for the sampleinfo message, which
2332 * has no parameter 0"
2334 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2335 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2336 (inst
->exec_size
/ 8) +
2337 inst
->header_size
- 1].is_zero()) {
2338 inst
->mlen
-= inst
->exec_size
/ 8;
2344 invalidate_live_intervals();
2350 * Optimize sample messages which are followed by the final RT write.
2352 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2353 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2354 * final texturing results copied to the framebuffer write payload and modify
2355 * them to write to the framebuffer directly.
2358 fs_visitor::opt_sampler_eot()
2360 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2362 if (stage
!= MESA_SHADER_FRAGMENT
)
2365 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2368 /* FINISHME: It should be possible to implement this optimization when there
2369 * are multiple drawbuffers.
2371 if (key
->nr_color_regions
!= 1)
2374 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2375 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2376 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2377 assert(fb_write
->eot
);
2378 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2380 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2382 /* There wasn't one; nothing to do. */
2383 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2386 /* 3D Sampler » Messages » Message Format
2388 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2389 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2391 if (tex_inst
->opcode
== SHADER_OPCODE_TXS
||
2392 tex_inst
->opcode
== SHADER_OPCODE_SAMPLEINFO
||
2393 tex_inst
->opcode
== SHADER_OPCODE_LOD
||
2394 tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2395 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2398 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2399 * It's very likely to be the previous instruction.
2401 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2402 if (load_payload
->is_head_sentinel() ||
2403 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2406 assert(!tex_inst
->eot
); /* We can't get here twice */
2407 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2409 const fs_builder
ibld(this, block
, tex_inst
);
2411 tex_inst
->offset
|= fb_write
->target
<< 24;
2412 tex_inst
->eot
= true;
2413 tex_inst
->dst
= ibld
.null_reg_ud();
2414 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2416 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2417 * to create a new LOAD_PAYLOAD command with the same sources and a space
2418 * saved for the header. Using a new destination register not only makes sure
2419 * we have enough space, but it will make sure the dead code eliminator kills
2420 * the instruction that this will replace.
2422 if (tex_inst
->header_size
!= 0)
2425 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2426 load_payload
->sources
+ 1);
2427 fs_reg
*new_sources
=
2428 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2430 new_sources
[0] = fs_reg();
2431 for (int i
= 0; i
< load_payload
->sources
; i
++)
2432 new_sources
[i
+1] = load_payload
->src
[i
];
2434 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2435 * requires a lot of information about the sources to appropriately figure
2436 * out the number of registers needed to be used. Given this stage in our
2437 * optimization, we may not have the appropriate GRFs required by
2438 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2439 * manually emit the instruction.
2441 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2442 load_payload
->exec_size
,
2445 load_payload
->sources
+ 1);
2447 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2448 new_load_payload
->header_size
= 1;
2450 tex_inst
->header_size
= 1;
2451 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2452 tex_inst
->src
[0] = send_header
;
2458 fs_visitor::opt_register_renaming()
2460 bool progress
= false;
2463 int remap
[alloc
.count
];
2464 memset(remap
, -1, sizeof(int) * alloc
.count
);
2466 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2467 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2469 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2470 inst
->opcode
== BRW_OPCODE_WHILE
) {
2474 /* Rewrite instruction sources. */
2475 for (int i
= 0; i
< inst
->sources
; i
++) {
2476 if (inst
->src
[i
].file
== VGRF
&&
2477 remap
[inst
->src
[i
].nr
] != -1 &&
2478 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2479 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2484 const int dst
= inst
->dst
.nr
;
2487 inst
->dst
.file
== VGRF
&&
2488 alloc
.sizes
[inst
->dst
.nr
] == inst
->exec_size
/ 8 &&
2489 !inst
->is_partial_write()) {
2490 if (remap
[dst
] == -1) {
2493 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2494 inst
->dst
.nr
= remap
[dst
];
2497 } else if (inst
->dst
.file
== VGRF
&&
2499 remap
[dst
] != dst
) {
2500 inst
->dst
.nr
= remap
[dst
];
2506 invalidate_live_intervals();
2508 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2509 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2510 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2519 * Remove redundant or useless discard jumps.
2521 * For example, we can eliminate jumps in the following sequence:
2523 * discard-jump (redundant with the next jump)
2524 * discard-jump (useless; jumps to the next instruction)
2528 fs_visitor::opt_redundant_discard_jumps()
2530 bool progress
= false;
2532 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2534 fs_inst
*placeholder_halt
= NULL
;
2535 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2536 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2537 placeholder_halt
= inst
;
2542 if (!placeholder_halt
)
2545 /* Delete any HALTs immediately before the placeholder halt. */
2546 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2547 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2548 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2549 prev
->remove(last_bblock
);
2554 invalidate_live_intervals();
2560 fs_visitor::compute_to_mrf()
2562 bool progress
= false;
2565 /* No MRFs on Gen >= 7. */
2566 if (devinfo
->gen
>= 7)
2569 calculate_live_intervals();
2571 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2575 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2576 inst
->is_partial_write() ||
2577 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2578 inst
->dst
.type
!= inst
->src
[0].type
||
2579 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2580 !inst
->src
[0].is_contiguous() ||
2581 inst
->src
[0].subreg_offset
)
2584 /* Work out which hardware MRF registers are written by this
2587 int mrf_low
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2589 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2590 mrf_high
= mrf_low
+ 4;
2591 } else if (inst
->exec_size
== 16) {
2592 mrf_high
= mrf_low
+ 1;
2597 /* Can't compute-to-MRF this GRF if someone else was going to
2600 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2603 /* Found a move of a GRF to a MRF. Let's see if we can go
2604 * rewrite the thing that made this GRF to write into the MRF.
2606 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2607 if (scan_inst
->dst
.file
== VGRF
&&
2608 scan_inst
->dst
.nr
== inst
->src
[0].nr
) {
2609 /* Found the last thing to write our reg we want to turn
2610 * into a compute-to-MRF.
2613 /* If this one instruction didn't populate all the
2614 * channels, bail. We might be able to rewrite everything
2615 * that writes that reg, but it would require smarter
2616 * tracking to delay the rewriting until complete success.
2618 if (scan_inst
->is_partial_write())
2621 /* Things returning more than one register would need us to
2622 * understand coalescing out more than one MOV at a time.
2624 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2627 /* SEND instructions can't have MRF as a destination. */
2628 if (scan_inst
->mlen
)
2631 if (devinfo
->gen
== 6) {
2632 /* gen6 math instructions must have the destination be
2633 * GRF, so no compute-to-MRF for them.
2635 if (scan_inst
->is_math()) {
2640 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2641 /* Found the creator of our MRF's source value. */
2642 scan_inst
->dst
.file
= MRF
;
2643 scan_inst
->dst
.nr
= inst
->dst
.nr
;
2644 scan_inst
->saturate
|= inst
->saturate
;
2645 inst
->remove(block
);
2651 /* We don't handle control flow here. Most computation of
2652 * values that end up in MRFs are shortly before the MRF
2655 if (block
->start() == scan_inst
)
2658 /* You can't read from an MRF, so if someone else reads our
2659 * MRF's source GRF that we wanted to rewrite, that stops us.
2661 bool interfered
= false;
2662 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2663 if (scan_inst
->src
[i
].file
== VGRF
&&
2664 scan_inst
->src
[i
].nr
== inst
->src
[0].nr
&&
2665 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2672 if (scan_inst
->dst
.file
== MRF
) {
2673 /* If somebody else writes our MRF here, we can't
2674 * compute-to-MRF before that.
2676 int scan_mrf_low
= scan_inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2679 if (scan_inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2680 scan_mrf_high
= scan_mrf_low
+ 4;
2681 } else if (scan_inst
->exec_size
== 16) {
2682 scan_mrf_high
= scan_mrf_low
+ 1;
2684 scan_mrf_high
= scan_mrf_low
;
2687 if (mrf_low
== scan_mrf_low
||
2688 mrf_low
== scan_mrf_high
||
2689 mrf_high
== scan_mrf_low
||
2690 mrf_high
== scan_mrf_high
) {
2695 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2696 /* Found a SEND instruction, which means that there are
2697 * live values in MRFs from base_mrf to base_mrf +
2698 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2701 if (mrf_low
>= scan_inst
->base_mrf
&&
2702 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2705 if (mrf_high
>= scan_inst
->base_mrf
&&
2706 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2714 invalidate_live_intervals();
2720 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2721 * flow. We could probably do better here with some form of divergence
2725 fs_visitor::eliminate_find_live_channel()
2727 bool progress
= false;
2730 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2731 switch (inst
->opcode
) {
2737 case BRW_OPCODE_ENDIF
:
2738 case BRW_OPCODE_WHILE
:
2742 case FS_OPCODE_DISCARD_JUMP
:
2743 /* This can potentially make control flow non-uniform until the end
2748 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2750 inst
->opcode
= BRW_OPCODE_MOV
;
2751 inst
->src
[0] = fs_reg(0u);
2753 inst
->force_writemask_all
= true;
2767 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2768 * instructions to FS_OPCODE_REP_FB_WRITE.
2771 fs_visitor::emit_repclear_shader()
2773 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2775 int color_mrf
= base_mrf
+ 2;
2777 fs_inst
*mov
= bld
.exec_all().group(4, 0)
2778 .MOV(brw_message_reg(color_mrf
),
2779 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2782 if (key
->nr_color_regions
== 1) {
2783 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2784 write
->saturate
= key
->clamp_fragment_color
;
2785 write
->base_mrf
= color_mrf
;
2787 write
->header_size
= 0;
2790 assume(key
->nr_color_regions
> 0);
2791 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2792 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2793 write
->saturate
= key
->clamp_fragment_color
;
2794 write
->base_mrf
= base_mrf
;
2796 write
->header_size
= 2;
2804 assign_constant_locations();
2805 assign_curb_setup();
2807 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2808 assert(mov
->src
[0].file
== FIXED_GRF
);
2809 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2813 * Walks through basic blocks, looking for repeated MRF writes and
2814 * removing the later ones.
2817 fs_visitor::remove_duplicate_mrf_writes()
2819 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2820 bool progress
= false;
2822 /* Need to update the MRF tracking for compressed instructions. */
2823 if (dispatch_width
== 16)
2826 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2828 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2829 if (inst
->is_control_flow()) {
2830 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2833 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2834 inst
->dst
.file
== MRF
) {
2835 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
2836 if (prev_inst
&& inst
->equals(prev_inst
)) {
2837 inst
->remove(block
);
2843 /* Clear out the last-write records for MRFs that were overwritten. */
2844 if (inst
->dst
.file
== MRF
) {
2845 last_mrf_move
[inst
->dst
.nr
] = NULL
;
2848 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2849 /* Found a SEND instruction, which will include two or fewer
2850 * implied MRF writes. We could do better here.
2852 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2853 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2857 /* Clear out any MRF move records whose sources got overwritten. */
2858 if (inst
->dst
.file
== VGRF
) {
2859 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2860 if (last_mrf_move
[i
] &&
2861 last_mrf_move
[i
]->src
[0].nr
== inst
->dst
.nr
) {
2862 last_mrf_move
[i
] = NULL
;
2867 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2868 inst
->dst
.file
== MRF
&&
2869 inst
->src
[0].file
== VGRF
&&
2870 !inst
->is_partial_write()) {
2871 last_mrf_move
[inst
->dst
.nr
] = inst
;
2876 invalidate_live_intervals();
2882 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2884 /* Clear the flag for registers that actually got read (as expected). */
2885 for (int i
= 0; i
< inst
->sources
; i
++) {
2887 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
2888 grf
= inst
->src
[i
].nr
;
2893 if (grf
>= first_grf
&&
2894 grf
< first_grf
+ grf_len
) {
2895 deps
[grf
- first_grf
] = false;
2896 if (inst
->exec_size
== 16)
2897 deps
[grf
- first_grf
+ 1] = false;
2903 * Implements this workaround for the original 965:
2905 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2906 * check for post destination dependencies on this instruction, software
2907 * must ensure that there is no destination hazard for the case of ‘write
2908 * followed by a posted write’ shown in the following example.
2911 * 2. send r3.xy <rest of send instruction>
2914 * Due to no post-destination dependency check on the ‘send’, the above
2915 * code sequence could have two instructions (1 and 2) in flight at the
2916 * same time that both consider ‘r3’ as the target of their final writes.
2919 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2922 int write_len
= inst
->regs_written
;
2923 int first_write_grf
= inst
->dst
.nr
;
2924 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2925 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2927 memset(needs_dep
, false, sizeof(needs_dep
));
2928 memset(needs_dep
, true, write_len
);
2930 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2932 /* Walk backwards looking for writes to registers we're writing which
2933 * aren't read since being written. If we hit the start of the program,
2934 * we assume that there are no outstanding dependencies on entry to the
2937 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2938 /* If we hit control flow, assume that there *are* outstanding
2939 * dependencies, and force their cleanup before our instruction.
2941 if (block
->start() == scan_inst
) {
2942 for (int i
= 0; i
< write_len
; i
++) {
2944 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
2945 first_write_grf
+ i
);
2950 /* We insert our reads as late as possible on the assumption that any
2951 * instruction but a MOV that might have left us an outstanding
2952 * dependency has more latency than a MOV.
2954 if (scan_inst
->dst
.file
== VGRF
) {
2955 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2956 int reg
= scan_inst
->dst
.nr
+ i
;
2958 if (reg
>= first_write_grf
&&
2959 reg
< first_write_grf
+ write_len
&&
2960 needs_dep
[reg
- first_write_grf
]) {
2961 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
2962 needs_dep
[reg
- first_write_grf
] = false;
2963 if (scan_inst
->exec_size
== 16)
2964 needs_dep
[reg
- first_write_grf
+ 1] = false;
2969 /* Clear the flag for registers that actually got read (as expected). */
2970 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2972 /* Continue the loop only if we haven't resolved all the dependencies */
2974 for (i
= 0; i
< write_len
; i
++) {
2984 * Implements this workaround for the original 965:
2986 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2987 * used as a destination register until after it has been sourced by an
2988 * instruction with a different destination register.
2991 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
2993 int write_len
= inst
->regs_written
;
2994 int first_write_grf
= inst
->dst
.nr
;
2995 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2996 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2998 memset(needs_dep
, false, sizeof(needs_dep
));
2999 memset(needs_dep
, true, write_len
);
3000 /* Walk forwards looking for writes to registers we're writing which aren't
3001 * read before being written.
3003 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3004 /* If we hit control flow, force resolve all remaining dependencies. */
3005 if (block
->end() == scan_inst
) {
3006 for (int i
= 0; i
< write_len
; i
++) {
3008 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3009 first_write_grf
+ i
);
3014 /* Clear the flag for registers that actually got read (as expected). */
3015 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3017 /* We insert our reads as late as possible since they're reading the
3018 * result of a SEND, which has massive latency.
3020 if (scan_inst
->dst
.file
== VGRF
&&
3021 scan_inst
->dst
.nr
>= first_write_grf
&&
3022 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3023 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3024 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3026 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3029 /* Continue the loop only if we haven't resolved all the dependencies */
3031 for (i
= 0; i
< write_len
; i
++) {
3041 fs_visitor::insert_gen4_send_dependency_workarounds()
3043 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3046 bool progress
= false;
3048 /* Note that we're done with register allocation, so GRF fs_regs always
3049 * have a .reg_offset of 0.
3052 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3053 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3054 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3055 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3061 invalidate_live_intervals();
3065 * Turns the generic expression-style uniform pull constant load instruction
3066 * into a hardware-specific series of instructions for loading a pull
3069 * The expression style allows the CSE pass before this to optimize out
3070 * repeated loads from the same offset, and gives the pre-register-allocation
3071 * scheduling full flexibility, while the conversion to native instructions
3072 * allows the post-register-allocation scheduler the best information
3075 * Note that execution masking for setting up pull constant loads is special:
3076 * the channels that need to be written are unrelated to the current execution
3077 * mask, since a later instruction will use one of the result channels as a
3078 * source operand for all 8 or 16 of its channels.
3081 fs_visitor::lower_uniform_pull_constant_loads()
3083 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3084 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3087 if (devinfo
->gen
>= 7) {
3088 /* The offset arg before was a vec4-aligned byte offset. We need to
3089 * turn it into a dword offset.
3091 fs_reg const_offset_reg
= inst
->src
[1];
3092 assert(const_offset_reg
.file
== IMM
&&
3093 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3094 const_offset_reg
.ud
/= 4;
3096 fs_reg payload
, offset
;
3097 if (devinfo
->gen
>= 9) {
3098 /* We have to use a message header on Skylake to get SIMD4x2
3099 * mode. Reserve space for the register.
3101 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3102 offset
.reg_offset
++;
3105 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3109 /* This is actually going to be a MOV, but since only the first dword
3110 * is accessed, we have a special opcode to do just that one. Note
3111 * that this needs to be an operation that will be considered a def
3112 * by live variable analysis, or register allocation will explode.
3114 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3115 8, offset
, const_offset_reg
);
3116 setup
->force_writemask_all
= true;
3118 setup
->ir
= inst
->ir
;
3119 setup
->annotation
= inst
->annotation
;
3120 inst
->insert_before(block
, setup
);
3122 /* Similarly, this will only populate the first 4 channels of the
3123 * result register (since we only use smear values from 0-3), but we
3124 * don't tell the optimizer.
3126 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3127 inst
->src
[1] = payload
;
3128 inst
->base_mrf
= -1;
3130 invalidate_live_intervals();
3132 /* Before register allocation, we didn't tell the scheduler about the
3133 * MRF we use. We know it's safe to use this MRF because nothing
3134 * else does except for register spill/unspill, which generates and
3135 * uses its MRF within a single IR instruction.
3137 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3144 fs_visitor::lower_load_payload()
3146 bool progress
= false;
3148 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3149 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3152 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3153 assert(inst
->saturate
== false);
3154 fs_reg dst
= inst
->dst
;
3156 /* Get rid of COMPR4. We'll add it back in if we need it */
3157 if (dst
.file
== MRF
)
3158 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3160 const fs_builder
ibld(this, block
, inst
);
3161 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3163 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3164 if (inst
->src
[i
].file
!= BAD_FILE
) {
3165 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3166 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3167 hbld
.MOV(mov_dst
, mov_src
);
3169 dst
= offset(dst
, hbld
, 1);
3172 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3173 inst
->exec_size
> 8) {
3174 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3175 * a straightforward copy. Instead, the result of the
3176 * LOAD_PAYLOAD is treated as interleaved and the first four
3177 * non-header sources are unpacked as:
3188 * This is used for gen <= 5 fb writes.
3190 assert(inst
->exec_size
== 16);
3191 assert(inst
->header_size
+ 4 <= inst
->sources
);
3192 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3193 if (inst
->src
[i
].file
!= BAD_FILE
) {
3194 if (devinfo
->has_compr4
) {
3195 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3196 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3197 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3199 /* Platform doesn't have COMPR4. We have to fake it */
3200 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3201 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3203 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3210 /* The loop above only ever incremented us through the first set
3211 * of 4 registers. However, thanks to the magic of COMPR4, we
3212 * actually wrote to the first 8 registers, so we need to take
3213 * that into account now.
3217 /* The COMPR4 code took care of the first 4 sources. We'll let
3218 * the regular path handle any remaining sources. Yes, we are
3219 * modifying the instruction but we're about to delete it so
3220 * this really doesn't hurt anything.
3222 inst
->header_size
+= 4;
3225 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3226 if (inst
->src
[i
].file
!= BAD_FILE
)
3227 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3228 dst
= offset(dst
, ibld
, 1);
3231 inst
->remove(block
);
3236 invalidate_live_intervals();
3242 fs_visitor::lower_integer_multiplication()
3244 bool progress
= false;
3246 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3247 const fs_builder
ibld(this, block
, inst
);
3249 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3250 if (inst
->dst
.is_accumulator() ||
3251 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3252 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3255 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3256 * operation directly, but CHV/BXT cannot.
3258 if (devinfo
->gen
>= 8 &&
3259 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3262 if (inst
->src
[1].file
== IMM
&&
3263 inst
->src
[1].ud
< (1 << 16)) {
3264 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3265 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3268 * If multiplying by an immediate value that fits in 16-bits, do a
3269 * single MUL instruction with that value in the proper location.
3271 if (devinfo
->gen
< 7) {
3272 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3274 ibld
.MOV(imm
, inst
->src
[1]);
3275 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3277 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3280 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3281 * do 32-bit integer multiplication in one instruction, but instead
3282 * must do a sequence (which actually calculates a 64-bit result):
3284 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3285 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3286 * mov(8) g2<1>D acc0<8,8,1>D
3288 * But on Gen > 6, the ability to use second accumulator register
3289 * (acc1) for non-float data types was removed, preventing a simple
3290 * implementation in SIMD16. A 16-channel result can be calculated by
3291 * executing the three instructions twice in SIMD8, once with quarter
3292 * control of 1Q for the first eight channels and again with 2Q for
3293 * the second eight channels.
3295 * Which accumulator register is implicitly accessed (by AccWrEnable
3296 * for instance) is determined by the quarter control. Unfortunately
3297 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3298 * implicit accumulator access by an instruction with 2Q will access
3299 * acc1 regardless of whether the data type is usable in acc1.
3301 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3302 * integer data types.
3304 * Since we only want the low 32-bits of the result, we can do two
3305 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3306 * adjust the high result and add them (like the mach is doing):
3308 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3309 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3310 * shl(8) g9<1>D g8<8,8,1>D 16D
3311 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3313 * We avoid the shl instruction by realizing that we only want to add
3314 * the low 16-bits of the "high" result to the high 16-bits of the
3315 * "low" result and using proper regioning on the add:
3317 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3318 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3319 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3321 * Since it does not use the (single) accumulator register, we can
3322 * schedule multi-component multiplications much better.
3325 fs_reg orig_dst
= inst
->dst
;
3326 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3327 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3330 fs_reg low
= inst
->dst
;
3331 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3334 if (devinfo
->gen
>= 7) {
3335 fs_reg src1_0_w
= inst
->src
[1];
3336 fs_reg src1_1_w
= inst
->src
[1];
3338 if (inst
->src
[1].file
== IMM
) {
3339 src1_0_w
.ud
&= 0xffff;
3342 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3343 if (src1_0_w
.stride
!= 0) {
3344 assert(src1_0_w
.stride
== 1);
3345 src1_0_w
.stride
= 2;
3348 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3349 if (src1_1_w
.stride
!= 0) {
3350 assert(src1_1_w
.stride
== 1);
3351 src1_1_w
.stride
= 2;
3353 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3355 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3356 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3358 fs_reg src0_0_w
= inst
->src
[0];
3359 fs_reg src0_1_w
= inst
->src
[0];
3361 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3362 if (src0_0_w
.stride
!= 0) {
3363 assert(src0_0_w
.stride
== 1);
3364 src0_0_w
.stride
= 2;
3367 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3368 if (src0_1_w
.stride
!= 0) {
3369 assert(src0_1_w
.stride
== 1);
3370 src0_1_w
.stride
= 2;
3372 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3374 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3375 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3378 fs_reg dst
= inst
->dst
;
3379 dst
.type
= BRW_REGISTER_TYPE_UW
;
3380 dst
.subreg_offset
= 2;
3383 high
.type
= BRW_REGISTER_TYPE_UW
;
3386 low
.type
= BRW_REGISTER_TYPE_UW
;
3387 low
.subreg_offset
= 2;
3390 ibld
.ADD(dst
, low
, high
);
3392 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3393 set_condmod(inst
->conditional_mod
,
3394 ibld
.MOV(orig_dst
, inst
->dst
));
3398 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3399 /* Should have been lowered to 8-wide. */
3400 assert(inst
->exec_size
<= 8);
3401 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3403 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3404 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3406 if (devinfo
->gen
>= 8) {
3407 /* Until Gen8, integer multiplies read 32-bits from one source,
3408 * and 16-bits from the other, and relying on the MACH instruction
3409 * to generate the high bits of the result.
3411 * On Gen8, the multiply instruction does a full 32x32-bit
3412 * multiply, but in order to do a 64-bit multiply we can simulate
3413 * the previous behavior and then use a MACH instruction.
3415 * FINISHME: Don't use source modifiers on src1.
3417 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3418 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3419 mul
->src
[1].type
= (type_is_signed(mul
->src
[1].type
) ?
3420 BRW_REGISTER_TYPE_W
: BRW_REGISTER_TYPE_UW
);
3421 mul
->src
[1].stride
*= 2;
3423 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3424 inst
->force_sechalf
) {
3425 /* Among other things the quarter control bits influence which
3426 * accumulator register is used by the hardware for instructions
3427 * that access the accumulator implicitly (e.g. MACH). A
3428 * second-half instruction would normally map to acc1, which
3429 * doesn't exist on Gen7 and up (the hardware does emulate it for
3430 * floating-point instructions *only* by taking advantage of the
3431 * extra precision of acc0 not normally used for floating point
3434 * HSW and up are careful enough not to try to access an
3435 * accumulator register that doesn't exist, but on earlier Gen7
3436 * hardware we need to make sure that the quarter control bits are
3437 * zero to avoid non-deterministic behaviour and emit an extra MOV
3438 * to get the result masked correctly according to the current
3441 mach
->force_sechalf
= false;
3442 mach
->force_writemask_all
= true;
3443 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3444 ibld
.MOV(inst
->dst
, mach
->dst
);
3450 inst
->remove(block
);
3455 invalidate_live_intervals();
3461 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3462 fs_reg
*dst
, fs_reg color
, unsigned components
)
3464 if (key
->clamp_fragment_color
) {
3465 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3466 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3468 for (unsigned i
= 0; i
< components
; i
++)
3470 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3475 for (unsigned i
= 0; i
< components
; i
++)
3476 dst
[i
] = offset(color
, bld
, i
);
3480 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3481 const brw_wm_prog_data
*prog_data
,
3482 const brw_wm_prog_key
*key
,
3483 const fs_visitor::thread_payload
&payload
)
3485 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3486 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3487 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3488 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3489 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3490 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3491 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3492 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3493 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3494 const unsigned components
=
3495 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3497 /* We can potentially have a message length of up to 15, so we have to set
3498 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3501 int header_size
= 2, payload_header_size
;
3502 unsigned length
= 0;
3504 /* From the Sandy Bridge PRM, volume 4, page 198:
3506 * "Dispatched Pixel Enables. One bit per pixel indicating
3507 * which pixels were originally enabled when the thread was
3508 * dispatched. This field is only required for the end-of-
3509 * thread message and on all dual-source messages."
3511 if (devinfo
->gen
>= 6 &&
3512 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3513 color1
.file
== BAD_FILE
&&
3514 key
->nr_color_regions
== 1) {
3518 if (header_size
!= 0) {
3519 assert(header_size
== 2);
3520 /* Allocate 2 registers for a header */
3524 if (payload
.aa_dest_stencil_reg
) {
3525 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3526 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3527 .MOV(sources
[length
],
3528 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3532 if (prog_data
->uses_omask
) {
3533 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3534 BRW_REGISTER_TYPE_UD
);
3536 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3537 * relevant. Since it's unsigned single words one vgrf is always
3538 * 16-wide, but only the lower or higher 8 channels will be used by the
3539 * hardware when doing a SIMD8 write depending on whether we have
3540 * selected the subspans for the first or second half respectively.
3542 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3543 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3544 sample_mask
.stride
*= 2;
3546 bld
.exec_all().annotate("FB write oMask")
3547 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3548 inst
->force_sechalf
),
3553 payload_header_size
= length
;
3555 if (src0_alpha
.file
!= BAD_FILE
) {
3556 /* FIXME: This is being passed at the wrong location in the payload and
3557 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3558 * It's supposed to be immediately before oMask but there seems to be no
3559 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3560 * requires header sources to form a contiguous segment at the beginning
3561 * of the message and src0_alpha has per-channel semantics.
3563 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3567 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3570 if (color1
.file
!= BAD_FILE
) {
3571 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3575 if (src_depth
.file
!= BAD_FILE
) {
3576 sources
[length
] = src_depth
;
3580 if (dst_depth
.file
!= BAD_FILE
) {
3581 sources
[length
] = dst_depth
;
3585 if (src_stencil
.file
!= BAD_FILE
) {
3586 assert(devinfo
->gen
>= 9);
3587 assert(bld
.dispatch_width() != 16);
3589 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3590 * available on gen9+. As such it's impossible to have both enabled at the
3591 * same time and therefore length cannot overrun the array.
3593 assert(length
< 15);
3595 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3596 bld
.exec_all().annotate("FB write OS")
3597 .emit(FS_OPCODE_PACK_STENCIL_REF
, sources
[length
],
3598 retype(src_stencil
, BRW_REGISTER_TYPE_UB
));
3603 if (devinfo
->gen
>= 7) {
3604 /* Send from the GRF */
3605 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3606 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3607 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3608 load
->dst
= payload
;
3610 inst
->src
[0] = payload
;
3611 inst
->resize_sources(1);
3612 inst
->base_mrf
= -1;
3614 /* Send from the MRF */
3615 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3616 sources
, length
, payload_header_size
);
3618 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3619 * will do this for us if we just give it a COMPR4 destination.
3621 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3622 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3624 inst
->resize_sources(0);
3628 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3629 inst
->mlen
= load
->regs_written
;
3630 inst
->header_size
= header_size
;
3634 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3635 const fs_reg
&coordinate
,
3636 const fs_reg
&shadow_c
,
3637 const fs_reg
&lod
, const fs_reg
&lod2
,
3638 const fs_reg
&sampler
,
3639 unsigned coord_components
,
3640 unsigned grad_components
)
3642 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3643 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3644 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3645 fs_reg msg_end
= msg_begin
;
3648 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3650 for (unsigned i
= 0; i
< coord_components
; i
++)
3651 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3652 offset(coordinate
, bld
, i
));
3654 msg_end
= offset(msg_end
, bld
, coord_components
);
3656 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3657 * require all three components to be present and zero if they are unused.
3659 if (coord_components
> 0 &&
3660 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3661 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3662 for (unsigned i
= coord_components
; i
< 3; i
++)
3663 bld
.MOV(offset(msg_end
, bld
, i
), fs_reg(0.0f
));
3665 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3668 if (op
== SHADER_OPCODE_TXD
) {
3669 /* TXD unsupported in SIMD16 mode. */
3670 assert(bld
.dispatch_width() == 8);
3672 /* the slots for u and v are always present, but r is optional */
3673 if (coord_components
< 2)
3674 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3677 * dPdx = dudx, dvdx, drdx
3678 * dPdy = dudy, dvdy, drdy
3680 * 1-arg: Does not exist.
3682 * 2-arg: dudx dvdx dudy dvdy
3683 * dPdx.x dPdx.y dPdy.x dPdy.y
3686 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3687 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3688 * m5 m6 m7 m8 m9 m10
3690 for (unsigned i
= 0; i
< grad_components
; i
++)
3691 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3693 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3695 for (unsigned i
= 0; i
< grad_components
; i
++)
3696 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3698 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3702 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3703 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3705 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3706 bld
.dispatch_width() == 16);
3708 const brw_reg_type type
=
3709 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3710 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3711 bld
.MOV(retype(msg_end
, type
), lod
);
3712 msg_end
= offset(msg_end
, bld
, 1);
3715 if (shadow_c
.file
!= BAD_FILE
) {
3716 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3717 /* There's no plain shadow compare message, so we use shadow
3718 * compare with a bias of 0.0.
3720 bld
.MOV(msg_end
, fs_reg(0.0f
));
3721 msg_end
= offset(msg_end
, bld
, 1);
3724 bld
.MOV(msg_end
, shadow_c
);
3725 msg_end
= offset(msg_end
, bld
, 1);
3729 inst
->src
[0] = reg_undef
;
3730 inst
->src
[1] = sampler
;
3731 inst
->resize_sources(2);
3732 inst
->base_mrf
= msg_begin
.nr
;
3733 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3734 inst
->header_size
= 1;
3738 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3740 const fs_reg
&shadow_c
,
3741 fs_reg lod
, fs_reg lod2
,
3742 const fs_reg
&sample_index
,
3743 const fs_reg
&sampler
,
3744 const fs_reg
&offset_value
,
3745 unsigned coord_components
,
3746 unsigned grad_components
)
3748 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3749 fs_reg msg_coords
= message
;
3750 unsigned header_size
= 0;
3752 if (offset_value
.file
!= BAD_FILE
) {
3753 /* The offsets set up by the visitor are in the m1 header, so we can't
3760 for (unsigned i
= 0; i
< coord_components
; i
++) {
3761 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3762 coordinate
= offset(coordinate
, bld
, 1);
3764 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3765 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3767 if (shadow_c
.file
!= BAD_FILE
) {
3768 fs_reg msg_shadow
= msg_lod
;
3769 bld
.MOV(msg_shadow
, shadow_c
);
3770 msg_lod
= offset(msg_shadow
, bld
, 1);
3775 case SHADER_OPCODE_TXL
:
3777 bld
.MOV(msg_lod
, lod
);
3778 msg_end
= offset(msg_lod
, bld
, 1);
3780 case SHADER_OPCODE_TXD
:
3783 * dPdx = dudx, dvdx, drdx
3784 * dPdy = dudy, dvdy, drdy
3786 * Load up these values:
3787 * - dudx dudy dvdx dvdy drdx drdy
3788 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3791 for (unsigned i
= 0; i
< grad_components
; i
++) {
3792 bld
.MOV(msg_end
, lod
);
3793 lod
= offset(lod
, bld
, 1);
3794 msg_end
= offset(msg_end
, bld
, 1);
3796 bld
.MOV(msg_end
, lod2
);
3797 lod2
= offset(lod2
, bld
, 1);
3798 msg_end
= offset(msg_end
, bld
, 1);
3801 case SHADER_OPCODE_TXS
:
3802 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3803 bld
.MOV(msg_lod
, lod
);
3804 msg_end
= offset(msg_lod
, bld
, 1);
3806 case SHADER_OPCODE_TXF
:
3807 msg_lod
= offset(msg_coords
, bld
, 3);
3808 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3809 msg_end
= offset(msg_lod
, bld
, 1);
3811 case SHADER_OPCODE_TXF_CMS
:
3812 msg_lod
= offset(msg_coords
, bld
, 3);
3814 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u));
3816 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3817 msg_end
= offset(msg_lod
, bld
, 2);
3824 inst
->src
[0] = reg_undef
;
3825 inst
->src
[1] = sampler
;
3826 inst
->resize_sources(2);
3827 inst
->base_mrf
= message
.nr
;
3828 inst
->mlen
= msg_end
.nr
- message
.nr
;
3829 inst
->header_size
= header_size
;
3831 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3832 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3836 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3838 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3841 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
3845 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3847 const fs_reg
&shadow_c
,
3848 fs_reg lod
, fs_reg lod2
,
3849 const fs_reg
&sample_index
,
3850 const fs_reg
&mcs
, const fs_reg
&sampler
,
3851 fs_reg offset_value
,
3852 unsigned coord_components
,
3853 unsigned grad_components
)
3855 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3856 int reg_width
= bld
.dispatch_width() / 8;
3857 unsigned header_size
= 0, length
= 0;
3858 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3859 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3860 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3862 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3863 offset_value
.file
!= BAD_FILE
||
3864 is_high_sampler(devinfo
, sampler
)) {
3865 /* For general texture offsets (no txf workaround), we need a header to
3866 * put them in. Note that we're only reserving space for it in the
3867 * message payload as it will be initialized implicitly by the
3870 * TG4 needs to place its channel select in the header, for interaction
3871 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3872 * larger sampler numbers we need to offset the Sampler State Pointer in
3876 sources
[0] = fs_reg();
3880 if (shadow_c
.file
!= BAD_FILE
) {
3881 bld
.MOV(sources
[length
], shadow_c
);
3885 bool coordinate_done
= false;
3887 /* The sampler can only meaningfully compute LOD for fragment shader
3888 * messages. For all other stages, we change the opcode to TXL and
3889 * hardcode the LOD to 0.
3891 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3892 op
== SHADER_OPCODE_TEX
) {
3893 op
= SHADER_OPCODE_TXL
;
3897 /* Set up the LOD info */
3900 case SHADER_OPCODE_TXL
:
3901 bld
.MOV(sources
[length
], lod
);
3904 case SHADER_OPCODE_TXD
:
3905 /* TXD should have been lowered in SIMD16 mode. */
3906 assert(bld
.dispatch_width() == 8);
3908 /* Load dPdx and the coordinate together:
3909 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3911 for (unsigned i
= 0; i
< coord_components
; i
++) {
3912 bld
.MOV(sources
[length
], coordinate
);
3913 coordinate
= offset(coordinate
, bld
, 1);
3916 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3917 * only derivatives for (u, v, r).
3919 if (i
< grad_components
) {
3920 bld
.MOV(sources
[length
], lod
);
3921 lod
= offset(lod
, bld
, 1);
3924 bld
.MOV(sources
[length
], lod2
);
3925 lod2
= offset(lod2
, bld
, 1);
3930 coordinate_done
= true;
3932 case SHADER_OPCODE_TXS
:
3933 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
3936 case SHADER_OPCODE_TXF
:
3937 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
3938 * On Gen9 they are u, v, lod, r
3940 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3941 coordinate
= offset(coordinate
, bld
, 1);
3944 if (devinfo
->gen
>= 9) {
3945 if (coord_components
>= 2) {
3946 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3947 coordinate
= offset(coordinate
, bld
, 1);
3952 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
3955 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
3956 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3957 coordinate
= offset(coordinate
, bld
, 1);
3961 coordinate_done
= true;
3963 case SHADER_OPCODE_TXF_CMS
:
3964 case SHADER_OPCODE_TXF_CMS_W
:
3965 case SHADER_OPCODE_TXF_UMS
:
3966 case SHADER_OPCODE_TXF_MCS
:
3967 if (op
== SHADER_OPCODE_TXF_UMS
||
3968 op
== SHADER_OPCODE_TXF_CMS
||
3969 op
== SHADER_OPCODE_TXF_CMS_W
) {
3970 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
3974 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
3975 /* Data from the multisample control surface. */
3976 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
3979 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
3982 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
3983 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
3986 offset(mcs
, bld
, 1));
3991 /* There is no offsetting for this message; just copy in the integer
3992 * texture coordinates.
3994 for (unsigned i
= 0; i
< coord_components
; i
++) {
3995 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3996 coordinate
= offset(coordinate
, bld
, 1);
4000 coordinate_done
= true;
4002 case SHADER_OPCODE_TG4_OFFSET
:
4003 /* gather4_po_c should have been lowered in SIMD16 mode. */
4004 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
4006 /* More crazy intermixing */
4007 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
4008 bld
.MOV(sources
[length
], coordinate
);
4009 coordinate
= offset(coordinate
, bld
, 1);
4013 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
4014 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
4015 offset_value
= offset(offset_value
, bld
, 1);
4019 if (coord_components
== 3) { /* r if present */
4020 bld
.MOV(sources
[length
], coordinate
);
4021 coordinate
= offset(coordinate
, bld
, 1);
4025 coordinate_done
= true;
4031 /* Set up the coordinate (except for cases where it was done above) */
4032 if (!coordinate_done
) {
4033 for (unsigned i
= 0; i
< coord_components
; i
++) {
4034 bld
.MOV(sources
[length
], coordinate
);
4035 coordinate
= offset(coordinate
, bld
, 1);
4042 mlen
= length
* reg_width
- header_size
;
4044 mlen
= length
* reg_width
;
4046 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4047 BRW_REGISTER_TYPE_F
);
4048 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4050 /* Generate the SEND. */
4052 inst
->src
[0] = src_payload
;
4053 inst
->src
[1] = sampler
;
4054 inst
->resize_sources(2);
4055 inst
->base_mrf
= -1;
4057 inst
->header_size
= header_size
;
4059 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4060 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4064 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4066 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4067 const fs_reg
&coordinate
= inst
->src
[0];
4068 const fs_reg
&shadow_c
= inst
->src
[1];
4069 const fs_reg
&lod
= inst
->src
[2];
4070 const fs_reg
&lod2
= inst
->src
[3];
4071 const fs_reg
&sample_index
= inst
->src
[4];
4072 const fs_reg
&mcs
= inst
->src
[5];
4073 const fs_reg
&sampler
= inst
->src
[6];
4074 const fs_reg
&offset_value
= inst
->src
[7];
4075 assert(inst
->src
[8].file
== IMM
&& inst
->src
[9].file
== IMM
);
4076 const unsigned coord_components
= inst
->src
[8].ud
;
4077 const unsigned grad_components
= inst
->src
[9].ud
;
4079 if (devinfo
->gen
>= 7) {
4080 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4081 shadow_c
, lod
, lod2
, sample_index
,
4082 mcs
, sampler
, offset_value
,
4083 coord_components
, grad_components
);
4084 } else if (devinfo
->gen
>= 5) {
4085 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4086 shadow_c
, lod
, lod2
, sample_index
,
4087 sampler
, offset_value
,
4088 coord_components
, grad_components
);
4090 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4091 shadow_c
, lod
, lod2
, sampler
,
4092 coord_components
, grad_components
);
4097 * Initialize the header present in some typed and untyped surface
4101 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4103 fs_builder ubld
= bld
.exec_all().group(8, 0);
4104 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4105 ubld
.MOV(dst
, fs_reg(0));
4106 ubld
.MOV(component(dst
, 7), sample_mask
);
4111 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4112 const fs_reg
&sample_mask
)
4114 /* Get the logical send arguments. */
4115 const fs_reg
&addr
= inst
->src
[0];
4116 const fs_reg
&src
= inst
->src
[1];
4117 const fs_reg
&surface
= inst
->src
[2];
4118 const UNUSED fs_reg
&dims
= inst
->src
[3];
4119 const fs_reg
&arg
= inst
->src
[4];
4121 /* Calculate the total number of components of the payload. */
4122 const unsigned addr_sz
= inst
->components_read(0);
4123 const unsigned src_sz
= inst
->components_read(1);
4124 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4125 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4127 /* Allocate space for the payload. */
4128 fs_reg
*const components
= new fs_reg
[sz
];
4129 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4132 /* Construct the payload. */
4134 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4136 for (unsigned i
= 0; i
< addr_sz
; i
++)
4137 components
[n
++] = offset(addr
, bld
, i
);
4139 for (unsigned i
= 0; i
< src_sz
; i
++)
4140 components
[n
++] = offset(src
, bld
, i
);
4142 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4144 /* Update the original instruction. */
4146 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4147 inst
->header_size
= header_sz
;
4149 inst
->src
[0] = payload
;
4150 inst
->src
[1] = surface
;
4152 inst
->resize_sources(3);
4154 delete[] components
;
4158 fs_visitor::lower_logical_sends()
4160 bool progress
= false;
4162 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4163 const fs_builder
ibld(this, block
, inst
);
4165 switch (inst
->opcode
) {
4166 case FS_OPCODE_FB_WRITE_LOGICAL
:
4167 assert(stage
== MESA_SHADER_FRAGMENT
);
4168 lower_fb_write_logical_send(ibld
, inst
,
4169 (const brw_wm_prog_data
*)prog_data
,
4170 (const brw_wm_prog_key
*)key
,
4174 case SHADER_OPCODE_TEX_LOGICAL
:
4175 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4178 case SHADER_OPCODE_TXD_LOGICAL
:
4179 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4182 case SHADER_OPCODE_TXF_LOGICAL
:
4183 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4186 case SHADER_OPCODE_TXL_LOGICAL
:
4187 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4190 case SHADER_OPCODE_TXS_LOGICAL
:
4191 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4194 case FS_OPCODE_TXB_LOGICAL
:
4195 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4198 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4199 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4202 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4203 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4206 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4207 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4210 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4211 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4214 case SHADER_OPCODE_LOD_LOGICAL
:
4215 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4218 case SHADER_OPCODE_TG4_LOGICAL
:
4219 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4222 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4223 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4226 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4227 lower_surface_logical_send(ibld
, inst
,
4228 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4232 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4233 lower_surface_logical_send(ibld
, inst
,
4234 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4235 ibld
.sample_mask_reg());
4238 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4239 lower_surface_logical_send(ibld
, inst
,
4240 SHADER_OPCODE_UNTYPED_ATOMIC
,
4241 ibld
.sample_mask_reg());
4244 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4245 lower_surface_logical_send(ibld
, inst
,
4246 SHADER_OPCODE_TYPED_SURFACE_READ
,
4250 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4251 lower_surface_logical_send(ibld
, inst
,
4252 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4253 ibld
.sample_mask_reg());
4256 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4257 lower_surface_logical_send(ibld
, inst
,
4258 SHADER_OPCODE_TYPED_ATOMIC
,
4259 ibld
.sample_mask_reg());
4270 invalidate_live_intervals();
4276 * Get the closest native SIMD width supported by the hardware for instruction
4277 * \p inst. The instruction will be left untouched by
4278 * fs_visitor::lower_simd_width() if the returned value is equal to the
4279 * original execution size.
4282 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4283 const fs_inst
*inst
)
4285 switch (inst
->opcode
) {
4286 case BRW_OPCODE_MOV
:
4287 case BRW_OPCODE_SEL
:
4288 case BRW_OPCODE_NOT
:
4289 case BRW_OPCODE_AND
:
4291 case BRW_OPCODE_XOR
:
4292 case BRW_OPCODE_SHR
:
4293 case BRW_OPCODE_SHL
:
4294 case BRW_OPCODE_ASR
:
4295 case BRW_OPCODE_CMP
:
4296 case BRW_OPCODE_CMPN
:
4297 case BRW_OPCODE_CSEL
:
4298 case BRW_OPCODE_F32TO16
:
4299 case BRW_OPCODE_F16TO32
:
4300 case BRW_OPCODE_BFREV
:
4301 case BRW_OPCODE_BFE
:
4302 case BRW_OPCODE_BFI1
:
4303 case BRW_OPCODE_BFI2
:
4304 case BRW_OPCODE_ADD
:
4305 case BRW_OPCODE_MUL
:
4306 case BRW_OPCODE_AVG
:
4307 case BRW_OPCODE_FRC
:
4308 case BRW_OPCODE_RNDU
:
4309 case BRW_OPCODE_RNDD
:
4310 case BRW_OPCODE_RNDE
:
4311 case BRW_OPCODE_RNDZ
:
4312 case BRW_OPCODE_LZD
:
4313 case BRW_OPCODE_FBH
:
4314 case BRW_OPCODE_FBL
:
4315 case BRW_OPCODE_CBIT
:
4316 case BRW_OPCODE_SAD2
:
4317 case BRW_OPCODE_MAD
:
4318 case BRW_OPCODE_LRP
:
4319 case SHADER_OPCODE_RCP
:
4320 case SHADER_OPCODE_RSQ
:
4321 case SHADER_OPCODE_SQRT
:
4322 case SHADER_OPCODE_EXP2
:
4323 case SHADER_OPCODE_LOG2
:
4324 case SHADER_OPCODE_POW
:
4325 case SHADER_OPCODE_INT_QUOTIENT
:
4326 case SHADER_OPCODE_INT_REMAINDER
:
4327 case SHADER_OPCODE_SIN
:
4328 case SHADER_OPCODE_COS
: {
4329 /* According to the PRMs:
4330 * "A. In Direct Addressing mode, a source cannot span more than 2
4331 * adjacent GRF registers.
4332 * B. A destination cannot span more than 2 adjacent GRF registers."
4334 * Look for the source or destination with the largest register region
4335 * which is the one that is going to limit the overal execution size of
4336 * the instruction due to this rule.
4338 unsigned reg_count
= inst
->regs_written
;
4340 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4341 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4343 /* Calculate the maximum execution size of the instruction based on the
4344 * factor by which it goes over the hardware limit of 2 GRFs.
4346 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4348 case SHADER_OPCODE_MULH
:
4349 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4350 * is 8-wide on Gen7+.
4352 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4354 case FS_OPCODE_FB_WRITE_LOGICAL
:
4355 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4358 assert(devinfo
->gen
!= 6 ||
4359 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4360 inst
->exec_size
== 8);
4361 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4362 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4363 8 : inst
->exec_size
);
4365 case SHADER_OPCODE_TXD_LOGICAL
:
4366 /* TXD is unsupported in SIMD16 mode. */
4369 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4370 /* gather4_po_c is unsupported in SIMD16 mode. */
4371 const fs_reg
&shadow_c
= inst
->src
[1];
4372 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4374 case SHADER_OPCODE_TXL_LOGICAL
:
4375 case FS_OPCODE_TXB_LOGICAL
: {
4376 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4377 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4378 * mode because the message exceeds the maximum length of 11.
4380 const fs_reg
&shadow_c
= inst
->src
[1];
4381 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4383 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4386 return inst
->exec_size
;
4388 case SHADER_OPCODE_TXF_LOGICAL
:
4389 case SHADER_OPCODE_TXS_LOGICAL
:
4390 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4391 * messages. Use SIMD16 instead.
4393 if (devinfo
->gen
== 4)
4396 return inst
->exec_size
;
4398 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4399 /* This opcode can take up to 6 arguments which means that in some
4400 * circumstances it can end up with a message that is too long in SIMD16
4403 const unsigned coord_components
= inst
->src
[8].ud
;
4404 /* First three arguments are the sample index and the two arguments for
4407 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
4410 return inst
->exec_size
;
4413 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4414 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4415 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4419 return inst
->exec_size
;
4424 * The \p rows array of registers represents a \p num_rows by \p num_columns
4425 * matrix in row-major order, write it in column-major order into the register
4426 * passed as destination. \p stride gives the separation between matrix
4427 * elements in the input in fs_builder::dispatch_width() units.
4430 emit_transpose(const fs_builder
&bld
,
4431 const fs_reg
&dst
, const fs_reg
*rows
,
4432 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4434 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4436 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4437 for (unsigned j
= 0; j
< num_rows
; ++j
)
4438 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4441 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4443 delete[] components
;
4447 fs_visitor::lower_simd_width()
4449 bool progress
= false;
4451 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4452 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4454 if (lower_width
!= inst
->exec_size
) {
4455 /* Builder matching the original instruction. We may also need to
4456 * emit an instruction of width larger than the original, set the
4457 * execution size of the builder to the highest of both for now so
4458 * we're sure that both cases can be handled.
4460 const fs_builder ibld
= bld
.at(block
, inst
)
4461 .exec_all(inst
->force_writemask_all
)
4462 .group(MAX2(inst
->exec_size
, lower_width
),
4463 inst
->force_sechalf
);
4465 /* Split the copies in chunks of the execution width of either the
4466 * original or the lowered instruction, whichever is lower.
4468 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4469 const unsigned n
= inst
->exec_size
/ copy_width
;
4470 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4471 inst
->dst
.component_size(inst
->exec_size
);
4474 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4475 !inst
->writes_accumulator
&& !inst
->mlen
);
4477 for (unsigned i
= 0; i
< n
; i
++) {
4478 /* Emit a copy of the original instruction with the lowered width.
4479 * If the EOT flag was set throw it away except for the last
4480 * instruction to avoid killing the thread prematurely.
4482 fs_inst split_inst
= *inst
;
4483 split_inst
.exec_size
= lower_width
;
4484 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4486 /* Select the correct channel enables for the i-th group, then
4487 * transform the sources and destination and emit the lowered
4490 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4492 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4493 if (inst
->src
[j
].file
!= BAD_FILE
&&
4494 !is_uniform(inst
->src
[j
])) {
4495 /* Get the i-th copy_width-wide chunk of the source. */
4496 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4497 const unsigned src_size
= inst
->components_read(j
);
4499 /* Use a trivial transposition to copy one every n
4500 * copy_width-wide components of the register into a
4501 * temporary passed as source to the lowered instruction.
4503 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4504 emit_transpose(lbld
.group(copy_width
, 0),
4505 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4509 if (inst
->regs_written
) {
4510 /* Allocate enough space to hold the result of the lowered
4511 * instruction and fix up the number of registers written.
4513 split_inst
.dst
= dsts
[i
] =
4514 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4515 split_inst
.regs_written
=
4516 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4520 lbld
.emit(split_inst
);
4523 if (inst
->regs_written
) {
4524 /* Distance between useful channels in the temporaries, skipping
4525 * garbage if the lowered instruction is wider than the original.
4527 const unsigned m
= lower_width
/ copy_width
;
4529 /* Interleave the components of the result from the lowered
4530 * instructions. We need to set exec_all() when copying more than
4531 * one half per component, because LOAD_PAYLOAD (in terms of which
4532 * emit_transpose is implemented) can only use the same channel
4533 * enable signals for all of its non-header sources.
4535 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4536 .group(copy_width
, 0),
4537 inst
->dst
, dsts
, n
, dst_size
, m
);
4540 inst
->remove(block
);
4546 invalidate_live_intervals();
4552 fs_visitor::dump_instructions()
4554 dump_instructions(NULL
);
4558 fs_visitor::dump_instructions(const char *name
)
4560 FILE *file
= stderr
;
4561 if (name
&& geteuid() != 0) {
4562 file
= fopen(name
, "w");
4568 calculate_register_pressure();
4569 int ip
= 0, max_pressure
= 0;
4570 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4571 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4572 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4573 dump_instruction(inst
, file
);
4576 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4579 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4580 fprintf(file
, "%4d: ", ip
++);
4581 dump_instruction(inst
, file
);
4585 if (file
!= stderr
) {
4591 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4593 dump_instruction(be_inst
, stderr
);
4597 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4599 fs_inst
*inst
= (fs_inst
*)be_inst
;
4601 if (inst
->predicate
) {
4602 fprintf(file
, "(%cf0.%d) ",
4603 inst
->predicate_inverse
? '-' : '+',
4607 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4609 fprintf(file
, ".sat");
4610 if (inst
->conditional_mod
) {
4611 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4612 if (!inst
->predicate
&&
4613 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4614 inst
->opcode
!= BRW_OPCODE_IF
&&
4615 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4616 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4619 fprintf(file
, "(%d) ", inst
->exec_size
);
4622 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4625 switch (inst
->dst
.file
) {
4627 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
4628 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
4629 inst
->dst
.subreg_offset
)
4630 fprintf(file
, "+%d.%d",
4631 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4634 fprintf(file
, "g%d", inst
->dst
.nr
);
4637 fprintf(file
, "m%d", inst
->dst
.nr
);
4640 fprintf(file
, "(null)");
4643 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4646 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4649 switch (inst
->dst
.nr
) {
4651 fprintf(file
, "null");
4653 case BRW_ARF_ADDRESS
:
4654 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
4656 case BRW_ARF_ACCUMULATOR
:
4657 fprintf(file
, "acc%d", inst
->dst
.subnr
);
4660 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4663 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4666 if (inst
->dst
.subnr
)
4667 fprintf(file
, "+%d", inst
->dst
.subnr
);
4670 unreachable("not reached");
4672 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4674 for (int i
= 0; i
< inst
->sources
; i
++) {
4675 if (inst
->src
[i
].negate
)
4677 if (inst
->src
[i
].abs
)
4679 switch (inst
->src
[i
].file
) {
4681 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
4682 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
4683 inst
->src
[i
].subreg_offset
)
4684 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4685 inst
->src
[i
].subreg_offset
);
4688 fprintf(file
, "g%d", inst
->src
[i
].nr
);
4691 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
4694 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
4697 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
4698 if (inst
->src
[i
].reladdr
) {
4699 fprintf(file
, "+reladdr");
4700 } else if (inst
->src
[i
].subreg_offset
) {
4701 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4702 inst
->src
[i
].subreg_offset
);
4706 fprintf(file
, "(null)");
4709 switch (inst
->src
[i
].type
) {
4710 case BRW_REGISTER_TYPE_F
:
4711 fprintf(file
, "%ff", inst
->src
[i
].f
);
4713 case BRW_REGISTER_TYPE_W
:
4714 case BRW_REGISTER_TYPE_D
:
4715 fprintf(file
, "%dd", inst
->src
[i
].d
);
4717 case BRW_REGISTER_TYPE_UW
:
4718 case BRW_REGISTER_TYPE_UD
:
4719 fprintf(file
, "%uu", inst
->src
[i
].ud
);
4721 case BRW_REGISTER_TYPE_VF
:
4722 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4723 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
4724 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
4725 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
4726 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
4729 fprintf(file
, "???");
4734 switch (inst
->src
[i
].nr
) {
4736 fprintf(file
, "null");
4738 case BRW_ARF_ADDRESS
:
4739 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
4741 case BRW_ARF_ACCUMULATOR
:
4742 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
4745 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4748 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4751 if (inst
->src
[i
].subnr
)
4752 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
4755 if (inst
->src
[i
].abs
)
4758 if (inst
->src
[i
].file
!= IMM
) {
4759 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4762 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4763 fprintf(file
, ", ");
4768 if (inst
->force_writemask_all
)
4769 fprintf(file
, "NoMask ");
4771 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4772 if (inst
->force_sechalf
)
4773 fprintf(file
, "2ndhalf ");
4775 fprintf(file
, "1sthalf ");
4778 fprintf(file
, "\n");
4782 * Possibly returns an instruction that set up @param reg.
4784 * Sometimes we want to take the result of some expression/variable
4785 * dereference tree and rewrite the instruction generating the result
4786 * of the tree. When processing the tree, we know that the
4787 * instructions generated are all writing temporaries that are dead
4788 * outside of this tree. So, if we have some instructions that write
4789 * a temporary, we're free to point that temp write somewhere else.
4791 * Note that this doesn't guarantee that the instruction generated
4792 * only reg -- it might be the size=4 destination of a texture instruction.
4795 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4800 end
->is_partial_write() ||
4802 !reg
.equals(end
->dst
)) {
4810 fs_visitor::setup_payload_gen6()
4813 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
4814 unsigned barycentric_interp_modes
=
4815 (stage
== MESA_SHADER_FRAGMENT
) ?
4816 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4818 assert(devinfo
->gen
>= 6);
4820 /* R0-1: masks, pixel X/Y coordinates. */
4821 payload
.num_regs
= 2;
4822 /* R2: only for 32-pixel dispatch.*/
4824 /* R3-26: barycentric interpolation coordinates. These appear in the
4825 * same order that they appear in the brw_wm_barycentric_interp_mode
4826 * enum. Each set of coordinates occupies 2 registers if dispatch width
4827 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4828 * appear if they were enabled using the "Barycentric Interpolation
4829 * Mode" bits in WM_STATE.
4831 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4832 if (barycentric_interp_modes
& (1 << i
)) {
4833 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4834 payload
.num_regs
+= 2;
4835 if (dispatch_width
== 16) {
4836 payload
.num_regs
+= 2;
4841 /* R27: interpolated depth if uses source depth */
4843 payload
.source_depth_reg
= payload
.num_regs
;
4845 if (dispatch_width
== 16) {
4846 /* R28: interpolated depth if not SIMD8. */
4850 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4852 payload
.source_w_reg
= payload
.num_regs
;
4854 if (dispatch_width
== 16) {
4855 /* R30: interpolated W if not SIMD8. */
4860 if (stage
== MESA_SHADER_FRAGMENT
) {
4861 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4862 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4863 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4864 /* R31: MSAA position offsets. */
4865 if (prog_data
->uses_pos_offset
) {
4866 payload
.sample_pos_reg
= payload
.num_regs
;
4871 /* R32: MSAA input coverage mask */
4872 if (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
4873 assert(devinfo
->gen
>= 7);
4874 payload
.sample_mask_in_reg
= payload
.num_regs
;
4876 if (dispatch_width
== 16) {
4877 /* R33: input coverage mask if not SIMD8. */
4882 /* R34-: bary for 32-pixel. */
4883 /* R58-59: interp W for 32-pixel. */
4885 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4886 source_depth_to_render_target
= true;
4891 fs_visitor::setup_vs_payload()
4893 /* R0: thread header, R1: urb handles */
4894 payload
.num_regs
= 2;
4898 * We are building the local ID push constant data using the simplest possible
4899 * method. We simply push the local IDs directly as they should appear in the
4900 * registers for the uvec3 gl_LocalInvocationID variable.
4902 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
4903 * registers worth of push constant space.
4905 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
4906 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
4909 * FINISHME: There are a few easy optimizations to consider.
4911 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
4912 * no need for using push constant space for that dimension.
4914 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
4915 * easily use 16-bit words rather than 32-bit dwords in the push constant
4918 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
4919 * conveying the data, and thereby reduce push constant usage.
4923 fs_visitor::setup_gs_payload()
4925 assert(stage
== MESA_SHADER_GEOMETRY
);
4927 struct brw_gs_prog_data
*gs_prog_data
=
4928 (struct brw_gs_prog_data
*) prog_data
;
4929 struct brw_vue_prog_data
*vue_prog_data
=
4930 (struct brw_vue_prog_data
*) prog_data
;
4932 /* R0: thread header, R1: output URB handles */
4933 payload
.num_regs
= 2;
4935 if (gs_prog_data
->include_primitive_id
) {
4936 /* R2: Primitive ID 0..7 */
4940 /* Use a maximum of 32 registers for push-model inputs. */
4941 const unsigned max_push_components
= 32;
4943 /* If pushing our inputs would take too many registers, reduce the URB read
4944 * length (which is in HWords, or 8 registers), and resort to pulling.
4946 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
4947 * have to multiply by VerticesIn to obtain the total storage requirement.
4949 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
4950 max_push_components
) {
4951 gs_prog_data
->base
.include_vue_handles
= true;
4953 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
4954 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
4956 vue_prog_data
->urb_read_length
=
4957 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
4962 fs_visitor::setup_cs_payload()
4964 assert(devinfo
->gen
>= 7);
4965 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
4967 payload
.num_regs
= 1;
4969 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
4970 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
4971 payload
.local_invocation_id_reg
= payload
.num_regs
;
4972 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
4977 fs_visitor::calculate_register_pressure()
4979 invalidate_live_intervals();
4980 calculate_live_intervals();
4982 unsigned num_instructions
= 0;
4983 foreach_block(block
, cfg
)
4984 num_instructions
+= block
->instructions
.length();
4986 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
4988 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
4989 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
4990 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
4995 fs_visitor::optimize()
4997 /* Start by validating the shader we currently have. */
5000 /* bld is the common builder object pointing at the end of the program we
5001 * used to translate it into i965 IR. For the optimization and lowering
5002 * passes coming next, any code added after the end of the program without
5003 * having explicitly called fs_builder::at() clearly points at a mistake.
5004 * Ideally optimization passes wouldn't be part of the visitor so they
5005 * wouldn't have access to bld at all, but they do, so just in case some
5006 * pass forgets to ask for a location explicitly set it to NULL here to
5007 * make it trip. The dispatch width is initialized to a bogus value to
5008 * make sure that optimizations set the execution controls explicitly to
5009 * match the code they are manipulating instead of relying on the defaults.
5011 bld
= fs_builder(this, 64);
5013 assign_constant_locations();
5014 demote_pull_constants();
5018 split_virtual_grfs();
5021 #define OPT(pass, args...) ({ \
5023 bool this_progress = pass(args); \
5025 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5026 char filename[64]; \
5027 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5028 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5030 backend_shader::dump_instructions(filename); \
5035 progress = progress || this_progress; \
5039 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5041 snprintf(filename
, 64, "%s%d-%s-00-start",
5042 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5044 backend_shader::dump_instructions(filename
);
5047 bool progress
= false;
5051 OPT(lower_simd_width
);
5052 OPT(lower_logical_sends
);
5059 OPT(remove_duplicate_mrf_writes
);
5063 OPT(opt_copy_propagate
);
5064 OPT(opt_predicated_break
, this);
5065 OPT(opt_cmod_propagation
);
5066 OPT(dead_code_eliminate
);
5067 OPT(opt_peephole_sel
);
5068 OPT(dead_control_flow_eliminate
, this);
5069 OPT(opt_register_renaming
);
5070 OPT(opt_redundant_discard_jumps
);
5071 OPT(opt_saturate_propagation
);
5072 OPT(opt_zero_samples
);
5073 OPT(register_coalesce
);
5074 OPT(compute_to_mrf
);
5075 OPT(eliminate_find_live_channel
);
5077 OPT(compact_virtual_grfs
);
5082 OPT(opt_sampler_eot
);
5084 if (OPT(lower_load_payload
)) {
5085 split_virtual_grfs();
5086 OPT(register_coalesce
);
5087 OPT(compute_to_mrf
);
5088 OPT(dead_code_eliminate
);
5091 OPT(opt_combine_constants
);
5092 OPT(lower_integer_multiplication
);
5094 lower_uniform_pull_constant_loads();
5100 * Three source instruction must have a GRF/MRF destination register.
5101 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5104 fs_visitor::fixup_3src_null_dest()
5106 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5107 if (inst
->is_3src() && inst
->dst
.is_null()) {
5108 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5115 fs_visitor::allocate_registers()
5117 bool allocated_without_spills
;
5119 static const enum instruction_scheduler_mode pre_modes
[] = {
5121 SCHEDULE_PRE_NON_LIFO
,
5125 /* Try each scheduling heuristic to see if it can successfully register
5126 * allocate without spilling. They should be ordered by decreasing
5127 * performance but increasing likelihood of allocating.
5129 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5130 schedule_instructions(pre_modes
[i
]);
5133 assign_regs_trivial();
5134 allocated_without_spills
= true;
5136 allocated_without_spills
= assign_regs(false);
5138 if (allocated_without_spills
)
5142 if (!allocated_without_spills
) {
5143 /* We assume that any spilling is worse than just dropping back to
5144 * SIMD8. There's probably actually some intermediate point where
5145 * SIMD16 with a couple of spills is still better.
5147 if (dispatch_width
== 16) {
5148 fail("Failure to register allocate. Reduce number of "
5149 "live scalar values to avoid this.");
5151 compiler
->shader_perf_log(log_data
,
5152 "%s shader triggered register spilling. "
5153 "Try reducing the number of live scalar "
5154 "values to improve performance.\n",
5158 /* Since we're out of heuristics, just go spill registers until we
5159 * get an allocation.
5161 while (!assign_regs(true)) {
5167 /* This must come after all optimization and register allocation, since
5168 * it inserts dead code that happens to have side effects, and it does
5169 * so based on the actual physical registers in use.
5171 insert_gen4_send_dependency_workarounds();
5176 schedule_instructions(SCHEDULE_POST
);
5178 if (last_scratch
> 0)
5179 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5183 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5185 assert(stage
== MESA_SHADER_VERTEX
);
5189 if (shader_time_index
>= 0)
5190 emit_shader_time_begin();
5197 compute_clip_distance(clip_planes
);
5201 if (shader_time_index
>= 0)
5202 emit_shader_time_end();
5208 assign_curb_setup();
5209 assign_vs_urb_setup();
5211 fixup_3src_null_dest();
5212 allocate_registers();
5218 fs_visitor::run_gs()
5220 assert(stage
== MESA_SHADER_GEOMETRY
);
5224 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
5226 if (gs_compile
->control_data_header_size_bits
> 0) {
5227 /* Create a VGRF to store accumulated control data bits. */
5228 this->control_data_bits
= vgrf(glsl_type::uint_type
);
5230 /* If we're outputting more than 32 control data bits, then EmitVertex()
5231 * will set control_data_bits to 0 after emitting the first vertex.
5232 * Otherwise, we need to initialize it to 0 here.
5234 if (gs_compile
->control_data_header_size_bits
<= 32) {
5235 const fs_builder abld
= bld
.annotate("initialize control data bits");
5236 abld
.MOV(this->control_data_bits
, fs_reg(0u));
5240 if (shader_time_index
>= 0)
5241 emit_shader_time_begin();
5245 emit_gs_thread_end();
5247 if (shader_time_index
>= 0)
5248 emit_shader_time_end();
5257 assign_curb_setup();
5258 assign_gs_urb_setup();
5260 fixup_3src_null_dest();
5261 allocate_registers();
5267 fs_visitor::run_fs(bool do_rep_send
)
5269 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5270 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
5272 assert(stage
== MESA_SHADER_FRAGMENT
);
5274 if (devinfo
->gen
>= 6)
5275 setup_payload_gen6();
5277 setup_payload_gen4();
5281 } else if (do_rep_send
) {
5282 assert(dispatch_width
== 16);
5283 emit_repclear_shader();
5285 if (shader_time_index
>= 0)
5286 emit_shader_time_begin();
5288 calculate_urb_setup();
5289 if (nir
->info
.inputs_read
> 0) {
5290 if (devinfo
->gen
< 6)
5291 emit_interpolation_setup_gen4();
5293 emit_interpolation_setup_gen6();
5296 /* We handle discards by keeping track of the still-live pixels in f0.1.
5297 * Initialize it with the dispatched pixels.
5299 if (wm_prog_data
->uses_kill
) {
5300 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5301 discard_init
->flag_subreg
= 1;
5304 /* Generate FS IR for main(). (the visitor only descends into
5305 * functions called "main").
5312 if (wm_prog_data
->uses_kill
)
5313 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5315 if (wm_key
->alpha_test_func
)
5320 if (shader_time_index
>= 0)
5321 emit_shader_time_end();
5327 assign_curb_setup();
5330 fixup_3src_null_dest();
5331 allocate_registers();
5337 if (dispatch_width
== 8)
5338 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5340 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5346 fs_visitor::run_cs()
5348 assert(stage
== MESA_SHADER_COMPUTE
);
5352 if (shader_time_index
>= 0)
5353 emit_shader_time_begin();
5360 emit_cs_terminate();
5362 if (shader_time_index
>= 0)
5363 emit_shader_time_end();
5369 assign_curb_setup();
5371 fixup_3src_null_dest();
5372 allocate_registers();
5381 * Return a bitfield where bit n is set if barycentric interpolation mode n
5382 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
5385 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
5386 bool shade_model_flat
,
5387 bool persample_shading
,
5388 const nir_shader
*shader
)
5390 unsigned barycentric_interp_modes
= 0;
5392 nir_foreach_variable(var
, &shader
->inputs
) {
5393 enum glsl_interp_qualifier interp_qualifier
=
5394 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5395 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
5396 bool is_sample
= var
->data
.sample
|| persample_shading
;
5397 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5398 (var
->data
.location
== VARYING_SLOT_COL1
);
5400 /* Ignore WPOS and FACE, because they don't require interpolation. */
5401 if (var
->data
.location
== VARYING_SLOT_POS
||
5402 var
->data
.location
== VARYING_SLOT_FACE
)
5405 /* Determine the set (or sets) of barycentric coordinates needed to
5406 * interpolate this variable. Note that when
5407 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
5408 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
5409 * for lit pixels, so we need both sets of barycentric coordinates.
5411 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
5413 barycentric_interp_modes
|=
5414 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
5415 } else if (is_sample
) {
5416 barycentric_interp_modes
|=
5417 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
5419 if ((!is_centroid
&& !is_sample
) ||
5420 devinfo
->needs_unlit_centroid_workaround
) {
5421 barycentric_interp_modes
|=
5422 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
5424 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
5425 (!(shade_model_flat
&& is_gl_Color
) &&
5426 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
5428 barycentric_interp_modes
|=
5429 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
5430 } else if (is_sample
) {
5431 barycentric_interp_modes
|=
5432 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
5434 if ((!is_centroid
&& !is_sample
) ||
5435 devinfo
->needs_unlit_centroid_workaround
) {
5436 barycentric_interp_modes
|=
5437 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
5442 return barycentric_interp_modes
;
5446 computed_depth_mode(const nir_shader
*shader
)
5448 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5449 switch (shader
->info
.fs
.depth_layout
) {
5450 case FRAG_DEPTH_LAYOUT_NONE
:
5451 case FRAG_DEPTH_LAYOUT_ANY
:
5452 return BRW_PSCDEPTH_ON
;
5453 case FRAG_DEPTH_LAYOUT_GREATER
:
5454 return BRW_PSCDEPTH_ON_GE
;
5455 case FRAG_DEPTH_LAYOUT_LESS
:
5456 return BRW_PSCDEPTH_ON_LE
;
5457 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
5458 return BRW_PSCDEPTH_OFF
;
5461 return BRW_PSCDEPTH_OFF
;
5465 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
5467 const struct brw_wm_prog_key
*key
,
5468 struct brw_wm_prog_data
*prog_data
,
5469 const nir_shader
*shader
,
5470 struct gl_program
*prog
,
5471 int shader_time_index8
, int shader_time_index16
,
5473 unsigned *final_assembly_size
,
5476 /* key->alpha_test_func means simulating alpha testing via discards,
5477 * so the shader definitely kills pixels.
5479 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
5480 prog_data
->uses_omask
=
5481 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
5482 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
5483 prog_data
->computed_stencil
=
5484 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
5486 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
5488 prog_data
->barycentric_interp_modes
=
5489 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
5491 key
->persample_shading
,
5494 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
,
5495 &prog_data
->base
, prog
, shader
, 8,
5496 shader_time_index8
);
5497 if (!v
.run_fs(false /* do_rep_send */)) {
5499 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
5504 cfg_t
*simd16_cfg
= NULL
;
5505 fs_visitor
v2(compiler
, log_data
, mem_ctx
, key
,
5506 &prog_data
->base
, prog
, shader
, 16,
5507 shader_time_index16
);
5508 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
5509 if (!v
.simd16_unsupported
) {
5510 /* Try a SIMD16 compile */
5511 v2
.import_uniforms(&v
);
5512 if (!v2
.run_fs(use_rep_send
)) {
5513 compiler
->shader_perf_log(log_data
,
5514 "SIMD16 shader failed to compile: %s",
5517 simd16_cfg
= v2
.cfg
;
5523 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || use_rep_send
;
5524 if ((no_simd8
|| compiler
->devinfo
->gen
< 5) && simd16_cfg
) {
5526 prog_data
->no_8
= true;
5529 prog_data
->no_8
= false;
5532 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
5533 v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
5535 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5536 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
5537 shader
->info
.label
? shader
->info
.label
:
5539 shader
->info
.name
));
5543 g
.generate_code(simd8_cfg
, 8);
5545 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5547 return g
.get_assembly(final_assembly_size
);
5551 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*prog_data
,
5552 void *buffer
, uint32_t threads
, uint32_t stride
)
5554 if (prog_data
->local_invocation_id_regs
== 0)
5557 /* 'stride' should be an integer number of registers, that is, a multiple
5560 assert(stride
% 32 == 0);
5562 unsigned x
= 0, y
= 0, z
= 0;
5563 for (unsigned t
= 0; t
< threads
; t
++) {
5564 uint32_t *param
= (uint32_t *) buffer
+ stride
* t
/ 4;
5566 for (unsigned i
= 0; i
< prog_data
->simd_size
; i
++) {
5567 param
[0 * prog_data
->simd_size
+ i
] = x
;
5568 param
[1 * prog_data
->simd_size
+ i
] = y
;
5569 param
[2 * prog_data
->simd_size
+ i
] = z
;
5572 if (x
== prog_data
->local_size
[0]) {
5575 if (y
== prog_data
->local_size
[1]) {
5578 if (z
== prog_data
->local_size
[2])
5587 fs_visitor::emit_cs_local_invocation_id_setup()
5589 assert(stage
== MESA_SHADER_COMPUTE
);
5591 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5593 struct brw_reg src
=
5594 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
5595 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
5597 src
.nr
+= dispatch_width
/ 8;
5598 bld
.MOV(offset(*reg
, bld
, 1), src
);
5599 src
.nr
+= dispatch_width
/ 8;
5600 bld
.MOV(offset(*reg
, bld
, 2), src
);
5606 fs_visitor::emit_cs_work_group_id_setup()
5608 assert(stage
== MESA_SHADER_COMPUTE
);
5610 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5612 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
5613 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
5614 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
5616 bld
.MOV(*reg
, r0_1
);
5617 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
5618 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
5624 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
5626 const struct brw_cs_prog_key
*key
,
5627 struct brw_cs_prog_data
*prog_data
,
5628 const nir_shader
*shader
,
5629 int shader_time_index
,
5630 unsigned *final_assembly_size
,
5633 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
5634 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
5635 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
5636 unsigned local_workgroup_size
=
5637 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
5638 shader
->info
.cs
.local_size
[2];
5640 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
5643 const char *fail_msg
= NULL
;
5645 /* Now the main event: Visit the shader IR and generate our CS IR for it.
5647 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5648 NULL
, /* Never used in core profile */
5649 shader
, 8, shader_time_index
);
5651 fail_msg
= v8
.fail_msg
;
5652 } else if (local_workgroup_size
<= 8 * max_cs_threads
) {
5654 prog_data
->simd_size
= 8;
5657 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5658 NULL
, /* Never used in core profile */
5659 shader
, 16, shader_time_index
);
5660 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
5661 !fail_msg
&& !v8
.simd16_unsupported
&&
5662 local_workgroup_size
<= 16 * max_cs_threads
) {
5663 /* Try a SIMD16 compile */
5664 v16
.import_uniforms(&v8
);
5665 if (!v16
.run_cs()) {
5666 compiler
->shader_perf_log(log_data
,
5667 "SIMD16 shader failed to compile: %s",
5671 "Couldn't generate SIMD16 program and not "
5672 "enough threads for SIMD8";
5676 prog_data
->simd_size
= 16;
5680 if (unlikely(cfg
== NULL
)) {
5683 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
5688 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
5689 v8
.promoted_constants
, v8
.runtime_check_aads_emit
, "CS");
5690 if (INTEL_DEBUG
& DEBUG_CS
) {
5691 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
5692 shader
->info
.label
? shader
->info
.label
:
5695 g
.enable_debug(name
);
5698 g
.generate_code(cfg
, prog_data
->simd_size
);
5700 return g
.get_assembly(final_assembly_size
);