src/mesa/drivers/dri/i965/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29
  30 #include "brw_shader.h"
  31
  32 extern "C" {
  33
  34 #include <sys/types.h>
  35
  36 #include "main/macros.h"
  37 #include "main/shaderobj.h"
  38 #include "main/uniforms.h"
  39 #include "program/prog_parameter.h"
  40 #include "program/prog_print.h"
  41 #include "program/prog_optimize.h"
  42 #include "util/register_allocate.h"
  43 #include "program/sampler.h"
  44 #include "program/hash_table.h"
  45 #include "brw_context.h"
  46 #include "brw_eu.h"
  47 #include "brw_wm.h"
  48 #include "brw_shader.h"
  49 #include "intel_asm_annotation.h"
  50 }
  51 #include "glsl/glsl_types.h"
  52 #include "glsl/ir.h"
  53
  54 #define MAX_SAMPLER_MESSAGE_SIZE 11
  55
  56 struct bblock_t;
  57 namespace {
  58    struct acp_entry;
  59 }
  60
  61 namespace brw {
  62    class fs_live_variables;
  63 }
  64
  65 class fs_visitor;
  66
  67 class fs_reg : public backend_reg {
  68 public:
  69    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  70
  71    void init();
  72
  73    fs_reg();
  74    explicit fs_reg(float f);
  75    explicit fs_reg(int32_t i);
  76    explicit fs_reg(uint32_t u);
  77    fs_reg(struct brw_reg fixed_hw_reg);
  78    fs_reg(enum register_file file, int reg);
  79    fs_reg(enum register_file file, int reg, enum brw_reg_type type);
  80    fs_reg(enum register_file file, int reg, enum brw_reg_type type, uint8_t width);
  81    fs_reg(fs_visitor *v, const struct glsl_type *type);
  82
  83    bool equals(const fs_reg &r) const;
  84    bool is_valid_3src() const;
  85    bool is_contiguous() const;
  86
  87    fs_reg &apply_stride(unsigned stride);
  88    /** Smear a channel of the reg to all channels. */
  89    fs_reg &set_smear(unsigned subreg);
  90
  91    /**
  92     * Offset in bytes from the start of the register.  Values up to a
  93     * backend_reg::reg_offset unit are valid.
  94     */
  95    int subreg_offset;
  96
  97    fs_reg *reladdr;
  98
  99    /**
 100     * The register width.  This indicates how many hardware values are
 101     * represented by each virtual value.  Valid values are 1, 8, or 16.
 102     * For immediate values, this is 1.  Most of the rest of the time, it
 103     * will be equal to the dispatch width.
 104     */
 105    uint8_t width;
 106
 107    /**
 108     * Returns the effective register width when used as a source in the
 109     * given instruction.  Registers such as uniforms and immediates
 110     * effectively take on the width of the instruction in which they are
 111     * used.
 112     */
 113    uint8_t effective_width(const fs_visitor *v) const;
 114
 115    /** Register region horizontal stride */
 116    uint8_t stride;
 117 };
 118
 119 static inline fs_reg
 120 retype(fs_reg reg, enum brw_reg_type type)
 121 {
 122    reg.fixed_hw_reg.type = reg.type = type;
 123    return reg;
 124 }
 125
 126 static inline fs_reg
 127 byte_offset(fs_reg reg, unsigned delta)
 128 {
 129    switch (reg.file) {
 130    case BAD_FILE:
 131       break;
 132    case GRF:
 133       reg.reg_offset += delta / 32;
 134       break;
 135    case MRF:
 136       reg.reg += delta / 32;
 137       break;
 138    default:
 139       assert(delta == 0);
 140    }
 141    reg.subreg_offset += delta % 32;
 142    return reg;
 143 }
 144
 145 static inline fs_reg
 146 offset(fs_reg reg, unsigned delta)
 147 {
 148    assert(reg.stride > 0);
 149    switch (reg.file) {
 150    case BAD_FILE:
 151       break;
 152    case GRF:
 153    case MRF:
 154       return byte_offset(reg, delta * reg.width * reg.stride * type_sz(reg.type));
 155    case UNIFORM:
 156       reg.reg_offset += delta;
 157       break;
 158    default:
 159       assert(delta == 0);
 160    }
 161    return reg;
 162 }
 163
 164 /**
 165  * Get either of the 8-component halves of a 16-component register.
 166  *
 167  * Note: this also works if \c reg represents a SIMD16 pair of registers.
 168  */
 169 static inline fs_reg
 170 half(fs_reg reg, unsigned idx)
 171 {
 172    assert(idx < 2);
 173    assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM));
 174    assert(reg.width == 16);
 175    reg.width = 8;
 176    return byte_offset(reg, 8 * idx * reg.stride * type_sz(reg.type));
 177 }
 178
 179 static const fs_reg reg_undef;
 180
 181 class ip_record : public exec_node {
 182 public:
 183    DECLARE_RALLOC_CXX_OPERATORS(ip_record)
 184
 185    ip_record(int ip)
 186    {
 187       this->ip = ip;
 188    }
 189
 190    int ip;
 191 };
 192
 193 class fs_inst : public backend_instruction {
 194    fs_inst &operator=(const fs_inst &);
 195
 196 public:
 197    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 198
 199    void init(enum opcode opcode, const fs_reg &dst, fs_reg *src, int sources);
 200
 201    fs_inst(enum opcode opcode = BRW_OPCODE_NOP, const fs_reg &dst = reg_undef);
 202    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 203    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 204            const fs_reg &src1);
 205    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 206            const fs_reg &src1, const fs_reg &src2);
 207    fs_inst(enum opcode opcode, const fs_reg &dst, fs_reg src[], int sources);
 208    fs_inst(const fs_inst &that);
 209
 210    void resize_sources(uint8_t num_sources);
 211
 212    bool equals(fs_inst *inst) const;
 213    bool overwrites_reg(const fs_reg &reg) const;
 214    bool is_send_from_grf() const;
 215    bool is_partial_write() const;
 216    int regs_read(fs_visitor *v, int arg) const;
 217    bool can_do_source_mods(struct brw_context *brw);
 218
 219    bool reads_flag() const;
 220    bool writes_flag() const;
 221
 222    fs_reg dst;
 223    fs_reg *src;
 224
 225    uint8_t sources; /**< Number of fs_reg sources. */
 226
 227    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 228     * mod and predication.
 229     */
 230    uint8_t flag_subreg;
 231
 232    uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
 233    bool eot:1;
 234    bool header_present:1;
 235    bool shadow_compare:1;
 236    bool force_uncompressed:1;
 237    bool force_sechalf:1;
 238    bool pi_noperspective:1;   /**< Pixel interpolator noperspective flag */
 239 };
 240
 241 /**
 242  * The fragment shader front-end.
 243  *
 244  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
 245  */
 246 class fs_visitor : public backend_visitor
 247 {
 248 public:
 249    const fs_reg reg_null_f;
 250    const fs_reg reg_null_d;
 251    const fs_reg reg_null_ud;
 252
 253    fs_visitor(struct brw_context *brw,
 254               void *mem_ctx,
 255               const struct brw_wm_prog_key *key,
 256               struct brw_wm_prog_data *prog_data,
 257               struct gl_shader_program *shader_prog,
 258               struct gl_fragment_program *fp,
 259               unsigned dispatch_width);
 260    ~fs_visitor();
 261    void init();
 262
 263    fs_reg *variable_storage(ir_variable *var);
 264    int virtual_grf_alloc(int size);
 265    void import_uniforms(fs_visitor *v);
 266
 267    void visit(ir_variable *ir);
 268    void visit(ir_assignment *ir);
 269    void visit(ir_dereference_variable *ir);
 270    void visit(ir_dereference_record *ir);
 271    void visit(ir_dereference_array *ir);
 272    void visit(ir_expression *ir);
 273    void visit(ir_texture *ir);
 274    void visit(ir_if *ir);
 275    void visit(ir_constant *ir);
 276    void visit(ir_swizzle *ir);
 277    void visit(ir_return *ir);
 278    void visit(ir_loop *ir);
 279    void visit(ir_loop_jump *ir);
 280    void visit(ir_discard *ir);
 281    void visit(ir_call *ir);
 282    void visit(ir_function *ir);
 283    void visit(ir_function_signature *ir);
 284    void visit(ir_emit_vertex *);
 285    void visit(ir_end_primitive *);
 286
 287    uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
 288    void swizzle_result(ir_texture *ir, fs_reg orig_val, uint32_t sampler);
 289
 290    fs_inst *emit(fs_inst *inst);
 291    void emit(exec_list list);
 292
 293    fs_inst *emit(enum opcode opcode);
 294    fs_inst *emit(enum opcode opcode, const fs_reg &dst);
 295    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 296    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 297                  const fs_reg &src1);
 298    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 299                  const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 300    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 301                  fs_reg src[], int sources);
 302
 303    fs_inst *MOV(const fs_reg &dst, const fs_reg &src);
 304    fs_inst *NOT(const fs_reg &dst, const fs_reg &src);
 305    fs_inst *RNDD(const fs_reg &dst, const fs_reg &src);
 306    fs_inst *RNDE(const fs_reg &dst, const fs_reg &src);
 307    fs_inst *RNDZ(const fs_reg &dst, const fs_reg &src);
 308    fs_inst *FRC(const fs_reg &dst, const fs_reg &src);
 309    fs_inst *ADD(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 310    fs_inst *MUL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 311    fs_inst *MACH(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 312    fs_inst *MAC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 313    fs_inst *SHL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 314    fs_inst *SHR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 315    fs_inst *ASR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 316    fs_inst *AND(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 317    fs_inst *OR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 318    fs_inst *XOR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 319    fs_inst *IF(enum brw_predicate predicate);
 320    fs_inst *IF(const fs_reg &src0, const fs_reg &src1,
 321                enum brw_conditional_mod condition);
 322    fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
 323                 enum brw_conditional_mod condition);
 324    fs_inst *LRP(const fs_reg &dst, const fs_reg &a, const fs_reg &y,
 325                 const fs_reg &x);
 326    fs_inst *DEP_RESOLVE_MOV(int grf);
 327    fs_inst *BFREV(const fs_reg &dst, const fs_reg &value);
 328    fs_inst *BFE(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset,
 329                 const fs_reg &value);
 330    fs_inst *BFI1(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset);
 331    fs_inst *BFI2(const fs_reg &dst, const fs_reg &bfi1_dst,
 332                  const fs_reg &insert, const fs_reg &base);
 333    fs_inst *FBH(const fs_reg &dst, const fs_reg &value);
 334    fs_inst *FBL(const fs_reg &dst, const fs_reg &value);
 335    fs_inst *CBIT(const fs_reg &dst, const fs_reg &value);
 336    fs_inst *MAD(const fs_reg &dst, const fs_reg &c, const fs_reg &b,
 337                 const fs_reg &a);
 338    fs_inst *ADDC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 339    fs_inst *SUBB(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 340    fs_inst *SEL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 341
 342    int type_size(const struct glsl_type *type);
 343    fs_inst *get_instruction_generating_reg(fs_inst *start,
 344                                            fs_inst *end,
 345                                            const fs_reg &reg);
 346
 347    fs_inst *LOAD_PAYLOAD(const fs_reg &dst, fs_reg *src, int sources);
 348
 349    exec_list VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
 350                                         const fs_reg &surf_index,
 351                                         const fs_reg &varying_offset,
 352                                         uint32_t const_offset);
 353
 354    bool run();
 355    void assign_binding_table_offsets();
 356    void setup_payload_gen4();
 357    void setup_payload_gen6();
 358    void assign_curb_setup();
 359    void calculate_urb_setup();
 360    void assign_urb_setup();
 361    bool assign_regs(bool allow_spilling);
 362    void assign_regs_trivial();
 363    void get_used_mrfs(bool *mrf_used);
 364    void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
 365                                    int first_payload_node);
 366    void setup_mrf_hack_interference(struct ra_graph *g,
 367                                     int first_mrf_hack_node);
 368    int choose_spill_reg(struct ra_graph *g);
 369    void spill_reg(int spill_reg);
 370    void split_virtual_grfs();
 371    bool compact_virtual_grfs();
 372    void move_uniform_array_access_to_pull_constants();
 373    void assign_constant_locations();
 374    void demote_pull_constants();
 375    void invalidate_live_intervals();
 376    void calculate_live_intervals();
 377    void calculate_register_pressure();
 378    bool opt_algebraic();
 379    bool opt_cse();
 380    bool opt_cse_local(bblock_t *block);
 381    bool opt_copy_propagate();
 382    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 383    bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
 384    bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
 385                                  exec_list *acp);
 386    void opt_drop_redundant_mov_to_flags();
 387    bool opt_register_renaming();
 388    bool register_coalesce();
 389    bool compute_to_mrf();
 390    bool dead_code_eliminate();
 391    bool remove_duplicate_mrf_writes();
 392    bool virtual_grf_interferes(int a, int b);
 393    void schedule_instructions(instruction_scheduler_mode mode);
 394    void insert_gen4_send_dependency_workarounds();
 395    void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
 396                                                     fs_inst *inst);
 397    void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
 398                                                      fs_inst *inst);
 399    void vfail(const char *msg, va_list args);
 400    void fail(const char *msg, ...);
 401    void no16(const char *msg, ...);
 402    void lower_uniform_pull_constant_loads();
 403    bool lower_load_payload();
 404
 405    void push_force_uncompressed();
 406    void pop_force_uncompressed();
 407
 408    void emit_dummy_fs();
 409    void emit_repclear_shader();
 410    fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
 411    fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
 412                          glsl_interp_qualifier interpolation_mode,
 413                          bool is_centroid, bool is_sample);
 414    fs_reg *emit_frontfacing_interpolation();
 415    fs_reg *emit_samplepos_setup();
 416    fs_reg *emit_sampleid_setup(ir_variable *ir);
 417    fs_reg *emit_general_interpolation(ir_variable *ir);
 418    void emit_interpolation_setup_gen4();
 419    void emit_interpolation_setup_gen6();
 420    void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
 421    fs_reg rescale_texcoord(ir_texture *ir, fs_reg coordinate,
 422                            bool is_rect, uint32_t sampler, int texunit);
 423    fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 424                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 425                               uint32_t sampler);
 426    fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 427                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 428                               fs_reg sample_index, uint32_t sampler);
 429    fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 430                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 431                               fs_reg sample_index, fs_reg mcs, fs_reg sampler);
 432    fs_reg emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, fs_reg sampler);
 433    void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
 434    fs_reg fix_math_operand(fs_reg src);
 435    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
 436    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
 437    void emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
 438                  const fs_reg &a);
 439    void emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &dst,
 440                     const fs_reg &src0, const fs_reg &src1);
 441    bool try_emit_saturate(ir_expression *ir);
 442    bool try_emit_mad(ir_expression *ir);
 443    void try_replace_with_sel();
 444    bool opt_peephole_sel();
 445    bool opt_peephole_predicated_break();
 446    bool opt_saturate_propagation();
 447    void emit_bool_to_cond_code(ir_rvalue *condition);
 448    void emit_if_gen6(ir_if *ir);
 449    void emit_unspill(bblock_t *block, fs_inst *inst, fs_reg reg,
 450                      uint32_t spill_offset, int count);
 451    void emit_spill(bblock_t *block, fs_inst *inst, fs_reg reg,
 452                    uint32_t spill_offset, int count);
 453
 454    void emit_fragment_program_code();
 455    void setup_fp_regs();
 456    fs_reg get_fp_src_reg(const prog_src_register *src);
 457    fs_reg get_fp_dst_reg(const prog_dst_register *dst);
 458    void emit_fp_alu1(enum opcode opcode,
 459                      const struct prog_instruction *fpi,
 460                      fs_reg dst, fs_reg src);
 461    void emit_fp_alu2(enum opcode opcode,
 462                      const struct prog_instruction *fpi,
 463                      fs_reg dst, fs_reg src0, fs_reg src1);
 464    void emit_fp_scalar_write(const struct prog_instruction *fpi,
 465                              fs_reg dst, fs_reg src);
 466    void emit_fp_scalar_math(enum opcode opcode,
 467                             const struct prog_instruction *fpi,
 468                             fs_reg dst, fs_reg src);
 469
 470    void emit_fp_minmax(const struct prog_instruction *fpi,
 471                        fs_reg dst, fs_reg src0, fs_reg src1);
 472
 473    void emit_fp_sop(enum brw_conditional_mod conditional_mod,
 474                     const struct prog_instruction *fpi,
 475                     fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
 476
 477    void emit_color_write(fs_reg color, int index, int first_color_mrf);
 478    void emit_alpha_test();
 479    fs_inst *emit_single_fb_write(fs_reg color1, fs_reg color2,
 480                                  fs_reg src0_alpha, unsigned components);
 481    void emit_fb_writes();
 482
 483    void emit_shader_time_begin();
 484    void emit_shader_time_end();
 485    void emit_shader_time_write(enum shader_time_shader_type type,
 486                                fs_reg value);
 487
 488    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 489                             fs_reg dst, fs_reg offset, fs_reg src0,
 490                             fs_reg src1);
 491
 492    void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
 493                                   fs_reg offset);
 494
 495    void emit_interpolate_expression(ir_expression *ir);
 496
 497    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 498                                fs_reg dst,
 499                                fs_reg src,
 500                                fs_inst *pre_rhs_inst,
 501                                fs_inst *last_rhs_inst);
 502    void emit_assignment_writes(fs_reg &l, fs_reg &r,
 503                                const glsl_type *type, bool predicated);
 504    void resolve_ud_negate(fs_reg *reg);
 505    void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
 506
 507    fs_reg get_timestamp();
 508
 509    struct brw_reg interp_reg(int location, int channel);
 510    void setup_uniform_values(ir_variable *ir);
 511    void setup_builtin_uniform_values(ir_variable *ir);
 512    int implied_mrf_writes(fs_inst *inst);
 513
 514    virtual void dump_instructions();
 515    virtual void dump_instructions(const char *name);
 516    void dump_instruction(backend_instruction *inst);
 517    void dump_instruction(backend_instruction *inst, FILE *file);
 518
 519    void visit_atomic_counter_intrinsic(ir_call *ir);
 520
 521    const void *const key;
 522    struct brw_stage_prog_data *prog_data;
 523    unsigned int sanity_param_count;
 524
 525    int *param_size;
 526
 527    int *virtual_grf_sizes;
 528    int virtual_grf_count;
 529    int virtual_grf_array_size;
 530    int *virtual_grf_start;
 531    int *virtual_grf_end;
 532    brw::fs_live_variables *live_intervals;
 533
 534    int *regs_live_at_ip;
 535
 536    /** Number of uniform variable components visited. */
 537    unsigned uniforms;
 538
 539    /** Byte-offset for the next available spot in the scratch space buffer. */
 540    unsigned last_scratch;
 541
 542    /**
 543     * Array mapping UNIFORM register numbers to the pull parameter index,
 544     * or -1 if this uniform register isn't being uploaded as a pull constant.
 545     */
 546    int *pull_constant_loc;
 547
 548    /**
 549     * Array mapping UNIFORM register numbers to the push parameter index,
 550     * or -1 if this uniform register isn't being uploaded as a push constant.
 551     */
 552    int *push_constant_loc;
 553
 554    struct hash_table *variable_ht;
 555    fs_reg frag_depth;
 556    fs_reg sample_mask;
 557    fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
 558    unsigned output_components[BRW_MAX_DRAW_BUFFERS];
 559    fs_reg dual_src_output;
 560    bool do_dual_src;
 561    int first_non_payload_grf;
 562    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 563    int max_grf;
 564
 565    fs_reg *fp_temp_regs;
 566    fs_reg *fp_input_regs;
 567
 568    /** @{ debug annotation info */
 569    const char *current_annotation;
 570    const void *base_ir;
 571    /** @} */
 572
 573    bool failed;
 574    char *fail_msg;
 575    bool simd16_unsupported;
 576    char *no16_msg;
 577
 578    /* Result of last visit() method. */
 579    fs_reg result;
 580
 581    /** Register numbers for thread payload fields. */
 582    struct {
 583       uint8_t source_depth_reg;
 584       uint8_t source_w_reg;
 585       uint8_t aa_dest_stencil_reg;
 586       uint8_t dest_depth_reg;
 587       uint8_t sample_pos_reg;
 588       uint8_t sample_mask_in_reg;
 589       uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 590
 591       /** The number of thread payload registers the hardware will supply. */
 592       uint8_t num_regs;
 593    } payload;
 594
 595    bool source_depth_to_render_target;
 596    bool runtime_check_aads_emit;
 597
 598    fs_reg pixel_x;
 599    fs_reg pixel_y;
 600    fs_reg wpos_w;
 601    fs_reg pixel_w;
 602    fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 603    fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 604    fs_reg shader_start_time;
 605
 606    int grf_used;
 607    bool spilled_any_registers;
 608
 609    const unsigned dispatch_width; /**< 8 or 16 */
 610
 611    int force_uncompressed_stack;
 612 };
 613
 614 /**
 615  * The fragment shader code generator.
 616  *
 617  * Translates FS IR to actual i965 assembly code.
 618  */
 619 class fs_generator
 620 {
 621 public:
 622    fs_generator(struct brw_context *brw,
 623                 void *mem_ctx,
 624                 const struct brw_wm_prog_key *key,
 625                 struct brw_wm_prog_data *prog_data,
 626                 struct gl_shader_program *shader_prog,
 627                 struct gl_fragment_program *fp,
 628                 bool runtime_check_aads_emit,
 629                 bool debug_flag);
 630    ~fs_generator();
 631
 632    const unsigned *generate_assembly(const cfg_t *simd8_cfg,
 633                                      const cfg_t *simd16_cfg,
 634                                      unsigned *assembly_size);
 635
 636 private:
 637    void generate_code(const cfg_t *cfg);
 638    void fire_fb_write(fs_inst *inst,
 639                       GLuint base_reg,
 640                       struct brw_reg implied_header,
 641                       GLuint nr);
 642    void generate_fb_write(fs_inst *inst);
 643    void generate_blorp_fb_write(fs_inst *inst);
 644    void generate_rep_fb_write(fs_inst *inst);
 645    void generate_pixel_xy(struct brw_reg dst, bool is_x);
 646    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 647                          struct brw_reg *src);
 648    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 649                      struct brw_reg sampler_index);
 650    void generate_math_gen6(fs_inst *inst,
 651                            struct brw_reg dst,
 652                            struct brw_reg src0,
 653                            struct brw_reg src1);
 654    void generate_math_gen4(fs_inst *inst,
 655                            struct brw_reg dst,
 656                            struct brw_reg src);
 657    void generate_math_g45(fs_inst *inst,
 658                           struct brw_reg dst,
 659                           struct brw_reg src);
 660    void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src, struct brw_reg quality);
 661    void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 662                      struct brw_reg quality, bool negate_value);
 663    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 664    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 665    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 666    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 667                                             struct brw_reg index,
 668                                             struct brw_reg offset);
 669    void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
 670                                                  struct brw_reg dst,
 671                                                  struct brw_reg surf_index,
 672                                                  struct brw_reg offset);
 673    void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 674                                             struct brw_reg index,
 675                                             struct brw_reg offset);
 676    void generate_varying_pull_constant_load_gen7(fs_inst *inst,
 677                                                  struct brw_reg dst,
 678                                                  struct brw_reg index,
 679                                                  struct brw_reg offset);
 680    void generate_mov_dispatch_to_flags(fs_inst *inst);
 681
 682    void generate_pixel_interpolator_query(fs_inst *inst,
 683                                           struct brw_reg dst,
 684                                           struct brw_reg src,
 685                                           struct brw_reg msg_data,
 686                                           unsigned msg_type);
 687
 688    void generate_set_omask(fs_inst *inst,
 689                            struct brw_reg dst,
 690                            struct brw_reg sample_mask);
 691
 692    void generate_set_sample_id(fs_inst *inst,
 693                                struct brw_reg dst,
 694                                struct brw_reg src0,
 695                                struct brw_reg src1);
 696
 697    void generate_set_simd4x2_offset(fs_inst *inst,
 698                                     struct brw_reg dst,
 699                                     struct brw_reg offset);
 700    void generate_discard_jump(fs_inst *inst);
 701
 702    void generate_pack_half_2x16_split(fs_inst *inst,
 703                                       struct brw_reg dst,
 704                                       struct brw_reg x,
 705                                       struct brw_reg y);
 706    void generate_unpack_half_2x16_split(fs_inst *inst,
 707                                         struct brw_reg dst,
 708                                         struct brw_reg src);
 709
 710    void generate_shader_time_add(fs_inst *inst,
 711                                  struct brw_reg payload,
 712                                  struct brw_reg offset,
 713                                  struct brw_reg value);
 714
 715    void generate_untyped_atomic(fs_inst *inst,
 716                                 struct brw_reg dst,
 717                                 struct brw_reg atomic_op,
 718                                 struct brw_reg surf_index);
 719
 720    void generate_untyped_surface_read(fs_inst *inst,
 721                                       struct brw_reg dst,
 722                                       struct brw_reg surf_index);
 723
 724    bool patch_discard_jumps_to_fb_writes();
 725
 726    struct brw_context *brw;
 727    struct gl_context *ctx;
 728
 729    struct brw_compile *p;
 730    gl_shader_stage stage;
 731    const void * const key;
 732    struct brw_stage_prog_data * const prog_data;
 733
 734    struct gl_shader_program * const shader_prog;
 735    const struct gl_program *prog;
 736
 737    unsigned dispatch_width; /**< 8 or 16 */
 738
 739    exec_list discard_halt_patches;
 740    bool runtime_check_aads_emit;
 741    const bool debug_flag;
 742    void *mem_ctx;
 743 };
 744
 745 bool brw_do_channel_expressions(struct exec_list *instructions);
 746 bool brw_do_vector_splitting(struct exec_list *instructions);
 747 bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);
 748
 749 struct brw_reg brw_reg_from_fs_reg(fs_reg *reg);