vk: Add four unit tests for our lock-free data-structures
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs.h
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #pragma once
29
30 #include "brw_shader.h"
31 #include "brw_ir_fs.h"
32 #include "brw_fs_builder.h"
33
34 extern "C" {
35
36 #include <sys/types.h>
37
38 #include "main/macros.h"
39 #include "main/shaderobj.h"
40 #include "main/uniforms.h"
41 #include "program/prog_parameter.h"
42 #include "program/prog_print.h"
43 #include "program/prog_optimize.h"
44 #include "util/register_allocate.h"
45 #include "program/hash_table.h"
46 #include "brw_context.h"
47 #include "brw_eu.h"
48 #include "brw_wm.h"
49 #include "intel_asm_annotation.h"
50 }
51 #include "glsl/glsl_types.h"
52 #include "glsl/ir.h"
53 #include "glsl/nir/nir.h"
54 #include "program/sampler.h"
55
56 struct bblock_t;
57 namespace {
58 struct acp_entry;
59 }
60
61 namespace brw {
62 class fs_live_variables;
63 }
64
65 /**
66 * The fragment shader front-end.
67 *
68 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
69 */
70 class fs_visitor : public backend_shader
71 {
72 public:
73 fs_visitor(const struct brw_compiler *compiler, void *log_data,
74 void *mem_ctx,
75 gl_shader_stage stage,
76 const void *key,
77 struct brw_stage_prog_data *prog_data,
78 struct gl_shader_program *shader_prog,
79 struct gl_program *prog,
80 unsigned dispatch_width,
81 int shader_time_index);
82
83 ~fs_visitor();
84
85 fs_reg vgrf(const glsl_type *const type);
86 void import_uniforms(fs_visitor *v);
87 void setup_uniform_clipplane_values(gl_clip_plane *clip_planes);
88 void compute_clip_distance(gl_clip_plane *clip_planes);
89
90 uint32_t gather_channel(int orig_chan, uint32_t sampler);
91 void swizzle_result(ir_texture_opcode op, int dest_components,
92 fs_reg orig_val, uint32_t sampler);
93
94 int type_size(const struct glsl_type *type);
95 fs_inst *get_instruction_generating_reg(fs_inst *start,
96 fs_inst *end,
97 const fs_reg &reg);
98
99 void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld,
100 const fs_reg &dst,
101 const fs_reg &surf_index,
102 const fs_reg &varying_offset,
103 uint32_t const_offset);
104 void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf);
105
106 bool run_fs(bool do_rep_send);
107 bool run_vs(gl_clip_plane *clip_planes);
108 bool run_cs();
109 void optimize();
110 void allocate_registers();
111 void assign_binding_table_offsets();
112 void setup_payload_gen4();
113 void setup_payload_gen6();
114 void setup_vs_payload();
115 void setup_cs_payload();
116 void fixup_3src_null_dest();
117 void assign_curb_setup();
118 void calculate_urb_setup();
119 void assign_urb_setup();
120 void assign_vs_urb_setup();
121 bool assign_regs(bool allow_spilling);
122 void assign_regs_trivial();
123 void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
124 int first_payload_node);
125 int choose_spill_reg(struct ra_graph *g);
126 void spill_reg(int spill_reg);
127 void split_virtual_grfs();
128 bool compact_virtual_grfs();
129 void move_uniform_array_access_to_pull_constants();
130 void assign_constant_locations();
131 void demote_pull_constants();
132 void invalidate_live_intervals();
133 void calculate_live_intervals();
134 void calculate_register_pressure();
135 bool opt_algebraic();
136 bool opt_redundant_discard_jumps();
137 bool opt_cse();
138 bool opt_cse_local(bblock_t *block);
139 bool opt_copy_propagate();
140 bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
141 bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
142 bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
143 exec_list *acp);
144 bool opt_register_renaming();
145 bool register_coalesce();
146 bool compute_to_mrf();
147 bool eliminate_find_live_channel();
148 bool dead_code_eliminate();
149 bool remove_duplicate_mrf_writes();
150
151 bool opt_sampler_eot();
152 bool virtual_grf_interferes(int a, int b);
153 void schedule_instructions(instruction_scheduler_mode mode);
154 void insert_gen4_send_dependency_workarounds();
155 void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
156 fs_inst *inst);
157 void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
158 fs_inst *inst);
159 void vfail(const char *msg, va_list args);
160 void fail(const char *msg, ...);
161 void no16(const char *msg);
162 void lower_uniform_pull_constant_loads();
163 bool lower_load_payload();
164 bool lower_integer_multiplication();
165 bool opt_combine_constants();
166
167 void emit_dummy_fs();
168 void emit_repclear_shader();
169 fs_reg *emit_fragcoord_interpolation(bool pixel_center_integer,
170 bool origin_upper_left);
171 fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
172 glsl_interp_qualifier interpolation_mode,
173 bool is_centroid, bool is_sample);
174 fs_reg *emit_frontfacing_interpolation();
175 fs_reg *emit_samplepos_setup();
176 fs_reg *emit_sampleid_setup();
177 void emit_general_interpolation(fs_reg attr, const char *name,
178 const glsl_type *type,
179 glsl_interp_qualifier interpolation_mode,
180 int location, bool mod_centroid,
181 bool mod_sample);
182 fs_reg *emit_vs_system_value(int location);
183 void emit_interpolation_setup_gen4();
184 void emit_interpolation_setup_gen6();
185 void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
186 fs_reg rescale_texcoord(fs_reg coordinate, int coord_components,
187 bool is_rect, uint32_t sampler, int texunit);
188 fs_inst *emit_texture_gen4(ir_texture_opcode op, fs_reg dst,
189 fs_reg coordinate, int coord_components,
190 fs_reg shadow_comp,
191 fs_reg lod, fs_reg lod2, int grad_components,
192 uint32_t sampler);
193 fs_inst *emit_texture_gen4_simd16(ir_texture_opcode op, fs_reg dst,
194 fs_reg coordinate, int vector_elements,
195 fs_reg shadow_c, fs_reg lod,
196 uint32_t sampler);
197 fs_inst *emit_texture_gen5(ir_texture_opcode op, fs_reg dst,
198 fs_reg coordinate, int coord_components,
199 fs_reg shadow_comp,
200 fs_reg lod, fs_reg lod2, int grad_components,
201 fs_reg sample_index, uint32_t sampler,
202 bool has_offset);
203 fs_inst *emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
204 fs_reg coordinate, int coord_components,
205 fs_reg shadow_comp,
206 fs_reg lod, fs_reg lod2, int grad_components,
207 fs_reg sample_index, fs_reg mcs, fs_reg sampler,
208 fs_reg offset_value);
209 void emit_texture(ir_texture_opcode op,
210 const glsl_type *dest_type,
211 fs_reg coordinate, int components,
212 fs_reg shadow_c,
213 fs_reg lod, fs_reg dpdy, int grad_components,
214 fs_reg sample_index,
215 fs_reg offset,
216 fs_reg mcs,
217 int gather_component,
218 bool is_cube_array,
219 bool is_rect,
220 uint32_t sampler,
221 fs_reg sampler_reg,
222 int texunit);
223 fs_reg emit_mcs_fetch(fs_reg coordinate, int components, fs_reg sampler);
224 void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
225 void resolve_source_modifiers(fs_reg *src);
226 void emit_discard_jump();
227 bool try_replace_with_sel();
228 bool opt_peephole_sel();
229 bool opt_peephole_predicated_break();
230 bool opt_saturate_propagation();
231 bool opt_cmod_propagation();
232 bool opt_zero_samples();
233 void emit_unspill(bblock_t *block, fs_inst *inst, fs_reg reg,
234 uint32_t spill_offset, int count);
235 void emit_spill(bblock_t *block, fs_inst *inst, fs_reg reg,
236 uint32_t spill_offset, int count);
237
238 void emit_nir_code();
239 void nir_setup_inputs(nir_shader *shader);
240 void nir_setup_outputs(nir_shader *shader);
241 void nir_setup_uniforms(nir_shader *shader);
242 void nir_setup_uniform(nir_variable *var);
243 void nir_setup_builtin_uniform(nir_variable *var);
244 void nir_emit_system_values(nir_shader *shader);
245 void nir_emit_impl(nir_function_impl *impl);
246 void nir_emit_cf_list(exec_list *list);
247 void nir_emit_if(nir_if *if_stmt);
248 void nir_emit_loop(nir_loop *loop);
249 void nir_emit_block(nir_block *block);
250 void nir_emit_instr(nir_instr *instr);
251 void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr);
252 void nir_emit_intrinsic(const brw::fs_builder &bld,
253 nir_intrinsic_instr *instr);
254 void nir_emit_texture(const brw::fs_builder &bld,
255 nir_tex_instr *instr);
256 void nir_emit_jump(const brw::fs_builder &bld,
257 nir_jump_instr *instr);
258 fs_reg get_nir_src(nir_src src);
259 fs_reg get_nir_dest(nir_dest dest);
260 void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst,
261 unsigned wr_mask);
262
263 bool optimize_frontfacing_ternary(nir_alu_instr *instr,
264 const fs_reg &result);
265
266 void setup_color_payload(fs_reg *dst, fs_reg color, unsigned components,
267 unsigned exec_size, bool use_2nd_half);
268 void emit_alpha_test();
269 fs_inst *emit_single_fb_write(const brw::fs_builder &bld,
270 fs_reg color1, fs_reg color2,
271 fs_reg src0_alpha, unsigned components,
272 unsigned exec_size, bool use_2nd_half = false);
273 void emit_fb_writes();
274 void emit_urb_writes(gl_clip_plane *clip_planes);
275 void emit_cs_terminate();
276
277 void emit_barrier();
278
279 void emit_shader_time_begin();
280 void emit_shader_time_end();
281 void SHADER_TIME_ADD(const brw::fs_builder &bld,
282 int shader_time_subindex,
283 fs_reg value);
284
285 void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
286 fs_reg dst, fs_reg offset, fs_reg src0,
287 fs_reg src1);
288
289 void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
290 fs_reg offset);
291
292 fs_reg get_timestamp(const brw::fs_builder &bld);
293
294 struct brw_reg interp_reg(int location, int channel);
295 int implied_mrf_writes(fs_inst *inst);
296
297 virtual void dump_instructions();
298 virtual void dump_instructions(const char *name);
299 void dump_instruction(backend_instruction *inst);
300 void dump_instruction(backend_instruction *inst, FILE *file);
301
302 const void *const key;
303 const struct brw_sampler_prog_key_data *key_tex;
304
305 struct brw_stage_prog_data *prog_data;
306 unsigned int sanity_param_count;
307
308 int *param_size;
309
310 int *virtual_grf_start;
311 int *virtual_grf_end;
312 brw::fs_live_variables *live_intervals;
313
314 int *regs_live_at_ip;
315
316 /** Number of uniform variable components visited. */
317 unsigned uniforms;
318
319 /** Total number of direct uniforms we can get from NIR */
320 unsigned num_direct_uniforms;
321
322 /** Byte-offset for the next available spot in the scratch space buffer. */
323 unsigned last_scratch;
324
325 /**
326 * Array mapping UNIFORM register numbers to the pull parameter index,
327 * or -1 if this uniform register isn't being uploaded as a pull constant.
328 */
329 int *pull_constant_loc;
330
331 /**
332 * Array mapping UNIFORM register numbers to the push parameter index,
333 * or -1 if this uniform register isn't being uploaded as a push constant.
334 */
335 int *push_constant_loc;
336
337 fs_reg frag_depth;
338 fs_reg sample_mask;
339 fs_reg outputs[VARYING_SLOT_MAX];
340 unsigned output_components[VARYING_SLOT_MAX];
341 fs_reg dual_src_output;
342 bool do_dual_src;
343 int first_non_payload_grf;
344 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
345 unsigned max_grf;
346
347 fs_reg *nir_locals;
348 fs_reg *nir_globals;
349 fs_reg nir_inputs;
350 fs_reg nir_outputs;
351 fs_reg *nir_system_values;
352
353 bool failed;
354 char *fail_msg;
355 bool simd16_unsupported;
356 char *no16_msg;
357
358 /* Result of last visit() method. Still used by emit_texture() */
359 fs_reg result;
360
361 /** Register numbers for thread payload fields. */
362 struct {
363 uint8_t source_depth_reg;
364 uint8_t source_w_reg;
365 uint8_t aa_dest_stencil_reg;
366 uint8_t dest_depth_reg;
367 uint8_t sample_pos_reg;
368 uint8_t sample_mask_in_reg;
369 uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
370
371 /** The number of thread payload registers the hardware will supply. */
372 uint8_t num_regs;
373 } payload;
374
375 bool source_depth_to_render_target;
376 bool runtime_check_aads_emit;
377
378 fs_reg pixel_x;
379 fs_reg pixel_y;
380 fs_reg wpos_w;
381 fs_reg pixel_w;
382 fs_reg delta_xy[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
383 fs_reg shader_start_time;
384 fs_reg userplane[MAX_CLIP_PLANES];
385
386 unsigned grf_used;
387 bool spilled_any_registers;
388
389 const unsigned dispatch_width; /**< 8 or 16 */
390
391 int shader_time_index;
392
393 unsigned promoted_constants;
394 brw::fs_builder bld;
395 };
396
397 /**
398 * The fragment shader code generator.
399 *
400 * Translates FS IR to actual i965 assembly code.
401 */
402 class fs_generator
403 {
404 public:
405 fs_generator(const struct brw_compiler *compiler, void *log_data,
406 void *mem_ctx,
407 const void *key,
408 struct brw_stage_prog_data *prog_data,
409 struct gl_program *fp,
410 unsigned promoted_constants,
411 bool runtime_check_aads_emit,
412 const char *stage_abbrev);
413 ~fs_generator();
414
415 void enable_debug(const char *shader_name);
416 int generate_code(const cfg_t *cfg, int dispatch_width);
417 const unsigned *get_assembly(unsigned int *assembly_size);
418
419 private:
420 void fire_fb_write(fs_inst *inst,
421 struct brw_reg payload,
422 struct brw_reg implied_header,
423 GLuint nr);
424 void generate_fb_write(fs_inst *inst, struct brw_reg payload);
425 void generate_urb_write(fs_inst *inst, struct brw_reg payload);
426 void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
427 void generate_barrier(fs_inst *inst, struct brw_reg src);
428 void generate_blorp_fb_write(fs_inst *inst);
429 void generate_linterp(fs_inst *inst, struct brw_reg dst,
430 struct brw_reg *src);
431 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
432 struct brw_reg sampler_index);
433 void generate_math_gen6(fs_inst *inst,
434 struct brw_reg dst,
435 struct brw_reg src0,
436 struct brw_reg src1);
437 void generate_math_gen4(fs_inst *inst,
438 struct brw_reg dst,
439 struct brw_reg src);
440 void generate_math_g45(fs_inst *inst,
441 struct brw_reg dst,
442 struct brw_reg src);
443 void generate_ddx(enum opcode op, struct brw_reg dst, struct brw_reg src);
444 void generate_ddy(enum opcode op, struct brw_reg dst, struct brw_reg src,
445 bool negate_value);
446 void generate_scratch_write(fs_inst *inst, struct brw_reg src);
447 void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
448 void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
449 void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
450 struct brw_reg index,
451 struct brw_reg offset);
452 void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
453 struct brw_reg dst,
454 struct brw_reg surf_index,
455 struct brw_reg offset);
456 void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
457 struct brw_reg index,
458 struct brw_reg offset);
459 void generate_varying_pull_constant_load_gen7(fs_inst *inst,
460 struct brw_reg dst,
461 struct brw_reg index,
462 struct brw_reg offset);
463 void generate_mov_dispatch_to_flags(fs_inst *inst);
464
465 void generate_pixel_interpolator_query(fs_inst *inst,
466 struct brw_reg dst,
467 struct brw_reg src,
468 struct brw_reg msg_data,
469 unsigned msg_type);
470
471 void generate_set_omask(fs_inst *inst,
472 struct brw_reg dst,
473 struct brw_reg sample_mask);
474
475 void generate_set_sample_id(fs_inst *inst,
476 struct brw_reg dst,
477 struct brw_reg src0,
478 struct brw_reg src1);
479
480 void generate_set_simd4x2_offset(fs_inst *inst,
481 struct brw_reg dst,
482 struct brw_reg offset);
483 void generate_discard_jump(fs_inst *inst);
484
485 void generate_pack_half_2x16_split(fs_inst *inst,
486 struct brw_reg dst,
487 struct brw_reg x,
488 struct brw_reg y);
489 void generate_unpack_half_2x16_split(fs_inst *inst,
490 struct brw_reg dst,
491 struct brw_reg src);
492
493 void generate_shader_time_add(fs_inst *inst,
494 struct brw_reg payload,
495 struct brw_reg offset,
496 struct brw_reg value);
497
498 bool patch_discard_jumps_to_fb_writes();
499
500 const struct brw_compiler *compiler;
501 void *log_data; /* Passed to compiler->*_log functions */
502
503 const struct brw_device_info *devinfo;
504
505 struct brw_codegen *p;
506 const void * const key;
507 struct brw_stage_prog_data * const prog_data;
508
509 const struct gl_program *prog;
510
511 unsigned dispatch_width; /**< 8 or 16 */
512
513 exec_list discard_halt_patches;
514 unsigned promoted_constants;
515 bool runtime_check_aads_emit;
516 bool debug_flag;
517 const char *shader_name;
518 const char *stage_abbrev;
519 void *mem_ctx;
520 };
521
522 bool brw_do_channel_expressions(struct exec_list *instructions);
523 bool brw_do_vector_splitting(struct exec_list *instructions);
524 void brw_setup_tex_for_precompile(struct brw_context *brw,
525 struct brw_sampler_prog_key_data *tex,
526 struct gl_program *prog);