src/mesa/drivers/dri/i965/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29
  30 #include "brw_shader.h"
  31
  32 extern "C" {
  33
  34 #include <sys/types.h>
  35
  36 #include "main/macros.h"
  37 #include "main/shaderobj.h"
  38 #include "main/uniforms.h"
  39 #include "program/prog_parameter.h"
  40 #include "program/prog_print.h"
  41 #include "program/prog_optimize.h"
  42 #include "program/register_allocate.h"
  43 #include "program/sampler.h"
  44 #include "program/hash_table.h"
  45 #include "brw_context.h"
  46 #include "brw_eu.h"
  47 #include "brw_wm.h"
  48 #include "brw_shader.h"
  49 }
  50 #include "gen8_generator.h"
  51 #include "glsl/glsl_types.h"
  52 #include "glsl/ir.h"
  53
  54 #define MAX_SAMPLER_MESSAGE_SIZE 11
  55
  56 class bblock_t;
  57 namespace {
  58    struct acp_entry;
  59 }
  60
  61 namespace brw {
  62    class fs_live_variables;
  63 }
  64
  65 class fs_reg {
  66 public:
  67    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  68
  69    void init();
  70
  71    fs_reg();
  72    fs_reg(float f);
  73    fs_reg(int32_t i);
  74    fs_reg(uint32_t u);
  75    fs_reg(struct brw_reg fixed_hw_reg);
  76    fs_reg(enum register_file file, int reg);
  77    fs_reg(enum register_file file, int reg, uint32_t type);
  78    fs_reg(class fs_visitor *v, const struct glsl_type *type);
  79
  80    bool equals(const fs_reg &r) const;
  81    bool is_zero() const;
  82    bool is_one() const;
  83    bool is_null() const;
  84    bool is_valid_3src() const;
  85    bool is_contiguous() const;
  86
  87    fs_reg &apply_stride(unsigned stride);
  88    /** Smear a channel of the reg to all channels. */
  89    fs_reg &set_smear(unsigned subreg);
  90
  91    /** Register file: GRF, MRF, IMM. */
  92    enum register_file file;
  93    /** Register type.  BRW_REGISTER_TYPE_* */
  94    uint8_t type;
  95    /**
  96     * Register number.  For MRF, it's the hardware register.  For
  97     * GRF, it's a virtual register number until register allocation
  98     */
  99    uint16_t reg;
 100    /**
 101     * Offset from the start of the contiguous register block.
 102     *
 103     * For pre-register-allocation GRFs, this is in units of a float per pixel
 104     * (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
 105     * For uniforms, this is in units of 1 float.
 106     */
 107    int reg_offset;
 108    /**
 109     * Offset in bytes from the start of the register.  Values up to a
 110     * backend_reg::reg_offset unit are valid.
 111     */
 112    int subreg_offset;
 113
 114    /** Value for file == IMM */
 115    union {
 116       int32_t i;
 117       uint32_t u;
 118       float f;
 119    } imm;
 120
 121    struct brw_reg fixed_hw_reg;
 122
 123    fs_reg *reladdr;
 124
 125    bool negate;
 126    bool abs;
 127
 128    /** Register region horizontal stride */
 129    uint8_t stride;
 130 };
 131
 132 static inline fs_reg
 133 retype(fs_reg reg, unsigned type)
 134 {
 135    reg.fixed_hw_reg.type = reg.type = type;
 136    return reg;
 137 }
 138
 139 static inline fs_reg
 140 offset(fs_reg reg, unsigned delta)
 141 {
 142    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 143    reg.reg_offset += delta;
 144    return reg;
 145 }
 146
 147 static inline fs_reg
 148 byte_offset(fs_reg reg, unsigned delta)
 149 {
 150    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 151    reg.subreg_offset += delta;
 152    return reg;
 153 }
 154
 155 /**
 156  * Get either of the 8-component halves of a 16-component register.
 157  *
 158  * Note: this also works if \c reg represents a SIMD16 pair of registers.
 159  */
 160 static inline fs_reg
 161 half(const fs_reg &reg, unsigned idx)
 162 {
 163    assert(idx < 2);
 164    assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM));
 165    return byte_offset(reg, 8 * idx * reg.stride * type_sz(reg.type));
 166 }
 167
 168 static const fs_reg reg_undef;
 169 static const fs_reg reg_null_f(retype(brw_null_reg(), BRW_REGISTER_TYPE_F));
 170 static const fs_reg reg_null_d(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 171 static const fs_reg reg_null_ud(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
 172
 173 class ip_record : public exec_node {
 174 public:
 175    DECLARE_RALLOC_CXX_OPERATORS(ip_record)
 176
 177    ip_record(int ip)
 178    {
 179       this->ip = ip;
 180    }
 181
 182    int ip;
 183 };
 184
 185 class fs_inst : public backend_instruction {
 186 public:
 187    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 188
 189    void init();
 190
 191    fs_inst();
 192    fs_inst(enum opcode opcode);
 193    fs_inst(enum opcode opcode, fs_reg dst);
 194    fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0);
 195    fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
 196    fs_inst(enum opcode opcode, fs_reg dst,
 197            fs_reg src0, fs_reg src1,fs_reg src2);
 198
 199    bool equals(fs_inst *inst);
 200    bool overwrites_reg(const fs_reg &reg);
 201    bool is_send_from_grf();
 202    bool is_partial_write();
 203    int regs_read(fs_visitor *v, int arg);
 204
 205    bool reads_flag();
 206    bool writes_flag();
 207
 208    fs_reg dst;
 209    fs_reg src[3];
 210
 211    /** @{
 212     * Annotation for the generated IR.  One of the two can be set.
 213     */
 214    const void *ir;
 215    const char *annotation;
 216    /** @} */
 217
 218    uint32_t texture_offset; /**< Texture offset bitfield */
 219    uint32_t offset; /* spill/unspill offset */
 220
 221    uint8_t conditional_mod; /**< BRW_CONDITIONAL_* */
 222
 223    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 224     * mod and predication.
 225     */
 226    uint8_t flag_subreg;
 227
 228    uint8_t mlen; /**< SEND message length */
 229    uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
 230    int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 231    uint8_t sampler;
 232    uint8_t target; /**< MRT target. */
 233    bool saturate:1;
 234    bool eot:1;
 235    bool header_present:1;
 236    bool shadow_compare:1;
 237    bool force_uncompressed:1;
 238    bool force_sechalf:1;
 239    bool force_writemask_all:1;
 240 };
 241
 242 /**
 243  * The fragment shader front-end.
 244  *
 245  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
 246  */
 247 class fs_visitor : public backend_visitor
 248 {
 249 public:
 250
 251    fs_visitor(struct brw_context *brw,
 252               struct brw_wm_compile *c,
 253               struct gl_shader_program *shader_prog,
 254               struct gl_fragment_program *fp,
 255               unsigned dispatch_width);
 256    ~fs_visitor();
 257
 258    fs_reg *variable_storage(ir_variable *var);
 259    int virtual_grf_alloc(int size);
 260    void import_uniforms(fs_visitor *v);
 261
 262    void visit(ir_variable *ir);
 263    void visit(ir_assignment *ir);
 264    void visit(ir_dereference_variable *ir);
 265    void visit(ir_dereference_record *ir);
 266    void visit(ir_dereference_array *ir);
 267    void visit(ir_expression *ir);
 268    void visit(ir_texture *ir);
 269    void visit(ir_if *ir);
 270    void visit(ir_constant *ir);
 271    void visit(ir_swizzle *ir);
 272    void visit(ir_return *ir);
 273    void visit(ir_loop *ir);
 274    void visit(ir_loop_jump *ir);
 275    void visit(ir_discard *ir);
 276    void visit(ir_call *ir);
 277    void visit(ir_function *ir);
 278    void visit(ir_function_signature *ir);
 279    void visit(ir_emit_vertex *);
 280    void visit(ir_end_primitive *);
 281
 282    uint32_t gather_channel(ir_texture *ir, int sampler);
 283    void swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler);
 284
 285    bool can_do_source_mods(fs_inst *inst);
 286
 287    fs_inst *emit(fs_inst *inst);
 288    void emit(exec_list list);
 289
 290    fs_inst *emit(enum opcode opcode);
 291    fs_inst *emit(enum opcode opcode, fs_reg dst);
 292    fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0);
 293    fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
 294    fs_inst *emit(enum opcode opcode, fs_reg dst,
 295                  fs_reg src0, fs_reg src1, fs_reg src2);
 296
 297    fs_inst *MOV(fs_reg dst, fs_reg src);
 298    fs_inst *NOT(fs_reg dst, fs_reg src);
 299    fs_inst *RNDD(fs_reg dst, fs_reg src);
 300    fs_inst *RNDE(fs_reg dst, fs_reg src);
 301    fs_inst *RNDZ(fs_reg dst, fs_reg src);
 302    fs_inst *FRC(fs_reg dst, fs_reg src);
 303    fs_inst *ADD(fs_reg dst, fs_reg src0, fs_reg src1);
 304    fs_inst *MUL(fs_reg dst, fs_reg src0, fs_reg src1);
 305    fs_inst *MACH(fs_reg dst, fs_reg src0, fs_reg src1);
 306    fs_inst *MAC(fs_reg dst, fs_reg src0, fs_reg src1);
 307    fs_inst *SHL(fs_reg dst, fs_reg src0, fs_reg src1);
 308    fs_inst *SHR(fs_reg dst, fs_reg src0, fs_reg src1);
 309    fs_inst *ASR(fs_reg dst, fs_reg src0, fs_reg src1);
 310    fs_inst *AND(fs_reg dst, fs_reg src0, fs_reg src1);
 311    fs_inst *OR(fs_reg dst, fs_reg src0, fs_reg src1);
 312    fs_inst *XOR(fs_reg dst, fs_reg src0, fs_reg src1);
 313    fs_inst *IF(uint32_t predicate);
 314    fs_inst *IF(fs_reg src0, fs_reg src1, uint32_t condition);
 315    fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
 316                 uint32_t condition);
 317    fs_inst *LRP(fs_reg dst, fs_reg a, fs_reg y, fs_reg x);
 318    fs_inst *DEP_RESOLVE_MOV(int grf);
 319    fs_inst *BFREV(fs_reg dst, fs_reg value);
 320    fs_inst *BFE(fs_reg dst, fs_reg bits, fs_reg offset, fs_reg value);
 321    fs_inst *BFI1(fs_reg dst, fs_reg bits, fs_reg offset);
 322    fs_inst *BFI2(fs_reg dst, fs_reg bfi1_dst, fs_reg insert, fs_reg base);
 323    fs_inst *FBH(fs_reg dst, fs_reg value);
 324    fs_inst *FBL(fs_reg dst, fs_reg value);
 325    fs_inst *CBIT(fs_reg dst, fs_reg value);
 326    fs_inst *MAD(fs_reg dst, fs_reg c, fs_reg b, fs_reg a);
 327    fs_inst *ADDC(fs_reg dst, fs_reg src0, fs_reg src1);
 328    fs_inst *SUBB(fs_reg dst, fs_reg src0, fs_reg src1);
 329    fs_inst *SEL(fs_reg dst, fs_reg src0, fs_reg src1);
 330
 331    int type_size(const struct glsl_type *type);
 332    fs_inst *get_instruction_generating_reg(fs_inst *start,
 333                                            fs_inst *end,
 334                                            const fs_reg &reg);
 335
 336    exec_list VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
 337                                         const fs_reg &surf_index,
 338                                         const fs_reg &varying_offset,
 339                                         uint32_t const_offset);
 340
 341    bool run();
 342    void assign_binding_table_offsets();
 343    void setup_payload_gen4();
 344    void setup_payload_gen6();
 345    void assign_curb_setup();
 346    void calculate_urb_setup();
 347    void assign_urb_setup();
 348    bool assign_regs(bool allow_spilling);
 349    void assign_regs_trivial();
 350    void get_used_mrfs(bool *mrf_used);
 351    void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
 352                                    int first_payload_node);
 353    void setup_mrf_hack_interference(struct ra_graph *g,
 354                                     int first_mrf_hack_node);
 355    int choose_spill_reg(struct ra_graph *g);
 356    void spill_reg(int spill_reg);
 357    void split_virtual_grfs();
 358    void compact_virtual_grfs();
 359    void move_uniform_array_access_to_pull_constants();
 360    void setup_pull_constants();
 361    void demote_pull_constants(bool reladdr_only);
 362    void invalidate_live_intervals();
 363    void calculate_live_intervals();
 364    void calculate_register_pressure();
 365    bool opt_algebraic();
 366    bool opt_cse();
 367    bool opt_cse_local(bblock_t *block, exec_list *aeb);
 368    bool opt_copy_propagate();
 369    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 370    bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
 371    bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
 372                                  exec_list *acp);
 373    void opt_drop_redundant_mov_to_flags();
 374    bool register_coalesce();
 375    bool compute_to_mrf();
 376    bool dead_code_eliminate();
 377    bool dead_code_eliminate_local();
 378    bool remove_dead_constants();
 379    bool remove_duplicate_mrf_writes();
 380    bool virtual_grf_interferes(int a, int b);
 381    void schedule_instructions(instruction_scheduler_mode mode);
 382    void insert_gen4_send_dependency_workarounds();
 383    void insert_gen4_pre_send_dependency_workarounds(fs_inst *inst);
 384    void insert_gen4_post_send_dependency_workarounds(fs_inst *inst);
 385    void fail(const char *msg, ...);
 386    void lower_uniform_pull_constant_loads();
 387
 388    void push_force_uncompressed();
 389    void pop_force_uncompressed();
 390
 391    void emit_dummy_fs();
 392    fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
 393    fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
 394                          glsl_interp_qualifier interpolation_mode,
 395                          bool is_centroid, bool is_sample);
 396    fs_reg *emit_frontfacing_interpolation(ir_variable *ir);
 397    fs_reg *emit_samplepos_setup(ir_variable *ir);
 398    fs_reg *emit_sampleid_setup(ir_variable *ir);
 399    fs_reg *emit_samplemaskin_setup(ir_variable *ir);
 400    fs_reg *emit_general_interpolation(ir_variable *ir);
 401    void emit_interpolation_setup_gen4();
 402    void emit_interpolation_setup_gen6();
 403    void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
 404    fs_reg rescale_texcoord(ir_texture *ir, fs_reg coordinate,
 405                            bool is_rect, int sampler, int texunit);
 406    fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 407                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2);
 408    fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 409                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 410                               fs_reg sample_index);
 411    fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 412                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 413                               fs_reg sample_index, fs_reg mcs, int sampler);
 414    fs_reg emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, int sampler);
 415    void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
 416    fs_reg fix_math_operand(fs_reg src);
 417    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
 418    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
 419    void emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
 420                  const fs_reg &a);
 421    void emit_minmax(uint32_t conditionalmod, const fs_reg &dst,
 422                     const fs_reg &src0, const fs_reg &src1);
 423    bool try_emit_saturate(ir_expression *ir);
 424    bool try_emit_mad(ir_expression *ir, int mul_arg);
 425    void try_replace_with_sel();
 426    bool opt_peephole_sel();
 427    bool opt_peephole_predicated_break();
 428    bool opt_saturate_propagation();
 429    void emit_bool_to_cond_code(ir_rvalue *condition);
 430    void emit_if_gen6(ir_if *ir);
 431    void emit_unspill(fs_inst *inst, fs_reg reg, uint32_t spill_offset,
 432                      int count);
 433
 434    void emit_fragment_program_code();
 435    void setup_fp_regs();
 436    fs_reg get_fp_src_reg(const prog_src_register *src);
 437    fs_reg get_fp_dst_reg(const prog_dst_register *dst);
 438    void emit_fp_alu1(enum opcode opcode,
 439                      const struct prog_instruction *fpi,
 440                      fs_reg dst, fs_reg src);
 441    void emit_fp_alu2(enum opcode opcode,
 442                      const struct prog_instruction *fpi,
 443                      fs_reg dst, fs_reg src0, fs_reg src1);
 444    void emit_fp_scalar_write(const struct prog_instruction *fpi,
 445                              fs_reg dst, fs_reg src);
 446    void emit_fp_scalar_math(enum opcode opcode,
 447                             const struct prog_instruction *fpi,
 448                             fs_reg dst, fs_reg src);
 449
 450    void emit_fp_minmax(const struct prog_instruction *fpi,
 451                        fs_reg dst, fs_reg src0, fs_reg src1);
 452
 453    void emit_fp_sop(uint32_t conditional_mod,
 454                     const struct prog_instruction *fpi,
 455                     fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
 456
 457    void emit_color_write(int target, int index, int first_color_mrf);
 458    void emit_alpha_test();
 459    void emit_fb_writes();
 460
 461    void emit_shader_time_begin();
 462    void emit_shader_time_end();
 463    void emit_shader_time_write(enum shader_time_shader_type type,
 464                                fs_reg value);
 465
 466    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 467                             fs_reg dst, fs_reg offset, fs_reg src0,
 468                             fs_reg src1);
 469
 470    void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
 471                                   fs_reg offset);
 472
 473    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 474                                fs_reg dst,
 475                                fs_reg src,
 476                                fs_inst *pre_rhs_inst,
 477                                fs_inst *last_rhs_inst);
 478    void emit_assignment_writes(fs_reg &l, fs_reg &r,
 479                                const glsl_type *type, bool predicated);
 480    void resolve_ud_negate(fs_reg *reg);
 481    void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
 482
 483    fs_reg get_timestamp();
 484
 485    struct brw_reg interp_reg(int location, int channel);
 486    void setup_uniform_values(ir_variable *ir);
 487    void setup_builtin_uniform_values(ir_variable *ir);
 488    int implied_mrf_writes(fs_inst *inst);
 489
 490    virtual void dump_instructions();
 491    void dump_instruction(backend_instruction *inst);
 492
 493    void visit_atomic_counter_intrinsic(ir_call *ir);
 494
 495    struct gl_fragment_program *fp;
 496    struct brw_wm_compile *c;
 497    unsigned int sanity_param_count;
 498
 499    int *param_size;
 500
 501    int *virtual_grf_sizes;
 502    int virtual_grf_count;
 503    int virtual_grf_array_size;
 504    int *virtual_grf_start;
 505    int *virtual_grf_end;
 506    brw::fs_live_variables *live_intervals;
 507
 508    int *regs_live_at_ip;
 509
 510    /** Number of uniform variable components visited. */
 511    unsigned uniforms;
 512
 513    /**
 514     * Array mapping UNIFORM register numbers to the pull parameter index,
 515     * or -1 if this uniform register isn't being uploaded as a pull constant.
 516     */
 517    int *pull_constant_loc;
 518
 519    /* This is the map from UNIFORM hw_reg + reg_offset as generated by
 520     * the visitor to the packed uniform number after
 521     * remove_dead_constants() that represents the actual uploaded
 522     * uniform index.
 523     */
 524    int *params_remap;
 525    int nr_params_remap;
 526
 527    struct hash_table *variable_ht;
 528    fs_reg frag_depth;
 529    fs_reg sample_mask;
 530    fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
 531    unsigned output_components[BRW_MAX_DRAW_BUFFERS];
 532    fs_reg dual_src_output;
 533    int first_non_payload_grf;
 534    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 535    int max_grf;
 536
 537    fs_reg *fp_temp_regs;
 538    fs_reg *fp_input_regs;
 539
 540    /** @{ debug annotation info */
 541    const char *current_annotation;
 542    const void *base_ir;
 543    /** @} */
 544
 545    bool failed;
 546    char *fail_msg;
 547
 548    /* Result of last visit() method. */
 549    fs_reg result;
 550
 551    fs_reg pixel_x;
 552    fs_reg pixel_y;
 553    fs_reg wpos_w;
 554    fs_reg pixel_w;
 555    fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 556    fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 557    fs_reg shader_start_time;
 558
 559    int grf_used;
 560    bool spilled_any_registers;
 561
 562    const unsigned dispatch_width; /**< 8 or 16 */
 563
 564    int force_uncompressed_stack;
 565 };
 566
 567 /**
 568  * The fragment shader code generator.
 569  *
 570  * Translates FS IR to actual i965 assembly code.
 571  */
 572 class fs_generator
 573 {
 574 public:
 575    fs_generator(struct brw_context *brw,
 576                 struct brw_wm_compile *c,
 577                 struct gl_shader_program *prog,
 578                 struct gl_fragment_program *fp,
 579                 bool dual_source_output);
 580    ~fs_generator();
 581
 582    const unsigned *generate_assembly(exec_list *simd8_instructions,
 583                                      exec_list *simd16_instructions,
 584                                      unsigned *assembly_size,
 585                                      FILE *dump_file = NULL);
 586
 587 private:
 588    void generate_code(exec_list *instructions, FILE *dump_file);
 589    void generate_fb_write(fs_inst *inst);
 590    void generate_blorp_fb_write(fs_inst *inst);
 591    void generate_pixel_xy(struct brw_reg dst, bool is_x);
 592    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 593                          struct brw_reg *src);
 594    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 595    void generate_math1_gen7(fs_inst *inst,
 596                             struct brw_reg dst,
 597                             struct brw_reg src);
 598    void generate_math2_gen7(fs_inst *inst,
 599                             struct brw_reg dst,
 600                             struct brw_reg src0,
 601                             struct brw_reg src1);
 602    void generate_math1_gen6(fs_inst *inst,
 603                             struct brw_reg dst,
 604                             struct brw_reg src);
 605    void generate_math2_gen6(fs_inst *inst,
 606                             struct brw_reg dst,
 607                             struct brw_reg src0,
 608                             struct brw_reg src1);
 609    void generate_math_gen4(fs_inst *inst,
 610                            struct brw_reg dst,
 611                            struct brw_reg src);
 612    void generate_math_g45(fs_inst *inst,
 613                           struct brw_reg dst,
 614                           struct brw_reg src);
 615    void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 616    void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 617                      bool negate_value);
 618    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 619    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 620    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 621    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 622                                             struct brw_reg index,
 623                                             struct brw_reg offset);
 624    void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
 625                                                  struct brw_reg dst,
 626                                                  struct brw_reg surf_index,
 627                                                  struct brw_reg offset);
 628    void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 629                                             struct brw_reg index,
 630                                             struct brw_reg offset);
 631    void generate_varying_pull_constant_load_gen7(fs_inst *inst,
 632                                                  struct brw_reg dst,
 633                                                  struct brw_reg index,
 634                                                  struct brw_reg offset);
 635    void generate_mov_dispatch_to_flags(fs_inst *inst);
 636
 637    void generate_set_omask(fs_inst *inst,
 638                            struct brw_reg dst,
 639                            struct brw_reg sample_mask);
 640
 641    void generate_set_sample_id(fs_inst *inst,
 642                                struct brw_reg dst,
 643                                struct brw_reg src0,
 644                                struct brw_reg src1);
 645
 646    void generate_set_simd4x2_offset(fs_inst *inst,
 647                                     struct brw_reg dst,
 648                                     struct brw_reg offset);
 649    void generate_discard_jump(fs_inst *inst);
 650
 651    void generate_pack_half_2x16_split(fs_inst *inst,
 652                                       struct brw_reg dst,
 653                                       struct brw_reg x,
 654                                       struct brw_reg y);
 655    void generate_unpack_half_2x16_split(fs_inst *inst,
 656                                         struct brw_reg dst,
 657                                         struct brw_reg src);
 658
 659    void generate_shader_time_add(fs_inst *inst,
 660                                  struct brw_reg payload,
 661                                  struct brw_reg offset,
 662                                  struct brw_reg value);
 663
 664    void generate_untyped_atomic(fs_inst *inst,
 665                                 struct brw_reg dst,
 666                                 struct brw_reg atomic_op,
 667                                 struct brw_reg surf_index);
 668
 669    void generate_untyped_surface_read(fs_inst *inst,
 670                                       struct brw_reg dst,
 671                                       struct brw_reg surf_index);
 672
 673    void patch_discard_jumps_to_fb_writes();
 674
 675    struct brw_context *brw;
 676    struct gl_context *ctx;
 677
 678    struct brw_compile *p;
 679    struct brw_wm_compile *c;
 680
 681    struct gl_shader_program *prog;
 682    const struct gl_fragment_program *fp;
 683
 684    unsigned dispatch_width; /**< 8 or 16 */
 685
 686    exec_list discard_halt_patches;
 687    bool dual_source_output;
 688    void *mem_ctx;
 689 };
 690
 691 /**
 692  * The fragment shader code generator.
 693  *
 694  * Translates FS IR to actual i965 assembly code.
 695  */
 696 class gen8_fs_generator : public gen8_generator
 697 {
 698 public:
 699    gen8_fs_generator(struct brw_context *brw,
 700                      struct brw_wm_compile *c,
 701                      struct gl_shader_program *prog,
 702                      struct gl_fragment_program *fp,
 703                      bool dual_source_output);
 704    ~gen8_fs_generator();
 705
 706    const unsigned *generate_assembly(exec_list *simd8_instructions,
 707                                      exec_list *simd16_instructions,
 708                                      unsigned *assembly_size);
 709
 710 private:
 711    void generate_code(exec_list *instructions);
 712    void generate_fb_write(fs_inst *inst);
 713    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 714                          struct brw_reg *src);
 715    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 716    void generate_math1(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 717    void generate_math2(fs_inst *inst, struct brw_reg dst,
 718                        struct brw_reg src0, struct brw_reg src1);
 719    void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 720    void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 721                      bool negate_value);
 722    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 723    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 724    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 725    void generate_uniform_pull_constant_load(fs_inst *inst,
 726                                             struct brw_reg dst,
 727                                             struct brw_reg index,
 728                                             struct brw_reg offset);
 729    void generate_varying_pull_constant_load(fs_inst *inst,
 730                                             struct brw_reg dst,
 731                                             struct brw_reg index,
 732                                             struct brw_reg offset);
 733    void generate_mov_dispatch_to_flags(fs_inst *ir);
 734    void generate_set_omask(fs_inst *ir,
 735                            struct brw_reg dst,
 736                            struct brw_reg sample_mask);
 737    void generate_set_sample_id(fs_inst *ir,
 738                                struct brw_reg dst,
 739                                struct brw_reg src0,
 740                                struct brw_reg src1);
 741    void generate_set_simd4x2_offset(fs_inst *ir,
 742                                     struct brw_reg dst,
 743                                     struct brw_reg offset);
 744    void generate_pack_half_2x16_split(fs_inst *inst,
 745                                       struct brw_reg dst,
 746                                       struct brw_reg x,
 747                                       struct brw_reg y);
 748    void generate_unpack_half_2x16_split(fs_inst *inst,
 749                                         struct brw_reg dst,
 750                                         struct brw_reg src);
 751    void generate_discard_jump(fs_inst *ir);
 752
 753    void patch_discard_jumps_to_fb_writes();
 754
 755    void mark_surface_used(unsigned surf_index);
 756
 757    struct brw_wm_compile *c;
 758    const struct gl_fragment_program *fp;
 759
 760    unsigned dispatch_width; /** 8 or 16 */
 761
 762    bool dual_source_output;
 763
 764    exec_list discard_halt_patches;
 765 };
 766
 767 bool brw_do_channel_expressions(struct exec_list *instructions);
 768 bool brw_do_vector_splitting(struct exec_list *instructions);
 769 bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);
 770
 771 struct brw_reg brw_reg_from_fs_reg(fs_reg *reg);