i965: Move binding table setup to codegen time.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs.h
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #pragma once
29
30 #include "brw_shader.h"
31 #include "brw_ir_fs.h"
32 #include "brw_fs_builder.h"
33
34 extern "C" {
35
36 #include <sys/types.h>
37
38 #include "main/macros.h"
39 #include "main/shaderobj.h"
40 #include "main/uniforms.h"
41 #include "program/prog_parameter.h"
42 #include "program/prog_print.h"
43 #include "program/prog_optimize.h"
44 #include "util/register_allocate.h"
45 #include "program/hash_table.h"
46 #include "brw_context.h"
47 #include "brw_eu.h"
48 #include "brw_wm.h"
49 #include "intel_asm_annotation.h"
50 }
51 #include "glsl/glsl_types.h"
52 #include "glsl/ir.h"
53 #include "glsl/nir/nir.h"
54 #include "program/sampler.h"
55
56 struct bblock_t;
57 namespace {
58 struct acp_entry;
59 }
60
61 namespace brw {
62 class fs_live_variables;
63 }
64
65 static inline fs_reg
66 offset(fs_reg reg, const brw::fs_builder& bld, unsigned delta)
67 {
68 switch (reg.file) {
69 case BAD_FILE:
70 break;
71 case GRF:
72 case MRF:
73 case HW_REG:
74 case ATTR:
75 return byte_offset(reg,
76 delta * reg.component_size(bld.dispatch_width()));
77 case UNIFORM:
78 reg.reg_offset += delta;
79 break;
80 case IMM:
81 assert(delta == 0);
82 }
83 return reg;
84 }
85
86 /**
87 * The fragment shader front-end.
88 *
89 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
90 */
91 class fs_visitor : public backend_shader
92 {
93 public:
94 fs_visitor(const struct brw_compiler *compiler, void *log_data,
95 void *mem_ctx,
96 gl_shader_stage stage,
97 const void *key,
98 struct brw_stage_prog_data *prog_data,
99 struct gl_shader_program *shader_prog,
100 struct gl_program *prog,
101 unsigned dispatch_width,
102 int shader_time_index);
103
104 ~fs_visitor();
105
106 fs_reg vgrf(const glsl_type *const type);
107 void import_uniforms(fs_visitor *v);
108 void setup_uniform_clipplane_values(gl_clip_plane *clip_planes);
109 void compute_clip_distance(gl_clip_plane *clip_planes);
110
111 uint32_t gather_channel(int orig_chan, uint32_t sampler);
112 void swizzle_result(ir_texture_opcode op, int dest_components,
113 fs_reg orig_val, uint32_t sampler);
114
115 fs_inst *get_instruction_generating_reg(fs_inst *start,
116 fs_inst *end,
117 const fs_reg &reg);
118
119 void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld,
120 const fs_reg &dst,
121 const fs_reg &surf_index,
122 const fs_reg &varying_offset,
123 uint32_t const_offset);
124 void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf);
125
126 bool run_fs(bool do_rep_send);
127 bool run_vs(gl_clip_plane *clip_planes);
128 bool run_cs();
129 void optimize();
130 void allocate_registers();
131 void setup_payload_gen4();
132 void setup_payload_gen6();
133 void setup_vs_payload();
134 void setup_cs_payload();
135 void fixup_3src_null_dest();
136 void assign_curb_setup();
137 void calculate_urb_setup();
138 void assign_urb_setup();
139 void assign_vs_urb_setup();
140 bool assign_regs(bool allow_spilling);
141 void assign_regs_trivial();
142 void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
143 int first_payload_node);
144 int choose_spill_reg(struct ra_graph *g);
145 void spill_reg(int spill_reg);
146 void split_virtual_grfs();
147 bool compact_virtual_grfs();
148 void assign_constant_locations();
149 void demote_pull_constants();
150 void invalidate_live_intervals();
151 void calculate_live_intervals();
152 void calculate_register_pressure();
153 void validate();
154 bool opt_algebraic();
155 bool opt_redundant_discard_jumps();
156 bool opt_cse();
157 bool opt_cse_local(bblock_t *block);
158 bool opt_copy_propagate();
159 bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
160 bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
161 bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
162 exec_list *acp);
163 bool opt_register_renaming();
164 bool register_coalesce();
165 bool compute_to_mrf();
166 bool eliminate_find_live_channel();
167 bool dead_code_eliminate();
168 bool remove_duplicate_mrf_writes();
169
170 bool opt_sampler_eot();
171 bool virtual_grf_interferes(int a, int b);
172 void schedule_instructions(instruction_scheduler_mode mode);
173 void insert_gen4_send_dependency_workarounds();
174 void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
175 fs_inst *inst);
176 void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
177 fs_inst *inst);
178 void vfail(const char *msg, va_list args);
179 void fail(const char *msg, ...);
180 void no16(const char *msg);
181 void lower_uniform_pull_constant_loads();
182 bool lower_load_payload();
183 bool lower_logical_sends();
184 bool lower_integer_multiplication();
185 bool lower_simd_width();
186 bool opt_combine_constants();
187
188 void emit_dummy_fs();
189 void emit_repclear_shader();
190 fs_reg *emit_fragcoord_interpolation(bool pixel_center_integer,
191 bool origin_upper_left);
192 fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
193 glsl_interp_qualifier interpolation_mode,
194 bool is_centroid, bool is_sample);
195 fs_reg *emit_frontfacing_interpolation();
196 fs_reg *emit_samplepos_setup();
197 fs_reg *emit_sampleid_setup();
198 void emit_general_interpolation(fs_reg attr, const char *name,
199 const glsl_type *type,
200 glsl_interp_qualifier interpolation_mode,
201 int location, bool mod_centroid,
202 bool mod_sample);
203 fs_reg *emit_vs_system_value(int location);
204 void emit_interpolation_setup_gen4();
205 void emit_interpolation_setup_gen6();
206 void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
207 fs_reg rescale_texcoord(fs_reg coordinate, int coord_components,
208 bool is_rect, uint32_t sampler, int texunit);
209 void emit_texture(ir_texture_opcode op,
210 const glsl_type *dest_type,
211 fs_reg coordinate, int components,
212 fs_reg shadow_c,
213 fs_reg lod, fs_reg dpdy, int grad_components,
214 fs_reg sample_index,
215 fs_reg offset,
216 fs_reg mcs,
217 int gather_component,
218 bool is_cube_array,
219 bool is_rect,
220 uint32_t sampler,
221 fs_reg sampler_reg,
222 int texunit);
223 fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
224 const fs_reg &sampler);
225 void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
226 fs_reg resolve_source_modifiers(const fs_reg &src);
227 void emit_discard_jump();
228 bool opt_peephole_sel();
229 bool opt_peephole_predicated_break();
230 bool opt_saturate_propagation();
231 bool opt_cmod_propagation();
232 bool opt_zero_samples();
233 void emit_unspill(bblock_t *block, fs_inst *inst, fs_reg reg,
234 uint32_t spill_offset, int count);
235 void emit_spill(bblock_t *block, fs_inst *inst, fs_reg reg,
236 uint32_t spill_offset, int count);
237
238 void emit_nir_code();
239 void nir_setup_inputs(nir_shader *shader);
240 void nir_setup_outputs(nir_shader *shader);
241 void nir_setup_uniforms(nir_shader *shader);
242 void nir_emit_system_values(nir_shader *shader);
243 void nir_emit_impl(nir_function_impl *impl);
244 void nir_emit_cf_list(exec_list *list);
245 void nir_emit_if(nir_if *if_stmt);
246 void nir_emit_loop(nir_loop *loop);
247 void nir_emit_block(nir_block *block);
248 void nir_emit_instr(nir_instr *instr);
249 void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr);
250 void nir_emit_load_const(const brw::fs_builder &bld,
251 nir_load_const_instr *instr);
252 void nir_emit_undef(const brw::fs_builder &bld,
253 nir_ssa_undef_instr *instr);
254 void nir_emit_intrinsic(const brw::fs_builder &bld,
255 nir_intrinsic_instr *instr);
256 void nir_emit_ssbo_atomic(const brw::fs_builder &bld,
257 int op, nir_intrinsic_instr *instr);
258 void nir_emit_texture(const brw::fs_builder &bld,
259 nir_tex_instr *instr);
260 void nir_emit_jump(const brw::fs_builder &bld,
261 nir_jump_instr *instr);
262 fs_reg get_nir_src(nir_src src);
263 fs_reg get_nir_dest(nir_dest dest);
264 fs_reg get_nir_image_deref(const nir_deref_var *deref);
265 void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst,
266 unsigned wr_mask);
267
268 bool optimize_frontfacing_ternary(nir_alu_instr *instr,
269 const fs_reg &result);
270
271 void emit_alpha_test();
272 fs_inst *emit_single_fb_write(const brw::fs_builder &bld,
273 fs_reg color1, fs_reg color2,
274 fs_reg src0_alpha, unsigned components);
275 void emit_fb_writes();
276 void emit_urb_writes();
277 void emit_cs_terminate();
278 fs_reg *emit_cs_local_invocation_id_setup();
279 fs_reg *emit_cs_work_group_id_setup();
280
281 void emit_barrier();
282
283 void emit_shader_time_begin();
284 void emit_shader_time_end();
285 void SHADER_TIME_ADD(const brw::fs_builder &bld,
286 int shader_time_subindex,
287 fs_reg value);
288
289 fs_reg get_timestamp(const brw::fs_builder &bld);
290
291 struct brw_reg interp_reg(int location, int channel);
292
293 int implied_mrf_writes(fs_inst *inst);
294
295 virtual void dump_instructions();
296 virtual void dump_instructions(const char *name);
297 void dump_instruction(backend_instruction *inst);
298 void dump_instruction(backend_instruction *inst, FILE *file);
299
300 const void *const key;
301 const struct brw_sampler_prog_key_data *key_tex;
302
303 struct brw_stage_prog_data *prog_data;
304 unsigned int sanity_param_count;
305
306 int *param_size;
307
308 int *virtual_grf_start;
309 int *virtual_grf_end;
310 brw::fs_live_variables *live_intervals;
311
312 int *regs_live_at_ip;
313
314 /** Number of uniform variable components visited. */
315 unsigned uniforms;
316
317 /** Byte-offset for the next available spot in the scratch space buffer. */
318 unsigned last_scratch;
319
320 /**
321 * Array mapping UNIFORM register numbers to the pull parameter index,
322 * or -1 if this uniform register isn't being uploaded as a pull constant.
323 */
324 int *pull_constant_loc;
325
326 /**
327 * Array mapping UNIFORM register numbers to the push parameter index,
328 * or -1 if this uniform register isn't being uploaded as a push constant.
329 */
330 int *push_constant_loc;
331
332 fs_reg frag_depth;
333 fs_reg sample_mask;
334 fs_reg outputs[VARYING_SLOT_MAX];
335 unsigned output_components[VARYING_SLOT_MAX];
336 fs_reg dual_src_output;
337 bool do_dual_src;
338 int first_non_payload_grf;
339 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
340 unsigned max_grf;
341
342 fs_reg *nir_locals;
343 fs_reg *nir_ssa_values;
344 fs_reg nir_inputs;
345 fs_reg nir_outputs;
346 fs_reg *nir_system_values;
347
348 bool failed;
349 char *fail_msg;
350 bool simd16_unsupported;
351 char *no16_msg;
352
353 /* Result of last visit() method. Still used by emit_texture() */
354 fs_reg result;
355
356 /** Register numbers for thread payload fields. */
357 struct thread_payload {
358 uint8_t source_depth_reg;
359 uint8_t source_w_reg;
360 uint8_t aa_dest_stencil_reg;
361 uint8_t dest_depth_reg;
362 uint8_t sample_pos_reg;
363 uint8_t sample_mask_in_reg;
364 uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
365 uint8_t local_invocation_id_reg;
366
367 /** The number of thread payload registers the hardware will supply. */
368 uint8_t num_regs;
369 } payload;
370
371 bool source_depth_to_render_target;
372 bool runtime_check_aads_emit;
373
374 fs_reg pixel_x;
375 fs_reg pixel_y;
376 fs_reg wpos_w;
377 fs_reg pixel_w;
378 fs_reg delta_xy[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
379 fs_reg shader_start_time;
380 fs_reg userplane[MAX_CLIP_PLANES];
381
382 unsigned grf_used;
383 bool spilled_any_registers;
384
385 const unsigned dispatch_width; /**< 8 or 16 */
386
387 int shader_time_index;
388
389 unsigned promoted_constants;
390 brw::fs_builder bld;
391 };
392
393 /**
394 * The fragment shader code generator.
395 *
396 * Translates FS IR to actual i965 assembly code.
397 */
398 class fs_generator
399 {
400 public:
401 fs_generator(const struct brw_compiler *compiler, void *log_data,
402 void *mem_ctx,
403 const void *key,
404 struct brw_stage_prog_data *prog_data,
405 struct gl_program *fp,
406 unsigned promoted_constants,
407 bool runtime_check_aads_emit,
408 const char *stage_abbrev);
409 ~fs_generator();
410
411 void enable_debug(const char *shader_name);
412 int generate_code(const cfg_t *cfg, int dispatch_width);
413 const unsigned *get_assembly(unsigned int *assembly_size);
414
415 private:
416 void fire_fb_write(fs_inst *inst,
417 struct brw_reg payload,
418 struct brw_reg implied_header,
419 GLuint nr);
420 void generate_fb_write(fs_inst *inst, struct brw_reg payload);
421 void generate_urb_write(fs_inst *inst, struct brw_reg payload);
422 void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
423 void generate_barrier(fs_inst *inst, struct brw_reg src);
424 void generate_blorp_fb_write(fs_inst *inst);
425 void generate_linterp(fs_inst *inst, struct brw_reg dst,
426 struct brw_reg *src);
427 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
428 struct brw_reg sampler_index);
429 void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst,
430 struct brw_reg src,
431 struct brw_reg surf_index);
432 void generate_math_gen6(fs_inst *inst,
433 struct brw_reg dst,
434 struct brw_reg src0,
435 struct brw_reg src1);
436 void generate_math_gen4(fs_inst *inst,
437 struct brw_reg dst,
438 struct brw_reg src);
439 void generate_math_g45(fs_inst *inst,
440 struct brw_reg dst,
441 struct brw_reg src);
442 void generate_ddx(enum opcode op, struct brw_reg dst, struct brw_reg src);
443 void generate_ddy(enum opcode op, struct brw_reg dst, struct brw_reg src,
444 bool negate_value);
445 void generate_scratch_write(fs_inst *inst, struct brw_reg src);
446 void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
447 void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
448 void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
449 struct brw_reg index,
450 struct brw_reg offset);
451 void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
452 struct brw_reg dst,
453 struct brw_reg surf_index,
454 struct brw_reg offset);
455 void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
456 struct brw_reg index,
457 struct brw_reg offset);
458 void generate_varying_pull_constant_load_gen7(fs_inst *inst,
459 struct brw_reg dst,
460 struct brw_reg index,
461 struct brw_reg offset);
462 void generate_mov_dispatch_to_flags(fs_inst *inst);
463
464 void generate_pixel_interpolator_query(fs_inst *inst,
465 struct brw_reg dst,
466 struct brw_reg src,
467 struct brw_reg msg_data,
468 unsigned msg_type);
469
470 void generate_set_sample_id(fs_inst *inst,
471 struct brw_reg dst,
472 struct brw_reg src0,
473 struct brw_reg src1);
474
475 void generate_set_simd4x2_offset(fs_inst *inst,
476 struct brw_reg dst,
477 struct brw_reg offset);
478 void generate_discard_jump(fs_inst *inst);
479
480 void generate_pack_half_2x16_split(fs_inst *inst,
481 struct brw_reg dst,
482 struct brw_reg x,
483 struct brw_reg y);
484 void generate_unpack_half_2x16_split(fs_inst *inst,
485 struct brw_reg dst,
486 struct brw_reg src);
487
488 void generate_shader_time_add(fs_inst *inst,
489 struct brw_reg payload,
490 struct brw_reg offset,
491 struct brw_reg value);
492
493 bool patch_discard_jumps_to_fb_writes();
494
495 const struct brw_compiler *compiler;
496 void *log_data; /* Passed to compiler->*_log functions */
497
498 const struct brw_device_info *devinfo;
499
500 struct brw_codegen *p;
501 const void * const key;
502 struct brw_stage_prog_data * const prog_data;
503
504 const struct gl_program *prog;
505
506 unsigned dispatch_width; /**< 8 or 16 */
507
508 exec_list discard_halt_patches;
509 unsigned promoted_constants;
510 bool runtime_check_aads_emit;
511 bool debug_flag;
512 const char *shader_name;
513 const char *stage_abbrev;
514 void *mem_ctx;
515 };
516
517 bool brw_do_channel_expressions(struct exec_list *instructions);
518 bool brw_do_vector_splitting(struct exec_list *instructions);