src/mesa/drivers/dri/i965/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29
  30 #include "brw_shader.h"
  31
  32 extern "C" {
  33
  34 #include <sys/types.h>
  35
  36 #include "main/macros.h"
  37 #include "main/shaderobj.h"
  38 #include "main/uniforms.h"
  39 #include "program/prog_parameter.h"
  40 #include "program/prog_print.h"
  41 #include "program/prog_optimize.h"
  42 #include "util/register_allocate.h"
  43 #include "program/sampler.h"
  44 #include "program/hash_table.h"
  45 #include "brw_context.h"
  46 #include "brw_eu.h"
  47 #include "brw_wm.h"
  48 #include "brw_shader.h"
  49 #include "intel_asm_annotation.h"
  50 }
  51 #include "glsl/glsl_types.h"
  52 #include "glsl/ir.h"
  53
  54 #define MAX_SAMPLER_MESSAGE_SIZE 11
  55 #define MAX_VGRF_SIZE 16
  56
  57 struct bblock_t;
  58 namespace {
  59    struct acp_entry;
  60 }
  61
  62 namespace brw {
  63    class fs_live_variables;
  64 }
  65
  66 class fs_inst;
  67 class fs_visitor;
  68
  69 class fs_reg : public backend_reg {
  70 public:
  71    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  72
  73    void init();
  74
  75    fs_reg();
  76    explicit fs_reg(float f);
  77    explicit fs_reg(int32_t i);
  78    explicit fs_reg(uint32_t u);
  79    explicit fs_reg(uint8_t vf[4]);
  80    explicit fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3);
  81    fs_reg(struct brw_reg fixed_hw_reg);
  82    fs_reg(enum register_file file, int reg);
  83    fs_reg(enum register_file file, int reg, enum brw_reg_type type);
  84    fs_reg(enum register_file file, int reg, enum brw_reg_type type, uint8_t width);
  85    fs_reg(fs_visitor *v, const struct glsl_type *type);
  86
  87    bool equals(const fs_reg &r) const;
  88    bool is_contiguous() const;
  89
  90    /** Smear a channel of the reg to all channels. */
  91    fs_reg &set_smear(unsigned subreg);
  92
  93    /**
  94     * Offset in bytes from the start of the register.  Values up to a
  95     * backend_reg::reg_offset unit are valid.
  96     */
  97    int subreg_offset;
  98
  99    fs_reg *reladdr;
 100
 101    /**
 102     * The register width.  This indicates how many hardware values are
 103     * represented by each virtual value.  Valid values are 1, 8, or 16.
 104     * For immediate values, this is 1.  Most of the rest of the time, it
 105     * will be equal to the dispatch width.
 106     */
 107    uint8_t width;
 108
 109    /**
 110     * Returns the effective register width when used as a source in the
 111     * given instruction.  Registers such as uniforms and immediates
 112     * effectively take on the width of the instruction in which they are
 113     * used.
 114     */
 115    uint8_t effective_width;
 116
 117    /** Register region horizontal stride */
 118    uint8_t stride;
 119 };
 120
 121 static inline fs_reg
 122 retype(fs_reg reg, enum brw_reg_type type)
 123 {
 124    reg.fixed_hw_reg.type = reg.type = type;
 125    return reg;
 126 }
 127
 128 static inline fs_reg
 129 byte_offset(fs_reg reg, unsigned delta)
 130 {
 131    switch (reg.file) {
 132    case BAD_FILE:
 133       break;
 134    case GRF:
 135       reg.reg_offset += delta / 32;
 136       break;
 137    case MRF:
 138       reg.reg += delta / 32;
 139       break;
 140    default:
 141       assert(delta == 0);
 142    }
 143    reg.subreg_offset += delta % 32;
 144    return reg;
 145 }
 146
 147 static inline fs_reg
 148 horiz_offset(fs_reg reg, unsigned delta)
 149 {
 150    switch (reg.file) {
 151    case BAD_FILE:
 152    case UNIFORM:
 153    case IMM:
 154       /* These only have a single component that is implicitly splatted.  A
 155        * horizontal offset should be a harmless no-op.
 156        */
 157       break;
 158    case GRF:
 159    case MRF:
 160       return byte_offset(reg, delta * reg.stride * type_sz(reg.type));
 161    default:
 162       assert(delta == 0);
 163    }
 164    return reg;
 165 }
 166
 167 static inline fs_reg
 168 offset(fs_reg reg, unsigned delta)
 169 {
 170    assert(reg.stride > 0);
 171    switch (reg.file) {
 172    case BAD_FILE:
 173       break;
 174    case GRF:
 175    case MRF:
 176       return byte_offset(reg, delta * reg.width * reg.stride * type_sz(reg.type));
 177    case UNIFORM:
 178       reg.reg_offset += delta;
 179       break;
 180    default:
 181       assert(delta == 0);
 182    }
 183    return reg;
 184 }
 185
 186 static inline fs_reg
 187 component(fs_reg reg, unsigned idx)
 188 {
 189    assert(reg.subreg_offset == 0);
 190    assert(idx < reg.width);
 191    reg.subreg_offset = idx * type_sz(reg.type);
 192    reg.width = 1;
 193    return reg;
 194 }
 195
 196 /**
 197  * Get either of the 8-component halves of a 16-component register.
 198  *
 199  * Note: this also works if \c reg represents a SIMD16 pair of registers.
 200  */
 201 static inline fs_reg
 202 half(fs_reg reg, unsigned idx)
 203 {
 204    assert(idx < 2);
 205    assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM));
 206    assert(reg.width == 16);
 207    reg.width = 8;
 208    return horiz_offset(reg, 8 * idx);
 209 }
 210
 211 static const fs_reg reg_undef;
 212
 213 class fs_inst : public backend_instruction {
 214    fs_inst &operator=(const fs_inst &);
 215
 216    void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
 217              fs_reg *src, int sources);
 218
 219 public:
 220    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 221
 222    fs_inst();
 223    fs_inst(enum opcode opcode, uint8_t exec_size);
 224    fs_inst(enum opcode opcode, const fs_reg &dst);
 225    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 226            const fs_reg &src0);
 227    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 228    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 229            const fs_reg &src0, const fs_reg &src1);
 230    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 231            const fs_reg &src1);
 232    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 233            const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 234    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 235            const fs_reg &src1, const fs_reg &src2);
 236    fs_inst(enum opcode opcode, const fs_reg &dst, fs_reg src[], int sources);
 237    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 238            fs_reg src[], int sources);
 239    fs_inst(const fs_inst &that);
 240
 241    void resize_sources(uint8_t num_sources);
 242
 243    bool equals(fs_inst *inst) const;
 244    bool overwrites_reg(const fs_reg &reg) const;
 245    bool is_send_from_grf() const;
 246    bool is_partial_write() const;
 247    int regs_read(fs_visitor *v, int arg) const;
 248    bool can_do_source_mods(struct brw_context *brw);
 249
 250    bool reads_flag() const;
 251    bool writes_flag() const;
 252
 253    fs_reg dst;
 254    fs_reg *src;
 255
 256    uint8_t sources; /**< Number of fs_reg sources. */
 257
 258    /**
 259     * Execution size of the instruction.  This is used by the generator to
 260     * generate the correct binary for the given fs_inst.  Current valid
 261     * values are 1, 8, 16.
 262     */
 263    uint8_t exec_size;
 264
 265    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 266     * mod and predication.
 267     */
 268    uint8_t flag_subreg;
 269
 270    uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
 271    bool eot:1;
 272    bool force_uncompressed:1;
 273    bool force_sechalf:1;
 274    bool pi_noperspective:1;   /**< Pixel interpolator noperspective flag */
 275 };
 276
 277 /**
 278  * The fragment shader front-end.
 279  *
 280  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
 281  */
 282 class fs_visitor : public backend_visitor
 283 {
 284 public:
 285    const fs_reg reg_null_f;
 286    const fs_reg reg_null_d;
 287    const fs_reg reg_null_ud;
 288
 289    fs_visitor(struct brw_context *brw,
 290               void *mem_ctx,
 291               const struct brw_wm_prog_key *key,
 292               struct brw_wm_prog_data *prog_data,
 293               struct gl_shader_program *shader_prog,
 294               struct gl_fragment_program *fp,
 295               unsigned dispatch_width);
 296    ~fs_visitor();
 297    void init();
 298
 299    fs_reg *variable_storage(ir_variable *var);
 300    int virtual_grf_alloc(int size);
 301    void import_uniforms(fs_visitor *v);
 302
 303    void visit(ir_variable *ir);
 304    void visit(ir_assignment *ir);
 305    void visit(ir_dereference_variable *ir);
 306    void visit(ir_dereference_record *ir);
 307    void visit(ir_dereference_array *ir);
 308    void visit(ir_expression *ir);
 309    void visit(ir_texture *ir);
 310    void visit(ir_if *ir);
 311    void visit(ir_constant *ir);
 312    void visit(ir_swizzle *ir);
 313    void visit(ir_return *ir);
 314    void visit(ir_loop *ir);
 315    void visit(ir_loop_jump *ir);
 316    void visit(ir_discard *ir);
 317    void visit(ir_call *ir);
 318    void visit(ir_function *ir);
 319    void visit(ir_function_signature *ir);
 320    void visit(ir_emit_vertex *);
 321    void visit(ir_end_primitive *);
 322
 323    uint32_t gather_channel(int orig_chan, uint32_t sampler);
 324    void swizzle_result(ir_texture_opcode op, int dest_components,
 325                        fs_reg orig_val, uint32_t sampler);
 326
 327    fs_inst *emit(fs_inst *inst);
 328    void emit(exec_list list);
 329
 330    fs_inst *emit(enum opcode opcode);
 331    fs_inst *emit(enum opcode opcode, const fs_reg &dst);
 332    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 333    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 334                  const fs_reg &src1);
 335    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 336                  const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 337    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 338                  fs_reg src[], int sources);
 339
 340    fs_inst *MOV(const fs_reg &dst, const fs_reg &src);
 341    fs_inst *NOT(const fs_reg &dst, const fs_reg &src);
 342    fs_inst *RNDD(const fs_reg &dst, const fs_reg &src);
 343    fs_inst *RNDE(const fs_reg &dst, const fs_reg &src);
 344    fs_inst *RNDZ(const fs_reg &dst, const fs_reg &src);
 345    fs_inst *FRC(const fs_reg &dst, const fs_reg &src);
 346    fs_inst *ADD(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 347    fs_inst *MUL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 348    fs_inst *MACH(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 349    fs_inst *MAC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 350    fs_inst *SHL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 351    fs_inst *SHR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 352    fs_inst *ASR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 353    fs_inst *AND(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 354    fs_inst *OR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 355    fs_inst *XOR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 356    fs_inst *IF(enum brw_predicate predicate);
 357    fs_inst *IF(const fs_reg &src0, const fs_reg &src1,
 358                enum brw_conditional_mod condition);
 359    fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
 360                 enum brw_conditional_mod condition);
 361    fs_inst *LRP(const fs_reg &dst, const fs_reg &a, const fs_reg &y,
 362                 const fs_reg &x);
 363    fs_inst *DEP_RESOLVE_MOV(int grf);
 364    fs_inst *BFREV(const fs_reg &dst, const fs_reg &value);
 365    fs_inst *BFE(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset,
 366                 const fs_reg &value);
 367    fs_inst *BFI1(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset);
 368    fs_inst *BFI2(const fs_reg &dst, const fs_reg &bfi1_dst,
 369                  const fs_reg &insert, const fs_reg &base);
 370    fs_inst *FBH(const fs_reg &dst, const fs_reg &value);
 371    fs_inst *FBL(const fs_reg &dst, const fs_reg &value);
 372    fs_inst *CBIT(const fs_reg &dst, const fs_reg &value);
 373    fs_inst *MAD(const fs_reg &dst, const fs_reg &c, const fs_reg &b,
 374                 const fs_reg &a);
 375    fs_inst *ADDC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 376    fs_inst *SUBB(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 377    fs_inst *SEL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 378
 379    int type_size(const struct glsl_type *type);
 380    fs_inst *get_instruction_generating_reg(fs_inst *start,
 381                                            fs_inst *end,
 382                                            const fs_reg &reg);
 383
 384    fs_inst *LOAD_PAYLOAD(const fs_reg &dst, fs_reg *src, int sources);
 385
 386    exec_list VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
 387                                         const fs_reg &surf_index,
 388                                         const fs_reg &varying_offset,
 389                                         uint32_t const_offset);
 390
 391    bool run();
 392    void optimize();
 393    void allocate_registers();
 394    void assign_binding_table_offsets();
 395    void setup_payload_gen4();
 396    void setup_payload_gen6();
 397    void assign_curb_setup();
 398    void calculate_urb_setup();
 399    void assign_urb_setup();
 400    bool assign_regs(bool allow_spilling);
 401    void assign_regs_trivial();
 402    void get_used_mrfs(bool *mrf_used);
 403    void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
 404                                    int first_payload_node);
 405    void setup_mrf_hack_interference(struct ra_graph *g,
 406                                     int first_mrf_hack_node);
 407    int choose_spill_reg(struct ra_graph *g);
 408    void spill_reg(int spill_reg);
 409    void split_virtual_grfs();
 410    bool compact_virtual_grfs();
 411    void move_uniform_array_access_to_pull_constants();
 412    void assign_constant_locations();
 413    void demote_pull_constants();
 414    void invalidate_live_intervals();
 415    void calculate_live_intervals();
 416    void calculate_register_pressure();
 417    bool opt_algebraic();
 418    bool opt_cse();
 419    bool opt_cse_local(bblock_t *block);
 420    bool opt_copy_propagate();
 421    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 422    bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
 423    bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
 424                                  exec_list *acp);
 425    void opt_drop_redundant_mov_to_flags();
 426    bool opt_register_renaming();
 427    bool register_coalesce();
 428    bool compute_to_mrf();
 429    bool dead_code_eliminate();
 430    bool remove_duplicate_mrf_writes();
 431    bool virtual_grf_interferes(int a, int b);
 432    void schedule_instructions(instruction_scheduler_mode mode);
 433    void insert_gen4_send_dependency_workarounds();
 434    void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
 435                                                     fs_inst *inst);
 436    void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
 437                                                      fs_inst *inst);
 438    void vfail(const char *msg, va_list args);
 439    void fail(const char *msg, ...);
 440    void no16(const char *msg, ...);
 441    void lower_uniform_pull_constant_loads();
 442    bool lower_load_payload();
 443
 444    void emit_dummy_fs();
 445    void emit_repclear_shader();
 446    fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
 447    fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
 448                          glsl_interp_qualifier interpolation_mode,
 449                          bool is_centroid, bool is_sample);
 450    fs_reg *emit_frontfacing_interpolation();
 451    fs_reg *emit_samplepos_setup();
 452    fs_reg *emit_sampleid_setup();
 453    fs_reg *emit_general_interpolation(ir_variable *ir);
 454    void emit_interpolation_setup_gen4();
 455    void emit_interpolation_setup_gen6();
 456    void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
 457    fs_reg rescale_texcoord(fs_reg coordinate, const glsl_type *coord_type,
 458                            bool is_rect, uint32_t sampler, int texunit);
 459    fs_inst *emit_texture_gen4(ir_texture_opcode op, fs_reg dst,
 460                               fs_reg coordinate, int coord_components,
 461                               fs_reg shadow_comp,
 462                               fs_reg lod, fs_reg lod2, int grad_components,
 463                               uint32_t sampler);
 464    fs_inst *emit_texture_gen5(ir_texture_opcode op, fs_reg dst,
 465                               fs_reg coordinate, int coord_components,
 466                               fs_reg shadow_comp,
 467                               fs_reg lod, fs_reg lod2, int grad_components,
 468                               fs_reg sample_index, uint32_t sampler,
 469                               bool has_offset);
 470    fs_inst *emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
 471                               fs_reg coordinate, int coord_components,
 472                               fs_reg shadow_comp,
 473                               fs_reg lod, fs_reg lod2, int grad_components,
 474                               fs_reg sample_index, fs_reg mcs, fs_reg sampler,
 475                               fs_reg offset_value);
 476    void emit_texture(ir_texture_opcode op,
 477                      const glsl_type *dest_type,
 478                      fs_reg coordinate, const struct glsl_type *coord_type,
 479                      fs_reg shadow_c,
 480                      fs_reg lod, fs_reg dpdy, int grad_components,
 481                      fs_reg sample_index,
 482                      fs_reg offset, unsigned offset_components,
 483                      fs_reg mcs,
 484                      int gather_component,
 485                      bool is_cube_array,
 486                      bool is_rect,
 487                      uint32_t sampler,
 488                      fs_reg sampler_reg,
 489                      int texunit);
 490    fs_reg emit_mcs_fetch(fs_reg coordinate, int components, fs_reg sampler);
 491    void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
 492    fs_reg fix_math_operand(fs_reg src);
 493    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
 494    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
 495    void emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
 496                  const fs_reg &a);
 497    void emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &dst,
 498                     const fs_reg &src0, const fs_reg &src1);
 499    bool try_emit_saturate(ir_expression *ir);
 500    bool try_emit_mad(ir_expression *ir);
 501    void try_replace_with_sel();
 502    bool opt_peephole_sel();
 503    bool opt_peephole_predicated_break();
 504    bool opt_saturate_propagation();
 505    void emit_bool_to_cond_code(ir_rvalue *condition);
 506    void emit_if_gen6(ir_if *ir);
 507    void emit_unspill(bblock_t *block, fs_inst *inst, fs_reg reg,
 508                      uint32_t spill_offset, int count);
 509    void emit_spill(bblock_t *block, fs_inst *inst, fs_reg reg,
 510                    uint32_t spill_offset, int count);
 511
 512    void emit_fragment_program_code();
 513    void setup_fp_regs();
 514    fs_reg get_fp_src_reg(const prog_src_register *src);
 515    fs_reg get_fp_dst_reg(const prog_dst_register *dst);
 516    void emit_fp_alu1(enum opcode opcode,
 517                      const struct prog_instruction *fpi,
 518                      fs_reg dst, fs_reg src);
 519    void emit_fp_alu2(enum opcode opcode,
 520                      const struct prog_instruction *fpi,
 521                      fs_reg dst, fs_reg src0, fs_reg src1);
 522    void emit_fp_scalar_write(const struct prog_instruction *fpi,
 523                              fs_reg dst, fs_reg src);
 524    void emit_fp_scalar_math(enum opcode opcode,
 525                             const struct prog_instruction *fpi,
 526                             fs_reg dst, fs_reg src);
 527
 528    void emit_fp_minmax(const struct prog_instruction *fpi,
 529                        fs_reg dst, fs_reg src0, fs_reg src1);
 530
 531    void emit_fp_sop(enum brw_conditional_mod conditional_mod,
 532                     const struct prog_instruction *fpi,
 533                     fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
 534
 535    int setup_color_payload(fs_reg *dst, fs_reg color, unsigned components);
 536    void emit_alpha_test();
 537    fs_inst *emit_single_fb_write(fs_reg color1, fs_reg color2,
 538                                  fs_reg src0_alpha, unsigned components);
 539    void emit_fb_writes();
 540
 541    void emit_shader_time_begin();
 542    void emit_shader_time_end();
 543    void emit_shader_time_write(enum shader_time_shader_type type,
 544                                fs_reg value);
 545
 546    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 547                             fs_reg dst, fs_reg offset, fs_reg src0,
 548                             fs_reg src1);
 549
 550    void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
 551                                   fs_reg offset);
 552
 553    void emit_interpolate_expression(ir_expression *ir);
 554
 555    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 556                                fs_reg dst,
 557                                fs_reg src,
 558                                fs_inst *pre_rhs_inst,
 559                                fs_inst *last_rhs_inst);
 560    void emit_assignment_writes(fs_reg &l, fs_reg &r,
 561                                const glsl_type *type, bool predicated);
 562    void resolve_ud_negate(fs_reg *reg);
 563    void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
 564
 565    fs_reg get_timestamp();
 566
 567    struct brw_reg interp_reg(int location, int channel);
 568    void setup_uniform_values(ir_variable *ir);
 569    void setup_builtin_uniform_values(ir_variable *ir);
 570    int implied_mrf_writes(fs_inst *inst);
 571
 572    virtual void dump_instructions();
 573    virtual void dump_instructions(const char *name);
 574    void dump_instruction(backend_instruction *inst);
 575    void dump_instruction(backend_instruction *inst, FILE *file);
 576
 577    void visit_atomic_counter_intrinsic(ir_call *ir);
 578
 579    const void *const key;
 580    struct brw_stage_prog_data *prog_data;
 581    unsigned int sanity_param_count;
 582
 583    int *param_size;
 584
 585    int *virtual_grf_sizes;
 586    int virtual_grf_count;
 587    int virtual_grf_array_size;
 588    int *virtual_grf_start;
 589    int *virtual_grf_end;
 590    brw::fs_live_variables *live_intervals;
 591
 592    int *regs_live_at_ip;
 593
 594    /** Number of uniform variable components visited. */
 595    unsigned uniforms;
 596
 597    /** Byte-offset for the next available spot in the scratch space buffer. */
 598    unsigned last_scratch;
 599
 600    /**
 601     * Array mapping UNIFORM register numbers to the pull parameter index,
 602     * or -1 if this uniform register isn't being uploaded as a pull constant.
 603     */
 604    int *pull_constant_loc;
 605
 606    /**
 607     * Array mapping UNIFORM register numbers to the push parameter index,
 608     * or -1 if this uniform register isn't being uploaded as a push constant.
 609     */
 610    int *push_constant_loc;
 611
 612    struct hash_table *variable_ht;
 613    fs_reg frag_depth;
 614    fs_reg sample_mask;
 615    fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
 616    unsigned output_components[BRW_MAX_DRAW_BUFFERS];
 617    fs_reg dual_src_output;
 618    bool do_dual_src;
 619    int first_non_payload_grf;
 620    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 621    int max_grf;
 622
 623    fs_reg *fp_temp_regs;
 624    fs_reg *fp_input_regs;
 625
 626    /** @{ debug annotation info */
 627    const char *current_annotation;
 628    const void *base_ir;
 629    /** @} */
 630
 631    bool failed;
 632    char *fail_msg;
 633    bool simd16_unsupported;
 634    char *no16_msg;
 635
 636    /* Result of last visit() method. */
 637    fs_reg result;
 638
 639    /** Register numbers for thread payload fields. */
 640    struct {
 641       uint8_t source_depth_reg;
 642       uint8_t source_w_reg;
 643       uint8_t aa_dest_stencil_reg;
 644       uint8_t dest_depth_reg;
 645       uint8_t sample_pos_reg;
 646       uint8_t sample_mask_in_reg;
 647       uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 648
 649       /** The number of thread payload registers the hardware will supply. */
 650       uint8_t num_regs;
 651    } payload;
 652
 653    bool source_depth_to_render_target;
 654    bool runtime_check_aads_emit;
 655
 656    fs_reg pixel_x;
 657    fs_reg pixel_y;
 658    fs_reg wpos_w;
 659    fs_reg pixel_w;
 660    fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 661    fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 662    fs_reg shader_start_time;
 663
 664    int grf_used;
 665    bool spilled_any_registers;
 666
 667    const unsigned dispatch_width; /**< 8 or 16 */
 668 };
 669
 670 /**
 671  * The fragment shader code generator.
 672  *
 673  * Translates FS IR to actual i965 assembly code.
 674  */
 675 class fs_generator
 676 {
 677 public:
 678    fs_generator(struct brw_context *brw,
 679                 void *mem_ctx,
 680                 const struct brw_wm_prog_key *key,
 681                 struct brw_wm_prog_data *prog_data,
 682                 struct gl_shader_program *shader_prog,
 683                 struct gl_fragment_program *fp,
 684                 bool runtime_check_aads_emit,
 685                 bool debug_flag);
 686    ~fs_generator();
 687
 688    int generate_code(const cfg_t *cfg, int dispatch_width);
 689    const unsigned *get_assembly(unsigned int *assembly_size);
 690
 691 private:
 692    void fire_fb_write(fs_inst *inst,
 693                       struct brw_reg payload,
 694                       struct brw_reg implied_header,
 695                       GLuint nr);
 696    void generate_fb_write(fs_inst *inst, struct brw_reg payload);
 697    void generate_blorp_fb_write(fs_inst *inst);
 698    void generate_pixel_xy(struct brw_reg dst, bool is_x);
 699    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 700                          struct brw_reg *src);
 701    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 702                      struct brw_reg sampler_index);
 703    void generate_math_gen6(fs_inst *inst,
 704                            struct brw_reg dst,
 705                            struct brw_reg src0,
 706                            struct brw_reg src1);
 707    void generate_math_gen4(fs_inst *inst,
 708                            struct brw_reg dst,
 709                            struct brw_reg src);
 710    void generate_math_g45(fs_inst *inst,
 711                           struct brw_reg dst,
 712                           struct brw_reg src);
 713    void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src, struct brw_reg quality);
 714    void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 715                      struct brw_reg quality, bool negate_value);
 716    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 717    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 718    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 719    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 720                                             struct brw_reg index,
 721                                             struct brw_reg offset);
 722    void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
 723                                                  struct brw_reg dst,
 724                                                  struct brw_reg surf_index,
 725                                                  struct brw_reg offset);
 726    void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 727                                             struct brw_reg index,
 728                                             struct brw_reg offset);
 729    void generate_varying_pull_constant_load_gen7(fs_inst *inst,
 730                                                  struct brw_reg dst,
 731                                                  struct brw_reg index,
 732                                                  struct brw_reg offset);
 733    void generate_mov_dispatch_to_flags(fs_inst *inst);
 734
 735    void generate_pixel_interpolator_query(fs_inst *inst,
 736                                           struct brw_reg dst,
 737                                           struct brw_reg src,
 738                                           struct brw_reg msg_data,
 739                                           unsigned msg_type);
 740
 741    void generate_set_omask(fs_inst *inst,
 742                            struct brw_reg dst,
 743                            struct brw_reg sample_mask);
 744
 745    void generate_set_sample_id(fs_inst *inst,
 746                                struct brw_reg dst,
 747                                struct brw_reg src0,
 748                                struct brw_reg src1);
 749
 750    void generate_set_simd4x2_offset(fs_inst *inst,
 751                                     struct brw_reg dst,
 752                                     struct brw_reg offset);
 753    void generate_discard_jump(fs_inst *inst);
 754
 755    void generate_pack_half_2x16_split(fs_inst *inst,
 756                                       struct brw_reg dst,
 757                                       struct brw_reg x,
 758                                       struct brw_reg y);
 759    void generate_unpack_half_2x16_split(fs_inst *inst,
 760                                         struct brw_reg dst,
 761                                         struct brw_reg src);
 762
 763    void generate_shader_time_add(fs_inst *inst,
 764                                  struct brw_reg payload,
 765                                  struct brw_reg offset,
 766                                  struct brw_reg value);
 767
 768    void generate_untyped_atomic(fs_inst *inst,
 769                                 struct brw_reg dst,
 770                                 struct brw_reg payload,
 771                                 struct brw_reg atomic_op,
 772                                 struct brw_reg surf_index);
 773
 774    void generate_untyped_surface_read(fs_inst *inst,
 775                                       struct brw_reg dst,
 776                                       struct brw_reg payload,
 777                                       struct brw_reg surf_index);
 778
 779    bool patch_discard_jumps_to_fb_writes();
 780
 781    struct brw_context *brw;
 782    struct gl_context *ctx;
 783
 784    struct brw_compile *p;
 785    gl_shader_stage stage;
 786    const void * const key;
 787    struct brw_stage_prog_data * const prog_data;
 788
 789    struct gl_shader_program * const shader_prog;
 790    const struct gl_program *prog;
 791
 792    unsigned dispatch_width; /**< 8 or 16 */
 793
 794    exec_list discard_halt_patches;
 795    bool runtime_check_aads_emit;
 796    const bool debug_flag;
 797    void *mem_ctx;
 798 };
 799
 800 bool brw_do_channel_expressions(struct exec_list *instructions);
 801 bool brw_do_vector_splitting(struct exec_list *instructions);
 802
 803 struct brw_reg brw_reg_from_fs_reg(fs_reg *reg);