src/mesa/drivers/dri/i965/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29
  30 #include "brw_shader.h"
  31 #include "brw_ir_fs.h"
  32 #include "brw_fs_builder.h"
  33
  34 extern "C" {
  35
  36 #include <sys/types.h>
  37
  38 #include "main/macros.h"
  39 #include "main/shaderobj.h"
  40 #include "main/uniforms.h"
  41 #include "program/prog_parameter.h"
  42 #include "program/prog_print.h"
  43 #include "program/prog_optimize.h"
  44 #include "util/register_allocate.h"
  45 #include "program/hash_table.h"
  46 #include "brw_context.h"
  47 #include "brw_eu.h"
  48 #include "brw_wm.h"
  49 #include "intel_asm_annotation.h"
  50 }
  51 #include "glsl/glsl_types.h"
  52 #include "glsl/ir.h"
  53 #include "glsl/nir/nir.h"
  54 #include "program/sampler.h"
  55
  56 struct bblock_t;
  57 namespace {
  58    struct acp_entry;
  59 }
  60
  61 namespace brw {
  62    class fs_live_variables;
  63 }
  64
  65 /**
  66  * The fragment shader front-end.
  67  *
  68  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
  69  */
  70 class fs_visitor : public backend_shader
  71 {
  72 public:
  73    const fs_reg reg_null_f;
  74    const fs_reg reg_null_d;
  75    const fs_reg reg_null_ud;
  76
  77    fs_visitor(struct brw_context *brw,
  78               void *mem_ctx,
  79               gl_shader_stage stage,
  80               const void *key,
  81               struct brw_stage_prog_data *prog_data,
  82               struct gl_shader_program *shader_prog,
  83               struct gl_program *prog,
  84               unsigned dispatch_width);
  85
  86    ~fs_visitor();
  87
  88    fs_reg vgrf(const glsl_type *const type);
  89    fs_reg vgrf(int num_components);
  90    void import_uniforms(fs_visitor *v);
  91    void setup_uniform_clipplane_values();
  92    void compute_clip_distance();
  93
  94    uint32_t gather_channel(int orig_chan, uint32_t sampler);
  95    void swizzle_result(ir_texture_opcode op, int dest_components,
  96                        fs_reg orig_val, uint32_t sampler);
  97
  98    fs_inst *emit(fs_inst *inst);
  99    void emit(exec_list list);
 100
 101    fs_inst *emit(enum opcode opcode);
 102    fs_inst *emit(enum opcode opcode, const fs_reg &dst);
 103    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 104    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 105                  const fs_reg &src1);
 106    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 107                  const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 108    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 109                  fs_reg src[], int sources);
 110
 111    fs_inst *MOV(const fs_reg &dst, const fs_reg &src);
 112    fs_inst *NOT(const fs_reg &dst, const fs_reg &src);
 113    fs_inst *RNDD(const fs_reg &dst, const fs_reg &src);
 114    fs_inst *RNDE(const fs_reg &dst, const fs_reg &src);
 115    fs_inst *RNDZ(const fs_reg &dst, const fs_reg &src);
 116    fs_inst *FRC(const fs_reg &dst, const fs_reg &src);
 117    fs_inst *ADD(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 118    fs_inst *MUL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 119    fs_inst *MACH(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 120    fs_inst *MAC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 121    fs_inst *SHL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 122    fs_inst *SHR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 123    fs_inst *ASR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 124    fs_inst *AND(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 125    fs_inst *OR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 126    fs_inst *XOR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 127    fs_inst *IF(enum brw_predicate predicate);
 128    fs_inst *IF(const fs_reg &src0, const fs_reg &src1,
 129                enum brw_conditional_mod condition);
 130    fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
 131                 enum brw_conditional_mod condition);
 132    fs_inst *LRP(const fs_reg &dst, const fs_reg &a, const fs_reg &y,
 133                 const fs_reg &x);
 134    fs_inst *BFREV(const fs_reg &dst, const fs_reg &value);
 135    fs_inst *BFE(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset,
 136                 const fs_reg &value);
 137    fs_inst *BFI1(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset);
 138    fs_inst *BFI2(const fs_reg &dst, const fs_reg &bfi1_dst,
 139                  const fs_reg &insert, const fs_reg &base);
 140    fs_inst *FBH(const fs_reg &dst, const fs_reg &value);
 141    fs_inst *FBL(const fs_reg &dst, const fs_reg &value);
 142    fs_inst *CBIT(const fs_reg &dst, const fs_reg &value);
 143    fs_inst *MAD(const fs_reg &dst, const fs_reg &c, const fs_reg &b,
 144                 const fs_reg &a);
 145    fs_inst *ADDC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 146    fs_inst *SUBB(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 147    fs_inst *SEL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 148
 149    int type_size(const struct glsl_type *type);
 150    fs_inst *get_instruction_generating_reg(fs_inst *start,
 151                                            fs_inst *end,
 152                                            const fs_reg &reg);
 153
 154    fs_inst *LOAD_PAYLOAD(const fs_reg &dst, fs_reg *src, int sources,
 155                          int header_size);
 156
 157    exec_list VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
 158                                         const fs_reg &surf_index,
 159                                         const fs_reg &varying_offset,
 160                                         uint32_t const_offset);
 161    void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf);
 162
 163    bool run_fs();
 164    bool run_vs();
 165    bool run_cs();
 166    void optimize();
 167    void allocate_registers();
 168    void assign_binding_table_offsets();
 169    void setup_payload_gen4();
 170    void setup_payload_gen6();
 171    void setup_vs_payload();
 172    void setup_cs_payload();
 173    void fixup_3src_null_dest();
 174    void assign_curb_setup();
 175    void calculate_urb_setup();
 176    void assign_urb_setup();
 177    void assign_vs_urb_setup();
 178    bool assign_regs(bool allow_spilling);
 179    void assign_regs_trivial();
 180    void get_used_mrfs(bool *mrf_used);
 181    void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
 182                                    int first_payload_node);
 183    void setup_mrf_hack_interference(struct ra_graph *g,
 184                                     int first_mrf_hack_node);
 185    int choose_spill_reg(struct ra_graph *g);
 186    void spill_reg(int spill_reg);
 187    void split_virtual_grfs();
 188    bool compact_virtual_grfs();
 189    void move_uniform_array_access_to_pull_constants();
 190    void assign_constant_locations();
 191    void demote_pull_constants();
 192    void invalidate_live_intervals();
 193    void calculate_live_intervals();
 194    void calculate_register_pressure();
 195    bool opt_algebraic();
 196    bool opt_redundant_discard_jumps();
 197    bool opt_cse();
 198    bool opt_cse_local(bblock_t *block);
 199    bool opt_copy_propagate();
 200    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 201    bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
 202    bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
 203                                  exec_list *acp);
 204    bool opt_register_renaming();
 205    bool register_coalesce();
 206    bool compute_to_mrf();
 207    bool eliminate_find_live_channel();
 208    bool dead_code_eliminate();
 209    bool remove_duplicate_mrf_writes();
 210
 211    bool opt_sampler_eot();
 212    bool virtual_grf_interferes(int a, int b);
 213    void schedule_instructions(instruction_scheduler_mode mode);
 214    void insert_gen4_send_dependency_workarounds();
 215    void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
 216                                                     fs_inst *inst);
 217    void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
 218                                                      fs_inst *inst);
 219    void vfail(const char *msg, va_list args);
 220    void fail(const char *msg, ...);
 221    void no16(const char *msg, ...);
 222    void lower_uniform_pull_constant_loads();
 223    bool lower_load_payload();
 224    bool lower_integer_multiplication();
 225    bool opt_combine_constants();
 226
 227    void emit_dummy_fs();
 228    void emit_repclear_shader();
 229    fs_reg *emit_fragcoord_interpolation(bool pixel_center_integer,
 230                                         bool origin_upper_left);
 231    fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
 232                          glsl_interp_qualifier interpolation_mode,
 233                          bool is_centroid, bool is_sample);
 234    fs_reg *emit_frontfacing_interpolation();
 235    fs_reg *emit_samplepos_setup();
 236    fs_reg *emit_sampleid_setup();
 237    void emit_general_interpolation(fs_reg attr, const char *name,
 238                                    const glsl_type *type,
 239                                    glsl_interp_qualifier interpolation_mode,
 240                                    int location, bool mod_centroid,
 241                                    bool mod_sample);
 242    fs_reg *emit_vs_system_value(int location);
 243    void emit_interpolation_setup_gen4();
 244    void emit_interpolation_setup_gen6();
 245    void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
 246    fs_reg rescale_texcoord(fs_reg coordinate, int coord_components,
 247                            bool is_rect, uint32_t sampler, int texunit);
 248    fs_inst *emit_texture_gen4(ir_texture_opcode op, fs_reg dst,
 249                               fs_reg coordinate, int coord_components,
 250                               fs_reg shadow_comp,
 251                               fs_reg lod, fs_reg lod2, int grad_components,
 252                               uint32_t sampler);
 253    fs_inst *emit_texture_gen4_simd16(ir_texture_opcode op, fs_reg dst,
 254                                      fs_reg coordinate, int vector_elements,
 255                                      fs_reg shadow_c, fs_reg lod,
 256                                      uint32_t sampler);
 257    fs_inst *emit_texture_gen5(ir_texture_opcode op, fs_reg dst,
 258                               fs_reg coordinate, int coord_components,
 259                               fs_reg shadow_comp,
 260                               fs_reg lod, fs_reg lod2, int grad_components,
 261                               fs_reg sample_index, uint32_t sampler,
 262                               bool has_offset);
 263    fs_inst *emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
 264                               fs_reg coordinate, int coord_components,
 265                               fs_reg shadow_comp,
 266                               fs_reg lod, fs_reg lod2, int grad_components,
 267                               fs_reg sample_index, fs_reg mcs, fs_reg sampler,
 268                               fs_reg offset_value);
 269    void emit_texture(ir_texture_opcode op,
 270                      const glsl_type *dest_type,
 271                      fs_reg coordinate, int components,
 272                      fs_reg shadow_c,
 273                      fs_reg lod, fs_reg dpdy, int grad_components,
 274                      fs_reg sample_index,
 275                      fs_reg offset,
 276                      fs_reg mcs,
 277                      int gather_component,
 278                      bool is_cube_array,
 279                      bool is_rect,
 280                      uint32_t sampler,
 281                      fs_reg sampler_reg,
 282                      int texunit);
 283    fs_reg emit_mcs_fetch(fs_reg coordinate, int components, fs_reg sampler);
 284    void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
 285    void resolve_source_modifiers(fs_reg *src);
 286    fs_reg fix_math_operand(fs_reg src);
 287    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
 288    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
 289    fs_inst *emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
 290                      const fs_reg &a);
 291    void emit_discard_jump();
 292    /** Copy any live channel from \p src to the first channel of \p dst. */
 293    void emit_uniformize(const fs_reg &dst, const fs_reg &src);
 294    bool try_replace_with_sel();
 295    bool opt_peephole_sel();
 296    bool opt_peephole_predicated_break();
 297    bool opt_saturate_propagation();
 298    bool opt_cmod_propagation();
 299    bool opt_zero_samples();
 300    void emit_unspill(bblock_t *block, fs_inst *inst, fs_reg reg,
 301                      uint32_t spill_offset, int count);
 302    void emit_spill(bblock_t *block, fs_inst *inst, fs_reg reg,
 303                    uint32_t spill_offset, int count);
 304
 305    void emit_nir_code();
 306    void nir_setup_inputs(nir_shader *shader);
 307    void nir_setup_outputs(nir_shader *shader);
 308    void nir_setup_uniforms(nir_shader *shader);
 309    void nir_setup_uniform(nir_variable *var);
 310    void nir_setup_builtin_uniform(nir_variable *var);
 311    void nir_emit_system_values(nir_shader *shader);
 312    void nir_emit_impl(nir_function_impl *impl);
 313    void nir_emit_cf_list(exec_list *list);
 314    void nir_emit_if(nir_if *if_stmt);
 315    void nir_emit_loop(nir_loop *loop);
 316    void nir_emit_block(nir_block *block);
 317    void nir_emit_instr(nir_instr *instr);
 318    void nir_emit_alu(nir_alu_instr *instr);
 319    void nir_emit_intrinsic(nir_intrinsic_instr *instr);
 320    void nir_emit_texture(nir_tex_instr *instr);
 321    void nir_emit_jump(nir_jump_instr *instr);
 322    fs_reg get_nir_src(nir_src src);
 323    fs_reg get_nir_dest(nir_dest dest);
 324    void emit_percomp(fs_inst *inst, unsigned wr_mask);
 325
 326    bool optimize_frontfacing_ternary(nir_alu_instr *instr,
 327                                      const fs_reg &result);
 328
 329    void setup_color_payload(fs_reg *dst, fs_reg color, unsigned components,
 330                             unsigned exec_size, bool use_2nd_half);
 331    void emit_alpha_test();
 332    fs_inst *emit_single_fb_write(fs_reg color1, fs_reg color2,
 333                                  fs_reg src0_alpha, unsigned components,
 334                                  unsigned exec_size, bool use_2nd_half = false);
 335    void emit_fb_writes();
 336    void emit_urb_writes();
 337    void emit_cs_terminate();
 338
 339    void emit_shader_time_begin();
 340    void emit_shader_time_end();
 341    fs_inst *SHADER_TIME_ADD(enum shader_time_shader_type type, fs_reg value);
 342
 343    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 344                             fs_reg dst, fs_reg offset, fs_reg src0,
 345                             fs_reg src1);
 346
 347    void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
 348                                   fs_reg offset);
 349
 350    void resolve_ud_negate(fs_reg *reg);
 351
 352    fs_reg get_timestamp(fs_inst **out_mov);
 353
 354    struct brw_reg interp_reg(int location, int channel);
 355    int implied_mrf_writes(fs_inst *inst);
 356
 357    virtual void dump_instructions();
 358    virtual void dump_instructions(const char *name);
 359    void dump_instruction(backend_instruction *inst);
 360    void dump_instruction(backend_instruction *inst, FILE *file);
 361
 362    const void *const key;
 363    const struct brw_sampler_prog_key_data *key_tex;
 364
 365    struct brw_stage_prog_data *prog_data;
 366    unsigned int sanity_param_count;
 367
 368    int *param_size;
 369
 370    int *virtual_grf_start;
 371    int *virtual_grf_end;
 372    brw::fs_live_variables *live_intervals;
 373
 374    int *regs_live_at_ip;
 375
 376    /** Number of uniform variable components visited. */
 377    unsigned uniforms;
 378
 379    /** Total number of direct uniforms we can get from NIR */
 380    unsigned num_direct_uniforms;
 381
 382    /** Byte-offset for the next available spot in the scratch space buffer. */
 383    unsigned last_scratch;
 384
 385    /**
 386     * Array mapping UNIFORM register numbers to the pull parameter index,
 387     * or -1 if this uniform register isn't being uploaded as a pull constant.
 388     */
 389    int *pull_constant_loc;
 390
 391    /**
 392     * Array mapping UNIFORM register numbers to the push parameter index,
 393     * or -1 if this uniform register isn't being uploaded as a push constant.
 394     */
 395    int *push_constant_loc;
 396
 397    fs_reg frag_depth;
 398    fs_reg sample_mask;
 399    fs_reg outputs[VARYING_SLOT_MAX];
 400    unsigned output_components[VARYING_SLOT_MAX];
 401    fs_reg dual_src_output;
 402    bool do_dual_src;
 403    int first_non_payload_grf;
 404    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 405    unsigned max_grf;
 406
 407    fs_reg *nir_locals;
 408    fs_reg *nir_globals;
 409    fs_reg nir_inputs;
 410    fs_reg nir_outputs;
 411    fs_reg *nir_system_values;
 412
 413    /** @{ debug annotation info */
 414    const char *current_annotation;
 415    const void *base_ir;
 416    /** @} */
 417
 418    bool failed;
 419    char *fail_msg;
 420    bool simd16_unsupported;
 421    char *no16_msg;
 422
 423    /* Result of last visit() method. Still used by emit_texture() */
 424    fs_reg result;
 425
 426    /** Register numbers for thread payload fields. */
 427    struct {
 428       uint8_t source_depth_reg;
 429       uint8_t source_w_reg;
 430       uint8_t aa_dest_stencil_reg;
 431       uint8_t dest_depth_reg;
 432       uint8_t sample_pos_reg;
 433       uint8_t sample_mask_in_reg;
 434       uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 435
 436       /** The number of thread payload registers the hardware will supply. */
 437       uint8_t num_regs;
 438    } payload;
 439
 440    bool source_depth_to_render_target;
 441    bool runtime_check_aads_emit;
 442
 443    fs_reg pixel_x;
 444    fs_reg pixel_y;
 445    fs_reg wpos_w;
 446    fs_reg pixel_w;
 447    fs_reg delta_xy[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 448    fs_reg shader_start_time;
 449    fs_reg userplane[MAX_CLIP_PLANES];
 450
 451    unsigned grf_used;
 452    bool spilled_any_registers;
 453
 454    const unsigned dispatch_width; /**< 8 or 16 */
 455
 456    unsigned promoted_constants;
 457    brw::fs_builder bld;
 458 };
 459
 460 /**
 461  * The fragment shader code generator.
 462  *
 463  * Translates FS IR to actual i965 assembly code.
 464  */
 465 class fs_generator
 466 {
 467 public:
 468    fs_generator(struct brw_context *brw,
 469                 void *mem_ctx,
 470                 const void *key,
 471                 struct brw_stage_prog_data *prog_data,
 472                 struct gl_program *fp,
 473                 unsigned promoted_constants,
 474                 bool runtime_check_aads_emit,
 475                 const char *stage_abbrev);
 476    ~fs_generator();
 477
 478    void enable_debug(const char *shader_name);
 479    int generate_code(const cfg_t *cfg, int dispatch_width);
 480    const unsigned *get_assembly(unsigned int *assembly_size);
 481
 482 private:
 483    void fire_fb_write(fs_inst *inst,
 484                       struct brw_reg payload,
 485                       struct brw_reg implied_header,
 486                       GLuint nr);
 487    void generate_fb_write(fs_inst *inst, struct brw_reg payload);
 488    void generate_urb_write(fs_inst *inst, struct brw_reg payload);
 489    void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
 490    void generate_blorp_fb_write(fs_inst *inst);
 491    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 492                          struct brw_reg *src);
 493    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 494                      struct brw_reg sampler_index);
 495    void generate_math_gen6(fs_inst *inst,
 496                            struct brw_reg dst,
 497                            struct brw_reg src0,
 498                            struct brw_reg src1);
 499    void generate_math_gen4(fs_inst *inst,
 500                            struct brw_reg dst,
 501                            struct brw_reg src);
 502    void generate_math_g45(fs_inst *inst,
 503                           struct brw_reg dst,
 504                           struct brw_reg src);
 505    void generate_ddx(enum opcode op, struct brw_reg dst, struct brw_reg src);
 506    void generate_ddy(enum opcode op, struct brw_reg dst, struct brw_reg src,
 507                      bool negate_value);
 508    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 509    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 510    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 511    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 512                                             struct brw_reg index,
 513                                             struct brw_reg offset);
 514    void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
 515                                                  struct brw_reg dst,
 516                                                  struct brw_reg surf_index,
 517                                                  struct brw_reg offset);
 518    void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 519                                             struct brw_reg index,
 520                                             struct brw_reg offset);
 521    void generate_varying_pull_constant_load_gen7(fs_inst *inst,
 522                                                  struct brw_reg dst,
 523                                                  struct brw_reg index,
 524                                                  struct brw_reg offset);
 525    void generate_mov_dispatch_to_flags(fs_inst *inst);
 526
 527    void generate_pixel_interpolator_query(fs_inst *inst,
 528                                           struct brw_reg dst,
 529                                           struct brw_reg src,
 530                                           struct brw_reg msg_data,
 531                                           unsigned msg_type);
 532
 533    void generate_set_omask(fs_inst *inst,
 534                            struct brw_reg dst,
 535                            struct brw_reg sample_mask);
 536
 537    void generate_set_sample_id(fs_inst *inst,
 538                                struct brw_reg dst,
 539                                struct brw_reg src0,
 540                                struct brw_reg src1);
 541
 542    void generate_set_simd4x2_offset(fs_inst *inst,
 543                                     struct brw_reg dst,
 544                                     struct brw_reg offset);
 545    void generate_discard_jump(fs_inst *inst);
 546
 547    void generate_pack_half_2x16_split(fs_inst *inst,
 548                                       struct brw_reg dst,
 549                                       struct brw_reg x,
 550                                       struct brw_reg y);
 551    void generate_unpack_half_2x16_split(fs_inst *inst,
 552                                         struct brw_reg dst,
 553                                         struct brw_reg src);
 554
 555    void generate_shader_time_add(fs_inst *inst,
 556                                  struct brw_reg payload,
 557                                  struct brw_reg offset,
 558                                  struct brw_reg value);
 559
 560    bool patch_discard_jumps_to_fb_writes();
 561
 562    struct brw_context *brw;
 563    const struct brw_device_info *devinfo;
 564
 565    struct brw_codegen *p;
 566    const void * const key;
 567    struct brw_stage_prog_data * const prog_data;
 568
 569    const struct gl_program *prog;
 570
 571    unsigned dispatch_width; /**< 8 or 16 */
 572
 573    exec_list discard_halt_patches;
 574    unsigned promoted_constants;
 575    bool runtime_check_aads_emit;
 576    bool debug_flag;
 577    const char *shader_name;
 578    const char *stage_abbrev;
 579    void *mem_ctx;
 580 };
 581
 582 bool brw_do_channel_expressions(struct exec_list *instructions);
 583 bool brw_do_vector_splitting(struct exec_list *instructions);
 584 void brw_setup_tex_for_precompile(struct brw_context *brw,
 585                                   struct brw_sampler_prog_key_data *tex,
 586                                   struct gl_program *prog);