2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include "brw_shader.h"
34 #include <sys/types.h>
36 #include "main/macros.h"
37 #include "main/shaderobj.h"
38 #include "main/uniforms.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/prog_optimize.h"
42 #include "util/register_allocate.h"
43 #include "program/sampler.h"
44 #include "program/hash_table.h"
45 #include "brw_context.h"
48 #include "brw_shader.h"
49 #include "intel_asm_annotation.h"
51 #include "glsl/glsl_types.h"
54 #define MAX_SAMPLER_MESSAGE_SIZE 11
62 class fs_live_variables
;
68 class fs_reg
: public backend_reg
{
70 DECLARE_RALLOC_CXX_OPERATORS(fs_reg
)
75 explicit fs_reg(float f
);
76 explicit fs_reg(int32_t i
);
77 explicit fs_reg(uint32_t u
);
78 fs_reg(struct brw_reg fixed_hw_reg
);
79 fs_reg(enum register_file file
, int reg
);
80 fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
);
81 fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
, uint8_t width
);
82 fs_reg(fs_visitor
*v
, const struct glsl_type
*type
);
84 bool equals(const fs_reg
&r
) const;
85 bool is_valid_3src() const;
86 bool is_contiguous() const;
88 fs_reg
&apply_stride(unsigned stride
);
89 /** Smear a channel of the reg to all channels. */
90 fs_reg
&set_smear(unsigned subreg
);
93 * Offset in bytes from the start of the register. Values up to a
94 * backend_reg::reg_offset unit are valid.
101 * The register width. This indicates how many hardware values are
102 * represented by each virtual value. Valid values are 1, 8, or 16.
103 * For immediate values, this is 1. Most of the rest of the time, it
104 * will be equal to the dispatch width.
109 * Returns the effective register width when used as a source in the
110 * given instruction. Registers such as uniforms and immediates
111 * effectively take on the width of the instruction in which they are
114 uint8_t effective_width
;
116 /** Register region horizontal stride */
121 retype(fs_reg reg
, enum brw_reg_type type
)
123 reg
.fixed_hw_reg
.type
= reg
.type
= type
;
128 byte_offset(fs_reg reg
, unsigned delta
)
134 reg
.reg_offset
+= delta
/ 32;
137 reg
.reg
+= delta
/ 32;
142 reg
.subreg_offset
+= delta
% 32;
147 offset(fs_reg reg
, unsigned delta
)
149 assert(reg
.stride
> 0);
155 return byte_offset(reg
, delta
* reg
.width
* reg
.stride
* type_sz(reg
.type
));
157 reg
.reg_offset
+= delta
;
166 component(fs_reg reg
, unsigned idx
)
168 assert(reg
.subreg_offset
== 0);
169 assert(idx
< reg
.width
);
170 reg
.subreg_offset
= idx
* type_sz(reg
.type
);
176 * Get either of the 8-component halves of a 16-component register.
178 * Note: this also works if \c reg represents a SIMD16 pair of registers.
181 half(fs_reg reg
, unsigned idx
)
184 assert(idx
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
185 assert(reg
.width
== 16);
187 return byte_offset(reg
, 8 * idx
* reg
.stride
* type_sz(reg
.type
));
190 static const fs_reg reg_undef
;
192 class ip_record
: public exec_node
{
194 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
204 class fs_inst
: public backend_instruction
{
205 fs_inst
&operator=(const fs_inst
&);
207 void init(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
208 fs_reg
*src
, int sources
);
211 DECLARE_RALLOC_CXX_OPERATORS(fs_inst
)
214 fs_inst(enum opcode opcode
, uint8_t exec_size
);
215 fs_inst(enum opcode opcode
, const fs_reg
&dst
);
216 fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
218 fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
);
219 fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
220 const fs_reg
&src0
, const fs_reg
&src1
);
221 fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
223 fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
224 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
);
225 fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
226 const fs_reg
&src1
, const fs_reg
&src2
);
227 fs_inst(enum opcode opcode
, const fs_reg
&dst
, fs_reg src
[], int sources
);
228 fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
229 fs_reg src
[], int sources
);
230 fs_inst(const fs_inst
&that
);
232 void resize_sources(uint8_t num_sources
);
234 bool equals(fs_inst
*inst
) const;
235 bool overwrites_reg(const fs_reg
®
) const;
236 bool is_send_from_grf() const;
237 bool is_partial_write() const;
238 int regs_read(fs_visitor
*v
, int arg
) const;
239 bool can_do_source_mods(struct brw_context
*brw
);
241 bool reads_flag() const;
242 bool writes_flag() const;
247 uint8_t sources
; /**< Number of fs_reg sources. */
250 * Execution size of the instruction. This is used by the generator to
251 * generate the correct binary for the given fs_inst. Current valid
252 * values are 1, 8, 16.
256 /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
257 * mod and predication.
261 uint8_t regs_written
; /**< Number of vgrfs written by a SEND message, or 1 */
263 bool header_present
:1;
264 bool shadow_compare
:1;
265 bool force_uncompressed
:1;
266 bool force_sechalf
:1;
267 bool pi_noperspective
:1; /**< Pixel interpolator noperspective flag */
271 * The fragment shader front-end.
273 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
275 class fs_visitor
: public backend_visitor
278 const fs_reg reg_null_f
;
279 const fs_reg reg_null_d
;
280 const fs_reg reg_null_ud
;
282 fs_visitor(struct brw_context
*brw
,
284 const struct brw_wm_prog_key
*key
,
285 struct brw_wm_prog_data
*prog_data
,
286 struct gl_shader_program
*shader_prog
,
287 struct gl_fragment_program
*fp
,
288 unsigned dispatch_width
);
292 fs_reg
*variable_storage(ir_variable
*var
);
293 int virtual_grf_alloc(int size
);
294 void import_uniforms(fs_visitor
*v
);
296 void visit(ir_variable
*ir
);
297 void visit(ir_assignment
*ir
);
298 void visit(ir_dereference_variable
*ir
);
299 void visit(ir_dereference_record
*ir
);
300 void visit(ir_dereference_array
*ir
);
301 void visit(ir_expression
*ir
);
302 void visit(ir_texture
*ir
);
303 void visit(ir_if
*ir
);
304 void visit(ir_constant
*ir
);
305 void visit(ir_swizzle
*ir
);
306 void visit(ir_return
*ir
);
307 void visit(ir_loop
*ir
);
308 void visit(ir_loop_jump
*ir
);
309 void visit(ir_discard
*ir
);
310 void visit(ir_call
*ir
);
311 void visit(ir_function
*ir
);
312 void visit(ir_function_signature
*ir
);
313 void visit(ir_emit_vertex
*);
314 void visit(ir_end_primitive
*);
316 uint32_t gather_channel(ir_texture
*ir
, uint32_t sampler
);
317 void swizzle_result(ir_texture
*ir
, fs_reg orig_val
, uint32_t sampler
);
319 fs_inst
*emit(fs_inst
*inst
);
320 void emit(exec_list list
);
322 fs_inst
*emit(enum opcode opcode
);
323 fs_inst
*emit(enum opcode opcode
, const fs_reg
&dst
);
324 fs_inst
*emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
);
325 fs_inst
*emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
327 fs_inst
*emit(enum opcode opcode
, const fs_reg
&dst
,
328 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
);
329 fs_inst
*emit(enum opcode opcode
, const fs_reg
&dst
,
330 fs_reg src
[], int sources
);
332 fs_inst
*MOV(const fs_reg
&dst
, const fs_reg
&src
);
333 fs_inst
*NOT(const fs_reg
&dst
, const fs_reg
&src
);
334 fs_inst
*RNDD(const fs_reg
&dst
, const fs_reg
&src
);
335 fs_inst
*RNDE(const fs_reg
&dst
, const fs_reg
&src
);
336 fs_inst
*RNDZ(const fs_reg
&dst
, const fs_reg
&src
);
337 fs_inst
*FRC(const fs_reg
&dst
, const fs_reg
&src
);
338 fs_inst
*ADD(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
339 fs_inst
*MUL(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
340 fs_inst
*MACH(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
341 fs_inst
*MAC(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
342 fs_inst
*SHL(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
343 fs_inst
*SHR(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
344 fs_inst
*ASR(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
345 fs_inst
*AND(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
346 fs_inst
*OR(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
347 fs_inst
*XOR(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
348 fs_inst
*IF(enum brw_predicate predicate
);
349 fs_inst
*IF(const fs_reg
&src0
, const fs_reg
&src1
,
350 enum brw_conditional_mod condition
);
351 fs_inst
*CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
,
352 enum brw_conditional_mod condition
);
353 fs_inst
*LRP(const fs_reg
&dst
, const fs_reg
&a
, const fs_reg
&y
,
355 fs_inst
*DEP_RESOLVE_MOV(int grf
);
356 fs_inst
*BFREV(const fs_reg
&dst
, const fs_reg
&value
);
357 fs_inst
*BFE(const fs_reg
&dst
, const fs_reg
&bits
, const fs_reg
&offset
,
358 const fs_reg
&value
);
359 fs_inst
*BFI1(const fs_reg
&dst
, const fs_reg
&bits
, const fs_reg
&offset
);
360 fs_inst
*BFI2(const fs_reg
&dst
, const fs_reg
&bfi1_dst
,
361 const fs_reg
&insert
, const fs_reg
&base
);
362 fs_inst
*FBH(const fs_reg
&dst
, const fs_reg
&value
);
363 fs_inst
*FBL(const fs_reg
&dst
, const fs_reg
&value
);
364 fs_inst
*CBIT(const fs_reg
&dst
, const fs_reg
&value
);
365 fs_inst
*MAD(const fs_reg
&dst
, const fs_reg
&c
, const fs_reg
&b
,
367 fs_inst
*ADDC(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
368 fs_inst
*SUBB(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
369 fs_inst
*SEL(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
371 int type_size(const struct glsl_type
*type
);
372 fs_inst
*get_instruction_generating_reg(fs_inst
*start
,
376 fs_inst
*LOAD_PAYLOAD(const fs_reg
&dst
, fs_reg
*src
, int sources
);
378 exec_list
VARYING_PULL_CONSTANT_LOAD(const fs_reg
&dst
,
379 const fs_reg
&surf_index
,
380 const fs_reg
&varying_offset
,
381 uint32_t const_offset
);
384 void assign_binding_table_offsets();
385 void setup_payload_gen4();
386 void setup_payload_gen6();
387 void assign_curb_setup();
388 void calculate_urb_setup();
389 void assign_urb_setup();
390 bool assign_regs(bool allow_spilling
);
391 void assign_regs_trivial();
392 void get_used_mrfs(bool *mrf_used
);
393 void setup_payload_interference(struct ra_graph
*g
, int payload_reg_count
,
394 int first_payload_node
);
395 void setup_mrf_hack_interference(struct ra_graph
*g
,
396 int first_mrf_hack_node
);
397 int choose_spill_reg(struct ra_graph
*g
);
398 void spill_reg(int spill_reg
);
399 void split_virtual_grfs();
400 bool compact_virtual_grfs();
401 void move_uniform_array_access_to_pull_constants();
402 void assign_constant_locations();
403 void demote_pull_constants();
404 void invalidate_live_intervals();
405 void calculate_live_intervals();
406 void calculate_register_pressure();
407 bool opt_algebraic();
409 bool opt_cse_local(bblock_t
*block
);
410 bool opt_copy_propagate();
411 bool try_copy_propagate(fs_inst
*inst
, int arg
, acp_entry
*entry
);
412 bool try_constant_propagate(fs_inst
*inst
, acp_entry
*entry
);
413 bool opt_copy_propagate_local(void *mem_ctx
, bblock_t
*block
,
415 void opt_drop_redundant_mov_to_flags();
416 bool opt_register_renaming();
417 bool register_coalesce();
418 bool compute_to_mrf();
419 bool dead_code_eliminate();
420 bool remove_duplicate_mrf_writes();
421 bool virtual_grf_interferes(int a
, int b
);
422 void schedule_instructions(instruction_scheduler_mode mode
);
423 void insert_gen4_send_dependency_workarounds();
424 void insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
426 void insert_gen4_post_send_dependency_workarounds(bblock_t
*block
,
428 void vfail(const char *msg
, va_list args
);
429 void fail(const char *msg
, ...);
430 void no16(const char *msg
, ...);
431 void lower_uniform_pull_constant_loads();
432 bool lower_load_payload();
434 void push_force_uncompressed();
435 void pop_force_uncompressed();
437 void emit_dummy_fs();
438 void emit_repclear_shader();
439 fs_reg
*emit_fragcoord_interpolation(ir_variable
*ir
);
440 fs_inst
*emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
441 glsl_interp_qualifier interpolation_mode
,
442 bool is_centroid
, bool is_sample
);
443 fs_reg
*emit_frontfacing_interpolation();
444 fs_reg
*emit_samplepos_setup();
445 fs_reg
*emit_sampleid_setup(ir_variable
*ir
);
446 fs_reg
*emit_general_interpolation(ir_variable
*ir
);
447 void emit_interpolation_setup_gen4();
448 void emit_interpolation_setup_gen6();
449 void compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
);
450 fs_reg
rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
451 bool is_rect
, uint32_t sampler
, int texunit
);
452 fs_inst
*emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
453 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
,
455 fs_inst
*emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
456 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
,
457 fs_reg sample_index
, uint32_t sampler
);
458 fs_inst
*emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
459 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
,
460 fs_reg sample_index
, fs_reg mcs
, fs_reg sampler
);
461 fs_reg
emit_mcs_fetch(ir_texture
*ir
, fs_reg coordinate
, fs_reg sampler
);
462 void emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
);
463 fs_reg
fix_math_operand(fs_reg src
);
464 fs_inst
*emit_math(enum opcode op
, fs_reg dst
, fs_reg src0
);
465 fs_inst
*emit_math(enum opcode op
, fs_reg dst
, fs_reg src0
, fs_reg src1
);
466 void emit_lrp(const fs_reg
&dst
, const fs_reg
&x
, const fs_reg
&y
,
468 void emit_minmax(enum brw_conditional_mod conditionalmod
, const fs_reg
&dst
,
469 const fs_reg
&src0
, const fs_reg
&src1
);
470 bool try_emit_saturate(ir_expression
*ir
);
471 bool try_emit_mad(ir_expression
*ir
);
472 void try_replace_with_sel();
473 bool opt_peephole_sel();
474 bool opt_peephole_predicated_break();
475 bool opt_saturate_propagation();
476 void emit_bool_to_cond_code(ir_rvalue
*condition
);
477 void emit_if_gen6(ir_if
*ir
);
478 void emit_unspill(bblock_t
*block
, fs_inst
*inst
, fs_reg reg
,
479 uint32_t spill_offset
, int count
);
480 void emit_spill(bblock_t
*block
, fs_inst
*inst
, fs_reg reg
,
481 uint32_t spill_offset
, int count
);
483 void emit_fragment_program_code();
484 void setup_fp_regs();
485 fs_reg
get_fp_src_reg(const prog_src_register
*src
);
486 fs_reg
get_fp_dst_reg(const prog_dst_register
*dst
);
487 void emit_fp_alu1(enum opcode opcode
,
488 const struct prog_instruction
*fpi
,
489 fs_reg dst
, fs_reg src
);
490 void emit_fp_alu2(enum opcode opcode
,
491 const struct prog_instruction
*fpi
,
492 fs_reg dst
, fs_reg src0
, fs_reg src1
);
493 void emit_fp_scalar_write(const struct prog_instruction
*fpi
,
494 fs_reg dst
, fs_reg src
);
495 void emit_fp_scalar_math(enum opcode opcode
,
496 const struct prog_instruction
*fpi
,
497 fs_reg dst
, fs_reg src
);
499 void emit_fp_minmax(const struct prog_instruction
*fpi
,
500 fs_reg dst
, fs_reg src0
, fs_reg src1
);
502 void emit_fp_sop(enum brw_conditional_mod conditional_mod
,
503 const struct prog_instruction
*fpi
,
504 fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg one
);
506 void emit_color_write(fs_reg color
, int index
, int first_color_mrf
);
507 void emit_alpha_test();
508 fs_inst
*emit_single_fb_write(fs_reg color1
, fs_reg color2
,
509 fs_reg src0_alpha
, unsigned components
);
510 void emit_fb_writes();
512 void emit_shader_time_begin();
513 void emit_shader_time_end();
514 void emit_shader_time_write(enum shader_time_shader_type type
,
517 void emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
518 fs_reg dst
, fs_reg offset
, fs_reg src0
,
521 void emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
524 void emit_interpolate_expression(ir_expression
*ir
);
526 bool try_rewrite_rhs_to_dst(ir_assignment
*ir
,
529 fs_inst
*pre_rhs_inst
,
530 fs_inst
*last_rhs_inst
);
531 void emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
532 const glsl_type
*type
, bool predicated
);
533 void resolve_ud_negate(fs_reg
*reg
);
534 void resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
);
536 fs_reg
get_timestamp();
538 struct brw_reg
interp_reg(int location
, int channel
);
539 void setup_uniform_values(ir_variable
*ir
);
540 void setup_builtin_uniform_values(ir_variable
*ir
);
541 int implied_mrf_writes(fs_inst
*inst
);
543 virtual void dump_instructions();
544 virtual void dump_instructions(const char *name
);
545 void dump_instruction(backend_instruction
*inst
);
546 void dump_instruction(backend_instruction
*inst
, FILE *file
);
548 void visit_atomic_counter_intrinsic(ir_call
*ir
);
550 const void *const key
;
551 struct brw_stage_prog_data
*prog_data
;
552 unsigned int sanity_param_count
;
556 int *virtual_grf_sizes
;
557 int virtual_grf_count
;
558 int virtual_grf_array_size
;
559 int *virtual_grf_start
;
560 int *virtual_grf_end
;
561 brw::fs_live_variables
*live_intervals
;
563 int *regs_live_at_ip
;
565 /** Number of uniform variable components visited. */
568 /** Byte-offset for the next available spot in the scratch space buffer. */
569 unsigned last_scratch
;
572 * Array mapping UNIFORM register numbers to the pull parameter index,
573 * or -1 if this uniform register isn't being uploaded as a pull constant.
575 int *pull_constant_loc
;
578 * Array mapping UNIFORM register numbers to the push parameter index,
579 * or -1 if this uniform register isn't being uploaded as a push constant.
581 int *push_constant_loc
;
583 struct hash_table
*variable_ht
;
586 fs_reg outputs
[BRW_MAX_DRAW_BUFFERS
];
587 unsigned output_components
[BRW_MAX_DRAW_BUFFERS
];
588 fs_reg dual_src_output
;
590 int first_non_payload_grf
;
591 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
594 fs_reg
*fp_temp_regs
;
595 fs_reg
*fp_input_regs
;
597 /** @{ debug annotation info */
598 const char *current_annotation
;
604 bool simd16_unsupported
;
607 /* Result of last visit() method. */
610 /** Register numbers for thread payload fields. */
612 uint8_t source_depth_reg
;
613 uint8_t source_w_reg
;
614 uint8_t aa_dest_stencil_reg
;
615 uint8_t dest_depth_reg
;
616 uint8_t sample_pos_reg
;
617 uint8_t sample_mask_in_reg
;
618 uint8_t barycentric_coord_reg
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
620 /** The number of thread payload registers the hardware will supply. */
624 bool source_depth_to_render_target
;
625 bool runtime_check_aads_emit
;
631 fs_reg delta_x
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
632 fs_reg delta_y
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
633 fs_reg shader_start_time
;
636 bool spilled_any_registers
;
638 const unsigned dispatch_width
; /**< 8 or 16 */
640 int force_uncompressed_stack
;
644 * The fragment shader code generator.
646 * Translates FS IR to actual i965 assembly code.
651 fs_generator(struct brw_context
*brw
,
653 const struct brw_wm_prog_key
*key
,
654 struct brw_wm_prog_data
*prog_data
,
655 struct gl_shader_program
*shader_prog
,
656 struct gl_fragment_program
*fp
,
657 bool runtime_check_aads_emit
,
661 const unsigned *generate_assembly(const cfg_t
*simd8_cfg
,
662 const cfg_t
*simd16_cfg
,
663 unsigned *assembly_size
);
666 void generate_code(const cfg_t
*cfg
);
667 void fire_fb_write(fs_inst
*inst
,
669 struct brw_reg implied_header
,
671 void generate_fb_write(fs_inst
*inst
);
672 void generate_blorp_fb_write(fs_inst
*inst
);
673 void generate_rep_fb_write(fs_inst
*inst
);
674 void generate_pixel_xy(struct brw_reg dst
, bool is_x
);
675 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
676 struct brw_reg
*src
);
677 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
678 struct brw_reg sampler_index
);
679 void generate_math_gen6(fs_inst
*inst
,
682 struct brw_reg src1
);
683 void generate_math_gen4(fs_inst
*inst
,
686 void generate_math_g45(fs_inst
*inst
,
689 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
, struct brw_reg quality
);
690 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
691 struct brw_reg quality
, bool negate_value
);
692 void generate_scratch_write(fs_inst
*inst
, struct brw_reg src
);
693 void generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
);
694 void generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
);
695 void generate_uniform_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
,
696 struct brw_reg index
,
697 struct brw_reg offset
);
698 void generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
700 struct brw_reg surf_index
,
701 struct brw_reg offset
);
702 void generate_varying_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
,
703 struct brw_reg index
,
704 struct brw_reg offset
);
705 void generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
707 struct brw_reg index
,
708 struct brw_reg offset
);
709 void generate_mov_dispatch_to_flags(fs_inst
*inst
);
711 void generate_pixel_interpolator_query(fs_inst
*inst
,
714 struct brw_reg msg_data
,
717 void generate_set_omask(fs_inst
*inst
,
719 struct brw_reg sample_mask
);
721 void generate_set_sample_id(fs_inst
*inst
,
724 struct brw_reg src1
);
726 void generate_set_simd4x2_offset(fs_inst
*inst
,
728 struct brw_reg offset
);
729 void generate_discard_jump(fs_inst
*inst
);
731 void generate_pack_half_2x16_split(fs_inst
*inst
,
735 void generate_unpack_half_2x16_split(fs_inst
*inst
,
739 void generate_shader_time_add(fs_inst
*inst
,
740 struct brw_reg payload
,
741 struct brw_reg offset
,
742 struct brw_reg value
);
744 void generate_untyped_atomic(fs_inst
*inst
,
746 struct brw_reg payload
,
747 struct brw_reg atomic_op
,
748 struct brw_reg surf_index
);
750 void generate_untyped_surface_read(fs_inst
*inst
,
752 struct brw_reg surf_index
);
754 bool patch_discard_jumps_to_fb_writes();
756 struct brw_context
*brw
;
757 struct gl_context
*ctx
;
759 struct brw_compile
*p
;
760 gl_shader_stage stage
;
761 const void * const key
;
762 struct brw_stage_prog_data
* const prog_data
;
764 struct gl_shader_program
* const shader_prog
;
765 const struct gl_program
*prog
;
767 unsigned dispatch_width
; /**< 8 or 16 */
769 exec_list discard_halt_patches
;
770 bool runtime_check_aads_emit
;
771 const bool debug_flag
;
775 bool brw_do_channel_expressions(struct exec_list
*instructions
);
776 bool brw_do_vector_splitting(struct exec_list
*instructions
);
777 bool brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
);
779 struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
);