2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include "brw_shader.h"
34 #include <sys/types.h>
36 #include "main/macros.h"
37 #include "main/shaderobj.h"
38 #include "main/uniforms.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/prog_optimize.h"
42 #include "program/register_allocate.h"
43 #include "program/sampler.h"
44 #include "program/hash_table.h"
45 #include "brw_context.h"
48 #include "brw_shader.h"
50 #include "gen8_generator.h"
51 #include "glsl/glsl_types.h"
54 #define MAX_SAMPLER_MESSAGE_SIZE 11
62 class fs_live_variables
;
67 DECLARE_RALLOC_CXX_OPERATORS(fs_reg
)
75 fs_reg(struct brw_reg fixed_hw_reg
);
76 fs_reg(enum register_file file
, int reg
);
77 fs_reg(enum register_file file
, int reg
, uint32_t type
);
78 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
80 bool equals(const fs_reg
&r
) const;
84 bool is_valid_3src() const;
85 bool is_contiguous() const;
87 fs_reg
&apply_stride(unsigned stride
);
88 /** Smear a channel of the reg to all channels. */
89 fs_reg
&set_smear(unsigned subreg
);
91 /** Register file: GRF, MRF, IMM. */
92 enum register_file file
;
93 /** Register type. BRW_REGISTER_TYPE_* */
96 * Register number. For MRF, it's the hardware register. For
97 * GRF, it's a virtual register number until register allocation
101 * Offset from the start of the contiguous register block.
103 * For pre-register-allocation GRFs, this is in units of a float per pixel
104 * (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
105 * For uniforms, this is in units of 1 float.
109 * Offset in bytes from the start of the register. Values up to a
110 * backend_reg::reg_offset unit are valid.
114 /** Value for file == IMM */
121 struct brw_reg fixed_hw_reg
;
128 /** Register region horizontal stride */
133 retype(fs_reg reg
, unsigned type
)
135 reg
.fixed_hw_reg
.type
= reg
.type
= type
;
140 offset(fs_reg reg
, unsigned delta
)
142 assert(delta
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
143 reg
.reg_offset
+= delta
;
148 byte_offset(fs_reg reg
, unsigned delta
)
150 assert(delta
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
151 reg
.subreg_offset
+= delta
;
156 * Get either of the 8-component halves of a 16-component register.
158 * Note: this also works if \c reg represents a SIMD16 pair of registers.
161 half(const fs_reg
®
, unsigned idx
)
164 assert(idx
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
165 return byte_offset(reg
, 8 * idx
* reg
.stride
* type_sz(reg
.type
));
168 static const fs_reg reg_undef
;
169 static const fs_reg
reg_null_f(retype(brw_null_reg(), BRW_REGISTER_TYPE_F
));
170 static const fs_reg
reg_null_d(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
171 static const fs_reg
reg_null_ud(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
173 class ip_record
: public exec_node
{
175 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
185 class fs_inst
: public backend_instruction
{
187 DECLARE_RALLOC_CXX_OPERATORS(fs_inst
)
192 fs_inst(enum opcode opcode
);
193 fs_inst(enum opcode opcode
, fs_reg dst
);
194 fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
);
195 fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
);
196 fs_inst(enum opcode opcode
, fs_reg dst
,
197 fs_reg src0
, fs_reg src1
,fs_reg src2
);
199 bool equals(fs_inst
*inst
);
200 bool overwrites_reg(const fs_reg
®
);
201 bool is_send_from_grf();
202 bool is_partial_write();
203 int regs_read(fs_visitor
*v
, int arg
);
212 * Annotation for the generated IR. One of the two can be set.
215 const char *annotation
;
218 uint32_t texture_offset
; /**< Texture offset bitfield */
219 uint32_t offset
; /* spill/unspill offset */
221 uint8_t conditional_mod
; /**< BRW_CONDITIONAL_* */
223 /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
224 * mod and predication.
228 uint8_t mlen
; /**< SEND message length */
229 uint8_t regs_written
; /**< Number of vgrfs written by a SEND message, or 1 */
230 int8_t base_mrf
; /**< First MRF in the SEND message, if mlen is nonzero. */
232 uint8_t target
; /**< MRT target. */
235 bool header_present
:1;
236 bool shadow_compare
:1;
237 bool force_uncompressed
:1;
238 bool force_sechalf
:1;
239 bool force_writemask_all
:1;
243 * The fragment shader front-end.
245 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
247 class fs_visitor
: public backend_visitor
251 fs_visitor(struct brw_context
*brw
,
252 struct brw_wm_compile
*c
,
253 struct gl_shader_program
*shader_prog
,
254 struct gl_fragment_program
*fp
,
255 unsigned dispatch_width
);
258 fs_reg
*variable_storage(ir_variable
*var
);
259 int virtual_grf_alloc(int size
);
260 void import_uniforms(fs_visitor
*v
);
262 void visit(ir_variable
*ir
);
263 void visit(ir_assignment
*ir
);
264 void visit(ir_dereference_variable
*ir
);
265 void visit(ir_dereference_record
*ir
);
266 void visit(ir_dereference_array
*ir
);
267 void visit(ir_expression
*ir
);
268 void visit(ir_texture
*ir
);
269 void visit(ir_if
*ir
);
270 void visit(ir_constant
*ir
);
271 void visit(ir_swizzle
*ir
);
272 void visit(ir_return
*ir
);
273 void visit(ir_loop
*ir
);
274 void visit(ir_loop_jump
*ir
);
275 void visit(ir_discard
*ir
);
276 void visit(ir_call
*ir
);
277 void visit(ir_function
*ir
);
278 void visit(ir_function_signature
*ir
);
279 void visit(ir_emit_vertex
*);
280 void visit(ir_end_primitive
*);
282 uint32_t gather_channel(ir_texture
*ir
, int sampler
);
283 void swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
);
285 bool can_do_source_mods(fs_inst
*inst
);
287 fs_inst
*emit(fs_inst
*inst
);
288 void emit(exec_list list
);
290 fs_inst
*emit(enum opcode opcode
);
291 fs_inst
*emit(enum opcode opcode
, fs_reg dst
);
292 fs_inst
*emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
);
293 fs_inst
*emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
);
294 fs_inst
*emit(enum opcode opcode
, fs_reg dst
,
295 fs_reg src0
, fs_reg src1
, fs_reg src2
);
297 fs_inst
*MOV(fs_reg dst
, fs_reg src
);
298 fs_inst
*NOT(fs_reg dst
, fs_reg src
);
299 fs_inst
*RNDD(fs_reg dst
, fs_reg src
);
300 fs_inst
*RNDE(fs_reg dst
, fs_reg src
);
301 fs_inst
*RNDZ(fs_reg dst
, fs_reg src
);
302 fs_inst
*FRC(fs_reg dst
, fs_reg src
);
303 fs_inst
*ADD(fs_reg dst
, fs_reg src0
, fs_reg src1
);
304 fs_inst
*MUL(fs_reg dst
, fs_reg src0
, fs_reg src1
);
305 fs_inst
*MACH(fs_reg dst
, fs_reg src0
, fs_reg src1
);
306 fs_inst
*MAC(fs_reg dst
, fs_reg src0
, fs_reg src1
);
307 fs_inst
*SHL(fs_reg dst
, fs_reg src0
, fs_reg src1
);
308 fs_inst
*SHR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
309 fs_inst
*ASR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
310 fs_inst
*AND(fs_reg dst
, fs_reg src0
, fs_reg src1
);
311 fs_inst
*OR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
312 fs_inst
*XOR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
313 fs_inst
*IF(uint32_t predicate
);
314 fs_inst
*IF(fs_reg src0
, fs_reg src1
, uint32_t condition
);
315 fs_inst
*CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
,
317 fs_inst
*LRP(fs_reg dst
, fs_reg a
, fs_reg y
, fs_reg x
);
318 fs_inst
*DEP_RESOLVE_MOV(int grf
);
319 fs_inst
*BFREV(fs_reg dst
, fs_reg value
);
320 fs_inst
*BFE(fs_reg dst
, fs_reg bits
, fs_reg offset
, fs_reg value
);
321 fs_inst
*BFI1(fs_reg dst
, fs_reg bits
, fs_reg offset
);
322 fs_inst
*BFI2(fs_reg dst
, fs_reg bfi1_dst
, fs_reg insert
, fs_reg base
);
323 fs_inst
*FBH(fs_reg dst
, fs_reg value
);
324 fs_inst
*FBL(fs_reg dst
, fs_reg value
);
325 fs_inst
*CBIT(fs_reg dst
, fs_reg value
);
326 fs_inst
*MAD(fs_reg dst
, fs_reg c
, fs_reg b
, fs_reg a
);
327 fs_inst
*ADDC(fs_reg dst
, fs_reg src0
, fs_reg src1
);
328 fs_inst
*SUBB(fs_reg dst
, fs_reg src0
, fs_reg src1
);
329 fs_inst
*SEL(fs_reg dst
, fs_reg src0
, fs_reg src1
);
331 int type_size(const struct glsl_type
*type
);
332 fs_inst
*get_instruction_generating_reg(fs_inst
*start
,
336 exec_list
VARYING_PULL_CONSTANT_LOAD(const fs_reg
&dst
,
337 const fs_reg
&surf_index
,
338 const fs_reg
&varying_offset
,
339 uint32_t const_offset
);
342 void assign_binding_table_offsets();
343 void setup_payload_gen4();
344 void setup_payload_gen6();
345 void assign_curb_setup();
346 void calculate_urb_setup();
347 void assign_urb_setup();
348 bool assign_regs(bool allow_spilling
);
349 void assign_regs_trivial();
350 void get_used_mrfs(bool *mrf_used
);
351 void setup_payload_interference(struct ra_graph
*g
, int payload_reg_count
,
352 int first_payload_node
);
353 void setup_mrf_hack_interference(struct ra_graph
*g
,
354 int first_mrf_hack_node
);
355 int choose_spill_reg(struct ra_graph
*g
);
356 void spill_reg(int spill_reg
);
357 void split_virtual_grfs();
358 void compact_virtual_grfs();
359 void move_uniform_array_access_to_pull_constants();
360 void setup_pull_constants();
361 void invalidate_live_intervals();
362 void calculate_live_intervals();
363 void calculate_register_pressure();
364 bool opt_algebraic();
366 bool opt_cse_local(bblock_t
*block
, exec_list
*aeb
);
367 bool opt_copy_propagate();
368 bool try_copy_propagate(fs_inst
*inst
, int arg
, acp_entry
*entry
);
369 bool try_constant_propagate(fs_inst
*inst
, acp_entry
*entry
);
370 bool opt_copy_propagate_local(void *mem_ctx
, bblock_t
*block
,
372 void opt_drop_redundant_mov_to_flags();
373 bool register_coalesce();
374 bool compute_to_mrf();
375 bool dead_code_eliminate();
376 bool dead_code_eliminate_local();
377 bool remove_dead_constants();
378 bool remove_duplicate_mrf_writes();
379 bool virtual_grf_interferes(int a
, int b
);
380 void schedule_instructions(instruction_scheduler_mode mode
);
381 void insert_gen4_send_dependency_workarounds();
382 void insert_gen4_pre_send_dependency_workarounds(fs_inst
*inst
);
383 void insert_gen4_post_send_dependency_workarounds(fs_inst
*inst
);
384 void fail(const char *msg
, ...);
385 void lower_uniform_pull_constant_loads();
387 void push_force_uncompressed();
388 void pop_force_uncompressed();
390 void emit_dummy_fs();
391 fs_reg
*emit_fragcoord_interpolation(ir_variable
*ir
);
392 fs_inst
*emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
393 glsl_interp_qualifier interpolation_mode
,
394 bool is_centroid
, bool is_sample
);
395 fs_reg
*emit_frontfacing_interpolation(ir_variable
*ir
);
396 fs_reg
*emit_samplepos_setup(ir_variable
*ir
);
397 fs_reg
*emit_sampleid_setup(ir_variable
*ir
);
398 fs_reg
*emit_samplemaskin_setup(ir_variable
*ir
);
399 fs_reg
*emit_general_interpolation(ir_variable
*ir
);
400 void emit_interpolation_setup_gen4();
401 void emit_interpolation_setup_gen6();
402 void compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
);
403 fs_reg
rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
404 bool is_rect
, int sampler
, int texunit
);
405 fs_inst
*emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
406 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
);
407 fs_inst
*emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
408 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
,
409 fs_reg sample_index
);
410 fs_inst
*emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
411 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
,
412 fs_reg sample_index
, fs_reg mcs
, int sampler
);
413 fs_reg
emit_mcs_fetch(ir_texture
*ir
, fs_reg coordinate
, int sampler
);
414 void emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
);
415 fs_reg
fix_math_operand(fs_reg src
);
416 fs_inst
*emit_math(enum opcode op
, fs_reg dst
, fs_reg src0
);
417 fs_inst
*emit_math(enum opcode op
, fs_reg dst
, fs_reg src0
, fs_reg src1
);
418 void emit_lrp(const fs_reg
&dst
, const fs_reg
&x
, const fs_reg
&y
,
420 void emit_minmax(uint32_t conditionalmod
, const fs_reg
&dst
,
421 const fs_reg
&src0
, const fs_reg
&src1
);
422 bool try_emit_saturate(ir_expression
*ir
);
423 bool try_emit_mad(ir_expression
*ir
, int mul_arg
);
424 void try_replace_with_sel();
425 bool opt_peephole_sel();
426 bool opt_peephole_predicated_break();
427 bool opt_saturate_propagation();
428 void emit_bool_to_cond_code(ir_rvalue
*condition
);
429 void emit_if_gen6(ir_if
*ir
);
430 void emit_unspill(fs_inst
*inst
, fs_reg reg
, uint32_t spill_offset
,
433 void emit_fragment_program_code();
434 void setup_fp_regs();
435 fs_reg
get_fp_src_reg(const prog_src_register
*src
);
436 fs_reg
get_fp_dst_reg(const prog_dst_register
*dst
);
437 void emit_fp_alu1(enum opcode opcode
,
438 const struct prog_instruction
*fpi
,
439 fs_reg dst
, fs_reg src
);
440 void emit_fp_alu2(enum opcode opcode
,
441 const struct prog_instruction
*fpi
,
442 fs_reg dst
, fs_reg src0
, fs_reg src1
);
443 void emit_fp_scalar_write(const struct prog_instruction
*fpi
,
444 fs_reg dst
, fs_reg src
);
445 void emit_fp_scalar_math(enum opcode opcode
,
446 const struct prog_instruction
*fpi
,
447 fs_reg dst
, fs_reg src
);
449 void emit_fp_minmax(const struct prog_instruction
*fpi
,
450 fs_reg dst
, fs_reg src0
, fs_reg src1
);
452 void emit_fp_sop(uint32_t conditional_mod
,
453 const struct prog_instruction
*fpi
,
454 fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg one
);
456 void emit_color_write(int target
, int index
, int first_color_mrf
);
457 void emit_alpha_test();
458 void emit_fb_writes();
460 void emit_shader_time_begin();
461 void emit_shader_time_end();
462 void emit_shader_time_write(enum shader_time_shader_type type
,
465 void emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
466 fs_reg dst
, fs_reg offset
, fs_reg src0
,
469 void emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
472 bool try_rewrite_rhs_to_dst(ir_assignment
*ir
,
475 fs_inst
*pre_rhs_inst
,
476 fs_inst
*last_rhs_inst
);
477 void emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
478 const glsl_type
*type
, bool predicated
);
479 void resolve_ud_negate(fs_reg
*reg
);
480 void resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
);
482 fs_reg
get_timestamp();
484 struct brw_reg
interp_reg(int location
, int channel
);
485 void setup_uniform_values(ir_variable
*ir
);
486 void setup_builtin_uniform_values(ir_variable
*ir
);
487 int implied_mrf_writes(fs_inst
*inst
);
489 virtual void dump_instructions();
490 void dump_instruction(backend_instruction
*inst
);
492 void visit_atomic_counter_intrinsic(ir_call
*ir
);
494 struct gl_fragment_program
*fp
;
495 struct brw_wm_compile
*c
;
496 unsigned int sanity_param_count
;
500 int *virtual_grf_sizes
;
501 int virtual_grf_count
;
502 int virtual_grf_array_size
;
503 int *virtual_grf_start
;
504 int *virtual_grf_end
;
505 brw::fs_live_variables
*live_intervals
;
507 int *regs_live_at_ip
;
509 /** Number of uniform variable components visited. */
512 /* This is the map from UNIFORM hw_reg + reg_offset as generated by
513 * the visitor to the packed uniform number after
514 * remove_dead_constants() that represents the actual uploaded
520 struct hash_table
*variable_ht
;
523 fs_reg outputs
[BRW_MAX_DRAW_BUFFERS
];
524 unsigned output_components
[BRW_MAX_DRAW_BUFFERS
];
525 fs_reg dual_src_output
;
526 int first_non_payload_grf
;
527 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
530 fs_reg
*fp_temp_regs
;
531 fs_reg
*fp_input_regs
;
533 /** @{ debug annotation info */
534 const char *current_annotation
;
541 /* Result of last visit() method. */
548 fs_reg delta_x
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
549 fs_reg delta_y
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
550 fs_reg shader_start_time
;
553 bool spilled_any_registers
;
555 const unsigned dispatch_width
; /**< 8 or 16 */
557 int force_uncompressed_stack
;
561 * The fragment shader code generator.
563 * Translates FS IR to actual i965 assembly code.
568 fs_generator(struct brw_context
*brw
,
569 struct brw_wm_compile
*c
,
570 struct gl_shader_program
*prog
,
571 struct gl_fragment_program
*fp
,
572 bool dual_source_output
);
575 const unsigned *generate_assembly(exec_list
*simd8_instructions
,
576 exec_list
*simd16_instructions
,
577 unsigned *assembly_size
,
578 FILE *dump_file
= NULL
);
581 void generate_code(exec_list
*instructions
, FILE *dump_file
);
582 void generate_fb_write(fs_inst
*inst
);
583 void generate_blorp_fb_write(fs_inst
*inst
);
584 void generate_pixel_xy(struct brw_reg dst
, bool is_x
);
585 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
586 struct brw_reg
*src
);
587 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
588 void generate_math1_gen7(fs_inst
*inst
,
591 void generate_math2_gen7(fs_inst
*inst
,
594 struct brw_reg src1
);
595 void generate_math1_gen6(fs_inst
*inst
,
598 void generate_math2_gen6(fs_inst
*inst
,
601 struct brw_reg src1
);
602 void generate_math_gen4(fs_inst
*inst
,
605 void generate_math_g45(fs_inst
*inst
,
608 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
609 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
611 void generate_scratch_write(fs_inst
*inst
, struct brw_reg src
);
612 void generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
);
613 void generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
);
614 void generate_uniform_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
,
615 struct brw_reg index
,
616 struct brw_reg offset
);
617 void generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
619 struct brw_reg surf_index
,
620 struct brw_reg offset
);
621 void generate_varying_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
,
622 struct brw_reg index
,
623 struct brw_reg offset
);
624 void generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
626 struct brw_reg index
,
627 struct brw_reg offset
);
628 void generate_mov_dispatch_to_flags(fs_inst
*inst
);
630 void generate_set_omask(fs_inst
*inst
,
632 struct brw_reg sample_mask
);
634 void generate_set_sample_id(fs_inst
*inst
,
637 struct brw_reg src1
);
639 void generate_set_simd4x2_offset(fs_inst
*inst
,
641 struct brw_reg offset
);
642 void generate_discard_jump(fs_inst
*inst
);
644 void generate_pack_half_2x16_split(fs_inst
*inst
,
648 void generate_unpack_half_2x16_split(fs_inst
*inst
,
652 void generate_shader_time_add(fs_inst
*inst
,
653 struct brw_reg payload
,
654 struct brw_reg offset
,
655 struct brw_reg value
);
657 void generate_untyped_atomic(fs_inst
*inst
,
659 struct brw_reg atomic_op
,
660 struct brw_reg surf_index
);
662 void generate_untyped_surface_read(fs_inst
*inst
,
664 struct brw_reg surf_index
);
666 void patch_discard_jumps_to_fb_writes();
668 struct brw_context
*brw
;
669 struct gl_context
*ctx
;
671 struct brw_compile
*p
;
672 struct brw_wm_compile
*c
;
674 struct gl_shader_program
*prog
;
675 const struct gl_fragment_program
*fp
;
677 unsigned dispatch_width
; /**< 8 or 16 */
679 exec_list discard_halt_patches
;
680 bool dual_source_output
;
685 * The fragment shader code generator.
687 * Translates FS IR to actual i965 assembly code.
689 class gen8_fs_generator
: public gen8_generator
692 gen8_fs_generator(struct brw_context
*brw
,
693 struct brw_wm_compile
*c
,
694 struct gl_shader_program
*prog
,
695 struct gl_fragment_program
*fp
,
696 bool dual_source_output
);
697 ~gen8_fs_generator();
699 const unsigned *generate_assembly(exec_list
*simd8_instructions
,
700 exec_list
*simd16_instructions
,
701 unsigned *assembly_size
);
704 void generate_code(exec_list
*instructions
);
705 void generate_fb_write(fs_inst
*inst
);
706 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
707 struct brw_reg
*src
);
708 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
709 void generate_math1(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
710 void generate_math2(fs_inst
*inst
, struct brw_reg dst
,
711 struct brw_reg src0
, struct brw_reg src1
);
712 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
713 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
715 void generate_scratch_write(fs_inst
*inst
, struct brw_reg src
);
716 void generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
);
717 void generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
);
718 void generate_uniform_pull_constant_load(fs_inst
*inst
,
720 struct brw_reg index
,
721 struct brw_reg offset
);
722 void generate_varying_pull_constant_load(fs_inst
*inst
,
724 struct brw_reg index
,
725 struct brw_reg offset
);
726 void generate_mov_dispatch_to_flags(fs_inst
*ir
);
727 void generate_set_omask(fs_inst
*ir
,
729 struct brw_reg sample_mask
);
730 void generate_set_sample_id(fs_inst
*ir
,
733 struct brw_reg src1
);
734 void generate_set_simd4x2_offset(fs_inst
*ir
,
736 struct brw_reg offset
);
737 void generate_pack_half_2x16_split(fs_inst
*inst
,
741 void generate_unpack_half_2x16_split(fs_inst
*inst
,
744 void generate_discard_jump(fs_inst
*ir
);
746 void patch_discard_jumps_to_fb_writes();
748 void mark_surface_used(unsigned surf_index
);
750 struct brw_wm_compile
*c
;
751 const struct gl_fragment_program
*fp
;
753 unsigned dispatch_width
; /** 8 or 16 */
755 bool dual_source_output
;
757 exec_list discard_halt_patches
;
760 bool brw_do_channel_expressions(struct exec_list
*instructions
);
761 bool brw_do_vector_splitting(struct exec_list
*instructions
);
762 bool brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
);
764 struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
);