src/mesa/drivers/dri/i965/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29
  30 #include "brw_shader.h"
  31
  32 extern "C" {
  33
  34 #include <sys/types.h>
  35
  36 #include "main/macros.h"
  37 #include "main/shaderobj.h"
  38 #include "main/uniforms.h"
  39 #include "program/prog_parameter.h"
  40 #include "program/prog_print.h"
  41 #include "program/prog_optimize.h"
  42 #include "util/register_allocate.h"
  43 #include "program/hash_table.h"
  44 #include "brw_context.h"
  45 #include "brw_eu.h"
  46 #include "brw_wm.h"
  47 #include "brw_shader.h"
  48 #include "intel_asm_annotation.h"
  49 }
  50 #include "glsl/glsl_types.h"
  51 #include "glsl/ir.h"
  52 #include "glsl/nir/nir.h"
  53 #include "program/sampler.h"
  54
  55 #define MAX_SAMPLER_MESSAGE_SIZE 11
  56 #define MAX_VGRF_SIZE 16
  57
  58 struct bblock_t;
  59 namespace {
  60    struct acp_entry;
  61 }
  62
  63 namespace brw {
  64    class fs_live_variables;
  65 }
  66
  67 class fs_inst;
  68 class fs_visitor;
  69
  70 class fs_reg : public backend_reg {
  71 public:
  72    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  73
  74    void init();
  75
  76    fs_reg();
  77    explicit fs_reg(float f);
  78    explicit fs_reg(int32_t i);
  79    explicit fs_reg(uint32_t u);
  80    explicit fs_reg(uint8_t vf[4]);
  81    explicit fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3);
  82    fs_reg(struct brw_reg fixed_hw_reg);
  83    fs_reg(enum register_file file, int reg);
  84    fs_reg(enum register_file file, int reg, enum brw_reg_type type);
  85    fs_reg(enum register_file file, int reg, enum brw_reg_type type, uint8_t width);
  86
  87    bool equals(const fs_reg &r) const;
  88    bool is_contiguous() const;
  89
  90    /** Smear a channel of the reg to all channels. */
  91    fs_reg &set_smear(unsigned subreg);
  92
  93    /**
  94     * Offset in bytes from the start of the register.  Values up to a
  95     * backend_reg::reg_offset unit are valid.
  96     */
  97    int subreg_offset;
  98
  99    fs_reg *reladdr;
 100
 101    /**
 102     * The register width.  This indicates how many hardware values are
 103     * represented by each virtual value.  Valid values are 1, 8, or 16.
 104     * For immediate values, this is 1.  Most of the rest of the time, it
 105     * will be equal to the dispatch width.
 106     */
 107    uint8_t width;
 108
 109    /**
 110     * Returns the effective register width when used as a source in the
 111     * given instruction.  Registers such as uniforms and immediates
 112     * effectively take on the width of the instruction in which they are
 113     * used.
 114     */
 115    uint8_t effective_width;
 116
 117    /** Register region horizontal stride */
 118    uint8_t stride;
 119 };
 120
 121 static inline fs_reg
 122 negate(fs_reg reg)
 123 {
 124    assert(reg.file != HW_REG && reg.file != IMM);
 125    reg.negate = !reg.negate;
 126    return reg;
 127 }
 128
 129 static inline fs_reg
 130 retype(fs_reg reg, enum brw_reg_type type)
 131 {
 132    reg.fixed_hw_reg.type = reg.type = type;
 133    return reg;
 134 }
 135
 136 static inline fs_reg
 137 byte_offset(fs_reg reg, unsigned delta)
 138 {
 139    switch (reg.file) {
 140    case BAD_FILE:
 141       break;
 142    case GRF:
 143    case ATTR:
 144       reg.reg_offset += delta / 32;
 145       break;
 146    case MRF:
 147       reg.reg += delta / 32;
 148       break;
 149    default:
 150       assert(delta == 0);
 151    }
 152    reg.subreg_offset += delta % 32;
 153    return reg;
 154 }
 155
 156 static inline fs_reg
 157 horiz_offset(fs_reg reg, unsigned delta)
 158 {
 159    switch (reg.file) {
 160    case BAD_FILE:
 161    case UNIFORM:
 162    case IMM:
 163       /* These only have a single component that is implicitly splatted.  A
 164        * horizontal offset should be a harmless no-op.
 165        */
 166       break;
 167    case GRF:
 168    case MRF:
 169    case ATTR:
 170       return byte_offset(reg, delta * reg.stride * type_sz(reg.type));
 171    default:
 172       assert(delta == 0);
 173    }
 174    return reg;
 175 }
 176
 177 static inline fs_reg
 178 offset(fs_reg reg, unsigned delta)
 179 {
 180    assert(reg.stride > 0);
 181    switch (reg.file) {
 182    case BAD_FILE:
 183       break;
 184    case GRF:
 185    case MRF:
 186    case ATTR:
 187       return byte_offset(reg, delta * reg.width * reg.stride * type_sz(reg.type));
 188    case UNIFORM:
 189       reg.reg_offset += delta;
 190       break;
 191    default:
 192       assert(delta == 0);
 193    }
 194    return reg;
 195 }
 196
 197 static inline fs_reg
 198 component(fs_reg reg, unsigned idx)
 199 {
 200    assert(reg.subreg_offset == 0);
 201    assert(idx < reg.width);
 202    reg.subreg_offset = idx * type_sz(reg.type);
 203    reg.width = 1;
 204    return reg;
 205 }
 206
 207 /**
 208  * Get either of the 8-component halves of a 16-component register.
 209  *
 210  * Note: this also works if \c reg represents a SIMD16 pair of registers.
 211  */
 212 static inline fs_reg
 213 half(fs_reg reg, unsigned idx)
 214 {
 215    assert(idx < 2);
 216
 217    if (reg.file == UNIFORM)
 218       return reg;
 219
 220    assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM));
 221    assert(reg.width == 16);
 222    reg.width = 8;
 223    return horiz_offset(reg, 8 * idx);
 224 }
 225
 226 static const fs_reg reg_undef;
 227
 228 class fs_inst : public backend_instruction {
 229    fs_inst &operator=(const fs_inst &);
 230
 231    void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
 232              fs_reg *src, int sources);
 233
 234 public:
 235    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 236
 237    fs_inst();
 238    fs_inst(enum opcode opcode, uint8_t exec_size);
 239    fs_inst(enum opcode opcode, const fs_reg &dst);
 240    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 241            const fs_reg &src0);
 242    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 243    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 244            const fs_reg &src0, const fs_reg &src1);
 245    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 246            const fs_reg &src1);
 247    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 248            const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 249    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 250            const fs_reg &src1, const fs_reg &src2);
 251    fs_inst(enum opcode opcode, const fs_reg &dst, fs_reg src[], int sources);
 252    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 253            fs_reg src[], int sources);
 254    fs_inst(const fs_inst &that);
 255
 256    void resize_sources(uint8_t num_sources);
 257
 258    bool equals(fs_inst *inst) const;
 259    bool overwrites_reg(const fs_reg &reg) const;
 260    bool is_send_from_grf() const;
 261    bool is_partial_write() const;
 262    int regs_read(fs_visitor *v, int arg) const;
 263    bool can_do_source_mods(struct brw_context *brw);
 264
 265    bool reads_flag() const;
 266    bool writes_flag() const;
 267
 268    fs_reg dst;
 269    fs_reg *src;
 270
 271    uint8_t sources; /**< Number of fs_reg sources. */
 272
 273    /**
 274     * Execution size of the instruction.  This is used by the generator to
 275     * generate the correct binary for the given fs_inst.  Current valid
 276     * values are 1, 8, 16.
 277     */
 278    uint8_t exec_size;
 279
 280    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 281     * mod and predication.
 282     */
 283    uint8_t flag_subreg;
 284
 285    uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
 286    bool eot:1;
 287    bool force_uncompressed:1;
 288    bool force_sechalf:1;
 289    bool pi_noperspective:1;   /**< Pixel interpolator noperspective flag */
 290 };
 291
 292 /**
 293  * The fragment shader front-end.
 294  *
 295  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
 296  */
 297 class fs_visitor : public backend_visitor
 298 {
 299 public:
 300    const fs_reg reg_null_f;
 301    const fs_reg reg_null_d;
 302    const fs_reg reg_null_ud;
 303
 304    fs_visitor(struct brw_context *brw,
 305               void *mem_ctx,
 306               const struct brw_wm_prog_key *key,
 307               struct brw_wm_prog_data *prog_data,
 308               struct gl_shader_program *shader_prog,
 309               struct gl_fragment_program *fp,
 310               unsigned dispatch_width);
 311
 312    fs_visitor(struct brw_context *brw,
 313               void *mem_ctx,
 314               const struct brw_vs_prog_key *key,
 315               struct brw_vs_prog_data *prog_data,
 316               struct gl_shader_program *shader_prog,
 317               struct gl_vertex_program *cp,
 318               unsigned dispatch_width);
 319
 320    ~fs_visitor();
 321    void init();
 322
 323    fs_reg *variable_storage(ir_variable *var);
 324    int virtual_grf_alloc(int size);
 325    fs_reg vgrf(const glsl_type *const type);
 326    fs_reg vgrf(int num_components);
 327    void import_uniforms(fs_visitor *v);
 328    void setup_uniform_clipplane_values();
 329    void compute_clip_distance();
 330
 331    void visit(ir_variable *ir);
 332    void visit(ir_assignment *ir);
 333    void visit(ir_dereference_variable *ir);
 334    void visit(ir_dereference_record *ir);
 335    void visit(ir_dereference_array *ir);
 336    void visit(ir_expression *ir);
 337    void visit(ir_texture *ir);
 338    void visit(ir_if *ir);
 339    void visit(ir_constant *ir);
 340    void visit(ir_swizzle *ir);
 341    void visit(ir_return *ir);
 342    void visit(ir_loop *ir);
 343    void visit(ir_loop_jump *ir);
 344    void visit(ir_discard *ir);
 345    void visit(ir_call *ir);
 346    void visit(ir_function *ir);
 347    void visit(ir_function_signature *ir);
 348    void visit(ir_emit_vertex *);
 349    void visit(ir_end_primitive *);
 350
 351    uint32_t gather_channel(int orig_chan, uint32_t sampler);
 352    void swizzle_result(ir_texture_opcode op, int dest_components,
 353                        fs_reg orig_val, uint32_t sampler);
 354
 355    fs_inst *emit(fs_inst *inst);
 356    void emit(exec_list list);
 357
 358    fs_inst *emit(enum opcode opcode);
 359    fs_inst *emit(enum opcode opcode, const fs_reg &dst);
 360    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 361    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 362                  const fs_reg &src1);
 363    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 364                  const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 365    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 366                  fs_reg src[], int sources);
 367
 368    fs_inst *MOV(const fs_reg &dst, const fs_reg &src);
 369    fs_inst *NOT(const fs_reg &dst, const fs_reg &src);
 370    fs_inst *RNDD(const fs_reg &dst, const fs_reg &src);
 371    fs_inst *RNDE(const fs_reg &dst, const fs_reg &src);
 372    fs_inst *RNDZ(const fs_reg &dst, const fs_reg &src);
 373    fs_inst *FRC(const fs_reg &dst, const fs_reg &src);
 374    fs_inst *ADD(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 375    fs_inst *MUL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 376    fs_inst *MACH(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 377    fs_inst *MAC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 378    fs_inst *SHL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 379    fs_inst *SHR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 380    fs_inst *ASR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 381    fs_inst *AND(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 382    fs_inst *OR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 383    fs_inst *XOR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 384    fs_inst *IF(enum brw_predicate predicate);
 385    fs_inst *IF(const fs_reg &src0, const fs_reg &src1,
 386                enum brw_conditional_mod condition);
 387    fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
 388                 enum brw_conditional_mod condition);
 389    fs_inst *LRP(const fs_reg &dst, const fs_reg &a, const fs_reg &y,
 390                 const fs_reg &x);
 391    fs_inst *DEP_RESOLVE_MOV(int grf);
 392    fs_inst *BFREV(const fs_reg &dst, const fs_reg &value);
 393    fs_inst *BFE(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset,
 394                 const fs_reg &value);
 395    fs_inst *BFI1(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset);
 396    fs_inst *BFI2(const fs_reg &dst, const fs_reg &bfi1_dst,
 397                  const fs_reg &insert, const fs_reg &base);
 398    fs_inst *FBH(const fs_reg &dst, const fs_reg &value);
 399    fs_inst *FBL(const fs_reg &dst, const fs_reg &value);
 400    fs_inst *CBIT(const fs_reg &dst, const fs_reg &value);
 401    fs_inst *MAD(const fs_reg &dst, const fs_reg &c, const fs_reg &b,
 402                 const fs_reg &a);
 403    fs_inst *ADDC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 404    fs_inst *SUBB(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 405    fs_inst *SEL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 406
 407    int type_size(const struct glsl_type *type);
 408    fs_inst *get_instruction_generating_reg(fs_inst *start,
 409                                            fs_inst *end,
 410                                            const fs_reg &reg);
 411
 412    fs_inst *LOAD_PAYLOAD(const fs_reg &dst, fs_reg *src, int sources);
 413
 414    exec_list VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
 415                                         const fs_reg &surf_index,
 416                                         const fs_reg &varying_offset,
 417                                         uint32_t const_offset);
 418
 419    bool run_fs();
 420    bool run_vs();
 421    void optimize();
 422    void allocate_registers();
 423    void assign_binding_table_offsets();
 424    void setup_payload_gen4();
 425    void setup_payload_gen6();
 426    void setup_vs_payload();
 427    void fixup_3src_null_dest();
 428    void assign_curb_setup();
 429    void calculate_urb_setup();
 430    void assign_urb_setup();
 431    void assign_vs_urb_setup();
 432    bool assign_regs(bool allow_spilling);
 433    void assign_regs_trivial();
 434    void get_used_mrfs(bool *mrf_used);
 435    void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
 436                                    int first_payload_node);
 437    void setup_mrf_hack_interference(struct ra_graph *g,
 438                                     int first_mrf_hack_node);
 439    int choose_spill_reg(struct ra_graph *g);
 440    void spill_reg(int spill_reg);
 441    void split_virtual_grfs();
 442    bool compact_virtual_grfs();
 443    void move_uniform_array_access_to_pull_constants();
 444    void assign_constant_locations();
 445    void demote_pull_constants();
 446    void invalidate_live_intervals();
 447    void calculate_live_intervals();
 448    void calculate_register_pressure();
 449    bool opt_algebraic();
 450    bool opt_cse();
 451    bool opt_cse_local(bblock_t *block);
 452    bool opt_copy_propagate();
 453    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 454    bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
 455    bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
 456                                  exec_list *acp);
 457    bool opt_register_renaming();
 458    bool register_coalesce();
 459    bool compute_to_mrf();
 460    bool dead_code_eliminate();
 461    bool remove_duplicate_mrf_writes();
 462    bool virtual_grf_interferes(int a, int b);
 463    void schedule_instructions(instruction_scheduler_mode mode);
 464    void insert_gen4_send_dependency_workarounds();
 465    void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
 466                                                     fs_inst *inst);
 467    void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
 468                                                      fs_inst *inst);
 469    void vfail(const char *msg, va_list args);
 470    void fail(const char *msg, ...);
 471    void no16(const char *msg, ...);
 472    void lower_uniform_pull_constant_loads();
 473    bool lower_load_payload();
 474
 475    void emit_dummy_fs();
 476    void emit_repclear_shader();
 477    fs_reg *emit_fragcoord_interpolation(bool pixel_center_integer,
 478                                         bool origin_upper_left);
 479    fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
 480                          glsl_interp_qualifier interpolation_mode,
 481                          bool is_centroid, bool is_sample);
 482    fs_reg *emit_frontfacing_interpolation();
 483    fs_reg *emit_samplepos_setup();
 484    fs_reg *emit_sampleid_setup();
 485    void emit_general_interpolation(fs_reg attr, const char *name,
 486                                    const glsl_type *type,
 487                                    glsl_interp_qualifier interpolation_mode,
 488                                    int location, bool mod_centroid,
 489                                    bool mod_sample);
 490    fs_reg *emit_vs_system_value(enum brw_reg_type type, int location);
 491    void emit_interpolation_setup_gen4();
 492    void emit_interpolation_setup_gen6();
 493    void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
 494    fs_reg rescale_texcoord(fs_reg coordinate, int coord_components,
 495                            bool is_rect, uint32_t sampler, int texunit);
 496    fs_inst *emit_texture_gen4(ir_texture_opcode op, fs_reg dst,
 497                               fs_reg coordinate, int coord_components,
 498                               fs_reg shadow_comp,
 499                               fs_reg lod, fs_reg lod2, int grad_components,
 500                               uint32_t sampler);
 501    fs_inst *emit_texture_gen5(ir_texture_opcode op, fs_reg dst,
 502                               fs_reg coordinate, int coord_components,
 503                               fs_reg shadow_comp,
 504                               fs_reg lod, fs_reg lod2, int grad_components,
 505                               fs_reg sample_index, uint32_t sampler,
 506                               bool has_offset);
 507    fs_inst *emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
 508                               fs_reg coordinate, int coord_components,
 509                               fs_reg shadow_comp,
 510                               fs_reg lod, fs_reg lod2, int grad_components,
 511                               fs_reg sample_index, fs_reg mcs, fs_reg sampler,
 512                               fs_reg offset_value);
 513    void emit_texture(ir_texture_opcode op,
 514                      const glsl_type *dest_type,
 515                      fs_reg coordinate, int components,
 516                      fs_reg shadow_c,
 517                      fs_reg lod, fs_reg dpdy, int grad_components,
 518                      fs_reg sample_index,
 519                      fs_reg offset, unsigned offset_components,
 520                      fs_reg mcs,
 521                      int gather_component,
 522                      bool is_cube_array,
 523                      bool is_rect,
 524                      uint32_t sampler,
 525                      fs_reg sampler_reg,
 526                      int texunit);
 527    fs_reg emit_mcs_fetch(fs_reg coordinate, int components, fs_reg sampler);
 528    void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
 529    fs_reg fix_math_operand(fs_reg src);
 530    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
 531    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
 532    void emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
 533                  const fs_reg &a);
 534    void emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &dst,
 535                     const fs_reg &src0, const fs_reg &src1);
 536    bool try_emit_saturate(ir_expression *ir);
 537    bool try_emit_line(ir_expression *ir);
 538    bool try_emit_mad(ir_expression *ir);
 539    bool try_replace_with_sel();
 540    bool opt_peephole_sel();
 541    bool opt_peephole_predicated_break();
 542    bool opt_saturate_propagation();
 543    void emit_bool_to_cond_code(ir_rvalue *condition);
 544    void emit_if_gen6(ir_if *ir);
 545    void emit_unspill(bblock_t *block, fs_inst *inst, fs_reg reg,
 546                      uint32_t spill_offset, int count);
 547    void emit_spill(bblock_t *block, fs_inst *inst, fs_reg reg,
 548                    uint32_t spill_offset, int count);
 549
 550    void emit_fragment_program_code();
 551    void setup_fp_regs();
 552    fs_reg get_fp_src_reg(const prog_src_register *src);
 553    fs_reg get_fp_dst_reg(const prog_dst_register *dst);
 554    void emit_fp_alu1(enum opcode opcode,
 555                      const struct prog_instruction *fpi,
 556                      fs_reg dst, fs_reg src);
 557    void emit_fp_alu2(enum opcode opcode,
 558                      const struct prog_instruction *fpi,
 559                      fs_reg dst, fs_reg src0, fs_reg src1);
 560    void emit_fp_scalar_write(const struct prog_instruction *fpi,
 561                              fs_reg dst, fs_reg src);
 562    void emit_fp_scalar_math(enum opcode opcode,
 563                             const struct prog_instruction *fpi,
 564                             fs_reg dst, fs_reg src);
 565
 566    void emit_fp_minmax(const struct prog_instruction *fpi,
 567                        fs_reg dst, fs_reg src0, fs_reg src1);
 568
 569    void emit_fp_sop(enum brw_conditional_mod conditional_mod,
 570                     const struct prog_instruction *fpi,
 571                     fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
 572
 573    void emit_nir_code();
 574    void nir_setup_inputs(nir_shader *shader);
 575    void nir_setup_outputs(nir_shader *shader);
 576    void nir_setup_uniforms(nir_shader *shader);
 577    void nir_setup_uniform(nir_variable *var);
 578    void nir_setup_builtin_uniform(nir_variable *var);
 579    void nir_emit_system_values(nir_shader *shader);
 580    void nir_emit_impl(nir_function_impl *impl);
 581    void nir_emit_cf_list(exec_list *list);
 582    void nir_emit_if(nir_if *if_stmt);
 583    void nir_emit_loop(nir_loop *loop);
 584    void nir_emit_block(nir_block *block);
 585    void nir_emit_instr(nir_instr *instr);
 586    void nir_emit_alu(nir_alu_instr *instr);
 587    void nir_emit_intrinsic(nir_intrinsic_instr *instr);
 588    void nir_emit_texture(nir_tex_instr *instr);
 589    void nir_emit_jump(nir_jump_instr *instr);
 590    fs_reg get_nir_src(nir_src src);
 591    fs_reg get_nir_alu_src(nir_alu_instr *instr, unsigned src);
 592    fs_reg get_nir_dest(nir_dest dest);
 593    void emit_percomp(fs_inst *inst, unsigned wr_mask);
 594    void emit_percomp(enum opcode op, fs_reg dest, fs_reg src0,
 595                      unsigned wr_mask, bool saturate = false,
 596                      enum brw_predicate predicate = BRW_PREDICATE_NONE,
 597                      enum brw_conditional_mod mod = BRW_CONDITIONAL_NONE);
 598    void emit_percomp(enum opcode op, fs_reg dest, fs_reg src0, fs_reg src1,
 599                      unsigned wr_mask, bool saturate = false,
 600                      enum brw_predicate predicate = BRW_PREDICATE_NONE,
 601                      enum brw_conditional_mod mod = BRW_CONDITIONAL_NONE);
 602    void emit_math_percomp(enum opcode op, fs_reg dest, fs_reg src0,
 603                           unsigned wr_mask, bool saturate = false);
 604    void emit_math_percomp(enum opcode op, fs_reg dest, fs_reg src0,
 605                           fs_reg src1, unsigned wr_mask,
 606                           bool saturate = false);
 607    void emit_reduction(enum opcode op, fs_reg dest, fs_reg src,
 608                        unsigned num_components);
 609
 610    int setup_color_payload(fs_reg *dst, fs_reg color, unsigned components);
 611    void emit_alpha_test();
 612    fs_inst *emit_single_fb_write(fs_reg color1, fs_reg color2,
 613                                  fs_reg src0_alpha, unsigned components);
 614    void emit_fb_writes();
 615    void emit_urb_writes();
 616
 617    void emit_shader_time_begin();
 618    void emit_shader_time_end();
 619    void emit_shader_time_write(enum shader_time_shader_type type,
 620                                fs_reg value);
 621
 622    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 623                             fs_reg dst, fs_reg offset, fs_reg src0,
 624                             fs_reg src1);
 625
 626    void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
 627                                   fs_reg offset);
 628
 629    void emit_interpolate_expression(ir_expression *ir);
 630
 631    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 632                                fs_reg dst,
 633                                fs_reg src,
 634                                fs_inst *pre_rhs_inst,
 635                                fs_inst *last_rhs_inst);
 636    void emit_assignment_writes(fs_reg &l, fs_reg &r,
 637                                const glsl_type *type, bool predicated);
 638    void resolve_ud_negate(fs_reg *reg);
 639    void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
 640
 641    fs_reg get_timestamp();
 642
 643    struct brw_reg interp_reg(int location, int channel);
 644    void setup_uniform_values(ir_variable *ir);
 645    void setup_builtin_uniform_values(ir_variable *ir);
 646    int implied_mrf_writes(fs_inst *inst);
 647
 648    virtual void dump_instructions();
 649    virtual void dump_instructions(const char *name);
 650    void dump_instruction(backend_instruction *inst);
 651    void dump_instruction(backend_instruction *inst, FILE *file);
 652
 653    void visit_atomic_counter_intrinsic(ir_call *ir);
 654
 655    const void *const key;
 656    struct brw_stage_prog_data *prog_data;
 657    unsigned int sanity_param_count;
 658
 659    int *param_size;
 660
 661    int *virtual_grf_sizes;
 662    int virtual_grf_count;
 663    int virtual_grf_array_size;
 664    int *virtual_grf_start;
 665    int *virtual_grf_end;
 666    brw::fs_live_variables *live_intervals;
 667
 668    int *regs_live_at_ip;
 669
 670    /** Number of uniform variable components visited. */
 671    unsigned uniforms;
 672
 673    /** Byte-offset for the next available spot in the scratch space buffer. */
 674    unsigned last_scratch;
 675
 676    /**
 677     * Array mapping UNIFORM register numbers to the pull parameter index,
 678     * or -1 if this uniform register isn't being uploaded as a pull constant.
 679     */
 680    int *pull_constant_loc;
 681
 682    /**
 683     * Array mapping UNIFORM register numbers to the push parameter index,
 684     * or -1 if this uniform register isn't being uploaded as a push constant.
 685     */
 686    int *push_constant_loc;
 687
 688    struct hash_table *variable_ht;
 689    fs_reg frag_depth;
 690    fs_reg sample_mask;
 691    fs_reg outputs[VARYING_SLOT_MAX];
 692    unsigned output_components[VARYING_SLOT_MAX];
 693    fs_reg dual_src_output;
 694    bool do_dual_src;
 695    int first_non_payload_grf;
 696    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 697    int max_grf;
 698
 699    fs_reg *fp_temp_regs;
 700    fs_reg *fp_input_regs;
 701
 702    fs_reg *nir_locals;
 703    fs_reg *nir_globals;
 704    fs_reg nir_inputs;
 705    fs_reg nir_outputs;
 706    fs_reg nir_uniforms;
 707    fs_reg *nir_system_values;
 708
 709    /** @{ debug annotation info */
 710    const char *current_annotation;
 711    const void *base_ir;
 712    /** @} */
 713
 714    bool failed;
 715    char *fail_msg;
 716    bool simd16_unsupported;
 717    char *no16_msg;
 718
 719    /* Result of last visit() method. */
 720    fs_reg result;
 721
 722    /** Register numbers for thread payload fields. */
 723    struct {
 724       uint8_t source_depth_reg;
 725       uint8_t source_w_reg;
 726       uint8_t aa_dest_stencil_reg;
 727       uint8_t dest_depth_reg;
 728       uint8_t sample_pos_reg;
 729       uint8_t sample_mask_in_reg;
 730       uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 731
 732       /** The number of thread payload registers the hardware will supply. */
 733       uint8_t num_regs;
 734    } payload;
 735
 736    bool source_depth_to_render_target;
 737    bool runtime_check_aads_emit;
 738
 739    fs_reg pixel_x;
 740    fs_reg pixel_y;
 741    fs_reg wpos_w;
 742    fs_reg pixel_w;
 743    fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 744    fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 745    fs_reg shader_start_time;
 746    fs_reg userplane[MAX_CLIP_PLANES];
 747
 748    int grf_used;
 749    bool spilled_any_registers;
 750
 751    const unsigned dispatch_width; /**< 8 or 16 */
 752 };
 753
 754 /**
 755  * The fragment shader code generator.
 756  *
 757  * Translates FS IR to actual i965 assembly code.
 758  */
 759 class fs_generator
 760 {
 761 public:
 762    fs_generator(struct brw_context *brw,
 763                 void *mem_ctx,
 764                 const void *key,
 765                 struct brw_stage_prog_data *prog_data,
 766                 struct gl_program *fp,
 767                 bool runtime_check_aads_emit,
 768                 const char *stage_abbrev);
 769    ~fs_generator();
 770
 771    void enable_debug(const char *shader_name);
 772    int generate_code(const cfg_t *cfg, int dispatch_width);
 773    const unsigned *get_assembly(unsigned int *assembly_size);
 774
 775 private:
 776    void fire_fb_write(fs_inst *inst,
 777                       struct brw_reg payload,
 778                       struct brw_reg implied_header,
 779                       GLuint nr);
 780    void generate_fb_write(fs_inst *inst, struct brw_reg payload);
 781    void generate_urb_write(fs_inst *inst, struct brw_reg payload);
 782    void generate_blorp_fb_write(fs_inst *inst);
 783    void generate_pixel_xy(struct brw_reg dst, bool is_x);
 784    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 785                          struct brw_reg *src);
 786    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 787                      struct brw_reg sampler_index);
 788    void generate_math_gen6(fs_inst *inst,
 789                            struct brw_reg dst,
 790                            struct brw_reg src0,
 791                            struct brw_reg src1);
 792    void generate_math_gen4(fs_inst *inst,
 793                            struct brw_reg dst,
 794                            struct brw_reg src);
 795    void generate_math_g45(fs_inst *inst,
 796                           struct brw_reg dst,
 797                           struct brw_reg src);
 798    void generate_ddx(enum opcode op, struct brw_reg dst, struct brw_reg src);
 799    void generate_ddy(enum opcode op, struct brw_reg dst, struct brw_reg src,
 800                      bool negate_value);
 801    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 802    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 803    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 804    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 805                                             struct brw_reg index,
 806                                             struct brw_reg offset);
 807    void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
 808                                                  struct brw_reg dst,
 809                                                  struct brw_reg surf_index,
 810                                                  struct brw_reg offset);
 811    void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 812                                             struct brw_reg index,
 813                                             struct brw_reg offset);
 814    void generate_varying_pull_constant_load_gen7(fs_inst *inst,
 815                                                  struct brw_reg dst,
 816                                                  struct brw_reg index,
 817                                                  struct brw_reg offset);
 818    void generate_mov_dispatch_to_flags(fs_inst *inst);
 819
 820    void generate_pixel_interpolator_query(fs_inst *inst,
 821                                           struct brw_reg dst,
 822                                           struct brw_reg src,
 823                                           struct brw_reg msg_data,
 824                                           unsigned msg_type);
 825
 826    void generate_set_omask(fs_inst *inst,
 827                            struct brw_reg dst,
 828                            struct brw_reg sample_mask);
 829
 830    void generate_set_sample_id(fs_inst *inst,
 831                                struct brw_reg dst,
 832                                struct brw_reg src0,
 833                                struct brw_reg src1);
 834
 835    void generate_set_simd4x2_offset(fs_inst *inst,
 836                                     struct brw_reg dst,
 837                                     struct brw_reg offset);
 838    void generate_discard_jump(fs_inst *inst);
 839
 840    void generate_pack_half_2x16_split(fs_inst *inst,
 841                                       struct brw_reg dst,
 842                                       struct brw_reg x,
 843                                       struct brw_reg y);
 844    void generate_unpack_half_2x16_split(fs_inst *inst,
 845                                         struct brw_reg dst,
 846                                         struct brw_reg src);
 847
 848    void generate_shader_time_add(fs_inst *inst,
 849                                  struct brw_reg payload,
 850                                  struct brw_reg offset,
 851                                  struct brw_reg value);
 852
 853    void generate_untyped_atomic(fs_inst *inst,
 854                                 struct brw_reg dst,
 855                                 struct brw_reg payload,
 856                                 struct brw_reg atomic_op,
 857                                 struct brw_reg surf_index);
 858
 859    void generate_untyped_surface_read(fs_inst *inst,
 860                                       struct brw_reg dst,
 861                                       struct brw_reg payload,
 862                                       struct brw_reg surf_index);
 863
 864    bool patch_discard_jumps_to_fb_writes();
 865
 866    struct brw_context *brw;
 867    struct gl_context *ctx;
 868
 869    struct brw_compile *p;
 870    const void * const key;
 871    struct brw_stage_prog_data * const prog_data;
 872
 873    const struct gl_program *prog;
 874
 875    unsigned dispatch_width; /**< 8 or 16 */
 876
 877    exec_list discard_halt_patches;
 878    bool runtime_check_aads_emit;
 879    bool debug_flag;
 880    const char *shader_name;
 881    const char *stage_abbrev;
 882    void *mem_ctx;
 883 };
 884
 885 bool brw_do_channel_expressions(struct exec_list *instructions);
 886 bool brw_do_vector_splitting(struct exec_list *instructions);