src/mesa/drivers/dri/i965/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29
  30 #include "brw_shader.h"
  31
  32 extern "C" {
  33
  34 #include <sys/types.h>
  35
  36 #include "main/macros.h"
  37 #include "main/shaderobj.h"
  38 #include "main/uniforms.h"
  39 #include "program/prog_parameter.h"
  40 #include "program/prog_print.h"
  41 #include "program/prog_optimize.h"
  42 #include "util/register_allocate.h"
  43 #include "program/hash_table.h"
  44 #include "brw_context.h"
  45 #include "brw_eu.h"
  46 #include "brw_wm.h"
  47 #include "brw_shader.h"
  48 #include "intel_asm_annotation.h"
  49 }
  50 #include "glsl/glsl_types.h"
  51 #include "glsl/ir.h"
  52 #include "glsl/nir/nir.h"
  53 #include "program/sampler.h"
  54
  55 #define MAX_SAMPLER_MESSAGE_SIZE 11
  56 #define MAX_VGRF_SIZE 16
  57
  58 struct bblock_t;
  59 namespace {
  60    struct acp_entry;
  61 }
  62
  63 namespace brw {
  64    class fs_live_variables;
  65 }
  66
  67 class fs_inst;
  68 class fs_visitor;
  69
  70 class fs_reg : public backend_reg {
  71 public:
  72    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  73
  74    void init();
  75
  76    fs_reg();
  77    explicit fs_reg(float f);
  78    explicit fs_reg(int32_t i);
  79    explicit fs_reg(uint32_t u);
  80    explicit fs_reg(uint8_t vf[4]);
  81    explicit fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3);
  82    fs_reg(struct brw_reg fixed_hw_reg);
  83    fs_reg(enum register_file file, int reg);
  84    fs_reg(enum register_file file, int reg, enum brw_reg_type type);
  85    fs_reg(enum register_file file, int reg, enum brw_reg_type type, uint8_t width);
  86    fs_reg(fs_visitor *v, const struct glsl_type *type);
  87
  88    bool equals(const fs_reg &r) const;
  89    bool is_contiguous() const;
  90
  91    /** Smear a channel of the reg to all channels. */
  92    fs_reg &set_smear(unsigned subreg);
  93
  94    /**
  95     * Offset in bytes from the start of the register.  Values up to a
  96     * backend_reg::reg_offset unit are valid.
  97     */
  98    int subreg_offset;
  99
 100    fs_reg *reladdr;
 101
 102    /**
 103     * The register width.  This indicates how many hardware values are
 104     * represented by each virtual value.  Valid values are 1, 8, or 16.
 105     * For immediate values, this is 1.  Most of the rest of the time, it
 106     * will be equal to the dispatch width.
 107     */
 108    uint8_t width;
 109
 110    /**
 111     * Returns the effective register width when used as a source in the
 112     * given instruction.  Registers such as uniforms and immediates
 113     * effectively take on the width of the instruction in which they are
 114     * used.
 115     */
 116    uint8_t effective_width;
 117
 118    /** Register region horizontal stride */
 119    uint8_t stride;
 120 };
 121
 122 static inline fs_reg
 123 negate(fs_reg reg)
 124 {
 125    assert(reg.file != HW_REG && reg.file != IMM);
 126    reg.negate = !reg.negate;
 127    return reg;
 128 }
 129
 130 static inline fs_reg
 131 retype(fs_reg reg, enum brw_reg_type type)
 132 {
 133    reg.fixed_hw_reg.type = reg.type = type;
 134    return reg;
 135 }
 136
 137 static inline fs_reg
 138 byte_offset(fs_reg reg, unsigned delta)
 139 {
 140    switch (reg.file) {
 141    case BAD_FILE:
 142       break;
 143    case GRF:
 144    case ATTR:
 145       reg.reg_offset += delta / 32;
 146       break;
 147    case MRF:
 148       reg.reg += delta / 32;
 149       break;
 150    default:
 151       assert(delta == 0);
 152    }
 153    reg.subreg_offset += delta % 32;
 154    return reg;
 155 }
 156
 157 static inline fs_reg
 158 horiz_offset(fs_reg reg, unsigned delta)
 159 {
 160    switch (reg.file) {
 161    case BAD_FILE:
 162    case UNIFORM:
 163    case IMM:
 164       /* These only have a single component that is implicitly splatted.  A
 165        * horizontal offset should be a harmless no-op.
 166        */
 167       break;
 168    case GRF:
 169    case MRF:
 170    case ATTR:
 171       return byte_offset(reg, delta * reg.stride * type_sz(reg.type));
 172    default:
 173       assert(delta == 0);
 174    }
 175    return reg;
 176 }
 177
 178 static inline fs_reg
 179 offset(fs_reg reg, unsigned delta)
 180 {
 181    assert(reg.stride > 0);
 182    switch (reg.file) {
 183    case BAD_FILE:
 184       break;
 185    case GRF:
 186    case MRF:
 187    case ATTR:
 188       return byte_offset(reg, delta * reg.width * reg.stride * type_sz(reg.type));
 189    case UNIFORM:
 190       reg.reg_offset += delta;
 191       break;
 192    default:
 193       assert(delta == 0);
 194    }
 195    return reg;
 196 }
 197
 198 static inline fs_reg
 199 component(fs_reg reg, unsigned idx)
 200 {
 201    assert(reg.subreg_offset == 0);
 202    assert(idx < reg.width);
 203    reg.subreg_offset = idx * type_sz(reg.type);
 204    reg.width = 1;
 205    return reg;
 206 }
 207
 208 /**
 209  * Get either of the 8-component halves of a 16-component register.
 210  *
 211  * Note: this also works if \c reg represents a SIMD16 pair of registers.
 212  */
 213 static inline fs_reg
 214 half(fs_reg reg, unsigned idx)
 215 {
 216    assert(idx < 2);
 217
 218    if (reg.file == UNIFORM)
 219       return reg;
 220
 221    assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM));
 222    assert(reg.width == 16);
 223    reg.width = 8;
 224    return horiz_offset(reg, 8 * idx);
 225 }
 226
 227 static const fs_reg reg_undef;
 228
 229 class fs_inst : public backend_instruction {
 230    fs_inst &operator=(const fs_inst &);
 231
 232    void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
 233              fs_reg *src, int sources);
 234
 235 public:
 236    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 237
 238    fs_inst();
 239    fs_inst(enum opcode opcode, uint8_t exec_size);
 240    fs_inst(enum opcode opcode, const fs_reg &dst);
 241    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 242            const fs_reg &src0);
 243    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 244    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 245            const fs_reg &src0, const fs_reg &src1);
 246    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 247            const fs_reg &src1);
 248    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 249            const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 250    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 251            const fs_reg &src1, const fs_reg &src2);
 252    fs_inst(enum opcode opcode, const fs_reg &dst, fs_reg src[], int sources);
 253    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 254            fs_reg src[], int sources);
 255    fs_inst(const fs_inst &that);
 256
 257    void resize_sources(uint8_t num_sources);
 258
 259    bool equals(fs_inst *inst) const;
 260    bool overwrites_reg(const fs_reg &reg) const;
 261    bool is_send_from_grf() const;
 262    bool is_partial_write() const;
 263    int regs_read(fs_visitor *v, int arg) const;
 264    bool can_do_source_mods(struct brw_context *brw);
 265
 266    bool reads_flag() const;
 267    bool writes_flag() const;
 268
 269    fs_reg dst;
 270    fs_reg *src;
 271
 272    uint8_t sources; /**< Number of fs_reg sources. */
 273
 274    /**
 275     * Execution size of the instruction.  This is used by the generator to
 276     * generate the correct binary for the given fs_inst.  Current valid
 277     * values are 1, 8, 16.
 278     */
 279    uint8_t exec_size;
 280
 281    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 282     * mod and predication.
 283     */
 284    uint8_t flag_subreg;
 285
 286    uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
 287    bool eot:1;
 288    bool force_uncompressed:1;
 289    bool force_sechalf:1;
 290    bool pi_noperspective:1;   /**< Pixel interpolator noperspective flag */
 291 };
 292
 293 /**
 294  * The fragment shader front-end.
 295  *
 296  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
 297  */
 298 class fs_visitor : public backend_visitor
 299 {
 300 public:
 301    const fs_reg reg_null_f;
 302    const fs_reg reg_null_d;
 303    const fs_reg reg_null_ud;
 304
 305    fs_visitor(struct brw_context *brw,
 306               void *mem_ctx,
 307               const struct brw_wm_prog_key *key,
 308               struct brw_wm_prog_data *prog_data,
 309               struct gl_shader_program *shader_prog,
 310               struct gl_fragment_program *fp,
 311               unsigned dispatch_width);
 312
 313    fs_visitor(struct brw_context *brw,
 314               void *mem_ctx,
 315               const struct brw_vs_prog_key *key,
 316               struct brw_vs_prog_data *prog_data,
 317               struct gl_shader_program *shader_prog,
 318               struct gl_vertex_program *cp,
 319               unsigned dispatch_width);
 320
 321    ~fs_visitor();
 322    void init();
 323
 324    fs_reg *variable_storage(ir_variable *var);
 325    int virtual_grf_alloc(int size);
 326    void import_uniforms(fs_visitor *v);
 327    void setup_uniform_clipplane_values();
 328    void compute_clip_distance();
 329
 330    void visit(ir_variable *ir);
 331    void visit(ir_assignment *ir);
 332    void visit(ir_dereference_variable *ir);
 333    void visit(ir_dereference_record *ir);
 334    void visit(ir_dereference_array *ir);
 335    void visit(ir_expression *ir);
 336    void visit(ir_texture *ir);
 337    void visit(ir_if *ir);
 338    void visit(ir_constant *ir);
 339    void visit(ir_swizzle *ir);
 340    void visit(ir_return *ir);
 341    void visit(ir_loop *ir);
 342    void visit(ir_loop_jump *ir);
 343    void visit(ir_discard *ir);
 344    void visit(ir_call *ir);
 345    void visit(ir_function *ir);
 346    void visit(ir_function_signature *ir);
 347    void visit(ir_emit_vertex *);
 348    void visit(ir_end_primitive *);
 349
 350    uint32_t gather_channel(int orig_chan, uint32_t sampler);
 351    void swizzle_result(ir_texture_opcode op, int dest_components,
 352                        fs_reg orig_val, uint32_t sampler);
 353
 354    fs_inst *emit(fs_inst *inst);
 355    void emit(exec_list list);
 356
 357    fs_inst *emit(enum opcode opcode);
 358    fs_inst *emit(enum opcode opcode, const fs_reg &dst);
 359    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 360    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 361                  const fs_reg &src1);
 362    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 363                  const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 364    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 365                  fs_reg src[], int sources);
 366
 367    fs_inst *MOV(const fs_reg &dst, const fs_reg &src);
 368    fs_inst *NOT(const fs_reg &dst, const fs_reg &src);
 369    fs_inst *RNDD(const fs_reg &dst, const fs_reg &src);
 370    fs_inst *RNDE(const fs_reg &dst, const fs_reg &src);
 371    fs_inst *RNDZ(const fs_reg &dst, const fs_reg &src);
 372    fs_inst *FRC(const fs_reg &dst, const fs_reg &src);
 373    fs_inst *ADD(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 374    fs_inst *MUL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 375    fs_inst *MACH(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 376    fs_inst *MAC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 377    fs_inst *SHL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 378    fs_inst *SHR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 379    fs_inst *ASR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 380    fs_inst *AND(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 381    fs_inst *OR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 382    fs_inst *XOR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 383    fs_inst *IF(enum brw_predicate predicate);
 384    fs_inst *IF(const fs_reg &src0, const fs_reg &src1,
 385                enum brw_conditional_mod condition);
 386    fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
 387                 enum brw_conditional_mod condition);
 388    fs_inst *LRP(const fs_reg &dst, const fs_reg &a, const fs_reg &y,
 389                 const fs_reg &x);
 390    fs_inst *DEP_RESOLVE_MOV(int grf);
 391    fs_inst *BFREV(const fs_reg &dst, const fs_reg &value);
 392    fs_inst *BFE(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset,
 393                 const fs_reg &value);
 394    fs_inst *BFI1(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset);
 395    fs_inst *BFI2(const fs_reg &dst, const fs_reg &bfi1_dst,
 396                  const fs_reg &insert, const fs_reg &base);
 397    fs_inst *FBH(const fs_reg &dst, const fs_reg &value);
 398    fs_inst *FBL(const fs_reg &dst, const fs_reg &value);
 399    fs_inst *CBIT(const fs_reg &dst, const fs_reg &value);
 400    fs_inst *MAD(const fs_reg &dst, const fs_reg &c, const fs_reg &b,
 401                 const fs_reg &a);
 402    fs_inst *ADDC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 403    fs_inst *SUBB(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 404    fs_inst *SEL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 405
 406    int type_size(const struct glsl_type *type);
 407    fs_inst *get_instruction_generating_reg(fs_inst *start,
 408                                            fs_inst *end,
 409                                            const fs_reg &reg);
 410
 411    fs_inst *LOAD_PAYLOAD(const fs_reg &dst, fs_reg *src, int sources);
 412
 413    exec_list VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
 414                                         const fs_reg &surf_index,
 415                                         const fs_reg &varying_offset,
 416                                         uint32_t const_offset);
 417
 418    bool run_fs();
 419    bool run_vs();
 420    void optimize();
 421    void allocate_registers();
 422    void assign_binding_table_offsets();
 423    void setup_payload_gen4();
 424    void setup_payload_gen6();
 425    void setup_vs_payload();
 426    void assign_curb_setup();
 427    void calculate_urb_setup();
 428    void assign_urb_setup();
 429    void assign_vs_urb_setup();
 430    bool assign_regs(bool allow_spilling);
 431    void assign_regs_trivial();
 432    void get_used_mrfs(bool *mrf_used);
 433    void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
 434                                    int first_payload_node);
 435    void setup_mrf_hack_interference(struct ra_graph *g,
 436                                     int first_mrf_hack_node);
 437    int choose_spill_reg(struct ra_graph *g);
 438    void spill_reg(int spill_reg);
 439    void split_virtual_grfs();
 440    bool compact_virtual_grfs();
 441    void move_uniform_array_access_to_pull_constants();
 442    void assign_constant_locations();
 443    void demote_pull_constants();
 444    void invalidate_live_intervals();
 445    void calculate_live_intervals();
 446    void calculate_register_pressure();
 447    bool opt_algebraic();
 448    bool opt_cse();
 449    bool opt_cse_local(bblock_t *block);
 450    bool opt_copy_propagate();
 451    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 452    bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
 453    bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
 454                                  exec_list *acp);
 455    bool opt_register_renaming();
 456    bool register_coalesce();
 457    bool compute_to_mrf();
 458    bool dead_code_eliminate();
 459    bool remove_duplicate_mrf_writes();
 460    bool virtual_grf_interferes(int a, int b);
 461    void schedule_instructions(instruction_scheduler_mode mode);
 462    void insert_gen4_send_dependency_workarounds();
 463    void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
 464                                                     fs_inst *inst);
 465    void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
 466                                                      fs_inst *inst);
 467    void vfail(const char *msg, va_list args);
 468    void fail(const char *msg, ...);
 469    void no16(const char *msg, ...);
 470    void lower_uniform_pull_constant_loads();
 471    bool lower_load_payload();
 472
 473    void emit_dummy_fs();
 474    void emit_repclear_shader();
 475    fs_reg *emit_fragcoord_interpolation(bool pixel_center_integer,
 476                                         bool origin_upper_left);
 477    fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
 478                          glsl_interp_qualifier interpolation_mode,
 479                          bool is_centroid, bool is_sample);
 480    fs_reg *emit_frontfacing_interpolation();
 481    fs_reg *emit_samplepos_setup();
 482    fs_reg *emit_sampleid_setup();
 483    void emit_general_interpolation(fs_reg attr, const char *name,
 484                                    const glsl_type *type,
 485                                    glsl_interp_qualifier interpolation_mode,
 486                                    int location, bool mod_centroid,
 487                                    bool mod_sample);
 488    fs_reg *emit_vs_system_value(enum brw_reg_type type, int location);
 489    void emit_interpolation_setup_gen4();
 490    void emit_interpolation_setup_gen6();
 491    void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
 492    fs_reg rescale_texcoord(fs_reg coordinate, int coord_components,
 493                            bool is_rect, uint32_t sampler, int texunit);
 494    fs_inst *emit_texture_gen4(ir_texture_opcode op, fs_reg dst,
 495                               fs_reg coordinate, int coord_components,
 496                               fs_reg shadow_comp,
 497                               fs_reg lod, fs_reg lod2, int grad_components,
 498                               uint32_t sampler);
 499    fs_inst *emit_texture_gen5(ir_texture_opcode op, fs_reg dst,
 500                               fs_reg coordinate, int coord_components,
 501                               fs_reg shadow_comp,
 502                               fs_reg lod, fs_reg lod2, int grad_components,
 503                               fs_reg sample_index, uint32_t sampler,
 504                               bool has_offset);
 505    fs_inst *emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
 506                               fs_reg coordinate, int coord_components,
 507                               fs_reg shadow_comp,
 508                               fs_reg lod, fs_reg lod2, int grad_components,
 509                               fs_reg sample_index, fs_reg mcs, fs_reg sampler,
 510                               fs_reg offset_value);
 511    void emit_texture(ir_texture_opcode op,
 512                      const glsl_type *dest_type,
 513                      fs_reg coordinate, int components,
 514                      fs_reg shadow_c,
 515                      fs_reg lod, fs_reg dpdy, int grad_components,
 516                      fs_reg sample_index,
 517                      fs_reg offset, unsigned offset_components,
 518                      fs_reg mcs,
 519                      int gather_component,
 520                      bool is_cube_array,
 521                      bool is_rect,
 522                      uint32_t sampler,
 523                      fs_reg sampler_reg,
 524                      int texunit);
 525    fs_reg emit_mcs_fetch(fs_reg coordinate, int components, fs_reg sampler);
 526    void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
 527    fs_reg fix_math_operand(fs_reg src);
 528    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
 529    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
 530    void emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
 531                  const fs_reg &a);
 532    void emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &dst,
 533                     const fs_reg &src0, const fs_reg &src1);
 534    bool try_emit_saturate(ir_expression *ir);
 535    bool try_emit_line(ir_expression *ir);
 536    bool try_emit_mad(ir_expression *ir);
 537    void try_replace_with_sel();
 538    bool opt_peephole_sel();
 539    bool opt_peephole_predicated_break();
 540    bool opt_saturate_propagation();
 541    void emit_bool_to_cond_code(ir_rvalue *condition);
 542    void emit_if_gen6(ir_if *ir);
 543    void emit_unspill(bblock_t *block, fs_inst *inst, fs_reg reg,
 544                      uint32_t spill_offset, int count);
 545    void emit_spill(bblock_t *block, fs_inst *inst, fs_reg reg,
 546                    uint32_t spill_offset, int count);
 547
 548    void emit_fragment_program_code();
 549    void setup_fp_regs();
 550    fs_reg get_fp_src_reg(const prog_src_register *src);
 551    fs_reg get_fp_dst_reg(const prog_dst_register *dst);
 552    void emit_fp_alu1(enum opcode opcode,
 553                      const struct prog_instruction *fpi,
 554                      fs_reg dst, fs_reg src);
 555    void emit_fp_alu2(enum opcode opcode,
 556                      const struct prog_instruction *fpi,
 557                      fs_reg dst, fs_reg src0, fs_reg src1);
 558    void emit_fp_scalar_write(const struct prog_instruction *fpi,
 559                              fs_reg dst, fs_reg src);
 560    void emit_fp_scalar_math(enum opcode opcode,
 561                             const struct prog_instruction *fpi,
 562                             fs_reg dst, fs_reg src);
 563
 564    void emit_fp_minmax(const struct prog_instruction *fpi,
 565                        fs_reg dst, fs_reg src0, fs_reg src1);
 566
 567    void emit_fp_sop(enum brw_conditional_mod conditional_mod,
 568                     const struct prog_instruction *fpi,
 569                     fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
 570
 571    void emit_nir_code();
 572    void nir_setup_inputs(nir_shader *shader);
 573    void nir_setup_outputs(nir_shader *shader);
 574    void nir_setup_uniforms(nir_shader *shader);
 575    void nir_setup_uniform(nir_variable *var);
 576    void nir_setup_builtin_uniform(nir_variable *var);
 577    void nir_emit_impl(nir_function_impl *impl);
 578    void nir_emit_cf_list(exec_list *list);
 579    void nir_emit_if(nir_if *if_stmt);
 580    void nir_emit_loop(nir_loop *loop);
 581    void nir_emit_block(nir_block *block);
 582    void nir_emit_instr(nir_instr *instr);
 583    void nir_emit_alu(nir_alu_instr *instr);
 584    void nir_emit_intrinsic(nir_intrinsic_instr *instr);
 585    void nir_emit_texture(nir_tex_instr *instr);
 586    void nir_emit_load_const(nir_load_const_instr *instr);
 587    void nir_emit_jump(nir_jump_instr *instr);
 588    fs_reg get_nir_src(nir_src src);
 589    fs_reg get_nir_alu_src(nir_alu_instr *instr, unsigned src);
 590    fs_reg get_nir_dest(nir_dest dest);
 591    void emit_percomp(fs_inst *inst, unsigned wr_mask);
 592    void emit_percomp(enum opcode op, fs_reg dest, fs_reg src0,
 593                      unsigned wr_mask, bool saturate = false,
 594                      enum brw_predicate predicate = BRW_PREDICATE_NONE,
 595                      enum brw_conditional_mod mod = BRW_CONDITIONAL_NONE);
 596    void emit_percomp(enum opcode op, fs_reg dest, fs_reg src0, fs_reg src1,
 597                      unsigned wr_mask, bool saturate = false,
 598                      enum brw_predicate predicate = BRW_PREDICATE_NONE,
 599                      enum brw_conditional_mod mod = BRW_CONDITIONAL_NONE);
 600    void emit_math_percomp(enum opcode op, fs_reg dest, fs_reg src0,
 601                           unsigned wr_mask, bool saturate = false);
 602    void emit_math_percomp(enum opcode op, fs_reg dest, fs_reg src0,
 603                           fs_reg src1, unsigned wr_mask,
 604                           bool saturate = false);
 605    void emit_reduction(enum opcode op, fs_reg dest, fs_reg src,
 606                        unsigned num_components);
 607
 608    int setup_color_payload(fs_reg *dst, fs_reg color, unsigned components);
 609    void emit_alpha_test();
 610    fs_inst *emit_single_fb_write(fs_reg color1, fs_reg color2,
 611                                  fs_reg src0_alpha, unsigned components);
 612    void emit_fb_writes();
 613    void emit_urb_writes();
 614
 615    void emit_shader_time_begin();
 616    void emit_shader_time_end();
 617    void emit_shader_time_write(enum shader_time_shader_type type,
 618                                fs_reg value);
 619
 620    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 621                             fs_reg dst, fs_reg offset, fs_reg src0,
 622                             fs_reg src1);
 623
 624    void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
 625                                   fs_reg offset);
 626
 627    void emit_interpolate_expression(ir_expression *ir);
 628
 629    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 630                                fs_reg dst,
 631                                fs_reg src,
 632                                fs_inst *pre_rhs_inst,
 633                                fs_inst *last_rhs_inst);
 634    void emit_assignment_writes(fs_reg &l, fs_reg &r,
 635                                const glsl_type *type, bool predicated);
 636    void resolve_ud_negate(fs_reg *reg);
 637    void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
 638
 639    fs_reg get_timestamp();
 640
 641    struct brw_reg interp_reg(int location, int channel);
 642    void setup_uniform_values(ir_variable *ir);
 643    void setup_builtin_uniform_values(ir_variable *ir);
 644    int implied_mrf_writes(fs_inst *inst);
 645
 646    virtual void dump_instructions();
 647    virtual void dump_instructions(const char *name);
 648    void dump_instruction(backend_instruction *inst);
 649    void dump_instruction(backend_instruction *inst, FILE *file);
 650
 651    void visit_atomic_counter_intrinsic(ir_call *ir);
 652
 653    const void *const key;
 654    struct brw_stage_prog_data *prog_data;
 655    unsigned int sanity_param_count;
 656
 657    int *param_size;
 658
 659    int *virtual_grf_sizes;
 660    int virtual_grf_count;
 661    int virtual_grf_array_size;
 662    int *virtual_grf_start;
 663    int *virtual_grf_end;
 664    brw::fs_live_variables *live_intervals;
 665
 666    int *regs_live_at_ip;
 667
 668    /** Number of uniform variable components visited. */
 669    unsigned uniforms;
 670
 671    /** Byte-offset for the next available spot in the scratch space buffer. */
 672    unsigned last_scratch;
 673
 674    /**
 675     * Array mapping UNIFORM register numbers to the pull parameter index,
 676     * or -1 if this uniform register isn't being uploaded as a pull constant.
 677     */
 678    int *pull_constant_loc;
 679
 680    /**
 681     * Array mapping UNIFORM register numbers to the push parameter index,
 682     * or -1 if this uniform register isn't being uploaded as a push constant.
 683     */
 684    int *push_constant_loc;
 685
 686    struct hash_table *variable_ht;
 687    fs_reg frag_depth;
 688    fs_reg sample_mask;
 689    fs_reg outputs[VARYING_SLOT_MAX];
 690    unsigned output_components[VARYING_SLOT_MAX];
 691    fs_reg dual_src_output;
 692    bool do_dual_src;
 693    int first_non_payload_grf;
 694    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 695    int max_grf;
 696
 697    fs_reg *fp_temp_regs;
 698    fs_reg *fp_input_regs;
 699
 700    fs_reg *nir_locals;
 701    fs_reg *nir_globals;
 702    fs_reg nir_inputs;
 703    fs_reg nir_outputs;
 704    fs_reg nir_uniforms;
 705
 706    /** @{ debug annotation info */
 707    const char *current_annotation;
 708    const void *base_ir;
 709    /** @} */
 710
 711    bool failed;
 712    char *fail_msg;
 713    bool simd16_unsupported;
 714    char *no16_msg;
 715
 716    /* Result of last visit() method. */
 717    fs_reg result;
 718
 719    /** Register numbers for thread payload fields. */
 720    struct {
 721       uint8_t source_depth_reg;
 722       uint8_t source_w_reg;
 723       uint8_t aa_dest_stencil_reg;
 724       uint8_t dest_depth_reg;
 725       uint8_t sample_pos_reg;
 726       uint8_t sample_mask_in_reg;
 727       uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 728
 729       /** The number of thread payload registers the hardware will supply. */
 730       uint8_t num_regs;
 731    } payload;
 732
 733    bool source_depth_to_render_target;
 734    bool runtime_check_aads_emit;
 735
 736    fs_reg pixel_x;
 737    fs_reg pixel_y;
 738    fs_reg wpos_w;
 739    fs_reg pixel_w;
 740    fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 741    fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 742    fs_reg shader_start_time;
 743    fs_reg userplane[MAX_CLIP_PLANES];
 744
 745    int grf_used;
 746    bool spilled_any_registers;
 747
 748    const unsigned dispatch_width; /**< 8 or 16 */
 749 };
 750
 751 /**
 752  * The fragment shader code generator.
 753  *
 754  * Translates FS IR to actual i965 assembly code.
 755  */
 756 class fs_generator
 757 {
 758 public:
 759    fs_generator(struct brw_context *brw,
 760                 void *mem_ctx,
 761                 const void *key,
 762                 struct brw_stage_prog_data *prog_data,
 763                 struct gl_program *fp,
 764                 bool runtime_check_aads_emit,
 765                 const char *stage_abbrev);
 766    ~fs_generator();
 767
 768    void enable_debug(const char *shader_name);
 769    int generate_code(const cfg_t *cfg, int dispatch_width);
 770    const unsigned *get_assembly(unsigned int *assembly_size);
 771
 772 private:
 773    void fire_fb_write(fs_inst *inst,
 774                       struct brw_reg payload,
 775                       struct brw_reg implied_header,
 776                       GLuint nr);
 777    void generate_fb_write(fs_inst *inst, struct brw_reg payload);
 778    void generate_urb_write(fs_inst *inst, struct brw_reg payload);
 779    void generate_blorp_fb_write(fs_inst *inst);
 780    void generate_pixel_xy(struct brw_reg dst, bool is_x);
 781    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 782                          struct brw_reg *src);
 783    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 784                      struct brw_reg sampler_index);
 785    void generate_math_gen6(fs_inst *inst,
 786                            struct brw_reg dst,
 787                            struct brw_reg src0,
 788                            struct brw_reg src1);
 789    void generate_math_gen4(fs_inst *inst,
 790                            struct brw_reg dst,
 791                            struct brw_reg src);
 792    void generate_math_g45(fs_inst *inst,
 793                           struct brw_reg dst,
 794                           struct brw_reg src);
 795    void generate_ddx(enum opcode op, struct brw_reg dst, struct brw_reg src);
 796    void generate_ddy(enum opcode op, struct brw_reg dst, struct brw_reg src,
 797                      bool negate_value);
 798    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 799    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 800    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 801    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 802                                             struct brw_reg index,
 803                                             struct brw_reg offset);
 804    void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
 805                                                  struct brw_reg dst,
 806                                                  struct brw_reg surf_index,
 807                                                  struct brw_reg offset);
 808    void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 809                                             struct brw_reg index,
 810                                             struct brw_reg offset);
 811    void generate_varying_pull_constant_load_gen7(fs_inst *inst,
 812                                                  struct brw_reg dst,
 813                                                  struct brw_reg index,
 814                                                  struct brw_reg offset);
 815    void generate_mov_dispatch_to_flags(fs_inst *inst);
 816
 817    void generate_pixel_interpolator_query(fs_inst *inst,
 818                                           struct brw_reg dst,
 819                                           struct brw_reg src,
 820                                           struct brw_reg msg_data,
 821                                           unsigned msg_type);
 822
 823    void generate_set_omask(fs_inst *inst,
 824                            struct brw_reg dst,
 825                            struct brw_reg sample_mask);
 826
 827    void generate_set_sample_id(fs_inst *inst,
 828                                struct brw_reg dst,
 829                                struct brw_reg src0,
 830                                struct brw_reg src1);
 831
 832    void generate_set_simd4x2_offset(fs_inst *inst,
 833                                     struct brw_reg dst,
 834                                     struct brw_reg offset);
 835    void generate_discard_jump(fs_inst *inst);
 836
 837    void generate_pack_half_2x16_split(fs_inst *inst,
 838                                       struct brw_reg dst,
 839                                       struct brw_reg x,
 840                                       struct brw_reg y);
 841    void generate_unpack_half_2x16_split(fs_inst *inst,
 842                                         struct brw_reg dst,
 843                                         struct brw_reg src);
 844
 845    void generate_shader_time_add(fs_inst *inst,
 846                                  struct brw_reg payload,
 847                                  struct brw_reg offset,
 848                                  struct brw_reg value);
 849
 850    void generate_untyped_atomic(fs_inst *inst,
 851                                 struct brw_reg dst,
 852                                 struct brw_reg payload,
 853                                 struct brw_reg atomic_op,
 854                                 struct brw_reg surf_index);
 855
 856    void generate_untyped_surface_read(fs_inst *inst,
 857                                       struct brw_reg dst,
 858                                       struct brw_reg payload,
 859                                       struct brw_reg surf_index);
 860
 861    bool patch_discard_jumps_to_fb_writes();
 862
 863    struct brw_context *brw;
 864    struct gl_context *ctx;
 865
 866    struct brw_compile *p;
 867    const void * const key;
 868    struct brw_stage_prog_data * const prog_data;
 869
 870    const struct gl_program *prog;
 871
 872    unsigned dispatch_width; /**< 8 or 16 */
 873
 874    exec_list discard_halt_patches;
 875    bool runtime_check_aads_emit;
 876    bool debug_flag;
 877    const char *shader_name;
 878    const char *stage_abbrev;
 879    void *mem_ctx;
 880 };
 881
 882 bool brw_do_channel_expressions(struct exec_list *instructions);
 883 bool brw_do_vector_splitting(struct exec_list *instructions);