f40e58b8ca0f2b88b5dcac16903159226b07ba00
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs.h
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #pragma once
29
30 #include "brw_shader.h"
31 #include "brw_ir_fs.h"
32 #include "brw_fs_builder.h"
33
34 extern "C" {
35
36 #include <sys/types.h>
37
38 #include "main/macros.h"
39 #include "main/shaderobj.h"
40 #include "main/uniforms.h"
41 #include "program/prog_parameter.h"
42 #include "program/prog_print.h"
43 #include "program/prog_optimize.h"
44 #include "util/register_allocate.h"
45 #include "program/hash_table.h"
46 #include "brw_context.h"
47 #include "brw_eu.h"
48 #include "brw_wm.h"
49 #include "intel_asm_annotation.h"
50 }
51 #include "glsl/nir/glsl_types.h"
52 #include "glsl/ir.h"
53 #include "glsl/nir/nir.h"
54 #include "program/sampler.h"
55
56 struct bblock_t;
57 namespace {
58 struct acp_entry;
59 }
60
61 namespace brw {
62 class fs_live_variables;
63 }
64
65 struct brw_gs_compile;
66
67 static inline fs_reg
68 offset(fs_reg reg, const brw::fs_builder& bld, unsigned delta)
69 {
70 switch (reg.file) {
71 case BAD_FILE:
72 break;
73 case ARF:
74 case FIXED_GRF:
75 case MRF:
76 case VGRF:
77 case ATTR:
78 return byte_offset(reg,
79 delta * reg.component_size(bld.dispatch_width()));
80 case UNIFORM:
81 reg.reg_offset += delta;
82 break;
83 case IMM:
84 assert(delta == 0);
85 }
86 return reg;
87 }
88
89 /**
90 * The fragment shader front-end.
91 *
92 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
93 */
94 class fs_visitor : public backend_shader
95 {
96 public:
97 fs_visitor(const struct brw_compiler *compiler, void *log_data,
98 void *mem_ctx,
99 const void *key,
100 struct brw_stage_prog_data *prog_data,
101 struct gl_program *prog,
102 const nir_shader *shader,
103 unsigned dispatch_width,
104 int shader_time_index);
105 fs_visitor(const struct brw_compiler *compiler, void *log_data,
106 void *mem_ctx,
107 struct brw_gs_compile *gs_compile,
108 struct brw_gs_prog_data *prog_data,
109 const nir_shader *shader,
110 int shader_time_index);
111 void init();
112 ~fs_visitor();
113
114 fs_reg vgrf(const glsl_type *const type);
115 void import_uniforms(fs_visitor *v);
116 void setup_uniform_clipplane_values(gl_clip_plane *clip_planes);
117 void compute_clip_distance(gl_clip_plane *clip_planes);
118
119 uint32_t gather_channel(int orig_chan, uint32_t sampler);
120 void swizzle_result(ir_texture_opcode op, int dest_components,
121 fs_reg orig_val, uint32_t sampler);
122
123 fs_inst *get_instruction_generating_reg(fs_inst *start,
124 fs_inst *end,
125 const fs_reg &reg);
126
127 void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld,
128 const fs_reg &dst,
129 const fs_reg &surf_index,
130 const fs_reg &varying_offset,
131 uint32_t const_offset);
132 void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf);
133
134 bool run_fs(bool do_rep_send);
135 bool run_vs(gl_clip_plane *clip_planes);
136 bool run_gs();
137 bool run_cs();
138 void optimize();
139 void allocate_registers();
140 void setup_payload_gen4();
141 void setup_payload_gen6();
142 void setup_vs_payload();
143 void setup_gs_payload();
144 void setup_cs_payload();
145 void fixup_3src_null_dest();
146 void assign_curb_setup();
147 void calculate_urb_setup();
148 void assign_urb_setup();
149 void convert_attr_sources_to_hw_regs(fs_inst *inst);
150 void assign_vs_urb_setup();
151 void assign_gs_urb_setup();
152 bool assign_regs(bool allow_spilling);
153 void assign_regs_trivial();
154 void calculate_payload_ranges(int payload_node_count,
155 int *payload_last_use_ip);
156 void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
157 int first_payload_node);
158 int choose_spill_reg(struct ra_graph *g);
159 void spill_reg(int spill_reg);
160 void split_virtual_grfs();
161 bool compact_virtual_grfs();
162 void assign_constant_locations();
163 void demote_pull_constants();
164 void invalidate_live_intervals();
165 void calculate_live_intervals();
166 void calculate_register_pressure();
167 void validate();
168 bool opt_algebraic();
169 bool opt_redundant_discard_jumps();
170 bool opt_cse();
171 bool opt_cse_local(bblock_t *block);
172 bool opt_copy_propagate();
173 bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
174 bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
175 bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
176 exec_list *acp);
177 bool opt_register_renaming();
178 bool register_coalesce();
179 bool compute_to_mrf();
180 bool eliminate_find_live_channel();
181 bool dead_code_eliminate();
182 bool remove_duplicate_mrf_writes();
183
184 bool opt_sampler_eot();
185 bool virtual_grf_interferes(int a, int b);
186 void schedule_instructions(instruction_scheduler_mode mode);
187 void insert_gen4_send_dependency_workarounds();
188 void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
189 fs_inst *inst);
190 void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
191 fs_inst *inst);
192 void vfail(const char *msg, va_list args);
193 void fail(const char *msg, ...);
194 void no16(const char *msg);
195 void lower_uniform_pull_constant_loads();
196 bool lower_load_payload();
197 bool lower_logical_sends();
198 bool lower_integer_multiplication();
199 bool lower_simd_width();
200 bool opt_combine_constants();
201
202 void emit_dummy_fs();
203 void emit_repclear_shader();
204 fs_reg *emit_fragcoord_interpolation(bool pixel_center_integer,
205 bool origin_upper_left);
206 fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
207 glsl_interp_qualifier interpolation_mode,
208 bool is_centroid, bool is_sample);
209 fs_reg *emit_frontfacing_interpolation();
210 fs_reg *emit_samplepos_setup();
211 fs_reg *emit_sampleid_setup();
212 void emit_general_interpolation(fs_reg attr, const char *name,
213 const glsl_type *type,
214 glsl_interp_qualifier interpolation_mode,
215 int location, bool mod_centroid,
216 bool mod_sample);
217 fs_reg *emit_vs_system_value(int location);
218 void emit_interpolation_setup_gen4();
219 void emit_interpolation_setup_gen6();
220 void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
221 fs_reg rescale_texcoord(fs_reg coordinate, int coord_components,
222 bool is_rect, uint32_t sampler);
223 void emit_texture(ir_texture_opcode op,
224 const glsl_type *dest_type,
225 fs_reg coordinate, int components,
226 fs_reg shadow_c,
227 fs_reg lod, fs_reg dpdy, int grad_components,
228 fs_reg sample_index,
229 fs_reg offset,
230 fs_reg mcs,
231 int gather_component,
232 bool is_cube_array,
233 bool is_rect,
234 uint32_t sampler,
235 fs_reg sampler_reg);
236 fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
237 const fs_reg &sampler);
238 void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
239 fs_reg resolve_source_modifiers(const fs_reg &src);
240 void emit_discard_jump();
241 bool opt_peephole_sel();
242 bool opt_peephole_predicated_break();
243 bool opt_saturate_propagation();
244 bool opt_cmod_propagation();
245 bool opt_zero_samples();
246 void emit_unspill(bblock_t *block, fs_inst *inst, fs_reg reg,
247 uint32_t spill_offset, int count);
248 void emit_spill(bblock_t *block, fs_inst *inst, fs_reg reg,
249 uint32_t spill_offset, int count);
250
251 void emit_nir_code();
252 void nir_setup_inputs();
253 void nir_setup_outputs();
254 void nir_setup_uniforms();
255 void nir_emit_system_values();
256 void nir_emit_impl(nir_function_impl *impl);
257 void nir_emit_cf_list(exec_list *list);
258 void nir_emit_if(nir_if *if_stmt);
259 void nir_emit_loop(nir_loop *loop);
260 void nir_emit_block(nir_block *block);
261 void nir_emit_instr(nir_instr *instr);
262 void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr);
263 void nir_emit_load_const(const brw::fs_builder &bld,
264 nir_load_const_instr *instr);
265 void nir_emit_undef(const brw::fs_builder &bld,
266 nir_ssa_undef_instr *instr);
267 void nir_emit_vs_intrinsic(const brw::fs_builder &bld,
268 nir_intrinsic_instr *instr);
269 void nir_emit_gs_intrinsic(const brw::fs_builder &bld,
270 nir_intrinsic_instr *instr);
271 void nir_emit_fs_intrinsic(const brw::fs_builder &bld,
272 nir_intrinsic_instr *instr);
273 void nir_emit_cs_intrinsic(const brw::fs_builder &bld,
274 nir_intrinsic_instr *instr);
275 void nir_emit_intrinsic(const brw::fs_builder &bld,
276 nir_intrinsic_instr *instr);
277 void nir_emit_ssbo_atomic(const brw::fs_builder &bld,
278 int op, nir_intrinsic_instr *instr);
279 void nir_emit_texture(const brw::fs_builder &bld,
280 nir_tex_instr *instr);
281 void nir_emit_jump(const brw::fs_builder &bld,
282 nir_jump_instr *instr);
283 fs_reg get_nir_src(nir_src src);
284 fs_reg get_nir_dest(nir_dest dest);
285 fs_reg get_nir_image_deref(const nir_deref_var *deref);
286 void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst,
287 unsigned wr_mask);
288
289 bool optimize_frontfacing_ternary(nir_alu_instr *instr,
290 const fs_reg &result);
291
292 void emit_alpha_test();
293 fs_inst *emit_single_fb_write(const brw::fs_builder &bld,
294 fs_reg color1, fs_reg color2,
295 fs_reg src0_alpha, unsigned components);
296 void emit_fb_writes();
297 void emit_urb_writes(const fs_reg &gs_vertex_count = fs_reg());
298 void set_gs_stream_control_data_bits(const fs_reg &vertex_count,
299 unsigned stream_id);
300 void emit_gs_control_data_bits(const fs_reg &vertex_count);
301 void emit_gs_end_primitive(const nir_src &vertex_count_nir_src);
302 void emit_gs_vertex(const nir_src &vertex_count_nir_src,
303 unsigned stream_id);
304 void emit_gs_thread_end();
305 void emit_gs_input_load(const fs_reg &dst, const nir_src &vertex_src,
306 unsigned offset, unsigned num_components);
307 void emit_cs_terminate();
308 fs_reg *emit_cs_local_invocation_id_setup();
309 fs_reg *emit_cs_work_group_id_setup();
310
311 void emit_barrier();
312
313 void emit_shader_time_begin();
314 void emit_shader_time_end();
315 void SHADER_TIME_ADD(const brw::fs_builder &bld,
316 int shader_time_subindex,
317 fs_reg value);
318
319 fs_reg get_timestamp(const brw::fs_builder &bld);
320
321 struct brw_reg interp_reg(int location, int channel);
322
323 int implied_mrf_writes(fs_inst *inst);
324
325 virtual void dump_instructions();
326 virtual void dump_instructions(const char *name);
327 void dump_instruction(backend_instruction *inst);
328 void dump_instruction(backend_instruction *inst, FILE *file);
329
330 const void *const key;
331 const struct brw_sampler_prog_key_data *key_tex;
332
333 struct brw_gs_compile *gs_compile;
334
335 struct brw_stage_prog_data *prog_data;
336 struct gl_program *prog;
337
338 int *param_size;
339
340 int *virtual_grf_start;
341 int *virtual_grf_end;
342 brw::fs_live_variables *live_intervals;
343
344 int *regs_live_at_ip;
345
346 /** Number of uniform variable components visited. */
347 unsigned uniforms;
348
349 /** Byte-offset for the next available spot in the scratch space buffer. */
350 unsigned last_scratch;
351
352 /**
353 * Array mapping UNIFORM register numbers to the pull parameter index,
354 * or -1 if this uniform register isn't being uploaded as a pull constant.
355 */
356 int *pull_constant_loc;
357
358 /**
359 * Array mapping UNIFORM register numbers to the push parameter index,
360 * or -1 if this uniform register isn't being uploaded as a push constant.
361 */
362 int *push_constant_loc;
363
364 fs_reg frag_depth;
365 fs_reg frag_stencil;
366 fs_reg sample_mask;
367 fs_reg outputs[VARYING_SLOT_MAX];
368 unsigned output_components[VARYING_SLOT_MAX];
369 fs_reg dual_src_output;
370 bool do_dual_src;
371 int first_non_payload_grf;
372 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
373 unsigned max_grf;
374
375 fs_reg *nir_locals;
376 fs_reg *nir_ssa_values;
377 fs_reg nir_inputs;
378 fs_reg nir_outputs;
379 fs_reg *nir_system_values;
380
381 bool failed;
382 char *fail_msg;
383 bool simd16_unsupported;
384 char *no16_msg;
385
386 /* Result of last visit() method. Still used by emit_texture() */
387 fs_reg result;
388
389 /** Register numbers for thread payload fields. */
390 struct thread_payload {
391 uint8_t source_depth_reg;
392 uint8_t source_w_reg;
393 uint8_t aa_dest_stencil_reg;
394 uint8_t dest_depth_reg;
395 uint8_t sample_pos_reg;
396 uint8_t sample_mask_in_reg;
397 uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
398 uint8_t local_invocation_id_reg;
399
400 /** The number of thread payload registers the hardware will supply. */
401 uint8_t num_regs;
402 } payload;
403
404 bool source_depth_to_render_target;
405 bool runtime_check_aads_emit;
406
407 fs_reg pixel_x;
408 fs_reg pixel_y;
409 fs_reg wpos_w;
410 fs_reg pixel_w;
411 fs_reg delta_xy[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
412 fs_reg shader_start_time;
413 fs_reg userplane[MAX_CLIP_PLANES];
414 fs_reg final_gs_vertex_count;
415 fs_reg control_data_bits;
416
417 unsigned grf_used;
418 bool spilled_any_registers;
419
420 const unsigned dispatch_width; /**< 8 or 16 */
421
422 int shader_time_index;
423
424 unsigned promoted_constants;
425 brw::fs_builder bld;
426 };
427
428 /**
429 * The fragment shader code generator.
430 *
431 * Translates FS IR to actual i965 assembly code.
432 */
433 class fs_generator
434 {
435 public:
436 fs_generator(const struct brw_compiler *compiler, void *log_data,
437 void *mem_ctx,
438 const void *key,
439 struct brw_stage_prog_data *prog_data,
440 unsigned promoted_constants,
441 bool runtime_check_aads_emit,
442 const char *stage_abbrev);
443 ~fs_generator();
444
445 void enable_debug(const char *shader_name);
446 int generate_code(const cfg_t *cfg, int dispatch_width);
447 const unsigned *get_assembly(unsigned int *assembly_size);
448
449 private:
450 void fire_fb_write(fs_inst *inst,
451 struct brw_reg payload,
452 struct brw_reg implied_header,
453 GLuint nr);
454 void generate_fb_write(fs_inst *inst, struct brw_reg payload);
455 void generate_urb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload);
456 void generate_urb_write(fs_inst *inst, struct brw_reg payload);
457 void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
458 void generate_stencil_ref_packing(fs_inst *inst, struct brw_reg dst,
459 struct brw_reg src);
460 void generate_barrier(fs_inst *inst, struct brw_reg src);
461 void generate_blorp_fb_write(fs_inst *inst);
462 void generate_linterp(fs_inst *inst, struct brw_reg dst,
463 struct brw_reg *src);
464 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
465 struct brw_reg sampler_index);
466 void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst,
467 struct brw_reg src,
468 struct brw_reg surf_index);
469 void generate_math_gen6(fs_inst *inst,
470 struct brw_reg dst,
471 struct brw_reg src0,
472 struct brw_reg src1);
473 void generate_math_gen4(fs_inst *inst,
474 struct brw_reg dst,
475 struct brw_reg src);
476 void generate_math_g45(fs_inst *inst,
477 struct brw_reg dst,
478 struct brw_reg src);
479 void generate_ddx(enum opcode op, struct brw_reg dst, struct brw_reg src);
480 void generate_ddy(enum opcode op, struct brw_reg dst, struct brw_reg src,
481 bool negate_value);
482 void generate_scratch_write(fs_inst *inst, struct brw_reg src);
483 void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
484 void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
485 void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
486 struct brw_reg index,
487 struct brw_reg offset);
488 void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
489 struct brw_reg dst,
490 struct brw_reg surf_index,
491 struct brw_reg offset);
492 void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
493 struct brw_reg index,
494 struct brw_reg offset);
495 void generate_varying_pull_constant_load_gen7(fs_inst *inst,
496 struct brw_reg dst,
497 struct brw_reg index,
498 struct brw_reg offset);
499 void generate_mov_dispatch_to_flags(fs_inst *inst);
500
501 void generate_pixel_interpolator_query(fs_inst *inst,
502 struct brw_reg dst,
503 struct brw_reg src,
504 struct brw_reg msg_data,
505 unsigned msg_type);
506
507 void generate_set_sample_id(fs_inst *inst,
508 struct brw_reg dst,
509 struct brw_reg src0,
510 struct brw_reg src1);
511
512 void generate_set_simd4x2_offset(fs_inst *inst,
513 struct brw_reg dst,
514 struct brw_reg offset);
515 void generate_discard_jump(fs_inst *inst);
516
517 void generate_pack_half_2x16_split(fs_inst *inst,
518 struct brw_reg dst,
519 struct brw_reg x,
520 struct brw_reg y);
521 void generate_unpack_half_2x16_split(fs_inst *inst,
522 struct brw_reg dst,
523 struct brw_reg src);
524
525 void generate_shader_time_add(fs_inst *inst,
526 struct brw_reg payload,
527 struct brw_reg offset,
528 struct brw_reg value);
529
530 bool patch_discard_jumps_to_fb_writes();
531
532 const struct brw_compiler *compiler;
533 void *log_data; /* Passed to compiler->*_log functions */
534
535 const struct brw_device_info *devinfo;
536
537 struct brw_codegen *p;
538 const void * const key;
539 struct brw_stage_prog_data * const prog_data;
540
541 unsigned dispatch_width; /**< 8 or 16 */
542
543 exec_list discard_halt_patches;
544 unsigned promoted_constants;
545 bool runtime_check_aads_emit;
546 bool debug_flag;
547 const char *shader_name;
548 const char *stage_abbrev;
549 void *mem_ctx;
550 };
551
552 bool brw_do_channel_expressions(struct exec_list *instructions);
553 bool brw_do_vector_splitting(struct exec_list *instructions);