src/mesa/drivers/dri/i965/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29
  30 #include "brw_shader.h"
  31
  32 extern "C" {
  33
  34 #include <sys/types.h>
  35
  36 #include "main/macros.h"
  37 #include "main/shaderobj.h"
  38 #include "main/uniforms.h"
  39 #include "program/prog_parameter.h"
  40 #include "program/prog_print.h"
  41 #include "program/prog_optimize.h"
  42 #include "util/register_allocate.h"
  43 #include "program/sampler.h"
  44 #include "program/hash_table.h"
  45 #include "brw_context.h"
  46 #include "brw_eu.h"
  47 #include "brw_wm.h"
  48 #include "brw_shader.h"
  49 #include "intel_asm_annotation.h"
  50 }
  51 #include "glsl/glsl_types.h"
  52 #include "glsl/ir.h"
  53
  54 #define MAX_SAMPLER_MESSAGE_SIZE 11
  55
  56 struct bblock_t;
  57 namespace {
  58    struct acp_entry;
  59 }
  60
  61 namespace brw {
  62    class fs_live_variables;
  63 }
  64
  65 class fs_visitor;
  66
  67 class fs_reg : public backend_reg {
  68 public:
  69    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  70
  71    void init();
  72
  73    fs_reg();
  74    explicit fs_reg(float f);
  75    explicit fs_reg(int32_t i);
  76    explicit fs_reg(uint32_t u);
  77    fs_reg(struct brw_reg fixed_hw_reg);
  78    fs_reg(enum register_file file, int reg);
  79    fs_reg(enum register_file file, int reg, enum brw_reg_type type);
  80    fs_reg(enum register_file file, int reg, enum brw_reg_type type, uint8_t width);
  81    fs_reg(fs_visitor *v, const struct glsl_type *type);
  82
  83    bool equals(const fs_reg &r) const;
  84    bool is_valid_3src() const;
  85    bool is_contiguous() const;
  86
  87    fs_reg &apply_stride(unsigned stride);
  88    /** Smear a channel of the reg to all channels. */
  89    fs_reg &set_smear(unsigned subreg);
  90
  91    /**
  92     * Offset in bytes from the start of the register.  Values up to a
  93     * backend_reg::reg_offset unit are valid.
  94     */
  95    int subreg_offset;
  96
  97    fs_reg *reladdr;
  98
  99    /**
 100     * The register width.  This indicates how many hardware values are
 101     * represented by each virtual value.  Valid values are 1, 8, or 16.
 102     * For immediate values, this is 1.  Most of the rest of the time, it
 103     * will be equal to the dispatch width.
 104     */
 105    uint8_t width;
 106
 107    /**
 108     * Returns the effective register width when used as a source in the
 109     * given instruction.  Registers such as uniforms and immediates
 110     * effectively take on the width of the instruction in which they are
 111     * used.
 112     */
 113    uint8_t effective_width(const fs_visitor *v) const;
 114
 115    /** Register region horizontal stride */
 116    uint8_t stride;
 117 };
 118
 119 static inline fs_reg
 120 retype(fs_reg reg, enum brw_reg_type type)
 121 {
 122    reg.fixed_hw_reg.type = reg.type = type;
 123    return reg;
 124 }
 125
 126 static inline fs_reg
 127 byte_offset(fs_reg reg, unsigned delta)
 128 {
 129    switch (reg.file) {
 130    case BAD_FILE:
 131       break;
 132    case GRF:
 133       reg.reg_offset += delta / 32;
 134       break;
 135    case MRF:
 136       reg.reg += delta / 32;
 137       break;
 138    default:
 139       assert(delta == 0);
 140    }
 141    reg.subreg_offset += delta % 32;
 142    return reg;
 143 }
 144
 145 static inline fs_reg
 146 offset(fs_reg reg, unsigned delta)
 147 {
 148    assert(reg.stride > 0);
 149    switch (reg.file) {
 150    case BAD_FILE:
 151       break;
 152    case GRF:
 153    case MRF:
 154       return byte_offset(reg, delta * reg.width * reg.stride * type_sz(reg.type));
 155    case UNIFORM:
 156       reg.reg_offset += delta;
 157       break;
 158    default:
 159       assert(delta == 0);
 160    }
 161    return reg;
 162 }
 163
 164 /**
 165  * Get either of the 8-component halves of a 16-component register.
 166  *
 167  * Note: this also works if \c reg represents a SIMD16 pair of registers.
 168  */
 169 static inline fs_reg
 170 half(fs_reg reg, unsigned idx)
 171 {
 172    assert(idx < 2);
 173    assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM));
 174    assert(reg.width == 16);
 175    reg.width = 8;
 176    return byte_offset(reg, 8 * idx * reg.stride * type_sz(reg.type));
 177 }
 178
 179 static const fs_reg reg_undef;
 180
 181 class ip_record : public exec_node {
 182 public:
 183    DECLARE_RALLOC_CXX_OPERATORS(ip_record)
 184
 185    ip_record(int ip)
 186    {
 187       this->ip = ip;
 188    }
 189
 190    int ip;
 191 };
 192
 193 class fs_inst : public backend_instruction {
 194    fs_inst &operator=(const fs_inst &);
 195
 196    void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
 197              fs_reg *src, int sources);
 198
 199 public:
 200    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 201
 202    fs_inst();
 203    fs_inst(enum opcode opcode, uint8_t exec_size);
 204    fs_inst(enum opcode opcode, const fs_reg &dst);
 205    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 206            const fs_reg &src0);
 207    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 208    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 209            const fs_reg &src0, const fs_reg &src1);
 210    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 211            const fs_reg &src1);
 212    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 213            const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 214    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 215            const fs_reg &src1, const fs_reg &src2);
 216    fs_inst(enum opcode opcode, const fs_reg &dst, fs_reg src[], int sources);
 217    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 218            fs_reg src[], int sources);
 219    fs_inst(const fs_inst &that);
 220
 221    void resize_sources(uint8_t num_sources);
 222
 223    bool equals(fs_inst *inst) const;
 224    bool overwrites_reg(const fs_reg &reg) const;
 225    bool is_send_from_grf() const;
 226    bool is_partial_write() const;
 227    int regs_read(fs_visitor *v, int arg) const;
 228    bool can_do_source_mods(struct brw_context *brw);
 229
 230    bool reads_flag() const;
 231    bool writes_flag() const;
 232
 233    fs_reg dst;
 234    fs_reg *src;
 235
 236    uint8_t sources; /**< Number of fs_reg sources. */
 237
 238    /**
 239     * Execution size of the instruction.  This is used by the generator to
 240     * generate the correct binary for the given fs_inst.  Current valid
 241     * values are 1, 8, 16.
 242     */
 243    uint8_t exec_size;
 244
 245    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 246     * mod and predication.
 247     */
 248    uint8_t flag_subreg;
 249
 250    uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
 251    bool eot:1;
 252    bool header_present:1;
 253    bool shadow_compare:1;
 254    bool force_uncompressed:1;
 255    bool force_sechalf:1;
 256    bool pi_noperspective:1;   /**< Pixel interpolator noperspective flag */
 257 };
 258
 259 /**
 260  * The fragment shader front-end.
 261  *
 262  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
 263  */
 264 class fs_visitor : public backend_visitor
 265 {
 266 public:
 267    const fs_reg reg_null_f;
 268    const fs_reg reg_null_d;
 269    const fs_reg reg_null_ud;
 270
 271    fs_visitor(struct brw_context *brw,
 272               void *mem_ctx,
 273               const struct brw_wm_prog_key *key,
 274               struct brw_wm_prog_data *prog_data,
 275               struct gl_shader_program *shader_prog,
 276               struct gl_fragment_program *fp,
 277               unsigned dispatch_width);
 278    ~fs_visitor();
 279    void init();
 280
 281    fs_reg *variable_storage(ir_variable *var);
 282    int virtual_grf_alloc(int size);
 283    void import_uniforms(fs_visitor *v);
 284
 285    void visit(ir_variable *ir);
 286    void visit(ir_assignment *ir);
 287    void visit(ir_dereference_variable *ir);
 288    void visit(ir_dereference_record *ir);
 289    void visit(ir_dereference_array *ir);
 290    void visit(ir_expression *ir);
 291    void visit(ir_texture *ir);
 292    void visit(ir_if *ir);
 293    void visit(ir_constant *ir);
 294    void visit(ir_swizzle *ir);
 295    void visit(ir_return *ir);
 296    void visit(ir_loop *ir);
 297    void visit(ir_loop_jump *ir);
 298    void visit(ir_discard *ir);
 299    void visit(ir_call *ir);
 300    void visit(ir_function *ir);
 301    void visit(ir_function_signature *ir);
 302    void visit(ir_emit_vertex *);
 303    void visit(ir_end_primitive *);
 304
 305    uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
 306    void swizzle_result(ir_texture *ir, fs_reg orig_val, uint32_t sampler);
 307
 308    fs_inst *emit(fs_inst *inst);
 309    void emit(exec_list list);
 310
 311    fs_inst *emit(enum opcode opcode);
 312    fs_inst *emit(enum opcode opcode, const fs_reg &dst);
 313    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 314    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 315                  const fs_reg &src1);
 316    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 317                  const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 318    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 319                  fs_reg src[], int sources);
 320
 321    fs_inst *MOV(const fs_reg &dst, const fs_reg &src);
 322    fs_inst *NOT(const fs_reg &dst, const fs_reg &src);
 323    fs_inst *RNDD(const fs_reg &dst, const fs_reg &src);
 324    fs_inst *RNDE(const fs_reg &dst, const fs_reg &src);
 325    fs_inst *RNDZ(const fs_reg &dst, const fs_reg &src);
 326    fs_inst *FRC(const fs_reg &dst, const fs_reg &src);
 327    fs_inst *ADD(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 328    fs_inst *MUL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 329    fs_inst *MACH(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 330    fs_inst *MAC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 331    fs_inst *SHL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 332    fs_inst *SHR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 333    fs_inst *ASR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 334    fs_inst *AND(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 335    fs_inst *OR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 336    fs_inst *XOR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 337    fs_inst *IF(enum brw_predicate predicate);
 338    fs_inst *IF(const fs_reg &src0, const fs_reg &src1,
 339                enum brw_conditional_mod condition);
 340    fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
 341                 enum brw_conditional_mod condition);
 342    fs_inst *LRP(const fs_reg &dst, const fs_reg &a, const fs_reg &y,
 343                 const fs_reg &x);
 344    fs_inst *DEP_RESOLVE_MOV(int grf);
 345    fs_inst *BFREV(const fs_reg &dst, const fs_reg &value);
 346    fs_inst *BFE(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset,
 347                 const fs_reg &value);
 348    fs_inst *BFI1(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset);
 349    fs_inst *BFI2(const fs_reg &dst, const fs_reg &bfi1_dst,
 350                  const fs_reg &insert, const fs_reg &base);
 351    fs_inst *FBH(const fs_reg &dst, const fs_reg &value);
 352    fs_inst *FBL(const fs_reg &dst, const fs_reg &value);
 353    fs_inst *CBIT(const fs_reg &dst, const fs_reg &value);
 354    fs_inst *MAD(const fs_reg &dst, const fs_reg &c, const fs_reg &b,
 355                 const fs_reg &a);
 356    fs_inst *ADDC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 357    fs_inst *SUBB(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 358    fs_inst *SEL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 359
 360    int type_size(const struct glsl_type *type);
 361    fs_inst *get_instruction_generating_reg(fs_inst *start,
 362                                            fs_inst *end,
 363                                            const fs_reg &reg);
 364
 365    fs_inst *LOAD_PAYLOAD(const fs_reg &dst, fs_reg *src, int sources);
 366
 367    exec_list VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
 368                                         const fs_reg &surf_index,
 369                                         const fs_reg &varying_offset,
 370                                         uint32_t const_offset);
 371
 372    bool run();
 373    void assign_binding_table_offsets();
 374    void setup_payload_gen4();
 375    void setup_payload_gen6();
 376    void assign_curb_setup();
 377    void calculate_urb_setup();
 378    void assign_urb_setup();
 379    bool assign_regs(bool allow_spilling);
 380    void assign_regs_trivial();
 381    void get_used_mrfs(bool *mrf_used);
 382    void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
 383                                    int first_payload_node);
 384    void setup_mrf_hack_interference(struct ra_graph *g,
 385                                     int first_mrf_hack_node);
 386    int choose_spill_reg(struct ra_graph *g);
 387    void spill_reg(int spill_reg);
 388    void split_virtual_grfs();
 389    bool compact_virtual_grfs();
 390    void move_uniform_array_access_to_pull_constants();
 391    void assign_constant_locations();
 392    void demote_pull_constants();
 393    void invalidate_live_intervals();
 394    void calculate_live_intervals();
 395    void calculate_register_pressure();
 396    bool opt_algebraic();
 397    bool opt_cse();
 398    bool opt_cse_local(bblock_t *block);
 399    bool opt_copy_propagate();
 400    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 401    bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
 402    bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
 403                                  exec_list *acp);
 404    void opt_drop_redundant_mov_to_flags();
 405    bool opt_register_renaming();
 406    bool register_coalesce();
 407    bool compute_to_mrf();
 408    bool dead_code_eliminate();
 409    bool remove_duplicate_mrf_writes();
 410    bool virtual_grf_interferes(int a, int b);
 411    void schedule_instructions(instruction_scheduler_mode mode);
 412    void insert_gen4_send_dependency_workarounds();
 413    void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
 414                                                     fs_inst *inst);
 415    void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
 416                                                      fs_inst *inst);
 417    void vfail(const char *msg, va_list args);
 418    void fail(const char *msg, ...);
 419    void no16(const char *msg, ...);
 420    void lower_uniform_pull_constant_loads();
 421    bool lower_load_payload();
 422
 423    void push_force_uncompressed();
 424    void pop_force_uncompressed();
 425
 426    void emit_dummy_fs();
 427    void emit_repclear_shader();
 428    fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
 429    fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
 430                          glsl_interp_qualifier interpolation_mode,
 431                          bool is_centroid, bool is_sample);
 432    fs_reg *emit_frontfacing_interpolation();
 433    fs_reg *emit_samplepos_setup();
 434    fs_reg *emit_sampleid_setup(ir_variable *ir);
 435    fs_reg *emit_general_interpolation(ir_variable *ir);
 436    void emit_interpolation_setup_gen4();
 437    void emit_interpolation_setup_gen6();
 438    void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
 439    fs_reg rescale_texcoord(ir_texture *ir, fs_reg coordinate,
 440                            bool is_rect, uint32_t sampler, int texunit);
 441    fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 442                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 443                               uint32_t sampler);
 444    fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 445                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 446                               fs_reg sample_index, uint32_t sampler);
 447    fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 448                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 449                               fs_reg sample_index, fs_reg mcs, fs_reg sampler);
 450    fs_reg emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, fs_reg sampler);
 451    void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
 452    fs_reg fix_math_operand(fs_reg src);
 453    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
 454    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
 455    void emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
 456                  const fs_reg &a);
 457    void emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &dst,
 458                     const fs_reg &src0, const fs_reg &src1);
 459    bool try_emit_saturate(ir_expression *ir);
 460    bool try_emit_mad(ir_expression *ir);
 461    void try_replace_with_sel();
 462    bool opt_peephole_sel();
 463    bool opt_peephole_predicated_break();
 464    bool opt_saturate_propagation();
 465    void emit_bool_to_cond_code(ir_rvalue *condition);
 466    void emit_if_gen6(ir_if *ir);
 467    void emit_unspill(bblock_t *block, fs_inst *inst, fs_reg reg,
 468                      uint32_t spill_offset, int count);
 469    void emit_spill(bblock_t *block, fs_inst *inst, fs_reg reg,
 470                    uint32_t spill_offset, int count);
 471
 472    void emit_fragment_program_code();
 473    void setup_fp_regs();
 474    fs_reg get_fp_src_reg(const prog_src_register *src);
 475    fs_reg get_fp_dst_reg(const prog_dst_register *dst);
 476    void emit_fp_alu1(enum opcode opcode,
 477                      const struct prog_instruction *fpi,
 478                      fs_reg dst, fs_reg src);
 479    void emit_fp_alu2(enum opcode opcode,
 480                      const struct prog_instruction *fpi,
 481                      fs_reg dst, fs_reg src0, fs_reg src1);
 482    void emit_fp_scalar_write(const struct prog_instruction *fpi,
 483                              fs_reg dst, fs_reg src);
 484    void emit_fp_scalar_math(enum opcode opcode,
 485                             const struct prog_instruction *fpi,
 486                             fs_reg dst, fs_reg src);
 487
 488    void emit_fp_minmax(const struct prog_instruction *fpi,
 489                        fs_reg dst, fs_reg src0, fs_reg src1);
 490
 491    void emit_fp_sop(enum brw_conditional_mod conditional_mod,
 492                     const struct prog_instruction *fpi,
 493                     fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
 494
 495    void emit_color_write(fs_reg color, int index, int first_color_mrf);
 496    void emit_alpha_test();
 497    fs_inst *emit_single_fb_write(fs_reg color1, fs_reg color2,
 498                                  fs_reg src0_alpha, unsigned components);
 499    void emit_fb_writes();
 500
 501    void emit_shader_time_begin();
 502    void emit_shader_time_end();
 503    void emit_shader_time_write(enum shader_time_shader_type type,
 504                                fs_reg value);
 505
 506    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 507                             fs_reg dst, fs_reg offset, fs_reg src0,
 508                             fs_reg src1);
 509
 510    void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
 511                                   fs_reg offset);
 512
 513    void emit_interpolate_expression(ir_expression *ir);
 514
 515    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 516                                fs_reg dst,
 517                                fs_reg src,
 518                                fs_inst *pre_rhs_inst,
 519                                fs_inst *last_rhs_inst);
 520    void emit_assignment_writes(fs_reg &l, fs_reg &r,
 521                                const glsl_type *type, bool predicated);
 522    void resolve_ud_negate(fs_reg *reg);
 523    void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
 524
 525    fs_reg get_timestamp();
 526
 527    struct brw_reg interp_reg(int location, int channel);
 528    void setup_uniform_values(ir_variable *ir);
 529    void setup_builtin_uniform_values(ir_variable *ir);
 530    int implied_mrf_writes(fs_inst *inst);
 531
 532    virtual void dump_instructions();
 533    virtual void dump_instructions(const char *name);
 534    void dump_instruction(backend_instruction *inst);
 535    void dump_instruction(backend_instruction *inst, FILE *file);
 536
 537    void visit_atomic_counter_intrinsic(ir_call *ir);
 538
 539    const void *const key;
 540    struct brw_stage_prog_data *prog_data;
 541    unsigned int sanity_param_count;
 542
 543    int *param_size;
 544
 545    int *virtual_grf_sizes;
 546    int virtual_grf_count;
 547    int virtual_grf_array_size;
 548    int *virtual_grf_start;
 549    int *virtual_grf_end;
 550    brw::fs_live_variables *live_intervals;
 551
 552    int *regs_live_at_ip;
 553
 554    /** Number of uniform variable components visited. */
 555    unsigned uniforms;
 556
 557    /** Byte-offset for the next available spot in the scratch space buffer. */
 558    unsigned last_scratch;
 559
 560    /**
 561     * Array mapping UNIFORM register numbers to the pull parameter index,
 562     * or -1 if this uniform register isn't being uploaded as a pull constant.
 563     */
 564    int *pull_constant_loc;
 565
 566    /**
 567     * Array mapping UNIFORM register numbers to the push parameter index,
 568     * or -1 if this uniform register isn't being uploaded as a push constant.
 569     */
 570    int *push_constant_loc;
 571
 572    struct hash_table *variable_ht;
 573    fs_reg frag_depth;
 574    fs_reg sample_mask;
 575    fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
 576    unsigned output_components[BRW_MAX_DRAW_BUFFERS];
 577    fs_reg dual_src_output;
 578    bool do_dual_src;
 579    int first_non_payload_grf;
 580    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 581    int max_grf;
 582
 583    fs_reg *fp_temp_regs;
 584    fs_reg *fp_input_regs;
 585
 586    /** @{ debug annotation info */
 587    const char *current_annotation;
 588    const void *base_ir;
 589    /** @} */
 590
 591    bool failed;
 592    char *fail_msg;
 593    bool simd16_unsupported;
 594    char *no16_msg;
 595
 596    /* Result of last visit() method. */
 597    fs_reg result;
 598
 599    /** Register numbers for thread payload fields. */
 600    struct {
 601       uint8_t source_depth_reg;
 602       uint8_t source_w_reg;
 603       uint8_t aa_dest_stencil_reg;
 604       uint8_t dest_depth_reg;
 605       uint8_t sample_pos_reg;
 606       uint8_t sample_mask_in_reg;
 607       uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 608
 609       /** The number of thread payload registers the hardware will supply. */
 610       uint8_t num_regs;
 611    } payload;
 612
 613    bool source_depth_to_render_target;
 614    bool runtime_check_aads_emit;
 615
 616    fs_reg pixel_x;
 617    fs_reg pixel_y;
 618    fs_reg wpos_w;
 619    fs_reg pixel_w;
 620    fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 621    fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 622    fs_reg shader_start_time;
 623
 624    int grf_used;
 625    bool spilled_any_registers;
 626
 627    const unsigned dispatch_width; /**< 8 or 16 */
 628
 629    int force_uncompressed_stack;
 630 };
 631
 632 /**
 633  * The fragment shader code generator.
 634  *
 635  * Translates FS IR to actual i965 assembly code.
 636  */
 637 class fs_generator
 638 {
 639 public:
 640    fs_generator(struct brw_context *brw,
 641                 void *mem_ctx,
 642                 const struct brw_wm_prog_key *key,
 643                 struct brw_wm_prog_data *prog_data,
 644                 struct gl_shader_program *shader_prog,
 645                 struct gl_fragment_program *fp,
 646                 bool runtime_check_aads_emit,
 647                 bool debug_flag);
 648    ~fs_generator();
 649
 650    const unsigned *generate_assembly(const cfg_t *simd8_cfg,
 651                                      const cfg_t *simd16_cfg,
 652                                      unsigned *assembly_size);
 653
 654 private:
 655    void generate_code(const cfg_t *cfg);
 656    void fire_fb_write(fs_inst *inst,
 657                       GLuint base_reg,
 658                       struct brw_reg implied_header,
 659                       GLuint nr);
 660    void generate_fb_write(fs_inst *inst);
 661    void generate_blorp_fb_write(fs_inst *inst);
 662    void generate_rep_fb_write(fs_inst *inst);
 663    void generate_pixel_xy(struct brw_reg dst, bool is_x);
 664    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 665                          struct brw_reg *src);
 666    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 667                      struct brw_reg sampler_index);
 668    void generate_math_gen6(fs_inst *inst,
 669                            struct brw_reg dst,
 670                            struct brw_reg src0,
 671                            struct brw_reg src1);
 672    void generate_math_gen4(fs_inst *inst,
 673                            struct brw_reg dst,
 674                            struct brw_reg src);
 675    void generate_math_g45(fs_inst *inst,
 676                           struct brw_reg dst,
 677                           struct brw_reg src);
 678    void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src, struct brw_reg quality);
 679    void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 680                      struct brw_reg quality, bool negate_value);
 681    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 682    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 683    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 684    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 685                                             struct brw_reg index,
 686                                             struct brw_reg offset);
 687    void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
 688                                                  struct brw_reg dst,
 689                                                  struct brw_reg surf_index,
 690                                                  struct brw_reg offset);
 691    void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 692                                             struct brw_reg index,
 693                                             struct brw_reg offset);
 694    void generate_varying_pull_constant_load_gen7(fs_inst *inst,
 695                                                  struct brw_reg dst,
 696                                                  struct brw_reg index,
 697                                                  struct brw_reg offset);
 698    void generate_mov_dispatch_to_flags(fs_inst *inst);
 699
 700    void generate_pixel_interpolator_query(fs_inst *inst,
 701                                           struct brw_reg dst,
 702                                           struct brw_reg src,
 703                                           struct brw_reg msg_data,
 704                                           unsigned msg_type);
 705
 706    void generate_set_omask(fs_inst *inst,
 707                            struct brw_reg dst,
 708                            struct brw_reg sample_mask);
 709
 710    void generate_set_sample_id(fs_inst *inst,
 711                                struct brw_reg dst,
 712                                struct brw_reg src0,
 713                                struct brw_reg src1);
 714
 715    void generate_set_simd4x2_offset(fs_inst *inst,
 716                                     struct brw_reg dst,
 717                                     struct brw_reg offset);
 718    void generate_discard_jump(fs_inst *inst);
 719
 720    void generate_pack_half_2x16_split(fs_inst *inst,
 721                                       struct brw_reg dst,
 722                                       struct brw_reg x,
 723                                       struct brw_reg y);
 724    void generate_unpack_half_2x16_split(fs_inst *inst,
 725                                         struct brw_reg dst,
 726                                         struct brw_reg src);
 727
 728    void generate_shader_time_add(fs_inst *inst,
 729                                  struct brw_reg payload,
 730                                  struct brw_reg offset,
 731                                  struct brw_reg value);
 732
 733    void generate_untyped_atomic(fs_inst *inst,
 734                                 struct brw_reg dst,
 735                                 struct brw_reg atomic_op,
 736                                 struct brw_reg surf_index);
 737
 738    void generate_untyped_surface_read(fs_inst *inst,
 739                                       struct brw_reg dst,
 740                                       struct brw_reg surf_index);
 741
 742    bool patch_discard_jumps_to_fb_writes();
 743
 744    struct brw_context *brw;
 745    struct gl_context *ctx;
 746
 747    struct brw_compile *p;
 748    gl_shader_stage stage;
 749    const void * const key;
 750    struct brw_stage_prog_data * const prog_data;
 751
 752    struct gl_shader_program * const shader_prog;
 753    const struct gl_program *prog;
 754
 755    unsigned dispatch_width; /**< 8 or 16 */
 756
 757    exec_list discard_halt_patches;
 758    bool runtime_check_aads_emit;
 759    const bool debug_flag;
 760    void *mem_ctx;
 761 };
 762
 763 bool brw_do_channel_expressions(struct exec_list *instructions);
 764 bool brw_do_vector_splitting(struct exec_list *instructions);
 765 bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);
 766
 767 struct brw_reg brw_reg_from_fs_reg(fs_reg *reg);