src/mesa/drivers/dri/i965/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29
  30 #include "brw_shader.h"
  31
  32 extern "C" {
  33
  34 #include <sys/types.h>
  35
  36 #include "main/macros.h"
  37 #include "main/shaderobj.h"
  38 #include "main/uniforms.h"
  39 #include "program/prog_parameter.h"
  40 #include "program/prog_print.h"
  41 #include "program/prog_optimize.h"
  42 #include "program/register_allocate.h"
  43 #include "program/sampler.h"
  44 #include "program/hash_table.h"
  45 #include "brw_context.h"
  46 #include "brw_eu.h"
  47 #include "brw_wm.h"
  48 #include "brw_shader.h"
  49 #include "intel_asm_printer.h"
  50 }
  51 #include "gen8_generator.h"
  52 #include "glsl/glsl_types.h"
  53 #include "glsl/ir.h"
  54
  55 #define MAX_SAMPLER_MESSAGE_SIZE 11
  56
  57 class bblock_t;
  58 namespace {
  59    struct acp_entry;
  60 }
  61
  62 namespace brw {
  63    class fs_live_variables;
  64 }
  65
  66 class fs_reg {
  67 public:
  68    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  69
  70    void init();
  71
  72    fs_reg();
  73    fs_reg(float f);
  74    fs_reg(int32_t i);
  75    fs_reg(uint32_t u);
  76    fs_reg(struct brw_reg fixed_hw_reg);
  77    fs_reg(enum register_file file, int reg);
  78    fs_reg(enum register_file file, int reg, uint32_t type);
  79    fs_reg(class fs_visitor *v, const struct glsl_type *type);
  80
  81    bool equals(const fs_reg &r) const;
  82    bool is_zero() const;
  83    bool is_one() const;
  84    bool is_null() const;
  85    bool is_valid_3src() const;
  86    bool is_contiguous() const;
  87    bool is_accumulator() const;
  88
  89    fs_reg &apply_stride(unsigned stride);
  90    /** Smear a channel of the reg to all channels. */
  91    fs_reg &set_smear(unsigned subreg);
  92
  93    /** Register file: GRF, MRF, IMM. */
  94    enum register_file file;
  95    /** Register type.  BRW_REGISTER_TYPE_* */
  96    uint8_t type;
  97    /**
  98     * Register number.  For MRF, it's the hardware register.  For
  99     * GRF, it's a virtual register number until register allocation
 100     */
 101    uint16_t reg;
 102    /**
 103     * Offset from the start of the contiguous register block.
 104     *
 105     * For pre-register-allocation GRFs, this is in units of a float per pixel
 106     * (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
 107     * For uniforms, this is in units of 1 float.
 108     */
 109    int reg_offset;
 110    /**
 111     * Offset in bytes from the start of the register.  Values up to a
 112     * backend_reg::reg_offset unit are valid.
 113     */
 114    int subreg_offset;
 115
 116    /** Value for file == IMM */
 117    union {
 118       int32_t i;
 119       uint32_t u;
 120       float f;
 121    } imm;
 122
 123    struct brw_reg fixed_hw_reg;
 124
 125    fs_reg *reladdr;
 126
 127    bool negate;
 128    bool abs;
 129
 130    /** Register region horizontal stride */
 131    uint8_t stride;
 132 };
 133
 134 static inline fs_reg
 135 retype(fs_reg reg, unsigned type)
 136 {
 137    reg.fixed_hw_reg.type = reg.type = type;
 138    return reg;
 139 }
 140
 141 static inline fs_reg
 142 offset(fs_reg reg, unsigned delta)
 143 {
 144    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 145    reg.reg_offset += delta;
 146    return reg;
 147 }
 148
 149 static inline fs_reg
 150 byte_offset(fs_reg reg, unsigned delta)
 151 {
 152    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 153    reg.subreg_offset += delta;
 154    return reg;
 155 }
 156
 157 /**
 158  * Get either of the 8-component halves of a 16-component register.
 159  *
 160  * Note: this also works if \c reg represents a SIMD16 pair of registers.
 161  */
 162 static inline fs_reg
 163 half(const fs_reg &reg, unsigned idx)
 164 {
 165    assert(idx < 2);
 166    assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM));
 167    return byte_offset(reg, 8 * idx * reg.stride * type_sz(reg.type));
 168 }
 169
 170 static const fs_reg reg_undef;
 171 static const fs_reg reg_null_f(retype(brw_null_reg(), BRW_REGISTER_TYPE_F));
 172 static const fs_reg reg_null_d(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 173 static const fs_reg reg_null_ud(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
 174
 175 class ip_record : public exec_node {
 176 public:
 177    DECLARE_RALLOC_CXX_OPERATORS(ip_record)
 178
 179    ip_record(int ip)
 180    {
 181       this->ip = ip;
 182    }
 183
 184    int ip;
 185 };
 186
 187 class fs_inst : public backend_instruction {
 188    fs_inst &operator=(const fs_inst &);
 189
 190 public:
 191    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 192
 193    void init(enum opcode opcode, const fs_reg &dst, fs_reg *src, int sources);
 194
 195    fs_inst(enum opcode opcode = BRW_OPCODE_NOP, const fs_reg &dst = reg_undef);
 196    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 197    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 198            const fs_reg &src1);
 199    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 200            const fs_reg &src1, const fs_reg &src2);
 201    fs_inst(enum opcode opcode, const fs_reg &dst, fs_reg src[], int sources);
 202    fs_inst(const fs_inst &that);
 203
 204    void resize_sources(uint8_t num_sources);
 205
 206    bool equals(fs_inst *inst) const;
 207    bool overwrites_reg(const fs_reg &reg) const;
 208    bool is_send_from_grf() const;
 209    bool is_partial_write() const;
 210    int regs_read(fs_visitor *v, int arg) const;
 211
 212    bool reads_flag() const;
 213    bool writes_flag() const;
 214
 215    fs_reg dst;
 216    fs_reg *src;
 217
 218    uint32_t texture_offset; /**< Texture offset bitfield */
 219    uint32_t offset; /* spill/unspill offset */
 220
 221    uint8_t sources; /**< Number of fs_reg sources. */
 222    uint8_t conditional_mod; /**< BRW_CONDITIONAL_* */
 223
 224    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 225     * mod and predication.
 226     */
 227    uint8_t flag_subreg;
 228
 229    uint8_t mlen; /**< SEND message length */
 230    uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
 231    int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 232    uint8_t sampler;
 233    uint8_t target; /**< MRT target. */
 234    bool saturate:1;
 235    bool eot:1;
 236    bool header_present:1;
 237    bool shadow_compare:1;
 238    bool force_uncompressed:1;
 239    bool force_sechalf:1;
 240    bool force_writemask_all:1;
 241 };
 242
 243 /**
 244  * The fragment shader front-end.
 245  *
 246  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
 247  */
 248 class fs_visitor : public backend_visitor
 249 {
 250 public:
 251
 252    fs_visitor(struct brw_context *brw,
 253               void *mem_ctx,
 254               const struct brw_wm_prog_key *key,
 255               struct brw_wm_prog_data *prog_data,
 256               struct gl_shader_program *shader_prog,
 257               struct gl_fragment_program *fp,
 258               unsigned dispatch_width);
 259    ~fs_visitor();
 260
 261    fs_reg *variable_storage(ir_variable *var);
 262    int virtual_grf_alloc(int size);
 263    void import_uniforms(fs_visitor *v);
 264
 265    void visit(ir_variable *ir);
 266    void visit(ir_assignment *ir);
 267    void visit(ir_dereference_variable *ir);
 268    void visit(ir_dereference_record *ir);
 269    void visit(ir_dereference_array *ir);
 270    void visit(ir_expression *ir);
 271    void visit(ir_texture *ir);
 272    void visit(ir_if *ir);
 273    void visit(ir_constant *ir);
 274    void visit(ir_swizzle *ir);
 275    void visit(ir_return *ir);
 276    void visit(ir_loop *ir);
 277    void visit(ir_loop_jump *ir);
 278    void visit(ir_discard *ir);
 279    void visit(ir_call *ir);
 280    void visit(ir_function *ir);
 281    void visit(ir_function_signature *ir);
 282    void visit(ir_emit_vertex *);
 283    void visit(ir_end_primitive *);
 284
 285    uint32_t gather_channel(ir_texture *ir, int sampler);
 286    void swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler);
 287
 288    bool can_do_source_mods(fs_inst *inst);
 289
 290    fs_inst *emit(fs_inst *inst);
 291    void emit(exec_list list);
 292
 293    fs_inst *emit(enum opcode opcode);
 294    fs_inst *emit(enum opcode opcode, fs_reg dst);
 295    fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0);
 296    fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
 297    fs_inst *emit(enum opcode opcode, fs_reg dst,
 298                  fs_reg src0, fs_reg src1, fs_reg src2);
 299    fs_inst *emit(enum opcode opcode, fs_reg dst,
 300                  fs_reg src[], int sources);
 301
 302    fs_inst *MOV(fs_reg dst, fs_reg src);
 303    fs_inst *NOT(fs_reg dst, fs_reg src);
 304    fs_inst *RNDD(fs_reg dst, fs_reg src);
 305    fs_inst *RNDE(fs_reg dst, fs_reg src);
 306    fs_inst *RNDZ(fs_reg dst, fs_reg src);
 307    fs_inst *FRC(fs_reg dst, fs_reg src);
 308    fs_inst *ADD(fs_reg dst, fs_reg src0, fs_reg src1);
 309    fs_inst *MUL(fs_reg dst, fs_reg src0, fs_reg src1);
 310    fs_inst *MACH(fs_reg dst, fs_reg src0, fs_reg src1);
 311    fs_inst *MAC(fs_reg dst, fs_reg src0, fs_reg src1);
 312    fs_inst *SHL(fs_reg dst, fs_reg src0, fs_reg src1);
 313    fs_inst *SHR(fs_reg dst, fs_reg src0, fs_reg src1);
 314    fs_inst *ASR(fs_reg dst, fs_reg src0, fs_reg src1);
 315    fs_inst *AND(fs_reg dst, fs_reg src0, fs_reg src1);
 316    fs_inst *OR(fs_reg dst, fs_reg src0, fs_reg src1);
 317    fs_inst *XOR(fs_reg dst, fs_reg src0, fs_reg src1);
 318    fs_inst *IF(uint32_t predicate);
 319    fs_inst *IF(fs_reg src0, fs_reg src1, uint32_t condition);
 320    fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
 321                 uint32_t condition);
 322    fs_inst *LRP(fs_reg dst, fs_reg a, fs_reg y, fs_reg x);
 323    fs_inst *DEP_RESOLVE_MOV(int grf);
 324    fs_inst *BFREV(fs_reg dst, fs_reg value);
 325    fs_inst *BFE(fs_reg dst, fs_reg bits, fs_reg offset, fs_reg value);
 326    fs_inst *BFI1(fs_reg dst, fs_reg bits, fs_reg offset);
 327    fs_inst *BFI2(fs_reg dst, fs_reg bfi1_dst, fs_reg insert, fs_reg base);
 328    fs_inst *FBH(fs_reg dst, fs_reg value);
 329    fs_inst *FBL(fs_reg dst, fs_reg value);
 330    fs_inst *CBIT(fs_reg dst, fs_reg value);
 331    fs_inst *MAD(fs_reg dst, fs_reg c, fs_reg b, fs_reg a);
 332    fs_inst *ADDC(fs_reg dst, fs_reg src0, fs_reg src1);
 333    fs_inst *SUBB(fs_reg dst, fs_reg src0, fs_reg src1);
 334    fs_inst *SEL(fs_reg dst, fs_reg src0, fs_reg src1);
 335
 336    int type_size(const struct glsl_type *type);
 337    fs_inst *get_instruction_generating_reg(fs_inst *start,
 338                                            fs_inst *end,
 339                                            const fs_reg &reg);
 340
 341    fs_inst *LOAD_PAYLOAD(const fs_reg &dst, fs_reg *src, int sources);
 342
 343    exec_list VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
 344                                         const fs_reg &surf_index,
 345                                         const fs_reg &varying_offset,
 346                                         uint32_t const_offset);
 347
 348    bool run();
 349    void assign_binding_table_offsets();
 350    void setup_payload_gen4();
 351    void setup_payload_gen6();
 352    void assign_curb_setup();
 353    void calculate_urb_setup();
 354    void assign_urb_setup();
 355    bool assign_regs(bool allow_spilling);
 356    void assign_regs_trivial();
 357    void get_used_mrfs(bool *mrf_used);
 358    void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
 359                                    int first_payload_node);
 360    void setup_mrf_hack_interference(struct ra_graph *g,
 361                                     int first_mrf_hack_node);
 362    int choose_spill_reg(struct ra_graph *g);
 363    void spill_reg(int spill_reg);
 364    void split_virtual_grfs();
 365    void compact_virtual_grfs();
 366    void move_uniform_array_access_to_pull_constants();
 367    void assign_constant_locations();
 368    void demote_pull_constants();
 369    void invalidate_live_intervals();
 370    void calculate_live_intervals();
 371    void calculate_register_pressure();
 372    bool opt_algebraic();
 373    bool opt_cse();
 374    bool opt_cse_local(bblock_t *block, exec_list *aeb);
 375    bool opt_copy_propagate();
 376    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 377    bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
 378    bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
 379                                  exec_list *acp);
 380    void opt_drop_redundant_mov_to_flags();
 381    bool register_coalesce();
 382    bool compute_to_mrf();
 383    bool dead_code_eliminate();
 384    bool remove_duplicate_mrf_writes();
 385    bool virtual_grf_interferes(int a, int b);
 386    void schedule_instructions(instruction_scheduler_mode mode);
 387    void insert_gen4_send_dependency_workarounds();
 388    void insert_gen4_pre_send_dependency_workarounds(fs_inst *inst);
 389    void insert_gen4_post_send_dependency_workarounds(fs_inst *inst);
 390    void vfail(const char *msg, va_list args);
 391    void fail(const char *msg, ...);
 392    void no16(const char *msg, ...);
 393    void lower_uniform_pull_constant_loads();
 394    bool lower_load_payload();
 395
 396    void push_force_uncompressed();
 397    void pop_force_uncompressed();
 398
 399    void emit_dummy_fs();
 400    fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
 401    fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
 402                          glsl_interp_qualifier interpolation_mode,
 403                          bool is_centroid, bool is_sample);
 404    fs_reg *emit_frontfacing_interpolation(ir_variable *ir);
 405    fs_reg *emit_samplepos_setup(ir_variable *ir);
 406    fs_reg *emit_sampleid_setup(ir_variable *ir);
 407    fs_reg *emit_general_interpolation(ir_variable *ir);
 408    void emit_interpolation_setup_gen4();
 409    void emit_interpolation_setup_gen6();
 410    void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
 411    fs_reg rescale_texcoord(ir_texture *ir, fs_reg coordinate,
 412                            bool is_rect, int sampler, int texunit);
 413    fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 414                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2);
 415    fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 416                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 417                               fs_reg sample_index);
 418    fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 419                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 420                               fs_reg sample_index, fs_reg mcs, int sampler);
 421    fs_reg emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, int sampler);
 422    void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
 423    fs_reg fix_math_operand(fs_reg src);
 424    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
 425    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
 426    void emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
 427                  const fs_reg &a);
 428    void emit_minmax(uint32_t conditionalmod, const fs_reg &dst,
 429                     const fs_reg &src0, const fs_reg &src1);
 430    bool try_emit_saturate(ir_expression *ir);
 431    bool try_emit_mad(ir_expression *ir);
 432    void try_replace_with_sel();
 433    bool opt_peephole_sel();
 434    bool opt_peephole_predicated_break();
 435    bool opt_saturate_propagation();
 436    void emit_bool_to_cond_code(ir_rvalue *condition);
 437    void emit_if_gen6(ir_if *ir);
 438    void emit_unspill(fs_inst *inst, fs_reg reg, uint32_t spill_offset,
 439                      int count);
 440
 441    void emit_fragment_program_code();
 442    void setup_fp_regs();
 443    fs_reg get_fp_src_reg(const prog_src_register *src);
 444    fs_reg get_fp_dst_reg(const prog_dst_register *dst);
 445    void emit_fp_alu1(enum opcode opcode,
 446                      const struct prog_instruction *fpi,
 447                      fs_reg dst, fs_reg src);
 448    void emit_fp_alu2(enum opcode opcode,
 449                      const struct prog_instruction *fpi,
 450                      fs_reg dst, fs_reg src0, fs_reg src1);
 451    void emit_fp_scalar_write(const struct prog_instruction *fpi,
 452                              fs_reg dst, fs_reg src);
 453    void emit_fp_scalar_math(enum opcode opcode,
 454                             const struct prog_instruction *fpi,
 455                             fs_reg dst, fs_reg src);
 456
 457    void emit_fp_minmax(const struct prog_instruction *fpi,
 458                        fs_reg dst, fs_reg src0, fs_reg src1);
 459
 460    void emit_fp_sop(uint32_t conditional_mod,
 461                     const struct prog_instruction *fpi,
 462                     fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
 463
 464    void emit_color_write(int target, int index, int first_color_mrf);
 465    void emit_alpha_test();
 466    void emit_fb_writes();
 467
 468    void emit_shader_time_begin();
 469    void emit_shader_time_end();
 470    void emit_shader_time_write(enum shader_time_shader_type type,
 471                                fs_reg value);
 472
 473    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 474                             fs_reg dst, fs_reg offset, fs_reg src0,
 475                             fs_reg src1);
 476
 477    void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
 478                                   fs_reg offset);
 479
 480    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 481                                fs_reg dst,
 482                                fs_reg src,
 483                                fs_inst *pre_rhs_inst,
 484                                fs_inst *last_rhs_inst);
 485    void emit_assignment_writes(fs_reg &l, fs_reg &r,
 486                                const glsl_type *type, bool predicated);
 487    void resolve_ud_negate(fs_reg *reg);
 488    void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
 489
 490    fs_reg get_timestamp();
 491
 492    struct brw_reg interp_reg(int location, int channel);
 493    void setup_uniform_values(ir_variable *ir);
 494    void setup_builtin_uniform_values(ir_variable *ir);
 495    int implied_mrf_writes(fs_inst *inst);
 496
 497    virtual void dump_instructions();
 498    virtual void dump_instructions(const char *name);
 499    void dump_instruction(backend_instruction *inst);
 500    void dump_instruction(backend_instruction *inst, FILE *file);
 501
 502    void visit_atomic_counter_intrinsic(ir_call *ir);
 503
 504    struct gl_fragment_program *fp;
 505    const struct brw_wm_prog_key *const key;
 506    struct brw_wm_prog_data *prog_data;
 507    unsigned int sanity_param_count;
 508
 509    int *param_size;
 510
 511    int *virtual_grf_sizes;
 512    int virtual_grf_count;
 513    int virtual_grf_array_size;
 514    int *virtual_grf_start;
 515    int *virtual_grf_end;
 516    brw::fs_live_variables *live_intervals;
 517
 518    int *regs_live_at_ip;
 519
 520    /** Number of uniform variable components visited. */
 521    unsigned uniforms;
 522
 523    /** Byte-offset for the next available spot in the scratch space buffer. */
 524    unsigned last_scratch;
 525
 526    /**
 527     * Array mapping UNIFORM register numbers to the pull parameter index,
 528     * or -1 if this uniform register isn't being uploaded as a pull constant.
 529     */
 530    int *pull_constant_loc;
 531
 532    /**
 533     * Array mapping UNIFORM register numbers to the push parameter index,
 534     * or -1 if this uniform register isn't being uploaded as a push constant.
 535     */
 536    int *push_constant_loc;
 537
 538    struct hash_table *variable_ht;
 539    fs_reg frag_depth;
 540    fs_reg sample_mask;
 541    fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
 542    unsigned output_components[BRW_MAX_DRAW_BUFFERS];
 543    fs_reg dual_src_output;
 544    bool do_dual_src;
 545    int first_non_payload_grf;
 546    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 547    int max_grf;
 548
 549    fs_reg *fp_temp_regs;
 550    fs_reg *fp_input_regs;
 551
 552    /** @{ debug annotation info */
 553    const char *current_annotation;
 554    const void *base_ir;
 555    /** @} */
 556
 557    bool failed;
 558    char *fail_msg;
 559    bool simd16_unsupported;
 560    char *no16_msg;
 561
 562    /* Result of last visit() method. */
 563    fs_reg result;
 564
 565    /** Register numbers for thread payload fields. */
 566    struct {
 567       uint8_t source_depth_reg;
 568       uint8_t source_w_reg;
 569       uint8_t aa_dest_stencil_reg;
 570       uint8_t dest_depth_reg;
 571       uint8_t sample_pos_reg;
 572       uint8_t sample_mask_in_reg;
 573       uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 574
 575       /** The number of thread payload registers the hardware will supply. */
 576       uint8_t num_regs;
 577    } payload;
 578
 579    bool source_depth_to_render_target;
 580    bool runtime_check_aads_emit;
 581
 582    fs_reg pixel_x;
 583    fs_reg pixel_y;
 584    fs_reg wpos_w;
 585    fs_reg pixel_w;
 586    fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 587    fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 588    fs_reg shader_start_time;
 589
 590    int grf_used;
 591    bool spilled_any_registers;
 592
 593    const unsigned dispatch_width; /**< 8 or 16 */
 594
 595    int force_uncompressed_stack;
 596 };
 597
 598 /**
 599  * The fragment shader code generator.
 600  *
 601  * Translates FS IR to actual i965 assembly code.
 602  */
 603 class fs_generator
 604 {
 605 public:
 606    fs_generator(struct brw_context *brw,
 607                 void *mem_ctx,
 608                 const struct brw_wm_prog_key *key,
 609                 struct brw_wm_prog_data *prog_data,
 610                 struct gl_shader_program *prog,
 611                 struct gl_fragment_program *fp,
 612                 bool dual_source_output,
 613                 bool runtime_check_aads_emit,
 614                 bool debug_flag);
 615    ~fs_generator();
 616
 617    const unsigned *generate_assembly(exec_list *simd8_instructions,
 618                                      exec_list *simd16_instructions,
 619                                      unsigned *assembly_size);
 620
 621 private:
 622    void generate_code(exec_list *instructions);
 623    void fire_fb_write(fs_inst *inst,
 624                       GLuint base_reg,
 625                       struct brw_reg implied_header,
 626                       GLuint nr);
 627    void generate_fb_write(fs_inst *inst);
 628    void generate_blorp_fb_write(fs_inst *inst);
 629    void generate_pixel_xy(struct brw_reg dst, bool is_x);
 630    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 631                          struct brw_reg *src);
 632    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 633    void generate_math_gen6(fs_inst *inst,
 634                            struct brw_reg dst,
 635                            struct brw_reg src0,
 636                            struct brw_reg src1);
 637    void generate_math_gen4(fs_inst *inst,
 638                            struct brw_reg dst,
 639                            struct brw_reg src);
 640    void generate_math_g45(fs_inst *inst,
 641                           struct brw_reg dst,
 642                           struct brw_reg src);
 643    void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 644    void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 645                      bool negate_value);
 646    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 647    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 648    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 649    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 650                                             struct brw_reg index,
 651                                             struct brw_reg offset);
 652    void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
 653                                                  struct brw_reg dst,
 654                                                  struct brw_reg surf_index,
 655                                                  struct brw_reg offset);
 656    void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 657                                             struct brw_reg index,
 658                                             struct brw_reg offset);
 659    void generate_varying_pull_constant_load_gen7(fs_inst *inst,
 660                                                  struct brw_reg dst,
 661                                                  struct brw_reg index,
 662                                                  struct brw_reg offset);
 663    void generate_mov_dispatch_to_flags(fs_inst *inst);
 664
 665    void generate_set_omask(fs_inst *inst,
 666                            struct brw_reg dst,
 667                            struct brw_reg sample_mask);
 668
 669    void generate_set_sample_id(fs_inst *inst,
 670                                struct brw_reg dst,
 671                                struct brw_reg src0,
 672                                struct brw_reg src1);
 673
 674    void generate_set_simd4x2_offset(fs_inst *inst,
 675                                     struct brw_reg dst,
 676                                     struct brw_reg offset);
 677    void generate_discard_jump(fs_inst *inst);
 678
 679    void generate_pack_half_2x16_split(fs_inst *inst,
 680                                       struct brw_reg dst,
 681                                       struct brw_reg x,
 682                                       struct brw_reg y);
 683    void generate_unpack_half_2x16_split(fs_inst *inst,
 684                                         struct brw_reg dst,
 685                                         struct brw_reg src);
 686
 687    void generate_shader_time_add(fs_inst *inst,
 688                                  struct brw_reg payload,
 689                                  struct brw_reg offset,
 690                                  struct brw_reg value);
 691
 692    void generate_untyped_atomic(fs_inst *inst,
 693                                 struct brw_reg dst,
 694                                 struct brw_reg atomic_op,
 695                                 struct brw_reg surf_index);
 696
 697    void generate_untyped_surface_read(fs_inst *inst,
 698                                       struct brw_reg dst,
 699                                       struct brw_reg surf_index);
 700
 701    bool patch_discard_jumps_to_fb_writes();
 702
 703    struct brw_context *brw;
 704    struct gl_context *ctx;
 705
 706    struct brw_compile *p;
 707    const struct brw_wm_prog_key *const key;
 708    struct brw_wm_prog_data *prog_data;
 709
 710    struct gl_shader_program *prog;
 711    const struct gl_fragment_program *fp;
 712
 713    unsigned dispatch_width; /**< 8 or 16 */
 714
 715    exec_list discard_halt_patches;
 716    bool dual_source_output;
 717    bool runtime_check_aads_emit;
 718    const bool debug_flag;
 719    void *mem_ctx;
 720 };
 721
 722 /**
 723  * The fragment shader code generator.
 724  *
 725  * Translates FS IR to actual i965 assembly code.
 726  */
 727 class gen8_fs_generator : public gen8_generator
 728 {
 729 public:
 730    gen8_fs_generator(struct brw_context *brw,
 731                      void *mem_ctx,
 732                      const struct brw_wm_prog_key *key,
 733                      struct brw_wm_prog_data *prog_data,
 734                      struct gl_shader_program *prog,
 735                      struct gl_fragment_program *fp,
 736                      bool dual_source_output);
 737    ~gen8_fs_generator();
 738
 739    const unsigned *generate_assembly(exec_list *simd8_instructions,
 740                                      exec_list *simd16_instructions,
 741                                      unsigned *assembly_size);
 742
 743 private:
 744    void generate_code(exec_list *instructions);
 745    void generate_fb_write(fs_inst *inst);
 746    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 747                          struct brw_reg *src);
 748    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 749    void generate_math1(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 750    void generate_math2(fs_inst *inst, struct brw_reg dst,
 751                        struct brw_reg src0, struct brw_reg src1);
 752    void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 753    void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 754                      bool negate_value);
 755    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 756    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 757    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 758    void generate_uniform_pull_constant_load(fs_inst *inst,
 759                                             struct brw_reg dst,
 760                                             struct brw_reg index,
 761                                             struct brw_reg offset);
 762    void generate_varying_pull_constant_load(fs_inst *inst,
 763                                             struct brw_reg dst,
 764                                             struct brw_reg index,
 765                                             struct brw_reg offset);
 766    void generate_mov_dispatch_to_flags(fs_inst *ir);
 767    void generate_set_omask(fs_inst *ir,
 768                            struct brw_reg dst,
 769                            struct brw_reg sample_mask);
 770    void generate_set_sample_id(fs_inst *ir,
 771                                struct brw_reg dst,
 772                                struct brw_reg src0,
 773                                struct brw_reg src1);
 774    void generate_set_simd4x2_offset(fs_inst *ir,
 775                                     struct brw_reg dst,
 776                                     struct brw_reg offset);
 777    void generate_pack_half_2x16_split(fs_inst *inst,
 778                                       struct brw_reg dst,
 779                                       struct brw_reg x,
 780                                       struct brw_reg y);
 781    void generate_unpack_half_2x16_split(fs_inst *inst,
 782                                         struct brw_reg dst,
 783                                         struct brw_reg src);
 784    void generate_untyped_atomic(fs_inst *inst,
 785                                 struct brw_reg dst,
 786                                 struct brw_reg atomic_op,
 787                                 struct brw_reg surf_index);
 788
 789    void generate_untyped_surface_read(fs_inst *inst,
 790                                       struct brw_reg dst,
 791                                       struct brw_reg surf_index);
 792    void generate_discard_jump(fs_inst *ir);
 793
 794    bool patch_discard_jumps_to_fb_writes();
 795
 796    const struct brw_wm_prog_key *const key;
 797    struct brw_wm_prog_data *prog_data;
 798    const struct gl_fragment_program *fp;
 799
 800    unsigned dispatch_width; /** 8 or 16 */
 801
 802    bool dual_source_output;
 803
 804    exec_list discard_halt_patches;
 805 };
 806
 807 bool brw_do_channel_expressions(struct exec_list *instructions);
 808 bool brw_do_vector_splitting(struct exec_list *instructions);
 809 bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);
 810
 811 struct brw_reg brw_reg_from_fs_reg(fs_reg *reg);