src/mesa/drivers/dri/i965/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29
  30 #include "brw_shader.h"
  31
  32 extern "C" {
  33
  34 #include <sys/types.h>
  35
  36 #include "main/macros.h"
  37 #include "main/shaderobj.h"
  38 #include "main/uniforms.h"
  39 #include "program/prog_parameter.h"
  40 #include "program/prog_print.h"
  41 #include "program/prog_optimize.h"
  42 #include "util/register_allocate.h"
  43 #include "program/sampler.h"
  44 #include "program/hash_table.h"
  45 #include "brw_context.h"
  46 #include "brw_eu.h"
  47 #include "brw_wm.h"
  48 #include "brw_shader.h"
  49 #include "intel_asm_annotation.h"
  50 }
  51 #include "glsl/glsl_types.h"
  52 #include "glsl/ir.h"
  53
  54 #define MAX_SAMPLER_MESSAGE_SIZE 11
  55 #define MAX_VGRF_SIZE 16
  56
  57 struct bblock_t;
  58 namespace {
  59    struct acp_entry;
  60 }
  61
  62 namespace brw {
  63    class fs_live_variables;
  64 }
  65
  66 class fs_inst;
  67 class fs_visitor;
  68
  69 class fs_reg : public backend_reg {
  70 public:
  71    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  72
  73    void init();
  74
  75    fs_reg();
  76    explicit fs_reg(float f);
  77    explicit fs_reg(int32_t i);
  78    explicit fs_reg(uint32_t u);
  79    fs_reg(struct brw_reg fixed_hw_reg);
  80    fs_reg(enum register_file file, int reg);
  81    fs_reg(enum register_file file, int reg, enum brw_reg_type type);
  82    fs_reg(enum register_file file, int reg, enum brw_reg_type type, uint8_t width);
  83    fs_reg(fs_visitor *v, const struct glsl_type *type);
  84
  85    bool equals(const fs_reg &r) const;
  86    bool is_valid_3src() const;
  87    bool is_contiguous() const;
  88
  89    fs_reg &apply_stride(unsigned stride);
  90    /** Smear a channel of the reg to all channels. */
  91    fs_reg &set_smear(unsigned subreg);
  92
  93    /**
  94     * Offset in bytes from the start of the register.  Values up to a
  95     * backend_reg::reg_offset unit are valid.
  96     */
  97    int subreg_offset;
  98
  99    fs_reg *reladdr;
 100
 101    /**
 102     * The register width.  This indicates how many hardware values are
 103     * represented by each virtual value.  Valid values are 1, 8, or 16.
 104     * For immediate values, this is 1.  Most of the rest of the time, it
 105     * will be equal to the dispatch width.
 106     */
 107    uint8_t width;
 108
 109    /**
 110     * Returns the effective register width when used as a source in the
 111     * given instruction.  Registers such as uniforms and immediates
 112     * effectively take on the width of the instruction in which they are
 113     * used.
 114     */
 115    uint8_t effective_width;
 116
 117    /** Register region horizontal stride */
 118    uint8_t stride;
 119 };
 120
 121 static inline fs_reg
 122 retype(fs_reg reg, enum brw_reg_type type)
 123 {
 124    reg.fixed_hw_reg.type = reg.type = type;
 125    return reg;
 126 }
 127
 128 static inline fs_reg
 129 byte_offset(fs_reg reg, unsigned delta)
 130 {
 131    switch (reg.file) {
 132    case BAD_FILE:
 133       break;
 134    case GRF:
 135       reg.reg_offset += delta / 32;
 136       break;
 137    case MRF:
 138       reg.reg += delta / 32;
 139       break;
 140    default:
 141       assert(delta == 0);
 142    }
 143    reg.subreg_offset += delta % 32;
 144    return reg;
 145 }
 146
 147 static inline fs_reg
 148 horiz_offset(fs_reg reg, unsigned delta)
 149 {
 150    switch (reg.file) {
 151    case BAD_FILE:
 152    case UNIFORM:
 153    case IMM:
 154       /* These only have a single component that is implicitly splatted.  A
 155        * horizontal offset should be a harmless no-op.
 156        */
 157       break;
 158    case GRF:
 159    case MRF:
 160       return byte_offset(reg, delta * reg.stride * type_sz(reg.type));
 161    default:
 162       assert(delta == 0);
 163    }
 164    return reg;
 165 }
 166
 167 static inline fs_reg
 168 offset(fs_reg reg, unsigned delta)
 169 {
 170    assert(reg.stride > 0);
 171    switch (reg.file) {
 172    case BAD_FILE:
 173       break;
 174    case GRF:
 175    case MRF:
 176       return byte_offset(reg, delta * reg.width * reg.stride * type_sz(reg.type));
 177    case UNIFORM:
 178       reg.reg_offset += delta;
 179       break;
 180    default:
 181       assert(delta == 0);
 182    }
 183    return reg;
 184 }
 185
 186 static inline fs_reg
 187 component(fs_reg reg, unsigned idx)
 188 {
 189    assert(reg.subreg_offset == 0);
 190    assert(idx < reg.width);
 191    reg.subreg_offset = idx * type_sz(reg.type);
 192    reg.width = 1;
 193    return reg;
 194 }
 195
 196 /**
 197  * Get either of the 8-component halves of a 16-component register.
 198  *
 199  * Note: this also works if \c reg represents a SIMD16 pair of registers.
 200  */
 201 static inline fs_reg
 202 half(fs_reg reg, unsigned idx)
 203 {
 204    assert(idx < 2);
 205    assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM));
 206    assert(reg.width == 16);
 207    reg.width = 8;
 208    return horiz_offset(reg, 8 * idx);
 209 }
 210
 211 static const fs_reg reg_undef;
 212
 213 class ip_record : public exec_node {
 214 public:
 215    DECLARE_RALLOC_CXX_OPERATORS(ip_record)
 216
 217    ip_record(int ip)
 218    {
 219       this->ip = ip;
 220    }
 221
 222    int ip;
 223 };
 224
 225 class fs_inst : public backend_instruction {
 226    fs_inst &operator=(const fs_inst &);
 227
 228    void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
 229              fs_reg *src, int sources);
 230
 231 public:
 232    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 233
 234    fs_inst();
 235    fs_inst(enum opcode opcode, uint8_t exec_size);
 236    fs_inst(enum opcode opcode, const fs_reg &dst);
 237    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 238            const fs_reg &src0);
 239    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 240    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 241            const fs_reg &src0, const fs_reg &src1);
 242    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 243            const fs_reg &src1);
 244    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 245            const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 246    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 247            const fs_reg &src1, const fs_reg &src2);
 248    fs_inst(enum opcode opcode, const fs_reg &dst, fs_reg src[], int sources);
 249    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 250            fs_reg src[], int sources);
 251    fs_inst(const fs_inst &that);
 252
 253    void resize_sources(uint8_t num_sources);
 254
 255    bool equals(fs_inst *inst) const;
 256    bool overwrites_reg(const fs_reg &reg) const;
 257    bool is_send_from_grf() const;
 258    bool is_partial_write() const;
 259    int regs_read(fs_visitor *v, int arg) const;
 260    bool can_do_source_mods(struct brw_context *brw);
 261
 262    bool reads_flag() const;
 263    bool writes_flag() const;
 264
 265    fs_reg dst;
 266    fs_reg *src;
 267
 268    uint8_t sources; /**< Number of fs_reg sources. */
 269
 270    /**
 271     * Execution size of the instruction.  This is used by the generator to
 272     * generate the correct binary for the given fs_inst.  Current valid
 273     * values are 1, 8, 16.
 274     */
 275    uint8_t exec_size;
 276
 277    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 278     * mod and predication.
 279     */
 280    uint8_t flag_subreg;
 281
 282    uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
 283    bool eot:1;
 284    bool header_present:1;
 285    bool shadow_compare:1;
 286    bool force_uncompressed:1;
 287    bool force_sechalf:1;
 288    bool pi_noperspective:1;   /**< Pixel interpolator noperspective flag */
 289 };
 290
 291 /**
 292  * The fragment shader front-end.
 293  *
 294  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
 295  */
 296 class fs_visitor : public backend_visitor
 297 {
 298 public:
 299    const fs_reg reg_null_f;
 300    const fs_reg reg_null_d;
 301    const fs_reg reg_null_ud;
 302
 303    fs_visitor(struct brw_context *brw,
 304               void *mem_ctx,
 305               const struct brw_wm_prog_key *key,
 306               struct brw_wm_prog_data *prog_data,
 307               struct gl_shader_program *shader_prog,
 308               struct gl_fragment_program *fp,
 309               unsigned dispatch_width);
 310    ~fs_visitor();
 311    void init();
 312
 313    fs_reg *variable_storage(ir_variable *var);
 314    int virtual_grf_alloc(int size);
 315    void import_uniforms(fs_visitor *v);
 316
 317    void visit(ir_variable *ir);
 318    void visit(ir_assignment *ir);
 319    void visit(ir_dereference_variable *ir);
 320    void visit(ir_dereference_record *ir);
 321    void visit(ir_dereference_array *ir);
 322    void visit(ir_expression *ir);
 323    void visit(ir_texture *ir);
 324    void visit(ir_if *ir);
 325    void visit(ir_constant *ir);
 326    void visit(ir_swizzle *ir);
 327    void visit(ir_return *ir);
 328    void visit(ir_loop *ir);
 329    void visit(ir_loop_jump *ir);
 330    void visit(ir_discard *ir);
 331    void visit(ir_call *ir);
 332    void visit(ir_function *ir);
 333    void visit(ir_function_signature *ir);
 334    void visit(ir_emit_vertex *);
 335    void visit(ir_end_primitive *);
 336
 337    uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
 338    void swizzle_result(ir_texture *ir, fs_reg orig_val, uint32_t sampler);
 339
 340    fs_inst *emit(fs_inst *inst);
 341    void emit(exec_list list);
 342
 343    fs_inst *emit(enum opcode opcode);
 344    fs_inst *emit(enum opcode opcode, const fs_reg &dst);
 345    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 346    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 347                  const fs_reg &src1);
 348    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 349                  const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 350    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 351                  fs_reg src[], int sources);
 352
 353    fs_inst *MOV(const fs_reg &dst, const fs_reg &src);
 354    fs_inst *NOT(const fs_reg &dst, const fs_reg &src);
 355    fs_inst *RNDD(const fs_reg &dst, const fs_reg &src);
 356    fs_inst *RNDE(const fs_reg &dst, const fs_reg &src);
 357    fs_inst *RNDZ(const fs_reg &dst, const fs_reg &src);
 358    fs_inst *FRC(const fs_reg &dst, const fs_reg &src);
 359    fs_inst *ADD(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 360    fs_inst *MUL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 361    fs_inst *MACH(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 362    fs_inst *MAC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 363    fs_inst *SHL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 364    fs_inst *SHR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 365    fs_inst *ASR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 366    fs_inst *AND(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 367    fs_inst *OR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 368    fs_inst *XOR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 369    fs_inst *IF(enum brw_predicate predicate);
 370    fs_inst *IF(const fs_reg &src0, const fs_reg &src1,
 371                enum brw_conditional_mod condition);
 372    fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
 373                 enum brw_conditional_mod condition);
 374    fs_inst *LRP(const fs_reg &dst, const fs_reg &a, const fs_reg &y,
 375                 const fs_reg &x);
 376    fs_inst *DEP_RESOLVE_MOV(int grf);
 377    fs_inst *BFREV(const fs_reg &dst, const fs_reg &value);
 378    fs_inst *BFE(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset,
 379                 const fs_reg &value);
 380    fs_inst *BFI1(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset);
 381    fs_inst *BFI2(const fs_reg &dst, const fs_reg &bfi1_dst,
 382                  const fs_reg &insert, const fs_reg &base);
 383    fs_inst *FBH(const fs_reg &dst, const fs_reg &value);
 384    fs_inst *FBL(const fs_reg &dst, const fs_reg &value);
 385    fs_inst *CBIT(const fs_reg &dst, const fs_reg &value);
 386    fs_inst *MAD(const fs_reg &dst, const fs_reg &c, const fs_reg &b,
 387                 const fs_reg &a);
 388    fs_inst *ADDC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 389    fs_inst *SUBB(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 390    fs_inst *SEL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 391
 392    int type_size(const struct glsl_type *type);
 393    fs_inst *get_instruction_generating_reg(fs_inst *start,
 394                                            fs_inst *end,
 395                                            const fs_reg &reg);
 396
 397    fs_inst *LOAD_PAYLOAD(const fs_reg &dst, fs_reg *src, int sources);
 398
 399    exec_list VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
 400                                         const fs_reg &surf_index,
 401                                         const fs_reg &varying_offset,
 402                                         uint32_t const_offset);
 403
 404    bool run();
 405    void assign_binding_table_offsets();
 406    void setup_payload_gen4();
 407    void setup_payload_gen6();
 408    void assign_curb_setup();
 409    void calculate_urb_setup();
 410    void assign_urb_setup();
 411    bool assign_regs(bool allow_spilling);
 412    void assign_regs_trivial();
 413    void get_used_mrfs(bool *mrf_used);
 414    void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
 415                                    int first_payload_node);
 416    void setup_mrf_hack_interference(struct ra_graph *g,
 417                                     int first_mrf_hack_node);
 418    int choose_spill_reg(struct ra_graph *g);
 419    void spill_reg(int spill_reg);
 420    void split_virtual_grfs();
 421    bool compact_virtual_grfs();
 422    void move_uniform_array_access_to_pull_constants();
 423    void assign_constant_locations();
 424    void demote_pull_constants();
 425    void invalidate_live_intervals();
 426    void calculate_live_intervals();
 427    void calculate_register_pressure();
 428    bool opt_algebraic();
 429    bool opt_cse();
 430    bool opt_cse_local(bblock_t *block);
 431    bool opt_copy_propagate();
 432    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 433    bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
 434    bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
 435                                  exec_list *acp);
 436    void opt_drop_redundant_mov_to_flags();
 437    bool opt_register_renaming();
 438    bool register_coalesce();
 439    bool compute_to_mrf();
 440    bool dead_code_eliminate();
 441    bool remove_duplicate_mrf_writes();
 442    bool virtual_grf_interferes(int a, int b);
 443    void schedule_instructions(instruction_scheduler_mode mode);
 444    void insert_gen4_send_dependency_workarounds();
 445    void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
 446                                                     fs_inst *inst);
 447    void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
 448                                                      fs_inst *inst);
 449    void vfail(const char *msg, va_list args);
 450    void fail(const char *msg, ...);
 451    void no16(const char *msg, ...);
 452    void lower_uniform_pull_constant_loads();
 453    bool lower_load_payload();
 454
 455    void push_force_uncompressed();
 456    void pop_force_uncompressed();
 457
 458    void emit_dummy_fs();
 459    void emit_repclear_shader();
 460    fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
 461    fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
 462                          glsl_interp_qualifier interpolation_mode,
 463                          bool is_centroid, bool is_sample);
 464    fs_reg *emit_frontfacing_interpolation();
 465    fs_reg *emit_samplepos_setup();
 466    fs_reg *emit_sampleid_setup(ir_variable *ir);
 467    fs_reg *emit_general_interpolation(ir_variable *ir);
 468    void emit_interpolation_setup_gen4();
 469    void emit_interpolation_setup_gen6();
 470    void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
 471    fs_reg rescale_texcoord(ir_texture *ir, fs_reg coordinate,
 472                            bool is_rect, uint32_t sampler, int texunit);
 473    fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 474                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 475                               uint32_t sampler);
 476    fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 477                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 478                               fs_reg sample_index, uint32_t sampler);
 479    fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 480                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 481                               fs_reg sample_index, fs_reg mcs, fs_reg sampler,
 482                               fs_reg offset_value);
 483    fs_reg emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, fs_reg sampler);
 484    void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
 485    fs_reg fix_math_operand(fs_reg src);
 486    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
 487    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
 488    void emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
 489                  const fs_reg &a);
 490    void emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &dst,
 491                     const fs_reg &src0, const fs_reg &src1);
 492    bool try_emit_saturate(ir_expression *ir);
 493    bool try_emit_mad(ir_expression *ir);
 494    void try_replace_with_sel();
 495    bool opt_peephole_sel();
 496    bool opt_peephole_predicated_break();
 497    bool opt_saturate_propagation();
 498    void emit_bool_to_cond_code(ir_rvalue *condition);
 499    void emit_if_gen6(ir_if *ir);
 500    void emit_unspill(bblock_t *block, fs_inst *inst, fs_reg reg,
 501                      uint32_t spill_offset, int count);
 502    void emit_spill(bblock_t *block, fs_inst *inst, fs_reg reg,
 503                    uint32_t spill_offset, int count);
 504
 505    void emit_fragment_program_code();
 506    void setup_fp_regs();
 507    fs_reg get_fp_src_reg(const prog_src_register *src);
 508    fs_reg get_fp_dst_reg(const prog_dst_register *dst);
 509    void emit_fp_alu1(enum opcode opcode,
 510                      const struct prog_instruction *fpi,
 511                      fs_reg dst, fs_reg src);
 512    void emit_fp_alu2(enum opcode opcode,
 513                      const struct prog_instruction *fpi,
 514                      fs_reg dst, fs_reg src0, fs_reg src1);
 515    void emit_fp_scalar_write(const struct prog_instruction *fpi,
 516                              fs_reg dst, fs_reg src);
 517    void emit_fp_scalar_math(enum opcode opcode,
 518                             const struct prog_instruction *fpi,
 519                             fs_reg dst, fs_reg src);
 520
 521    void emit_fp_minmax(const struct prog_instruction *fpi,
 522                        fs_reg dst, fs_reg src0, fs_reg src1);
 523
 524    void emit_fp_sop(enum brw_conditional_mod conditional_mod,
 525                     const struct prog_instruction *fpi,
 526                     fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
 527
 528    int setup_color_payload(fs_reg *dst, fs_reg color, unsigned components);
 529    void emit_alpha_test();
 530    fs_inst *emit_single_fb_write(fs_reg color1, fs_reg color2,
 531                                  fs_reg src0_alpha, unsigned components);
 532    void emit_fb_writes();
 533
 534    void emit_shader_time_begin();
 535    void emit_shader_time_end();
 536    void emit_shader_time_write(enum shader_time_shader_type type,
 537                                fs_reg value);
 538
 539    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 540                             fs_reg dst, fs_reg offset, fs_reg src0,
 541                             fs_reg src1);
 542
 543    void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
 544                                   fs_reg offset);
 545
 546    void emit_interpolate_expression(ir_expression *ir);
 547
 548    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 549                                fs_reg dst,
 550                                fs_reg src,
 551                                fs_inst *pre_rhs_inst,
 552                                fs_inst *last_rhs_inst);
 553    void emit_assignment_writes(fs_reg &l, fs_reg &r,
 554                                const glsl_type *type, bool predicated);
 555    void resolve_ud_negate(fs_reg *reg);
 556    void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
 557
 558    fs_reg get_timestamp();
 559
 560    struct brw_reg interp_reg(int location, int channel);
 561    void setup_uniform_values(ir_variable *ir);
 562    void setup_builtin_uniform_values(ir_variable *ir);
 563    int implied_mrf_writes(fs_inst *inst);
 564
 565    virtual void dump_instructions();
 566    virtual void dump_instructions(const char *name);
 567    void dump_instruction(backend_instruction *inst);
 568    void dump_instruction(backend_instruction *inst, FILE *file);
 569
 570    void visit_atomic_counter_intrinsic(ir_call *ir);
 571
 572    const void *const key;
 573    struct brw_stage_prog_data *prog_data;
 574    unsigned int sanity_param_count;
 575
 576    int *param_size;
 577
 578    int *virtual_grf_sizes;
 579    int virtual_grf_count;
 580    int virtual_grf_array_size;
 581    int *virtual_grf_start;
 582    int *virtual_grf_end;
 583    brw::fs_live_variables *live_intervals;
 584
 585    int *regs_live_at_ip;
 586
 587    /** Number of uniform variable components visited. */
 588    unsigned uniforms;
 589
 590    /** Byte-offset for the next available spot in the scratch space buffer. */
 591    unsigned last_scratch;
 592
 593    /**
 594     * Array mapping UNIFORM register numbers to the pull parameter index,
 595     * or -1 if this uniform register isn't being uploaded as a pull constant.
 596     */
 597    int *pull_constant_loc;
 598
 599    /**
 600     * Array mapping UNIFORM register numbers to the push parameter index,
 601     * or -1 if this uniform register isn't being uploaded as a push constant.
 602     */
 603    int *push_constant_loc;
 604
 605    struct hash_table *variable_ht;
 606    fs_reg frag_depth;
 607    fs_reg sample_mask;
 608    fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
 609    unsigned output_components[BRW_MAX_DRAW_BUFFERS];
 610    fs_reg dual_src_output;
 611    bool do_dual_src;
 612    int first_non_payload_grf;
 613    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 614    int max_grf;
 615
 616    fs_reg *fp_temp_regs;
 617    fs_reg *fp_input_regs;
 618
 619    /** @{ debug annotation info */
 620    const char *current_annotation;
 621    const void *base_ir;
 622    /** @} */
 623
 624    bool failed;
 625    char *fail_msg;
 626    bool simd16_unsupported;
 627    char *no16_msg;
 628
 629    /* Result of last visit() method. */
 630    fs_reg result;
 631
 632    /** Register numbers for thread payload fields. */
 633    struct {
 634       uint8_t source_depth_reg;
 635       uint8_t source_w_reg;
 636       uint8_t aa_dest_stencil_reg;
 637       uint8_t dest_depth_reg;
 638       uint8_t sample_pos_reg;
 639       uint8_t sample_mask_in_reg;
 640       uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 641
 642       /** The number of thread payload registers the hardware will supply. */
 643       uint8_t num_regs;
 644    } payload;
 645
 646    bool source_depth_to_render_target;
 647    bool runtime_check_aads_emit;
 648
 649    fs_reg pixel_x;
 650    fs_reg pixel_y;
 651    fs_reg wpos_w;
 652    fs_reg pixel_w;
 653    fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 654    fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 655    fs_reg shader_start_time;
 656
 657    int grf_used;
 658    bool spilled_any_registers;
 659
 660    const unsigned dispatch_width; /**< 8 or 16 */
 661
 662    int force_uncompressed_stack;
 663 };
 664
 665 /**
 666  * The fragment shader code generator.
 667  *
 668  * Translates FS IR to actual i965 assembly code.
 669  */
 670 class fs_generator
 671 {
 672 public:
 673    fs_generator(struct brw_context *brw,
 674                 void *mem_ctx,
 675                 const struct brw_wm_prog_key *key,
 676                 struct brw_wm_prog_data *prog_data,
 677                 struct gl_shader_program *shader_prog,
 678                 struct gl_fragment_program *fp,
 679                 bool runtime_check_aads_emit,
 680                 bool debug_flag);
 681    ~fs_generator();
 682
 683    const unsigned *generate_assembly(const cfg_t *simd8_cfg,
 684                                      const cfg_t *simd16_cfg,
 685                                      unsigned *assembly_size);
 686
 687 private:
 688    void generate_code(const cfg_t *cfg);
 689    void fire_fb_write(fs_inst *inst,
 690                       struct brw_reg payload,
 691                       struct brw_reg implied_header,
 692                       GLuint nr);
 693    void generate_fb_write(fs_inst *inst, struct brw_reg payload);
 694    void generate_blorp_fb_write(fs_inst *inst);
 695    void generate_pixel_xy(struct brw_reg dst, bool is_x);
 696    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 697                          struct brw_reg *src);
 698    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 699                      struct brw_reg sampler_index);
 700    void generate_math_gen6(fs_inst *inst,
 701                            struct brw_reg dst,
 702                            struct brw_reg src0,
 703                            struct brw_reg src1);
 704    void generate_math_gen4(fs_inst *inst,
 705                            struct brw_reg dst,
 706                            struct brw_reg src);
 707    void generate_math_g45(fs_inst *inst,
 708                           struct brw_reg dst,
 709                           struct brw_reg src);
 710    void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src, struct brw_reg quality);
 711    void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 712                      struct brw_reg quality, bool negate_value);
 713    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 714    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 715    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 716    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 717                                             struct brw_reg index,
 718                                             struct brw_reg offset);
 719    void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
 720                                                  struct brw_reg dst,
 721                                                  struct brw_reg surf_index,
 722                                                  struct brw_reg offset);
 723    void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 724                                             struct brw_reg index,
 725                                             struct brw_reg offset);
 726    void generate_varying_pull_constant_load_gen7(fs_inst *inst,
 727                                                  struct brw_reg dst,
 728                                                  struct brw_reg index,
 729                                                  struct brw_reg offset);
 730    void generate_mov_dispatch_to_flags(fs_inst *inst);
 731
 732    void generate_pixel_interpolator_query(fs_inst *inst,
 733                                           struct brw_reg dst,
 734                                           struct brw_reg src,
 735                                           struct brw_reg msg_data,
 736                                           unsigned msg_type);
 737
 738    void generate_set_omask(fs_inst *inst,
 739                            struct brw_reg dst,
 740                            struct brw_reg sample_mask);
 741
 742    void generate_set_sample_id(fs_inst *inst,
 743                                struct brw_reg dst,
 744                                struct brw_reg src0,
 745                                struct brw_reg src1);
 746
 747    void generate_set_simd4x2_offset(fs_inst *inst,
 748                                     struct brw_reg dst,
 749                                     struct brw_reg offset);
 750    void generate_discard_jump(fs_inst *inst);
 751
 752    void generate_pack_half_2x16_split(fs_inst *inst,
 753                                       struct brw_reg dst,
 754                                       struct brw_reg x,
 755                                       struct brw_reg y);
 756    void generate_unpack_half_2x16_split(fs_inst *inst,
 757                                         struct brw_reg dst,
 758                                         struct brw_reg src);
 759
 760    void generate_shader_time_add(fs_inst *inst,
 761                                  struct brw_reg payload,
 762                                  struct brw_reg offset,
 763                                  struct brw_reg value);
 764
 765    void generate_untyped_atomic(fs_inst *inst,
 766                                 struct brw_reg dst,
 767                                 struct brw_reg payload,
 768                                 struct brw_reg atomic_op,
 769                                 struct brw_reg surf_index);
 770
 771    void generate_untyped_surface_read(fs_inst *inst,
 772                                       struct brw_reg dst,
 773                                       struct brw_reg payload,
 774                                       struct brw_reg surf_index);
 775
 776    bool patch_discard_jumps_to_fb_writes();
 777
 778    struct brw_context *brw;
 779    struct gl_context *ctx;
 780
 781    struct brw_compile *p;
 782    gl_shader_stage stage;
 783    const void * const key;
 784    struct brw_stage_prog_data * const prog_data;
 785
 786    struct gl_shader_program * const shader_prog;
 787    const struct gl_program *prog;
 788
 789    unsigned dispatch_width; /**< 8 or 16 */
 790
 791    exec_list discard_halt_patches;
 792    bool runtime_check_aads_emit;
 793    const bool debug_flag;
 794    void *mem_ctx;
 795 };
 796
 797 bool brw_do_channel_expressions(struct exec_list *instructions);
 798 bool brw_do_vector_splitting(struct exec_list *instructions);
 799 bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);
 800
 801 struct brw_reg brw_reg_from_fs_reg(fs_reg *reg);