src/mesa/drivers/dri/i965/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29
  30 #include "brw_shader.h"
  31
  32 extern "C" {
  33
  34 #include <sys/types.h>
  35
  36 #include "main/macros.h"
  37 #include "main/shaderobj.h"
  38 #include "main/uniforms.h"
  39 #include "program/prog_parameter.h"
  40 #include "program/prog_print.h"
  41 #include "program/prog_optimize.h"
  42 #include "util/register_allocate.h"
  43 #include "program/sampler.h"
  44 #include "program/hash_table.h"
  45 #include "brw_context.h"
  46 #include "brw_eu.h"
  47 #include "brw_wm.h"
  48 #include "brw_shader.h"
  49 #include "intel_asm_annotation.h"
  50 }
  51 #include "glsl/glsl_types.h"
  52 #include "glsl/ir.h"
  53
  54 #define MAX_SAMPLER_MESSAGE_SIZE 11
  55
  56 struct bblock_t;
  57 namespace {
  58    struct acp_entry;
  59 }
  60
  61 namespace brw {
  62    class fs_live_variables;
  63 }
  64
  65 class fs_visitor;
  66
  67 class fs_reg : public backend_reg {
  68 public:
  69    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  70
  71    void init();
  72
  73    fs_reg();
  74    explicit fs_reg(float f);
  75    explicit fs_reg(int32_t i);
  76    explicit fs_reg(uint32_t u);
  77    fs_reg(struct brw_reg fixed_hw_reg);
  78    fs_reg(enum register_file file, int reg);
  79    fs_reg(enum register_file file, int reg, enum brw_reg_type type);
  80    fs_reg(enum register_file file, int reg, enum brw_reg_type type, uint8_t width);
  81    fs_reg(fs_visitor *v, const struct glsl_type *type);
  82
  83    bool equals(const fs_reg &r) const;
  84    bool is_valid_3src() const;
  85    bool is_contiguous() const;
  86
  87    fs_reg &apply_stride(unsigned stride);
  88    /** Smear a channel of the reg to all channels. */
  89    fs_reg &set_smear(unsigned subreg);
  90
  91    /**
  92     * Offset in bytes from the start of the register.  Values up to a
  93     * backend_reg::reg_offset unit are valid.
  94     */
  95    int subreg_offset;
  96
  97    fs_reg *reladdr;
  98
  99    /**
 100     * The register width.  This indicates how many hardware values are
 101     * represented by each virtual value.  Valid values are 1, 8, or 16.
 102     * For immediate values, this is 1.  Most of the rest of the time, it
 103     * will be equal to the dispatch width.
 104     */
 105    uint8_t width;
 106
 107    /**
 108     * Returns the effective register width when used as a source in the
 109     * given instruction.  Registers such as uniforms and immediates
 110     * effectively take on the width of the instruction in which they are
 111     * used.
 112     */
 113    uint8_t effective_width(const fs_visitor *v) const;
 114
 115    /** Register region horizontal stride */
 116    uint8_t stride;
 117 };
 118
 119 static inline fs_reg
 120 retype(fs_reg reg, enum brw_reg_type type)
 121 {
 122    reg.fixed_hw_reg.type = reg.type = type;
 123    return reg;
 124 }
 125
 126 static inline fs_reg
 127 offset(fs_reg reg, unsigned delta)
 128 {
 129    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 130    reg.reg_offset += delta;
 131    return reg;
 132 }
 133
 134 static inline fs_reg
 135 byte_offset(fs_reg reg, unsigned delta)
 136 {
 137    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 138    reg.subreg_offset += delta;
 139    return reg;
 140 }
 141
 142 /**
 143  * Get either of the 8-component halves of a 16-component register.
 144  *
 145  * Note: this also works if \c reg represents a SIMD16 pair of registers.
 146  */
 147 static inline fs_reg
 148 half(const fs_reg &reg, unsigned idx)
 149 {
 150    assert(idx < 2);
 151    assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM));
 152    return byte_offset(reg, 8 * idx * reg.stride * type_sz(reg.type));
 153 }
 154
 155 static const fs_reg reg_undef;
 156
 157 class ip_record : public exec_node {
 158 public:
 159    DECLARE_RALLOC_CXX_OPERATORS(ip_record)
 160
 161    ip_record(int ip)
 162    {
 163       this->ip = ip;
 164    }
 165
 166    int ip;
 167 };
 168
 169 class fs_inst : public backend_instruction {
 170    fs_inst &operator=(const fs_inst &);
 171
 172 public:
 173    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 174
 175    void init(enum opcode opcode, const fs_reg &dst, fs_reg *src, int sources);
 176
 177    fs_inst(enum opcode opcode = BRW_OPCODE_NOP, const fs_reg &dst = reg_undef);
 178    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 179    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 180            const fs_reg &src1);
 181    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 182            const fs_reg &src1, const fs_reg &src2);
 183    fs_inst(enum opcode opcode, const fs_reg &dst, fs_reg src[], int sources);
 184    fs_inst(const fs_inst &that);
 185
 186    void resize_sources(uint8_t num_sources);
 187
 188    bool equals(fs_inst *inst) const;
 189    bool overwrites_reg(const fs_reg &reg) const;
 190    bool is_send_from_grf() const;
 191    bool is_partial_write() const;
 192    int regs_read(fs_visitor *v, int arg) const;
 193    bool can_do_source_mods(struct brw_context *brw);
 194
 195    bool reads_flag() const;
 196    bool writes_flag() const;
 197
 198    fs_reg dst;
 199    fs_reg *src;
 200
 201    uint8_t sources; /**< Number of fs_reg sources. */
 202
 203    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 204     * mod and predication.
 205     */
 206    uint8_t flag_subreg;
 207
 208    uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
 209    bool eot:1;
 210    bool header_present:1;
 211    bool shadow_compare:1;
 212    bool force_uncompressed:1;
 213    bool force_sechalf:1;
 214    bool pi_noperspective:1;   /**< Pixel interpolator noperspective flag */
 215 };
 216
 217 /**
 218  * The fragment shader front-end.
 219  *
 220  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
 221  */
 222 class fs_visitor : public backend_visitor
 223 {
 224 public:
 225    const fs_reg reg_null_f;
 226    const fs_reg reg_null_d;
 227    const fs_reg reg_null_ud;
 228
 229    fs_visitor(struct brw_context *brw,
 230               void *mem_ctx,
 231               const struct brw_wm_prog_key *key,
 232               struct brw_wm_prog_data *prog_data,
 233               struct gl_shader_program *shader_prog,
 234               struct gl_fragment_program *fp,
 235               unsigned dispatch_width);
 236    ~fs_visitor();
 237    void init();
 238
 239    fs_reg *variable_storage(ir_variable *var);
 240    int virtual_grf_alloc(int size);
 241    void import_uniforms(fs_visitor *v);
 242
 243    void visit(ir_variable *ir);
 244    void visit(ir_assignment *ir);
 245    void visit(ir_dereference_variable *ir);
 246    void visit(ir_dereference_record *ir);
 247    void visit(ir_dereference_array *ir);
 248    void visit(ir_expression *ir);
 249    void visit(ir_texture *ir);
 250    void visit(ir_if *ir);
 251    void visit(ir_constant *ir);
 252    void visit(ir_swizzle *ir);
 253    void visit(ir_return *ir);
 254    void visit(ir_loop *ir);
 255    void visit(ir_loop_jump *ir);
 256    void visit(ir_discard *ir);
 257    void visit(ir_call *ir);
 258    void visit(ir_function *ir);
 259    void visit(ir_function_signature *ir);
 260    void visit(ir_emit_vertex *);
 261    void visit(ir_end_primitive *);
 262
 263    uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
 264    void swizzle_result(ir_texture *ir, fs_reg orig_val, uint32_t sampler);
 265
 266    fs_inst *emit(fs_inst *inst);
 267    void emit(exec_list list);
 268
 269    fs_inst *emit(enum opcode opcode);
 270    fs_inst *emit(enum opcode opcode, const fs_reg &dst);
 271    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 272    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 273                  const fs_reg &src1);
 274    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 275                  const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 276    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 277                  fs_reg src[], int sources);
 278
 279    fs_inst *MOV(const fs_reg &dst, const fs_reg &src);
 280    fs_inst *NOT(const fs_reg &dst, const fs_reg &src);
 281    fs_inst *RNDD(const fs_reg &dst, const fs_reg &src);
 282    fs_inst *RNDE(const fs_reg &dst, const fs_reg &src);
 283    fs_inst *RNDZ(const fs_reg &dst, const fs_reg &src);
 284    fs_inst *FRC(const fs_reg &dst, const fs_reg &src);
 285    fs_inst *ADD(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 286    fs_inst *MUL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 287    fs_inst *MACH(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 288    fs_inst *MAC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 289    fs_inst *SHL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 290    fs_inst *SHR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 291    fs_inst *ASR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 292    fs_inst *AND(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 293    fs_inst *OR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 294    fs_inst *XOR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 295    fs_inst *IF(enum brw_predicate predicate);
 296    fs_inst *IF(const fs_reg &src0, const fs_reg &src1,
 297                enum brw_conditional_mod condition);
 298    fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
 299                 enum brw_conditional_mod condition);
 300    fs_inst *LRP(const fs_reg &dst, const fs_reg &a, const fs_reg &y,
 301                 const fs_reg &x);
 302    fs_inst *DEP_RESOLVE_MOV(int grf);
 303    fs_inst *BFREV(const fs_reg &dst, const fs_reg &value);
 304    fs_inst *BFE(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset,
 305                 const fs_reg &value);
 306    fs_inst *BFI1(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset);
 307    fs_inst *BFI2(const fs_reg &dst, const fs_reg &bfi1_dst,
 308                  const fs_reg &insert, const fs_reg &base);
 309    fs_inst *FBH(const fs_reg &dst, const fs_reg &value);
 310    fs_inst *FBL(const fs_reg &dst, const fs_reg &value);
 311    fs_inst *CBIT(const fs_reg &dst, const fs_reg &value);
 312    fs_inst *MAD(const fs_reg &dst, const fs_reg &c, const fs_reg &b,
 313                 const fs_reg &a);
 314    fs_inst *ADDC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 315    fs_inst *SUBB(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 316    fs_inst *SEL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 317
 318    int type_size(const struct glsl_type *type);
 319    fs_inst *get_instruction_generating_reg(fs_inst *start,
 320                                            fs_inst *end,
 321                                            const fs_reg &reg);
 322
 323    fs_inst *LOAD_PAYLOAD(const fs_reg &dst, fs_reg *src, int sources);
 324
 325    exec_list VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
 326                                         const fs_reg &surf_index,
 327                                         const fs_reg &varying_offset,
 328                                         uint32_t const_offset);
 329
 330    bool run();
 331    void assign_binding_table_offsets();
 332    void setup_payload_gen4();
 333    void setup_payload_gen6();
 334    void assign_curb_setup();
 335    void calculate_urb_setup();
 336    void assign_urb_setup();
 337    bool assign_regs(bool allow_spilling);
 338    void assign_regs_trivial();
 339    void get_used_mrfs(bool *mrf_used);
 340    void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
 341                                    int first_payload_node);
 342    void setup_mrf_hack_interference(struct ra_graph *g,
 343                                     int first_mrf_hack_node);
 344    int choose_spill_reg(struct ra_graph *g);
 345    void spill_reg(int spill_reg);
 346    void split_virtual_grfs();
 347    bool compact_virtual_grfs();
 348    void move_uniform_array_access_to_pull_constants();
 349    void assign_constant_locations();
 350    void demote_pull_constants();
 351    void invalidate_live_intervals();
 352    void calculate_live_intervals();
 353    void calculate_register_pressure();
 354    bool opt_algebraic();
 355    bool opt_cse();
 356    bool opt_cse_local(bblock_t *block);
 357    bool opt_copy_propagate();
 358    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 359    bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
 360    bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
 361                                  exec_list *acp);
 362    void opt_drop_redundant_mov_to_flags();
 363    bool opt_register_renaming();
 364    bool register_coalesce();
 365    bool compute_to_mrf();
 366    bool dead_code_eliminate();
 367    bool remove_duplicate_mrf_writes();
 368    bool virtual_grf_interferes(int a, int b);
 369    void schedule_instructions(instruction_scheduler_mode mode);
 370    void insert_gen4_send_dependency_workarounds();
 371    void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
 372                                                     fs_inst *inst);
 373    void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
 374                                                      fs_inst *inst);
 375    void vfail(const char *msg, va_list args);
 376    void fail(const char *msg, ...);
 377    void no16(const char *msg, ...);
 378    void lower_uniform_pull_constant_loads();
 379    bool lower_load_payload();
 380
 381    void push_force_uncompressed();
 382    void pop_force_uncompressed();
 383
 384    void emit_dummy_fs();
 385    void emit_repclear_shader();
 386    fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
 387    fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
 388                          glsl_interp_qualifier interpolation_mode,
 389                          bool is_centroid, bool is_sample);
 390    fs_reg *emit_frontfacing_interpolation();
 391    fs_reg *emit_samplepos_setup();
 392    fs_reg *emit_sampleid_setup(ir_variable *ir);
 393    fs_reg *emit_general_interpolation(ir_variable *ir);
 394    void emit_interpolation_setup_gen4();
 395    void emit_interpolation_setup_gen6();
 396    void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
 397    fs_reg rescale_texcoord(ir_texture *ir, fs_reg coordinate,
 398                            bool is_rect, uint32_t sampler, int texunit);
 399    fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 400                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 401                               uint32_t sampler);
 402    fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 403                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 404                               fs_reg sample_index, uint32_t sampler);
 405    fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 406                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 407                               fs_reg sample_index, fs_reg mcs, fs_reg sampler);
 408    fs_reg emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, fs_reg sampler);
 409    void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
 410    fs_reg fix_math_operand(fs_reg src);
 411    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
 412    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
 413    void emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
 414                  const fs_reg &a);
 415    void emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &dst,
 416                     const fs_reg &src0, const fs_reg &src1);
 417    bool try_emit_saturate(ir_expression *ir);
 418    bool try_emit_mad(ir_expression *ir);
 419    void try_replace_with_sel();
 420    bool opt_peephole_sel();
 421    bool opt_peephole_predicated_break();
 422    bool opt_saturate_propagation();
 423    void emit_bool_to_cond_code(ir_rvalue *condition);
 424    void emit_if_gen6(ir_if *ir);
 425    void emit_unspill(bblock_t *block, fs_inst *inst, fs_reg reg,
 426                      uint32_t spill_offset, int count);
 427
 428    void emit_fragment_program_code();
 429    void setup_fp_regs();
 430    fs_reg get_fp_src_reg(const prog_src_register *src);
 431    fs_reg get_fp_dst_reg(const prog_dst_register *dst);
 432    void emit_fp_alu1(enum opcode opcode,
 433                      const struct prog_instruction *fpi,
 434                      fs_reg dst, fs_reg src);
 435    void emit_fp_alu2(enum opcode opcode,
 436                      const struct prog_instruction *fpi,
 437                      fs_reg dst, fs_reg src0, fs_reg src1);
 438    void emit_fp_scalar_write(const struct prog_instruction *fpi,
 439                              fs_reg dst, fs_reg src);
 440    void emit_fp_scalar_math(enum opcode opcode,
 441                             const struct prog_instruction *fpi,
 442                             fs_reg dst, fs_reg src);
 443
 444    void emit_fp_minmax(const struct prog_instruction *fpi,
 445                        fs_reg dst, fs_reg src0, fs_reg src1);
 446
 447    void emit_fp_sop(enum brw_conditional_mod conditional_mod,
 448                     const struct prog_instruction *fpi,
 449                     fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
 450
 451    void emit_color_write(fs_reg color, int index, int first_color_mrf);
 452    void emit_alpha_test();
 453    fs_inst *emit_single_fb_write(fs_reg color1, fs_reg color2,
 454                                  fs_reg src0_alpha, unsigned components);
 455    void emit_fb_writes();
 456
 457    void emit_shader_time_begin();
 458    void emit_shader_time_end();
 459    void emit_shader_time_write(enum shader_time_shader_type type,
 460                                fs_reg value);
 461
 462    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 463                             fs_reg dst, fs_reg offset, fs_reg src0,
 464                             fs_reg src1);
 465
 466    void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
 467                                   fs_reg offset);
 468
 469    void emit_interpolate_expression(ir_expression *ir);
 470
 471    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 472                                fs_reg dst,
 473                                fs_reg src,
 474                                fs_inst *pre_rhs_inst,
 475                                fs_inst *last_rhs_inst);
 476    void emit_assignment_writes(fs_reg &l, fs_reg &r,
 477                                const glsl_type *type, bool predicated);
 478    void resolve_ud_negate(fs_reg *reg);
 479    void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
 480
 481    fs_reg get_timestamp();
 482
 483    struct brw_reg interp_reg(int location, int channel);
 484    void setup_uniform_values(ir_variable *ir);
 485    void setup_builtin_uniform_values(ir_variable *ir);
 486    int implied_mrf_writes(fs_inst *inst);
 487
 488    virtual void dump_instructions();
 489    virtual void dump_instructions(const char *name);
 490    void dump_instruction(backend_instruction *inst);
 491    void dump_instruction(backend_instruction *inst, FILE *file);
 492
 493    void visit_atomic_counter_intrinsic(ir_call *ir);
 494
 495    const void *const key;
 496    struct brw_stage_prog_data *prog_data;
 497    unsigned int sanity_param_count;
 498
 499    int *param_size;
 500
 501    int *virtual_grf_sizes;
 502    int virtual_grf_count;
 503    int virtual_grf_array_size;
 504    int *virtual_grf_start;
 505    int *virtual_grf_end;
 506    brw::fs_live_variables *live_intervals;
 507
 508    int *regs_live_at_ip;
 509
 510    /** Number of uniform variable components visited. */
 511    unsigned uniforms;
 512
 513    /** Byte-offset for the next available spot in the scratch space buffer. */
 514    unsigned last_scratch;
 515
 516    /**
 517     * Array mapping UNIFORM register numbers to the pull parameter index,
 518     * or -1 if this uniform register isn't being uploaded as a pull constant.
 519     */
 520    int *pull_constant_loc;
 521
 522    /**
 523     * Array mapping UNIFORM register numbers to the push parameter index,
 524     * or -1 if this uniform register isn't being uploaded as a push constant.
 525     */
 526    int *push_constant_loc;
 527
 528    struct hash_table *variable_ht;
 529    fs_reg frag_depth;
 530    fs_reg sample_mask;
 531    fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
 532    unsigned output_components[BRW_MAX_DRAW_BUFFERS];
 533    fs_reg dual_src_output;
 534    bool do_dual_src;
 535    int first_non_payload_grf;
 536    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 537    int max_grf;
 538
 539    fs_reg *fp_temp_regs;
 540    fs_reg *fp_input_regs;
 541
 542    /** @{ debug annotation info */
 543    const char *current_annotation;
 544    const void *base_ir;
 545    /** @} */
 546
 547    bool failed;
 548    char *fail_msg;
 549    bool simd16_unsupported;
 550    char *no16_msg;
 551
 552    /* Result of last visit() method. */
 553    fs_reg result;
 554
 555    /** Register numbers for thread payload fields. */
 556    struct {
 557       uint8_t source_depth_reg;
 558       uint8_t source_w_reg;
 559       uint8_t aa_dest_stencil_reg;
 560       uint8_t dest_depth_reg;
 561       uint8_t sample_pos_reg;
 562       uint8_t sample_mask_in_reg;
 563       uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 564
 565       /** The number of thread payload registers the hardware will supply. */
 566       uint8_t num_regs;
 567    } payload;
 568
 569    bool source_depth_to_render_target;
 570    bool runtime_check_aads_emit;
 571
 572    fs_reg pixel_x;
 573    fs_reg pixel_y;
 574    fs_reg wpos_w;
 575    fs_reg pixel_w;
 576    fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 577    fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 578    fs_reg shader_start_time;
 579
 580    int grf_used;
 581    bool spilled_any_registers;
 582
 583    const unsigned dispatch_width; /**< 8 or 16 */
 584
 585    int force_uncompressed_stack;
 586 };
 587
 588 /**
 589  * The fragment shader code generator.
 590  *
 591  * Translates FS IR to actual i965 assembly code.
 592  */
 593 class fs_generator
 594 {
 595 public:
 596    fs_generator(struct brw_context *brw,
 597                 void *mem_ctx,
 598                 const struct brw_wm_prog_key *key,
 599                 struct brw_wm_prog_data *prog_data,
 600                 struct gl_shader_program *shader_prog,
 601                 struct gl_fragment_program *fp,
 602                 bool runtime_check_aads_emit,
 603                 bool debug_flag);
 604    ~fs_generator();
 605
 606    const unsigned *generate_assembly(const cfg_t *simd8_cfg,
 607                                      const cfg_t *simd16_cfg,
 608                                      unsigned *assembly_size);
 609
 610 private:
 611    void generate_code(const cfg_t *cfg);
 612    void fire_fb_write(fs_inst *inst,
 613                       GLuint base_reg,
 614                       struct brw_reg implied_header,
 615                       GLuint nr);
 616    void generate_fb_write(fs_inst *inst);
 617    void generate_blorp_fb_write(fs_inst *inst);
 618    void generate_rep_fb_write(fs_inst *inst);
 619    void generate_pixel_xy(struct brw_reg dst, bool is_x);
 620    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 621                          struct brw_reg *src);
 622    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 623                      struct brw_reg sampler_index);
 624    void generate_math_gen6(fs_inst *inst,
 625                            struct brw_reg dst,
 626                            struct brw_reg src0,
 627                            struct brw_reg src1);
 628    void generate_math_gen4(fs_inst *inst,
 629                            struct brw_reg dst,
 630                            struct brw_reg src);
 631    void generate_math_g45(fs_inst *inst,
 632                           struct brw_reg dst,
 633                           struct brw_reg src);
 634    void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src, struct brw_reg quality);
 635    void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 636                      struct brw_reg quality, bool negate_value);
 637    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 638    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 639    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 640    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 641                                             struct brw_reg index,
 642                                             struct brw_reg offset);
 643    void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
 644                                                  struct brw_reg dst,
 645                                                  struct brw_reg surf_index,
 646                                                  struct brw_reg offset);
 647    void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 648                                             struct brw_reg index,
 649                                             struct brw_reg offset);
 650    void generate_varying_pull_constant_load_gen7(fs_inst *inst,
 651                                                  struct brw_reg dst,
 652                                                  struct brw_reg index,
 653                                                  struct brw_reg offset);
 654    void generate_mov_dispatch_to_flags(fs_inst *inst);
 655
 656    void generate_pixel_interpolator_query(fs_inst *inst,
 657                                           struct brw_reg dst,
 658                                           struct brw_reg src,
 659                                           struct brw_reg msg_data,
 660                                           unsigned msg_type);
 661
 662    void generate_set_omask(fs_inst *inst,
 663                            struct brw_reg dst,
 664                            struct brw_reg sample_mask);
 665
 666    void generate_set_sample_id(fs_inst *inst,
 667                                struct brw_reg dst,
 668                                struct brw_reg src0,
 669                                struct brw_reg src1);
 670
 671    void generate_set_simd4x2_offset(fs_inst *inst,
 672                                     struct brw_reg dst,
 673                                     struct brw_reg offset);
 674    void generate_discard_jump(fs_inst *inst);
 675
 676    void generate_pack_half_2x16_split(fs_inst *inst,
 677                                       struct brw_reg dst,
 678                                       struct brw_reg x,
 679                                       struct brw_reg y);
 680    void generate_unpack_half_2x16_split(fs_inst *inst,
 681                                         struct brw_reg dst,
 682                                         struct brw_reg src);
 683
 684    void generate_shader_time_add(fs_inst *inst,
 685                                  struct brw_reg payload,
 686                                  struct brw_reg offset,
 687                                  struct brw_reg value);
 688
 689    void generate_untyped_atomic(fs_inst *inst,
 690                                 struct brw_reg dst,
 691                                 struct brw_reg atomic_op,
 692                                 struct brw_reg surf_index);
 693
 694    void generate_untyped_surface_read(fs_inst *inst,
 695                                       struct brw_reg dst,
 696                                       struct brw_reg surf_index);
 697
 698    bool patch_discard_jumps_to_fb_writes();
 699
 700    struct brw_context *brw;
 701    struct gl_context *ctx;
 702
 703    struct brw_compile *p;
 704    gl_shader_stage stage;
 705    const void * const key;
 706    struct brw_stage_prog_data * const prog_data;
 707
 708    struct gl_shader_program * const shader_prog;
 709    const struct gl_program *prog;
 710
 711    unsigned dispatch_width; /**< 8 or 16 */
 712
 713    exec_list discard_halt_patches;
 714    bool runtime_check_aads_emit;
 715    const bool debug_flag;
 716    void *mem_ctx;
 717 };
 718
 719 bool brw_do_channel_expressions(struct exec_list *instructions);
 720 bool brw_do_vector_splitting(struct exec_list *instructions);
 721 bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);
 722
 723 struct brw_reg brw_reg_from_fs_reg(fs_reg *reg);