i965/fs: Try to avoid generating extra MOVs to do saturates.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs.h
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #include "brw_shader.h"
29
30 extern "C" {
31
32 #include <sys/types.h>
33
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
44 #include "brw_eu.h"
45 #include "brw_wm.h"
46 }
47 #include "glsl/glsl_types.h"
48 #include "glsl/ir.h"
49
50 enum register_file {
51 BAD_FILE,
52 ARF,
53 GRF,
54 MRF,
55 IMM,
56 FIXED_HW_REG, /* a struct brw_reg */
57 UNIFORM, /* prog_data->params[reg] */
58 };
59
60 class fs_reg {
61 public:
62 /* Callers of this ralloc-based new need not call delete. It's
63 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
64 static void* operator new(size_t size, void *ctx)
65 {
66 void *node;
67
68 node = ralloc_size(ctx, size);
69 assert(node != NULL);
70
71 return node;
72 }
73
74 void init()
75 {
76 memset(this, 0, sizeof(*this));
77 this->smear = -1;
78 }
79
80 /** Generic unset register constructor. */
81 fs_reg()
82 {
83 init();
84 this->file = BAD_FILE;
85 }
86
87 /** Immediate value constructor. */
88 fs_reg(float f)
89 {
90 init();
91 this->file = IMM;
92 this->type = BRW_REGISTER_TYPE_F;
93 this->imm.f = f;
94 }
95
96 /** Immediate value constructor. */
97 fs_reg(int32_t i)
98 {
99 init();
100 this->file = IMM;
101 this->type = BRW_REGISTER_TYPE_D;
102 this->imm.i = i;
103 }
104
105 /** Immediate value constructor. */
106 fs_reg(uint32_t u)
107 {
108 init();
109 this->file = IMM;
110 this->type = BRW_REGISTER_TYPE_UD;
111 this->imm.u = u;
112 }
113
114 /** Fixed brw_reg Immediate value constructor. */
115 fs_reg(struct brw_reg fixed_hw_reg)
116 {
117 init();
118 this->file = FIXED_HW_REG;
119 this->fixed_hw_reg = fixed_hw_reg;
120 this->type = fixed_hw_reg.type;
121 }
122
123 fs_reg(enum register_file file, int reg);
124 fs_reg(enum register_file file, int reg, uint32_t type);
125 fs_reg(class fs_visitor *v, const struct glsl_type *type);
126
127 bool equals(fs_reg *r)
128 {
129 return (file == r->file &&
130 reg == r->reg &&
131 reg_offset == r->reg_offset &&
132 type == r->type &&
133 negate == r->negate &&
134 abs == r->abs &&
135 memcmp(&fixed_hw_reg, &r->fixed_hw_reg,
136 sizeof(fixed_hw_reg)) == 0 &&
137 smear == r->smear &&
138 imm.u == r->imm.u);
139 }
140
141 /** Register file: ARF, GRF, MRF, IMM. */
142 enum register_file file;
143 /**
144 * Register number. For ARF/MRF, it's the hardware register. For
145 * GRF, it's a virtual register number until register allocation
146 */
147 int reg;
148 /**
149 * For virtual registers, this is a hardware register offset from
150 * the start of the register block (for example, a constant index
151 * in an array access).
152 */
153 int reg_offset;
154 /** Register type. BRW_REGISTER_TYPE_* */
155 int type;
156 bool negate;
157 bool abs;
158 bool sechalf;
159 struct brw_reg fixed_hw_reg;
160 int smear; /* -1, or a channel of the reg to smear to all channels. */
161
162 /** Value for file == IMM */
163 union {
164 int32_t i;
165 uint32_t u;
166 float f;
167 } imm;
168 };
169
170 static const fs_reg reg_undef;
171 static const fs_reg reg_null_f(ARF, BRW_ARF_NULL, BRW_REGISTER_TYPE_F);
172 static const fs_reg reg_null_d(ARF, BRW_ARF_NULL, BRW_REGISTER_TYPE_D);
173
174 class ip_record : public exec_node {
175 public:
176 static void* operator new(size_t size, void *ctx)
177 {
178 void *node;
179
180 node = rzalloc_size(ctx, size);
181 assert(node != NULL);
182
183 return node;
184 }
185
186 ip_record(int ip)
187 {
188 this->ip = ip;
189 }
190
191 int ip;
192 };
193
194 class fs_inst : public exec_node {
195 public:
196 /* Callers of this ralloc-based new need not call delete. It's
197 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
198 static void* operator new(size_t size, void *ctx)
199 {
200 void *node;
201
202 node = rzalloc_size(ctx, size);
203 assert(node != NULL);
204
205 return node;
206 }
207
208 void init()
209 {
210 memset(this, 0, sizeof(*this));
211 this->opcode = BRW_OPCODE_NOP;
212 this->conditional_mod = BRW_CONDITIONAL_NONE;
213
214 this->dst = reg_undef;
215 this->src[0] = reg_undef;
216 this->src[1] = reg_undef;
217 this->src[2] = reg_undef;
218 }
219
220 fs_inst()
221 {
222 init();
223 }
224
225 fs_inst(enum opcode opcode)
226 {
227 init();
228 this->opcode = opcode;
229 }
230
231 fs_inst(enum opcode opcode, fs_reg dst)
232 {
233 init();
234 this->opcode = opcode;
235 this->dst = dst;
236
237 if (dst.file == GRF)
238 assert(dst.reg_offset >= 0);
239 }
240
241 fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0)
242 {
243 init();
244 this->opcode = opcode;
245 this->dst = dst;
246 this->src[0] = src0;
247
248 if (dst.file == GRF)
249 assert(dst.reg_offset >= 0);
250 if (src[0].file == GRF)
251 assert(src[0].reg_offset >= 0);
252 }
253
254 fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
255 {
256 init();
257 this->opcode = opcode;
258 this->dst = dst;
259 this->src[0] = src0;
260 this->src[1] = src1;
261
262 if (dst.file == GRF)
263 assert(dst.reg_offset >= 0);
264 if (src[0].file == GRF)
265 assert(src[0].reg_offset >= 0);
266 if (src[1].file == GRF)
267 assert(src[1].reg_offset >= 0);
268 }
269
270 fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2)
271 {
272 init();
273 this->opcode = opcode;
274 this->dst = dst;
275 this->src[0] = src0;
276 this->src[1] = src1;
277 this->src[2] = src2;
278
279 if (dst.file == GRF)
280 assert(dst.reg_offset >= 0);
281 if (src[0].file == GRF)
282 assert(src[0].reg_offset >= 0);
283 if (src[1].file == GRF)
284 assert(src[1].reg_offset >= 0);
285 if (src[2].file == GRF)
286 assert(src[2].reg_offset >= 0);
287 }
288
289 bool equals(fs_inst *inst)
290 {
291 return (opcode == inst->opcode &&
292 dst.equals(&inst->dst) &&
293 src[0].equals(&inst->src[0]) &&
294 src[1].equals(&inst->src[1]) &&
295 src[2].equals(&inst->src[2]) &&
296 saturate == inst->saturate &&
297 predicated == inst->predicated &&
298 conditional_mod == inst->conditional_mod &&
299 mlen == inst->mlen &&
300 base_mrf == inst->base_mrf &&
301 sampler == inst->sampler &&
302 target == inst->target &&
303 eot == inst->eot &&
304 header_present == inst->header_present &&
305 shadow_compare == inst->shadow_compare &&
306 offset == inst->offset);
307 }
308
309 int regs_written()
310 {
311 if (is_tex())
312 return 4;
313
314 /* The SINCOS and INT_DIV_QUOTIENT_AND_REMAINDER math functions return 2,
315 * but we don't currently use them...nor do we have an opcode for them.
316 */
317
318 return 1;
319 }
320
321 bool is_tex()
322 {
323 return (opcode == SHADER_OPCODE_TEX ||
324 opcode == FS_OPCODE_TXB ||
325 opcode == SHADER_OPCODE_TXD ||
326 opcode == SHADER_OPCODE_TXF ||
327 opcode == SHADER_OPCODE_TXL ||
328 opcode == SHADER_OPCODE_TXS);
329 }
330
331 bool is_math()
332 {
333 return (opcode == SHADER_OPCODE_RCP ||
334 opcode == SHADER_OPCODE_RSQ ||
335 opcode == SHADER_OPCODE_SQRT ||
336 opcode == SHADER_OPCODE_EXP2 ||
337 opcode == SHADER_OPCODE_LOG2 ||
338 opcode == SHADER_OPCODE_SIN ||
339 opcode == SHADER_OPCODE_COS ||
340 opcode == SHADER_OPCODE_INT_QUOTIENT ||
341 opcode == SHADER_OPCODE_INT_REMAINDER ||
342 opcode == SHADER_OPCODE_POW);
343 }
344
345 enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
346 fs_reg dst;
347 fs_reg src[3];
348 bool saturate;
349 bool predicated;
350 bool predicate_inverse;
351 int conditional_mod; /**< BRW_CONDITIONAL_* */
352
353 int mlen; /**< SEND message length */
354 int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
355 int sampler;
356 int target; /**< MRT target. */
357 bool eot;
358 bool header_present;
359 bool shadow_compare;
360 bool force_uncompressed;
361 bool force_sechalf;
362 uint32_t offset; /* spill/unspill offset */
363
364 /** @{
365 * Annotation for the generated IR. One of the two can be set.
366 */
367 ir_instruction *ir;
368 const char *annotation;
369 /** @} */
370 };
371
372 class fs_visitor : public ir_visitor
373 {
374 public:
375
376 fs_visitor(struct brw_wm_compile *c, struct gl_shader_program *prog,
377 struct brw_shader *shader)
378 {
379 this->c = c;
380 this->p = &c->func;
381 this->brw = p->brw;
382 this->fp = (struct gl_fragment_program *)
383 prog->_LinkedShaders[MESA_SHADER_FRAGMENT]->Program;
384 this->prog = prog;
385 this->intel = &brw->intel;
386 this->ctx = &intel->ctx;
387 this->mem_ctx = ralloc_context(NULL);
388 this->shader = shader;
389 this->failed = false;
390 this->variable_ht = hash_table_ctor(0,
391 hash_table_pointer_hash,
392 hash_table_pointer_compare);
393
394 /* There's a question that appears to be left open in the spec:
395 * How do implicit dst conversions interact with the CMP
396 * instruction or conditional mods? On gen6, the instruction:
397 *
398 * CMP null<d> src0<f> src1<f>
399 *
400 * will do src1 - src0 and compare that result as if it was an
401 * integer. On gen4, it will do src1 - src0 as float, convert
402 * the result to int, and compare as int. In between, it
403 * appears that it does src1 - src0 and does the compare in the
404 * execution type so dst type doesn't matter.
405 */
406 if (this->intel->gen > 4)
407 this->reg_null_cmp = reg_null_d;
408 else
409 this->reg_null_cmp = reg_null_f;
410
411 this->frag_depth = NULL;
412 memset(this->outputs, 0, sizeof(this->outputs));
413 this->first_non_payload_grf = 0;
414 this->max_grf = intel->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
415
416 this->current_annotation = NULL;
417 this->base_ir = NULL;
418
419 this->virtual_grf_sizes = NULL;
420 this->virtual_grf_next = 0;
421 this->virtual_grf_array_size = 0;
422 this->virtual_grf_def = NULL;
423 this->virtual_grf_use = NULL;
424 this->live_intervals_valid = false;
425
426 this->kill_emitted = false;
427 this->force_uncompressed_stack = 0;
428 this->force_sechalf_stack = 0;
429 }
430
431 ~fs_visitor()
432 {
433 ralloc_free(this->mem_ctx);
434 hash_table_dtor(this->variable_ht);
435 }
436
437 fs_reg *variable_storage(ir_variable *var);
438 int virtual_grf_alloc(int size);
439 void import_uniforms(fs_visitor *v);
440
441 void visit(ir_variable *ir);
442 void visit(ir_assignment *ir);
443 void visit(ir_dereference_variable *ir);
444 void visit(ir_dereference_record *ir);
445 void visit(ir_dereference_array *ir);
446 void visit(ir_expression *ir);
447 void visit(ir_texture *ir);
448 void visit(ir_if *ir);
449 void visit(ir_constant *ir);
450 void visit(ir_swizzle *ir);
451 void visit(ir_return *ir);
452 void visit(ir_loop *ir);
453 void visit(ir_loop_jump *ir);
454 void visit(ir_discard *ir);
455 void visit(ir_call *ir);
456 void visit(ir_function *ir);
457 void visit(ir_function_signature *ir);
458
459 void swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler);
460
461 fs_inst *emit(fs_inst inst);
462
463 fs_inst *emit(enum opcode opcode)
464 {
465 return emit(fs_inst(opcode));
466 }
467
468 fs_inst *emit(enum opcode opcode, fs_reg dst)
469 {
470 return emit(fs_inst(opcode, dst));
471 }
472
473 fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0)
474 {
475 return emit(fs_inst(opcode, dst, src0));
476 }
477
478 fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
479 {
480 return emit(fs_inst(opcode, dst, src0, src1));
481 }
482
483 fs_inst *emit(enum opcode opcode, fs_reg dst,
484 fs_reg src0, fs_reg src1, fs_reg src2)
485 {
486 return emit(fs_inst(opcode, dst, src0, src1, src2));
487 }
488
489 int type_size(const struct glsl_type *type);
490 fs_inst *get_instruction_generating_reg(fs_inst *start,
491 fs_inst *end,
492 fs_reg reg);
493
494 bool run();
495 void setup_paramvalues_refs();
496 void assign_curb_setup();
497 void calculate_urb_setup();
498 void assign_urb_setup();
499 bool assign_regs();
500 void assign_regs_trivial();
501 int choose_spill_reg(struct ra_graph *g);
502 void spill_reg(int spill_reg);
503 void split_virtual_grfs();
504 void setup_pull_constants();
505 void calculate_live_intervals();
506 bool propagate_constants();
507 bool opt_algebraic();
508 bool register_coalesce();
509 bool compute_to_mrf();
510 bool dead_code_eliminate();
511 bool remove_dead_constants();
512 bool remove_duplicate_mrf_writes();
513 bool virtual_grf_interferes(int a, int b);
514 void schedule_instructions();
515 void patch_discard_jumps_to_fb_writes();
516 void fail(const char *msg, ...);
517
518 void push_force_uncompressed();
519 void pop_force_uncompressed();
520 void push_force_sechalf();
521 void pop_force_sechalf();
522
523 void generate_code();
524 void generate_fb_write(fs_inst *inst);
525 void generate_pixel_xy(struct brw_reg dst, bool is_x);
526 void generate_linterp(fs_inst *inst, struct brw_reg dst,
527 struct brw_reg *src);
528 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
529 void generate_math1_gen7(fs_inst *inst,
530 struct brw_reg dst,
531 struct brw_reg src);
532 void generate_math2_gen7(fs_inst *inst,
533 struct brw_reg dst,
534 struct brw_reg src0,
535 struct brw_reg src1);
536 void generate_math1_gen6(fs_inst *inst,
537 struct brw_reg dst,
538 struct brw_reg src);
539 void generate_math2_gen6(fs_inst *inst,
540 struct brw_reg dst,
541 struct brw_reg src0,
542 struct brw_reg src1);
543 void generate_math_gen4(fs_inst *inst,
544 struct brw_reg dst,
545 struct brw_reg src);
546 void generate_discard(fs_inst *inst);
547 void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
548 void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
549 void generate_spill(fs_inst *inst, struct brw_reg src);
550 void generate_unspill(fs_inst *inst, struct brw_reg dst);
551 void generate_pull_constant_load(fs_inst *inst, struct brw_reg dst);
552
553 void emit_dummy_fs();
554 fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
555 fs_reg *emit_frontfacing_interpolation(ir_variable *ir);
556 fs_reg *emit_general_interpolation(ir_variable *ir);
557 void emit_interpolation_setup_gen4();
558 void emit_interpolation_setup_gen6();
559 fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
560 int sampler);
561 fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
562 int sampler);
563 fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
564 int sampler);
565 fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
566 fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
567 bool try_emit_saturate(ir_expression *ir);
568 bool try_emit_mad(ir_expression *ir, int mul_arg);
569 void emit_bool_to_cond_code(ir_rvalue *condition);
570 void emit_if_gen6(ir_if *ir);
571 void emit_unspill(fs_inst *inst, fs_reg reg, uint32_t spill_offset);
572
573 void emit_color_write(int target, int index, int first_color_mrf);
574 void emit_fb_writes();
575 bool try_rewrite_rhs_to_dst(ir_assignment *ir,
576 fs_reg dst,
577 fs_reg src,
578 fs_inst *pre_rhs_inst,
579 fs_inst *last_rhs_inst);
580 void emit_assignment_writes(fs_reg &l, fs_reg &r,
581 const glsl_type *type, bool predicated);
582 void resolve_ud_negate(fs_reg *reg);
583
584 struct brw_reg interp_reg(int location, int channel);
585 int setup_uniform_values(int loc, const glsl_type *type);
586 void setup_builtin_uniform_values(ir_variable *ir);
587 int implied_mrf_writes(fs_inst *inst);
588
589 struct brw_context *brw;
590 const struct gl_fragment_program *fp;
591 struct intel_context *intel;
592 struct gl_context *ctx;
593 struct brw_wm_compile *c;
594 struct brw_compile *p;
595 struct brw_shader *shader;
596 struct gl_shader_program *prog;
597 void *mem_ctx;
598 exec_list instructions;
599 exec_list discard_halt_patches;
600
601 /* Delayed setup of c->prog_data.params[] due to realloc of
602 * ParamValues[] during compile.
603 */
604 int param_index[MAX_UNIFORMS * 4];
605 int param_offset[MAX_UNIFORMS * 4];
606
607 int *virtual_grf_sizes;
608 int virtual_grf_next;
609 int virtual_grf_array_size;
610 int *virtual_grf_def;
611 int *virtual_grf_use;
612 bool live_intervals_valid;
613
614 /* This is the map from UNIFORM hw_reg + reg_offset as generated by
615 * the visitor to the packed uniform number after
616 * remove_dead_constants() that represents the actual uploaded
617 * uniform index.
618 */
619 int *params_remap;
620
621 struct hash_table *variable_ht;
622 ir_variable *frag_depth;
623 fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
624 int first_non_payload_grf;
625 int max_grf;
626 int urb_setup[FRAG_ATTRIB_MAX];
627 bool kill_emitted;
628
629 /** @{ debug annotation info */
630 const char *current_annotation;
631 ir_instruction *base_ir;
632 /** @} */
633
634 bool failed;
635 char *fail_msg;
636
637 /* Result of last visit() method. */
638 fs_reg result;
639
640 fs_reg pixel_x;
641 fs_reg pixel_y;
642 fs_reg wpos_w;
643 fs_reg pixel_w;
644 fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
645 fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
646 fs_reg reg_null_cmp;
647
648 int grf_used;
649
650 int force_uncompressed_stack;
651 int force_sechalf_stack;
652 };
653
654 bool brw_do_channel_expressions(struct exec_list *instructions);
655 bool brw_do_vector_splitting(struct exec_list *instructions);
656 bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);