2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include "brw_shader.h"
34 #include <sys/types.h>
36 #include "main/macros.h"
37 #include "main/shaderobj.h"
38 #include "main/uniforms.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/prog_optimize.h"
42 #include "program/register_allocate.h"
43 #include "program/sampler.h"
44 #include "program/hash_table.h"
45 #include "brw_context.h"
48 #include "brw_shader.h"
50 #include "gen8_generator.h"
51 #include "glsl/glsl_types.h"
54 #define MAX_SAMPLER_MESSAGE_SIZE 11
62 class fs_live_variables
;
67 DECLARE_RALLOC_CXX_OPERATORS(fs_reg
)
75 fs_reg(struct brw_reg fixed_hw_reg
);
76 fs_reg(enum register_file file
, int reg
);
77 fs_reg(enum register_file file
, int reg
, uint32_t type
);
78 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
80 bool equals(const fs_reg
&r
) const;
84 bool is_valid_3src() const;
85 fs_reg
retype(uint32_t type
);
87 /** Register file: GRF, MRF, IMM. */
88 enum register_file file
;
90 * Register number. For MRF, it's the hardware register. For
91 * GRF, it's a virtual register number until register allocation
95 * Offset from the start of the contiguous register block.
97 * For pre-register-allocation GRFs, this is in units of a float per pixel
98 * (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
99 * For uniforms, this is in units of 1 float.
102 /** Register type. BRW_REGISTER_TYPE_* */
107 struct brw_reg fixed_hw_reg
;
108 int smear
; /* -1, or a channel of the reg to smear to all channels. */
110 /** Value for file == IMM */
120 static const fs_reg reg_undef
;
121 static const fs_reg
reg_null_f(retype(brw_null_reg(), BRW_REGISTER_TYPE_F
));
122 static const fs_reg
reg_null_d(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
123 static const fs_reg
reg_null_ud(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
125 class ip_record
: public exec_node
{
127 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
137 class fs_inst
: public backend_instruction
{
139 DECLARE_RALLOC_CXX_OPERATORS(fs_inst
)
144 fs_inst(enum opcode opcode
);
145 fs_inst(enum opcode opcode
, fs_reg dst
);
146 fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
);
147 fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
);
148 fs_inst(enum opcode opcode
, fs_reg dst
,
149 fs_reg src0
, fs_reg src1
,fs_reg src2
);
151 bool equals(fs_inst
*inst
);
152 bool overwrites_reg(const fs_reg
®
);
153 bool is_send_from_grf();
154 bool is_partial_write();
155 int regs_read(fs_visitor
*v
, int arg
);
163 int conditional_mod
; /**< BRW_CONDITIONAL_* */
165 /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
166 * mod and predication.
170 int mlen
; /**< SEND message length */
171 int regs_written
; /**< Number of vgrfs written by a SEND message, or 1 */
172 int base_mrf
; /**< First MRF in the SEND message, if mlen is nonzero. */
173 uint32_t texture_offset
; /**< Texture offset bitfield */
175 int target
; /**< MRT target. */
179 bool force_uncompressed
;
181 bool force_writemask_all
;
182 uint32_t offset
; /* spill/unspill offset */
185 * Annotation for the generated IR. One of the two can be set.
188 const char *annotation
;
193 * The fragment shader front-end.
195 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
197 class fs_visitor
: public backend_visitor
201 fs_visitor(struct brw_context
*brw
,
202 struct brw_wm_compile
*c
,
203 struct gl_shader_program
*shader_prog
,
204 struct gl_fragment_program
*fp
,
205 unsigned dispatch_width
);
208 fs_reg
*variable_storage(ir_variable
*var
);
209 int virtual_grf_alloc(int size
);
210 void import_uniforms(fs_visitor
*v
);
212 void visit(ir_variable
*ir
);
213 void visit(ir_assignment
*ir
);
214 void visit(ir_dereference_variable
*ir
);
215 void visit(ir_dereference_record
*ir
);
216 void visit(ir_dereference_array
*ir
);
217 void visit(ir_expression
*ir
);
218 void visit(ir_texture
*ir
);
219 void visit(ir_if
*ir
);
220 void visit(ir_constant
*ir
);
221 void visit(ir_swizzle
*ir
);
222 void visit(ir_return
*ir
);
223 void visit(ir_loop
*ir
);
224 void visit(ir_loop_jump
*ir
);
225 void visit(ir_discard
*ir
);
226 void visit(ir_call
*ir
);
227 void visit(ir_function
*ir
);
228 void visit(ir_function_signature
*ir
);
229 void visit(ir_emit_vertex
*);
230 void visit(ir_end_primitive
*);
232 uint32_t gather_channel(ir_texture
*ir
, int sampler
);
233 void swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
);
235 bool can_do_source_mods(fs_inst
*inst
);
237 fs_inst
*emit(fs_inst inst
);
238 fs_inst
*emit(fs_inst
*inst
);
239 void emit(exec_list list
);
241 fs_inst
*emit(enum opcode opcode
);
242 fs_inst
*emit(enum opcode opcode
, fs_reg dst
);
243 fs_inst
*emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
);
244 fs_inst
*emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
);
245 fs_inst
*emit(enum opcode opcode
, fs_reg dst
,
246 fs_reg src0
, fs_reg src1
, fs_reg src2
);
248 fs_inst
*MOV(fs_reg dst
, fs_reg src
);
249 fs_inst
*NOT(fs_reg dst
, fs_reg src
);
250 fs_inst
*RNDD(fs_reg dst
, fs_reg src
);
251 fs_inst
*RNDE(fs_reg dst
, fs_reg src
);
252 fs_inst
*RNDZ(fs_reg dst
, fs_reg src
);
253 fs_inst
*FRC(fs_reg dst
, fs_reg src
);
254 fs_inst
*ADD(fs_reg dst
, fs_reg src0
, fs_reg src1
);
255 fs_inst
*MUL(fs_reg dst
, fs_reg src0
, fs_reg src1
);
256 fs_inst
*MACH(fs_reg dst
, fs_reg src0
, fs_reg src1
);
257 fs_inst
*MAC(fs_reg dst
, fs_reg src0
, fs_reg src1
);
258 fs_inst
*SHL(fs_reg dst
, fs_reg src0
, fs_reg src1
);
259 fs_inst
*SHR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
260 fs_inst
*ASR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
261 fs_inst
*AND(fs_reg dst
, fs_reg src0
, fs_reg src1
);
262 fs_inst
*OR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
263 fs_inst
*XOR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
264 fs_inst
*IF(uint32_t predicate
);
265 fs_inst
*IF(fs_reg src0
, fs_reg src1
, uint32_t condition
);
266 fs_inst
*CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
,
268 fs_inst
*LRP(fs_reg dst
, fs_reg a
, fs_reg y
, fs_reg x
);
269 fs_inst
*DEP_RESOLVE_MOV(int grf
);
270 fs_inst
*BFREV(fs_reg dst
, fs_reg value
);
271 fs_inst
*BFE(fs_reg dst
, fs_reg bits
, fs_reg offset
, fs_reg value
);
272 fs_inst
*BFI1(fs_reg dst
, fs_reg bits
, fs_reg offset
);
273 fs_inst
*BFI2(fs_reg dst
, fs_reg bfi1_dst
, fs_reg insert
, fs_reg base
);
274 fs_inst
*FBH(fs_reg dst
, fs_reg value
);
275 fs_inst
*FBL(fs_reg dst
, fs_reg value
);
276 fs_inst
*CBIT(fs_reg dst
, fs_reg value
);
277 fs_inst
*MAD(fs_reg dst
, fs_reg c
, fs_reg b
, fs_reg a
);
278 fs_inst
*ADDC(fs_reg dst
, fs_reg src0
, fs_reg src1
);
279 fs_inst
*SUBB(fs_reg dst
, fs_reg src0
, fs_reg src1
);
280 fs_inst
*SEL(fs_reg dst
, fs_reg src0
, fs_reg src1
);
282 int type_size(const struct glsl_type
*type
);
283 fs_inst
*get_instruction_generating_reg(fs_inst
*start
,
287 exec_list
VARYING_PULL_CONSTANT_LOAD(fs_reg dst
, fs_reg surf_index
,
288 fs_reg varying_offset
,
289 uint32_t const_offset
);
292 void assign_binding_table_offsets();
293 void setup_payload_gen4();
294 void setup_payload_gen6();
295 void assign_curb_setup();
296 void calculate_urb_setup();
297 void assign_urb_setup();
298 bool assign_regs(bool allow_spilling
);
299 void assign_regs_trivial();
300 void get_used_mrfs(bool *mrf_used
);
301 void setup_payload_interference(struct ra_graph
*g
, int payload_reg_count
,
302 int first_payload_node
);
303 void setup_mrf_hack_interference(struct ra_graph
*g
,
304 int first_mrf_hack_node
);
305 int choose_spill_reg(struct ra_graph
*g
);
306 void spill_reg(int spill_reg
);
307 void split_virtual_grfs();
308 void compact_virtual_grfs();
309 void move_uniform_array_access_to_pull_constants();
310 void setup_pull_constants();
311 void invalidate_live_intervals();
312 void calculate_live_intervals();
313 void calculate_register_pressure();
314 bool opt_algebraic();
316 bool opt_cse_local(bblock_t
*block
, exec_list
*aeb
);
317 bool opt_copy_propagate();
318 bool try_copy_propagate(fs_inst
*inst
, int arg
, acp_entry
*entry
);
319 bool try_constant_propagate(fs_inst
*inst
, acp_entry
*entry
);
320 bool opt_copy_propagate_local(void *mem_ctx
, bblock_t
*block
,
322 bool register_coalesce();
323 bool compute_to_mrf();
324 bool dead_code_eliminate();
325 bool dead_code_eliminate_local();
326 bool remove_dead_constants();
327 bool remove_duplicate_mrf_writes();
328 bool virtual_grf_interferes(int a
, int b
);
329 void schedule_instructions(instruction_scheduler_mode mode
);
330 void insert_gen4_send_dependency_workarounds();
331 void insert_gen4_pre_send_dependency_workarounds(fs_inst
*inst
);
332 void insert_gen4_post_send_dependency_workarounds(fs_inst
*inst
);
333 void fail(const char *msg
, ...);
334 void lower_uniform_pull_constant_loads();
336 void push_force_uncompressed();
337 void pop_force_uncompressed();
339 void emit_dummy_fs();
340 fs_reg
*emit_fragcoord_interpolation(ir_variable
*ir
);
341 fs_inst
*emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
342 glsl_interp_qualifier interpolation_mode
,
344 fs_reg
*emit_frontfacing_interpolation(ir_variable
*ir
);
345 fs_reg
*emit_samplepos_setup(ir_variable
*ir
);
346 fs_reg
*emit_sampleid_setup(ir_variable
*ir
);
347 fs_reg
*emit_samplemaskin_setup(ir_variable
*ir
);
348 fs_reg
*emit_general_interpolation(ir_variable
*ir
);
349 void emit_interpolation_setup_gen4();
350 void emit_interpolation_setup_gen6();
351 void compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
);
352 fs_reg
rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
353 bool is_rect
, int sampler
, int texunit
);
354 fs_inst
*emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
355 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
);
356 fs_inst
*emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
357 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
,
358 fs_reg sample_index
);
359 fs_inst
*emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
360 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
,
361 fs_reg sample_index
, fs_reg mcs
);
362 fs_reg
emit_mcs_fetch(ir_texture
*ir
, fs_reg coordinate
, int sampler
);
363 fs_reg
fix_math_operand(fs_reg src
);
364 fs_inst
*emit_math(enum opcode op
, fs_reg dst
, fs_reg src0
);
365 fs_inst
*emit_math(enum opcode op
, fs_reg dst
, fs_reg src0
, fs_reg src1
);
366 void emit_lrp(fs_reg dst
, fs_reg x
, fs_reg y
, fs_reg a
);
367 void emit_minmax(uint32_t conditionalmod
, fs_reg dst
,
368 fs_reg src0
, fs_reg src1
);
369 bool try_emit_saturate(ir_expression
*ir
);
370 bool try_emit_mad(ir_expression
*ir
, int mul_arg
);
371 void try_replace_with_sel();
372 bool opt_peephole_sel();
373 bool opt_peephole_predicated_break();
374 void emit_bool_to_cond_code(ir_rvalue
*condition
);
375 void emit_if_gen6(ir_if
*ir
);
376 void emit_unspill(fs_inst
*inst
, fs_reg reg
, uint32_t spill_offset
,
379 void emit_fragment_program_code();
380 void setup_fp_regs();
381 fs_reg
get_fp_src_reg(const prog_src_register
*src
);
382 fs_reg
get_fp_dst_reg(const prog_dst_register
*dst
);
383 void emit_fp_alu1(enum opcode opcode
,
384 const struct prog_instruction
*fpi
,
385 fs_reg dst
, fs_reg src
);
386 void emit_fp_alu2(enum opcode opcode
,
387 const struct prog_instruction
*fpi
,
388 fs_reg dst
, fs_reg src0
, fs_reg src1
);
389 void emit_fp_scalar_write(const struct prog_instruction
*fpi
,
390 fs_reg dst
, fs_reg src
);
391 void emit_fp_scalar_math(enum opcode opcode
,
392 const struct prog_instruction
*fpi
,
393 fs_reg dst
, fs_reg src
);
395 void emit_fp_minmax(const struct prog_instruction
*fpi
,
396 fs_reg dst
, fs_reg src0
, fs_reg src1
);
398 void emit_fp_sop(uint32_t conditional_mod
,
399 const struct prog_instruction
*fpi
,
400 fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg one
);
402 void emit_color_write(int target
, int index
, int first_color_mrf
);
403 void emit_alpha_test();
404 void emit_fb_writes();
406 void emit_shader_time_begin();
407 void emit_shader_time_end();
408 void emit_shader_time_write(enum shader_time_shader_type type
,
411 void emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
412 fs_reg dst
, fs_reg offset
, fs_reg src0
,
415 void emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
418 bool try_rewrite_rhs_to_dst(ir_assignment
*ir
,
421 fs_inst
*pre_rhs_inst
,
422 fs_inst
*last_rhs_inst
);
423 void emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
424 const glsl_type
*type
, bool predicated
);
425 void resolve_ud_negate(fs_reg
*reg
);
426 void resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
);
428 fs_reg
get_timestamp();
430 struct brw_reg
interp_reg(int location
, int channel
);
431 void setup_uniform_values(ir_variable
*ir
);
432 void setup_builtin_uniform_values(ir_variable
*ir
);
433 int implied_mrf_writes(fs_inst
*inst
);
435 void dump_instruction(backend_instruction
*inst
);
437 void visit_atomic_counter_intrinsic(ir_call
*ir
);
439 struct gl_fragment_program
*fp
;
440 struct brw_wm_compile
*c
;
441 unsigned int sanity_param_count
;
443 int param_size
[MAX_UNIFORMS
* 4];
445 int *virtual_grf_sizes
;
446 int virtual_grf_count
;
447 int virtual_grf_array_size
;
448 int *virtual_grf_start
;
449 int *virtual_grf_end
;
450 brw::fs_live_variables
*live_intervals
;
452 int *regs_live_at_ip
;
454 /* This is the map from UNIFORM hw_reg + reg_offset as generated by
455 * the visitor to the packed uniform number after
456 * remove_dead_constants() that represents the actual uploaded
462 struct hash_table
*variable_ht
;
465 fs_reg outputs
[BRW_MAX_DRAW_BUFFERS
];
466 unsigned output_components
[BRW_MAX_DRAW_BUFFERS
];
467 fs_reg dual_src_output
;
468 int first_non_payload_grf
;
469 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
472 fs_reg
*fp_temp_regs
;
473 fs_reg
*fp_input_regs
;
475 /** @{ debug annotation info */
476 const char *current_annotation
;
483 /* Result of last visit() method. */
490 fs_reg delta_x
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
491 fs_reg delta_y
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
492 fs_reg shader_start_time
;
495 bool spilled_any_registers
;
497 const unsigned dispatch_width
; /**< 8 or 16 */
499 int force_uncompressed_stack
;
503 * The fragment shader code generator.
505 * Translates FS IR to actual i965 assembly code.
510 fs_generator(struct brw_context
*brw
,
511 struct brw_wm_compile
*c
,
512 struct gl_shader_program
*prog
,
513 struct gl_fragment_program
*fp
,
514 bool dual_source_output
);
517 const unsigned *generate_assembly(exec_list
*simd8_instructions
,
518 exec_list
*simd16_instructions
,
519 unsigned *assembly_size
);
522 void generate_code(exec_list
*instructions
);
523 void generate_fb_write(fs_inst
*inst
);
524 void generate_pixel_xy(struct brw_reg dst
, bool is_x
);
525 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
526 struct brw_reg
*src
);
527 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
528 void generate_math1_gen7(fs_inst
*inst
,
531 void generate_math2_gen7(fs_inst
*inst
,
534 struct brw_reg src1
);
535 void generate_math1_gen6(fs_inst
*inst
,
538 void generate_math2_gen6(fs_inst
*inst
,
541 struct brw_reg src1
);
542 void generate_math_gen4(fs_inst
*inst
,
545 void generate_math_g45(fs_inst
*inst
,
548 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
549 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
551 void generate_scratch_write(fs_inst
*inst
, struct brw_reg src
);
552 void generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
);
553 void generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
);
554 void generate_uniform_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
,
555 struct brw_reg index
,
556 struct brw_reg offset
);
557 void generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
559 struct brw_reg surf_index
,
560 struct brw_reg offset
);
561 void generate_varying_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
,
562 struct brw_reg index
,
563 struct brw_reg offset
);
564 void generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
566 struct brw_reg index
,
567 struct brw_reg offset
);
568 void generate_mov_dispatch_to_flags(fs_inst
*inst
);
570 void generate_set_omask(fs_inst
*inst
,
572 struct brw_reg sample_mask
);
574 void generate_set_sample_id(fs_inst
*inst
,
577 struct brw_reg src1
);
579 void generate_set_simd4x2_offset(fs_inst
*inst
,
581 struct brw_reg offset
);
582 void generate_discard_jump(fs_inst
*inst
);
584 void generate_pack_half_2x16_split(fs_inst
*inst
,
588 void generate_unpack_half_2x16_split(fs_inst
*inst
,
592 void generate_shader_time_add(fs_inst
*inst
,
593 struct brw_reg payload
,
594 struct brw_reg offset
,
595 struct brw_reg value
);
597 void generate_untyped_atomic(fs_inst
*inst
,
599 struct brw_reg atomic_op
,
600 struct brw_reg surf_index
);
602 void generate_untyped_surface_read(fs_inst
*inst
,
604 struct brw_reg surf_index
);
606 void mark_surface_used(unsigned surf_index
);
608 void patch_discard_jumps_to_fb_writes();
610 struct brw_context
*brw
;
611 struct gl_context
*ctx
;
613 struct brw_compile
*p
;
614 struct brw_wm_compile
*c
;
616 struct gl_shader_program
*prog
;
617 struct gl_shader
*shader
;
618 const struct gl_fragment_program
*fp
;
620 unsigned dispatch_width
; /**< 8 or 16 */
622 exec_list discard_halt_patches
;
623 bool dual_source_output
;
628 * The fragment shader code generator.
630 * Translates FS IR to actual i965 assembly code.
632 class gen8_fs_generator
: public gen8_generator
635 gen8_fs_generator(struct brw_context
*brw
,
636 struct brw_wm_compile
*c
,
637 struct gl_shader_program
*prog
,
638 struct gl_fragment_program
*fp
,
639 bool dual_source_output
);
640 ~gen8_fs_generator();
642 const unsigned *generate_assembly(exec_list
*simd8_instructions
,
643 exec_list
*simd16_instructions
,
644 unsigned *assembly_size
);
647 void generate_code(exec_list
*instructions
);
648 void generate_fb_write(fs_inst
*inst
);
649 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
650 struct brw_reg
*src
);
651 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
652 void generate_math1(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
653 void generate_math2(fs_inst
*inst
, struct brw_reg dst
,
654 struct brw_reg src0
, struct brw_reg src1
);
655 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
656 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
658 void generate_scratch_write(fs_inst
*inst
, struct brw_reg src
);
659 void generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
);
660 void generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
);
661 void generate_uniform_pull_constant_load(fs_inst
*inst
,
663 struct brw_reg index
,
664 struct brw_reg offset
);
665 void generate_varying_pull_constant_load(fs_inst
*inst
,
667 struct brw_reg index
,
668 struct brw_reg offset
);
669 void generate_mov_dispatch_to_flags(fs_inst
*ir
);
670 void generate_set_simd4x2_offset(fs_inst
*ir
,
672 struct brw_reg offset
);
673 void generate_discard_jump(fs_inst
*ir
);
675 void patch_discard_jumps_to_fb_writes();
677 void mark_surface_used(unsigned surf_index
);
679 struct brw_wm_compile
*c
;
680 const struct gl_fragment_program
*fp
;
682 unsigned dispatch_width
; /** 8 or 16 */
684 bool dual_source_output
;
686 exec_list discard_halt_patches
;
689 bool brw_do_channel_expressions(struct exec_list
*instructions
);
690 bool brw_do_vector_splitting(struct exec_list
*instructions
);
691 bool brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
);
693 struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
);