2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include "brw_shader.h"
34 #include <sys/types.h>
36 #include "main/macros.h"
37 #include "main/shaderobj.h"
38 #include "main/uniforms.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/prog_optimize.h"
42 #include "program/register_allocate.h"
43 #include "program/sampler.h"
44 #include "program/hash_table.h"
45 #include "brw_context.h"
48 #include "brw_shader.h"
50 #include "gen8_generator.h"
51 #include "glsl/glsl_types.h"
54 #define MAX_SAMPLER_MESSAGE_SIZE 11
62 class fs_live_variables
;
67 DECLARE_RALLOC_CXX_OPERATORS(fs_reg
)
75 fs_reg(struct brw_reg fixed_hw_reg
);
76 fs_reg(enum register_file file
, int reg
);
77 fs_reg(enum register_file file
, int reg
, uint32_t type
);
78 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
80 bool equals(const fs_reg
&r
) const;
84 bool is_valid_3src() const;
85 bool is_contiguous() const;
86 fs_reg
retype(uint32_t type
);
87 fs_reg
&apply_stride(unsigned stride
);
89 /** Register file: GRF, MRF, IMM. */
90 enum register_file file
;
92 * Register number. For MRF, it's the hardware register. For
93 * GRF, it's a virtual register number until register allocation
97 * Offset from the start of the contiguous register block.
99 * For pre-register-allocation GRFs, this is in units of a float per pixel
100 * (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
101 * For uniforms, this is in units of 1 float.
104 /** Register type. BRW_REGISTER_TYPE_* */
108 struct brw_reg fixed_hw_reg
;
110 /** Smear a channel of the reg to all channels. */
111 fs_reg
&set_smear(unsigned subreg
);
113 /** Value for file == IMM */
121 * Offset in bytes from the start of the register. Values up to a
122 * backend_reg::reg_offset unit are valid.
126 /** Register region horizontal stride */
133 retype(fs_reg reg
, unsigned type
)
135 reg
.fixed_hw_reg
.type
= reg
.type
= type
;
140 offset(fs_reg reg
, unsigned delta
)
142 assert(delta
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
143 reg
.reg_offset
+= delta
;
148 byte_offset(fs_reg reg
, unsigned delta
)
150 assert(delta
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
151 reg
.subreg_offset
+= delta
;
156 * Get either of the 8-component halves of a 16-component register.
158 * Note: this also works if \c reg represents a SIMD16 pair of registers.
161 half(const fs_reg
®
, unsigned idx
)
164 assert(idx
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
165 return byte_offset(reg
, 8 * idx
* reg
.stride
* type_sz(reg
.type
));
168 static const fs_reg reg_undef
;
169 static const fs_reg
reg_null_f(retype(brw_null_reg(), BRW_REGISTER_TYPE_F
));
170 static const fs_reg
reg_null_d(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
171 static const fs_reg
reg_null_ud(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
173 class ip_record
: public exec_node
{
175 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
185 class fs_inst
: public backend_instruction
{
187 DECLARE_RALLOC_CXX_OPERATORS(fs_inst
)
192 fs_inst(enum opcode opcode
);
193 fs_inst(enum opcode opcode
, fs_reg dst
);
194 fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
);
195 fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
);
196 fs_inst(enum opcode opcode
, fs_reg dst
,
197 fs_reg src0
, fs_reg src1
,fs_reg src2
);
199 bool equals(fs_inst
*inst
);
200 bool overwrites_reg(const fs_reg
®
);
201 bool is_send_from_grf();
202 bool is_partial_write();
203 int regs_read(fs_visitor
*v
, int arg
);
211 int conditional_mod
; /**< BRW_CONDITIONAL_* */
213 /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
214 * mod and predication.
218 int mlen
; /**< SEND message length */
219 int regs_written
; /**< Number of vgrfs written by a SEND message, or 1 */
220 int base_mrf
; /**< First MRF in the SEND message, if mlen is nonzero. */
221 uint32_t texture_offset
; /**< Texture offset bitfield */
223 int target
; /**< MRT target. */
227 bool force_uncompressed
;
229 bool force_writemask_all
;
230 uint32_t offset
; /* spill/unspill offset */
233 * Annotation for the generated IR. One of the two can be set.
236 const char *annotation
;
241 * The fragment shader front-end.
243 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
245 class fs_visitor
: public backend_visitor
249 fs_visitor(struct brw_context
*brw
,
250 struct brw_wm_compile
*c
,
251 struct gl_shader_program
*shader_prog
,
252 struct gl_fragment_program
*fp
,
253 unsigned dispatch_width
);
256 fs_reg
*variable_storage(ir_variable
*var
);
257 int virtual_grf_alloc(int size
);
258 void import_uniforms(fs_visitor
*v
);
260 void visit(ir_variable
*ir
);
261 void visit(ir_assignment
*ir
);
262 void visit(ir_dereference_variable
*ir
);
263 void visit(ir_dereference_record
*ir
);
264 void visit(ir_dereference_array
*ir
);
265 void visit(ir_expression
*ir
);
266 void visit(ir_texture
*ir
);
267 void visit(ir_if
*ir
);
268 void visit(ir_constant
*ir
);
269 void visit(ir_swizzle
*ir
);
270 void visit(ir_return
*ir
);
271 void visit(ir_loop
*ir
);
272 void visit(ir_loop_jump
*ir
);
273 void visit(ir_discard
*ir
);
274 void visit(ir_call
*ir
);
275 void visit(ir_function
*ir
);
276 void visit(ir_function_signature
*ir
);
277 void visit(ir_emit_vertex
*);
278 void visit(ir_end_primitive
*);
280 uint32_t gather_channel(ir_texture
*ir
, int sampler
);
281 void swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
);
283 bool can_do_source_mods(fs_inst
*inst
);
285 fs_inst
*emit(fs_inst inst
);
286 fs_inst
*emit(fs_inst
*inst
);
287 void emit(exec_list list
);
289 fs_inst
*emit(enum opcode opcode
);
290 fs_inst
*emit(enum opcode opcode
, fs_reg dst
);
291 fs_inst
*emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
);
292 fs_inst
*emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
);
293 fs_inst
*emit(enum opcode opcode
, fs_reg dst
,
294 fs_reg src0
, fs_reg src1
, fs_reg src2
);
296 fs_inst
*MOV(fs_reg dst
, fs_reg src
);
297 fs_inst
*NOT(fs_reg dst
, fs_reg src
);
298 fs_inst
*RNDD(fs_reg dst
, fs_reg src
);
299 fs_inst
*RNDE(fs_reg dst
, fs_reg src
);
300 fs_inst
*RNDZ(fs_reg dst
, fs_reg src
);
301 fs_inst
*FRC(fs_reg dst
, fs_reg src
);
302 fs_inst
*ADD(fs_reg dst
, fs_reg src0
, fs_reg src1
);
303 fs_inst
*MUL(fs_reg dst
, fs_reg src0
, fs_reg src1
);
304 fs_inst
*MACH(fs_reg dst
, fs_reg src0
, fs_reg src1
);
305 fs_inst
*MAC(fs_reg dst
, fs_reg src0
, fs_reg src1
);
306 fs_inst
*SHL(fs_reg dst
, fs_reg src0
, fs_reg src1
);
307 fs_inst
*SHR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
308 fs_inst
*ASR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
309 fs_inst
*AND(fs_reg dst
, fs_reg src0
, fs_reg src1
);
310 fs_inst
*OR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
311 fs_inst
*XOR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
312 fs_inst
*IF(uint32_t predicate
);
313 fs_inst
*IF(fs_reg src0
, fs_reg src1
, uint32_t condition
);
314 fs_inst
*CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
,
316 fs_inst
*LRP(fs_reg dst
, fs_reg a
, fs_reg y
, fs_reg x
);
317 fs_inst
*DEP_RESOLVE_MOV(int grf
);
318 fs_inst
*BFREV(fs_reg dst
, fs_reg value
);
319 fs_inst
*BFE(fs_reg dst
, fs_reg bits
, fs_reg offset
, fs_reg value
);
320 fs_inst
*BFI1(fs_reg dst
, fs_reg bits
, fs_reg offset
);
321 fs_inst
*BFI2(fs_reg dst
, fs_reg bfi1_dst
, fs_reg insert
, fs_reg base
);
322 fs_inst
*FBH(fs_reg dst
, fs_reg value
);
323 fs_inst
*FBL(fs_reg dst
, fs_reg value
);
324 fs_inst
*CBIT(fs_reg dst
, fs_reg value
);
325 fs_inst
*MAD(fs_reg dst
, fs_reg c
, fs_reg b
, fs_reg a
);
326 fs_inst
*ADDC(fs_reg dst
, fs_reg src0
, fs_reg src1
);
327 fs_inst
*SUBB(fs_reg dst
, fs_reg src0
, fs_reg src1
);
328 fs_inst
*SEL(fs_reg dst
, fs_reg src0
, fs_reg src1
);
330 int type_size(const struct glsl_type
*type
);
331 fs_inst
*get_instruction_generating_reg(fs_inst
*start
,
335 exec_list
VARYING_PULL_CONSTANT_LOAD(fs_reg dst
, fs_reg surf_index
,
336 fs_reg varying_offset
,
337 uint32_t const_offset
);
340 void assign_binding_table_offsets();
341 void setup_payload_gen4();
342 void setup_payload_gen6();
343 void assign_curb_setup();
344 void calculate_urb_setup();
345 void assign_urb_setup();
346 bool assign_regs(bool allow_spilling
);
347 void assign_regs_trivial();
348 void get_used_mrfs(bool *mrf_used
);
349 void setup_payload_interference(struct ra_graph
*g
, int payload_reg_count
,
350 int first_payload_node
);
351 void setup_mrf_hack_interference(struct ra_graph
*g
,
352 int first_mrf_hack_node
);
353 int choose_spill_reg(struct ra_graph
*g
);
354 void spill_reg(int spill_reg
);
355 void split_virtual_grfs();
356 void compact_virtual_grfs();
357 void move_uniform_array_access_to_pull_constants();
358 void setup_pull_constants();
359 void invalidate_live_intervals();
360 void calculate_live_intervals();
361 void calculate_register_pressure();
362 bool opt_algebraic();
364 bool opt_cse_local(bblock_t
*block
, exec_list
*aeb
);
365 bool opt_copy_propagate();
366 bool try_copy_propagate(fs_inst
*inst
, int arg
, acp_entry
*entry
);
367 bool try_constant_propagate(fs_inst
*inst
, acp_entry
*entry
);
368 bool opt_copy_propagate_local(void *mem_ctx
, bblock_t
*block
,
370 bool register_coalesce();
371 bool compute_to_mrf();
372 bool dead_code_eliminate();
373 bool dead_code_eliminate_local();
374 bool remove_dead_constants();
375 bool remove_duplicate_mrf_writes();
376 bool virtual_grf_interferes(int a
, int b
);
377 void schedule_instructions(instruction_scheduler_mode mode
);
378 void insert_gen4_send_dependency_workarounds();
379 void insert_gen4_pre_send_dependency_workarounds(fs_inst
*inst
);
380 void insert_gen4_post_send_dependency_workarounds(fs_inst
*inst
);
381 void fail(const char *msg
, ...);
382 void lower_uniform_pull_constant_loads();
384 void push_force_uncompressed();
385 void pop_force_uncompressed();
387 void emit_dummy_fs();
388 fs_reg
*emit_fragcoord_interpolation(ir_variable
*ir
);
389 fs_inst
*emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
390 glsl_interp_qualifier interpolation_mode
,
391 bool is_centroid
, bool is_sample
);
392 fs_reg
*emit_frontfacing_interpolation(ir_variable
*ir
);
393 fs_reg
*emit_samplepos_setup(ir_variable
*ir
);
394 fs_reg
*emit_sampleid_setup(ir_variable
*ir
);
395 fs_reg
*emit_samplemaskin_setup(ir_variable
*ir
);
396 fs_reg
*emit_general_interpolation(ir_variable
*ir
);
397 void emit_interpolation_setup_gen4();
398 void emit_interpolation_setup_gen6();
399 void compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
);
400 fs_reg
rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
401 bool is_rect
, int sampler
, int texunit
);
402 fs_inst
*emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
403 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
);
404 fs_inst
*emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
405 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
,
406 fs_reg sample_index
);
407 fs_inst
*emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
408 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
,
409 fs_reg sample_index
, fs_reg mcs
, int sampler
);
410 fs_reg
emit_mcs_fetch(ir_texture
*ir
, fs_reg coordinate
, int sampler
);
411 void emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
);
412 fs_reg
fix_math_operand(fs_reg src
);
413 fs_inst
*emit_math(enum opcode op
, fs_reg dst
, fs_reg src0
);
414 fs_inst
*emit_math(enum opcode op
, fs_reg dst
, fs_reg src0
, fs_reg src1
);
415 void emit_lrp(fs_reg dst
, fs_reg x
, fs_reg y
, fs_reg a
);
416 void emit_minmax(uint32_t conditionalmod
, fs_reg dst
,
417 fs_reg src0
, fs_reg src1
);
418 bool try_emit_saturate(ir_expression
*ir
);
419 bool try_emit_mad(ir_expression
*ir
, int mul_arg
);
420 void try_replace_with_sel();
421 bool opt_peephole_sel();
422 bool opt_peephole_predicated_break();
423 bool opt_saturate_propagation();
424 void emit_bool_to_cond_code(ir_rvalue
*condition
);
425 void emit_if_gen6(ir_if
*ir
);
426 void emit_unspill(fs_inst
*inst
, fs_reg reg
, uint32_t spill_offset
,
429 void emit_fragment_program_code();
430 void setup_fp_regs();
431 fs_reg
get_fp_src_reg(const prog_src_register
*src
);
432 fs_reg
get_fp_dst_reg(const prog_dst_register
*dst
);
433 void emit_fp_alu1(enum opcode opcode
,
434 const struct prog_instruction
*fpi
,
435 fs_reg dst
, fs_reg src
);
436 void emit_fp_alu2(enum opcode opcode
,
437 const struct prog_instruction
*fpi
,
438 fs_reg dst
, fs_reg src0
, fs_reg src1
);
439 void emit_fp_scalar_write(const struct prog_instruction
*fpi
,
440 fs_reg dst
, fs_reg src
);
441 void emit_fp_scalar_math(enum opcode opcode
,
442 const struct prog_instruction
*fpi
,
443 fs_reg dst
, fs_reg src
);
445 void emit_fp_minmax(const struct prog_instruction
*fpi
,
446 fs_reg dst
, fs_reg src0
, fs_reg src1
);
448 void emit_fp_sop(uint32_t conditional_mod
,
449 const struct prog_instruction
*fpi
,
450 fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg one
);
452 void emit_color_write(int target
, int index
, int first_color_mrf
);
453 void emit_alpha_test();
454 void emit_fb_writes();
456 void emit_shader_time_begin();
457 void emit_shader_time_end();
458 void emit_shader_time_write(enum shader_time_shader_type type
,
461 void emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
462 fs_reg dst
, fs_reg offset
, fs_reg src0
,
465 void emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
468 bool try_rewrite_rhs_to_dst(ir_assignment
*ir
,
471 fs_inst
*pre_rhs_inst
,
472 fs_inst
*last_rhs_inst
);
473 void emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
474 const glsl_type
*type
, bool predicated
);
475 void resolve_ud_negate(fs_reg
*reg
);
476 void resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
);
478 fs_reg
get_timestamp();
480 struct brw_reg
interp_reg(int location
, int channel
);
481 void setup_uniform_values(ir_variable
*ir
);
482 void setup_builtin_uniform_values(ir_variable
*ir
);
483 int implied_mrf_writes(fs_inst
*inst
);
485 virtual void dump_instructions();
486 void dump_instruction(backend_instruction
*inst
);
488 void visit_atomic_counter_intrinsic(ir_call
*ir
);
490 struct gl_fragment_program
*fp
;
491 struct brw_wm_compile
*c
;
492 unsigned int sanity_param_count
;
494 int param_size
[MAX_UNIFORMS
* 4];
496 int *virtual_grf_sizes
;
497 int virtual_grf_count
;
498 int virtual_grf_array_size
;
499 int *virtual_grf_start
;
500 int *virtual_grf_end
;
501 brw::fs_live_variables
*live_intervals
;
503 int *regs_live_at_ip
;
505 /* This is the map from UNIFORM hw_reg + reg_offset as generated by
506 * the visitor to the packed uniform number after
507 * remove_dead_constants() that represents the actual uploaded
513 struct hash_table
*variable_ht
;
516 fs_reg outputs
[BRW_MAX_DRAW_BUFFERS
];
517 unsigned output_components
[BRW_MAX_DRAW_BUFFERS
];
518 fs_reg dual_src_output
;
519 int first_non_payload_grf
;
520 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
523 fs_reg
*fp_temp_regs
;
524 fs_reg
*fp_input_regs
;
526 /** @{ debug annotation info */
527 const char *current_annotation
;
534 /* Result of last visit() method. */
541 fs_reg delta_x
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
542 fs_reg delta_y
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
543 fs_reg shader_start_time
;
546 bool spilled_any_registers
;
548 const unsigned dispatch_width
; /**< 8 or 16 */
550 int force_uncompressed_stack
;
554 * The fragment shader code generator.
556 * Translates FS IR to actual i965 assembly code.
561 fs_generator(struct brw_context
*brw
,
562 struct brw_wm_compile
*c
,
563 struct gl_shader_program
*prog
,
564 struct gl_fragment_program
*fp
,
565 bool dual_source_output
);
568 const unsigned *generate_assembly(exec_list
*simd8_instructions
,
569 exec_list
*simd16_instructions
,
570 unsigned *assembly_size
,
571 FILE *dump_file
= NULL
);
574 void generate_code(exec_list
*instructions
, FILE *dump_file
);
575 void generate_fb_write(fs_inst
*inst
);
576 void generate_blorp_fb_write(fs_inst
*inst
);
577 void generate_pixel_xy(struct brw_reg dst
, bool is_x
);
578 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
579 struct brw_reg
*src
);
580 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
581 void generate_math1_gen7(fs_inst
*inst
,
584 void generate_math2_gen7(fs_inst
*inst
,
587 struct brw_reg src1
);
588 void generate_math1_gen6(fs_inst
*inst
,
591 void generate_math2_gen6(fs_inst
*inst
,
594 struct brw_reg src1
);
595 void generate_math_gen4(fs_inst
*inst
,
598 void generate_math_g45(fs_inst
*inst
,
601 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
602 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
604 void generate_scratch_write(fs_inst
*inst
, struct brw_reg src
);
605 void generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
);
606 void generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
);
607 void generate_uniform_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
,
608 struct brw_reg index
,
609 struct brw_reg offset
);
610 void generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
612 struct brw_reg surf_index
,
613 struct brw_reg offset
);
614 void generate_varying_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
,
615 struct brw_reg index
,
616 struct brw_reg offset
);
617 void generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
619 struct brw_reg index
,
620 struct brw_reg offset
);
621 void generate_mov_dispatch_to_flags(fs_inst
*inst
);
623 void generate_set_omask(fs_inst
*inst
,
625 struct brw_reg sample_mask
);
627 void generate_set_sample_id(fs_inst
*inst
,
630 struct brw_reg src1
);
632 void generate_set_simd4x2_offset(fs_inst
*inst
,
634 struct brw_reg offset
);
635 void generate_discard_jump(fs_inst
*inst
);
637 void generate_pack_half_2x16_split(fs_inst
*inst
,
641 void generate_unpack_half_2x16_split(fs_inst
*inst
,
645 void generate_shader_time_add(fs_inst
*inst
,
646 struct brw_reg payload
,
647 struct brw_reg offset
,
648 struct brw_reg value
);
650 void generate_untyped_atomic(fs_inst
*inst
,
652 struct brw_reg atomic_op
,
653 struct brw_reg surf_index
);
655 void generate_untyped_surface_read(fs_inst
*inst
,
657 struct brw_reg surf_index
);
659 void patch_discard_jumps_to_fb_writes();
661 struct brw_context
*brw
;
662 struct gl_context
*ctx
;
664 struct brw_compile
*p
;
665 struct brw_wm_compile
*c
;
667 struct gl_shader_program
*prog
;
668 const struct gl_fragment_program
*fp
;
670 unsigned dispatch_width
; /**< 8 or 16 */
672 exec_list discard_halt_patches
;
673 bool dual_source_output
;
678 * The fragment shader code generator.
680 * Translates FS IR to actual i965 assembly code.
682 class gen8_fs_generator
: public gen8_generator
685 gen8_fs_generator(struct brw_context
*brw
,
686 struct brw_wm_compile
*c
,
687 struct gl_shader_program
*prog
,
688 struct gl_fragment_program
*fp
,
689 bool dual_source_output
);
690 ~gen8_fs_generator();
692 const unsigned *generate_assembly(exec_list
*simd8_instructions
,
693 exec_list
*simd16_instructions
,
694 unsigned *assembly_size
);
697 void generate_code(exec_list
*instructions
);
698 void generate_fb_write(fs_inst
*inst
);
699 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
700 struct brw_reg
*src
);
701 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
702 void generate_math1(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
703 void generate_math2(fs_inst
*inst
, struct brw_reg dst
,
704 struct brw_reg src0
, struct brw_reg src1
);
705 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
706 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
708 void generate_scratch_write(fs_inst
*inst
, struct brw_reg src
);
709 void generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
);
710 void generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
);
711 void generate_uniform_pull_constant_load(fs_inst
*inst
,
713 struct brw_reg index
,
714 struct brw_reg offset
);
715 void generate_varying_pull_constant_load(fs_inst
*inst
,
717 struct brw_reg index
,
718 struct brw_reg offset
);
719 void generate_mov_dispatch_to_flags(fs_inst
*ir
);
720 void generate_set_simd4x2_offset(fs_inst
*ir
,
722 struct brw_reg offset
);
723 void generate_discard_jump(fs_inst
*ir
);
725 void patch_discard_jumps_to_fb_writes();
727 void mark_surface_used(unsigned surf_index
);
729 struct brw_wm_compile
*c
;
730 const struct gl_fragment_program
*fp
;
732 unsigned dispatch_width
; /** 8 or 16 */
734 bool dual_source_output
;
736 exec_list discard_halt_patches
;
739 bool brw_do_channel_expressions(struct exec_list
*instructions
);
740 bool brw_do_vector_splitting(struct exec_list
*instructions
);
741 bool brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
);
743 struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
);