i965/nir: Sort uniforms direct-first and use two different uniform registers
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs.h
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #pragma once
29
30 #include "brw_shader.h"
31 #include "brw_ir_fs.h"
32
33 extern "C" {
34
35 #include <sys/types.h>
36
37 #include "main/macros.h"
38 #include "main/shaderobj.h"
39 #include "main/uniforms.h"
40 #include "program/prog_parameter.h"
41 #include "program/prog_print.h"
42 #include "program/prog_optimize.h"
43 #include "util/register_allocate.h"
44 #include "program/hash_table.h"
45 #include "brw_context.h"
46 #include "brw_eu.h"
47 #include "brw_wm.h"
48 #include "intel_asm_annotation.h"
49 }
50 #include "glsl/glsl_types.h"
51 #include "glsl/ir.h"
52 #include "glsl/nir/nir.h"
53 #include "program/sampler.h"
54
55 struct bblock_t;
56 namespace {
57 struct acp_entry;
58 }
59
60 namespace brw {
61 class fs_live_variables;
62 }
63
64 /**
65 * The fragment shader front-end.
66 *
67 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
68 */
69 class fs_visitor : public backend_visitor
70 {
71 public:
72 const fs_reg reg_null_f;
73 const fs_reg reg_null_d;
74 const fs_reg reg_null_ud;
75
76 fs_visitor(struct brw_context *brw,
77 void *mem_ctx,
78 const struct brw_wm_prog_key *key,
79 struct brw_wm_prog_data *prog_data,
80 struct gl_shader_program *shader_prog,
81 struct gl_fragment_program *fp,
82 unsigned dispatch_width);
83
84 fs_visitor(struct brw_context *brw,
85 void *mem_ctx,
86 const struct brw_vs_prog_key *key,
87 struct brw_vs_prog_data *prog_data,
88 struct gl_shader_program *shader_prog,
89 struct gl_vertex_program *cp,
90 unsigned dispatch_width);
91
92 ~fs_visitor();
93 void init();
94
95 fs_reg *variable_storage(ir_variable *var);
96 fs_reg vgrf(const glsl_type *const type);
97 fs_reg vgrf(int num_components);
98 void import_uniforms(fs_visitor *v);
99 void setup_uniform_clipplane_values();
100 void compute_clip_distance();
101
102 void visit(ir_variable *ir);
103 void visit(ir_assignment *ir);
104 void visit(ir_dereference_variable *ir);
105 void visit(ir_dereference_record *ir);
106 void visit(ir_dereference_array *ir);
107 void visit(ir_expression *ir);
108 void visit(ir_texture *ir);
109 void visit(ir_if *ir);
110 void visit(ir_constant *ir);
111 void visit(ir_swizzle *ir);
112 void visit(ir_return *ir);
113 void visit(ir_loop *ir);
114 void visit(ir_loop_jump *ir);
115 void visit(ir_discard *ir);
116 void visit(ir_call *ir);
117 void visit(ir_function *ir);
118 void visit(ir_function_signature *ir);
119 void visit(ir_emit_vertex *);
120 void visit(ir_end_primitive *);
121
122 uint32_t gather_channel(int orig_chan, uint32_t sampler);
123 void swizzle_result(ir_texture_opcode op, int dest_components,
124 fs_reg orig_val, uint32_t sampler);
125
126 fs_inst *emit(fs_inst *inst);
127 void emit(exec_list list);
128
129 fs_inst *emit(enum opcode opcode);
130 fs_inst *emit(enum opcode opcode, const fs_reg &dst);
131 fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
132 fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
133 const fs_reg &src1);
134 fs_inst *emit(enum opcode opcode, const fs_reg &dst,
135 const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
136 fs_inst *emit(enum opcode opcode, const fs_reg &dst,
137 fs_reg src[], int sources);
138
139 fs_inst *MOV(const fs_reg &dst, const fs_reg &src);
140 fs_inst *NOT(const fs_reg &dst, const fs_reg &src);
141 fs_inst *RNDD(const fs_reg &dst, const fs_reg &src);
142 fs_inst *RNDE(const fs_reg &dst, const fs_reg &src);
143 fs_inst *RNDZ(const fs_reg &dst, const fs_reg &src);
144 fs_inst *FRC(const fs_reg &dst, const fs_reg &src);
145 fs_inst *ADD(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
146 fs_inst *MUL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
147 fs_inst *MACH(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
148 fs_inst *MAC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
149 fs_inst *SHL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
150 fs_inst *SHR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
151 fs_inst *ASR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
152 fs_inst *AND(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
153 fs_inst *OR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
154 fs_inst *XOR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
155 fs_inst *IF(enum brw_predicate predicate);
156 fs_inst *IF(const fs_reg &src0, const fs_reg &src1,
157 enum brw_conditional_mod condition);
158 fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
159 enum brw_conditional_mod condition);
160 fs_inst *LRP(const fs_reg &dst, const fs_reg &a, const fs_reg &y,
161 const fs_reg &x);
162 fs_inst *DEP_RESOLVE_MOV(int grf);
163 fs_inst *BFREV(const fs_reg &dst, const fs_reg &value);
164 fs_inst *BFE(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset,
165 const fs_reg &value);
166 fs_inst *BFI1(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset);
167 fs_inst *BFI2(const fs_reg &dst, const fs_reg &bfi1_dst,
168 const fs_reg &insert, const fs_reg &base);
169 fs_inst *FBH(const fs_reg &dst, const fs_reg &value);
170 fs_inst *FBL(const fs_reg &dst, const fs_reg &value);
171 fs_inst *CBIT(const fs_reg &dst, const fs_reg &value);
172 fs_inst *MAD(const fs_reg &dst, const fs_reg &c, const fs_reg &b,
173 const fs_reg &a);
174 fs_inst *ADDC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
175 fs_inst *SUBB(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
176 fs_inst *SEL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
177
178 int type_size(const struct glsl_type *type);
179 fs_inst *get_instruction_generating_reg(fs_inst *start,
180 fs_inst *end,
181 const fs_reg &reg);
182
183 fs_inst *LOAD_PAYLOAD(const fs_reg &dst, fs_reg *src, int sources);
184
185 exec_list VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
186 const fs_reg &surf_index,
187 const fs_reg &varying_offset,
188 uint32_t const_offset);
189
190 bool run_fs();
191 bool run_vs();
192 void optimize();
193 void allocate_registers();
194 void assign_binding_table_offsets();
195 void setup_payload_gen4();
196 void setup_payload_gen6();
197 void setup_vs_payload();
198 void fixup_3src_null_dest();
199 void assign_curb_setup();
200 void calculate_urb_setup();
201 void assign_urb_setup();
202 void assign_vs_urb_setup();
203 bool assign_regs(bool allow_spilling);
204 void assign_regs_trivial();
205 void get_used_mrfs(bool *mrf_used);
206 void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
207 int first_payload_node);
208 void setup_mrf_hack_interference(struct ra_graph *g,
209 int first_mrf_hack_node);
210 int choose_spill_reg(struct ra_graph *g);
211 void spill_reg(int spill_reg);
212 void split_virtual_grfs();
213 bool compact_virtual_grfs();
214 void move_uniform_array_access_to_pull_constants();
215 void assign_constant_locations();
216 void demote_pull_constants();
217 void invalidate_live_intervals();
218 void calculate_live_intervals();
219 void calculate_register_pressure();
220 bool opt_algebraic();
221 bool opt_redundant_discard_jumps();
222 bool opt_cse();
223 bool opt_cse_local(bblock_t *block);
224 bool opt_copy_propagate();
225 bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
226 bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
227 bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
228 exec_list *acp);
229 bool opt_register_renaming();
230 bool register_coalesce();
231 bool compute_to_mrf();
232 bool dead_code_eliminate();
233 bool remove_duplicate_mrf_writes();
234 bool virtual_grf_interferes(int a, int b);
235 void schedule_instructions(instruction_scheduler_mode mode);
236 void insert_gen4_send_dependency_workarounds();
237 void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
238 fs_inst *inst);
239 void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
240 fs_inst *inst);
241 void vfail(const char *msg, va_list args);
242 void fail(const char *msg, ...);
243 void no16(const char *msg, ...);
244 void lower_uniform_pull_constant_loads();
245 bool lower_load_payload();
246 bool opt_combine_constants();
247
248 void emit_dummy_fs();
249 void emit_repclear_shader();
250 fs_reg *emit_fragcoord_interpolation(bool pixel_center_integer,
251 bool origin_upper_left);
252 fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
253 glsl_interp_qualifier interpolation_mode,
254 bool is_centroid, bool is_sample);
255 fs_reg *emit_frontfacing_interpolation();
256 fs_reg *emit_samplepos_setup();
257 fs_reg *emit_sampleid_setup();
258 void emit_general_interpolation(fs_reg attr, const char *name,
259 const glsl_type *type,
260 glsl_interp_qualifier interpolation_mode,
261 int location, bool mod_centroid,
262 bool mod_sample);
263 fs_reg *emit_vs_system_value(int location);
264 void emit_interpolation_setup_gen4();
265 void emit_interpolation_setup_gen6();
266 void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
267 fs_reg rescale_texcoord(fs_reg coordinate, int coord_components,
268 bool is_rect, uint32_t sampler, int texunit);
269 fs_inst *emit_texture_gen4(ir_texture_opcode op, fs_reg dst,
270 fs_reg coordinate, int coord_components,
271 fs_reg shadow_comp,
272 fs_reg lod, fs_reg lod2, int grad_components,
273 uint32_t sampler);
274 fs_inst *emit_texture_gen5(ir_texture_opcode op, fs_reg dst,
275 fs_reg coordinate, int coord_components,
276 fs_reg shadow_comp,
277 fs_reg lod, fs_reg lod2, int grad_components,
278 fs_reg sample_index, uint32_t sampler,
279 bool has_offset);
280 fs_inst *emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
281 fs_reg coordinate, int coord_components,
282 fs_reg shadow_comp,
283 fs_reg lod, fs_reg lod2, int grad_components,
284 fs_reg sample_index, fs_reg mcs, fs_reg sampler,
285 fs_reg offset_value);
286 void emit_texture(ir_texture_opcode op,
287 const glsl_type *dest_type,
288 fs_reg coordinate, int components,
289 fs_reg shadow_c,
290 fs_reg lod, fs_reg dpdy, int grad_components,
291 fs_reg sample_index,
292 fs_reg offset,
293 fs_reg mcs,
294 int gather_component,
295 bool is_cube_array,
296 bool is_rect,
297 uint32_t sampler,
298 fs_reg sampler_reg,
299 int texunit);
300 fs_reg emit_mcs_fetch(fs_reg coordinate, int components, fs_reg sampler);
301 void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
302 void resolve_source_modifiers(fs_reg *src);
303 fs_reg fix_math_operand(fs_reg src);
304 fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
305 fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
306 void emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
307 const fs_reg &a);
308 void emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &dst,
309 const fs_reg &src0, const fs_reg &src1);
310 bool try_emit_b2f_of_comparison(ir_expression *ir);
311 bool try_emit_saturate(ir_expression *ir);
312 bool try_emit_line(ir_expression *ir);
313 bool try_emit_mad(ir_expression *ir);
314 bool try_replace_with_sel();
315 bool try_opt_frontfacing_ternary(ir_if *ir);
316 bool opt_peephole_sel();
317 bool opt_peephole_predicated_break();
318 bool opt_saturate_propagation();
319 bool opt_cmod_propagation();
320 void emit_bool_to_cond_code(ir_rvalue *condition);
321 void emit_bool_to_cond_code_of_reg(ir_expression *expr, fs_reg op[3]);
322 void emit_if_gen6(ir_if *ir);
323 void emit_unspill(bblock_t *block, fs_inst *inst, fs_reg reg,
324 uint32_t spill_offset, int count);
325 void emit_spill(bblock_t *block, fs_inst *inst, fs_reg reg,
326 uint32_t spill_offset, int count);
327
328 void emit_fragment_program_code();
329 void setup_fp_regs();
330 fs_reg get_fp_src_reg(const prog_src_register *src);
331 fs_reg get_fp_dst_reg(const prog_dst_register *dst);
332 void emit_fp_alu1(enum opcode opcode,
333 const struct prog_instruction *fpi,
334 fs_reg dst, fs_reg src);
335 void emit_fp_alu2(enum opcode opcode,
336 const struct prog_instruction *fpi,
337 fs_reg dst, fs_reg src0, fs_reg src1);
338 void emit_fp_scalar_write(const struct prog_instruction *fpi,
339 fs_reg dst, fs_reg src);
340 void emit_fp_scalar_math(enum opcode opcode,
341 const struct prog_instruction *fpi,
342 fs_reg dst, fs_reg src);
343
344 void emit_fp_minmax(const struct prog_instruction *fpi,
345 fs_reg dst, fs_reg src0, fs_reg src1);
346
347 void emit_fp_sop(enum brw_conditional_mod conditional_mod,
348 const struct prog_instruction *fpi,
349 fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
350
351 void emit_nir_code();
352 void nir_setup_inputs(nir_shader *shader);
353 void nir_setup_outputs(nir_shader *shader);
354 void nir_setup_uniforms(nir_shader *shader);
355 void nir_setup_uniform(nir_variable *var);
356 void nir_setup_builtin_uniform(nir_variable *var);
357 void nir_emit_system_values(nir_shader *shader);
358 void nir_emit_impl(nir_function_impl *impl);
359 void nir_emit_cf_list(exec_list *list);
360 void nir_emit_if(nir_if *if_stmt);
361 void nir_emit_loop(nir_loop *loop);
362 void nir_emit_block(nir_block *block);
363 void nir_emit_instr(nir_instr *instr);
364 void nir_emit_alu(nir_alu_instr *instr);
365 void nir_emit_intrinsic(nir_intrinsic_instr *instr);
366 void nir_emit_texture(nir_tex_instr *instr);
367 void nir_emit_jump(nir_jump_instr *instr);
368 fs_reg get_nir_src(nir_src src);
369 fs_reg get_nir_dest(nir_dest dest);
370 void emit_percomp(fs_inst *inst, unsigned wr_mask);
371
372 bool optimize_frontfacing_ternary(nir_alu_instr *instr,
373 const fs_reg &result);
374
375 int setup_color_payload(fs_reg *dst, fs_reg color, unsigned components,
376 bool use_2nd_half);
377 void emit_alpha_test();
378 fs_inst *emit_single_fb_write(fs_reg color1, fs_reg color2,
379 fs_reg src0_alpha, unsigned components,
380 bool use_2nd_half = false);
381 void emit_fb_writes();
382 void emit_urb_writes();
383
384 void emit_shader_time_begin();
385 void emit_shader_time_end();
386 fs_inst *SHADER_TIME_ADD(enum shader_time_shader_type type, fs_reg value);
387
388 void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
389 fs_reg dst, fs_reg offset, fs_reg src0,
390 fs_reg src1);
391
392 void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
393 fs_reg offset);
394
395 void emit_interpolate_expression(ir_expression *ir);
396
397 bool try_rewrite_rhs_to_dst(ir_assignment *ir,
398 fs_reg dst,
399 fs_reg src,
400 fs_inst *pre_rhs_inst,
401 fs_inst *last_rhs_inst);
402 void emit_assignment_writes(fs_reg &l, fs_reg &r,
403 const glsl_type *type, bool predicated);
404 void resolve_ud_negate(fs_reg *reg);
405 void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
406
407 fs_reg get_timestamp(fs_inst **out_mov);
408
409 struct brw_reg interp_reg(int location, int channel);
410 void setup_uniform_values(ir_variable *ir);
411 void setup_builtin_uniform_values(ir_variable *ir);
412 int implied_mrf_writes(fs_inst *inst);
413
414 virtual void dump_instructions();
415 virtual void dump_instructions(const char *name);
416 void dump_instruction(backend_instruction *inst);
417 void dump_instruction(backend_instruction *inst, FILE *file);
418
419 void visit_atomic_counter_intrinsic(ir_call *ir);
420
421 const void *const key;
422 const struct brw_sampler_prog_key_data *key_tex;
423
424 struct brw_stage_prog_data *prog_data;
425 unsigned int sanity_param_count;
426
427 int *param_size;
428
429 int *virtual_grf_start;
430 int *virtual_grf_end;
431 brw::fs_live_variables *live_intervals;
432
433 int *regs_live_at_ip;
434
435 /** Number of uniform variable components visited. */
436 unsigned uniforms;
437
438 /** Total number of direct uniforms we can get from NIR */
439 unsigned num_direct_uniforms;
440
441 /** Byte-offset for the next available spot in the scratch space buffer. */
442 unsigned last_scratch;
443
444 /**
445 * Array mapping UNIFORM register numbers to the pull parameter index,
446 * or -1 if this uniform register isn't being uploaded as a pull constant.
447 */
448 int *pull_constant_loc;
449
450 /**
451 * Array mapping UNIFORM register numbers to the push parameter index,
452 * or -1 if this uniform register isn't being uploaded as a push constant.
453 */
454 int *push_constant_loc;
455
456 struct hash_table *variable_ht;
457 fs_reg frag_depth;
458 fs_reg sample_mask;
459 fs_reg outputs[VARYING_SLOT_MAX];
460 unsigned output_components[VARYING_SLOT_MAX];
461 fs_reg dual_src_output;
462 bool do_dual_src;
463 int first_non_payload_grf;
464 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
465 unsigned max_grf;
466
467 fs_reg *fp_temp_regs;
468 fs_reg *fp_input_regs;
469
470 fs_reg *nir_locals;
471 fs_reg *nir_globals;
472 fs_reg nir_inputs;
473 fs_reg nir_outputs;
474 fs_reg *nir_system_values;
475
476 /** @{ debug annotation info */
477 const char *current_annotation;
478 const void *base_ir;
479 /** @} */
480
481 bool failed;
482 char *fail_msg;
483 bool simd16_unsupported;
484 char *no16_msg;
485
486 /* Result of last visit() method. */
487 fs_reg result;
488
489 /** Register numbers for thread payload fields. */
490 struct {
491 uint8_t source_depth_reg;
492 uint8_t source_w_reg;
493 uint8_t aa_dest_stencil_reg;
494 uint8_t dest_depth_reg;
495 uint8_t sample_pos_reg;
496 uint8_t sample_mask_in_reg;
497 uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
498
499 /** The number of thread payload registers the hardware will supply. */
500 uint8_t num_regs;
501 } payload;
502
503 bool source_depth_to_render_target;
504 bool runtime_check_aads_emit;
505
506 fs_reg pixel_x;
507 fs_reg pixel_y;
508 fs_reg wpos_w;
509 fs_reg pixel_w;
510 fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
511 fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
512 fs_reg shader_start_time;
513 fs_reg userplane[MAX_CLIP_PLANES];
514
515 unsigned grf_used;
516 bool spilled_any_registers;
517
518 const unsigned dispatch_width; /**< 8 or 16 */
519
520 unsigned promoted_constants;
521 };
522
523 /**
524 * The fragment shader code generator.
525 *
526 * Translates FS IR to actual i965 assembly code.
527 */
528 class fs_generator
529 {
530 public:
531 fs_generator(struct brw_context *brw,
532 void *mem_ctx,
533 const void *key,
534 struct brw_stage_prog_data *prog_data,
535 struct gl_program *fp,
536 unsigned promoted_constants,
537 bool runtime_check_aads_emit,
538 const char *stage_abbrev);
539 ~fs_generator();
540
541 void enable_debug(const char *shader_name);
542 int generate_code(const cfg_t *cfg, int dispatch_width);
543 const unsigned *get_assembly(unsigned int *assembly_size);
544
545 private:
546 void fire_fb_write(fs_inst *inst,
547 struct brw_reg payload,
548 struct brw_reg implied_header,
549 GLuint nr);
550 void generate_fb_write(fs_inst *inst, struct brw_reg payload);
551 void generate_urb_write(fs_inst *inst, struct brw_reg payload);
552 void generate_blorp_fb_write(fs_inst *inst);
553 void generate_pixel_xy(struct brw_reg dst, bool is_x);
554 void generate_linterp(fs_inst *inst, struct brw_reg dst,
555 struct brw_reg *src);
556 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
557 struct brw_reg sampler_index);
558 void generate_math_gen6(fs_inst *inst,
559 struct brw_reg dst,
560 struct brw_reg src0,
561 struct brw_reg src1);
562 void generate_math_gen4(fs_inst *inst,
563 struct brw_reg dst,
564 struct brw_reg src);
565 void generate_math_g45(fs_inst *inst,
566 struct brw_reg dst,
567 struct brw_reg src);
568 void generate_ddx(enum opcode op, struct brw_reg dst, struct brw_reg src);
569 void generate_ddy(enum opcode op, struct brw_reg dst, struct brw_reg src,
570 bool negate_value);
571 void generate_scratch_write(fs_inst *inst, struct brw_reg src);
572 void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
573 void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
574 void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
575 struct brw_reg index,
576 struct brw_reg offset);
577 void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
578 struct brw_reg dst,
579 struct brw_reg surf_index,
580 struct brw_reg offset);
581 void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
582 struct brw_reg index,
583 struct brw_reg offset);
584 void generate_varying_pull_constant_load_gen7(fs_inst *inst,
585 struct brw_reg dst,
586 struct brw_reg index,
587 struct brw_reg offset);
588 void generate_mov_dispatch_to_flags(fs_inst *inst);
589
590 void generate_pixel_interpolator_query(fs_inst *inst,
591 struct brw_reg dst,
592 struct brw_reg src,
593 struct brw_reg msg_data,
594 unsigned msg_type);
595
596 void generate_set_omask(fs_inst *inst,
597 struct brw_reg dst,
598 struct brw_reg sample_mask);
599
600 void generate_set_sample_id(fs_inst *inst,
601 struct brw_reg dst,
602 struct brw_reg src0,
603 struct brw_reg src1);
604
605 void generate_set_simd4x2_offset(fs_inst *inst,
606 struct brw_reg dst,
607 struct brw_reg offset);
608 void generate_discard_jump(fs_inst *inst);
609
610 void generate_pack_half_2x16_split(fs_inst *inst,
611 struct brw_reg dst,
612 struct brw_reg x,
613 struct brw_reg y);
614 void generate_unpack_half_2x16_split(fs_inst *inst,
615 struct brw_reg dst,
616 struct brw_reg src);
617
618 void generate_shader_time_add(fs_inst *inst,
619 struct brw_reg payload,
620 struct brw_reg offset,
621 struct brw_reg value);
622
623 void generate_untyped_atomic(fs_inst *inst,
624 struct brw_reg dst,
625 struct brw_reg payload,
626 struct brw_reg atomic_op,
627 struct brw_reg surf_index);
628
629 void generate_untyped_surface_read(fs_inst *inst,
630 struct brw_reg dst,
631 struct brw_reg payload,
632 struct brw_reg surf_index);
633
634 bool patch_discard_jumps_to_fb_writes();
635
636 struct brw_context *brw;
637 struct gl_context *ctx;
638
639 struct brw_compile *p;
640 const void * const key;
641 struct brw_stage_prog_data * const prog_data;
642
643 const struct gl_program *prog;
644
645 unsigned dispatch_width; /**< 8 or 16 */
646
647 exec_list discard_halt_patches;
648 unsigned promoted_constants;
649 bool runtime_check_aads_emit;
650 bool debug_flag;
651 const char *shader_name;
652 const char *stage_abbrev;
653 void *mem_ctx;
654 };
655
656 bool brw_do_channel_expressions(struct exec_list *instructions);
657 bool brw_do_vector_splitting(struct exec_list *instructions);