src/mesa/drivers/dri/i965/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29
  30 #include "brw_shader.h"
  31
  32 extern "C" {
  33
  34 #include <sys/types.h>
  35
  36 #include "main/macros.h"
  37 #include "main/shaderobj.h"
  38 #include "main/uniforms.h"
  39 #include "program/prog_parameter.h"
  40 #include "program/prog_print.h"
  41 #include "program/prog_optimize.h"
  42 #include "program/register_allocate.h"
  43 #include "program/sampler.h"
  44 #include "program/hash_table.h"
  45 #include "brw_context.h"
  46 #include "brw_eu.h"
  47 #include "brw_wm.h"
  48 #include "brw_shader.h"
  49 }
  50 #include "glsl/glsl_types.h"
  51 #include "glsl/ir.h"
  52
  53 class bblock_t;
  54 namespace {
  55    struct acp_entry;
  56 }
  57
  58 class fs_reg {
  59 public:
  60    /* Callers of this ralloc-based new need not call delete. It's
  61     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
  62    static void* operator new(size_t size, void *ctx)
  63    {
  64       void *node;
  65
  66       node = ralloc_size(ctx, size);
  67       assert(node != NULL);
  68
  69       return node;
  70    }
  71
  72    void init();
  73
  74    fs_reg();
  75    fs_reg(float f);
  76    fs_reg(int32_t i);
  77    fs_reg(uint32_t u);
  78    fs_reg(struct brw_reg fixed_hw_reg);
  79    fs_reg(enum register_file file, int reg);
  80    fs_reg(enum register_file file, int reg, uint32_t type);
  81    fs_reg(class fs_visitor *v, const struct glsl_type *type);
  82
  83    bool equals(const fs_reg &r) const;
  84    bool is_zero() const;
  85    bool is_one() const;
  86    bool is_valid_3src() const;
  87
  88    /** Register file: ARF, GRF, MRF, IMM. */
  89    enum register_file file;
  90    /**
  91     * Register number.  For ARF/MRF, it's the hardware register.  For
  92     * GRF, it's a virtual register number until register allocation
  93     */
  94    int reg;
  95    /**
  96     * For virtual registers, this is a hardware register offset from
  97     * the start of the register block (for example, a constant index
  98     * in an array access).
  99     */
 100    int reg_offset;
 101    /** Register type.  BRW_REGISTER_TYPE_* */
 102    int type;
 103    bool negate;
 104    bool abs;
 105    bool sechalf;
 106    struct brw_reg fixed_hw_reg;
 107    int smear; /* -1, or a channel of the reg to smear to all channels. */
 108
 109    /** Value for file == IMM */
 110    union {
 111       int32_t i;
 112       uint32_t u;
 113       float f;
 114    } imm;
 115
 116    fs_reg *reladdr;
 117 };
 118
 119 static const fs_reg reg_undef;
 120 static const fs_reg reg_null_f(ARF, BRW_ARF_NULL, BRW_REGISTER_TYPE_F);
 121 static const fs_reg reg_null_d(ARF, BRW_ARF_NULL, BRW_REGISTER_TYPE_D);
 122
 123 class ip_record : public exec_node {
 124 public:
 125    static void* operator new(size_t size, void *ctx)
 126    {
 127       void *node;
 128
 129       node = rzalloc_size(ctx, size);
 130       assert(node != NULL);
 131
 132       return node;
 133    }
 134
 135    ip_record(int ip)
 136    {
 137       this->ip = ip;
 138    }
 139
 140    int ip;
 141 };
 142
 143 class fs_inst : public backend_instruction {
 144 public:
 145    /* Callers of this ralloc-based new need not call delete. It's
 146     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 147    static void* operator new(size_t size, void *ctx)
 148    {
 149       void *node;
 150
 151       node = rzalloc_size(ctx, size);
 152       assert(node != NULL);
 153
 154       return node;
 155    }
 156
 157    void init();
 158
 159    fs_inst();
 160    fs_inst(enum opcode opcode);
 161    fs_inst(enum opcode opcode, fs_reg dst);
 162    fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0);
 163    fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
 164    fs_inst(enum opcode opcode, fs_reg dst,
 165            fs_reg src0, fs_reg src1,fs_reg src2);
 166
 167    bool equals(fs_inst *inst);
 168    bool overwrites_reg(const fs_reg &reg);
 169    bool is_send_from_grf();
 170    bool is_partial_write();
 171
 172    fs_reg dst;
 173    fs_reg src[3];
 174    bool saturate;
 175    int conditional_mod; /**< BRW_CONDITIONAL_* */
 176
 177    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 178     * mod and predication.
 179     */
 180    uint8_t flag_subreg;
 181
 182    int mlen; /**< SEND message length */
 183    int regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
 184    int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 185    uint32_t texture_offset; /**< Texture offset bitfield */
 186    int sampler;
 187    int target; /**< MRT target. */
 188    bool eot;
 189    bool header_present;
 190    bool shadow_compare;
 191    bool force_uncompressed;
 192    bool force_sechalf;
 193    bool force_writemask_all;
 194    uint32_t offset; /* spill/unspill offset */
 195
 196    /** @{
 197     * Annotation for the generated IR.  One of the two can be set.
 198     */
 199    const void *ir;
 200    const char *annotation;
 201    /** @} */
 202 };
 203
 204 /**
 205  * The fragment shader front-end.
 206  *
 207  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
 208  */
 209 class fs_visitor : public backend_visitor
 210 {
 211 public:
 212
 213    fs_visitor(struct brw_context *brw,
 214               struct brw_wm_compile *c,
 215               struct gl_shader_program *shader_prog,
 216               struct gl_fragment_program *fp,
 217               unsigned dispatch_width);
 218    ~fs_visitor();
 219
 220    fs_reg *variable_storage(ir_variable *var);
 221    int virtual_grf_alloc(int size);
 222    void import_uniforms(fs_visitor *v);
 223
 224    void visit(ir_variable *ir);
 225    void visit(ir_assignment *ir);
 226    void visit(ir_dereference_variable *ir);
 227    void visit(ir_dereference_record *ir);
 228    void visit(ir_dereference_array *ir);
 229    void visit(ir_expression *ir);
 230    void visit(ir_texture *ir);
 231    void visit(ir_if *ir);
 232    void visit(ir_constant *ir);
 233    void visit(ir_swizzle *ir);
 234    void visit(ir_return *ir);
 235    void visit(ir_loop *ir);
 236    void visit(ir_loop_jump *ir);
 237    void visit(ir_discard *ir);
 238    void visit(ir_call *ir);
 239    void visit(ir_function *ir);
 240    void visit(ir_function_signature *ir);
 241    void visit(ir_emit_vertex *);
 242    void visit(ir_end_primitive *);
 243
 244    void swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler);
 245
 246    bool can_do_source_mods(fs_inst *inst);
 247
 248    fs_inst *emit(fs_inst inst);
 249    fs_inst *emit(fs_inst *inst);
 250    void emit(exec_list list);
 251
 252    fs_inst *emit(enum opcode opcode);
 253    fs_inst *emit(enum opcode opcode, fs_reg dst);
 254    fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0);
 255    fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
 256    fs_inst *emit(enum opcode opcode, fs_reg dst,
 257                  fs_reg src0, fs_reg src1, fs_reg src2);
 258
 259    fs_inst *MOV(fs_reg dst, fs_reg src);
 260    fs_inst *NOT(fs_reg dst, fs_reg src);
 261    fs_inst *RNDD(fs_reg dst, fs_reg src);
 262    fs_inst *RNDE(fs_reg dst, fs_reg src);
 263    fs_inst *RNDZ(fs_reg dst, fs_reg src);
 264    fs_inst *FRC(fs_reg dst, fs_reg src);
 265    fs_inst *ADD(fs_reg dst, fs_reg src0, fs_reg src1);
 266    fs_inst *MUL(fs_reg dst, fs_reg src0, fs_reg src1);
 267    fs_inst *MACH(fs_reg dst, fs_reg src0, fs_reg src1);
 268    fs_inst *MAC(fs_reg dst, fs_reg src0, fs_reg src1);
 269    fs_inst *SHL(fs_reg dst, fs_reg src0, fs_reg src1);
 270    fs_inst *SHR(fs_reg dst, fs_reg src0, fs_reg src1);
 271    fs_inst *ASR(fs_reg dst, fs_reg src0, fs_reg src1);
 272    fs_inst *AND(fs_reg dst, fs_reg src0, fs_reg src1);
 273    fs_inst *OR(fs_reg dst, fs_reg src0, fs_reg src1);
 274    fs_inst *XOR(fs_reg dst, fs_reg src0, fs_reg src1);
 275    fs_inst *IF(uint32_t predicate);
 276    fs_inst *IF(fs_reg src0, fs_reg src1, uint32_t condition);
 277    fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
 278                 uint32_t condition);
 279    fs_inst *LRP(fs_reg dst, fs_reg a, fs_reg y, fs_reg x);
 280    fs_inst *DEP_RESOLVE_MOV(int grf);
 281    fs_inst *BFREV(fs_reg dst, fs_reg value);
 282    fs_inst *BFE(fs_reg dst, fs_reg bits, fs_reg offset, fs_reg value);
 283    fs_inst *BFI1(fs_reg dst, fs_reg bits, fs_reg offset);
 284    fs_inst *BFI2(fs_reg dst, fs_reg bfi1_dst, fs_reg insert, fs_reg base);
 285    fs_inst *FBH(fs_reg dst, fs_reg value);
 286    fs_inst *FBL(fs_reg dst, fs_reg value);
 287    fs_inst *CBIT(fs_reg dst, fs_reg value);
 288    fs_inst *MAD(fs_reg dst, fs_reg c, fs_reg b, fs_reg a);
 289
 290    int type_size(const struct glsl_type *type);
 291    fs_inst *get_instruction_generating_reg(fs_inst *start,
 292                                            fs_inst *end,
 293                                            fs_reg reg);
 294
 295    exec_list VARYING_PULL_CONSTANT_LOAD(fs_reg dst, fs_reg surf_index,
 296                                         fs_reg varying_offset,
 297                                         uint32_t const_offset);
 298
 299    bool run();
 300    void setup_payload_gen4();
 301    void setup_payload_gen6();
 302    void assign_curb_setup();
 303    void calculate_urb_setup();
 304    void assign_urb_setup();
 305    bool assign_regs();
 306    void assign_regs_trivial();
 307    void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
 308                                    int first_payload_node);
 309    void setup_mrf_hack_interference(struct ra_graph *g,
 310                                     int first_mrf_hack_node);
 311    int choose_spill_reg(struct ra_graph *g);
 312    void spill_reg(int spill_reg);
 313    void split_virtual_grfs();
 314    void compact_virtual_grfs();
 315    void move_uniform_array_access_to_pull_constants();
 316    void setup_pull_constants();
 317    void calculate_live_intervals();
 318    bool opt_algebraic();
 319    bool opt_cse();
 320    bool opt_cse_local(bblock_t *block, exec_list *aeb);
 321    bool opt_copy_propagate();
 322    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 323    bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
 324    bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
 325                                  exec_list *acp);
 326    bool register_coalesce();
 327    bool register_coalesce_2();
 328    bool compute_to_mrf();
 329    bool dead_code_eliminate();
 330    bool dead_code_eliminate_local();
 331    bool remove_dead_constants();
 332    bool remove_duplicate_mrf_writes();
 333    bool virtual_grf_interferes(int a, int b);
 334    void schedule_instructions(bool post_reg_alloc);
 335    void insert_gen4_send_dependency_workarounds();
 336    void insert_gen4_pre_send_dependency_workarounds(fs_inst *inst);
 337    void insert_gen4_post_send_dependency_workarounds(fs_inst *inst);
 338    void fail(const char *msg, ...);
 339    void lower_uniform_pull_constant_loads();
 340
 341    void push_force_uncompressed();
 342    void pop_force_uncompressed();
 343    void push_force_sechalf();
 344    void pop_force_sechalf();
 345
 346    void emit_dummy_fs();
 347    fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
 348    fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
 349                          glsl_interp_qualifier interpolation_mode,
 350                          bool is_centroid);
 351    fs_reg *emit_frontfacing_interpolation(ir_variable *ir);
 352    fs_reg *emit_general_interpolation(ir_variable *ir);
 353    void emit_interpolation_setup_gen4();
 354    void emit_interpolation_setup_gen6();
 355    fs_reg rescale_texcoord(ir_texture *ir, fs_reg coordinate,
 356                            bool is_rect, int sampler, int texunit);
 357    fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 358                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2);
 359    fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 360                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 361                               fs_reg sample_index);
 362    fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 363                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 364                               fs_reg sample_index);
 365    fs_reg fix_math_operand(fs_reg src);
 366    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
 367    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
 368    void emit_lrp(fs_reg dst, fs_reg x, fs_reg y, fs_reg a);
 369    void emit_minmax(uint32_t conditionalmod, fs_reg dst,
 370                     fs_reg src0, fs_reg src1);
 371    bool try_emit_saturate(ir_expression *ir);
 372    bool try_emit_mad(ir_expression *ir, int mul_arg);
 373    void try_replace_with_sel();
 374    void emit_bool_to_cond_code(ir_rvalue *condition);
 375    void emit_if_gen6(ir_if *ir);
 376    void emit_unspill(fs_inst *inst, fs_reg reg, uint32_t spill_offset);
 377
 378    void emit_fragment_program_code();
 379    void setup_fp_regs();
 380    fs_reg get_fp_src_reg(const prog_src_register *src);
 381    fs_reg get_fp_dst_reg(const prog_dst_register *dst);
 382    void emit_fp_alu1(enum opcode opcode,
 383                      const struct prog_instruction *fpi,
 384                      fs_reg dst, fs_reg src);
 385    void emit_fp_alu2(enum opcode opcode,
 386                      const struct prog_instruction *fpi,
 387                      fs_reg dst, fs_reg src0, fs_reg src1);
 388    void emit_fp_scalar_write(const struct prog_instruction *fpi,
 389                              fs_reg dst, fs_reg src);
 390    void emit_fp_scalar_math(enum opcode opcode,
 391                             const struct prog_instruction *fpi,
 392                             fs_reg dst, fs_reg src);
 393
 394    void emit_fp_minmax(const struct prog_instruction *fpi,
 395                        fs_reg dst, fs_reg src0, fs_reg src1);
 396
 397    void emit_fp_sop(uint32_t conditional_mod,
 398                     const struct prog_instruction *fpi,
 399                     fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
 400
 401    void emit_color_write(int target, int index, int first_color_mrf);
 402    void emit_fb_writes();
 403
 404    void emit_shader_time_begin();
 405    void emit_shader_time_end();
 406    void emit_shader_time_write(enum shader_time_shader_type type,
 407                                fs_reg value);
 408
 409    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 410                                fs_reg dst,
 411                                fs_reg src,
 412                                fs_inst *pre_rhs_inst,
 413                                fs_inst *last_rhs_inst);
 414    void emit_assignment_writes(fs_reg &l, fs_reg &r,
 415                                const glsl_type *type, bool predicated);
 416    void resolve_ud_negate(fs_reg *reg);
 417    void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
 418
 419    fs_reg get_timestamp();
 420
 421    struct brw_reg interp_reg(int location, int channel);
 422    void setup_uniform_values(ir_variable *ir);
 423    void setup_builtin_uniform_values(ir_variable *ir);
 424    int implied_mrf_writes(fs_inst *inst);
 425
 426    void dump_instruction(backend_instruction *inst);
 427
 428    struct gl_fragment_program *fp;
 429    struct brw_wm_compile *c;
 430    unsigned int sanity_param_count;
 431
 432    int param_size[MAX_UNIFORMS * 4];
 433
 434    int *virtual_grf_sizes;
 435    int virtual_grf_count;
 436    int virtual_grf_array_size;
 437    int *virtual_grf_start;
 438    int *virtual_grf_end;
 439    bool live_intervals_valid;
 440
 441    /* This is the map from UNIFORM hw_reg + reg_offset as generated by
 442     * the visitor to the packed uniform number after
 443     * remove_dead_constants() that represents the actual uploaded
 444     * uniform index.
 445     */
 446    int *params_remap;
 447    int nr_params_remap;
 448
 449    struct hash_table *variable_ht;
 450    fs_reg frag_depth;
 451    fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
 452    unsigned output_components[BRW_MAX_DRAW_BUFFERS];
 453    fs_reg dual_src_output;
 454    int first_non_payload_grf;
 455    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 456    int max_grf;
 457
 458    fs_reg *fp_temp_regs;
 459    fs_reg *fp_input_regs;
 460
 461    /** @{ debug annotation info */
 462    const char *current_annotation;
 463    const void *base_ir;
 464    /** @} */
 465
 466    bool failed;
 467    char *fail_msg;
 468
 469    /* Result of last visit() method. */
 470    fs_reg result;
 471
 472    fs_reg pixel_x;
 473    fs_reg pixel_y;
 474    fs_reg wpos_w;
 475    fs_reg pixel_w;
 476    fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 477    fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 478    fs_reg shader_start_time;
 479
 480    int grf_used;
 481
 482    const unsigned dispatch_width; /**< 8 or 16 */
 483
 484    int force_uncompressed_stack;
 485    int force_sechalf_stack;
 486 };
 487
 488 /**
 489  * The fragment shader code generator.
 490  *
 491  * Translates FS IR to actual i965 assembly code.
 492  */
 493 class fs_generator
 494 {
 495 public:
 496    fs_generator(struct brw_context *brw,
 497                 struct brw_wm_compile *c,
 498                 struct gl_shader_program *prog,
 499                 struct gl_fragment_program *fp,
 500                 bool dual_source_output);
 501    ~fs_generator();
 502
 503    const unsigned *generate_assembly(exec_list *simd8_instructions,
 504                                      exec_list *simd16_instructions,
 505                                      unsigned *assembly_size);
 506
 507 private:
 508    void generate_code(exec_list *instructions);
 509    void generate_fb_write(fs_inst *inst);
 510    void generate_pixel_xy(struct brw_reg dst, bool is_x);
 511    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 512                          struct brw_reg *src);
 513    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 514    void generate_math1_gen7(fs_inst *inst,
 515                             struct brw_reg dst,
 516                             struct brw_reg src);
 517    void generate_math2_gen7(fs_inst *inst,
 518                             struct brw_reg dst,
 519                             struct brw_reg src0,
 520                             struct brw_reg src1);
 521    void generate_math1_gen6(fs_inst *inst,
 522                             struct brw_reg dst,
 523                             struct brw_reg src);
 524    void generate_math2_gen6(fs_inst *inst,
 525                             struct brw_reg dst,
 526                             struct brw_reg src0,
 527                             struct brw_reg src1);
 528    void generate_math_gen4(fs_inst *inst,
 529                            struct brw_reg dst,
 530                            struct brw_reg src);
 531    void generate_math_g45(fs_inst *inst,
 532                           struct brw_reg dst,
 533                           struct brw_reg src);
 534    void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 535    void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 536                      bool negate_value);
 537    void generate_spill(fs_inst *inst, struct brw_reg src);
 538    void generate_unspill(fs_inst *inst, struct brw_reg dst);
 539    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 540                                             struct brw_reg index,
 541                                             struct brw_reg offset);
 542    void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
 543                                                  struct brw_reg dst,
 544                                                  struct brw_reg surf_index,
 545                                                  struct brw_reg offset);
 546    void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 547                                             struct brw_reg index,
 548                                             struct brw_reg offset);
 549    void generate_varying_pull_constant_load_gen7(fs_inst *inst,
 550                                                  struct brw_reg dst,
 551                                                  struct brw_reg index,
 552                                                  struct brw_reg offset);
 553    void generate_mov_dispatch_to_flags(fs_inst *inst);
 554    void generate_set_simd4x2_offset(fs_inst *inst,
 555                                     struct brw_reg dst,
 556                                     struct brw_reg offset);
 557    void generate_discard_jump(fs_inst *inst);
 558
 559    void generate_pack_half_2x16_split(fs_inst *inst,
 560                                       struct brw_reg dst,
 561                                       struct brw_reg x,
 562                                       struct brw_reg y);
 563    void generate_unpack_half_2x16_split(fs_inst *inst,
 564                                         struct brw_reg dst,
 565                                         struct brw_reg src);
 566
 567    void generate_shader_time_add(fs_inst *inst,
 568                                  struct brw_reg payload,
 569                                  struct brw_reg offset,
 570                                  struct brw_reg value);
 571
 572    void mark_surface_used(unsigned surf_index);
 573
 574    void patch_discard_jumps_to_fb_writes();
 575
 576    struct brw_context *brw;
 577    struct gl_context *ctx;
 578
 579    struct brw_compile *p;
 580    struct brw_wm_compile *c;
 581
 582    struct gl_shader_program *prog;
 583    struct gl_shader *shader;
 584    const struct gl_fragment_program *fp;
 585
 586    unsigned dispatch_width; /**< 8 or 16 */
 587
 588    exec_list discard_halt_patches;
 589    bool dual_source_output;
 590    void *mem_ctx;
 591 };
 592
 593 bool brw_do_channel_expressions(struct exec_list *instructions);
 594 bool brw_do_vector_splitting(struct exec_list *instructions);
 595 bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);